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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 00054 /* Add NutOS includes */ 00055 #include <cfg/arch.h> 00056 #include <cfg/clock.h> 00057 00058 #ifndef __STM32L1XX_H 00059 #define __STM32L1XX_H 00060 00061 #ifdef __cplusplus 00062 extern "C" { 00063 #endif 00064 00069 /* Uncomment the line below according to the target STM32L device used in your 00070 application 00071 */ 00072 00073 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) 00074 /* #define STM32L1XX_MD */ 00075 /* #define STM32L1XX_MDP */ 00076 #define STM32L1XX_HD 00077 #endif 00078 /* Tip: To avoid modifying this file each time you need to switch between these 00079 devices, you can define the device in your toolchain compiler preprocessor. 00080 00081 - Ultra Low Power Medium-density devices are STM32L151xx and STM32L152xx 00082 microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. 00083 - Ultra Low Power Medium-density Plus devices are STM32L151xx, STM32L152xx and 00084 STM32L162xx microcontrollers where the Flash memory density is 256 Kbytes. 00085 - Ultra Low Power High-density devices are STM32L151xx, STM32L152xx and STM32L162xx 00086 microcontrollers where the Flash memory density is 384 Kbytes. 00087 */ 00088 00089 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) 00090 #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)" 00091 #endif 00092 00093 #if !defined USE_STDPERIPH_DRIVER 00094 00099 /*#define USE_STDPERIPH_DRIVER*/ 00100 #endif 00101 00109 #if !defined (HSE_VALUE) 00110 #define HSE_VALUE ((uint32_t)8000000) 00111 #endif 00112 00117 #if !defined (HSE_STARTUP_TIMEOUT) 00118 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 00119 #endif 00120 00125 #if !defined (HSI_STARTUP_TIMEOUT) 00126 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) 00127 #endif 00128 00129 #if !defined (HSI_VALUE) 00130 #define HSI_VALUE ((uint32_t)16000000) 00133 #endif 00134 00135 #if !defined (LSI_VALUE) 00136 #define LSI_VALUE ((uint32_t)37000) 00139 #endif 00140 00141 #if !defined (LSE_VALUE) 00142 #define LSE_VALUE ((uint32_t)32768) 00143 #endif 00144 00148 #define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) 00149 #define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x01) 00150 #define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x01) 00151 #define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) 00152 #define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\ 00153 |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\ 00154 |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\ 00155 |(__STM32L1XX_STDPERIPH_VERSION_RC)) 00156 00169 #define __CM3_REV 0x200 00170 #define __MPU_PRESENT 1 00171 #define __NVIC_PRIO_BITS 4 00172 #define __Vendor_SysTickConfig 0 00175 typedef enum IRQn 00176 { 00177 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/ 00178 NonMaskableInt_IRQn = -14, 00179 MemoryManagement_IRQn = -12, 00180 BusFault_IRQn = -11, 00181 UsageFault_IRQn = -10, 00182 SVC_IRQn = -5, 00183 DebugMonitor_IRQn = -4, 00184 PendSV_IRQn = -2, 00185 SysTick_IRQn = -1, 00187 /****** STM32L specific Interrupt Numbers ***********************************************************/ 00188 WWDG_IRQn = 0, 00189 PVD_IRQn = 1, 00190 TAMPER_STAMP_IRQn = 2, 00191 RTC_WKUP_IRQn = 3, 00192 FLASH_IRQn = 4, 00193 RCC_IRQn = 5, 00194 EXTI0_IRQn = 6, 00195 EXTI1_IRQn = 7, 00196 EXTI2_IRQn = 8, 00197 EXTI3_IRQn = 9, 00198 EXTI4_IRQn = 10, 00199 DMA1_Channel1_IRQn = 11, 00200 DMA1_Channel2_IRQn = 12, 00201 DMA1_Channel3_IRQn = 13, 00202 DMA1_Channel4_IRQn = 14, 00203 DMA1_Channel5_IRQn = 15, 00204 DMA1_Channel6_IRQn = 16, 00205 DMA1_Channel7_IRQn = 17, 00206 ADC1_IRQn = 18, 00207 USB_HP_IRQn = 19, 00208 USB_LP_IRQn = 20, 00209 DAC_IRQn = 21, 00210 COMP_IRQn = 22, 00211 EXTI9_5_IRQn = 23, 00212 LCD_IRQn = 24, 00213 TIM9_IRQn = 25, 00214 TIM10_IRQn = 26, 00215 TIM11_IRQn = 27, 00216 TIM2_IRQn = 28, 00217 TIM3_IRQn = 29, 00218 TIM4_IRQn = 30, 00219 I2C1_EV_IRQn = 31, 00220 I2C1_ER_IRQn = 32, 00221 I2C2_EV_IRQn = 33, 00222 I2C2_ER_IRQn = 34, 00223 SPI1_IRQn = 35, 00224 SPI2_IRQn = 36, 00225 USART1_IRQn = 37, 00226 USART2_IRQn = 38, 00227 USART3_IRQn = 39, 00228 EXTI15_10_IRQn = 40, 00229 RTC_Alarm_IRQn = 41, 00230 USB_FS_WKUP_IRQn = 42, 00231 TIM6_IRQn = 43, 00232 #ifdef STM32L1XX_MD 00233 TIM7_IRQn = 44 00234 #endif 00235 00236 #ifdef STM32L1XX_MDP 00237 TIM7_IRQn = 44, 00238 TIM5_IRQn = 46, 00239 SPI3_IRQn = 47, 00240 DMA2_Channel1_IRQn = 50, 00241 DMA2_Channel2_IRQn = 51, 00242 DMA2_Channel3_IRQn = 52, 00243 DMA2_Channel4_IRQn = 53, 00244 DMA2_Channel5_IRQn = 54, 00245 AES_IRQn = 55, 00246 COMP_ACQ_IRQn = 56 00247 #endif 00248 00249 #ifdef STM32L1XX_HD 00250 TIM7_IRQn = 44, 00251 SDIO_IRQn = 45, 00252 TIM5_IRQn = 46, 00253 SPI3_IRQn = 47, 00254 UART4_IRQn = 48, 00255 UART5_IRQn = 49, 00256 DMA2_Channel1_IRQn = 50, 00257 DMA2_Channel2_IRQn = 51, 00258 DMA2_Channel3_IRQn = 52, 00259 DMA2_Channel4_IRQn = 53, 00260 DMA2_Channel5_IRQn = 54, 00261 AES_IRQn = 55, 00262 COMP_ACQ_IRQn = 56 00263 #endif 00264 } IRQn_Type; 00265 00270 #include <arch/cm3/core_cm3.h> 00271 #include <arch/cm3/stm/system_stm32f10x.h> 00272 #include <stdint.h> 00273 00278 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 00279 00280 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00281 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00282 00283 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00284 00288 #if defined ( __CC_ARM ) 00289 /* ARM Compiler 00290 ------------ 00291 RAM functions are defined using the toolchain options. 00292 Functions that are executed in RAM should reside in a separate source 00293 module. Using the 'Options for File' dialog you can simply change the 00294 'Code / Const' area of a module to a memory space in physical RAM. 00295 Available memory areas are declared in the 'Target' tab of the 00296 'Options for Target' dialog. 00297 */ 00298 #define __RAM_FUNC FLASH_Status 00299 00300 #elif defined ( __ICCARM__ ) 00301 /* ICCARM Compiler 00302 --------------- 00303 RAM functions are defined using a specific toolchain keyword "__ramfunc". 00304 */ 00305 #define __RAM_FUNC __ramfunc FLASH_Status 00306 00307 #elif defined ( __GNUC__ ) 00308 /* GNU Compiler 00309 ------------ 00310 RAM functions are defined using a specific toolchain attribute 00311 "__attribute__((section(".data")))". 00312 */ 00313 #define __RAM_FUNC FLASH_Status __attribute__((section(".data"))) 00314 00315 #elif defined ( __TASKING__ ) 00316 /* TASKING Compiler 00317 ---------------- 00318 RAM functions are defined using a specific toolchain pragma. This pragma is 00319 defined in the stm32l1xx_flash_ramfunc.c 00320 */ 00321 #define __RAM_FUNC FLASH_Status 00322 00323 #endif 00324 00337 typedef struct 00338 { 00339 __IO uint32_t SR; 00340 __IO uint32_t CR1; 00341 __IO uint32_t CR2; 00342 __IO uint32_t SMPR1; 00343 __IO uint32_t SMPR2; 00344 __IO uint32_t SMPR3; 00345 __IO uint32_t JOFR1; 00346 __IO uint32_t JOFR2; 00347 __IO uint32_t JOFR3; 00348 __IO uint32_t JOFR4; 00349 __IO uint32_t HTR; 00350 __IO uint32_t LTR; 00351 __IO uint32_t SQR1; 00352 __IO uint32_t SQR2; 00353 __IO uint32_t SQR3; 00354 __IO uint32_t SQR4; 00355 __IO uint32_t SQR5; 00356 __IO uint32_t JSQR; 00357 __IO uint32_t JDR1; 00358 __IO uint32_t JDR2; 00359 __IO uint32_t JDR3; 00360 __IO uint32_t JDR4; 00361 __IO uint32_t DR; 00362 __IO uint32_t SMPR0; 00363 } ADC_TypeDef; 00364 00365 typedef struct 00366 { 00367 __IO uint32_t CSR; 00368 __IO uint32_t CCR; 00369 } ADC_Common_TypeDef; 00370 00371 00376 typedef struct 00377 { 00378 __IO uint32_t CR; 00379 __IO uint32_t SR; 00380 __IO uint32_t DINR; 00381 __IO uint32_t DOUTR; 00382 __IO uint32_t KEYR0; 00383 __IO uint32_t KEYR1; 00384 __IO uint32_t KEYR2; 00385 __IO uint32_t KEYR3; 00386 __IO uint32_t IVR0; 00387 __IO uint32_t IVR1; 00388 __IO uint32_t IVR2; 00389 __IO uint32_t IVR3; 00390 } AES_TypeDef; 00391 00396 typedef struct 00397 { 00398 __IO uint32_t CSR; 00399 } COMP_TypeDef; 00400 00405 typedef struct 00406 { 00407 __IO uint32_t DR; 00408 __IO uint8_t IDR; 00409 uint8_t RESERVED0; 00410 uint16_t RESERVED1; 00411 __IO uint32_t CR; 00412 } CRC_TypeDef; 00413 00418 typedef struct 00419 { 00420 __IO uint32_t CR; 00421 __IO uint32_t SWTRIGR; 00422 __IO uint32_t DHR12R1; 00423 __IO uint32_t DHR12L1; 00424 __IO uint32_t DHR8R1; 00425 __IO uint32_t DHR12R2; 00426 __IO uint32_t DHR12L2; 00427 __IO uint32_t DHR8R2; 00428 __IO uint32_t DHR12RD; 00429 __IO uint32_t DHR12LD; 00430 __IO uint32_t DHR8RD; 00431 __IO uint32_t DOR1; 00432 __IO uint32_t DOR2; 00433 __IO uint32_t SR; 00434 } DAC_TypeDef; 00435 00440 typedef struct 00441 { 00442 __IO uint32_t IDCODE; 00443 __IO uint32_t CR; 00444 __IO uint32_t APB1FZ; 00445 __IO uint32_t APB2FZ; 00446 }DBGMCU_TypeDef; 00447 00452 typedef struct 00453 { 00454 __IO uint32_t CCR; 00455 __IO uint32_t CNDTR; 00456 __IO uint32_t CPAR; 00457 __IO uint32_t CMAR; 00458 } DMA_Channel_TypeDef; 00459 00460 typedef struct 00461 { 00462 __IO uint32_t ISR; 00463 __IO uint32_t IFCR; 00464 } DMA_TypeDef; 00465 00470 typedef struct 00471 { 00472 __IO uint32_t IMR; 00473 __IO uint32_t EMR; 00474 __IO uint32_t RTSR; 00475 __IO uint32_t FTSR; 00476 __IO uint32_t SWIER; 00477 __IO uint32_t PR; 00478 } EXTI_TypeDef; 00479 00484 typedef struct 00485 { 00486 __IO uint32_t ACR; 00487 __IO uint32_t PECR; 00488 __IO uint32_t PDKEYR; 00489 __IO uint32_t PEKEYR; 00490 __IO uint32_t PRGKEYR; 00491 __IO uint32_t OPTKEYR; 00492 __IO uint32_t SR; 00493 __IO uint32_t OBR; 00494 __IO uint32_t WRPR; 00495 uint32_t RESERVED[23]; 00496 __IO uint32_t WRPR1; 00497 __IO uint32_t WRPR2; 00498 } FLASH_TypeDef; 00499 00504 typedef struct 00505 { 00506 __IO uint32_t RDP; 00507 __IO uint32_t USER; 00508 __IO uint32_t WRP01; 00509 __IO uint32_t WRP23; 00510 __IO uint32_t WRP45; 00511 __IO uint32_t WRP67; 00512 __IO uint32_t WRP89; 00513 __IO uint32_t WRP1011; 00514 } OB_TypeDef; 00515 00520 typedef struct 00521 { 00522 __IO uint32_t CSR; 00523 __IO uint32_t OTR; 00524 __IO uint32_t LPOTR; 00525 } OPAMP_TypeDef; 00526 00531 typedef struct 00532 { 00533 __IO uint32_t BTCR[8]; 00534 } FSMC_Bank1_TypeDef; 00535 00540 typedef struct 00541 { 00542 __IO uint32_t BWTR[7]; 00543 } FSMC_Bank1E_TypeDef; 00544 00549 typedef struct 00550 { 00551 __IO uint32_t MODER; 00552 __IO uint16_t OTYPER; 00553 uint16_t RESERVED0; 00554 __IO uint32_t OSPEEDR; 00555 __IO uint32_t PUPDR; 00556 __IO uint16_t IDR; 00557 uint16_t RESERVED1; 00558 __IO uint16_t ODR; 00559 uint16_t RESERVED2; 00560 __IO uint16_t BSRRL; 00561 __IO uint16_t BSRRH; 00562 __IO uint32_t LCKR; 00563 __IO uint32_t AFR[2]; 00564 __IO uint16_t BRR; 00565 uint16_t RESERVED3; 00566 } GPIO_TypeDef; 00567 00572 typedef struct 00573 { 00574 __IO uint32_t MEMRMP; 00575 __IO uint32_t PMC; 00576 __IO uint32_t EXTICR[4]; 00577 } SYSCFG_TypeDef; 00578 00583 typedef struct 00584 { 00585 __IO uint16_t CR1; 00586 uint16_t RESERVED0; 00587 __IO uint16_t CR2; 00588 uint16_t RESERVED1; 00589 __IO uint16_t OAR1; 00590 uint16_t RESERVED2; 00591 __IO uint16_t OAR2; 00592 uint16_t RESERVED3; 00593 __IO uint16_t DR; 00594 uint16_t RESERVED4; 00595 __IO uint16_t SR1; 00596 uint16_t RESERVED5; 00597 __IO uint16_t SR2; 00598 uint16_t RESERVED6; 00599 __IO uint16_t CCR; 00600 uint16_t RESERVED7; 00601 __IO uint16_t TRISE; 00602 uint16_t RESERVED8; 00603 } I2C_TypeDef; 00604 00609 typedef struct 00610 { 00611 __IO uint32_t KR; 00612 __IO uint32_t PR; 00613 __IO uint32_t RLR; 00614 __IO uint32_t SR; 00615 } IWDG_TypeDef; 00616 00617 00622 typedef struct 00623 { 00624 __IO uint32_t CR; 00625 __IO uint32_t FCR; 00626 __IO uint32_t SR; 00627 __IO uint32_t CLR; 00628 uint32_t RESERVED; 00629 __IO uint32_t RAM[16]; 00630 } LCD_TypeDef; 00631 00636 typedef struct 00637 { 00638 __IO uint32_t CR; 00639 __IO uint32_t CSR; 00640 } PWR_TypeDef; 00641 00646 typedef struct 00647 { 00648 __IO uint32_t CR; 00649 __IO uint32_t ICSCR; 00650 __IO uint32_t CFGR; 00651 __IO uint32_t CIR; 00652 __IO uint32_t AHBRSTR; 00653 __IO uint32_t APB2RSTR; 00654 __IO uint32_t APB1RSTR; 00655 __IO uint32_t AHBENR; 00656 __IO uint32_t APB2ENR; 00657 __IO uint32_t APB1ENR; 00658 __IO uint32_t AHBLPENR; 00659 __IO uint32_t APB2LPENR; 00660 __IO uint32_t APB1LPENR; 00661 __IO uint32_t CSR; 00662 } RCC_TypeDef; 00663 00668 typedef struct 00669 { 00670 __IO uint32_t ICR; 00671 __IO uint32_t ASCR1; 00672 __IO uint32_t ASCR2; 00673 __IO uint32_t HYSCR1; 00674 __IO uint32_t HYSCR2; 00675 __IO uint32_t HYSCR3; 00676 __IO uint32_t HYSCR4; 00677 } RI_TypeDef; 00678 00683 typedef struct 00684 { 00685 __IO uint32_t TR; 00686 __IO uint32_t DR; 00687 __IO uint32_t CR; 00688 __IO uint32_t ISR; 00689 __IO uint32_t PRER; 00690 __IO uint32_t WUTR; 00691 __IO uint32_t CALIBR; 00692 __IO uint32_t ALRMAR; 00693 __IO uint32_t ALRMBR; 00694 __IO uint32_t WPR; 00695 __IO uint32_t SSR; 00696 __IO uint32_t SHIFTR; 00697 __IO uint32_t TSTR; 00698 __IO uint32_t TSDR; 00699 __IO uint32_t TSSSR; 00700 __IO uint32_t CALR; 00701 __IO uint32_t TAFCR; 00702 __IO uint32_t ALRMASSR; 00703 __IO uint32_t ALRMBSSR; 00704 uint32_t RESERVED7; 00705 __IO uint32_t BKP0R; 00706 __IO uint32_t BKP1R; 00707 __IO uint32_t BKP2R; 00708 __IO uint32_t BKP3R; 00709 __IO uint32_t BKP4R; 00710 __IO uint32_t BKP5R; 00711 __IO uint32_t BKP6R; 00712 __IO uint32_t BKP7R; 00713 __IO uint32_t BKP8R; 00714 __IO uint32_t BKP9R; 00715 __IO uint32_t BKP10R; 00716 __IO uint32_t BKP11R; 00717 __IO uint32_t BKP12R; 00718 __IO uint32_t BKP13R; 00719 __IO uint32_t BKP14R; 00720 __IO uint32_t BKP15R; 00721 __IO uint32_t BKP16R; 00722 __IO uint32_t BKP17R; 00723 __IO uint32_t BKP18R; 00724 __IO uint32_t BKP19R; 00725 __IO uint32_t BKP20R; 00726 __IO uint32_t BKP21R; 00727 __IO uint32_t BKP22R; 00728 __IO uint32_t BKP23R; 00729 __IO uint32_t BKP24R; 00730 __IO uint32_t BKP25R; 00731 __IO uint32_t BKP26R; 00732 __IO uint32_t BKP27R; 00733 __IO uint32_t BKP28R; 00734 __IO uint32_t BKP29R; 00735 __IO uint32_t BKP30R; 00736 __IO uint32_t BKP31R; 00737 } RTC_TypeDef; 00738 00743 typedef struct 00744 { 00745 __IO uint32_t POWER; 00746 __IO uint32_t CLKCR; 00747 __IO uint32_t ARG; 00748 __IO uint32_t CMD; 00749 __I uint32_t RESPCMD; 00750 __I uint32_t RESP1; 00751 __I uint32_t RESP2; 00752 __I uint32_t RESP3; 00753 __I uint32_t RESP4; 00754 __IO uint32_t DTIMER; 00755 __IO uint32_t DLEN; 00756 __IO uint32_t DCTRL; 00757 __I uint32_t DCOUNT; 00758 __I uint32_t STA; 00759 __IO uint32_t ICR; 00760 __IO uint32_t MASK; 00761 uint32_t RESERVED0[2]; 00762 __I uint32_t FIFOCNT; 00763 uint32_t RESERVED1[13]; 00764 __IO uint32_t FIFO; 00765 } SDIO_TypeDef; 00766 00771 typedef struct 00772 { 00773 __IO uint16_t CR1; 00774 uint16_t RESERVED0; 00775 __IO uint16_t CR2; 00776 uint16_t RESERVED1; 00777 __IO uint16_t SR; 00778 uint16_t RESERVED2; 00779 __IO uint16_t DR; 00780 uint16_t RESERVED3; 00781 __IO uint16_t CRCPR; 00782 uint16_t RESERVED4; 00783 __IO uint16_t RXCRCR; 00784 uint16_t RESERVED5; 00785 __IO uint16_t TXCRCR; 00786 uint16_t RESERVED6; 00787 __IO uint16_t I2SCFGR; 00788 uint16_t RESERVED7; 00789 __IO uint16_t I2SPR; 00790 uint16_t RESERVED8; 00791 } SPI_TypeDef; 00792 00797 typedef struct 00798 { 00799 __IO uint16_t CR1; 00800 uint16_t RESERVED0; 00801 __IO uint16_t CR2; 00802 uint16_t RESERVED1; 00803 __IO uint16_t SMCR; 00804 uint16_t RESERVED2; 00805 __IO uint16_t DIER; 00806 uint16_t RESERVED3; 00807 __IO uint16_t SR; 00808 uint16_t RESERVED4; 00809 __IO uint16_t EGR; 00810 uint16_t RESERVED5; 00811 __IO uint16_t CCMR1; 00812 uint16_t RESERVED6; 00813 __IO uint16_t CCMR2; 00814 uint16_t RESERVED7; 00815 __IO uint16_t CCER; 00816 uint16_t RESERVED8; 00817 __IO uint32_t CNT; 00818 __IO uint16_t PSC; 00819 uint16_t RESERVED10; 00820 __IO uint32_t ARR; 00821 uint32_t RESERVED12; 00822 __IO uint32_t CCR1; 00823 __IO uint32_t CCR2; 00824 __IO uint32_t CCR3; 00825 __IO uint32_t CCR4; 00826 uint32_t RESERVED17; 00827 __IO uint16_t DCR; 00828 uint16_t RESERVED18; 00829 __IO uint16_t DMAR; 00830 uint16_t RESERVED19; 00831 __IO uint16_t OR; 00832 uint16_t RESERVED20; 00833 } TIM_TypeDef; 00834 00839 typedef struct 00840 { 00841 __IO uint16_t SR; 00842 uint16_t RESERVED0; 00843 __IO uint16_t DR; 00844 uint16_t RESERVED1; 00845 __IO uint16_t BRR; 00846 uint16_t RESERVED2; 00847 __IO uint16_t CR1; 00848 uint16_t RESERVED3; 00849 __IO uint16_t CR2; 00850 uint16_t RESERVED4; 00851 __IO uint16_t CR3; 00852 uint16_t RESERVED5; 00853 __IO uint16_t GTPR; 00854 uint16_t RESERVED6; 00855 } USART_TypeDef; 00856 00861 typedef struct 00862 { 00863 __IO uint32_t CR; 00864 __IO uint32_t CFR; 00865 __IO uint32_t SR; 00866 } WWDG_TypeDef; 00867 00876 #define FLASH_BASE ((uint32_t)0x08000000) 00877 #define SRAM_BASE ((uint32_t)0x20000000) 00878 #define PERIPH_BASE ((uint32_t)0x40000000) 00880 #define SRAM_BB_BASE ((uint32_t)0x22000000) 00881 #define PERIPH_BB_BASE ((uint32_t)0x42000000) 00883 #define FSMC_R_BASE ((uint32_t)0xA0000000) 00886 #define APB1PERIPH_BASE PERIPH_BASE 00887 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 00888 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 00889 00890 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 00891 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 00892 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 00893 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 00894 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 00895 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 00896 #define LCD_BASE (APB1PERIPH_BASE + 0x2400) 00897 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 00898 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 00899 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 00900 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 00901 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 00902 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 00903 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 00904 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 00905 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 00906 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 00907 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 00908 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 00909 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 00910 #define COMP_BASE (APB1PERIPH_BASE + 0x7C00) 00911 #define RI_BASE (APB1PERIPH_BASE + 0x7C04) 00912 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) 00913 00914 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) 00915 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 00916 #define TIM9_BASE (APB2PERIPH_BASE + 0x0800) 00917 #define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) 00918 #define TIM11_BASE (APB2PERIPH_BASE + 0x1000) 00919 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 00920 #define ADC_BASE (APB2PERIPH_BASE + 0x2700) 00921 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) 00922 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 00923 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 00924 00925 #define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) 00926 #define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) 00927 #define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) 00928 #define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) 00929 #define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) 00930 #define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) 00931 #define GPIOF_BASE (AHBPERIPH_BASE + 0x1800) 00932 #define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) 00933 #define CRC_BASE (AHBPERIPH_BASE + 0x3000) 00934 #define RCC_BASE (AHBPERIPH_BASE + 0x3800) 00935 00936 00937 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) 00938 #define OB_BASE ((uint32_t)0x1FF80000) 00940 #define DMA1_BASE (AHBPERIPH_BASE + 0x6000) 00941 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) 00942 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) 00943 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) 00944 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) 00945 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) 00946 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) 00947 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) 00948 00949 #define DMA2_BASE (AHBPERIPH_BASE + 0x6400) 00950 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) 00951 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) 00952 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) 00953 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) 00954 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) 00955 00956 #define AES_BASE ((uint32_t)0x50060000) 00957 00958 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) 00959 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) 00961 #define DBGMCU_BASE ((uint32_t)0xE0042000) 00971 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 00972 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 00973 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 00974 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 00975 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 00976 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 00977 #define LCD ((LCD_TypeDef *) LCD_BASE) 00978 #define RTC ((RTC_TypeDef *) RTC_BASE) 00979 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 00980 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 00981 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 00982 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 00983 #define USART2 ((USART_TypeDef *) USART2_BASE) 00984 #define USART3 ((USART_TypeDef *) USART3_BASE) 00985 #define UART4 ((USART_TypeDef *) UART4_BASE) 00986 #define UART5 ((USART_TypeDef *) UART5_BASE) 00987 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 00988 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 00989 #define PWR ((PWR_TypeDef *) PWR_BASE) 00990 #define DAC ((DAC_TypeDef *) DAC_BASE) 00991 #define COMP ((COMP_TypeDef *) COMP_BASE) 00992 #define RI ((RI_TypeDef *) RI_BASE) 00993 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE) 00994 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 00995 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 00996 00997 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 00998 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) 00999 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 01000 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 01001 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 01002 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 01003 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01004 #define USART1 ((USART_TypeDef *) USART1_BASE) 01005 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01006 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 01007 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 01008 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 01009 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 01010 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 01011 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 01012 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 01013 01014 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01015 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 01016 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 01017 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 01018 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 01019 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 01020 01021 #define RCC ((RCC_TypeDef *) RCC_BASE) 01022 #define CRC ((CRC_TypeDef *) CRC_BASE) 01023 01024 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01025 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01026 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01027 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01028 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01029 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 01030 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01031 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01032 01033 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01034 #define OB ((OB_TypeDef *) OB_BASE) 01035 01036 #define AES ((AES_TypeDef *) AES_BASE) 01037 01038 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 01039 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 01040 01041 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01042 01055 /******************************************************************************/ 01056 /* Peripheral Registers Bits Definition */ 01057 /******************************************************************************/ 01058 /******************************************************************************/ 01059 /* */ 01060 /* Analog to Digital Converter (ADC) */ 01061 /* */ 01062 /******************************************************************************/ 01063 01064 /******************** Bit definition for ADC_SR register ********************/ 01065 #define ADC_SR_AWD ((uint32_t)0x00000001) 01066 #define ADC_SR_EOC ((uint32_t)0x00000002) 01067 #define ADC_SR_JEOC ((uint32_t)0x00000004) 01068 #define ADC_SR_JSTRT ((uint32_t)0x00000008) 01069 #define ADC_SR_STRT ((uint32_t)0x00000010) 01070 #define ADC_SR_OVR ((uint32_t)0x00000020) 01071 #define ADC_SR_ADONS ((uint32_t)0x00000040) 01072 #define ADC_SR_RCNR ((uint32_t)0x00000100) 01073 #define ADC_SR_JCNR ((uint32_t)0x00000200) 01075 /******************* Bit definition for ADC_CR1 register ********************/ 01076 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) 01077 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) 01078 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) 01079 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) 01080 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) 01081 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) 01083 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) 01084 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) 01085 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) 01086 #define ADC_CR1_SCAN ((uint32_t)0x00000100) 01087 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) 01088 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) 01089 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) 01090 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) 01092 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) 01093 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) 01094 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) 01095 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) 01097 #define ADC_CR1_PDD ((uint32_t)0x00010000) 01098 #define ADC_CR1_PDI ((uint32_t)0x00020000) 01100 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) 01101 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) 01103 #define ADC_CR1_RES ((uint32_t)0x03000000) 01104 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) 01105 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) 01107 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) 01109 /******************* Bit definition for ADC_CR2 register ********************/ 01110 #define ADC_CR2_ADON ((uint32_t)0x00000001) 01111 #define ADC_CR2_CONT ((uint32_t)0x00000002) 01112 #define ADC_CR2_CFG ((uint32_t)0x00000004) 01114 #define ADC_CR2_DELS ((uint32_t)0x00000070) 01115 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) 01116 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) 01117 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) 01119 #define ADC_CR2_DMA ((uint32_t)0x00000100) 01120 #define ADC_CR2_DDS ((uint32_t)0x00000200) 01121 #define ADC_CR2_EOCS ((uint32_t)0x00000400) 01122 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) 01124 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) 01125 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) 01126 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) 01127 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) 01128 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) 01130 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) 01131 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) 01132 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) 01134 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) 01136 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) 01137 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) 01138 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) 01139 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) 01140 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) 01142 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) 01143 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) 01144 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) 01146 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) 01148 /****************** Bit definition for ADC_SMPR1 register *******************/ 01149 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) 01150 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) 01151 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) 01152 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) 01154 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) 01155 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) 01156 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) 01157 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) 01159 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) 01160 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) 01161 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) 01162 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) 01164 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) 01165 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) 01166 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) 01167 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) 01169 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) 01170 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) 01171 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) 01172 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) 01174 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) 01175 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) 01176 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) 01177 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) 01179 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) 01180 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) 01181 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) 01182 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) 01184 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) 01185 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) 01186 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) 01187 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) 01189 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) 01190 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) 01191 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) 01192 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) 01194 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) 01195 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) 01196 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) 01197 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) 01199 /****************** Bit definition for ADC_SMPR2 register *******************/ 01200 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) 01201 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) 01202 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) 01203 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) 01205 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) 01206 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) 01207 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) 01208 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) 01210 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) 01211 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) 01212 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) 01213 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) 01215 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) 01216 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) 01217 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) 01218 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) 01220 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) 01221 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) 01222 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) 01223 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) 01225 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) 01226 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) 01227 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) 01228 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) 01230 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) 01231 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) 01232 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) 01233 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) 01235 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) 01236 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) 01237 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) 01238 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) 01240 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) 01241 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) 01242 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) 01243 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) 01245 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) 01246 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) 01247 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) 01248 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) 01250 /****************** Bit definition for ADC_SMPR3 register *******************/ 01251 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) 01252 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) 01253 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) 01254 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) 01256 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) 01257 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) 01258 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) 01259 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) 01261 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) 01262 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) 01263 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) 01264 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) 01266 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) 01267 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) 01268 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) 01269 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) 01271 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) 01272 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) 01273 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) 01274 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) 01276 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) 01277 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) 01278 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) 01279 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) 01281 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) 01282 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) 01283 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) 01284 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) 01286 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) 01287 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) 01288 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) 01289 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) 01291 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) 01292 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) 01293 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) 01294 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) 01296 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) 01297 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) 01298 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) 01299 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) 01301 /****************** Bit definition for ADC_JOFR1 register *******************/ 01302 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) 01304 /****************** Bit definition for ADC_JOFR2 register *******************/ 01305 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) 01307 /****************** Bit definition for ADC_JOFR3 register *******************/ 01308 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) 01310 /****************** Bit definition for ADC_JOFR4 register *******************/ 01311 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) 01313 /******************* Bit definition for ADC_HTR register ********************/ 01314 #define ADC_HTR_HT ((uint32_t)0x00000FFF) 01316 /******************* Bit definition for ADC_LTR register ********************/ 01317 #define ADC_LTR_LT ((uint32_t)0x00000FFF) 01319 /******************* Bit definition for ADC_SQR1 register *******************/ 01320 #define ADC_SQR1_L ((uint32_t)0x00F00000) 01321 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) 01322 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) 01323 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) 01324 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) 01326 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) 01327 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) 01328 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) 01329 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) 01330 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) 01331 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) 01333 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) 01334 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) 01335 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) 01336 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) 01337 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) 01338 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) 01340 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) 01341 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) 01342 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) 01343 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) 01344 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) 01345 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) 01347 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) 01348 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) 01349 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) 01350 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) 01351 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) 01352 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) 01354 /******************* Bit definition for ADC_SQR2 register *******************/ 01355 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) 01356 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) 01357 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) 01358 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) 01359 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) 01360 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) 01362 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) 01363 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) 01364 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) 01365 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) 01366 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) 01367 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) 01369 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) 01370 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) 01371 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) 01372 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) 01373 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) 01374 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) 01376 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) 01377 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) 01378 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) 01379 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) 01380 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) 01381 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) 01383 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) 01384 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) 01385 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) 01386 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) 01387 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) 01388 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) 01390 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) 01391 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) 01392 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) 01393 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) 01394 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) 01395 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) 01397 /******************* Bit definition for ADC_SQR3 register *******************/ 01398 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) 01399 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) 01400 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) 01401 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) 01402 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) 01403 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) 01405 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) 01406 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) 01407 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) 01408 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) 01409 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) 01410 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) 01412 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) 01413 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) 01414 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) 01415 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) 01416 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) 01417 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) 01419 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) 01420 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) 01421 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) 01422 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) 01423 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) 01424 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) 01426 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) 01427 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) 01428 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) 01429 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) 01430 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) 01431 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) 01433 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) 01434 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) 01435 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) 01436 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) 01437 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) 01438 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) 01440 /******************* Bit definition for ADC_SQR4 register *******************/ 01441 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) 01442 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) 01443 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) 01444 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) 01445 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) 01446 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) 01448 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) 01449 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) 01450 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) 01451 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) 01452 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) 01453 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) 01455 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) 01456 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) 01457 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) 01458 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) 01459 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) 01460 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) 01462 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) 01463 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) 01464 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) 01465 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) 01466 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) 01467 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) 01469 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) 01470 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) 01471 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) 01472 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) 01473 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) 01474 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) 01476 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) 01477 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) 01478 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) 01479 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) 01480 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) 01481 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) 01483 /******************* Bit definition for ADC_SQR5 register *******************/ 01484 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) 01485 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) 01486 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) 01487 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) 01488 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) 01489 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) 01491 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) 01492 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) 01493 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) 01494 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) 01495 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) 01496 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) 01498 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) 01499 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) 01500 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) 01501 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) 01502 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) 01503 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) 01505 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) 01506 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) 01507 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) 01508 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) 01509 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) 01510 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) 01512 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) 01513 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) 01514 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) 01515 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) 01516 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) 01517 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) 01519 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) 01520 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) 01521 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) 01522 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) 01523 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) 01524 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) 01527 /******************* Bit definition for ADC_JSQR register *******************/ 01528 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) 01529 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) 01530 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) 01531 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) 01532 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) 01533 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) 01535 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) 01536 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) 01537 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) 01538 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) 01539 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) 01540 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) 01542 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) 01543 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) 01544 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) 01545 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) 01546 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) 01547 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) 01549 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) 01550 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) 01551 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) 01552 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) 01553 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) 01554 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) 01556 #define ADC_JSQR_JL ((uint32_t)0x00300000) 01557 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) 01558 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) 01560 /******************* Bit definition for ADC_JDR1 register *******************/ 01561 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) 01563 /******************* Bit definition for ADC_JDR2 register *******************/ 01564 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) 01566 /******************* Bit definition for ADC_JDR3 register *******************/ 01567 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) 01569 /******************* Bit definition for ADC_JDR4 register *******************/ 01570 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) 01572 /******************** Bit definition for ADC_DR register ********************/ 01573 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) 01575 /****************** Bit definition for ADC_SMPR0 register *******************/ 01576 #define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) 01577 #define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) 01578 #define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) 01579 #define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) 01581 #define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) 01582 #define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) 01583 #define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) 01584 #define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) 01586 /******************* Bit definition for ADC_CSR register ********************/ 01587 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) 01588 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) 01589 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) 01590 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) 01591 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) 01592 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) 01593 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) 01595 /******************* Bit definition for ADC_CCR register ********************/ 01596 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) 01597 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) 01598 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) 01599 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) 01601 /******************************************************************************/ 01602 /* */ 01603 /* Advanced Encryption Standard (AES) */ 01604 /* */ 01605 /******************************************************************************/ 01606 /******************* Bit definition for AES_CR register *********************/ 01607 #define AES_CR_EN ((uint32_t)0x00000001) 01608 #define AES_CR_DATATYPE ((uint32_t)0x00000006) 01609 #define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) 01610 #define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) 01612 #define AES_CR_MODE ((uint32_t)0x00000018) 01613 #define AES_CR_MODE_0 ((uint32_t)0x00000008) 01614 #define AES_CR_MODE_1 ((uint32_t)0x00000010) 01616 #define AES_CR_CHMOD ((uint32_t)0x00000060) 01617 #define AES_CR_CHMOD_0 ((uint32_t)0x00000020) 01618 #define AES_CR_CHMOD_1 ((uint32_t)0x00000040) 01620 #define AES_CR_CCFC ((uint32_t)0x00000080) 01621 #define AES_CR_ERRC ((uint32_t)0x00000100) 01622 #define AES_CR_CCIE ((uint32_t)0x00000200) 01623 #define AES_CR_ERRIE ((uint32_t)0x00000400) 01624 #define AES_CR_DMAINEN ((uint32_t)0x00000800) 01625 #define AES_CR_DMAOUTEN ((uint32_t)0x00001000) 01627 /******************* Bit definition for AES_SR register *********************/ 01628 #define AES_SR_CCF ((uint32_t)0x00000001) 01629 #define AES_SR_RDERR ((uint32_t)0x00000002) 01630 #define AES_SR_WRERR ((uint32_t)0x00000004) 01632 /******************* Bit definition for AES_DINR register *******************/ 01633 #define AES_DINR ((uint32_t)0x0000FFFF) 01635 /******************* Bit definition for AES_DOUTR register ******************/ 01636 #define AES_DOUTR ((uint32_t)0x0000FFFF) 01638 /******************* Bit definition for AES_KEYR0 register ******************/ 01639 #define AES_KEYR0 ((uint32_t)0x0000FFFF) 01641 /******************* Bit definition for AES_KEYR1 register ******************/ 01642 #define AES_KEYR1 ((uint32_t)0x0000FFFF) 01644 /******************* Bit definition for AES_KEYR2 register ******************/ 01645 #define AES_KEYR2 ((uint32_t)0x0000FFFF) 01647 /******************* Bit definition for AES_KEYR3 register ******************/ 01648 #define AES_KEYR3 ((uint32_t)0x0000FFFF) 01650 /******************* Bit definition for AES_IVR0 register *******************/ 01651 #define AES_IVR0 ((uint32_t)0x0000FFFF) 01653 /******************* Bit definition for AES_IVR1 register *******************/ 01654 #define AES_IVR1 ((uint32_t)0x0000FFFF) 01656 /******************* Bit definition for AES_IVR2 register *******************/ 01657 #define AES_IVR2 ((uint32_t)0x0000FFFF) 01659 /******************* Bit definition for AES_IVR3 register *******************/ 01660 #define AES_IVR3 ((uint32_t)0x0000FFFF) 01662 /******************************************************************************/ 01663 /* */ 01664 /* Analog Comparators (COMP) */ 01665 /* */ 01666 /******************************************************************************/ 01667 01668 /****************** Bit definition for COMP_CSR register ********************/ 01669 #define COMP_CSR_10KPU ((uint32_t)0x00000001) 01670 #define COMP_CSR_400KPU ((uint32_t)0x00000002) 01671 #define COMP_CSR_10KPD ((uint32_t)0x00000004) 01672 #define COMP_CSR_400KPD ((uint32_t)0x00000008) 01674 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) 01675 #define COMP_CSR_SW1 ((uint32_t)0x00000020) 01676 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) 01678 #define COMP_CSR_SPEED ((uint32_t)0x00001000) 01679 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) 01681 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) 01682 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) 01684 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) 01685 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) 01686 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) 01687 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) 01689 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) 01690 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) 01691 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) 01692 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) 01694 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) 01695 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) 01696 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) 01698 #define COMP_CSR_CAIE ((uint32_t)0x20000000) 01699 #define COMP_CSR_CAIF ((uint32_t)0x40000000) 01700 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) 01702 /******************************************************************************/ 01703 /* */ 01704 /* Operational Amplifier (OPAMP) */ 01705 /* */ 01706 /******************************************************************************/ 01707 /******************* Bit definition for OPAMP_CSR register ******************/ 01708 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) 01709 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) 01710 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) 01711 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) 01712 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) 01713 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) 01714 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) 01715 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) 01716 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) 01717 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) 01718 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) 01719 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) 01720 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) 01721 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) 01722 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) 01723 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) 01724 #define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) 01725 #define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) 01726 #define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) 01727 #define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) 01728 #define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) 01729 #define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) 01730 #define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) 01731 #define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) 01732 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) 01733 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) 01734 #define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) 01735 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) 01736 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) 01737 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) 01738 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) 01739 #define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) 01741 /******************* Bit definition for OPAMP_OTR register ******************/ 01742 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) 01743 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) 01744 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) 01745 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) 01747 /******************* Bit definition for OPAMP_LPOTR register ****************/ 01748 #define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) 01749 #define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) 01750 #define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) 01752 /******************************************************************************/ 01753 /* */ 01754 /* CRC calculation unit (CRC) */ 01755 /* */ 01756 /******************************************************************************/ 01757 01758 /******************* Bit definition for CRC_DR register *********************/ 01759 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) 01761 /******************* Bit definition for CRC_IDR register ********************/ 01762 #define CRC_IDR_IDR ((uint8_t)0xFF) 01764 /******************** Bit definition for CRC_CR register ********************/ 01765 #define CRC_CR_RESET ((uint32_t)0x00000001) 01767 /******************************************************************************/ 01768 /* */ 01769 /* Digital to Analog Converter (DAC) */ 01770 /* */ 01771 /******************************************************************************/ 01772 01773 /******************** Bit definition for DAC_CR register ********************/ 01774 #define DAC_CR_EN1 ((uint32_t)0x00000001) 01775 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) 01776 #define DAC_CR_TEN1 ((uint32_t)0x00000004) 01778 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) 01779 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) 01780 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) 01781 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) 01783 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) 01784 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) 01785 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) 01787 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) 01788 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) 01789 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) 01790 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) 01791 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) 01793 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) 01794 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) 01795 #define DAC_CR_EN2 ((uint32_t)0x00010000) 01796 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) 01797 #define DAC_CR_TEN2 ((uint32_t)0x00040000) 01799 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) 01800 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) 01801 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) 01802 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) 01804 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) 01805 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) 01806 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) 01808 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) 01809 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) 01810 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) 01811 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) 01812 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) 01814 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) 01815 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) 01816 /***************** Bit definition for DAC_SWTRIGR register ******************/ 01817 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) 01818 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) 01820 /***************** Bit definition for DAC_DHR12R1 register ******************/ 01821 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) 01823 /***************** Bit definition for DAC_DHR12L1 register ******************/ 01824 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) 01826 /****************** Bit definition for DAC_DHR8R1 register ******************/ 01827 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) 01829 /***************** Bit definition for DAC_DHR12R2 register ******************/ 01830 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) 01832 /***************** Bit definition for DAC_DHR12L2 register ******************/ 01833 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) 01835 /****************** Bit definition for DAC_DHR8R2 register ******************/ 01836 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) 01838 /***************** Bit definition for DAC_DHR12RD register ******************/ 01839 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) 01840 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) 01842 /***************** Bit definition for DAC_DHR12LD register ******************/ 01843 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) 01844 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) 01846 /****************** Bit definition for DAC_DHR8RD register ******************/ 01847 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) 01848 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) 01850 /******************* Bit definition for DAC_DOR1 register *******************/ 01851 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) 01853 /******************* Bit definition for DAC_DOR2 register *******************/ 01854 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) 01856 /******************** Bit definition for DAC_SR register ********************/ 01857 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) 01858 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) 01860 /******************************************************************************/ 01861 /* */ 01862 /* Debug MCU (DBGMCU) */ 01863 /* */ 01864 /******************************************************************************/ 01865 01866 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 01867 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 01869 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 01870 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) 01871 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) 01872 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) 01873 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) 01874 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) 01875 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) 01876 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) 01877 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) 01878 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) 01879 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) 01880 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) 01881 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) 01882 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) 01883 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) 01884 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) 01885 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) 01887 /****************** Bit definition for DBGMCU_CR register *******************/ 01888 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 01889 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 01890 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 01891 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 01893 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 01894 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) 01895 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) 01897 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 01898 01899 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) 01900 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) 01901 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) 01902 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) 01903 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) 01904 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) 01905 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) 01906 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) 01907 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) 01908 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) 01909 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) 01911 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 01912 01913 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) 01914 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) 01915 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) 01917 /******************************************************************************/ 01918 /* */ 01919 /* DMA Controller (DMA) */ 01920 /* */ 01921 /******************************************************************************/ 01922 01923 /******************* Bit definition for DMA_ISR register ********************/ 01924 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) 01925 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) 01926 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) 01927 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) 01928 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) 01929 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) 01930 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) 01931 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) 01932 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) 01933 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) 01934 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) 01935 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) 01936 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) 01937 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) 01938 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) 01939 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) 01940 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) 01941 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) 01942 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) 01943 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) 01944 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) 01945 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) 01946 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) 01947 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) 01948 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) 01949 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) 01950 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) 01951 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) 01953 /******************* Bit definition for DMA_IFCR register *******************/ 01954 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) 01955 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) 01956 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) 01957 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) 01958 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) 01959 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) 01960 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) 01961 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) 01962 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) 01963 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) 01964 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) 01965 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) 01966 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) 01967 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) 01968 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) 01969 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) 01970 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) 01971 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) 01972 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) 01973 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) 01974 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) 01975 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) 01976 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) 01977 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) 01978 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) 01979 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) 01980 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) 01981 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) 01983 /******************* Bit definition for DMA_CCR1 register *******************/ 01984 #define DMA_CCR1_EN ((uint16_t)0x0001) 01985 #define DMA_CCR1_TCIE ((uint16_t)0x0002) 01986 #define DMA_CCR1_HTIE ((uint16_t)0x0004) 01987 #define DMA_CCR1_TEIE ((uint16_t)0x0008) 01988 #define DMA_CCR1_DIR ((uint16_t)0x0010) 01989 #define DMA_CCR1_CIRC ((uint16_t)0x0020) 01990 #define DMA_CCR1_PINC ((uint16_t)0x0040) 01991 #define DMA_CCR1_MINC ((uint16_t)0x0080) 01993 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) 01994 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) 01995 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) 01997 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) 01998 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) 01999 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) 02001 #define DMA_CCR1_PL ((uint16_t)0x3000) 02002 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) 02003 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) 02005 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) 02007 /******************* Bit definition for DMA_CCR2 register *******************/ 02008 #define DMA_CCR2_EN ((uint16_t)0x0001) 02009 #define DMA_CCR2_TCIE ((uint16_t)0x0002) 02010 #define DMA_CCR2_HTIE ((uint16_t)0x0004) 02011 #define DMA_CCR2_TEIE ((uint16_t)0x0008) 02012 #define DMA_CCR2_DIR ((uint16_t)0x0010) 02013 #define DMA_CCR2_CIRC ((uint16_t)0x0020) 02014 #define DMA_CCR2_PINC ((uint16_t)0x0040) 02015 #define DMA_CCR2_MINC ((uint16_t)0x0080) 02017 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) 02018 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) 02019 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) 02021 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) 02022 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) 02023 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) 02025 #define DMA_CCR2_PL ((uint16_t)0x3000) 02026 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) 02027 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) 02029 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) 02031 /******************* Bit definition for DMA_CCR3 register *******************/ 02032 #define DMA_CCR3_EN ((uint16_t)0x0001) 02033 #define DMA_CCR3_TCIE ((uint16_t)0x0002) 02034 #define DMA_CCR3_HTIE ((uint16_t)0x0004) 02035 #define DMA_CCR3_TEIE ((uint16_t)0x0008) 02036 #define DMA_CCR3_DIR ((uint16_t)0x0010) 02037 #define DMA_CCR3_CIRC ((uint16_t)0x0020) 02038 #define DMA_CCR3_PINC ((uint16_t)0x0040) 02039 #define DMA_CCR3_MINC ((uint16_t)0x0080) 02041 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) 02042 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) 02043 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) 02045 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) 02046 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) 02047 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) 02049 #define DMA_CCR3_PL ((uint16_t)0x3000) 02050 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) 02051 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) 02053 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) 02056 #define DMA_CCR4_EN ((uint16_t)0x0001) 02057 #define DMA_CCR4_TCIE ((uint16_t)0x0002) 02058 #define DMA_CCR4_HTIE ((uint16_t)0x0004) 02059 #define DMA_CCR4_TEIE ((uint16_t)0x0008) 02060 #define DMA_CCR4_DIR ((uint16_t)0x0010) 02061 #define DMA_CCR4_CIRC ((uint16_t)0x0020) 02062 #define DMA_CCR4_PINC ((uint16_t)0x0040) 02063 #define DMA_CCR4_MINC ((uint16_t)0x0080) 02065 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) 02066 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) 02067 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) 02069 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) 02070 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) 02071 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) 02073 #define DMA_CCR4_PL ((uint16_t)0x3000) 02074 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) 02075 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) 02077 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) 02079 /****************** Bit definition for DMA_CCR5 register *******************/ 02080 #define DMA_CCR5_EN ((uint16_t)0x0001) 02081 #define DMA_CCR5_TCIE ((uint16_t)0x0002) 02082 #define DMA_CCR5_HTIE ((uint16_t)0x0004) 02083 #define DMA_CCR5_TEIE ((uint16_t)0x0008) 02084 #define DMA_CCR5_DIR ((uint16_t)0x0010) 02085 #define DMA_CCR5_CIRC ((uint16_t)0x0020) 02086 #define DMA_CCR5_PINC ((uint16_t)0x0040) 02087 #define DMA_CCR5_MINC ((uint16_t)0x0080) 02089 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) 02090 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) 02091 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) 02093 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) 02094 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) 02095 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) 02097 #define DMA_CCR5_PL ((uint16_t)0x3000) 02098 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) 02099 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) 02101 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) 02103 /******************* Bit definition for DMA_CCR6 register *******************/ 02104 #define DMA_CCR6_EN ((uint16_t)0x0001) 02105 #define DMA_CCR6_TCIE ((uint16_t)0x0002) 02106 #define DMA_CCR6_HTIE ((uint16_t)0x0004) 02107 #define DMA_CCR6_TEIE ((uint16_t)0x0008) 02108 #define DMA_CCR6_DIR ((uint16_t)0x0010) 02109 #define DMA_CCR6_CIRC ((uint16_t)0x0020) 02110 #define DMA_CCR6_PINC ((uint16_t)0x0040) 02111 #define DMA_CCR6_MINC ((uint16_t)0x0080) 02113 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) 02114 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) 02115 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) 02117 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) 02118 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) 02119 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) 02121 #define DMA_CCR6_PL ((uint16_t)0x3000) 02122 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) 02123 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) 02125 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) 02127 /******************* Bit definition for DMA_CCR7 register *******************/ 02128 #define DMA_CCR7_EN ((uint16_t)0x0001) 02129 #define DMA_CCR7_TCIE ((uint16_t)0x0002) 02130 #define DMA_CCR7_HTIE ((uint16_t)0x0004) 02131 #define DMA_CCR7_TEIE ((uint16_t)0x0008) 02132 #define DMA_CCR7_DIR ((uint16_t)0x0010) 02133 #define DMA_CCR7_CIRC ((uint16_t)0x0020) 02134 #define DMA_CCR7_PINC ((uint16_t)0x0040) 02135 #define DMA_CCR7_MINC ((uint16_t)0x0080) 02137 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300) 02138 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) 02139 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) 02141 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) 02142 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) 02143 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) 02145 #define DMA_CCR7_PL ((uint16_t)0x3000) 02146 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) 02147 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) 02149 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) 02151 /****************** Bit definition for DMA_CNDTR1 register ******************/ 02152 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) 02154 /****************** Bit definition for DMA_CNDTR2 register ******************/ 02155 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) 02157 /****************** Bit definition for DMA_CNDTR3 register ******************/ 02158 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) 02160 /****************** Bit definition for DMA_CNDTR4 register ******************/ 02161 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) 02163 /****************** Bit definition for DMA_CNDTR5 register ******************/ 02164 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) 02166 /****************** Bit definition for DMA_CNDTR6 register ******************/ 02167 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) 02169 /****************** Bit definition for DMA_CNDTR7 register ******************/ 02170 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) 02172 /****************** Bit definition for DMA_CPAR1 register *******************/ 02173 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) 02175 /****************** Bit definition for DMA_CPAR2 register *******************/ 02176 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) 02178 /****************** Bit definition for DMA_CPAR3 register *******************/ 02179 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) 02182 /****************** Bit definition for DMA_CPAR4 register *******************/ 02183 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) 02185 /****************** Bit definition for DMA_CPAR5 register *******************/ 02186 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) 02188 /****************** Bit definition for DMA_CPAR6 register *******************/ 02189 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) 02192 /****************** Bit definition for DMA_CPAR7 register *******************/ 02193 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) 02195 /****************** Bit definition for DMA_CMAR1 register *******************/ 02196 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) 02198 /****************** Bit definition for DMA_CMAR2 register *******************/ 02199 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) 02201 /****************** Bit definition for DMA_CMAR3 register *******************/ 02202 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) 02205 /****************** Bit definition for DMA_CMAR4 register *******************/ 02206 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) 02208 /****************** Bit definition for DMA_CMAR5 register *******************/ 02209 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) 02211 /****************** Bit definition for DMA_CMAR6 register *******************/ 02212 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) 02214 /****************** Bit definition for DMA_CMAR7 register *******************/ 02215 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) 02217 /******************************************************************************/ 02218 /* */ 02219 /* External Interrupt/Event Controller (EXTI) */ 02220 /* */ 02221 /******************************************************************************/ 02222 02223 /******************* Bit definition for EXTI_IMR register *******************/ 02224 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) 02225 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) 02226 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) 02227 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) 02228 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) 02229 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) 02230 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) 02231 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) 02232 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) 02233 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) 02234 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) 02235 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) 02236 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) 02237 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) 02238 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) 02239 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) 02240 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) 02241 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) 02242 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) 02243 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) 02244 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) 02245 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) 02246 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) 02247 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) 02249 /******************* Bit definition for EXTI_EMR register *******************/ 02250 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) 02251 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) 02252 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) 02253 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) 02254 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) 02255 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) 02256 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) 02257 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) 02258 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) 02259 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) 02260 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) 02261 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) 02262 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) 02263 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) 02264 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) 02265 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) 02266 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) 02267 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) 02268 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) 02269 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) 02270 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) 02271 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) 02272 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) 02273 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) 02275 /****************** Bit definition for EXTI_RTSR register *******************/ 02276 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) 02277 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) 02278 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) 02279 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) 02280 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) 02281 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) 02282 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) 02283 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) 02284 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) 02285 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) 02286 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) 02287 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) 02288 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) 02289 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) 02290 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) 02291 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) 02292 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) 02293 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) 02294 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) 02295 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) 02296 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) 02297 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) 02298 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) 02299 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) 02301 /****************** Bit definition for EXTI_FTSR register *******************/ 02302 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) 02303 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) 02304 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) 02305 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) 02306 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) 02307 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) 02308 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) 02309 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) 02310 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) 02311 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) 02312 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) 02313 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) 02314 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) 02315 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) 02316 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) 02317 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) 02318 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) 02319 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) 02320 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) 02321 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) 02322 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) 02323 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) 02324 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) 02325 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) 02327 /****************** Bit definition for EXTI_SWIER register ******************/ 02328 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) 02329 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) 02330 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) 02331 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) 02332 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) 02333 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) 02334 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) 02335 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) 02336 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) 02337 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) 02338 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) 02339 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) 02340 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) 02341 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) 02342 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) 02343 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) 02344 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) 02345 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) 02346 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) 02347 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) 02348 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) 02349 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) 02350 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) 02351 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) 02353 /******************* Bit definition for EXTI_PR register ********************/ 02354 #define EXTI_PR_PR0 ((uint32_t)0x00000001) 02355 #define EXTI_PR_PR1 ((uint32_t)0x00000002) 02356 #define EXTI_PR_PR2 ((uint32_t)0x00000004) 02357 #define EXTI_PR_PR3 ((uint32_t)0x00000008) 02358 #define EXTI_PR_PR4 ((uint32_t)0x00000010) 02359 #define EXTI_PR_PR5 ((uint32_t)0x00000020) 02360 #define EXTI_PR_PR6 ((uint32_t)0x00000040) 02361 #define EXTI_PR_PR7 ((uint32_t)0x00000080) 02362 #define EXTI_PR_PR8 ((uint32_t)0x00000100) 02363 #define EXTI_PR_PR9 ((uint32_t)0x00000200) 02364 #define EXTI_PR_PR10 ((uint32_t)0x00000400) 02365 #define EXTI_PR_PR11 ((uint32_t)0x00000800) 02366 #define EXTI_PR_PR12 ((uint32_t)0x00001000) 02367 #define EXTI_PR_PR13 ((uint32_t)0x00002000) 02368 #define EXTI_PR_PR14 ((uint32_t)0x00004000) 02369 #define EXTI_PR_PR15 ((uint32_t)0x00008000) 02370 #define EXTI_PR_PR16 ((uint32_t)0x00010000) 02371 #define EXTI_PR_PR17 ((uint32_t)0x00020000) 02372 #define EXTI_PR_PR18 ((uint32_t)0x00040000) 02373 #define EXTI_PR_PR19 ((uint32_t)0x00080000) 02374 #define EXTI_PR_PR20 ((uint32_t)0x00100000) 02375 #define EXTI_PR_PR21 ((uint32_t)0x00200000) 02376 #define EXTI_PR_PR22 ((uint32_t)0x00400000) 02377 #define EXTI_PR_PR23 ((uint32_t)0x00800000) 02379 /******************************************************************************/ 02380 /* */ 02381 /* FLASH, DATA EEPROM and Option Bytes Registers */ 02382 /* (FLASH, DATA_EEPROM, OB) */ 02383 /* */ 02384 /******************************************************************************/ 02385 02386 /******************* Bit definition for FLASH_ACR register ******************/ 02387 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) 02388 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) 02389 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) 02390 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) 02391 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) 02393 /******************* Bit definition for FLASH_PECR register ******************/ 02394 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) 02395 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) 02396 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) 02397 #define FLASH_PECR_PROG ((uint32_t)0x00000008) 02398 #define FLASH_PECR_DATA ((uint32_t)0x00000010) 02399 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) 02400 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) 02401 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) 02402 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) 02403 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) 02404 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) 02405 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) 02407 /****************** Bit definition for FLASH_PDKEYR register ******************/ 02408 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) 02410 /****************** Bit definition for FLASH_PEKEYR register ******************/ 02411 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) 02413 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 02414 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) 02416 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 02417 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) 02419 /****************** Bit definition for FLASH_SR register *******************/ 02420 #define FLASH_SR_BSY ((uint32_t)0x00000001) 02421 #define FLASH_SR_EOP ((uint32_t)0x00000002) 02422 #define FLASH_SR_ENHV ((uint32_t)0x00000004) 02423 #define FLASH_SR_READY ((uint32_t)0x00000008) 02425 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) 02426 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) 02427 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) 02428 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) 02429 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) 02431 /****************** Bit definition for FLASH_OBR register *******************/ 02432 #define FLASH_OBR_RDPRT ((uint16_t)0x000000AA) 02433 #define FLASH_OBR_BOR_LEV ((uint16_t)0x000F0000) 02434 #define FLASH_OBR_USER ((uint32_t)0x00700000) 02435 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) 02436 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) 02437 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) 02438 #define FLASH_OBR_nRST_BFB2 ((uint32_t)0x00800000) 02440 /****************** Bit definition for FLASH_WRPR register ******************/ 02441 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) 02443 /****************** Bit definition for FLASH_WRPR1 register *****************/ 02444 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) 02446 /****************** Bit definition for FLASH_WRPR2 register *****************/ 02447 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) 02448 /******************************************************************************/ 02449 /* */ 02450 /* Flexible Static Memory Controller */ 02451 /* */ 02452 /******************************************************************************/ 02453 /****************** Bit definition for FSMC_BCR1 register *******************/ 02454 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) 02455 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) 02457 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) 02458 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) 02459 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) 02461 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) 02462 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) 02463 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) 02465 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) 02466 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) 02467 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) 02468 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) 02469 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) 02470 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) 02471 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) 02472 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) 02473 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) 02474 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) 02476 /****************** Bit definition for FSMC_BCR2 register *******************/ 02477 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) 02478 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) 02480 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) 02481 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) 02482 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) 02484 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) 02485 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) 02486 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) 02488 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) 02489 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) 02490 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) 02491 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) 02492 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) 02493 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) 02494 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) 02495 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) 02496 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) 02497 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) 02499 /****************** Bit definition for FSMC_BCR3 register *******************/ 02500 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) 02501 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) 02503 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) 02504 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) 02505 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) 02507 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) 02508 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) 02509 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) 02511 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) 02512 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) 02513 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) 02514 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) 02515 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) 02516 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) 02517 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) 02518 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) 02519 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) 02520 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) 02522 /****************** Bit definition for FSMC_BCR4 register *******************/ 02523 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) 02524 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) 02526 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) 02527 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) 02528 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) 02530 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) 02531 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) 02532 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) 02534 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) 02535 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) 02536 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) 02537 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) 02538 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) 02539 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) 02540 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) 02541 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) 02542 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) 02543 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) 02545 /****************** Bit definition for FSMC_BTR1 register ******************/ 02546 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) 02547 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) 02548 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) 02549 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) 02550 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) 02552 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) 02553 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) 02554 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) 02555 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) 02556 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) 02558 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) 02559 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) 02560 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) 02561 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) 02562 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) 02564 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) 02565 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) 02566 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) 02567 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) 02568 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) 02570 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) 02571 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) 02572 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) 02573 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) 02574 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) 02576 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) 02577 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) 02578 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) 02579 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) 02580 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) 02582 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) 02583 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) 02584 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) 02586 /****************** Bit definition for FSMC_BTR2 register *******************/ 02587 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) 02588 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) 02589 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) 02590 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) 02591 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) 02593 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) 02594 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) 02595 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) 02596 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) 02597 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) 02599 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) 02600 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) 02601 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) 02602 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) 02603 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) 02605 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) 02606 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) 02607 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) 02608 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) 02609 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) 02611 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) 02612 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) 02613 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) 02614 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) 02615 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) 02617 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) 02618 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) 02619 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) 02620 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) 02621 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) 02623 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) 02624 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) 02625 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) 02627 /******************* Bit definition for FSMC_BTR3 register *******************/ 02628 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) 02629 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) 02630 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) 02631 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) 02632 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) 02634 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) 02635 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) 02636 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) 02637 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) 02638 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) 02640 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) 02641 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) 02642 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) 02643 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) 02644 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) 02646 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) 02647 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) 02648 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) 02649 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) 02650 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) 02652 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) 02653 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) 02654 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) 02655 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) 02656 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) 02658 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) 02659 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) 02660 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) 02661 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) 02662 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) 02664 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) 02665 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) 02666 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) 02668 /****************** Bit definition for FSMC_BTR4 register *******************/ 02669 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) 02670 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) 02671 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) 02672 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) 02673 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) 02675 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) 02676 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) 02677 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) 02678 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) 02679 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) 02681 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) 02682 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) 02683 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) 02684 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) 02685 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) 02687 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) 02688 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) 02689 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) 02690 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) 02691 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) 02693 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) 02694 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) 02695 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) 02696 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) 02697 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) 02699 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) 02700 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) 02701 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) 02702 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) 02703 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) 02705 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) 02706 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) 02707 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) 02709 /****************** Bit definition for FSMC_BWTR1 register ******************/ 02710 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) 02711 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) 02712 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) 02713 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) 02714 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) 02716 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) 02717 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) 02718 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) 02719 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) 02720 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) 02722 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) 02723 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) 02724 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) 02725 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) 02726 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) 02728 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) 02729 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) 02730 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) 02731 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) 02732 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) 02734 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) 02735 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) 02736 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) 02737 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) 02738 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) 02740 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) 02741 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) 02742 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) 02744 /****************** Bit definition for FSMC_BWTR2 register ******************/ 02745 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) 02746 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) 02747 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) 02748 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) 02749 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) 02751 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) 02752 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) 02753 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) 02754 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) 02755 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) 02757 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) 02758 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) 02759 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) 02760 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) 02761 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) 02763 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) 02764 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) 02765 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) 02766 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) 02767 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) 02769 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) 02770 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) 02771 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) 02772 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) 02773 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) 02775 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) 02776 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) 02777 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) 02779 /****************** Bit definition for FSMC_BWTR3 register ******************/ 02780 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) 02781 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) 02782 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) 02783 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) 02784 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) 02786 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) 02787 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) 02788 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) 02789 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) 02790 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) 02792 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) 02793 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) 02794 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) 02795 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) 02796 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) 02798 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) 02799 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) 02800 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) 02801 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) 02802 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) 02804 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) 02805 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) 02806 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) 02807 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) 02808 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) 02810 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) 02811 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) 02812 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) 02814 /****************** Bit definition for FSMC_BWTR4 register ******************/ 02815 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) 02816 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) 02817 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) 02818 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) 02819 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) 02821 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) 02822 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) 02823 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) 02824 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) 02825 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) 02827 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) 02828 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) 02829 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) 02830 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) 02831 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) 02833 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) 02834 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) 02835 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) 02836 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) 02837 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) 02839 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 02840 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 02841 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 02842 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 02843 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) 02845 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 02846 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 02847 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 02849 /******************************************************************************/ 02850 /* */ 02851 /* General Purpose IOs (GPIO) */ 02852 /* */ 02853 /******************************************************************************/ 02854 /******************* Bit definition for GPIO_MODER register *****************/ 02855 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) 02856 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) 02857 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) 02858 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) 02859 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) 02860 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) 02861 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) 02862 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) 02863 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) 02864 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) 02865 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) 02866 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) 02867 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) 02868 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) 02869 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) 02870 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) 02871 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) 02872 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) 02873 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) 02874 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) 02875 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) 02876 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) 02877 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) 02878 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) 02879 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) 02880 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) 02881 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) 02882 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) 02883 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) 02884 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) 02885 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) 02886 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) 02887 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) 02888 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) 02889 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) 02890 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) 02891 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) 02892 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) 02893 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) 02894 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) 02895 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) 02896 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) 02897 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) 02898 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) 02899 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) 02900 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) 02901 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) 02902 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) 02903 02904 /******************* Bit definition for GPIO_OTYPER register ****************/ 02905 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) 02906 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) 02907 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) 02908 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) 02909 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) 02910 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) 02911 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) 02912 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) 02913 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) 02914 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) 02915 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) 02916 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) 02917 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) 02918 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) 02919 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) 02920 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) 02921 02922 /******************* Bit definition for GPIO_OSPEEDR register ***************/ 02923 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) 02924 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) 02925 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) 02926 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) 02927 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) 02928 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) 02929 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) 02930 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) 02931 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) 02932 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) 02933 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) 02934 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) 02935 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) 02936 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) 02937 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) 02938 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) 02939 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) 02940 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) 02941 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) 02942 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) 02943 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) 02944 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) 02945 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) 02946 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) 02947 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) 02948 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) 02949 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) 02950 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) 02951 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) 02952 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) 02953 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) 02954 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) 02955 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) 02956 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) 02957 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) 02958 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) 02959 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) 02960 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) 02961 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) 02962 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) 02963 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) 02964 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) 02965 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) 02966 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) 02967 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) 02968 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) 02969 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) 02970 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) 02971 02972 /******************* Bit definition for GPIO_PUPDR register *****************/ 02973 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) 02974 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) 02975 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) 02976 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) 02977 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) 02978 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) 02979 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) 02980 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) 02981 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) 02982 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) 02983 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) 02984 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) 02985 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) 02986 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) 02987 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) 02988 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) 02989 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) 02990 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) 02991 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) 02992 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) 02993 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) 02994 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) 02995 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) 02996 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) 02997 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) 02998 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) 02999 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) 03000 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) 03001 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) 03002 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) 03003 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) 03004 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) 03005 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) 03006 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) 03007 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) 03008 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) 03009 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) 03010 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) 03011 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) 03012 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) 03013 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) 03014 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) 03015 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) 03016 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) 03017 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) 03018 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) 03019 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) 03020 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) 03021 03022 /****************** Bits definition for GPIO_IDR register *******************/ 03023 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) 03024 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) 03025 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) 03026 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) 03027 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) 03028 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) 03029 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) 03030 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) 03031 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) 03032 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) 03033 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) 03034 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) 03035 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) 03036 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) 03037 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) 03038 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) 03039 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ 03040 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 03041 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 03042 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 03043 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 03044 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 03045 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 03046 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 03047 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 03048 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 03049 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 03050 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 03051 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 03052 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 03053 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 03054 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 03055 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 03056 03057 /****************** Bits definition for GPIO_ODR register *******************/ 03058 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) 03059 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) 03060 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) 03061 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) 03062 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) 03063 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) 03064 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) 03065 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) 03066 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) 03067 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) 03068 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) 03069 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) 03070 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) 03071 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) 03072 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) 03073 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) 03074 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ 03075 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 03076 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 03077 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 03078 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 03079 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 03080 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 03081 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 03082 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 03083 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 03084 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 03085 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 03086 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 03087 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 03088 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 03089 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 03090 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 03091 03092 /******************* Bit definition for GPIO_BSRR register ******************/ 03093 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) 03094 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) 03095 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) 03096 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) 03097 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) 03098 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) 03099 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) 03100 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) 03101 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) 03102 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) 03103 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) 03104 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) 03105 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) 03106 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) 03107 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) 03108 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) 03109 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) 03110 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) 03111 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) 03112 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) 03113 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) 03114 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) 03115 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) 03116 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) 03117 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) 03118 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) 03119 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) 03120 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) 03121 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) 03122 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) 03123 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) 03124 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) 03125 03126 /******************* Bit definition for GPIO_LCKR register ******************/ 03127 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) 03128 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) 03129 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) 03130 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) 03131 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) 03132 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) 03133 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) 03134 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) 03135 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) 03136 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) 03137 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) 03138 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) 03139 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) 03140 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) 03141 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) 03142 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) 03143 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) 03144 03145 /******************* Bit definition for GPIO_AFRL register ******************/ 03146 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F) 03147 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0) 03148 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00) 03149 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000) 03150 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000) 03151 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000) 03152 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000) 03153 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000) 03154 03155 /******************* Bit definition for GPIO_AFRH register ******************/ 03156 #define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F) 03157 #define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0) 03158 #define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00) 03159 #define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000) 03160 #define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000) 03161 #define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000) 03162 #define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000) 03163 #define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000) 03164 03165 /******************************************************************************/ 03166 /* */ 03167 /* Inter-integrated Circuit Interface (I2C) */ 03168 /* */ 03169 /******************************************************************************/ 03170 03171 /******************* Bit definition for I2C_CR1 register ********************/ 03172 #define I2C_CR1_PE ((uint16_t)0x0001) 03173 #define I2C_CR1_SMBUS ((uint16_t)0x0002) 03174 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) 03175 #define I2C_CR1_ENARP ((uint16_t)0x0010) 03176 #define I2C_CR1_ENPEC ((uint16_t)0x0020) 03177 #define I2C_CR1_ENGC ((uint16_t)0x0040) 03178 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) 03179 #define I2C_CR1_START ((uint16_t)0x0100) 03180 #define I2C_CR1_STOP ((uint16_t)0x0200) 03181 #define I2C_CR1_ACK ((uint16_t)0x0400) 03182 #define I2C_CR1_POS ((uint16_t)0x0800) 03183 #define I2C_CR1_PEC ((uint16_t)0x1000) 03184 #define I2C_CR1_ALERT ((uint16_t)0x2000) 03185 #define I2C_CR1_SWRST ((uint16_t)0x8000) 03187 /******************* Bit definition for I2C_CR2 register ********************/ 03188 #define I2C_CR2_FREQ ((uint16_t)0x003F) 03189 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) 03190 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) 03191 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) 03192 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) 03193 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) 03194 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) 03196 #define I2C_CR2_ITERREN ((uint16_t)0x0100) 03197 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) 03198 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) 03199 #define I2C_CR2_DMAEN ((uint16_t)0x0800) 03200 #define I2C_CR2_LAST ((uint16_t)0x1000) 03202 /******************* Bit definition for I2C_OAR1 register *******************/ 03203 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) 03204 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) 03206 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) 03207 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) 03208 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) 03209 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) 03210 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) 03211 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) 03212 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) 03213 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) 03214 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) 03215 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) 03217 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) 03219 /******************* Bit definition for I2C_OAR2 register *******************/ 03220 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) 03221 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) 03223 /******************** Bit definition for I2C_DR register ********************/ 03224 #define I2C_DR_DR ((uint8_t)0xFF) 03226 /******************* Bit definition for I2C_SR1 register ********************/ 03227 #define I2C_SR1_SB ((uint16_t)0x0001) 03228 #define I2C_SR1_ADDR ((uint16_t)0x0002) 03229 #define I2C_SR1_BTF ((uint16_t)0x0004) 03230 #define I2C_SR1_ADD10 ((uint16_t)0x0008) 03231 #define I2C_SR1_STOPF ((uint16_t)0x0010) 03232 #define I2C_SR1_RXNE ((uint16_t)0x0040) 03233 #define I2C_SR1_TXE ((uint16_t)0x0080) 03234 #define I2C_SR1_BERR ((uint16_t)0x0100) 03235 #define I2C_SR1_ARLO ((uint16_t)0x0200) 03236 #define I2C_SR1_AF ((uint16_t)0x0400) 03237 #define I2C_SR1_OVR ((uint16_t)0x0800) 03238 #define I2C_SR1_PECERR ((uint16_t)0x1000) 03239 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) 03240 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) 03242 /******************* Bit definition for I2C_SR2 register ********************/ 03243 #define I2C_SR2_MSL ((uint16_t)0x0001) 03244 #define I2C_SR2_BUSY ((uint16_t)0x0002) 03245 #define I2C_SR2_TRA ((uint16_t)0x0004) 03246 #define I2C_SR2_GENCALL ((uint16_t)0x0010) 03247 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) 03248 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) 03249 #define I2C_SR2_DUALF ((uint16_t)0x0080) 03250 #define I2C_SR2_PEC ((uint16_t)0xFF00) 03252 /******************* Bit definition for I2C_CCR register ********************/ 03253 #define I2C_CCR_CCR ((uint16_t)0x0FFF) 03254 #define I2C_CCR_DUTY ((uint16_t)0x4000) 03255 #define I2C_CCR_FS ((uint16_t)0x8000) 03257 /****************** Bit definition for I2C_TRISE register *******************/ 03258 #define I2C_TRISE_TRISE ((uint8_t)0x3F) 03260 /******************************************************************************/ 03261 /* */ 03262 /* Independent WATCHDOG (IWDG) */ 03263 /* */ 03264 /******************************************************************************/ 03265 03266 /******************* Bit definition for IWDG_KR register ********************/ 03267 #define IWDG_KR_KEY ((uint16_t)0xFFFF) 03269 /******************* Bit definition for IWDG_PR register ********************/ 03270 #define IWDG_PR_PR ((uint8_t)0x07) 03271 #define IWDG_PR_PR_0 ((uint8_t)0x01) 03272 #define IWDG_PR_PR_1 ((uint8_t)0x02) 03273 #define IWDG_PR_PR_2 ((uint8_t)0x04) 03275 /******************* Bit definition for IWDG_RLR register *******************/ 03276 #define IWDG_RLR_RL ((uint16_t)0x0FFF) 03278 /******************* Bit definition for IWDG_SR register ********************/ 03279 #define IWDG_SR_PVU ((uint8_t)0x01) 03280 #define IWDG_SR_RVU ((uint8_t)0x02) 03282 /******************************************************************************/ 03283 /* */ 03284 /* LCD Controller (LCD) */ 03285 /* */ 03286 /******************************************************************************/ 03287 03288 /******************* Bit definition for LCD_CR register *********************/ 03289 #define LCD_CR_LCDEN ((uint32_t)0x00000001) 03290 #define LCD_CR_VSEL ((uint32_t)0x00000002) 03292 #define LCD_CR_DUTY ((uint32_t)0x0000001C) 03293 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) 03294 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) 03295 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) 03297 #define LCD_CR_BIAS ((uint32_t)0x00000060) 03298 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) 03299 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) 03301 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) 03303 /******************* Bit definition for LCD_FCR register ********************/ 03304 #define LCD_FCR_HD ((uint32_t)0x00000001) 03305 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) 03306 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) 03308 #define LCD_FCR_PON ((uint32_t)0x00000070) 03309 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) 03310 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) 03311 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) 03313 #define LCD_FCR_DEAD ((uint32_t)0x00000380) 03314 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) 03315 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) 03316 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) 03318 #define LCD_FCR_CC ((uint32_t)0x00001C00) 03319 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) 03320 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) 03321 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) 03323 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) 03324 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) 03325 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) 03326 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) 03328 #define LCD_FCR_BLINK ((uint32_t)0x00030000) 03329 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) 03330 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) 03332 #define LCD_FCR_DIV ((uint32_t)0x003C0000) 03333 #define LCD_FCR_PS ((uint32_t)0x03C00000) 03335 /******************* Bit definition for LCD_SR register *********************/ 03336 #define LCD_SR_ENS ((uint32_t)0x00000001) 03337 #define LCD_SR_SOF ((uint32_t)0x00000002) 03338 #define LCD_SR_UDR ((uint32_t)0x00000004) 03339 #define LCD_SR_UDD ((uint32_t)0x00000008) 03340 #define LCD_SR_RDY ((uint32_t)0x00000010) 03341 #define LCD_SR_FCRSR ((uint32_t)0x00000020) 03343 /******************* Bit definition for LCD_CLR register ********************/ 03344 #define LCD_CLR_SOFC ((uint32_t)0x00000002) 03345 #define LCD_CLR_UDDC ((uint32_t)0x00000008) 03347 /******************* Bit definition for LCD_RAM register ********************/ 03348 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) 03350 /******************************************************************************/ 03351 /* */ 03352 /* Power Control (PWR) */ 03353 /* */ 03354 /******************************************************************************/ 03355 03356 /******************** Bit definition for PWR_CR register ********************/ 03357 #define PWR_CR_LPSDSR ((uint16_t)0x0001) 03358 #define PWR_CR_PDDS ((uint16_t)0x0002) 03359 #define PWR_CR_CWUF ((uint16_t)0x0004) 03360 #define PWR_CR_CSBF ((uint16_t)0x0008) 03361 #define PWR_CR_PVDE ((uint16_t)0x0010) 03363 #define PWR_CR_PLS ((uint16_t)0x00E0) 03364 #define PWR_CR_PLS_0 ((uint16_t)0x0020) 03365 #define PWR_CR_PLS_1 ((uint16_t)0x0040) 03366 #define PWR_CR_PLS_2 ((uint16_t)0x0080) 03369 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) 03370 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) 03371 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) 03372 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) 03373 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) 03374 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) 03375 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) 03376 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) 03378 #define PWR_CR_DBP ((uint16_t)0x0100) 03379 #define PWR_CR_ULP ((uint16_t)0x0200) 03380 #define PWR_CR_FWU ((uint16_t)0x0400) 03382 #define PWR_CR_VOS ((uint16_t)0x1800) 03383 #define PWR_CR_VOS_0 ((uint16_t)0x0800) 03384 #define PWR_CR_VOS_1 ((uint16_t)0x1000) 03385 #define PWR_CR_LPRUN ((uint16_t)0x4000) 03387 /******************* Bit definition for PWR_CSR register ********************/ 03388 #define PWR_CSR_WUF ((uint16_t)0x0001) 03389 #define PWR_CSR_SBF ((uint16_t)0x0002) 03390 #define PWR_CSR_PVDO ((uint16_t)0x0004) 03391 #define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) 03392 #define PWR_CSR_VOSF ((uint16_t)0x0010) 03393 #define PWR_CSR_REGLPF ((uint16_t)0x0020) 03395 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) 03396 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) 03397 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) 03399 /******************************************************************************/ 03400 /* */ 03401 /* Reset and Clock Control (RCC) */ 03402 /* */ 03403 /******************************************************************************/ 03404 /******************** Bit definition for RCC_CR register ********************/ 03405 #define RCC_CR_HSION ((uint32_t)0x00000001) 03406 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 03408 #define RCC_CR_MSION ((uint32_t)0x00000100) 03409 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) 03411 #define RCC_CR_HSEON ((uint32_t)0x00010000) 03412 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 03413 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 03415 #define RCC_CR_PLLON ((uint32_t)0x01000000) 03416 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 03417 #define RCC_CR_CSSON ((uint32_t)0x10000000) 03419 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) 03420 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) 03421 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) 03423 /******************** Bit definition for RCC_ICSCR register *****************/ 03424 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) 03425 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) 03427 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) 03428 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) 03429 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) 03430 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) 03431 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) 03432 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) 03433 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) 03434 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) 03435 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) 03436 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) 03438 /******************** Bit definition for RCC_CFGR register ******************/ 03439 #define RCC_CFGR_SW ((uint32_t)0x00000003) 03440 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) 03441 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) 03444 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) 03445 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) 03446 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) 03447 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) 03449 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) 03450 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) 03451 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) 03454 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) 03455 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) 03456 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) 03457 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) 03459 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) 03460 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) 03461 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) 03462 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) 03463 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) 03466 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) 03467 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) 03468 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) 03469 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) 03470 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) 03471 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) 03472 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) 03473 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) 03474 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) 03476 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) 03477 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) 03478 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) 03479 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) 03482 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) 03483 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) 03484 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) 03485 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) 03486 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) 03488 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) 03489 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) 03490 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) 03491 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) 03494 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) 03495 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) 03496 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) 03497 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) 03498 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) 03501 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) 03503 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) 03504 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) 03507 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) 03508 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) 03509 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) 03510 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) 03511 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) 03514 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) 03515 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) 03516 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) 03517 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) 03518 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) 03519 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) 03520 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) 03521 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) 03522 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) 03525 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) 03526 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) 03527 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) 03531 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) 03532 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) 03533 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) 03534 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) 03537 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) 03538 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) 03539 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) 03540 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) 03543 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 03544 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) 03545 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) 03546 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) 03547 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) 03548 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) 03549 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) 03550 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) 03552 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) 03553 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) 03554 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) 03555 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) 03558 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) 03559 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) 03560 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) 03561 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) 03562 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) 03565 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 03566 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) 03567 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 03568 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) 03569 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 03570 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) 03571 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) 03572 #define RCC_CIR_CSSF ((uint32_t)0x00000080) 03574 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) 03575 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) 03576 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) 03577 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) 03578 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) 03579 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) 03580 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) 03582 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) 03583 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 03584 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 03585 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 03586 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) 03587 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) 03588 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) 03589 #define RCC_CIR_CSSC ((uint32_t)0x00800000) 03592 /***************** Bit definition for RCC_AHBRSTR register ******************/ 03593 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) 03594 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) 03595 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) 03596 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) 03597 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) 03598 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) 03599 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) 03600 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) 03601 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) 03602 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) 03603 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) 03604 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) 03605 #define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) 03606 #define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) 03608 /***************** Bit definition for RCC_APB2RSTR register *****************/ 03609 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) 03610 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) 03611 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) 03612 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) 03613 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) 03614 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) 03615 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) 03616 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) 03618 /***************** Bit definition for RCC_APB1RSTR register *****************/ 03619 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) 03620 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 03621 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) 03622 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 03623 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 03624 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 03625 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) 03626 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) 03627 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) 03628 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) 03629 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 03630 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) 03631 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 03632 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 03633 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) 03634 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 03635 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) 03636 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 03637 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 03638 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) 03640 /****************** Bit definition for RCC_AHBENR register ******************/ 03641 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) 03642 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) 03643 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) 03644 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) 03645 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) 03646 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) 03647 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) 03648 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) 03649 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) 03650 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) 03652 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) 03653 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) 03654 #define RCC_AHBENR_AESEN ((uint32_t)0x08000000) 03655 #define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) 03658 /****************** Bit definition for RCC_APB2ENR register *****************/ 03659 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) 03660 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) 03661 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) 03662 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) 03663 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) 03664 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) 03665 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) 03666 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) 03669 /***************** Bit definition for RCC_APB1ENR register ******************/ 03670 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 03671 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) 03672 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) 03673 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 03674 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 03675 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 03676 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) 03677 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 03678 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) 03679 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 03680 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 03681 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) 03682 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 03683 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 03684 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) 03685 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 03686 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) 03687 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) 03688 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 03689 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) 03691 /****************** Bit definition for RCC_AHBLPENR register ****************/ 03692 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) 03693 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) 03694 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) 03695 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) 03696 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) 03697 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) 03698 #define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) 03699 #define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) 03700 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) 03701 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) 03704 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) 03705 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) 03706 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) 03707 #define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) 03708 #define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) 03710 /****************** Bit definition for RCC_APB2LPENR register ***************/ 03711 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) 03712 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) 03713 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) 03714 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) 03715 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) 03716 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) 03717 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) 03718 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) 03720 /***************** Bit definition for RCC_APB1LPENR register ****************/ 03721 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) 03722 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) 03723 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) 03724 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) 03725 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) 03726 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) 03727 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) 03728 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) 03729 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) 03730 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) 03731 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) 03732 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) 03733 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) 03734 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) 03735 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) 03736 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) 03737 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) 03738 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) 03739 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) 03740 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) 03742 /******************* Bit definition for RCC_CSR register ********************/ 03743 #define RCC_CSR_LSION ((uint32_t)0x00000001) 03744 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) 03746 #define RCC_CSR_LSEON ((uint32_t)0x00000100) 03747 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) 03748 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) 03749 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) 03750 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) 03752 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) 03753 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) 03754 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) 03757 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) 03758 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) 03759 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) 03760 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) 03762 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) 03763 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) 03765 #define RCC_CSR_RMVF ((uint32_t)0x01000000) 03766 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) 03767 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) 03768 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) 03769 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 03770 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) 03771 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) 03772 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) 03775 /******************************************************************************/ 03776 /* */ 03777 /* Real-Time Clock (RTC) */ 03778 /* */ 03779 /******************************************************************************/ 03780 /******************** Bits definition for RTC_TR register *******************/ 03781 #define RTC_TR_PM ((uint32_t)0x00400000) 03782 #define RTC_TR_HT ((uint32_t)0x00300000) 03783 #define RTC_TR_HT_0 ((uint32_t)0x00100000) 03784 #define RTC_TR_HT_1 ((uint32_t)0x00200000) 03785 #define RTC_TR_HU ((uint32_t)0x000F0000) 03786 #define RTC_TR_HU_0 ((uint32_t)0x00010000) 03787 #define RTC_TR_HU_1 ((uint32_t)0x00020000) 03788 #define RTC_TR_HU_2 ((uint32_t)0x00040000) 03789 #define RTC_TR_HU_3 ((uint32_t)0x00080000) 03790 #define RTC_TR_MNT ((uint32_t)0x00007000) 03791 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) 03792 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) 03793 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) 03794 #define RTC_TR_MNU ((uint32_t)0x00000F00) 03795 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) 03796 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) 03797 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) 03798 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) 03799 #define RTC_TR_ST ((uint32_t)0x00000070) 03800 #define RTC_TR_ST_0 ((uint32_t)0x00000010) 03801 #define RTC_TR_ST_1 ((uint32_t)0x00000020) 03802 #define RTC_TR_ST_2 ((uint32_t)0x00000040) 03803 #define RTC_TR_SU ((uint32_t)0x0000000F) 03804 #define RTC_TR_SU_0 ((uint32_t)0x00000001) 03805 #define RTC_TR_SU_1 ((uint32_t)0x00000002) 03806 #define RTC_TR_SU_2 ((uint32_t)0x00000004) 03807 #define RTC_TR_SU_3 ((uint32_t)0x00000008) 03808 03809 /******************** Bits definition for RTC_DR register *******************/ 03810 #define RTC_DR_YT ((uint32_t)0x00F00000) 03811 #define RTC_DR_YT_0 ((uint32_t)0x00100000) 03812 #define RTC_DR_YT_1 ((uint32_t)0x00200000) 03813 #define RTC_DR_YT_2 ((uint32_t)0x00400000) 03814 #define RTC_DR_YT_3 ((uint32_t)0x00800000) 03815 #define RTC_DR_YU ((uint32_t)0x000F0000) 03816 #define RTC_DR_YU_0 ((uint32_t)0x00010000) 03817 #define RTC_DR_YU_1 ((uint32_t)0x00020000) 03818 #define RTC_DR_YU_2 ((uint32_t)0x00040000) 03819 #define RTC_DR_YU_3 ((uint32_t)0x00080000) 03820 #define RTC_DR_WDU ((uint32_t)0x0000E000) 03821 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) 03822 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) 03823 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) 03824 #define RTC_DR_MT ((uint32_t)0x00001000) 03825 #define RTC_DR_MU ((uint32_t)0x00000F00) 03826 #define RTC_DR_MU_0 ((uint32_t)0x00000100) 03827 #define RTC_DR_MU_1 ((uint32_t)0x00000200) 03828 #define RTC_DR_MU_2 ((uint32_t)0x00000400) 03829 #define RTC_DR_MU_3 ((uint32_t)0x00000800) 03830 #define RTC_DR_DT ((uint32_t)0x00000030) 03831 #define RTC_DR_DT_0 ((uint32_t)0x00000010) 03832 #define RTC_DR_DT_1 ((uint32_t)0x00000020) 03833 #define RTC_DR_DU ((uint32_t)0x0000000F) 03834 #define RTC_DR_DU_0 ((uint32_t)0x00000001) 03835 #define RTC_DR_DU_1 ((uint32_t)0x00000002) 03836 #define RTC_DR_DU_2 ((uint32_t)0x00000004) 03837 #define RTC_DR_DU_3 ((uint32_t)0x00000008) 03838 03839 /******************** Bits definition for RTC_CR register *******************/ 03840 #define RTC_CR_COE ((uint32_t)0x00800000) 03841 #define RTC_CR_OSEL ((uint32_t)0x00600000) 03842 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) 03843 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) 03844 #define RTC_CR_POL ((uint32_t)0x00100000) 03845 #define RTC_CR_COSEL ((uint32_t)0x00080000) 03846 #define RTC_CR_BCK ((uint32_t)0x00040000) 03847 #define RTC_CR_SUB1H ((uint32_t)0x00020000) 03848 #define RTC_CR_ADD1H ((uint32_t)0x00010000) 03849 #define RTC_CR_TSIE ((uint32_t)0x00008000) 03850 #define RTC_CR_WUTIE ((uint32_t)0x00004000) 03851 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) 03852 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) 03853 #define RTC_CR_TSE ((uint32_t)0x00000800) 03854 #define RTC_CR_WUTE ((uint32_t)0x00000400) 03855 #define RTC_CR_ALRBE ((uint32_t)0x00000200) 03856 #define RTC_CR_ALRAE ((uint32_t)0x00000100) 03857 #define RTC_CR_DCE ((uint32_t)0x00000080) 03858 #define RTC_CR_FMT ((uint32_t)0x00000040) 03859 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) 03860 #define RTC_CR_REFCKON ((uint32_t)0x00000010) 03861 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) 03862 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) 03863 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) 03864 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) 03865 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) 03866 03867 /******************** Bits definition for RTC_ISR register ******************/ 03868 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) 03869 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000) 03870 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000) 03871 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) 03872 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) 03873 #define RTC_ISR_TSF ((uint32_t)0x00000800) 03874 #define RTC_ISR_WUTF ((uint32_t)0x00000400) 03875 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) 03876 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) 03877 #define RTC_ISR_INIT ((uint32_t)0x00000080) 03878 #define RTC_ISR_INITF ((uint32_t)0x00000040) 03879 #define RTC_ISR_RSF ((uint32_t)0x00000020) 03880 #define RTC_ISR_INITS ((uint32_t)0x00000010) 03881 #define RTC_ISR_SHPF ((uint32_t)0x00000008) 03882 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) 03883 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) 03884 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) 03885 03886 /******************** Bits definition for RTC_PRER register *****************/ 03887 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) 03888 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF) 03889 03890 /******************** Bits definition for RTC_WUTR register *****************/ 03891 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) 03892 03893 /******************** Bits definition for RTC_CALIBR register ***************/ 03894 #define RTC_CALIBR_DCS ((uint32_t)0x00000080) 03895 #define RTC_CALIBR_DC ((uint32_t)0x0000001F) 03896 03897 /******************** Bits definition for RTC_ALRMAR register ***************/ 03898 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) 03899 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) 03900 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) 03901 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) 03902 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) 03903 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) 03904 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) 03905 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) 03906 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) 03907 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) 03908 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) 03909 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) 03910 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) 03911 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) 03912 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) 03913 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) 03914 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) 03915 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) 03916 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) 03917 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) 03918 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) 03919 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) 03920 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) 03921 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) 03922 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) 03923 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) 03924 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) 03925 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) 03926 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) 03927 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) 03928 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) 03929 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) 03930 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) 03931 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) 03932 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) 03933 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) 03934 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) 03935 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) 03936 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) 03937 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) 03938 03939 /******************** Bits definition for RTC_ALRMBR register ***************/ 03940 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) 03941 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) 03942 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) 03943 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) 03944 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) 03945 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) 03946 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) 03947 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) 03948 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) 03949 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) 03950 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) 03951 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) 03952 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) 03953 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) 03954 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) 03955 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) 03956 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) 03957 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) 03958 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) 03959 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) 03960 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) 03961 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) 03962 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) 03963 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) 03964 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) 03965 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) 03966 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) 03967 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) 03968 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) 03969 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) 03970 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) 03971 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) 03972 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) 03973 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) 03974 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) 03975 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) 03976 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) 03977 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) 03978 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) 03979 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) 03980 03981 /******************** Bits definition for RTC_WPR register ******************/ 03982 #define RTC_WPR_KEY ((uint32_t)0x000000FF) 03983 03984 /******************** Bits definition for RTC_SSR register ******************/ 03985 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) 03986 03987 /******************** Bits definition for RTC_SHIFTR register ***************/ 03988 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) 03989 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) 03990 03991 /******************** Bits definition for RTC_TSTR register *****************/ 03992 #define RTC_TSTR_PM ((uint32_t)0x00400000) 03993 #define RTC_TSTR_HT ((uint32_t)0x00300000) 03994 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) 03995 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) 03996 #define RTC_TSTR_HU ((uint32_t)0x000F0000) 03997 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) 03998 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) 03999 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) 04000 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) 04001 #define RTC_TSTR_MNT ((uint32_t)0x00007000) 04002 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) 04003 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) 04004 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) 04005 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) 04006 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) 04007 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) 04008 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) 04009 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) 04010 #define RTC_TSTR_ST ((uint32_t)0x00000070) 04011 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) 04012 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) 04013 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) 04014 #define RTC_TSTR_SU ((uint32_t)0x0000000F) 04015 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) 04016 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) 04017 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) 04018 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) 04019 04020 /******************** Bits definition for RTC_TSDR register *****************/ 04021 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) 04022 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) 04023 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) 04024 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) 04025 #define RTC_TSDR_MT ((uint32_t)0x00001000) 04026 #define RTC_TSDR_MU ((uint32_t)0x00000F00) 04027 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) 04028 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) 04029 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) 04030 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) 04031 #define RTC_TSDR_DT ((uint32_t)0x00000030) 04032 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) 04033 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) 04034 #define RTC_TSDR_DU ((uint32_t)0x0000000F) 04035 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) 04036 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) 04037 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) 04038 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) 04039 04040 /******************** Bits definition for RTC_TSSSR register ****************/ 04041 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) 04042 04043 /******************** Bits definition for RTC_CAL register *****************/ 04044 #define RTC_CALR_CALP ((uint32_t)0x00008000) 04045 #define RTC_CALR_CALW8 ((uint32_t)0x00004000) 04046 #define RTC_CALR_CALW16 ((uint32_t)0x00002000) 04047 #define RTC_CALR_CALM ((uint32_t)0x000001FF) 04048 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) 04049 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) 04050 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) 04051 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) 04052 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) 04053 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) 04054 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) 04055 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) 04056 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) 04057 04058 /******************** Bits definition for RTC_TAFCR register ****************/ 04059 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) 04060 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) 04061 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) 04062 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) 04063 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) 04064 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) 04065 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) 04066 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) 04067 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) 04068 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) 04069 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) 04070 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) 04071 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) 04072 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040) 04073 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020) 04074 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010) 04075 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008) 04076 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) 04077 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) 04078 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) 04079 04080 /******************** Bits definition for RTC_ALRMASSR register *************/ 04081 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) 04082 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) 04083 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) 04084 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) 04085 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) 04086 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) 04087 04088 /******************** Bits definition for RTC_ALRMBSSR register *************/ 04089 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) 04090 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) 04091 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) 04092 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) 04093 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) 04094 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) 04095 04096 /******************** Bits definition for RTC_BKP0R register ****************/ 04097 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) 04098 04099 /******************** Bits definition for RTC_BKP1R register ****************/ 04100 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) 04101 04102 /******************** Bits definition for RTC_BKP2R register ****************/ 04103 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) 04104 04105 /******************** Bits definition for RTC_BKP3R register ****************/ 04106 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) 04107 04108 /******************** Bits definition for RTC_BKP4R register ****************/ 04109 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) 04110 04111 /******************** Bits definition for RTC_BKP5R register ****************/ 04112 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) 04113 04114 /******************** Bits definition for RTC_BKP6R register ****************/ 04115 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) 04116 04117 /******************** Bits definition for RTC_BKP7R register ****************/ 04118 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) 04119 04120 /******************** Bits definition for RTC_BKP8R register ****************/ 04121 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) 04122 04123 /******************** Bits definition for RTC_BKP9R register ****************/ 04124 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) 04125 04126 /******************** Bits definition for RTC_BKP10R register ***************/ 04127 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) 04128 04129 /******************** Bits definition for RTC_BKP11R register ***************/ 04130 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) 04131 04132 /******************** Bits definition for RTC_BKP12R register ***************/ 04133 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) 04134 04135 /******************** Bits definition for RTC_BKP13R register ***************/ 04136 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) 04137 04138 /******************** Bits definition for RTC_BKP14R register ***************/ 04139 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) 04140 04141 /******************** Bits definition for RTC_BKP15R register ***************/ 04142 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) 04143 04144 /******************** Bits definition for RTC_BKP16R register ***************/ 04145 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) 04146 04147 /******************** Bits definition for RTC_BKP17R register ***************/ 04148 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) 04149 04150 /******************** Bits definition for RTC_BKP18R register ***************/ 04151 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) 04152 04153 /******************** Bits definition for RTC_BKP19R register ***************/ 04154 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) 04155 04156 /******************** Bits definition for RTC_BKP20R register ***************/ 04157 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF) 04158 04159 /******************** Bits definition for RTC_BKP21R register ***************/ 04160 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF) 04161 04162 /******************** Bits definition for RTC_BKP22R register ***************/ 04163 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF) 04164 04165 /******************** Bits definition for RTC_BKP23R register ***************/ 04166 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF) 04167 04168 /******************** Bits definition for RTC_BKP24R register ***************/ 04169 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF) 04170 04171 /******************** Bits definition for RTC_BKP25R register ***************/ 04172 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF) 04173 04174 /******************** Bits definition for RTC_BKP26R register ***************/ 04175 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF) 04176 04177 /******************** Bits definition for RTC_BKP27R register ***************/ 04178 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF) 04179 04180 /******************** Bits definition for RTC_BKP28R register ***************/ 04181 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF) 04182 04183 /******************** Bits definition for RTC_BKP29R register ***************/ 04184 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF) 04185 04186 /******************** Bits definition for RTC_BKP30R register ***************/ 04187 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF) 04188 04189 /******************** Bits definition for RTC_BKP31R register ***************/ 04190 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF) 04191 04192 /******************************************************************************/ 04193 /* */ 04194 /* SD host Interface */ 04195 /* */ 04196 /******************************************************************************/ 04197 04198 /****************** Bit definition for SDIO_POWER register ******************/ 04199 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) 04200 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) 04201 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) 04203 /****************** Bit definition for SDIO_CLKCR register ******************/ 04204 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) 04205 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) 04206 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) 04207 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) 04209 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) 04210 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) 04211 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) 04213 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) 04214 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) 04216 /******************* Bit definition for SDIO_ARG register *******************/ 04217 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) 04219 /******************* Bit definition for SDIO_CMD register *******************/ 04220 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) 04222 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) 04223 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) 04224 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) 04226 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) 04227 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) 04228 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) 04229 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) 04230 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) 04231 #define SDIO_CMD_NIEN ((uint16_t)0x2000) 04232 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) 04234 /***************** Bit definition for SDIO_RESPCMD register *****************/ 04235 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) 04237 /****************** Bit definition for SDIO_RESP0 register ******************/ 04238 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) 04240 /****************** Bit definition for SDIO_RESP1 register ******************/ 04241 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) 04243 /****************** Bit definition for SDIO_RESP2 register ******************/ 04244 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) 04246 /****************** Bit definition for SDIO_RESP3 register ******************/ 04247 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) 04249 /****************** Bit definition for SDIO_RESP4 register ******************/ 04250 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) 04252 /****************** Bit definition for SDIO_DTIMER register *****************/ 04253 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) 04255 /****************** Bit definition for SDIO_DLEN register *******************/ 04256 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) 04258 /****************** Bit definition for SDIO_DCTRL register ******************/ 04259 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) 04260 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) 04261 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) 04262 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) 04264 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) 04265 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) 04266 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) 04267 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) 04268 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) 04270 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) 04271 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) 04272 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) 04273 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) 04275 /****************** Bit definition for SDIO_DCOUNT register *****************/ 04276 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) 04278 /****************** Bit definition for SDIO_STA register ********************/ 04279 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) 04280 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) 04281 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) 04282 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) 04283 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) 04284 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) 04285 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) 04286 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) 04287 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) 04288 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) 04289 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) 04290 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) 04291 #define SDIO_STA_TXACT ((uint32_t)0x00001000) 04292 #define SDIO_STA_RXACT ((uint32_t)0x00002000) 04293 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) 04294 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) 04295 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) 04296 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) 04297 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) 04298 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) 04299 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) 04300 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) 04301 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) 04302 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) 04304 /******************* Bit definition for SDIO_ICR register *******************/ 04305 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) 04306 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) 04307 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) 04308 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) 04309 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) 04310 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) 04311 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) 04312 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) 04313 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) 04314 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) 04315 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) 04316 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) 04317 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) 04319 /****************** Bit definition for SDIO_MASK register *******************/ 04320 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) 04321 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) 04322 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) 04323 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) 04324 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) 04325 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) 04326 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) 04327 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) 04328 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) 04329 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) 04330 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) 04331 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) 04332 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) 04333 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) 04334 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) 04335 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) 04336 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) 04337 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) 04338 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) 04339 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) 04340 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) 04341 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) 04342 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) 04343 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) 04345 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 04346 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) 04348 /****************** Bit definition for SDIO_FIFO register *******************/ 04349 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) 04351 /******************************************************************************/ 04352 /* */ 04353 /* Serial Peripheral Interface (SPI) */ 04354 /* */ 04355 /******************************************************************************/ 04356 04357 /******************* Bit definition for SPI_CR1 register ********************/ 04358 #define SPI_CR1_CPHA ((uint16_t)0x0001) 04359 #define SPI_CR1_CPOL ((uint16_t)0x0002) 04360 #define SPI_CR1_MSTR ((uint16_t)0x0004) 04362 #define SPI_CR1_BR ((uint16_t)0x0038) 04363 #define SPI_CR1_BR_0 ((uint16_t)0x0008) 04364 #define SPI_CR1_BR_1 ((uint16_t)0x0010) 04365 #define SPI_CR1_BR_2 ((uint16_t)0x0020) 04367 #define SPI_CR1_SPE ((uint16_t)0x0040) 04368 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) 04369 #define SPI_CR1_SSI ((uint16_t)0x0100) 04370 #define SPI_CR1_SSM ((uint16_t)0x0200) 04371 #define SPI_CR1_RXONLY ((uint16_t)0x0400) 04372 #define SPI_CR1_DFF ((uint16_t)0x0800) 04373 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) 04374 #define SPI_CR1_CRCEN ((uint16_t)0x2000) 04375 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) 04376 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) 04378 /******************* Bit definition for SPI_CR2 register ********************/ 04379 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) 04380 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) 04381 #define SPI_CR2_SSOE ((uint8_t)0x04) 04382 #define SPI_CR2_FRF ((uint8_t)0x08) 04383 #define SPI_CR2_ERRIE ((uint8_t)0x20) 04384 #define SPI_CR2_RXNEIE ((uint8_t)0x40) 04385 #define SPI_CR2_TXEIE ((uint8_t)0x80) 04387 /******************** Bit definition for SPI_SR register ********************/ 04388 #define SPI_SR_RXNE ((uint8_t)0x01) 04389 #define SPI_SR_TXE ((uint8_t)0x02) 04390 #define SPI_SR_CHSIDE ((uint8_t)0x04) 04391 #define SPI_SR_UDR ((uint8_t)0x08) 04392 #define SPI_SR_CRCERR ((uint8_t)0x10) 04393 #define SPI_SR_MODF ((uint8_t)0x20) 04394 #define SPI_SR_OVR ((uint8_t)0x40) 04395 #define SPI_SR_BSY ((uint8_t)0x80) 04397 /******************** Bit definition for SPI_DR register ********************/ 04398 #define SPI_DR_DR ((uint16_t)0xFFFF) 04400 /******************* Bit definition for SPI_CRCPR register ******************/ 04401 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) 04403 /****************** Bit definition for SPI_RXCRCR register ******************/ 04404 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) 04406 /****************** Bit definition for SPI_TXCRCR register ******************/ 04407 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) 04409 /****************** Bit definition for SPI_I2SCFGR register *****************/ 04410 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) 04412 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) 04413 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) 04414 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) 04416 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) 04418 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) 04419 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) 04420 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) 04422 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) 04424 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) 04425 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) 04426 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) 04428 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) 04429 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) 04431 /****************** Bit definition for SPI_I2SPR register *******************/ 04432 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) 04433 #define SPI_I2SPR_ODD ((uint16_t)0x0100) 04434 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) 04436 /******************************************************************************/ 04437 /* */ 04438 /* System Configuration (SYSCFG) */ 04439 /* */ 04440 /******************************************************************************/ 04441 /***************** Bit definition for SYSCFG_MEMRMP register ****************/ 04442 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) 04443 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) 04444 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) 04445 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) 04446 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) 04447 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) 04449 /***************** Bit definition for SYSCFG_PMC register *******************/ 04450 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) 04452 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 04453 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) 04454 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) 04455 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) 04456 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) 04461 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) 04462 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) 04463 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) 04464 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) 04465 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) 04466 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) 04467 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) 04468 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) 04473 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) 04474 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) 04475 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) 04476 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) 04477 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) 04478 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) 04479 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) 04480 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) 04485 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) 04486 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) 04487 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) 04488 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) 04489 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) 04490 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) 04491 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) 04492 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) 04497 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) 04498 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) 04499 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) 04500 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) 04501 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) 04502 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) 04503 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) 04505 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 04506 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) 04507 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) 04508 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) 04509 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) 04514 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) 04515 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) 04516 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) 04517 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) 04518 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) 04519 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) 04520 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) 04525 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) 04526 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) 04527 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) 04528 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) 04529 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) 04530 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) 04531 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) 04536 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) 04537 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) 04538 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) 04539 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) 04540 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) 04541 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) 04542 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) 04547 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) 04548 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) 04549 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) 04550 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) 04551 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) 04552 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) 04553 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) 04555 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 04556 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) 04557 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) 04558 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) 04559 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) 04564 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) 04565 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) 04566 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) 04567 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) 04568 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) 04569 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) 04570 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) 04575 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) 04576 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) 04577 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) 04578 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) 04579 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) 04580 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) 04581 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) 04586 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) 04587 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) 04588 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) 04589 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) 04590 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) 04591 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) 04592 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) 04597 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) 04598 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) 04599 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) 04600 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) 04601 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) 04602 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) 04603 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) 04605 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 04606 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) 04607 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) 04608 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) 04609 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) 04614 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) 04615 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) 04616 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) 04617 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) 04618 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) 04619 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) 04620 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) 04625 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) 04626 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) 04627 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) 04628 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) 04629 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) 04630 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) 04631 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) 04636 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) 04637 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) 04638 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) 04639 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) 04640 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) 04641 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) 04642 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) 04647 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) 04648 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) 04649 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) 04650 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) 04651 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) 04652 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) 04653 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) 04655 /******************************************************************************/ 04656 /* */ 04657 /* Routing Interface (RI) */ 04658 /* */ 04659 /******************************************************************************/ 04660 04661 /******************** Bit definition for RI_ICR register ********************/ 04662 #define RI_ICR_IC1Z ((uint32_t)0x0000000F) 04663 #define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) 04664 #define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) 04665 #define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) 04666 #define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) 04668 #define RI_ICR_IC2Z ((uint32_t)0x000000F0) 04669 #define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) 04670 #define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) 04671 #define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) 04672 #define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) 04674 #define RI_ICR_IC3Z ((uint32_t)0x00000F00) 04675 #define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) 04676 #define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) 04677 #define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) 04678 #define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) 04680 #define RI_ICR_IC4Z ((uint32_t)0x0000F000) 04681 #define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) 04682 #define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) 04683 #define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) 04684 #define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) 04686 #define RI_ICR_TIM ((uint32_t)0x00030000) 04687 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) 04688 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) 04690 #define RI_ICR_IC1 ((uint32_t)0x00040000) 04691 #define RI_ICR_IC2 ((uint32_t)0x00080000) 04692 #define RI_ICR_IC3 ((uint32_t)0x00100000) 04693 #define RI_ICR_IC4 ((uint32_t)0x00200000) 04695 /******************** Bit definition for RI_ASCR1 register ********************/ 04696 #define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) 04697 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) 04698 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) 04699 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) 04700 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) 04701 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) 04702 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) 04703 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) 04704 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) 04705 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) 04706 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) 04707 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) 04708 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) 04709 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) 04710 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) 04711 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) 04712 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) 04713 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) 04714 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) 04715 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) 04716 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) 04717 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) 04718 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) 04719 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) 04720 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) 04721 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) 04722 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) 04723 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) 04724 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) 04725 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) 04726 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) 04727 #define RI_ASCR1_SCM ((uint32_t)0x80000000) 04729 /******************** Bit definition for RI_ASCR2 register ********************/ 04730 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) 04731 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) 04732 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) 04733 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) 04734 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) 04735 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) 04736 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) 04737 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) 04738 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) 04739 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) 04740 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) 04741 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) 04742 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) 04743 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) 04744 #define RI_ASCR2_CH1b ((uint32_t)0x00020000) 04745 #define RI_ASCR2_CH2b ((uint32_t)0x00040000) 04746 #define RI_ASCR2_CH3b ((uint32_t)0x00080000) 04747 #define RI_ASCR2_CH6b ((uint32_t)0x00100000) 04748 #define RI_ASCR2_CH7b ((uint32_t)0x00200000) 04749 #define RI_ASCR2_CH8b ((uint32_t)0x00400000) 04750 #define RI_ASCR2_CH9b ((uint32_t)0x00800000) 04751 #define RI_ASCR2_CH10b ((uint32_t)0x01000000) 04752 #define RI_ASCR2_CH11b ((uint32_t)0x02000000) 04753 #define RI_ASCR2_CH12b ((uint32_t)0x04000000) 04754 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) 04755 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) 04756 #define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) 04758 /******************** Bit definition for RI_HYSCR1 register ********************/ 04759 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) 04760 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) 04761 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) 04762 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) 04763 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) 04764 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) 04765 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) 04766 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) 04767 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) 04768 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) 04769 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) 04770 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) 04771 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) 04772 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) 04773 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) 04774 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) 04775 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) 04777 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) 04778 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) 04779 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) 04780 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) 04781 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) 04782 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) 04783 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) 04784 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) 04785 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) 04786 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) 04787 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) 04788 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) 04789 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) 04790 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) 04791 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) 04792 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) 04793 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) 04795 /******************** Bit definition for RI_HYSCR2 register ********************/ 04796 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) 04797 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) 04798 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) 04799 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) 04800 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) 04801 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) 04802 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) 04803 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) 04804 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) 04805 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) 04806 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) 04807 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) 04808 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) 04809 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) 04810 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) 04811 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) 04812 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) 04814 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) 04815 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) 04816 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) 04817 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) 04818 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) 04819 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) 04820 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) 04821 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) 04822 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) 04823 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) 04824 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) 04825 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) 04826 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) 04827 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) 04828 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) 04829 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) 04830 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) 04832 /******************** Bit definition for RI_HYSCR3 register ********************/ 04833 #define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) 04834 #define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) 04835 #define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) 04836 #define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) 04837 #define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) 04838 #define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) 04839 #define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) 04840 #define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) 04841 #define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) 04842 #define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) 04843 #define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) 04844 #define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) 04845 #define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) 04846 #define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) 04847 #define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) 04848 #define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) 04849 #define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) 04851 #define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) 04852 #define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) 04853 #define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) 04854 #define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) 04855 #define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) 04856 #define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) 04857 #define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) 04858 #define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) 04859 #define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) 04860 #define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) 04861 #define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) 04862 #define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) 04863 #define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) 04864 #define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) 04865 #define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) 04866 #define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) 04867 #define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) 04869 /******************** Bit definition for RI_HYSCR4 register ********************/ 04870 #define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) 04871 #define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) 04872 #define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) 04873 #define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) 04874 #define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) 04875 #define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) 04876 #define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) 04877 #define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) 04878 #define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) 04879 #define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) 04880 #define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) 04881 #define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) 04882 #define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) 04883 #define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) 04884 #define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) 04885 #define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) 04886 #define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) 04888 /******************************************************************************/ 04889 /* */ 04890 /* Timers (TIM) */ 04891 /* */ 04892 /******************************************************************************/ 04893 04894 /******************* Bit definition for TIM_CR1 register ********************/ 04895 #define TIM_CR1_CEN ((uint16_t)0x0001) 04896 #define TIM_CR1_UDIS ((uint16_t)0x0002) 04897 #define TIM_CR1_URS ((uint16_t)0x0004) 04898 #define TIM_CR1_OPM ((uint16_t)0x0008) 04899 #define TIM_CR1_DIR ((uint16_t)0x0010) 04901 #define TIM_CR1_CMS ((uint16_t)0x0060) 04902 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) 04903 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) 04905 #define TIM_CR1_ARPE ((uint16_t)0x0080) 04907 #define TIM_CR1_CKD ((uint16_t)0x0300) 04908 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) 04909 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) 04911 /******************* Bit definition for TIM_CR2 register ********************/ 04912 #define TIM_CR2_CCDS ((uint16_t)0x0008) 04914 #define TIM_CR2_MMS ((uint16_t)0x0070) 04915 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) 04916 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) 04917 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) 04919 #define TIM_CR2_TI1S ((uint16_t)0x0080) 04921 /******************* Bit definition for TIM_SMCR register *******************/ 04922 #define TIM_SMCR_SMS ((uint16_t)0x0007) 04923 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) 04924 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) 04925 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) 04927 #define TIM_SMCR_OCCS ((uint16_t)0x0008) 04929 #define TIM_SMCR_TS ((uint16_t)0x0070) 04930 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) 04931 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) 04932 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) 04934 #define TIM_SMCR_MSM ((uint16_t)0x0080) 04936 #define TIM_SMCR_ETF ((uint16_t)0x0F00) 04937 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) 04938 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) 04939 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) 04940 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) 04942 #define TIM_SMCR_ETPS ((uint16_t)0x3000) 04943 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) 04944 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) 04946 #define TIM_SMCR_ECE ((uint16_t)0x4000) 04947 #define TIM_SMCR_ETP ((uint16_t)0x8000) 04949 /******************* Bit definition for TIM_DIER register *******************/ 04950 #define TIM_DIER_UIE ((uint16_t)0x0001) 04951 #define TIM_DIER_CC1IE ((uint16_t)0x0002) 04952 #define TIM_DIER_CC2IE ((uint16_t)0x0004) 04953 #define TIM_DIER_CC3IE ((uint16_t)0x0008) 04954 #define TIM_DIER_CC4IE ((uint16_t)0x0010) 04955 #define TIM_DIER_TIE ((uint16_t)0x0040) 04956 #define TIM_DIER_UDE ((uint16_t)0x0100) 04957 #define TIM_DIER_CC1DE ((uint16_t)0x0200) 04958 #define TIM_DIER_CC2DE ((uint16_t)0x0400) 04959 #define TIM_DIER_CC3DE ((uint16_t)0x0800) 04960 #define TIM_DIER_CC4DE ((uint16_t)0x1000) 04961 #define TIM_DIER_TDE ((uint16_t)0x4000) 04963 /******************** Bit definition for TIM_SR register ********************/ 04964 #define TIM_SR_UIF ((uint16_t)0x0001) 04965 #define TIM_SR_CC1IF ((uint16_t)0x0002) 04966 #define TIM_SR_CC2IF ((uint16_t)0x0004) 04967 #define TIM_SR_CC3IF ((uint16_t)0x0008) 04968 #define TIM_SR_CC4IF ((uint16_t)0x0010) 04969 #define TIM_SR_TIF ((uint16_t)0x0040) 04970 #define TIM_SR_CC1OF ((uint16_t)0x0200) 04971 #define TIM_SR_CC2OF ((uint16_t)0x0400) 04972 #define TIM_SR_CC3OF ((uint16_t)0x0800) 04973 #define TIM_SR_CC4OF ((uint16_t)0x1000) 04975 /******************* Bit definition for TIM_EGR register ********************/ 04976 #define TIM_EGR_UG ((uint8_t)0x01) 04977 #define TIM_EGR_CC1G ((uint8_t)0x02) 04978 #define TIM_EGR_CC2G ((uint8_t)0x04) 04979 #define TIM_EGR_CC3G ((uint8_t)0x08) 04980 #define TIM_EGR_CC4G ((uint8_t)0x10) 04981 #define TIM_EGR_TG ((uint8_t)0x40) 04983 /****************** Bit definition for TIM_CCMR1 register *******************/ 04984 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) 04985 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) 04986 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) 04988 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) 04989 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) 04991 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) 04992 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 04993 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 04994 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 04996 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) 04998 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) 04999 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 05000 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 05002 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) 05003 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) 05005 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) 05006 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 05007 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 05008 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 05010 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) 05012 /*----------------------------------------------------------------------------*/ 05013 05014 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 05015 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 05016 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 05018 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) 05019 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 05020 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 05021 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 05022 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 05024 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 05025 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) 05026 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) 05028 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) 05029 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) 05030 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) 05031 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) 05032 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) 05034 /****************** Bit definition for TIM_CCMR2 register *******************/ 05035 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) 05036 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) 05037 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) 05039 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) 05040 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) 05042 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) 05043 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) 05044 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) 05045 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) 05047 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) 05049 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) 05050 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) 05051 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) 05053 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) 05054 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) 05056 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) 05057 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) 05058 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) 05059 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) 05061 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) 05063 /*----------------------------------------------------------------------------*/ 05064 05065 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) 05066 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) 05067 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) 05069 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) 05070 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) 05071 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) 05072 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) 05073 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) 05075 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) 05076 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) 05077 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) 05079 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) 05080 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) 05081 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) 05082 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) 05083 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) 05085 /******************* Bit definition for TIM_CCER register *******************/ 05086 #define TIM_CCER_CC1E ((uint16_t)0x0001) 05087 #define TIM_CCER_CC1P ((uint16_t)0x0002) 05088 #define TIM_CCER_CC1NP ((uint16_t)0x0008) 05089 #define TIM_CCER_CC2E ((uint16_t)0x0010) 05090 #define TIM_CCER_CC2P ((uint16_t)0x0020) 05091 #define TIM_CCER_CC2NP ((uint16_t)0x0080) 05092 #define TIM_CCER_CC3E ((uint16_t)0x0100) 05093 #define TIM_CCER_CC3P ((uint16_t)0x0200) 05094 #define TIM_CCER_CC3NP ((uint16_t)0x0800) 05095 #define TIM_CCER_CC4E ((uint16_t)0x1000) 05096 #define TIM_CCER_CC4P ((uint16_t)0x2000) 05097 #define TIM_CCER_CC4NP ((uint16_t)0x8000) 05099 /******************* Bit definition for TIM_CNT register ********************/ 05100 #define TIM_CNT_CNT ((uint16_t)0xFFFF) 05102 /******************* Bit definition for TIM_PSC register ********************/ 05103 #define TIM_PSC_PSC ((uint16_t)0xFFFF) 05105 /******************* Bit definition for TIM_ARR register ********************/ 05106 #define TIM_ARR_ARR ((uint16_t)0xFFFF) 05108 /******************* Bit definition for TIM_CCR1 register *******************/ 05109 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) 05111 /******************* Bit definition for TIM_CCR2 register *******************/ 05112 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) 05114 /******************* Bit definition for TIM_CCR3 register *******************/ 05115 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) 05117 /******************* Bit definition for TIM_CCR4 register *******************/ 05118 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) 05120 /******************* Bit definition for TIM_DCR register ********************/ 05121 #define TIM_DCR_DBA ((uint16_t)0x001F) 05122 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) 05123 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) 05124 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) 05125 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) 05126 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) 05128 #define TIM_DCR_DBL ((uint16_t)0x1F00) 05129 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) 05130 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) 05131 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) 05132 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) 05133 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) 05135 /******************* Bit definition for TIM_DMAR register *******************/ 05136 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) 05138 /******************* Bit definition for TIM_OR register *********************/ 05139 #define TIM_OR_TI1RMP ((uint16_t)0x0003) 05140 #define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) 05141 #define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) 05143 /******************************************************************************/ 05144 /* */ 05145 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 05146 /* */ 05147 /******************************************************************************/ 05148 05149 /******************* Bit definition for USART_SR register *******************/ 05150 #define USART_SR_PE ((uint16_t)0x0001) 05151 #define USART_SR_FE ((uint16_t)0x0002) 05152 #define USART_SR_NE ((uint16_t)0x0004) 05153 #define USART_SR_ORE ((uint16_t)0x0008) 05154 #define USART_SR_IDLE ((uint16_t)0x0010) 05155 #define USART_SR_RXNE ((uint16_t)0x0020) 05156 #define USART_SR_TC ((uint16_t)0x0040) 05157 #define USART_SR_TXE ((uint16_t)0x0080) 05158 #define USART_SR_LBD ((uint16_t)0x0100) 05159 #define USART_SR_CTS ((uint16_t)0x0200) 05161 /******************* Bit definition for USART_DR register *******************/ 05162 #define USART_DR_DR ((uint16_t)0x01FF) 05164 /****************** Bit definition for USART_BRR register *******************/ 05165 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) 05166 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) 05168 /****************** Bit definition for USART_CR1 register *******************/ 05169 #define USART_CR1_SBK ((uint16_t)0x0001) 05170 #define USART_CR1_RWU ((uint16_t)0x0002) 05171 #define USART_CR1_RE ((uint16_t)0x0004) 05172 #define USART_CR1_TE ((uint16_t)0x0008) 05173 #define USART_CR1_IDLEIE ((uint16_t)0x0010) 05174 #define USART_CR1_RXNEIE ((uint16_t)0x0020) 05175 #define USART_CR1_TCIE ((uint16_t)0x0040) 05176 #define USART_CR1_TXEIE ((uint16_t)0x0080) 05177 #define USART_CR1_PEIE ((uint16_t)0x0100) 05178 #define USART_CR1_PS ((uint16_t)0x0200) 05179 #define USART_CR1_PCE ((uint16_t)0x0400) 05180 #define USART_CR1_WAKE ((uint16_t)0x0800) 05181 #define USART_CR1_M ((uint16_t)0x1000) 05182 #define USART_CR1_UE ((uint16_t)0x2000) 05183 #define USART_CR1_OVER8 ((uint16_t)0x8000) 05185 /****************** Bit definition for USART_CR2 register *******************/ 05186 #define USART_CR2_ADD ((uint16_t)0x000F) 05187 #define USART_CR2_LBDL ((uint16_t)0x0020) 05188 #define USART_CR2_LBDIE ((uint16_t)0x0040) 05189 #define USART_CR2_LBCL ((uint16_t)0x0100) 05190 #define USART_CR2_CPHA ((uint16_t)0x0200) 05191 #define USART_CR2_CPOL ((uint16_t)0x0400) 05192 #define USART_CR2_CLKEN ((uint16_t)0x0800) 05194 #define USART_CR2_STOP ((uint16_t)0x3000) 05195 #define USART_CR2_STOP_0 ((uint16_t)0x1000) 05196 #define USART_CR2_STOP_1 ((uint16_t)0x2000) 05198 #define USART_CR2_LINEN ((uint16_t)0x4000) 05200 /****************** Bit definition for USART_CR3 register *******************/ 05201 #define USART_CR3_EIE ((uint16_t)0x0001) 05202 #define USART_CR3_IREN ((uint16_t)0x0002) 05203 #define USART_CR3_IRLP ((uint16_t)0x0004) 05204 #define USART_CR3_HDSEL ((uint16_t)0x0008) 05205 #define USART_CR3_NACK ((uint16_t)0x0010) 05206 #define USART_CR3_SCEN ((uint16_t)0x0020) 05207 #define USART_CR3_DMAR ((uint16_t)0x0040) 05208 #define USART_CR3_DMAT ((uint16_t)0x0080) 05209 #define USART_CR3_RTSE ((uint16_t)0x0100) 05210 #define USART_CR3_CTSE ((uint16_t)0x0200) 05211 #define USART_CR3_CTSIE ((uint16_t)0x0400) 05212 #define USART_CR3_ONEBIT ((uint16_t)0x0800) 05214 /****************** Bit definition for USART_GTPR register ******************/ 05215 #define USART_GTPR_PSC ((uint16_t)0x00FF) 05216 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) 05217 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) 05218 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) 05219 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) 05220 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) 05221 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) 05222 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) 05223 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) 05225 #define USART_GTPR_GT ((uint16_t)0xFF00) 05227 /******************************************************************************/ 05228 /* */ 05229 /* Universal Serial Bus (USB) */ 05230 /* */ 05231 /******************************************************************************/ 05232 05234 /******************* Bit definition for USB_EP0R register *******************/ 05235 #define USB_EP0R_EA ((uint16_t)0x000F) 05237 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) 05238 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) 05239 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) 05241 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) 05242 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) 05243 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) 05245 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) 05246 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) 05247 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) 05249 #define USB_EP0R_SETUP ((uint16_t)0x0800) 05251 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) 05252 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) 05253 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) 05255 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) 05256 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) 05258 /******************* Bit definition for USB_EP1R register *******************/ 05259 #define USB_EP1R_EA ((uint16_t)0x000F) 05261 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) 05262 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) 05263 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) 05265 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) 05266 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) 05267 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) 05269 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) 05270 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) 05271 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) 05273 #define USB_EP1R_SETUP ((uint16_t)0x0800) 05275 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) 05276 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) 05277 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) 05279 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) 05280 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) 05282 /******************* Bit definition for USB_EP2R register *******************/ 05283 #define USB_EP2R_EA ((uint16_t)0x000F) 05285 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) 05286 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) 05287 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) 05289 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) 05290 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) 05291 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) 05293 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) 05294 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) 05295 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) 05297 #define USB_EP2R_SETUP ((uint16_t)0x0800) 05299 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) 05300 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) 05301 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) 05303 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) 05304 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) 05306 /******************* Bit definition for USB_EP3R register *******************/ 05307 #define USB_EP3R_EA ((uint16_t)0x000F) 05309 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) 05310 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) 05311 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) 05313 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) 05314 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) 05315 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) 05317 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) 05318 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) 05319 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) 05321 #define USB_EP3R_SETUP ((uint16_t)0x0800) 05323 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) 05324 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) 05325 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) 05327 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) 05328 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) 05330 /******************* Bit definition for USB_EP4R register *******************/ 05331 #define USB_EP4R_EA ((uint16_t)0x000F) 05333 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) 05334 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) 05335 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) 05337 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) 05338 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) 05339 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) 05341 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) 05342 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) 05343 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) 05345 #define USB_EP4R_SETUP ((uint16_t)0x0800) 05347 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) 05348 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) 05349 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) 05351 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) 05352 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) 05354 /******************* Bit definition for USB_EP5R register *******************/ 05355 #define USB_EP5R_EA ((uint16_t)0x000F) 05357 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) 05358 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) 05359 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) 05361 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) 05362 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) 05363 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) 05365 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) 05366 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) 05367 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) 05369 #define USB_EP5R_SETUP ((uint16_t)0x0800) 05371 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) 05372 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) 05373 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) 05375 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) 05376 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) 05378 /******************* Bit definition for USB_EP6R register *******************/ 05379 #define USB_EP6R_EA ((uint16_t)0x000F) 05381 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) 05382 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) 05383 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) 05385 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) 05386 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) 05387 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) 05389 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) 05390 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) 05391 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) 05393 #define USB_EP6R_SETUP ((uint16_t)0x0800) 05395 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) 05396 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) 05397 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) 05399 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) 05400 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) 05402 /******************* Bit definition for USB_EP7R register *******************/ 05403 #define USB_EP7R_EA ((uint16_t)0x000F) 05405 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) 05406 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) 05407 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) 05409 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) 05410 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) 05411 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) 05413 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) 05414 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) 05415 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) 05417 #define USB_EP7R_SETUP ((uint16_t)0x0800) 05419 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) 05420 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) 05421 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) 05423 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) 05424 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) 05427 /******************* Bit definition for USB_CNTR register *******************/ 05428 #define USB_CNTR_FRES ((uint16_t)0x0001) 05429 #define USB_CNTR_PDWN ((uint16_t)0x0002) 05430 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) 05431 #define USB_CNTR_FSUSP ((uint16_t)0x0008) 05432 #define USB_CNTR_RESUME ((uint16_t)0x0010) 05433 #define USB_CNTR_ESOFM ((uint16_t)0x0100) 05434 #define USB_CNTR_SOFM ((uint16_t)0x0200) 05435 #define USB_CNTR_RESETM ((uint16_t)0x0400) 05436 #define USB_CNTR_SUSPM ((uint16_t)0x0800) 05437 #define USB_CNTR_WKUPM ((uint16_t)0x1000) 05438 #define USB_CNTR_ERRM ((uint16_t)0x2000) 05439 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) 05440 #define USB_CNTR_CTRM ((uint16_t)0x8000) 05442 /******************* Bit definition for USB_ISTR register *******************/ 05443 #define USB_ISTR_EP_ID ((uint16_t)0x000F) 05444 #define USB_ISTR_DIR ((uint16_t)0x0010) 05445 #define USB_ISTR_ESOF ((uint16_t)0x0100) 05446 #define USB_ISTR_SOF ((uint16_t)0x0200) 05447 #define USB_ISTR_RESET ((uint16_t)0x0400) 05448 #define USB_ISTR_SUSP ((uint16_t)0x0800) 05449 #define USB_ISTR_WKUP ((uint16_t)0x1000) 05450 #define USB_ISTR_ERR ((uint16_t)0x2000) 05451 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) 05452 #define USB_ISTR_CTR ((uint16_t)0x8000) 05454 /******************* Bit definition for USB_FNR register ********************/ 05455 #define USB_FNR_FN ((uint16_t)0x07FF) 05456 #define USB_FNR_LSOF ((uint16_t)0x1800) 05457 #define USB_FNR_LCK ((uint16_t)0x2000) 05458 #define USB_FNR_RXDM ((uint16_t)0x4000) 05459 #define USB_FNR_RXDP ((uint16_t)0x8000) 05461 /****************** Bit definition for USB_DADDR register *******************/ 05462 #define USB_DADDR_ADD ((uint8_t)0x7F) 05463 #define USB_DADDR_ADD0 ((uint8_t)0x01) 05464 #define USB_DADDR_ADD1 ((uint8_t)0x02) 05465 #define USB_DADDR_ADD2 ((uint8_t)0x04) 05466 #define USB_DADDR_ADD3 ((uint8_t)0x08) 05467 #define USB_DADDR_ADD4 ((uint8_t)0x10) 05468 #define USB_DADDR_ADD5 ((uint8_t)0x20) 05469 #define USB_DADDR_ADD6 ((uint8_t)0x40) 05471 #define USB_DADDR_EF ((uint8_t)0x80) 05473 /****************** Bit definition for USB_BTABLE register ******************/ 05474 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) 05477 /***************** Bit definition for USB_ADDR0_TX register *****************/ 05478 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) 05480 /***************** Bit definition for USB_ADDR1_TX register *****************/ 05481 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) 05483 /***************** Bit definition for USB_ADDR2_TX register *****************/ 05484 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) 05486 /***************** Bit definition for USB_ADDR3_TX register *****************/ 05487 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) 05489 /***************** Bit definition for USB_ADDR4_TX register *****************/ 05490 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) 05492 /***************** Bit definition for USB_ADDR5_TX register *****************/ 05493 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) 05495 /***************** Bit definition for USB_ADDR6_TX register *****************/ 05496 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) 05498 /***************** Bit definition for USB_ADDR7_TX register *****************/ 05499 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) 05501 /*----------------------------------------------------------------------------*/ 05502 05503 /***************** Bit definition for USB_COUNT0_TX register ****************/ 05504 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) 05506 /***************** Bit definition for USB_COUNT1_TX register ****************/ 05507 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) 05509 /***************** Bit definition for USB_COUNT2_TX register ****************/ 05510 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) 05512 /***************** Bit definition for USB_COUNT3_TX register ****************/ 05513 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) 05515 /***************** Bit definition for USB_COUNT4_TX register ****************/ 05516 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) 05518 /***************** Bit definition for USB_COUNT5_TX register ****************/ 05519 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) 05521 /***************** Bit definition for USB_COUNT6_TX register ****************/ 05522 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) 05524 /***************** Bit definition for USB_COUNT7_TX register ****************/ 05525 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) 05527 /*----------------------------------------------------------------------------*/ 05528 05529 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 05530 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) 05532 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 05533 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) 05535 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 05536 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) 05538 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 05539 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) 05541 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 05542 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) 05544 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 05545 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) 05547 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 05548 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) 05550 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 05551 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) 05553 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 05554 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) 05556 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 05557 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) 05559 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 05560 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) 05562 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 05563 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) 05565 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 05566 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) 05568 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 05569 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) 05571 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 05572 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) 05574 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 05575 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) 05577 /*----------------------------------------------------------------------------*/ 05578 05579 /***************** Bit definition for USB_ADDR0_RX register *****************/ 05580 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) 05582 /***************** Bit definition for USB_ADDR1_RX register *****************/ 05583 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) 05585 /***************** Bit definition for USB_ADDR2_RX register *****************/ 05586 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) 05588 /***************** Bit definition for USB_ADDR3_RX register *****************/ 05589 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) 05591 /***************** Bit definition for USB_ADDR4_RX register *****************/ 05592 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) 05594 /***************** Bit definition for USB_ADDR5_RX register *****************/ 05595 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) 05597 /***************** Bit definition for USB_ADDR6_RX register *****************/ 05598 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) 05600 /***************** Bit definition for USB_ADDR7_RX register *****************/ 05601 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) 05603 /*----------------------------------------------------------------------------*/ 05604 05605 /***************** Bit definition for USB_COUNT0_RX register ****************/ 05606 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) 05608 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) 05609 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05610 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05611 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05612 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05613 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05615 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) 05617 /***************** Bit definition for USB_COUNT1_RX register ****************/ 05618 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) 05620 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) 05621 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05622 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05623 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05624 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05625 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05627 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) 05629 /***************** Bit definition for USB_COUNT2_RX register ****************/ 05630 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) 05632 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) 05633 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05634 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05635 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05636 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05637 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05639 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) 05641 /***************** Bit definition for USB_COUNT3_RX register ****************/ 05642 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) 05644 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) 05645 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05646 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05647 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05648 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05649 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05651 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) 05653 /***************** Bit definition for USB_COUNT4_RX register ****************/ 05654 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) 05656 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) 05657 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05658 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05659 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05660 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05661 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05663 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) 05665 /***************** Bit definition for USB_COUNT5_RX register ****************/ 05666 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) 05668 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) 05669 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05670 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05671 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05672 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05673 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05675 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) 05677 /***************** Bit definition for USB_COUNT6_RX register ****************/ 05678 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) 05680 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) 05681 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05682 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05683 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05684 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05685 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05687 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) 05689 /***************** Bit definition for USB_COUNT7_RX register ****************/ 05690 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) 05692 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) 05693 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05694 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05695 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05696 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05697 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05699 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) 05701 /*----------------------------------------------------------------------------*/ 05702 05703 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 05704 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) 05706 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05707 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05708 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05709 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05710 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05711 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05713 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05715 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 05716 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) 05718 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05719 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05720 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05721 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05722 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05723 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05725 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05727 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 05728 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) 05730 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05731 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05732 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05733 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05734 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05735 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05737 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05739 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 05740 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) 05742 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05743 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05744 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05745 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05746 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05747 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05749 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05751 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 05752 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) 05754 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05755 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05756 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05757 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05758 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05759 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05761 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05763 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 05764 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) 05766 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05767 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05768 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05769 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05770 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05771 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05773 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05775 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 05776 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) 05778 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05779 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05780 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05781 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05782 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05783 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05785 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05787 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 05788 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) 05790 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05791 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05792 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05793 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05794 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05795 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05797 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05799 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 05800 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) 05802 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05803 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05804 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05805 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05806 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05807 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05809 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05811 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 05812 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) 05814 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05815 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05816 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05817 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05818 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05819 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05821 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05823 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 05824 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) 05826 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05827 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05828 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05829 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05830 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05831 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05833 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05835 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 05836 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) 05838 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05839 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05840 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05841 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05842 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05843 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05845 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05847 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 05848 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) 05850 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05851 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05852 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05853 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05854 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05855 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05857 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05859 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 05860 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) 05862 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05863 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05864 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05865 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05866 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05867 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05869 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05871 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 05872 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) 05874 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05875 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05876 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05877 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05878 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05879 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05881 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05883 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 05884 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) 05886 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05887 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05888 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05889 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05890 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05891 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05893 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05895 /******************************************************************************/ 05896 /* */ 05897 /* Window WATCHDOG (WWDG) */ 05898 /* */ 05899 /******************************************************************************/ 05900 05901 /******************* Bit definition for WWDG_CR register ********************/ 05902 #define WWDG_CR_T ((uint8_t)0x7F) 05903 #define WWDG_CR_T0 ((uint8_t)0x01) 05904 #define WWDG_CR_T1 ((uint8_t)0x02) 05905 #define WWDG_CR_T2 ((uint8_t)0x04) 05906 #define WWDG_CR_T3 ((uint8_t)0x08) 05907 #define WWDG_CR_T4 ((uint8_t)0x10) 05908 #define WWDG_CR_T5 ((uint8_t)0x20) 05909 #define WWDG_CR_T6 ((uint8_t)0x40) 05911 #define WWDG_CR_WDGA ((uint8_t)0x80) 05913 /******************* Bit definition for WWDG_CFR register *******************/ 05914 #define WWDG_CFR_W ((uint16_t)0x007F) 05915 #define WWDG_CFR_W0 ((uint16_t)0x0001) 05916 #define WWDG_CFR_W1 ((uint16_t)0x0002) 05917 #define WWDG_CFR_W2 ((uint16_t)0x0004) 05918 #define WWDG_CFR_W3 ((uint16_t)0x0008) 05919 #define WWDG_CFR_W4 ((uint16_t)0x0010) 05920 #define WWDG_CFR_W5 ((uint16_t)0x0020) 05921 #define WWDG_CFR_W6 ((uint16_t)0x0040) 05923 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) 05924 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) 05925 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) 05927 #define WWDG_CFR_EWI ((uint16_t)0x0200) 05929 /******************* Bit definition for WWDG_SR register ********************/ 05930 #define WWDG_SR_EWIF ((uint8_t)0x01) 05932 /******************************************************************************/ 05933 /* */ 05934 /* SystemTick (SysTick) */ 05935 /* */ 05936 /******************************************************************************/ 05937 05938 /***************** Bit definition for SysTick_CTRL register *****************/ 05939 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) 05940 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) 05941 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) 05942 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) 05944 /***************** Bit definition for SysTick_LOAD register *****************/ 05945 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) 05947 /***************** Bit definition for SysTick_VAL register ******************/ 05948 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) 05950 /***************** Bit definition for SysTick_CALIB register ****************/ 05951 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) 05952 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) 05953 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) 05955 /******************************************************************************/ 05956 /* */ 05957 /* Nested Vectored Interrupt Controller (NVIC) */ 05958 /* */ 05959 /******************************************************************************/ 05960 05961 /****************** Bit definition for NVIC_ISER register *******************/ 05962 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) 05963 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) 05964 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) 05965 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) 05966 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) 05967 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) 05968 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) 05969 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) 05970 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) 05971 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) 05972 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) 05973 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) 05974 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) 05975 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) 05976 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) 05977 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) 05978 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) 05979 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) 05980 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) 05981 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) 05982 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) 05983 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) 05984 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) 05985 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) 05986 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) 05987 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) 05988 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) 05989 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) 05990 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) 05991 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) 05992 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) 05993 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) 05994 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) 05996 /****************** Bit definition for NVIC_ICER register *******************/ 05997 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) 05998 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) 05999 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) 06000 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) 06001 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) 06002 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) 06003 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) 06004 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) 06005 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) 06006 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) 06007 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) 06008 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) 06009 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) 06010 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) 06011 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) 06012 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) 06013 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) 06014 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) 06015 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) 06016 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) 06017 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) 06018 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) 06019 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) 06020 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) 06021 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) 06022 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) 06023 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) 06024 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) 06025 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) 06026 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) 06027 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) 06028 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) 06029 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) 06031 /****************** Bit definition for NVIC_ISPR register *******************/ 06032 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) 06033 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) 06034 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) 06035 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) 06036 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) 06037 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) 06038 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) 06039 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) 06040 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) 06041 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) 06042 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) 06043 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) 06044 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) 06045 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) 06046 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) 06047 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) 06048 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) 06049 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) 06050 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) 06051 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) 06052 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) 06053 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) 06054 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) 06055 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) 06056 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) 06057 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) 06058 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) 06059 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) 06060 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) 06061 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) 06062 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) 06063 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) 06064 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) 06066 /****************** Bit definition for NVIC_ICPR register *******************/ 06067 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) 06068 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) 06069 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) 06070 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) 06071 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) 06072 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) 06073 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) 06074 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) 06075 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) 06076 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) 06077 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) 06078 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) 06079 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) 06080 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) 06081 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) 06082 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) 06083 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) 06084 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) 06085 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) 06086 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) 06087 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) 06088 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) 06089 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) 06090 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) 06091 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) 06092 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) 06093 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) 06094 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) 06095 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) 06096 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) 06097 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) 06098 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) 06099 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) 06101 /****************** Bit definition for NVIC_IABR register *******************/ 06102 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) 06103 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) 06104 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) 06105 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) 06106 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) 06107 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) 06108 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) 06109 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) 06110 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) 06111 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) 06112 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) 06113 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) 06114 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) 06115 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) 06116 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) 06117 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) 06118 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) 06119 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) 06120 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) 06121 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) 06122 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) 06123 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) 06124 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) 06125 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) 06126 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) 06127 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) 06128 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) 06129 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) 06130 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) 06131 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) 06132 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) 06133 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) 06134 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) 06136 /****************** Bit definition for NVIC_PRI0 register *******************/ 06137 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) 06138 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) 06139 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) 06140 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) 06142 /****************** Bit definition for NVIC_PRI1 register *******************/ 06143 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) 06144 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) 06145 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) 06146 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) 06148 /****************** Bit definition for NVIC_PRI2 register *******************/ 06149 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) 06150 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) 06151 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) 06152 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) 06154 /****************** Bit definition for NVIC_PRI3 register *******************/ 06155 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) 06156 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) 06157 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) 06158 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) 06160 /****************** Bit definition for NVIC_PRI4 register *******************/ 06161 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) 06162 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) 06163 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) 06164 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) 06166 /****************** Bit definition for NVIC_PRI5 register *******************/ 06167 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) 06168 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) 06169 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) 06170 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) 06172 /****************** Bit definition for NVIC_PRI6 register *******************/ 06173 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) 06174 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) 06175 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) 06176 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) 06178 /****************** Bit definition for NVIC_PRI7 register *******************/ 06179 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) 06180 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) 06181 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) 06182 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) 06184 /****************** Bit definition for SCB_CPUID register *******************/ 06185 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) 06186 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) 06187 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) 06188 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) 06189 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) 06191 /******************* Bit definition for SCB_ICSR register *******************/ 06192 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) 06193 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) 06194 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) 06195 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) 06196 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) 06197 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) 06198 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) 06199 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) 06200 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) 06201 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) 06203 /******************* Bit definition for SCB_VTOR register *******************/ 06204 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) 06205 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) 06208 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) 06209 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) 06210 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) 06212 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) 06213 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) 06214 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) 06215 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) 06217 /* prority group configuration */ 06218 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) 06219 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) 06220 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) 06221 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) 06222 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) 06223 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) 06224 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) 06225 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) 06227 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) 06228 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) 06230 /******************* Bit definition for SCB_SCR register ********************/ 06231 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) 06232 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) 06233 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) 06235 /******************** Bit definition for SCB_CCR register *******************/ 06236 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) 06237 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) 06238 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) 06239 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) 06240 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) 06241 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) 06243 /******************* Bit definition for SCB_SHPR register ********************/ 06244 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) 06245 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) 06246 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) 06247 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) 06249 /****************** Bit definition for SCB_SHCSR register *******************/ 06250 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) 06251 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) 06252 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) 06253 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) 06254 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) 06255 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) 06256 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) 06257 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) 06258 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) 06259 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) 06260 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) 06261 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) 06262 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) 06263 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) 06265 /******************* Bit definition for SCB_CFSR register *******************/ 06266 06267 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) 06268 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) 06269 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) 06270 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) 06271 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) 06273 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) 06274 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) 06275 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) 06276 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) 06277 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) 06278 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) 06280 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) 06281 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) 06282 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) 06283 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) 06284 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) 06285 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) 06287 /******************* Bit definition for SCB_HFSR register *******************/ 06288 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) 06289 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) 06290 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) 06292 /******************* Bit definition for SCB_DFSR register *******************/ 06293 #define SCB_DFSR_HALTED ((uint8_t)0x01) 06294 #define SCB_DFSR_BKPT ((uint8_t)0x02) 06295 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) 06296 #define SCB_DFSR_VCATCH ((uint8_t)0x08) 06297 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) 06299 /******************* Bit definition for SCB_MMFAR register ******************/ 06300 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 06302 /******************* Bit definition for SCB_BFAR register *******************/ 06303 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 06305 /******************* Bit definition for SCB_afsr register *******************/ 06306 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) 06315 #ifdef USE_STDPERIPH_DRIVER 06316 #include "stm32l1xx_conf.h" 06317 #endif 06318 06323 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 06324 06325 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 06326 06327 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 06328 06329 #define CLEAR_REG(REG) ((REG) = (0x0)) 06330 06331 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 06332 06333 #define READ_REG(REG) ((REG)) 06334 06335 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 06336 06341 #ifdef __cplusplus 06342 } 06343 #endif 06344 06345 #endif /* __STM32L1XX_H */ 06346 06355 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/