CMSIS Cortex-M3 Core Peripheral Access Layer Header File. More...

#include <stdint.h>
#include <arch/cm3/core_cmInstr.h>
#include <arch/cm3/core_cmFunc.h>

Include dependency graph for core_cm3.h:

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Data Structures
union	APSR_Type
	Union type to access the Application Program Status Register (APSR). More...
union	IPSR_Type
	Union type to access the Interrupt Program Status Register (IPSR). More...
union	xPSR_Type
	Union type to access the Special-Purpose Program Status Registers (xPSR). More...
union	CONTROL_Type
	Union type to access the Control Registers (CONTROL). More...
struct	NVIC_Type
	Structure type to access the Nested Vectored Interrupt Controller (NVIC). More...
struct	SCB_Type
	Structure type to access the System Control Block (SCB). More...
struct	SCnSCB_Type
	Structure type to access the System Control and ID Register not in the SCB. More...
struct	SysTick_Type
	Structure type to access the System Timer (SysTick). More...
struct	ITM_Type
	Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...
struct	DWT_Type
	Structure type to access the Data Watchpoint and Trace Register (DWT). More...
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...
struct	CoreDebug_Type
	Structure type to access the Core Debug Register (CoreDebug). More...
Defines
#define	__CORE_CM3_H_GENERIC
#define	NVIC_STIR_INTID_Pos 0
#define	NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
#define	SCB_CPUID_IMPLEMENTER_Pos 24
#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
#define	SCB_CPUID_VARIANT_Pos 20
#define	SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
#define	SCB_CPUID_ARCHITECTURE_Pos 16
#define	SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
#define	SCB_CPUID_PARTNO_Pos 4
#define	SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
#define	SCB_CPUID_REVISION_Pos 0
#define	SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
#define	SCB_ICSR_NMIPENDSET_Pos 31
#define	SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
#define	SCB_ICSR_PENDSVSET_Pos 28
#define	SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
#define	SCB_ICSR_PENDSVCLR_Pos 27
#define	SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
#define	SCB_ICSR_PENDSTSET_Pos 26
#define	SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
#define	SCB_ICSR_PENDSTCLR_Pos 25
#define	SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
#define	SCB_ICSR_ISRPREEMPT_Pos 23
#define	SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
#define	SCB_ICSR_ISRPENDING_Pos 22
#define	SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
#define	SCB_ICSR_VECTPENDING_Pos 12
#define	SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
#define	SCB_ICSR_RETTOBASE_Pos 11
#define	SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
#define	SCB_ICSR_VECTACTIVE_Pos 0
#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
#define	SCB_VTOR_TBLBASE_Pos 29
#define	SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos)
#define	SCB_VTOR_TBLOFF_Pos 7
#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
#define	SCB_AIRCR_VECTKEY_Pos 16
#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
#define	SCB_AIRCR_VECTKEYSTAT_Pos 16
#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
#define	SCB_AIRCR_ENDIANESS_Pos 15
#define	SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
#define	SCB_AIRCR_PRIGROUP_Pos 8
#define	SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
#define	SCB_AIRCR_SYSRESETREQ_Pos 2
#define	SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1
#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
#define	SCB_AIRCR_VECTRESET_Pos 0
#define	SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
#define	SCB_SCR_SEVONPEND_Pos 4
#define	SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
#define	SCB_SCR_SLEEPDEEP_Pos 2
#define	SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
#define	SCB_SCR_SLEEPONEXIT_Pos 1
#define	SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
#define	SCB_CCR_STKALIGN_Pos 9
#define	SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
#define	SCB_CCR_BFHFNMIGN_Pos 8
#define	SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
#define	SCB_CCR_DIV_0_TRP_Pos 4
#define	SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
#define	SCB_CCR_UNALIGN_TRP_Pos 3
#define	SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
#define	SCB_CCR_USERSETMPEND_Pos 1
#define	SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
#define	SCB_CCR_NONBASETHRDENA_Pos 0
#define	SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
#define	SCB_SHCSR_USGFAULTENA_Pos 18
#define	SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
#define	SCB_SHCSR_BUSFAULTENA_Pos 17
#define	SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
#define	SCB_SHCSR_MEMFAULTENA_Pos 16
#define	SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
#define	SCB_SHCSR_SVCALLPENDED_Pos 15
#define	SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14
#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13
#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
#define	SCB_SHCSR_USGFAULTPENDED_Pos 12
#define	SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
#define	SCB_SHCSR_SYSTICKACT_Pos 11
#define	SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
#define	SCB_SHCSR_PENDSVACT_Pos 10
#define	SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
#define	SCB_SHCSR_MONITORACT_Pos 8
#define	SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
#define	SCB_SHCSR_SVCALLACT_Pos 7
#define	SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
#define	SCB_SHCSR_USGFAULTACT_Pos 3
#define	SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
#define	SCB_SHCSR_BUSFAULTACT_Pos 1
#define	SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
#define	SCB_SHCSR_MEMFAULTACT_Pos 0
#define	SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
#define	SCB_CFSR_USGFAULTSR_Pos 16
#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
#define	SCB_CFSR_BUSFAULTSR_Pos 8
#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
#define	SCB_CFSR_MEMFAULTSR_Pos 0
#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
#define	SCB_HFSR_DEBUGEVT_Pos 31
#define	SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
#define	SCB_HFSR_FORCED_Pos 30
#define	SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
#define	SCB_HFSR_VECTTBL_Pos 1
#define	SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
#define	SCB_DFSR_EXTERNAL_Pos 4
#define	SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
#define	SCB_DFSR_VCATCH_Pos 3
#define	SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
#define	SCB_DFSR_DWTTRAP_Pos 2
#define	SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
#define	SCB_DFSR_BKPT_Pos 1
#define	SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
#define	SCB_DFSR_HALTED_Pos 0
#define	SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos)
#define	SCnSCB_ICTR_INTLINESNUM_Pos 0
#define	SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
#define	SCnSCB_ACTLR_DISFOLD_Pos 2
#define	SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
#define	SCnSCB_ACTLR_DISDEFWBUF_Pos 1
#define	SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
#define	SCnSCB_ACTLR_DISMCYCINT_Pos 0
#define	SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)
#define	SysTick_CTRL_COUNTFLAG_Pos 16
#define	SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
#define	SysTick_CTRL_CLKSOURCE_Pos 2
#define	SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
#define	SysTick_CTRL_TICKINT_Pos 1
#define	SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
#define	SysTick_CTRL_ENABLE_Pos 0
#define	SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos)
#define	SysTick_LOAD_RELOAD_Pos 0
#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
#define	SysTick_VAL_CURRENT_Pos 0
#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
#define	SysTick_CALIB_NOREF_Pos 31
#define	SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
#define	SysTick_CALIB_SKEW_Pos 30
#define	SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
#define	SysTick_CALIB_TENMS_Pos 0
#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
#define	ITM_TPR_PRIVMASK_Pos 0
#define	ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos)
#define	ITM_TCR_BUSY_Pos 23
#define	ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
#define	ITM_TCR_TraceBusID_Pos 16
#define	ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
#define	ITM_TCR_GTSFREQ_Pos 10
#define	ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
#define	ITM_TCR_TSPrescale_Pos 8
#define	ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
#define	ITM_TCR_SWOENA_Pos 4
#define	ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
#define	ITM_TCR_TXENA_Pos 3
#define	ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos)
#define	ITM_TCR_SYNCENA_Pos 2
#define	ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
#define	ITM_TCR_TSENA_Pos 1
#define	ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
#define	ITM_TCR_ITMENA_Pos 0
#define	ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos)
#define	DWT_CTRL_NUMCOMP_Pos 28
#define	DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
#define	DWT_CTRL_NOTRCPKT_Pos 27
#define	DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
#define	DWT_CTRL_NOEXTTRIG_Pos 26
#define	DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
#define	DWT_CTRL_NOCYCCNT_Pos 25
#define	DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
#define	DWT_CTRL_NOPRFCNT_Pos 24
#define	DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
#define	DWT_CTRL_CYCEVTENA_Pos 22
#define	DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
#define	DWT_CTRL_FOLDEVTENA_Pos 21
#define	DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
#define	DWT_CTRL_LSUEVTENA_Pos 20
#define	DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
#define	DWT_CTRL_SLEEPEVTENA_Pos 19
#define	DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
#define	DWT_CTRL_EXCEVTENA_Pos 18
#define	DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
#define	DWT_CTRL_CPIEVTENA_Pos 17
#define	DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
#define	DWT_CTRL_EXCTRCENA_Pos 16
#define	DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
#define	DWT_CTRL_PCSAMPLENA_Pos 12
#define	DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
#define	DWT_CTRL_SYNCTAP_Pos 10
#define	DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
#define	DWT_CTRL_CYCTAP_Pos 9
#define	DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
#define	DWT_CTRL_POSTINIT_Pos 5
#define	DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
#define	DWT_CTRL_POSTPRESET_Pos 1
#define	DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
#define	DWT_CTRL_CYCCNTENA_Pos 0
#define	DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos)
#define	DWT_CPICNT_CPICNT_Pos 0
#define	DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos)
#define	DWT_EXCCNT_EXCCNT_Pos 0
#define	DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos)
#define	DWT_SLEEPCNT_SLEEPCNT_Pos 0
#define	DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos)
#define	DWT_LSUCNT_LSUCNT_Pos 0
#define	DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos)
#define	DWT_FOLDCNT_FOLDCNT_Pos 0
#define	DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos)
#define	DWT_MASK_MASK_Pos 0
#define	DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos)
#define	DWT_FUNCTION_MATCHED_Pos 24
#define	DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
#define	DWT_FUNCTION_DATAVADDR1_Pos 16
#define	DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
#define	DWT_FUNCTION_DATAVADDR0_Pos 12
#define	DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
#define	DWT_FUNCTION_DATAVSIZE_Pos 10
#define	DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
#define	DWT_FUNCTION_LNK1ENA_Pos 9
#define	DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
#define	DWT_FUNCTION_DATAVMATCH_Pos 8
#define	DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
#define	DWT_FUNCTION_CYCMATCH_Pos 7
#define	DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
#define	DWT_FUNCTION_EMITRANGE_Pos 5
#define	DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
#define	DWT_FUNCTION_FUNCTION_Pos 0
#define	DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos)
#define	TPI_ACPR_PRESCALER_Pos 0
#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos)
#define	TPI_SPPR_TXMODE_Pos 0
#define	TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos)
#define	TPI_FFSR_FtNonStop_Pos 3
#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
#define	TPI_FFSR_TCPresent_Pos 2
#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
#define	TPI_FFSR_FtStopped_Pos 1
#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
#define	TPI_FFSR_FlInProg_Pos 0
#define	TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos)
#define	TPI_FFCR_TrigIn_Pos 8
#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
#define	TPI_FFCR_EnFCont_Pos 1
#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
#define	TPI_TRIGGER_TRIGGER_Pos 0
#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos)
#define	TPI_FIFO0_ITM_ATVALID_Pos 29
#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
#define	TPI_FIFO0_ITM_bytecount_Pos 27
#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
#define	TPI_FIFO0_ETM_ATVALID_Pos 26
#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
#define	TPI_FIFO0_ETM_bytecount_Pos 24
#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
#define	TPI_FIFO0_ETM2_Pos 16
#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
#define	TPI_FIFO0_ETM1_Pos 8
#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
#define	TPI_FIFO0_ETM0_Pos 0
#define	TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos)
#define	TPI_ITATBCTR2_ATREADY_Pos 0
#define	TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos)
#define	TPI_FIFO1_ITM_ATVALID_Pos 29
#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
#define	TPI_FIFO1_ITM_bytecount_Pos 27
#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
#define	TPI_FIFO1_ETM_ATVALID_Pos 26
#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
#define	TPI_FIFO1_ETM_bytecount_Pos 24
#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
#define	TPI_FIFO1_ITM2_Pos 16
#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
#define	TPI_FIFO1_ITM1_Pos 8
#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
#define	TPI_FIFO1_ITM0_Pos 0
#define	TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos)
#define	TPI_ITATBCTR0_ATREADY_Pos 0
#define	TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos)
#define	TPI_ITCTRL_Mode_Pos 0
#define	TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos)
#define	TPI_DEVID_NRZVALID_Pos 11
#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
#define	TPI_DEVID_MANCVALID_Pos 10
#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
#define	TPI_DEVID_PTINVALID_Pos 9
#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
#define	TPI_DEVID_MinBufSz_Pos 6
#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
#define	TPI_DEVID_AsynClkIn_Pos 5
#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
#define	TPI_DEVID_NrTraceInput_Pos 0
#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos)
#define	TPI_DEVTYPE_SubType_Pos 0
#define	TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos)
#define	TPI_DEVTYPE_MajorType_Pos 4
#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
#define	CoreDebug_DHCSR_DBGKEY_Pos 16
#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25
#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19
#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
#define	CoreDebug_DHCSR_S_SLEEP_Pos 18
#define	CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
#define	CoreDebug_DHCSR_S_HALT_Pos 17
#define	CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
#define	CoreDebug_DHCSR_S_REGRDY_Pos 16
#define	CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3
#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
#define	CoreDebug_DHCSR_C_STEP_Pos 2
#define	CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
#define	CoreDebug_DHCSR_C_HALT_Pos 1
#define	CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0
#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
#define	CoreDebug_DCRSR_REGWnR_Pos 16
#define	CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
#define	CoreDebug_DCRSR_REGSEL_Pos 0
#define	CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
#define	CoreDebug_DEMCR_TRCENA_Pos 24
#define	CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
#define	CoreDebug_DEMCR_MON_REQ_Pos 19
#define	CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
#define	CoreDebug_DEMCR_MON_STEP_Pos 18
#define	CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
#define	CoreDebug_DEMCR_MON_PEND_Pos 17
#define	CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
#define	CoreDebug_DEMCR_MON_EN_Pos 16
#define	CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10
#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
#define	CoreDebug_DEMCR_VC_INTERR_Pos 9
#define	CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8
#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
#define	CoreDebug_DEMCR_VC_STATERR_Pos 7
#define	CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6
#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5
#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
#define	CoreDebug_DEMCR_VC_MMERR_Pos 4
#define	CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0
#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
#define	SCS_BASE (0xE000E000UL)
#define	ITM_BASE (0xE0000000UL)
#define	DWT_BASE (0xE0001000UL)
#define	TPI_BASE (0xE0040000UL)
#define	CoreDebug_BASE (0xE000EDF0UL)
#define	SysTick_BASE (SCS_BASE + 0x0010UL)
#define	NVIC_BASE (SCS_BASE + 0x0100UL)
#define	SCB_BASE (SCS_BASE + 0x0D00UL)
#define	SCnSCB ((SCnSCB_Type *) SCS_BASE )
#define	SCB ((SCB_Type *) SCB_BASE )
#define	SysTick ((SysTick_Type *) SysTick_BASE )
#define	NVIC ((NVIC_Type *) NVIC_BASE )
#define	ITM ((ITM_Type *) ITM_BASE )
#define	DWT ((DWT_Type *) DWT_BASE )
#define	TPI ((TPI_Type *) TPI_BASE )
#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
#define	NVIC_GetEnableIRQ NVIC_GetActive
#define	ITM_RXBUFFER_EMPTY 0x5AA55AA5
Functions
__STATIC_INLINE void	NVIC_SetPriorityGrouping (uint32_t PriorityGroup)
	Set Priority Grouping.
__STATIC_INLINE uint32_t	NVIC_GetPriorityGrouping (void)
	Get Priority Grouping.
__STATIC_INLINE void	NVIC_EnableIRQ (IRQn_Type IRQn)
	Enable External Interrupt.
__STATIC_INLINE void	NVIC_DisableIRQ (IRQn_Type IRQn)
	Disable External Interrupt.
__STATIC_INLINE uint32_t	NVIC_GetPendingIRQ (IRQn_Type IRQn)
	Get Pending Interrupt.
__STATIC_INLINE void	NVIC_SetPendingIRQ (IRQn_Type IRQn)
	Set Pending Interrupt.
__STATIC_INLINE void	NVIC_ClearPendingIRQ (IRQn_Type IRQn)
	Clear Pending Interrupt.
__STATIC_INLINE uint32_t	NVIC_GetActive (IRQn_Type IRQn)
	Get Active Interrupt.
__STATIC_INLINE void	NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)
	Set Interrupt Priority.
__STATIC_INLINE uint32_t	NVIC_GetPriority (IRQn_Type IRQn)
	Get Interrupt Priority.
__STATIC_INLINE uint32_t	NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
	Encode Priority.
__STATIC_INLINE void	NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t pPreemptPriority, uint32_t pSubPriority)
	Decode Priority.
__STATIC_INLINE void	NVIC_SystemReset (void)
	System Reset.
__STATIC_INLINE uint32_t	SysTick_Config (uint32_t ticks)
	System Tick Configuration.
__STATIC_INLINE uint32_t	ITM_SendChar (uint32_t ch)
	ITM Send Character.
__STATIC_INLINE int32_t	ITM_ReceiveChar (void)
	ITM Receive Character.
__STATIC_INLINE int32_t	ITM_CheckChar (void)
	ITM Check Character.
Variables
volatile int32_t	ITM_RxBuffer
#define	__CM3_CMSIS_VERSION_MAIN (0x03)
#define	__CM3_CMSIS_VERSION_SUB (0x01)
#define	__CM3_CMSIS_VERSION
#define	__CORTEX_M (0x03)
#define	__ASM __asm
#define	__INLINE inline
#define	__STATIC_INLINE static inline
#define	__FPU_USED 0
#define	__CORE_CM3_H_DEPENDANT
#define	__I volatile const
#define	__O volatile
#define	__IO volatile

Detailed Description

CMSIS Cortex-M3 Core Peripheral Access Layer Header File.

Version:: V3.01

Date:: 06. March 2012

Note:: Copyright (C) 2009-2012 ARM Limited. All rights reserved.

: ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

: THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Define Documentation

#define __CORE_CM3_H_GENERIC

#define __CM3_CMSIS_VERSION_MAIN (0x03)

[31:16] CMSIS HAL main version

#define __CM3_CMSIS_VERSION_SUB (0x01)

[15:0] CMSIS HAL sub version

#define __CM3_CMSIS_VERSION

Value:

((__CM3_CMSIS_VERSION_MAIN << 16) | \
                                    __CM3_CMSIS_VERSION_SUB          )

CMSIS HAL version number

#define __CORTEX_M (0x03)

Cortex-M Core

#define __ASM __asm

asm keyword for GNU Compiler

Referenced by __disable_irq(), __DMB(), __DSB(), __enable_irq(), __get_APSR(), __get_CONTROL(), __get_IPSR(), __get_MSP(), __get_PRIMASK(), __get_PSP(), __get_xPSR(), __ISB(), __NOP(), __QADD(), __QADD16(), __QADD8(), __QASX(), __QSAX(), __QSUB(), __QSUB16(), __QSUB8(), __REV(), __REV16(), __REVSH(), __ROR(), __SADD16(), __SADD8(), __SASX(), __SEL(), __set_CONTROL(), __set_MSP(), __set_PRIMASK(), __set_PSP(), __SEV(), __SHADD16(), __SHADD8(), __SHASX(), __SHSAX(), __SHSUB16(), __SHSUB8(), __SMLAD(), __SMLADX(), __SMLSD(), __SMLSDX(), __SMUAD(), __SMUADX(), __SMUSD(), __SMUSDX(), __SSAX(), __SSUB16(), __SSUB8(), __SXTAB16(), __SXTB16(), __UADD16(), __UADD8(), __UASX(), __UHADD16(), __UHADD8(), __UHASX(), __UHSAX(), __UHSUB16(), __UHSUB8(), __UQADD16(), __UQADD8(), __UQASX(), __UQSAX(), __UQSUB16(), __UQSUB8(), __USAD8(), __USADA8(), __USAX(), __USUB16(), __USUB8(), __UXTAB16(), __UXTB16(), __WFE(), and __WFI().

#define __INLINE inline

inline keyword for GNU Compiler

#define __STATIC_INLINE static inline

#define __FPU_USED 0

__FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all

#define __CORE_CM3_H_DEPENDANT

#define __I volatile const

Defines 'read only' permissions

#define __O volatile

Defines 'write only' permissions

#define __IO volatile

Defines 'read / write' permissions

Referenced by CanEnableRx(), CanInput(), FLASH_EraseAllPages(), Get_SerialNum(), GPIO_ETH_MediaInterfaceConfig(), GPIO_EventOutputCmd(), GpioPinConfigGet(), GpioPinConfigSet(), GpioPortConfigSet(), OTGD_FS_Dev_GetEPStatus(), OTGD_FS_Dev_ResetRemoteWakeup(), OTGD_FS_Dev_SetEPStatus(), OTGD_FS_Dev_SetRemoteWakeup(), OTGD_FS_EPActivate(), OTGD_FS_EPClearStall(), OTGD_FS_EPDeactivate(), OTGD_FS_EPSetStall(), OTGD_FS_EPStartXfer(), OTGD_FS_FlushRxFifo(), OTGD_FS_FlushTxFifo(), OTGD_FS_ReadPacket(), OTGD_FS_WritePacket(), RCC_AdjustMSICalibrationValue(), RCC_BackupResetCmd(), RCC_ClearITPendingBit(), RCC_ClockSecuritySystemCmd(), RCC_HSEConfig(), RCC_HSICmd(), RCC_I2SCLKConfig(), RCC_ITConfig(), RCC_LSEConfig(), RCC_LSICmd(), RCC_MCOConfig(), RCC_MSICmd(), RCC_PLLCmd(), RCC_PLLConfig(), RCC_PLLI2SCmd(), RCC_RTCCLKCmd(), RCC_RTCResetCmd(), RCC_USBCLKConfig(), RCC_WaitForHSEStartUp(), Stm32CanHw1Init(), Stm32CanHw2Init(), TIM_SelectOCxM(), and USART_ITConfig().

Data Structures

Defines

Functions

Variables

Detailed Description

Define Documentation