sam3u.h File Reference

Go to the source code of this file.

Data Structures
struct	_AT91S_UDPHS_EPTFIFO
struct	_AT91S_UDPHS_EPT
struct	_AT91S_UDPHS_DMA
struct	_AT91S_UDPHS
Defines
#define	AT91_CAST(a)   (a)
#define	AT91C_GPBR_GPRV   (0x0 << 0)
#define	AT91C_HSMC4_NWE_SETUP   (0x3F << 0)
#define	AT91C_HSMC4_NCS_WR_SETUP   (0x3F << 8)
#define	AT91C_HSMC4_NRD_SETUP   (0x3F << 16)
#define	AT91C_HSMC4_NCS_RD_SETUP   (0x3F << 24)
#define	AT91C_HSMC4_NWE_PULSE   (0x3F << 0)
#define	AT91C_HSMC4_NCS_WR_PULSE   (0x3F << 8)
#define	AT91C_HSMC4_NRD_PULSE   (0x3F << 16)
#define	AT91C_HSMC4_NCS_RD_PULSE   (0x3F << 24)
#define	AT91C_HSMC4_NWE_CYCLE   (0x1FF << 0)
#define	AT91C_HSMC4_NRD_CYCLE   (0x1FF << 16)
#define	AT91C_HSMC4_TCLR   (0xF << 0)
#define	AT91C_HSMC4_TADL   (0xF << 4)
#define	AT91C_HSMC4_TAR   (0xF << 8)
#define	AT91C_HSMC4_OCMSEN   (0x1 << 12)
#define	AT91C_HSMC4_TRR   (0xF << 16)
#define	AT91C_HSMC4_TWB   (0xF << 24)
#define	AT91C_HSMC4_RBNSEL   (0x7 << 28)
#define	AT91C_HSMC4_NFSEL   (0x1 << 31)
#define	AT91C_HSMC4_READ_MODE   (0x1 << 0)
#define	AT91C_HSMC4_WRITE_MODE   (0x1 << 1)
#define	AT91C_HSMC4_EXNW_MODE   (0x3 << 4)
#define	AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE   (0x0 << 4)
#define	AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN   (0x2 << 4)
#define	AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY   (0x3 << 4)
#define	AT91C_HSMC4_BAT   (0x1 << 8)
#define	AT91C_HSMC4_BAT_BYTE_SELECT   (0x0 << 8)
#define	AT91C_HSMC4_BAT_BYTE_WRITE   (0x1 << 8)
#define	AT91C_HSMC4_DBW   (0x3 << 12)
#define	AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS   (0x0 << 12)
#define	AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12)
#define	AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS   (0x2 << 12)
#define	AT91C_HSMC4_TDF_CYCLES   (0xF << 16)
#define	AT91C_HSMC4_TDF_MODE   (0x1 << 20)
#define	AT91C_HSMC4_PMEN   (0x1 << 24)
#define	AT91C_HSMC4_PS   (0x3 << 28)
#define	AT91C_HSMC4_PS_SIZE_FOUR_BYTES   (0x0 << 28)
#define	AT91C_HSMC4_PS_SIZE_EIGHT_BYTES   (0x1 << 28)
#define	AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28)
#define	AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES   (0x3 << 28)
#define	AT91C_HSMC4_PAGESIZE   (0x3 << 0)
#define	AT91C_HSMC4_PAGESIZE_528_Bytes   (0x0)
#define	AT91C_HSMC4_PAGESIZE_1056_Bytes   (0x1)
#define	AT91C_HSMC4_PAGESIZE_2112_Bytes   (0x2)
#define	AT91C_HSMC4_PAGESIZE_4224_Bytes   (0x3)
#define	AT91C_HSMC4_WSPARE   (0x1 << 8)
#define	AT91C_HSMC4_RSPARE   (0x1 << 9)
#define	AT91C_HSMC4_EDGECTRL   (0x1 << 12)
#define	AT91C_HSMC4_RBEDGE   (0x1 << 13)
#define	AT91C_HSMC4_DTOCYC   (0xF << 16)
#define	AT91C_HSMC4_DTOMUL   (0x7 << 20)
#define	AT91C_HSMC4_DTOMUL_1   (0x0 << 20)
#define	AT91C_HSMC4_DTOMUL_16   (0x1 << 20)
#define	AT91C_HSMC4_DTOMUL_128   (0x2 << 20)
#define	AT91C_HSMC4_DTOMUL_256   (0x3 << 20)
#define	AT91C_HSMC4_DTOMUL_1024   (0x4 << 20)
#define	AT91C_HSMC4_DTOMUL_4096   (0x5 << 20)
#define	AT91C_HSMC4_DTOMUL_65536   (0x6 << 20)
#define	AT91C_HSMC4_DTOMUL_1048576   (0x7 << 20)
#define	AT91C_HSMC4_NFCEN   (0x1 << 0)
#define	AT91C_HSMC4_NFCDIS   (0x1 << 1)
#define	AT91C_HSMC4_HOSTEN   (0x1 << 8)
#define	AT91C_HSMC4_HOSTWR   (0x1 << 11)
#define	AT91C_HSMC4_HOSTCSID   (0x7 << 12)
#define	AT91C_HSMC4_HOSTCSID_0   (0x0 << 12)
#define	AT91C_HSMC4_HOSTCSID_1   (0x1 << 12)
#define	AT91C_HSMC4_HOSTCSID_2   (0x2 << 12)
#define	AT91C_HSMC4_HOSTCSID_3   (0x3 << 12)
#define	AT91C_HSMC4_HOSTCSID_4   (0x4 << 12)
#define	AT91C_HSMC4_HOSTCSID_5   (0x5 << 12)
#define	AT91C_HSMC4_HOSTCSID_6   (0x6 << 12)
#define	AT91C_HSMC4_HOSTCSID_7   (0x7 << 12)
#define	AT91C_HSMC4_VALID   (0x1 << 15)
#define	AT91C_HSMC4_NFCSTS   (0x1 << 0)
#define	AT91C_HSMC4_RBRISE   (0x1 << 4)
#define	AT91C_HSMC4_RBFALL   (0x1 << 5)
#define	AT91C_HSMC4_HOSTBUSY   (0x1 << 8)
#define	AT91C_HSMC4_HOSTW   (0x1 << 11)
#define	AT91C_HSMC4_HOSTCS   (0x7 << 12)
#define	AT91C_HSMC4_HOSTCS_0   (0x0 << 12)
#define	AT91C_HSMC4_HOSTCS_1   (0x1 << 12)
#define	AT91C_HSMC4_HOSTCS_2   (0x2 << 12)
#define	AT91C_HSMC4_HOSTCS_3   (0x3 << 12)
#define	AT91C_HSMC4_HOSTCS_4   (0x4 << 12)
#define	AT91C_HSMC4_HOSTCS_5   (0x5 << 12)
#define	AT91C_HSMC4_HOSTCS_6   (0x6 << 12)
#define	AT91C_HSMC4_HOSTCS_7   (0x7 << 12)
#define	AT91C_HSMC4_XFRDONE   (0x1 << 16)
#define	AT91C_HSMC4_CMDDONE   (0x1 << 17)
#define	AT91C_HSMC4_ECCRDY   (0x1 << 18)
#define	AT91C_HSMC4_DTOE   (0x1 << 20)
#define	AT91C_HSMC4_UNDEF   (0x1 << 21)
#define	AT91C_HSMC4_AWB   (0x1 << 22)
#define	AT91C_HSMC4_HASE   (0x1 << 23)
#define	AT91C_HSMC4_RBEDGE0   (0x1 << 24)
#define	AT91C_HSMC4_RBEDGE1   (0x1 << 25)
#define	AT91C_HSMC4_RBEDGE2   (0x1 << 26)
#define	AT91C_HSMC4_RBEDGE3   (0x1 << 27)
#define	AT91C_HSMC4_RBEDGE4   (0x1 << 28)
#define	AT91C_HSMC4_RBEDGE5   (0x1 << 29)
#define	AT91C_HSMC4_RBEDGE6   (0x1 << 30)
#define	AT91C_HSMC4_RBEDGE7   (0x1 << 31)
#define	AT91C_HSMC4_ADDRCYCLE0   (0xFF << 0)
#define	AT91C_BANK   (0x7 << 0)
#define	AT91C_BANK_0   (0x0)
#define	AT91C_BANK_1   (0x1)
#define	AT91C_BANK_2   (0x2)
#define	AT91C_BANK_3   (0x3)
#define	AT91C_BANK_4   (0x4)
#define	AT91C_BANK_5   (0x5)
#define	AT91C_BANK_6   (0x6)
#define	AT91C_BANK_7   (0x7)
#define	AT91C_HSMC4_ECCRESET   (0x1 << 0)
#define	AT91C_ECC_PAGE_SIZE   (0x3 << 0)
#define	AT91C_ECC_TYPCORRECT   (0x3 << 4)
#define	AT91C_ECC_TYPCORRECT_ONE_PER_PAGE   (0x0 << 4)
#define	AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES   (0x1 << 4)
#define	AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES   (0x2 << 4)
#define	AT91C_HSMC4_ECC_RECERR0   (0x1 << 0)
#define	AT91C_HSMC4_ECC_ECCERR0   (0x1 << 1)
#define	AT91C_HSMC4_ECC_MULERR0   (0x1 << 2)
#define	AT91C_HSMC4_ECC_RECERR1   (0x1 << 4)
#define	AT91C_HSMC4_ECC_ECCERR1   (0x1 << 5)
#define	AT91C_HSMC4_ECC_MULERR1   (0x1 << 6)
#define	AT91C_HSMC4_ECC_RECERR2   (0x1 << 8)
#define	AT91C_HSMC4_ECC_ECCERR2   (0x1 << 9)
#define	AT91C_HSMC4_ECC_MULERR2   (0x1 << 10)
#define	AT91C_HSMC4_ECC_RECERR3   (0x1 << 12)
#define	AT91C_HSMC4_ECC_ECCERR3   (0x1 << 13)
#define	AT91C_HSMC4_ECC_MULERR3   (0x1 << 14)
#define	AT91C_HSMC4_ECC_RECERR4   (0x1 << 16)
#define	AT91C_HSMC4_ECC_ECCERR4   (0x1 << 17)
#define	AT91C_HSMC4_ECC_MULERR4   (0x1 << 18)
#define	AT91C_HSMC4_ECC_RECERR5   (0x1 << 20)
#define	AT91C_HSMC4_ECC_ECCERR5   (0x1 << 21)
#define	AT91C_HSMC4_ECC_MULERR5   (0x1 << 22)
#define	AT91C_HSMC4_ECC_RECERR6   (0x1 << 24)
#define	AT91C_HSMC4_ECC_ECCERR6   (0x1 << 25)
#define	AT91C_HSMC4_ECC_MULERR6   (0x1 << 26)
#define	AT91C_HSMC4_ECC_RECERR7   (0x1 << 28)
#define	AT91C_HSMC4_ECC_ECCERR7   (0x1 << 29)
#define	AT91C_HSMC4_ECC_MULERR7   (0x1 << 30)
#define	AT91C_HSMC4_ECC_BITADDR   (0x7 << 0)
#define	AT91C_HSMC4_ECC_WORDADDR   (0xFF << 3)
#define	AT91C_HSMC4_ECC_NPARITY   (0x7FF << 12)
#define	AT91C_HSMC4_ECC_RECERR8   (0x1 << 0)
#define	AT91C_HSMC4_ECC_ECCERR8   (0x1 << 1)
#define	AT91C_HSMC4_ECC_MULERR8   (0x1 << 2)
#define	AT91C_HSMC4_ECC_RECERR9   (0x1 << 4)
#define	AT91C_HSMC4_ECC_ECCERR9   (0x1 << 5)
#define	AT91C_HSMC4_ECC_MULERR9   (0x1 << 6)
#define	AT91C_HSMC4_ECC_RECERR10   (0x1 << 8)
#define	AT91C_HSMC4_ECC_ECCERR10   (0x1 << 9)
#define	AT91C_HSMC4_ECC_MULERR10   (0x1 << 10)
#define	AT91C_HSMC4_ECC_RECERR11   (0x1 << 12)
#define	AT91C_HSMC4_ECC_ECCERR11   (0x1 << 13)
#define	AT91C_HSMC4_ECC_MULERR11   (0x1 << 14)
#define	AT91C_HSMC4_ECC_RECERR12   (0x1 << 16)
#define	AT91C_HSMC4_ECC_ECCERR12   (0x1 << 17)
#define	AT91C_HSMC4_ECC_MULERR12   (0x1 << 18)
#define	AT91C_HSMC4_ECC_RECERR13   (0x1 << 20)
#define	AT91C_HSMC4_ECC_ECCERR13   (0x1 << 21)
#define	AT91C_HSMC4_ECC_MULERR13   (0x1 << 22)
#define	AT91C_HSMC4_ECC_RECERR14   (0x1 << 24)
#define	AT91C_HSMC4_ECC_ECCERR14   (0x1 << 25)
#define	AT91C_HSMC4_ECC_MULERR14   (0x1 << 26)
#define	AT91C_HSMC4_ECC_RECERR15   (0x1 << 28)
#define	AT91C_HSMC4_ECC_ECCERR15   (0x1 << 29)
#define	AT91C_HSMC4_ECC_MULERR15   (0x1 << 30)
#define	AT91C_HSMC4_OCMS_SRSE   (0x1 << 0)
#define	AT91C_HSMC4_OCMS_SMSE   (0x1 << 1)
#define	AT91C_HSMC4_OCMS_KEY1   (0x0 << 0)
#define	AT91C_HSMC4_OCMS_KEY2   (0x0 << 0)
#define	AT91C_HSMC4_WP_EN   (0x1 << 0)
#define	AT91C_HSMC4_WP_KEY   (0xFFFFFF << 8)
#define	AT91C_HSMC4_WP_VS   (0xF << 0)
#define	AT91C_HSMC4_WP_VS_WP_VS0   (0x0)
#define	AT91C_HSMC4_WP_VS_WP_VS1   (0x1)
#define	AT91C_HSMC4_WP_VS_WP_VS2   (0x2)
#define	AT91C_HSMC4_WP_VS_WP_VS3   (0x3)
#define	AT91C_   (0x0 << 8)
#define	AT91C_HSMC4_CMD1   (0xFF << 2)
#define	AT91C_HSMC4_CMD2   (0xFF << 10)
#define	AT91C_HSMC4_VCMD2   (0x1 << 18)
#define	AT91C_HSMC4_ACYCLE   (0x7 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE   (0x0 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE   (0x1 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO   (0x2 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE   (0x3 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR   (0x4 << 19)
#define	AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE   (0x5 << 19)
#define	AT91C_HSMC4_CSID   (0x7 << 22)
#define	AT91C_HSMC4_CSID_0   (0x0 << 22)
#define	AT91C_HSMC4_CSID_1   (0x1 << 22)
#define	AT91C_HSMC4_CSID_2   (0x2 << 22)
#define	AT91C_HSMC4_CSID_3   (0x3 << 22)
#define	AT91C_HSMC4_CSID_4   (0x4 << 22)
#define	AT91C_HSMC4_CSID_5   (0x5 << 22)
#define	AT91C_HSMC4_CSID_6   (0x6 << 22)
#define	AT91C_HSMC4_CSID_7   (0x7 << 22)
#define	AT91C_HSMC4_HOST_EN   (0x1 << 25)
#define	AT91C_HSMC4_HOST_WR   (0x1 << 26)
#define	AT91C_HSMC4_HOSTCMD   (0x1 << 27)
#define	AT91C_MATRIX_ULBT   (0x7 << 0)
#define	AT91C_MATRIX_ULBT_INFINIT_LENGTH   (0x0)
#define	AT91C_MATRIX_ULBT_SINGLE_ACCESS   (0x1)
#define	AT91C_MATRIX_ULBT_4_BEAT   (0x2)
#define	AT91C_MATRIX_ULBT_8_BEAT   (0x3)
#define	AT91C_MATRIX_ULBT_16_BEAT   (0x4)
#define	AT91C_MATRIX_ULBT_32_BEAT   (0x5)
#define	AT91C_MATRIX_ULBT_64_BEAT   (0x6)
#define	AT91C_MATRIX_ULBT_128_BEAT   (0x7)
#define	AT91C_MATRIX_SLOT_CYCLE   (0x1FF << 0)
#define	AT91C_MATRIX_DEFMSTR_TYPE   (0x3 << 16)
#define	AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR   (0x0 << 16)
#define	AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR   (0x1 << 16)
#define	AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR   (0x2 << 16)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG0   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG1   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG2   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG3   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC   (0x0 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG4   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMC   (0x0 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG5   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG6   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG7   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG8   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA   (0x4 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG9   (0x7 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_ARMS   (0x1 << 18)
#define	AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_HDMA   (0x4 << 18)
#define	AT91C_HMATRIX2_VER   (0xF << 0)
#define	AT91C_NVIC_INTLINESNUM   (0xF << 0)
#define	AT91C_NVIC_INTLINESNUM_32   (0x0)
#define	AT91C_NVIC_INTLINESNUM_64   (0x1)
#define	AT91C_NVIC_INTLINESNUM_96   (0x2)
#define	AT91C_NVIC_INTLINESNUM_128   (0x3)
#define	AT91C_NVIC_INTLINESNUM_160   (0x4)
#define	AT91C_NVIC_INTLINESNUM_192   (0x5)
#define	AT91C_NVIC_INTLINESNUM_224   (0x6)
#define	AT91C_NVIC_INTLINESNUM_256   (0x7)
#define	AT91C_NVIC_INTLINESNUM_288   (0x8)
#define	AT91C_NVIC_INTLINESNUM_320   (0x9)
#define	AT91C_NVIC_INTLINESNUM_352   (0xA)
#define	AT91C_NVIC_INTLINESNUM_384   (0xB)
#define	AT91C_NVIC_INTLINESNUM_416   (0xC)
#define	AT91C_NVIC_INTLINESNUM_448   (0xD)
#define	AT91C_NVIC_INTLINESNUM_480   (0xE)
#define	AT91C_NVIC_INTLINESNUM_496   (0xF)
#define	AT91C_NVIC_STICKENABLE   (0x1 << 0)
#define	AT91C_NVIC_STICKINT   (0x1 << 1)
#define	AT91C_NVIC_STICKCLKSOURCE   (0x1 << 2)
#define	AT91C_NVIC_STICKCOUNTFLAG   (0x1 << 16)
#define	AT91C_NVIC_STICKRELOAD   (0xFFFFFF << 0)
#define	AT91C_NVIC_STICKCURRENT   (0x7FFFFFFF << 0)
#define	AT91C_NVIC_STICKTENMS   (0xFFFFFF << 0)
#define	AT91C_NVIC_STICKSKEW   (0x1 << 30)
#define	AT91C_NVIC_STICKNOREF   (0x1 << 31)
#define	AT91C_NVIC_PRI_N   (0xFF << 0)
#define	AT91C_NVIC_PRI_N1   (0xFF << 8)
#define	AT91C_NVIC_PRI_N2   (0xFF << 16)
#define	AT91C_NVIC_PRI_N3   (0xFF << 24)
#define	AT91C_NVIC_REVISION   (0xF << 0)
#define	AT91C_NVIC_PARTNO   (0xFFF << 4)
#define	AT91C_NVIC_CONSTANT   (0xF << 16)
#define	AT91C_NVIC_VARIANT   (0xF << 20)
#define	AT91C_NVIC_IMPLEMENTER   (0xFF << 24)
#define	AT91C_NVIC_VECTACTIVE   (0x1FF << 0)
#define	AT91C_NVIC_RETTOBASE   (0x1 << 11)
#define	AT91C_NVIC_VECTPENDING   (0x1FF << 12)
#define	AT91C_NVIC_ISRPENDING   (0x1 << 22)
#define	AT91C_NVIC_ISRPREEMPT   (0x1 << 23)
#define	AT91C_NVIC_PENDSTCLR   (0x1 << 25)
#define	AT91C_NVIC_PENDSTSET   (0x1 << 26)
#define	AT91C_NVIC_PENDSVCLR   (0x1 << 27)
#define	AT91C_NVIC_PENDSVSET   (0x1 << 28)
#define	AT91C_NVIC_NMIPENDSET   (0x1 << 31)
#define	AT91C_NVIC_TBLOFF   (0x3FFFFF << 7)
#define	AT91C_NVIC_TBLBASE   (0x1 << 29)
#define	AT91C_NVIC_TBLBASE_CODE   (0x0 << 29)
#define	AT91C_NVIC_TBLBASE_RAM   (0x1 << 29)
#define	AT91C_NVIC_VECTRESET   (0x1 << 0)
#define	AT91C_NVIC_VECTCLRACTIVE   (0x1 << 1)
#define	AT91C_NVIC_SYSRESETREQ   (0x1 << 2)
#define	AT91C_NVIC_PRIGROUP   (0x7 << 8)
#define	AT91C_NVIC_PRIGROUP_0   (0x0 << 8)
#define	AT91C_NVIC_PRIGROUP_1   (0x1 << 8)
#define	AT91C_NVIC_PRIGROUP_2   (0x2 << 8)
#define	AT91C_NVIC_PRIGROUP_3   (0x3 << 8)
#define	AT91C_NVIC_PRIGROUP_4   (0x4 << 8)
#define	AT91C_NVIC_PRIGROUP_5   (0x5 << 8)
#define	AT91C_NVIC_PRIGROUP_6   (0x6 << 8)
#define	AT91C_NVIC_PRIGROUP_7   (0x7 << 8)
#define	AT91C_NVIC_ENDIANESS   (0x1 << 15)
#define	AT91C_NVIC_VECTKEY   (0xFFFF << 16)
#define	AT91C_NVIC_SLEEPONEXIT   (0x1 << 1)
#define	AT91C_NVIC_SLEEPDEEP   (0x1 << 2)
#define	AT91C_NVIC_SEVONPEND   (0x1 << 4)
#define	AT91C_NVIC_NONEBASETHRDENA   (0x1 << 0)
#define	AT91C_NVIC_USERSETMPEND   (0x1 << 1)
#define	AT91C_NVIC_UNALIGN_TRP   (0x1 << 3)
#define	AT91C_NVIC_DIV_0_TRP   (0x1 << 4)
#define	AT91C_NVIC_BFHFNMIGN   (0x1 << 8)
#define	AT91C_NVIC_STKALIGN   (0x1 << 9)
#define	AT91C_NVIC_PRI_4   (0xFF << 0)
#define	AT91C_NVIC_PRI_5   (0xFF << 8)
#define	AT91C_NVIC_PRI_6   (0xFF << 16)
#define	AT91C_NVIC_PRI_7   (0xFF << 24)
#define	AT91C_NVIC_PRI_8   (0xFF << 0)
#define	AT91C_NVIC_PRI_9   (0xFF << 8)
#define	AT91C_NVIC_PRI_10   (0xFF << 16)
#define	AT91C_NVIC_PRI_11   (0xFF << 24)
#define	AT91C_NVIC_PRI_12   (0xFF << 0)
#define	AT91C_NVIC_PRI_13   (0xFF << 8)
#define	AT91C_NVIC_PRI_14   (0xFF << 16)
#define	AT91C_NVIC_PRI_15   (0xFF << 24)
#define	AT91C_NVIC_MEMFAULTACT   (0x1 << 0)
#define	AT91C_NVIC_BUSFAULTACT   (0x1 << 1)
#define	AT91C_NVIC_USGFAULTACT   (0x1 << 3)
#define	AT91C_NVIC_SVCALLACT   (0x1 << 7)
#define	AT91C_NVIC_MONITORACT   (0x1 << 8)
#define	AT91C_NVIC_PENDSVACT   (0x1 << 10)
#define	AT91C_NVIC_SYSTICKACT   (0x1 << 11)
#define	AT91C_NVIC_USGFAULTPENDED   (0x1 << 12)
#define	AT91C_NVIC_MEMFAULTPENDED   (0x1 << 13)
#define	AT91C_NVIC_BUSFAULTPENDED   (0x1 << 14)
#define	AT91C_NVIC_SVCALLPENDED   (0x1 << 15)
#define	AT91C_NVIC_MEMFAULTENA   (0x1 << 16)
#define	AT91C_NVIC_BUSFAULTENA   (0x1 << 17)
#define	AT91C_NVIC_USGFAULTENA   (0x1 << 18)
#define	AT91C_NVIC_MEMMANAGE   (0xFF << 0)
#define	AT91C_NVIC_BUSFAULT   (0xFF << 8)
#define	AT91C_NVIC_USAGEFAULT   (0xFF << 16)
#define	AT91C_NVIC_IBUSERR   (0x1 << 0)
#define	AT91C_NVIC_PRECISERR   (0x1 << 1)
#define	AT91C_NVIC_IMPRECISERR   (0x1 << 2)
#define	AT91C_NVIC_UNSTKERR   (0x1 << 3)
#define	AT91C_NVIC_STKERR   (0x1 << 4)
#define	AT91C_NVIC_BFARVALID   (0x1 << 7)
#define	AT91C_NVIC_ID_PFR0_0   (0xF << 0)
#define	AT91C_NVIC_ID_PRF0_1   (0xF << 4)
#define	AT91C_NVIC_ID_PRF1_MODEL   (0xF << 8)
#define	AT91C_NVIC_ID_DFR0_MODEL   (0xF << 20)
#define	AT91C_NVIC_ID_MMFR0_PMSA   (0xF << 4)
#define	AT91C_NVIC_ID_MMFR0_CACHE   (0xF << 8)
#define	AT91C_MPU_SEPARATE   (0x1 << 0)
#define	AT91C_MPU_DREGION   (0xFF << 8)
#define	AT91C_MPU_IREGION   (0xFF << 16)
#define	AT91C_MPU_ENABLE   (0x1 << 0)
#define	AT91C_MPU_HFNMIENA   (0x1 << 1)
#define	AT91C_MPU_PRIVDEFENA   (0x1 << 2)
#define	AT91C_MPU_REGION   (0xFF << 0)
#define	AT91C_MPU_REG   (0xF << 0)
#define	AT91C_MPU_VALID   (0x1 << 4)
#define	AT91C_MPU_ADDR   (0x3FFFFFF << 5)
#define	AT91C_MPU_ENA   (0x1 << 0)
#define	AT91C_MPU_SIZE   (0xF << 1)
#define	AT91C_MPU_SRD   (0xFF << 8)
#define	AT91C_MPU_B   (0x1 << 16)
#define	AT91C_MPU_C   (0x1 << 17)
#define	AT91C_MPU_S   (0x1 << 18)
#define	AT91C_MPU_TEX   (0x7 << 19)
#define	AT91C_MPU_AP   (0x7 << 24)
#define	AT91C_MPU_XN   (0x7 << 28)
#define	AT91C_CM3_SYSRESETREQ   (0x1 << 2)
#define	AT91C_CM3_SLEEPONEXIT   (0x1 << 1)
#define	AT91C_CM3_SLEEPDEEP   (0x1 << 2)
#define	AT91C_CM3_SEVONPEND   (0x1 << 4)
#define	AT91C_CM3_SYSTICKACT   (0x1 << 11)
#define	AT91C_PDC_RXTEN   (0x1 << 0)
#define	AT91C_PDC_RXTDIS   (0x1 << 1)
#define	AT91C_PDC_TXTEN   (0x1 << 8)
#define	AT91C_PDC_TXTDIS   (0x1 << 9)
#define	AT91C_DBGU_RSTRX   (0x1 << 2)
#define	AT91C_DBGU_RSTTX   (0x1 << 3)
#define	AT91C_DBGU_RXEN   (0x1 << 4)
#define	AT91C_DBGU_RXDIS   (0x1 << 5)
#define	AT91C_DBGU_TXEN   (0x1 << 6)
#define	AT91C_DBGU_TXDIS   (0x1 << 7)
#define	AT91C_DBGU_RSTSTA   (0x1 << 8)
#define	AT91C_DBGU_PAR   (0x7 << 9)
#define	AT91C_DBGU_PAR_EVEN   (0x0 << 9)
#define	AT91C_DBGU_PAR_ODD   (0x1 << 9)
#define	AT91C_DBGU_PAR_SPACE   (0x2 << 9)
#define	AT91C_DBGU_PAR_MARK   (0x3 << 9)
#define	AT91C_DBGU_PAR_NONE   (0x4 << 9)
#define	AT91C_DBGU_CHMODE   (0x3 << 14)
#define	AT91C_DBGU_CHMODE_NORMAL   (0x0 << 14)
#define	AT91C_DBGU_CHMODE_AUTO   (0x1 << 14)
#define	AT91C_DBGU_CHMODE_LOCAL   (0x2 << 14)
#define	AT91C_DBGU_CHMODE_REMOTE   (0x3 << 14)
#define	AT91C_DBGU_RXRDY   (0x1 << 0)
#define	AT91C_DBGU_TXRDY   (0x1 << 1)
#define	AT91C_DBGU_ENDRX   (0x1 << 3)
#define	AT91C_DBGU_ENDTX   (0x1 << 4)
#define	AT91C_DBGU_OVRE   (0x1 << 5)
#define	AT91C_DBGU_FRAME   (0x1 << 6)
#define	AT91C_DBGU_PARE   (0x1 << 7)
#define	AT91C_DBGU_TXEMPTY   (0x1 << 9)
#define	AT91C_DBGU_TXBUFE   (0x1 << 11)
#define	AT91C_DBGU_RXBUFF   (0x1 << 12)
#define	AT91C_DBGU_COMM_TX   (0x1 << 30)
#define	AT91C_DBGU_COMM_RX   (0x1 << 31)
#define	AT91C_DBGU_FORCE_NTRST   (0x1 << 0)
#define	AT91C_PIO_KCE   (0x1 << 0)
#define	AT91C_PIO_NBR   (0x7 << 0)
#define	AT91C_PIO_NBC   (0x7 << 8)
#define	AT91C_PIO_DBC   (0x3FF << 0)
#define	AT91C_PIO_KPR   (0x1 << 0)
#define	AT91C_PIO_KRL   (0x1 << 1)
#define	AT91C_PIO_NBKPR   (0x3 << 8)
#define	AT91C_PIO_NBKRL   (0x3 << 16)
#define	AT91C_KEY0ROW   (0x7 << 0)
#define	AT91C_KEY0COL   (0x7 << 4)
#define	AT91C_KEY1ROW   (0x7 << 8)
#define	AT91C_KEY1COL   (0x7 << 12)
#define	AT91C_KEY2ROW   (0x7 << 16)
#define	AT91C_KEY2COL   (0x7 << 20)
#define	AT91C_KEY3ROW   (0x7 << 24)
#define	AT91C_KEY3COL   (0x7 << 28)
#define	AT91C_PMC_PCK   (0x1 << 0)
#define	AT91C_PMC_PCK0   (0x1 << 8)
#define	AT91C_PMC_PCK1   (0x1 << 9)
#define	AT91C_PMC_PCK2   (0x1 << 10)
#define	AT91C_CKGR_UPLLEN   (0x1 << 16)
#define	AT91C_CKGR_UPLLEN_DISABLED   (0x0 << 16)
#define	AT91C_CKGR_UPLLEN_ENABLED   (0x1 << 16)
#define	AT91C_CKGR_UPLLCOUNT   (0xF << 20)
#define	AT91C_CKGR_BIASEN   (0x1 << 24)
#define	AT91C_CKGR_BIASEN_DISABLED   (0x0 << 24)
#define	AT91C_CKGR_BIASEN_ENABLED   (0x1 << 24)
#define	AT91C_CKGR_BIASCOUNT   (0xF << 28)
#define	AT91C_CKGR_MOSCXTEN   (0x1 << 0)
#define	AT91C_CKGR_MOSCXTBY   (0x1 << 1)
#define	AT91C_CKGR_WAITMODE   (0x1 << 2)
#define	AT91C_CKGR_MOSCRCEN   (0x1 << 3)
#define	AT91C_CKGR_MOSCRCF   (0x7 << 4)
#define	AT91C_CKGR_MOSCXTST   (0xFF << 8)
#define	AT91C_CKGR_KEY   (0xFF << 16)
#define	AT91C_CKGR_MOSCSEL   (0x1 << 24)
#define	AT91C_CKGR_CFDEN   (0x1 << 25)
#define	AT91C_CKGR_MAINF   (0xFFFF << 0)
#define	AT91C_CKGR_MAINRDY   (0x1 << 16)
#define	AT91C_CKGR_DIVA   (0xFF << 0)
#define	AT91C_CKGR_DIVA_0   (0x0)
#define	AT91C_CKGR_DIVA_BYPASS   (0x1)
#define	AT91C_CKGR_PLLACOUNT   (0x3F << 8)
#define	AT91C_CKGR_STMODE   (0x3 << 14)
#define	AT91C_CKGR_STMODE_0   (0x0 << 14)
#define	AT91C_CKGR_STMODE_1   (0x1 << 14)
#define	AT91C_CKGR_STMODE_2   (0x2 << 14)
#define	AT91C_CKGR_STMODE_3   (0x3 << 14)
#define	AT91C_CKGR_MULA   (0x7FF << 16)
#define	AT91C_CKGR_SRC   (0x1 << 29)
#define	AT91C_PMC_CSS   (0x7 << 0)
#define	AT91C_PMC_CSS_SLOW_CLK   (0x0)
#define	AT91C_PMC_CSS_MAIN_CLK   (0x1)
#define	AT91C_PMC_CSS_PLLA_CLK   (0x2)
#define	AT91C_PMC_CSS_UPLL_CLK   (0x3)
#define	AT91C_PMC_CSS_SYS_CLK   (0x4)
#define	AT91C_PMC_PRES   (0x7 << 4)
#define	AT91C_PMC_PRES_CLK   (0x0 << 4)
#define	AT91C_PMC_PRES_CLK_2   (0x1 << 4)
#define	AT91C_PMC_PRES_CLK_4   (0x2 << 4)
#define	AT91C_PMC_PRES_CLK_8   (0x3 << 4)
#define	AT91C_PMC_PRES_CLK_16   (0x4 << 4)
#define	AT91C_PMC_PRES_CLK_32   (0x5 << 4)
#define	AT91C_PMC_PRES_CLK_64   (0x6 << 4)
#define	AT91C_PMC_PRES_CLK_6   (0x7 << 4)
#define	AT91C_PMC_MOSCXTS   (0x1 << 0)
#define	AT91C_PMC_LOCKA   (0x1 << 1)
#define	AT91C_PMC_MCKRDY   (0x1 << 3)
#define	AT91C_PMC_LOCKU   (0x1 << 6)
#define	AT91C_PMC_PCKRDY0   (0x1 << 8)
#define	AT91C_PMC_PCKRDY1   (0x1 << 9)
#define	AT91C_PMC_PCKRDY2   (0x1 << 10)
#define	AT91C_PMC_MOSCSELS   (0x1 << 16)
#define	AT91C_PMC_MOSCRCS   (0x1 << 17)
#define	AT91C_PMC_CFDEV   (0x1 << 18)
#define	AT91C_PMC_OSCSELS   (0x1 << 7)
#define	AT91C_PMC_CFDS   (0x1 << 19)
#define	AT91C_PMC_FOS   (0x1 << 20)
#define	AT91C_PMC_FSTT   (0xFFFF << 0)
#define	AT91C_PMC_RTTAL   (0x1 << 16)
#define	AT91C_PMC_RTCAL   (0x1 << 17)
#define	AT91C_PMC_USBAL   (0x1 << 18)
#define	AT91C_PMC_LPM   (0x1 << 20)
#define	AT91C_PMC_FSTP   (0xFFFF << 0)
#define	AT91C_PMC_FOCLR   (0x1 << 0)
#define	AT91C_RSTC_PROCRST   (0x1 << 0)
#define	AT91C_RSTC_ICERST   (0x1 << 1)
#define	AT91C_RSTC_PERRST   (0x1 << 2)
#define	AT91C_RSTC_EXTRST   (0x1 << 3)
#define	AT91C_RSTC_KEY   (0xFF << 24)
#define	AT91C_RSTC_URSTS   (0x1 << 0)
#define	AT91C_RSTC_RSTTYP   (0x7 << 8)
#define	AT91C_RSTC_RSTTYP_GENERAL   (0x0 << 8)
#define	AT91C_RSTC_RSTTYP_WAKEUP   (0x1 << 8)
#define	AT91C_RSTC_RSTTYP_WATCHDOG   (0x2 << 8)
#define	AT91C_RSTC_RSTTYP_SOFTWARE   (0x3 << 8)
#define	AT91C_RSTC_RSTTYP_USER   (0x4 << 8)
#define	AT91C_RSTC_NRSTL   (0x1 << 16)
#define	AT91C_RSTC_SRCMP   (0x1 << 17)
#define	AT91C_RSTC_URSTEN   (0x1 << 0)
#define	AT91C_RSTC_URSTIEN   (0x1 << 4)
#define	AT91C_RSTC_ERSTL   (0xF << 8)
#define	AT91C_SUPC_CR_VROFF   (0x1 << 2)
#define	AT91C_SUPC_CR_VROFF_NO_EFFECT   (0x0 << 2)
#define	AT91C_SUPC_CR_VROFF_STOP_VREG   (0x1 << 2)
#define	AT91C_SUPC_CR_XTALSEL   (0x1 << 3)
#define	AT91C_SUPC_CR_XTALSEL_NO_EFFECT   (0x0 << 3)
#define	AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL   (0x1 << 3)
#define	AT91C_SUPC_CR_KEY   (0xff << 24)
#define	AT91C_SUPC_SMMR_SMTH   (0xf << 0)
#define	AT91C_SUPC_SMMR_SMTH_1_9V   (0x0 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_0V   (0x1 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_1V   (0x2 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_2V   (0x3 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_3V   (0x4 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_4V   (0x5 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_5V   (0x6 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_6V   (0x7 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_7V   (0x8 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_8V   (0x9 << 0)
#define	AT91C_SUPC_SMMR_SMTH_2_9V   (0xA << 0)
#define	AT91C_SUPC_SMMR_SMTH_3_0V   (0xB << 0)
#define	AT91C_SUPC_SMMR_SMTH_3_1V   (0xC << 0)
#define	AT91C_SUPC_SMMR_SMTH_3_2V   (0xD << 0)
#define	AT91C_SUPC_SMMR_SMTH_3_3V   (0xE << 0)
#define	AT91C_SUPC_SMMR_SMTH_3_4V   (0xF << 0)
#define	AT91C_SUPC_SMMR_SMSMPL   (0x7 << 8)
#define	AT91C_SUPC_SMMR_SMSMPL_SMD   (0x0 << 8)
#define	AT91C_SUPC_SMMR_SMSMPL_CSM   (0x1 << 8)
#define	AT91C_SUPC_SMMR_SMSMPL_32SLCK   (0x2 << 8)
#define	AT91C_SUPC_SMMR_SMSMPL_256SLCK   (0x3 << 8)
#define	AT91C_SUPC_SMMR_SMSMPL_2048SLCK   (0x4 << 8)
#define	AT91C_SUPC_SMMR_SMRSTEN   (0x1 << 12)
#define	AT91C_SUPC_SMMR_SMRSTEN_NOT_ENABLE   (0x0 << 12)
#define	AT91C_SUPC_SMMR_SMRSTEN_ENABLE   (0x1 << 12)
#define	AT91C_SUPC_SMMR_SMIEN   (0x1 << 13)
#define	AT91C_SUPC_SMMR_SMIEN_NOT_ENABLE   (0x0 << 13)
#define	AT91C_SUPC_SMMR_SMIEN_ENABLE   (0x1 << 13)
#define	AT91C_SUPC_MR_BODRSTEN   (0x1 << 12)
#define	AT91C_SUPC_MR_BODRSTEN_NOT_ENABLE   (0x0 << 12)
#define	AT91C_SUPC_MR_BODRSTEN_ENABLE   (0x1 << 12)
#define	AT91C_SUPC_MR_BODDIS   (0x1 << 13)
#define	AT91C_SUPC_MR_BODDIS_ENABLE   (0x0 << 13)
#define	AT91C_SUPC_MR_BODDIS_DISABLE   (0x1 << 13)
#define	AT91C_SUPC_MR_VDDIORDY   (0x1 << 14)
#define	AT91C_SUPC_MR_VDDIORDY_VDDIO_REMOVED   (0x0 << 14)
#define	AT91C_SUPC_MR_VDDIORDY_VDDIO_PRESENT   (0x1 << 14)
#define	AT91C_SUPC_MR_OSCBYPASS   (0x1 << 20)
#define	AT91C_SUPC_MR_OSCBYPASS_NO_EFFECT   (0x0 << 20)
#define	AT91C_SUPC_MR_OSCBYPASS_BYPASS   (0x1 << 20)
#define	AT91C_SUPC_MR_KEY   (0xff << 24)
#define	AT91C_SUPC_WUMR_FWUPEN   (0x1 << 0)
#define	AT91C_SUPC_WUMR_FWUPEN_NOT_ENABLE   (0x0 << 0)
#define	AT91C_SUPC_WUMR_FWUPEN_ENABLE   (0x1 << 0)
#define	AT91C_SUPC_WUMR_SMEN   (0x1 << 1)
#define	AT91C_SUPC_WUMR_SMEN_NOT_ENABLE   (0x0 << 1)
#define	AT91C_SUPC_WUMR_SMEN_ENABLE   (0x1 << 1)
#define	AT91C_SUPC_WUMR_RTTEN   (0x1 << 2)
#define	AT91C_SUPC_WUMR_RTTEN_NOT_ENABLE   (0x0 << 2)
#define	AT91C_SUPC_WUMR_RTTEN_ENABLE   (0x1 << 2)
#define	AT91C_SUPC_WUMR_RTCEN   (0x1 << 3)
#define	AT91C_SUPC_WUMR_RTCEN_NOT_ENABLE   (0x0 << 3)
#define	AT91C_SUPC_WUMR_RTCEN_ENABLE   (0x1 << 3)
#define	AT91C_SUPC_WUMR_FWUPDBC   (0x7 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_1SCLK   (0x0 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_3SCLK   (0x1 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_32SCLK   (0x2 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_512SCLK   (0x3 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_4096SCLK   (0x4 << 8)
#define	AT91C_SUPC_WUMR_FWUPDBC_32768SCLK   (0x5 << 8)
#define	AT91C_SUPC_WUMR_WKUPDBC   (0x7 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_1SCLK   (0x0 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_3SCLK   (0x1 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_32SCLK   (0x2 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_512SCLK   (0x3 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_4096SCLK   (0x4 << 12)
#define	AT91C_SUPC_WUMR_WKUPDBC_32768SCLK   (0x5 << 12)
#define	AT91C_SUPC_WUIR_WKUPEN0   (0x1 << 0)
#define	AT91C_SUPC_WUIR_WKUPEN0_NOT_ENABLE   (0x0 << 0)
#define	AT91C_SUPC_WUIR_WKUPEN0_ENABLE   (0x1 << 0)
#define	AT91C_SUPC_WUIR_WKUPEN1   (0x1 << 1)
#define	AT91C_SUPC_WUIR_WKUPEN1_NOT_ENABLE   (0x0 << 1)
#define	AT91C_SUPC_WUIR_WKUPEN1_ENABLE   (0x1 << 1)
#define	AT91C_SUPC_WUIR_WKUPEN2   (0x1 << 2)
#define	AT91C_SUPC_WUIR_WKUPEN2_NOT_ENABLE   (0x0 << 2)
#define	AT91C_SUPC_WUIR_WKUPEN2_ENABLE   (0x1 << 2)
#define	AT91C_SUPC_WUIR_WKUPEN3   (0x1 << 3)
#define	AT91C_SUPC_WUIR_WKUPEN3_NOT_ENABLE   (0x0 << 3)
#define	AT91C_SUPC_WUIR_WKUPEN3_ENABLE   (0x1 << 3)
#define	AT91C_SUPC_WUIR_WKUPEN4   (0x1 << 4)
#define	AT91C_SUPC_WUIR_WKUPEN4_NOT_ENABLE   (0x0 << 4)
#define	AT91C_SUPC_WUIR_WKUPEN4_ENABLE   (0x1 << 4)
#define	AT91C_SUPC_WUIR_WKUPEN5   (0x1 << 5)
#define	AT91C_SUPC_WUIR_WKUPEN5_NOT_ENABLE   (0x0 << 5)
#define	AT91C_SUPC_WUIR_WKUPEN5_ENABLE   (0x1 << 5)
#define	AT91C_SUPC_WUIR_WKUPEN6   (0x1 << 6)
#define	AT91C_SUPC_WUIR_WKUPEN6_NOT_ENABLE   (0x0 << 6)
#define	AT91C_SUPC_WUIR_WKUPEN6_ENABLE   (0x1 << 6)
#define	AT91C_SUPC_WUIR_WKUPEN7   (0x1 << 7)
#define	AT91C_SUPC_WUIR_WKUPEN7_NOT_ENABLE   (0x0 << 7)
#define	AT91C_SUPC_WUIR_WKUPEN7_ENABLE   (0x1 << 7)
#define	AT91C_SUPC_WUIR_WKUPEN8   (0x1 << 8)
#define	AT91C_SUPC_WUIR_WKUPEN8_NOT_ENABLE   (0x0 << 8)
#define	AT91C_SUPC_WUIR_WKUPEN8_ENABLE   (0x1 << 8)
#define	AT91C_SUPC_WUIR_WKUPEN9   (0x1 << 9)
#define	AT91C_SUPC_WUIR_WKUPEN9_NOT_ENABLE   (0x0 << 9)
#define	AT91C_SUPC_WUIR_WKUPEN9_ENABLE   (0x1 << 9)
#define	AT91C_SUPC_WUIR_WKUPEN10   (0x1 << 10)
#define	AT91C_SUPC_WUIR_WKUPEN10_NOT_ENABLE   (0x0 << 10)
#define	AT91C_SUPC_WUIR_WKUPEN10_ENABLE   (0x1 << 10)
#define	AT91C_SUPC_WUIR_WKUPEN11   (0x1 << 11)
#define	AT91C_SUPC_WUIR_WKUPEN11_NOT_ENABLE   (0x0 << 11)
#define	AT91C_SUPC_WUIR_WKUPEN11_ENABLE   (0x1 << 11)
#define	AT91C_SUPC_WUIR_WKUPEN12   (0x1 << 12)
#define	AT91C_SUPC_WUIR_WKUPEN12_NOT_ENABLE   (0x0 << 12)
#define	AT91C_SUPC_WUIR_WKUPEN12_ENABLE   (0x1 << 12)
#define	AT91C_SUPC_WUIR_WKUPEN13   (0x1 << 13)
#define	AT91C_SUPC_WUIR_WKUPEN13_NOT_ENABLE   (0x0 << 13)
#define	AT91C_SUPC_WUIR_WKUPEN13_ENABLE   (0x1 << 13)
#define	AT91C_SUPC_WUIR_WKUPEN14   (0x1 << 14)
#define	AT91C_SUPC_WUIR_WKUPEN14_NOT_ENABLE   (0x0 << 14)
#define	AT91C_SUPC_WUIR_WKUPEN14_ENABLE   (0x1 << 14)
#define	AT91C_SUPC_WUIR_WKUPEN15   (0x1 << 15)
#define	AT91C_SUPC_WUIR_WKUPEN15_NOT_ENABLE   (0x0 << 15)
#define	AT91C_SUPC_WUIR_WKUPEN15_ENABLE   (0x1 << 15)
#define	AT91C_SUPC_WUIR_WKUPT0   (0x1 << 16)
#define	AT91C_SUPC_WUIR_WKUPT0_HIGH_TO_LOW   (0x0 << 16)
#define	AT91C_SUPC_WUIR_WKUPT0_LOW_TO_HIGH   (0x1 << 16)
#define	AT91C_SUPC_WUIR_WKUPT1   (0x1 << 17)
#define	AT91C_SUPC_WUIR_WKUPT1_HIGH_TO_LOW   (0x0 << 17)
#define	AT91C_SUPC_WUIR_WKUPT1_LOW_TO_HIGH   (0x1 << 17)
#define	AT91C_SUPC_WUIR_WKUPT2   (0x1 << 18)
#define	AT91C_SUPC_WUIR_WKUPT2_HIGH_TO_LOW   (0x0 << 18)
#define	AT91C_SUPC_WUIR_WKUPT2_LOW_TO_HIGH   (0x1 << 18)
#define	AT91C_SUPC_WUIR_WKUPT3   (0x1 << 19)
#define	AT91C_SUPC_WUIR_WKUPT3_HIGH_TO_LOW   (0x0 << 19)
#define	AT91C_SUPC_WUIR_WKUPT3_LOW_TO_HIGH   (0x1 << 19)
#define	AT91C_SUPC_WUIR_WKUPT4   (0x1 << 20)
#define	AT91C_SUPC_WUIR_WKUPT4_HIGH_TO_LOW   (0x0 << 20)
#define	AT91C_SUPC_WUIR_WKUPT4_LOW_TO_HIGH   (0x1 << 20)
#define	AT91C_SUPC_WUIR_WKUPT5   (0x1 << 21)
#define	AT91C_SUPC_WUIR_WKUPT5_HIGH_TO_LOW   (0x0 << 21)
#define	AT91C_SUPC_WUIR_WKUPT5_LOW_TO_HIGH   (0x1 << 21)
#define	AT91C_SUPC_WUIR_WKUPT6   (0x1 << 22)
#define	AT91C_SUPC_WUIR_WKUPT6_HIGH_TO_LOW   (0x0 << 22)
#define	AT91C_SUPC_WUIR_WKUPT6_LOW_TO_HIGH   (0x1 << 22)
#define	AT91C_SUPC_WUIR_WKUPT7   (0x1 << 23)
#define	AT91C_SUPC_WUIR_WKUPT7_HIGH_TO_LOW   (0x0 << 23)
#define	AT91C_SUPC_WUIR_WKUPT7_LOW_TO_HIGH   (0x1 << 23)
#define	AT91C_SUPC_WUIR_WKUPT8   (0x1 << 24)
#define	AT91C_SUPC_WUIR_WKUPT8_HIGH_TO_LOW   (0x0 << 24)
#define	AT91C_SUPC_WUIR_WKUPT8_LOW_TO_HIGH   (0x1 << 24)
#define	AT91C_SUPC_WUIR_WKUPT9   (0x1 << 25)
#define	AT91C_SUPC_WUIR_WKUPT9_HIGH_TO_LOW   (0x0 << 25)
#define	AT91C_SUPC_WUIR_WKUPT9_LOW_TO_HIGH   (0x1 << 25)
#define	AT91C_SUPC_WUIR_WKUPT10   (0x1 << 26)
#define	AT91C_SUPC_WUIR_WKUPT10_HIGH_TO_LOW   (0x0 << 26)
#define	AT91C_SUPC_WUIR_WKUPT10_LOW_TO_HIGH   (0x1 << 26)
#define	AT91C_SUPC_WUIR_WKUPT11   (0x1 << 27)
#define	AT91C_SUPC_WUIR_WKUPT11_HIGH_TO_LOW   (0x0 << 27)
#define	AT91C_SUPC_WUIR_WKUPT11_LOW_TO_HIGH   (0x1 << 27)
#define	AT91C_SUPC_WUIR_WKUPT12   (0x1 << 28)
#define	AT91C_SUPC_WUIR_WKUPT12_HIGH_TO_LOW   (0x0 << 28)
#define	AT91C_SUPC_WUIR_WKUPT12_LOW_TO_HIGH   (0x1 << 28)
#define	AT91C_SUPC_WUIR_WKUPT13   (0x1 << 29)
#define	AT91C_SUPC_WUIR_WKUPT13_HIGH_TO_LOW   (0x0 << 29)
#define	AT91C_SUPC_WUIR_WKUPT13_LOW_TO_HIGH   (0x1 << 29)
#define	AT91C_SUPC_WUIR_WKUPT14   (0x1 << 30)
#define	AT91C_SUPC_WUIR_WKUPT14_HIGH_TO_LOW   (0x0 << 30)
#define	AT91C_SUPC_WUIR_WKUPT14_LOW_TO_HIGH   (0x1 << 30)
#define	AT91C_SUPC_WUIR_WKUPT15   (0x1 << 31)
#define	AT91C_SUPC_WUIR_WKUPT15_HIGH_TO_LOW   (0x0 << 31)
#define	AT91C_SUPC_WUIR_WKUPT15_LOW_TO_HIGH   (0x1 << 31)
#define	AT91C_SUPC_SR_FWUPS   (0x1 << 0)
#define	AT91C_SUPC_SR_FWUPS_NO   (0x0 << 0)
#define	AT91C_SUPC_SR_FWUPS_PRESENT   (0x1 << 0)
#define	AT91C_SUPC_SR_WKUPS   (0x1 << 1)
#define	AT91C_SUPC_SR_WKUPS_NO   (0x0 << 1)
#define	AT91C_SUPC_SR_WKUPS_PRESENT   (0x1 << 1)
#define	AT91C_SUPC_SR_SMWS   (0x1 << 2)
#define	AT91C_SUPC_SR_SMWS_NO   (0x0 << 2)
#define	AT91C_SUPC_SR_SMWS_PRESENT   (0x1 << 2)
#define	AT91C_SUPC_SR_BODRSTS   (0x1 << 3)
#define	AT91C_SUPC_SR_BODRSTS_NO   (0x0 << 3)
#define	AT91C_SUPC_SR_BODRSTS_PRESENT   (0x1 << 3)
#define	AT91C_SUPC_SR_SMRSTS   (0x1 << 4)
#define	AT91C_SUPC_SR_SMRSTS_NO   (0x0 << 4)
#define	AT91C_SUPC_SR_SMRSTS_PRESENT   (0x1 << 4)
#define	AT91C_SUPC_SR_SMS   (0x1 << 5)
#define	AT91C_SUPC_SR_SMS_NO   (0x0 << 5)
#define	AT91C_SUPC_SR_SMS_PRESENT   (0x1 << 5)
#define	AT91C_SUPC_SR_SMOS   (0x1 << 6)
#define	AT91C_SUPC_SR_SMOS_HIGH   (0x0 << 6)
#define	AT91C_SUPC_SR_SMOS_LOW   (0x1 << 6)
#define	AT91C_SUPC_SR_OSCSEL   (0x1 << 7)
#define	AT91C_SUPC_SR_OSCSEL_RC   (0x0 << 7)
#define	AT91C_SUPC_SR_OSCSEL_CRYST   (0x1 << 7)
#define	AT91C_SUPC_SR_FWUPIS   (0x1 << 12)
#define	AT91C_SUPC_SR_FWUPIS_LOW   (0x0 << 12)
#define	AT91C_SUPC_SR_FWUPIS_HIGH   (0x1 << 12)
#define	AT91C_SUPC_SR_WKUPIS0   (0x1 << 16)
#define	AT91C_SUPC_SR_WKUPIS0_DIS   (0x0 << 16)
#define	AT91C_SUPC_SR_WKUPIS0_EN   (0x1 << 16)
#define	AT91C_SUPC_SR_WKUPIS1   (0x1 << 17)
#define	AT91C_SUPC_SR_WKUPIS1_DIS   (0x0 << 17)
#define	AT91C_SUPC_SR_WKUPIS1_EN   (0x1 << 17)
#define	AT91C_SUPC_SR_WKUPIS2   (0x1 << 18)
#define	AT91C_SUPC_SR_WKUPIS2_DIS   (0x0 << 18)
#define	AT91C_SUPC_SR_WKUPIS2_EN   (0x1 << 18)
#define	AT91C_SUPC_SR_WKUPIS3   (0x1 << 19)
#define	AT91C_SUPC_SR_WKUPIS3_DIS   (0x0 << 19)
#define	AT91C_SUPC_SR_WKUPIS3_EN   (0x1 << 19)
#define	AT91C_SUPC_SR_WKUPIS4   (0x1 << 20)
#define	AT91C_SUPC_SR_WKUPIS4_DIS   (0x0 << 20)
#define	AT91C_SUPC_SR_WKUPIS4_EN   (0x1 << 20)
#define	AT91C_SUPC_SR_WKUPIS5   (0x1 << 21)
#define	AT91C_SUPC_SR_WKUPIS5_DIS   (0x0 << 21)
#define	AT91C_SUPC_SR_WKUPIS5_EN   (0x1 << 21)
#define	AT91C_SUPC_SR_WKUPIS6   (0x1 << 22)
#define	AT91C_SUPC_SR_WKUPIS6_DIS   (0x0 << 22)
#define	AT91C_SUPC_SR_WKUPIS6_EN   (0x1 << 22)
#define	AT91C_SUPC_SR_WKUPIS7   (0x1 << 23)
#define	AT91C_SUPC_SR_WKUPIS7_DIS   (0x0 << 23)
#define	AT91C_SUPC_SR_WKUPIS7_EN   (0x1 << 23)
#define	AT91C_SUPC_SR_WKUPIS8   (0x1 << 24)
#define	AT91C_SUPC_SR_WKUPIS8_DIS   (0x0 << 24)
#define	AT91C_SUPC_SR_WKUPIS8_EN   (0x1 << 24)
#define	AT91C_SUPC_SR_WKUPIS9   (0x1 << 25)
#define	AT91C_SUPC_SR_WKUPIS9_DIS   (0x0 << 25)
#define	AT91C_SUPC_SR_WKUPIS9_EN   (0x1 << 25)
#define	AT91C_SUPC_SR_WKUPIS10   (0x1 << 26)
#define	AT91C_SUPC_SR_WKUPIS10_DIS   (0x0 << 26)
#define	AT91C_SUPC_SR_WKUPIS10_EN   (0x1 << 26)
#define	AT91C_SUPC_SR_WKUPIS11   (0x1 << 27)
#define	AT91C_SUPC_SR_WKUPIS11_DIS   (0x0 << 27)
#define	AT91C_SUPC_SR_WKUPIS11_EN   (0x1 << 27)
#define	AT91C_SUPC_SR_WKUPIS12   (0x1 << 28)
#define	AT91C_SUPC_SR_WKUPIS12_DIS   (0x0 << 28)
#define	AT91C_SUPC_SR_WKUPIS12_EN   (0x1 << 28)
#define	AT91C_SUPC_SR_WKUPIS13   (0x1 << 29)
#define	AT91C_SUPC_SR_WKUPIS13_DIS   (0x0 << 29)
#define	AT91C_SUPC_SR_WKUPIS13_EN   (0x1 << 29)
#define	AT91C_SUPC_SR_WKUPIS14   (0x1 << 30)
#define	AT91C_SUPC_SR_WKUPIS14_DIS   (0x0 << 30)
#define	AT91C_SUPC_SR_WKUPIS14_EN   (0x1 << 30)
#define	AT91C_SUPC_SR_WKUPIS15   (0x1 << 31)
#define	AT91C_SUPC_SR_WKUPIS15_DIS   (0x0 << 31)
#define	AT91C_SUPC_SR_WKUPIS15_EN   (0x1 << 31)
#define	AT91C_RTTC_RTPRES   (0xFFFF << 0)
#define	AT91C_RTTC_ALMIEN   (0x1 << 16)
#define	AT91C_RTTC_RTTINCIEN   (0x1 << 17)
#define	AT91C_RTTC_RTTRST   (0x1 << 18)
#define	AT91C_RTTC_ALMV   (0x0 << 0)
#define	AT91C_RTTC_CRTV   (0x0 << 0)
#define	AT91C_RTTC_ALMS   (0x1 << 0)
#define	AT91C_RTTC_RTTINC   (0x1 << 1)
#define	AT91C_WDTC_WDRSTT   (0x1 << 0)
#define	AT91C_WDTC_KEY   (0xFF << 24)
#define	AT91C_WDTC_WDV   (0xFFF << 0)
#define	AT91C_WDTC_WDFIEN   (0x1 << 12)
#define	AT91C_WDTC_WDRSTEN   (0x1 << 13)
#define	AT91C_WDTC_WDRPROC   (0x1 << 14)
#define	AT91C_WDTC_WDDIS   (0x1 << 15)
#define	AT91C_WDTC_WDD   (0xFFF << 16)
#define	AT91C_WDTC_WDDBGHLT   (0x1 << 28)
#define	AT91C_WDTC_WDIDLEHLT   (0x1 << 29)
#define	AT91C_WDTC_WDUNF   (0x1 << 0)
#define	AT91C_WDTC_WDERR   (0x1 << 1)
#define	AT91C_RTC_UPDTIM   (0x1 << 0)
#define	AT91C_RTC_UPDCAL   (0x1 << 1)
#define	AT91C_RTC_TIMEVSEL   (0x3 << 8)
#define	AT91C_RTC_TIMEVSEL_MINUTE   (0x0 << 8)
#define	AT91C_RTC_TIMEVSEL_HOUR   (0x1 << 8)
#define	AT91C_RTC_TIMEVSEL_DAY24   (0x2 << 8)
#define	AT91C_RTC_TIMEVSEL_DAY12   (0x3 << 8)
#define	AT91C_RTC_CALEVSEL   (0x3 << 16)
#define	AT91C_RTC_CALEVSEL_WEEK   (0x0 << 16)
#define	AT91C_RTC_CALEVSEL_MONTH   (0x1 << 16)
#define	AT91C_RTC_CALEVSEL_YEAR   (0x2 << 16)
#define	AT91C_RTC_HRMOD   (0x1 << 0)
#define	AT91C_RTC_SEC   (0x7F << 0)
#define	AT91C_RTC_MIN   (0x7F << 8)
#define	AT91C_RTC_HOUR   (0x3F << 16)
#define	AT91C_RTC_AMPM   (0x1 << 22)
#define	AT91C_RTC_CENT   (0x3F << 0)
#define	AT91C_RTC_YEAR   (0xFF << 8)
#define	AT91C_RTC_MONTH   (0x1F << 16)
#define	AT91C_RTC_DAY   (0x7 << 21)
#define	AT91C_RTC_DATE   (0x3F << 24)
#define	AT91C_RTC_SECEN   (0x1 << 7)
#define	AT91C_RTC_MINEN   (0x1 << 15)
#define	AT91C_RTC_HOUREN   (0x1 << 23)
#define	AT91C_RTC_MONTHEN   (0x1 << 23)
#define	AT91C_RTC_DATEEN   (0x1 << 31)
#define	AT91C_RTC_ACKUPD   (0x1 << 0)
#define	AT91C_RTC_ALARM   (0x1 << 1)
#define	AT91C_RTC_SECEV   (0x1 << 2)
#define	AT91C_RTC_TIMEV   (0x1 << 3)
#define	AT91C_RTC_CALEV   (0x1 << 4)
#define	AT91C_RTC_NVTIM   (0x1 << 0)
#define	AT91C_RTC_NVCAL   (0x1 << 1)
#define	AT91C_RTC_NVTIMALR   (0x1 << 2)
#define	AT91C_RTC_NVCALALR   (0x1 << 3)
#define	AT91C_ADC_SWRST   (0x1 << 0)
#define	AT91C_ADC_START   (0x1 << 1)
#define	AT91C_ADC_TRGEN   (0x1 << 0)
#define	AT91C_ADC_TRGEN_DIS   (0x0)
#define	AT91C_ADC_TRGEN_EN   (0x1)
#define	AT91C_ADC_TRGSEL   (0x7 << 1)
#define	AT91C_ADC_TRGSEL_EXT   (0x0 << 1)
#define	AT91C_ADC_TRGSEL_TIOA0   (0x1 << 1)
#define	AT91C_ADC_TRGSEL_TIOA1   (0x2 << 1)
#define	AT91C_ADC_TRGSEL_TIOA2   (0x3 << 1)
#define	AT91C_ADC_TRGSEL_PWM0_TRIG   (0x4 << 1)
#define	AT91C_ADC_TRGSEL_PWM1_TRIG   (0x5 << 1)
#define	AT91C_ADC_TRGSEL_RESERVED   (0x6 << 1)
#define	AT91C_ADC_LOWRES   (0x1 << 4)
#define	AT91C_ADC_LOWRES_12_BIT   (0x0 << 4)
#define	AT91C_ADC_LOWRES_10_BIT   (0x1 << 4)
#define	AT91C_ADC_SLEEP   (0x1 << 5)
#define	AT91C_ADC_SLEEP_NORMAL_MODE   (0x0 << 5)
#define	AT91C_ADC_SLEEP_MODE   (0x1 << 5)
#define	AT91C_ADC_PRESCAL   (0x3F << 8)
#define	AT91C_ADC_STARTUP   (0x1F << 16)
#define	AT91C_ADC_SHTIM   (0xF << 24)
#define	AT91C_ADC_CH0   (0x1 << 0)
#define	AT91C_ADC_CH1   (0x1 << 1)
#define	AT91C_ADC_CH2   (0x1 << 2)
#define	AT91C_ADC_CH3   (0x1 << 3)
#define	AT91C_ADC_CH4   (0x1 << 4)
#define	AT91C_ADC_CH5   (0x1 << 5)
#define	AT91C_ADC_CH6   (0x1 << 6)
#define	AT91C_ADC_CH7   (0x1 << 7)
#define	AT91C_ADC_EOC0   (0x1 << 0)
#define	AT91C_ADC_EOC1   (0x1 << 1)
#define	AT91C_ADC_EOC2   (0x1 << 2)
#define	AT91C_ADC_EOC3   (0x1 << 3)
#define	AT91C_ADC_EOC4   (0x1 << 4)
#define	AT91C_ADC_EOC5   (0x1 << 5)
#define	AT91C_ADC_EOC6   (0x1 << 6)
#define	AT91C_ADC_EOC7   (0x1 << 7)
#define	AT91C_ADC_OVRE0   (0x1 << 8)
#define	AT91C_ADC_OVRE1   (0x1 << 9)
#define	AT91C_ADC_OVRE2   (0x1 << 10)
#define	AT91C_ADC_OVRE3   (0x1 << 11)
#define	AT91C_ADC_OVRE4   (0x1 << 12)
#define	AT91C_ADC_OVRE5   (0x1 << 13)
#define	AT91C_ADC_OVRE6   (0x1 << 14)
#define	AT91C_ADC_OVRE7   (0x1 << 15)
#define	AT91C_ADC_DRDY   (0x1 << 16)
#define	AT91C_ADC_GOVRE   (0x1 << 17)
#define	AT91C_ADC_ENDRX   (0x1 << 18)
#define	AT91C_ADC_RXBUFF   (0x1 << 19)
#define	AT91C_ADC_LDATA   (0x3FF << 0)
#define	AT91C_ADC_DATA   (0x3FF << 0)
#define	AT91C_ADC_GAIN   (0x3 << 0)
#define	AT91C_ADC_IBCTL   (0x3 << 6)
#define	AT91C_ADC_IBCTL_00   (0x0 << 6)
#define	AT91C_ADC_IBCTL_01   (0x1 << 6)
#define	AT91C_ADC_IBCTL_10   (0x2 << 6)
#define	AT91C_ADC_IBCTL_11   (0x3 << 6)
#define	AT91C_ADC_DIFF   (0x1 << 16)
#define	AT91C_ADC_OFFSET   (0x1 << 17)
#define	AT91C_OFFMODES   (0x1 << 0)
#define	AT91C_OFF_MODE_STARTUP_TIME   (0x1 << 16)
#define	AT91C_ADC_VER   (0xF << 0)
#define	AT91C_ADC12B_CR_SWRST   (0x1 << 0)
#define	AT91C_ADC12B_CR_SWRST_NO_EFFECT   (0x0 << 0)
#define	AT91C_ADC12B_CR_SWRST_RESET   (0x1 << 0)
#define	AT91C_ADC12B_CR_START   (0x1 << 1)
#define	AT91C_ADC12B_CR_START_NO_EFFECT   (0x0 << 1)
#define	AT91C_ADC12B_CR_START_BEGIN_ADC   (0x1 << 1)
#define	AT91C_ADC12B_MR_TRGEN   (0x1 << 0)
#define	AT91C_ADC12B_MR_TRGEN_DIS   (0x0 << 0)
#define	AT91C_ADC12B_MR_TRGEN_EN   (0x1 << 0)
#define	AT91C_ADC12B_MR_TRGSEL   (0x7 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_EXT_TRIG   (0x0 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_TIOA_0   (0x1 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_TIOA_1   (0x2 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_TIOA_2   (0x3 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_TIOA_3   (0x4 << 1)
#define	AT91C_ADC12B_MR_TRGSEL_TIOA_4   (0x5 << 1)
#define	AT91C_ADC12B_MR_LOWRES   (0x1 << 4)
#define	AT91C_ADC12B_MR_LOWRES_12_BIT   (0x0 << 4)
#define	AT91C_ADC12B_MR_LOWRES_10_BIT   (0x1 << 4)
#define	AT91C_ADC12B_MR_SLEEP   (0x1 << 5)
#define	AT91C_ADC12B_MR_SLEEP_NORMAL   (0x0 << 5)
#define	AT91C_ADC12B_MR_SLEEP_SLEEP   (0x1 << 5)
#define	AT91C_ADC12B_MR_PRESCAL   (0xff << 8)
#define	AT91C_ADC12B_MR_STARTUP   (0xff << 16)
#define	AT91C_ADC12B_MR_SHTIM   (0xf << 24)
#define	AT91C_ADC12B_CHER_CH0   (0x1 << 0)
#define	AT91C_ADC12B_CHER_CH0_NO_EFFECT   (0x0 << 0)
#define	AT91C_ADC12B_CHER_CH0_ENABLE   (0x1 << 0)
#define	AT91C_ADC12B_CHER_CH1   (0x1 << 1)
#define	AT91C_ADC12B_CHER_CH1_NO_EFFECT   (0x0 << 1)
#define	AT91C_ADC12B_CHER_CH1_ENABLE   (0x1 << 1)
#define	AT91C_ADC12B_CHER_CH2   (0x1 << 2)
#define	AT91C_ADC12B_CHER_CH2_NO_EFFECT   (0x0 << 2)
#define	AT91C_ADC12B_CHER_CH2_ENABLE   (0x1 << 2)
#define	AT91C_ADC12B_CHER_CH3   (0x1 << 3)
#define	AT91C_ADC12B_CHER_CH3_NO_EFFECT   (0x0 << 3)
#define	AT91C_ADC12B_CHER_CH3_ENABLE   (0x1 << 3)
#define	AT91C_ADC12B_CHER_CH4   (0x1 << 4)
#define	AT91C_ADC12B_CHER_CH4_NO_EFFECT   (0x0 << 4)
#define	AT91C_ADC12B_CHER_CH4_ENABLE   (0x1 << 4)
#define	AT91C_ADC12B_CHER_CH5   (0x1 << 5)
#define	AT91C_ADC12B_CHER_CH5_NO_EFFECT   (0x0 << 5)
#define	AT91C_ADC12B_CHER_CH5_ENABLE   (0x1 << 5)
#define	AT91C_ADC12B_CHER_CH6   (0x1 << 6)
#define	AT91C_ADC12B_CHER_CH6_NO_EFFECT   (0x0 << 6)
#define	AT91C_ADC12B_CHER_CH6_ENABLE   (0x1 << 6)
#define	AT91C_ADC12B_CHER_CH7   (0x1 << 7)
#define	AT91C_ADC12B_CHER_CH7_NO_EFFECT   (0x0 << 7)
#define	AT91C_ADC12B_CHER_CH7_ENABLE   (0x1 << 7)
#define	AT91C_ADC12B_CHDR_CH0   (0x1 << 0)
#define	AT91C_ADC12B_CHDR_CH0_NO_EFFECT   (0x0 << 0)
#define	AT91C_ADC12B_CHDR_CH0_DISABLE   (0x1 << 0)
#define	AT91C_ADC12B_CHDR_CH1   (0x1 << 1)
#define	AT91C_ADC12B_CHDR_CH1_NO_EFFECT   (0x0 << 1)
#define	AT91C_ADC12B_CHDR_CH1_DISABLE   (0x1 << 1)
#define	AT91C_ADC12B_CHDR_CH2   (0x1 << 2)
#define	AT91C_ADC12B_CHDR_CH2_NO_EFFECT   (0x0 << 2)
#define	AT91C_ADC12B_CHDR_CH2_DISABLE   (0x1 << 2)
#define	AT91C_ADC12B_CHDR_CH3   (0x1 << 3)
#define	AT91C_ADC12B_CHDR_CH3_NO_EFFECT   (0x0 << 3)
#define	AT91C_ADC12B_CHDR_CH3_DISABLE   (0x1 << 3)
#define	AT91C_ADC12B_CHDR_CH4   (0x1 << 4)
#define	AT91C_ADC12B_CHDR_CH4_NO_EFFECT   (0x0 << 4)
#define	AT91C_ADC12B_CHDR_CH4_DISABLE   (0x1 << 4)
#define	AT91C_ADC12B_CHDR_CH5   (0x1 << 5)
#define	AT91C_ADC12B_CHDR_CH5_NO_EFFECT   (0x0 << 5)
#define	AT91C_ADC12B_CHDR_CH5_DISABLE   (0x1 << 5)
#define	AT91C_ADC12B_CHDR_CH6   (0x1 << 6)
#define	AT91C_ADC12B_CHDR_CH6_NO_EFFECT   (0x0 << 6)
#define	AT91C_ADC12B_CHDR_CH6_DISABLE   (0x1 << 6)
#define	AT91C_ADC12B_CHDR_CH7   (0x1 << 7)
#define	AT91C_ADC12B_CHDR_CH7_NO_EFFECT   (0x0 << 7)
#define	AT91C_ADC12B_CHDR_CH7_DISABLE   (0x1 << 7)
#define	AT91C_ADC12B_CHSR_CH0   (0x1 << 0)
#define	AT91C_ADC12B_CHSR_CH0_DISABLED   (0x0 << 0)
#define	AT91C_ADC12B_CHSR_CH0_ENABLED   (0x1 << 0)
#define	AT91C_ADC12B_CHSR_CH1   (0x1 << 1)
#define	AT91C_ADC12B_CHSR_CH1_DISABLED   (0x0 << 1)
#define	AT91C_ADC12B_CHSR_CH1_ENABLED   (0x1 << 1)
#define	AT91C_ADC12B_CHSR_CH2   (0x1 << 2)
#define	AT91C_ADC12B_CHSR_CH2_DISABLED   (0x0 << 2)
#define	AT91C_ADC12B_CHSR_CH2_ENABLED   (0x1 << 2)
#define	AT91C_ADC12B_CHSR_CH3   (0x1 << 3)
#define	AT91C_ADC12B_CHSR_CH3_DISABLED   (0x0 << 3)
#define	AT91C_ADC12B_CHSR_CH3_ENABLED   (0x1 << 3)
#define	AT91C_ADC12B_CHSR_CH4   (0x1 << 4)
#define	AT91C_ADC12B_CHSR_CH4_DISABLED   (0x0 << 4)
#define	AT91C_ADC12B_CHSR_CH4_ENABLED   (0x1 << 4)
#define	AT91C_ADC12B_CHSR_CH5   (0x1 << 5)
#define	AT91C_ADC12B_CHSR_CH5_DISABLED   (0x0 << 5)
#define	AT91C_ADC12B_CHSR_CH5_ENABLED   (0x1 << 5)
#define	AT91C_ADC12B_CHSR_CH6   (0x1 << 6)
#define	AT91C_ADC12B_CHSR_CH6_DISABLED   (0x0 << 6)
#define	AT91C_ADC12B_CHSR_CH6_ENABLED   (0x1 << 6)
#define	AT91C_ADC12B_CHSR_CH7   (0x1 << 7)
#define	AT91C_ADC12B_CHSR_CH7_DISABLED   (0x0 << 7)
#define	AT91C_ADC12B_CHSR_CH7_ENABLED   (0x1 << 7)
#define	AT91C_ADC12B_SR_EOC0   (0x1 << 0)
#define	AT91C_ADC12B_SR_EOC0_DISABLE   (0x0 << 0)
#define	AT91C_ADC12B_SR_EOC0_ENABLE   (0x1 << 0)
#define	AT91C_ADC12B_SR_EOC1   (0x1 << 1)
#define	AT91C_ADC12B_SR_EOC1_DISABLE   (0x0 << 1)
#define	AT91C_ADC12B_SR_EOC1_ENABLE   (0x1 << 1)
#define	AT91C_ADC12B_SR_EOC2   (0x1 << 2)
#define	AT91C_ADC12B_SR_EOC2_DISABLE   (0x0 << 2)
#define	AT91C_ADC12B_SR_EOC2_ENABLE   (0x1 << 2)
#define	AT91C_ADC12B_SR_EOC3   (0x1 << 3)
#define	AT91C_ADC12B_SR_EOC3_DISABLE   (0x0 << 3)
#define	AT91C_ADC12B_SR_EOC3_ENABLE   (0x1 << 3)
#define	AT91C_ADC12B_SR_EOC4   (0x1 << 4)
#define	AT91C_ADC12B_SR_EOC4_DISABLE   (0x0 << 4)
#define	AT91C_ADC12B_SR_EOC4_ENABLE   (0x1 << 4)
#define	AT91C_ADC12B_SR_EOC5   (0x1 << 5)
#define	AT91C_ADC12B_SR_EOC5_DISABLE   (0x0 << 5)
#define	AT91C_ADC12B_SR_EOC5_ENABLE   (0x1 << 5)
#define	AT91C_ADC12B_SR_EOC6   (0x1 << 6)
#define	AT91C_ADC12B_SR_EOC6_DISABLE   (0x0 << 6)
#define	AT91C_ADC12B_SR_EOC6_ENABLE   (0x1 << 6)
#define	AT91C_ADC12B_SR_EOC7   (0x1 << 7)
#define	AT91C_ADC12B_SR_EOC7_DISABLE   (0x0 << 7)
#define	AT91C_ADC12B_SR_EOC7_ENABLE   (0x1 << 7)
#define	AT91C_ADC12B_SR_OVRE0   (0x1 << 8)
#define	AT91C_ADC12B_SR_OVRE0_NO_ERROR   (0x0 << 8)
#define	AT91C_ADC12B_SR_OVRE0_ERROR   (0x1 << 8)
#define	AT91C_ADC12B_SR_OVRE1   (0x1 << 9)
#define	AT91C_ADC12B_SR_OVRE1_NO_ERROR   (0x0 << 9)
#define	AT91C_ADC12B_SR_OVRE1_ERROR   (0x1 << 9)
#define	AT91C_ADC12B_SR_OVRE2   (0x1 << 10)
#define	AT91C_ADC12B_SR_OVRE2_NO_ERROR   (0x0 << 10)
#define	AT91C_ADC12B_SR_OVRE2_ERROR   (0x1 << 10)
#define	AT91C_ADC12B_SR_OVRE3   (0x1 << 11)
#define	AT91C_ADC12B_SR_OVRE3_NO_ERROR   (0x0 << 11)
#define	AT91C_ADC12B_SR_OVRE3_ERROR   (0x1 << 11)
#define	AT91C_ADC12B_SR_OVRE4   (0x1 << 12)
#define	AT91C_ADC12B_SR_OVRE4_NO_ERROR   (0x0 << 12)
#define	AT91C_ADC12B_SR_OVRE4_ERROR   (0x1 << 12)
#define	AT91C_ADC12B_SR_OVRE5   (0x1 << 13)
#define	AT91C_ADC12B_SR_OVRE5_NO_ERROR   (0x0 << 13)
#define	AT91C_ADC12B_SR_OVRE5_ERROR   (0x1 << 13)
#define	AT91C_ADC12B_SR_OVRE6   (0x1 << 14)
#define	AT91C_ADC12B_SR_OVRE6_NO_ERROR   (0x0 << 14)
#define	AT91C_ADC12B_SR_OVRE6_ERROR   (0x1 << 14)
#define	AT91C_ADC12B_SR_OVRE7   (0x1 << 15)
#define	AT91C_ADC12B_SR_OVRE7_NO_ERROR   (0x0 << 15)
#define	AT91C_ADC12B_SR_OVRE7_ERROR   (0x1 << 15)
#define	AT91C_ADC12B_SR_DRDY   (0x1 << 16)
#define	AT91C_ADC12B_SR_DRDY_NO_CONV   (0x0 << 16)
#define	AT91C_ADC12B_SR_DRDY_CONV   (0x1 << 16)
#define	AT91C_ADC12B_SR_GOVRE   (0x1 << 17)
#define	AT91C_ADC12B_SR_GOVRE_NO_ERROR   (0x0 << 17)
#define	AT91C_ADC12B_SR_GOVRE_ERROR   (0x1 << 17)
#define	AT91C_ADC12B_SR_ENDRX   (0x1 << 18)
#define	AT91C_ADC12B_SR_ENDRX_NOT_REACH   (0x0 << 18)
#define	AT91C_ADC12B_SR_ENDRX_REACH_0   (0x1 << 18)
#define	AT91C_ADC12B_SR_RXBUFF   (0x1 << 19)
#define	AT91C_ADC12B_SR_RXBUFF_NO_ZERO   (0x0 << 19)
#define	AT91C_ADC12B_SR_RXBUFF_ZERO   (0x1 << 19)
#define	AT91C_ADC12B_LCDR_LDATA   (0xfff << 0)
#define	AT91C_ADC12B_IER_EOC0   (0x1 << 0)
#define	AT91C_ADC12B_IER_EOC0_NO_EFFECT   (0x0 << 0)
#define	AT91C_ADC12B_IER_EOC0_ENABLE   (0x1 << 0)
#define	AT91C_ADC12B_IER_EOC1   (0x1 << 1)
#define	AT91C_ADC12B_IER_EOC1_NO_EFFECT   (0x0 << 1)
#define	AT91C_ADC12B_IER_EOC1_ENABLE   (0x1 << 1)
#define	AT91C_ADC12B_IER_EOC2   (0x1 << 2)
#define	AT91C_ADC12B_IER_EOC2_NO_EFFECT   (0x0 << 2)
#define	AT91C_ADC12B_IER_EOC2_ENABLE   (0x1 << 2)
#define	AT91C_ADC12B_IER_EOC3   (0x1 << 3)
#define	AT91C_ADC12B_IER_EOC3_NO_EFFECT   (0x0 << 3)
#define	AT91C_ADC12B_IER_EOC3_ENABLE   (0x1 << 3)
#define	AT91C_ADC12B_IER_EOC4   (0x1 << 4)
#define	AT91C_ADC12B_IER_EOC4_NO_EFFECT   (0x0 << 4)
#define	AT91C_ADC12B_IER_EOC4_ENABLE   (0x1 << 4)
#define	AT91C_ADC12B_IER_EOC5   (0x1 << 5)
#define	AT91C_ADC12B_IER_EOC5_NO_EFFECT   (0x0 << 5)
#define	AT91C_ADC12B_IER_EOC5_ENABLE   (0x1 << 5)
#define	AT91C_ADC12B_IER_EOC6   (0x1 << 6)
#define	AT91C_ADC12B_IER_EOC6_NO_EFFECT   (0x0 << 6)
#define	AT91C_ADC12B_IER_EOC6_ENABLE   (0x1 << 6)
#define	AT91C_ADC12B_IER_EOC7   (0x1 << 7)
#define	AT91C_ADC12B_IER_EOC7_NO_EFFECT   (0x0 << 7)
#define	AT91C_ADC12B_IER_EOC7_ENABLE   (0x1 << 7)
#define	AT91C_ADC12B_IER_OVRE0   (0x1 << 8)
#define	AT91C_ADC12B_IER_OVRE0_NO_EFFECT   (0x0 << 8)
#define	AT91C_ADC12B_IER_OVRE0_ENABLE   (0x1 << 8)
#define	AT91C_ADC12B_IER_OVRE1   (0x1 << 9)
#define	AT91C_ADC12B_IER_OVRE1_NO_EFFECT   (0x0 << 9)
#define	AT91C_ADC12B_IER_OVRE1_ENABLE   (0x1 << 9)
#define	AT91C_ADC12B_IER_OVRE2   (0x1 << 10)
#define	AT91C_ADC12B_IER_OVRE2_NO_EFFECT   (0x0 << 10)
#define	AT91C_ADC12B_IER_OVRE2_ENABLE   (0x1 << 10)
#define	AT91C_ADC12B_IER_OVRE3   (0x1 << 11)
#define	AT91C_ADC12B_IER_OVRE3_NO_EFFECT   (0x0 << 11)
#define	AT91C_ADC12B_IER_OVRE3_ENABLE   (0x1 << 11)
#define	AT91C_ADC12B_IER_OVRE4   (0x1 << 12)
#define	AT91C_ADC12B_IER_OVRE4_NO_EFFECT   (0x0 << 12)
#define	AT91C_ADC12B_IER_OVRE4_ENABLE   (0x1 << 12)
#define	AT91C_ADC12B_IER_OVRE5   (0x1 << 13)
#define	AT91C_ADC12B_IER_OVRE5_NO_EFFECT   (0x0 << 13)
#define	AT91C_ADC12B_IER_OVRE5_ENABLE   (0x1 << 13)
#define	AT91C_ADC12B_IER_OVRE6   (0x1 << 14)
#define	AT91C_ADC12B_IER_OVRE6_NO_EFFECT   (0x0 << 14)
#define	AT91C_ADC12B_IER_OVRE6_ENABLE   (0x1 << 14)
#define	AT91C_ADC12B_IER_OVRE7   (0x1 << 15)
#define	AT91C_ADC12B_IER_OVRE7_NO_EFFECT   (0x0 << 15)
#define	AT91C_ADC12B_IER_OVRE7_ENABLE   (0x1 << 15)
#define	AT91C_ADC12B_IER_DRDY   (0x1 << 16)
#define	AT91C_ADC12B_IER_DRDY_NO_EFFECT   (0x0 << 16)
#define	AT91C_ADC12B_IER_DRDY_ENABLE   (0x1 << 16)
#define	AT91C_ADC12B_IER_GOVRE   (0x1 << 17)
#define	AT91C_ADC12B_IER_GOVRE_NO_EFFECT   (0x0 << 17)
#define	AT91C_ADC12B_IER_GOVRE_ENABLE   (0x1 << 17)
#define	AT91C_ADC12B_IER_ENDRX   (0x1 << 18)
#define	AT91C_ADC12B_IER_ENDRX_NO_EFFECT   (0x0 << 18)
#define	AT91C_ADC12B_IER_ENDRX_ENABLE   (0x1 << 18)
#define	AT91C_ADC12B_IER_RXBUFF   (0x1 << 19)
#define	AT91C_ADC12B_IER_RXBUFF_NO_EFFECT   (0x0 << 19)
#define	AT91C_ADC12B_IER_RXBUFF_ENABLE   (0x1 << 19)
#define	AT91C_ADC12B_IDR_EOC0   (0x1 << 0)
#define	AT91C_ADC12B_IDR_EOC0_NO_EFFECT   (0x0 << 0)
#define	AT91C_ADC12B_IDR_EOC0_DISABLE   (0x1 << 0)
#define	AT91C_ADC12B_IDR_EOC1   (0x1 << 1)
#define	AT91C_ADC12B_IDR_EOC1_NO_EFFECT   (0x0 << 1)
#define	AT91C_ADC12B_IDR_EOC1_DISABLE   (0x1 << 1)
#define	AT91C_ADC12B_IDR_EOC2   (0x1 << 2)
#define	AT91C_ADC12B_IDR_EOC2_NO_EFFECT   (0x0 << 2)
#define	AT91C_ADC12B_IDR_EOC2_DISABLE   (0x1 << 2)
#define	AT91C_ADC12B_IDR_EOC3   (0x1 << 3)
#define	AT91C_ADC12B_IDR_EOC3_NO_EFFECT   (0x0 << 3)
#define	AT91C_ADC12B_IDR_EOC3_DISABLE   (0x1 << 3)
#define	AT91C_ADC12B_IDR_EOC4   (0x1 << 4)
#define	AT91C_ADC12B_IDR_EOC4_NO_EFFECT   (0x0 << 4)
#define	AT91C_ADC12B_IDR_EOC4_DISABLE   (0x1 << 4)
#define	AT91C_ADC12B_IDR_EOC5   (0x1 << 5)
#define	AT91C_ADC12B_IDR_EOC5_NO_EFFECT   (0x0 << 5)
#define	AT91C_ADC12B_IDR_EOC5_DISABLE   (0x1 << 5)
#define	AT91C_ADC12B_IDR_EOC6   (0x1 << 6)
#define	AT91C_ADC12B_IDR_EOC6_NO_EFFECT   (0x0 << 6)
#define	AT91C_ADC12B_IDR_EOC6_DISABLE   (0x1 << 6)
#define	AT91C_ADC12B_IDR_EOC7   (0x1 << 7)
#define	AT91C_ADC12B_IDR_EOC7_NO_EFFECT   (0x0 << 7)
#define	AT91C_ADC12B_IDR_EOC7_DISABLE   (0x1 << 7)
#define	AT91C_ADC12B_IDR_OVRE0   (0x1 << 8)
#define	AT91C_ADC12B_IDR_OVRE0_NO_EFFECT   (0x0 << 8)
#define	AT91C_ADC12B_IDR_OVRE0_DISABLE   (0x1 << 8)
#define	AT91C_ADC12B_IDR_OVRE1   (0x1 << 9)
#define	AT91C_ADC12B_IDR_OVRE1_NO_EFFECT   (0x0 << 9)
#define	AT91C_ADC12B_IDR_OVRE1_DISABLE   (0x1 << 9)
#define	AT91C_ADC12B_IDR_OVRE2   (0x1 << 10)
#define	AT91C_ADC12B_IDR_OVRE2_NO_EFFECT   (0x0 << 10)
#define	AT91C_ADC12B_IDR_OVRE2_DISABLE   (0x1 << 10)
#define	AT91C_ADC12B_IDR_OVRE3   (0x1 << 11)
#define	AT91C_ADC12B_IDR_OVRE3_NO_EFFECT   (0x0 << 11)
#define	AT91C_ADC12B_IDR_OVRE3_DISABLE   (0x1 << 11)
#define	AT91C_ADC12B_IDR_OVRE4   (0x1 << 12)
#define	AT91C_ADC12B_IDR_OVRE4_NO_EFFECT   (0x0 << 12)
#define	AT91C_ADC12B_IDR_OVRE4_DISABLE   (0x1 << 12)
#define	AT91C_ADC12B_IDR_OVRE5   (0x1 << 13)
#define	AT91C_ADC12B_IDR_OVRE5_NO_EFFECT   (0x0 << 13)
#define	AT91C_ADC12B_IDR_OVRE5_DISABLE   (0x1 << 13)
#define	AT91C_ADC12B_IDR_OVRE6   (0x1 << 14)
#define	AT91C_ADC12B_IDR_OVRE6_NO_EFFECT   (0x0 << 14)
#define	AT91C_ADC12B_IDR_OVRE6_DISABLE   (0x1 << 14)
#define	AT91C_ADC12B_IDR_OVRE7   (0x1 << 15)
#define	AT91C_ADC12B_IDR_OVRE7_NO_EFFECT   (0x0 << 15)
#define	AT91C_ADC12B_IDR_OVRE7_DISABLE   (0x1 << 15)
#define	AT91C_ADC12B_IDR_DRDY   (0x1 << 16)
#define	AT91C_ADC12B_IDR_DRDY_NO_EFFECT   (0x0 << 16)
#define	AT91C_ADC12B_IDR_DRDY_DISABLE   (0x1 << 16)
#define	AT91C_ADC12B_IDR_GOVRE   (0x1 << 17)
#define	AT91C_ADC12B_IDR_GOVRE_NO_EFFECT   (0x0 << 17)
#define	AT91C_ADC12B_IDR_GOVRE_DISABLE   (0x1 << 17)
#define	AT91C_ADC12B_IDR_ENDRX   (0x1 << 18)
#define	AT91C_ADC12B_IDR_ENDRX_NO_EFFECT   (0x0 << 18)
#define	AT91C_ADC12B_IDR_ENDRX_DISABLE   (0x1 << 18)
#define	AT91C_ADC12B_IDR_RXBUFF   (0x1 << 19)
#define	AT91C_ADC12B_IDR_RXBUFF_NO_EFFECT   (0x0 << 19)
#define	AT91C_ADC12B_IDR_RXBUFF_DISABLE   (0x1 << 19)
#define	AT91C_ADC12B_IMR_EOC0   (0x1 << 0)
#define	AT91C_ADC12B_IMR_EOC0_DIS   (0x0 << 0)
#define	AT91C_ADC12B_IMR_EOC0_EN   (0x1 << 0)
#define	AT91C_ADC12B_IMR_EOC1   (0x1 << 1)
#define	AT91C_ADC12B_IMR_EOC1_DIS   (0x0 << 1)
#define	AT91C_ADC12B_IMR_EOC1_EN   (0x1 << 1)
#define	AT91C_ADC12B_IMR_EOC2   (0x1 << 2)
#define	AT91C_ADC12B_IMR_EOC2_DIS   (0x0 << 2)
#define	AT91C_ADC12B_IMR_EOC2_EN   (0x1 << 2)
#define	AT91C_ADC12B_IMR_EOC3   (0x1 << 3)
#define	AT91C_ADC12B_IMR_EOC3_DIS   (0x0 << 3)
#define	AT91C_ADC12B_IMR_EOC3_EN   (0x1 << 3)
#define	AT91C_ADC12B_IMR_EOC4   (0x1 << 4)
#define	AT91C_ADC12B_IMR_EOC4_DIS   (0x0 << 4)
#define	AT91C_ADC12B_IMR_EOC4_EN   (0x1 << 4)
#define	AT91C_ADC12B_IMR_EOC5   (0x1 << 5)
#define	AT91C_ADC12B_IMR_EOC5_DIS   (0x0 << 5)
#define	AT91C_ADC12B_IMR_EOC5_EN   (0x1 << 5)
#define	AT91C_ADC12B_IMR_EOC6   (0x1 << 6)
#define	AT91C_ADC12B_IMR_EOC6_DIS   (0x0 << 6)
#define	AT91C_ADC12B_IMR_EOC6_EN   (0x1 << 6)
#define	AT91C_ADC12B_IMR_EOC7   (0x1 << 7)
#define	AT91C_ADC12B_IMR_EOC7_DIS   (0x0 << 7)
#define	AT91C_ADC12B_IMR_EOC7_EN   (0x1 << 7)
#define	AT91C_ADC12B_IMR_OVRE0   (0x1 << 8)
#define	AT91C_ADC12B_IMR_OVRE0_DIS   (0x0 << 8)
#define	AT91C_ADC12B_IMR_OVRE0_EN   (0x1 << 8)
#define	AT91C_ADC12B_IMR_OVRE1   (0x1 << 9)
#define	AT91C_ADC12B_IMR_OVRE1_DIS   (0x0 << 9)
#define	AT91C_ADC12B_IMR_OVRE1_EN   (0x1 << 9)
#define	AT91C_ADC12B_IMR_OVRE2   (0x1 << 10)
#define	AT91C_ADC12B_IMR_OVRE2_DIS   (0x0 << 10)
#define	AT91C_ADC12B_IMR_OVRE2_EN   (0x1 << 10)
#define	AT91C_ADC12B_IMR_OVRE3   (0x1 << 11)
#define	AT91C_ADC12B_IMR_OVRE3_DIS   (0x0 << 11)
#define	AT91C_ADC12B_IMR_OVRE3_EN   (0x1 << 11)
#define	AT91C_ADC12B_IMR_OVRE4   (0x1 << 12)
#define	AT91C_ADC12B_IMR_OVRE4_DIS   (0x0 << 12)
#define	AT91C_ADC12B_IMR_OVRE4_EN   (0x1 << 12)
#define	AT91C_ADC12B_IMR_OVRE5   (0x1 << 13)
#define	AT91C_ADC12B_IMR_OVRE5_DIS   (0x0 << 13)
#define	AT91C_ADC12B_IMR_OVRE5_EN   (0x1 << 13)
#define	AT91C_ADC12B_IMR_OVRE6   (0x1 << 14)
#define	AT91C_ADC12B_IMR_OVRE6_DIS   (0x0 << 14)
#define	AT91C_ADC12B_IMR_OVRE6_EN   (0x1 << 14)
#define	AT91C_ADC12B_IMR_OVRE7   (0x1 << 15)
#define	AT91C_ADC12B_IMR_OVRE7_DIS   (0x0 << 15)
#define	AT91C_ADC12B_IMR_OVRE7_EN   (0x1 << 15)
#define	AT91C_ADC12B_IMR_DRDY   (0x1 << 16)
#define	AT91C_ADC12B_IMR_DRDY_DIS   (0x0 << 16)
#define	AT91C_ADC12B_IMR_DRDY_EN   (0x1 << 16)
#define	AT91C_ADC12B_IMR_GOVRE   (0x1 << 17)
#define	AT91C_ADC12B_IMR_GOVRE_DIS   (0x0 << 17)
#define	AT91C_ADC12B_IMR_GOVRE_EN   (0x1 << 17)
#define	AT91C_ADC12B_IMR_ENDRX   (0x1 << 18)
#define	AT91C_ADC12B_IMR_ENDRX_DIS   (0x0 << 18)
#define	AT91C_ADC12B_IMR_ENDRX_EN   (0x1 << 18)
#define	AT91C_ADC12B_IMR_RXBUFF   (0x1 << 19)
#define	AT91C_ADC12B_IMR_RXBUFF_DIS   (0x0 << 19)
#define	AT91C_ADC12B_IMR_RXBUFF_EN   (0x1 << 19)
#define	AT91C_ADC12B_CDR_DATA   (0xfff << 0)
#define	AT91C_ADC12B_ACR_GAIN   (0x3 << 0)
#define	AT91C_ADC12B_ACR_IBCTL   (0x3 << 6)
#define	AT91C_ADC12B_ACR_IBCTL_MIN20   (0x0 << 6)
#define	AT91C_ADC12B_ACR_IBCTL_TYP   (0x1 << 6)
#define	AT91C_ADC12B_ACR_IBCTL_PLUS20   (0x2 << 6)
#define	AT91C_ADC12B_ACR_IBCTL_PLUS40   (0x3 << 6)
#define	AT91C_ADC12B_ACR_DIFF   (0x1 << 16)
#define	AT91C_ADC12B_ACR_DIFF_SINGLE   (0x0 << 16)
#define	AT91C_ADC12B_ACR_DIFF_FULLY   (0x1 << 16)
#define	AT91C_ADC12B_ACR_OFFSET   (0x1 << 17)
#define	AT91C_ADC12B_EMR_OFFMODES   (0x1 << 0)
#define	AT91C_ADC12B_EMR_OFFMODES_STBY   (0x0 << 0)
#define	AT91C_ADC12B_EMR_OFFMODES_OFF   (0x1 << 0)
#define	AT91C_ADC12B_EMR_OFF_MODE_STARTUP_TIME   (0xff << 16)
#define	AT91C_TC_CLKEN   (0x1 << 0)
#define	AT91C_TC_CLKDIS   (0x1 << 1)
#define	AT91C_TC_SWTRG   (0x1 << 2)
#define	AT91C_TC_CLKS   (0x7 << 0)
#define	AT91C_TC_CLKS_TIMER_DIV1_CLOCK   (0x0)
#define	AT91C_TC_CLKS_TIMER_DIV2_CLOCK   (0x1)
#define	AT91C_TC_CLKS_TIMER_DIV3_CLOCK   (0x2)
#define	AT91C_TC_CLKS_TIMER_DIV4_CLOCK   (0x3)
#define	AT91C_TC_CLKS_TIMER_DIV5_CLOCK   (0x4)
#define	AT91C_TC_CLKS_XC0   (0x5)
#define	AT91C_TC_CLKS_XC1   (0x6)
#define	AT91C_TC_CLKS_XC2   (0x7)
#define	AT91C_TC_CLKI   (0x1 << 3)
#define	AT91C_TC_BURST   (0x3 << 4)
#define	AT91C_TC_BURST_NONE   (0x0 << 4)
#define	AT91C_TC_BURST_XC0   (0x1 << 4)
#define	AT91C_TC_BURST_XC1   (0x2 << 4)
#define	AT91C_TC_BURST_XC2   (0x3 << 4)
#define	AT91C_TC_CPCSTOP   (0x1 << 6)
#define	AT91C_TC_LDBSTOP   (0x1 << 6)
#define	AT91C_TC_CPCDIS   (0x1 << 7)
#define	AT91C_TC_LDBDIS   (0x1 << 7)
#define	AT91C_TC_ETRGEDG   (0x3 << 8)
#define	AT91C_TC_ETRGEDG_NONE   (0x0 << 8)
#define	AT91C_TC_ETRGEDG_RISING   (0x1 << 8)
#define	AT91C_TC_ETRGEDG_FALLING   (0x2 << 8)
#define	AT91C_TC_ETRGEDG_BOTH   (0x3 << 8)
#define	AT91C_TC_EEVTEDG   (0x3 << 8)
#define	AT91C_TC_EEVTEDG_NONE   (0x0 << 8)
#define	AT91C_TC_EEVTEDG_RISING   (0x1 << 8)
#define	AT91C_TC_EEVTEDG_FALLING   (0x2 << 8)
#define	AT91C_TC_EEVTEDG_BOTH   (0x3 << 8)
#define	AT91C_TC_EEVT   (0x3 << 10)
#define	AT91C_TC_EEVT_TIOB   (0x0 << 10)
#define	AT91C_TC_EEVT_XC0   (0x1 << 10)
#define	AT91C_TC_EEVT_XC1   (0x2 << 10)
#define	AT91C_TC_EEVT_XC2   (0x3 << 10)
#define	AT91C_TC_ABETRG   (0x1 << 10)
#define	AT91C_TC_ENETRG   (0x1 << 12)
#define	AT91C_TC_WAVESEL   (0x3 << 13)
#define	AT91C_TC_WAVESEL_UP   (0x0 << 13)
#define	AT91C_TC_WAVESEL_UPDOWN   (0x1 << 13)
#define	AT91C_TC_WAVESEL_UP_AUTO   (0x2 << 13)
#define	AT91C_TC_WAVESEL_UPDOWN_AUTO   (0x3 << 13)
#define	AT91C_TC_CPCTRG   (0x1 << 14)
#define	AT91C_TC_WAVE   (0x1 << 15)
#define	AT91C_TC_ACPA   (0x3 << 16)
#define	AT91C_TC_ACPA_NONE   (0x0 << 16)
#define	AT91C_TC_ACPA_SET   (0x1 << 16)
#define	AT91C_TC_ACPA_CLEAR   (0x2 << 16)
#define	AT91C_TC_ACPA_TOGGLE   (0x3 << 16)
#define	AT91C_TC_LDRA   (0x3 << 16)
#define	AT91C_TC_LDRA_NONE   (0x0 << 16)
#define	AT91C_TC_LDRA_RISING   (0x1 << 16)
#define	AT91C_TC_LDRA_FALLING   (0x2 << 16)
#define	AT91C_TC_LDRA_BOTH   (0x3 << 16)
#define	AT91C_TC_ACPC   (0x3 << 18)
#define	AT91C_TC_ACPC_NONE   (0x0 << 18)
#define	AT91C_TC_ACPC_SET   (0x1 << 18)
#define	AT91C_TC_ACPC_CLEAR   (0x2 << 18)
#define	AT91C_TC_ACPC_TOGGLE   (0x3 << 18)
#define	AT91C_TC_LDRB   (0x3 << 18)
#define	AT91C_TC_LDRB_NONE   (0x0 << 18)
#define	AT91C_TC_LDRB_RISING   (0x1 << 18)
#define	AT91C_TC_LDRB_FALLING   (0x2 << 18)
#define	AT91C_TC_LDRB_BOTH   (0x3 << 18)
#define	AT91C_TC_AEEVT   (0x3 << 20)
#define	AT91C_TC_AEEVT_NONE   (0x0 << 20)
#define	AT91C_TC_AEEVT_SET   (0x1 << 20)
#define	AT91C_TC_AEEVT_CLEAR   (0x2 << 20)
#define	AT91C_TC_AEEVT_TOGGLE   (0x3 << 20)
#define	AT91C_TC_ASWTRG   (0x3 << 22)
#define	AT91C_TC_ASWTRG_NONE   (0x0 << 22)
#define	AT91C_TC_ASWTRG_SET   (0x1 << 22)
#define	AT91C_TC_ASWTRG_CLEAR   (0x2 << 22)
#define	AT91C_TC_ASWTRG_TOGGLE   (0x3 << 22)
#define	AT91C_TC_BCPB   (0x3 << 24)
#define	AT91C_TC_BCPB_NONE   (0x0 << 24)
#define	AT91C_TC_BCPB_SET   (0x1 << 24)
#define	AT91C_TC_BCPB_CLEAR   (0x2 << 24)
#define	AT91C_TC_BCPB_TOGGLE   (0x3 << 24)
#define	AT91C_TC_BCPC   (0x3 << 26)
#define	AT91C_TC_BCPC_NONE   (0x0 << 26)
#define	AT91C_TC_BCPC_SET   (0x1 << 26)
#define	AT91C_TC_BCPC_CLEAR   (0x2 << 26)
#define	AT91C_TC_BCPC_TOGGLE   (0x3 << 26)
#define	AT91C_TC_BEEVT   (0x3 << 28)
#define	AT91C_TC_BEEVT_NONE   (0x0 << 28)
#define	AT91C_TC_BEEVT_SET   (0x1 << 28)
#define	AT91C_TC_BEEVT_CLEAR   (0x2 << 28)
#define	AT91C_TC_BEEVT_TOGGLE   (0x3 << 28)
#define	AT91C_TC_BSWTRG   (0x3 << 30)
#define	AT91C_TC_BSWTRG_NONE   (0x0 << 30)
#define	AT91C_TC_BSWTRG_SET   (0x1 << 30)
#define	AT91C_TC_BSWTRG_CLEAR   (0x2 << 30)
#define	AT91C_TC_BSWTRG_TOGGLE   (0x3 << 30)
#define	AT91C_TC_COVFS   (0x1 << 0)
#define	AT91C_TC_LOVRS   (0x1 << 1)
#define	AT91C_TC_CPAS   (0x1 << 2)
#define	AT91C_TC_CPBS   (0x1 << 3)
#define	AT91C_TC_CPCS   (0x1 << 4)
#define	AT91C_TC_LDRAS   (0x1 << 5)
#define	AT91C_TC_LDRBS   (0x1 << 6)
#define	AT91C_TC_ETRGS   (0x1 << 7)
#define	AT91C_TC_CLKSTA   (0x1 << 16)
#define	AT91C_TC_MTIOA   (0x1 << 17)
#define	AT91C_TC_MTIOB   (0x1 << 18)
#define	AT91C_TCB_SYNC   (0x1 << 0)
#define	AT91C_TCB_TC0XC0S   (0x3 << 0)
#define	AT91C_TCB_TC0XC0S_TCLK0   (0x0)
#define	AT91C_TCB_TC0XC0S_NONE   (0x1)
#define	AT91C_TCB_TC0XC0S_TIOA1   (0x2)
#define	AT91C_TCB_TC0XC0S_TIOA2   (0x3)
#define	AT91C_TCB_TC1XC1S   (0x3 << 2)
#define	AT91C_TCB_TC1XC1S_TCLK1   (0x0 << 2)
#define	AT91C_TCB_TC1XC1S_NONE   (0x1 << 2)
#define	AT91C_TCB_TC1XC1S_TIOA0   (0x2 << 2)
#define	AT91C_TCB_TC1XC1S_TIOA2   (0x3 << 2)
#define	AT91C_TCB_TC2XC2S   (0x3 << 4)
#define	AT91C_TCB_TC2XC2S_TCLK2   (0x0 << 4)
#define	AT91C_TCB_TC2XC2S_NONE   (0x1 << 4)
#define	AT91C_TCB_TC2XC2S_TIOA0   (0x2 << 4)
#define	AT91C_TCB_TC2XC2S_TIOA1   (0x3 << 4)
#define	AT91C_EFC_FRDY   (0x1 << 0)
#define	AT91C_EFC_FWS   (0xF << 8)
#define	AT91C_EFC_FWS_0WS   (0x0 << 8)
#define	AT91C_EFC_FWS_1WS   (0x1 << 8)
#define	AT91C_EFC_FWS_2WS   (0x2 << 8)
#define	AT91C_EFC_FWS_3WS   (0x3 << 8)
#define	AT91C_EFC_FCMD   (0xFF << 0)
#define	AT91C_EFC_FCMD_GETD   (0x0)
#define	AT91C_EFC_FCMD_WP   (0x1)
#define	AT91C_EFC_FCMD_WPL   (0x2)
#define	AT91C_EFC_FCMD_EWP   (0x3)
#define	AT91C_EFC_FCMD_EWPL   (0x4)
#define	AT91C_EFC_FCMD_EA   (0x5)
#define	AT91C_EFC_FCMD_EPL   (0x6)
#define	AT91C_EFC_FCMD_EPA   (0x7)
#define	AT91C_EFC_FCMD_SLB   (0x8)
#define	AT91C_EFC_FCMD_CLB   (0x9)
#define	AT91C_EFC_FCMD_GLB   (0xA)
#define	AT91C_EFC_FCMD_SFB   (0xB)
#define	AT91C_EFC_FCMD_CFB   (0xC)
#define	AT91C_EFC_FCMD_GFB   (0xD)
#define	AT91C_EFC_FCMD_STUI   (0xE)
#define	AT91C_EFC_FCMD_SPUI   (0xF)
#define	AT91C_EFC_FARG   (0xFFFF << 8)
#define	AT91C_EFC_FKEY   (0xFF << 24)
#define	AT91C_EFC_FRDY_S   (0x1 << 0)
#define	AT91C_EFC_FCMDE   (0x1 << 1)
#define	AT91C_EFC_LOCKE   (0x1 << 2)
#define	AT91C_EFC_FVALUE   (0x0 << 0)
#define	AT91C_MCI_MCIEN   (0x1 << 0)
#define	AT91C_MCI_MCIEN_0   (0x0)
#define	AT91C_MCI_MCIEN_1   (0x1)
#define	AT91C_MCI_MCIDIS   (0x1 << 1)
#define	AT91C_MCI_MCIDIS_0   (0x0 << 1)
#define	AT91C_MCI_MCIDIS_1   (0x1 << 1)
#define	AT91C_MCI_PWSEN   (0x1 << 2)
#define	AT91C_MCI_PWSEN_0   (0x0 << 2)
#define	AT91C_MCI_PWSEN_1   (0x1 << 2)
#define	AT91C_MCI_PWSDIS   (0x1 << 3)
#define	AT91C_MCI_PWSDIS_0   (0x0 << 3)
#define	AT91C_MCI_PWSDIS_1   (0x1 << 3)
#define	AT91C_MCI_IOWAITEN   (0x1 << 4)
#define	AT91C_MCI_IOWAITEN_0   (0x0 << 4)
#define	AT91C_MCI_IOWAITEN_1   (0x1 << 4)
#define	AT91C_MCI_IOWAITDIS   (0x1 << 5)
#define	AT91C_MCI_IOWAITDIS_0   (0x0 << 5)
#define	AT91C_MCI_IOWAITDIS_1   (0x1 << 5)
#define	AT91C_MCI_SWRST   (0x1 << 7)
#define	AT91C_MCI_SWRST_0   (0x0 << 7)
#define	AT91C_MCI_SWRST_1   (0x1 << 7)
#define	AT91C_MCI_CLKDIV   (0xFF << 0)
#define	AT91C_MCI_PWSDIV   (0x7 << 8)
#define	AT91C_MCI_RDPROOF   (0x1 << 11)
#define	AT91C_MCI_RDPROOF_DISABLE   (0x0 << 11)
#define	AT91C_MCI_RDPROOF_ENABLE   (0x1 << 11)
#define	AT91C_MCI_WRPROOF   (0x1 << 12)
#define	AT91C_MCI_WRPROOF_DISABLE   (0x0 << 12)
#define	AT91C_MCI_WRPROOF_ENABLE   (0x1 << 12)
#define	AT91C_MCI_PDCFBYTE   (0x1 << 13)
#define	AT91C_MCI_PDCFBYTE_DISABLE   (0x0 << 13)
#define	AT91C_MCI_PDCFBYTE_ENABLE   (0x1 << 13)
#define	AT91C_MCI_PDCPADV   (0x1 << 14)
#define	AT91C_MCI_PDCMODE   (0x1 << 15)
#define	AT91C_MCI_PDCMODE_DISABLE   (0x0 << 15)
#define	AT91C_MCI_PDCMODE_ENABLE   (0x1 << 15)
#define	AT91C_MCI_BLKLEN   (0xFFFF << 16)
#define	AT91C_MCI_DTOCYC   (0xF << 0)
#define	AT91C_MCI_DTOMUL   (0x7 << 4)
#define	AT91C_MCI_DTOMUL_1   (0x0 << 4)
#define	AT91C_MCI_DTOMUL_16   (0x1 << 4)
#define	AT91C_MCI_DTOMUL_128   (0x2 << 4)
#define	AT91C_MCI_DTOMUL_256   (0x3 << 4)
#define	AT91C_MCI_DTOMUL_1024   (0x4 << 4)
#define	AT91C_MCI_DTOMUL_4096   (0x5 << 4)
#define	AT91C_MCI_DTOMUL_65536   (0x6 << 4)
#define	AT91C_MCI_DTOMUL_1048576   (0x7 << 4)
#define	AT91C_MCI_SCDSEL   (0x3 << 0)
#define	AT91C_MCI_SCDSEL_SLOTA   (0x0)
#define	AT91C_MCI_SCDSEL_SLOTB   (0x1)
#define	AT91C_MCI_SCDSEL_SLOTC   (0x2)
#define	AT91C_MCI_SCDSEL_SLOTD   (0x3)
#define	AT91C_MCI_SCDBUS   (0x3 << 6)
#define	AT91C_MCI_SCDBUS_1BIT   (0x0 << 6)
#define	AT91C_MCI_SCDBUS_4BITS   (0x2 << 6)
#define	AT91C_MCI_SCDBUS_8BITS   (0x3 << 6)
#define	AT91C_MCI_CMDNB   (0x3F << 0)
#define	AT91C_MCI_RSPTYP   (0x3 << 6)
#define	AT91C_MCI_RSPTYP_NO   (0x0 << 6)
#define	AT91C_MCI_RSPTYP_48   (0x1 << 6)
#define	AT91C_MCI_RSPTYP_136   (0x2 << 6)
#define	AT91C_MCI_RSPTYP_R1B   (0x3 << 6)
#define	AT91C_MCI_SPCMD   (0x7 << 8)
#define	AT91C_MCI_SPCMD_NONE   (0x0 << 8)
#define	AT91C_MCI_SPCMD_INIT   (0x1 << 8)
#define	AT91C_MCI_SPCMD_SYNC   (0x2 << 8)
#define	AT91C_MCI_SPCMD_CE_ATA   (0x3 << 8)
#define	AT91C_MCI_SPCMD_IT_CMD   (0x4 << 8)
#define	AT91C_MCI_SPCMD_IT_REP   (0x5 << 8)
#define	AT91C_MCI_OPDCMD   (0x1 << 11)
#define	AT91C_MCI_OPDCMD_PUSHPULL   (0x0 << 11)
#define	AT91C_MCI_OPDCMD_OPENDRAIN   (0x1 << 11)
#define	AT91C_MCI_MAXLAT   (0x1 << 12)
#define	AT91C_MCI_MAXLAT_5   (0x0 << 12)
#define	AT91C_MCI_MAXLAT_64   (0x1 << 12)
#define	AT91C_MCI_TRCMD   (0x3 << 16)
#define	AT91C_MCI_TRCMD_NO   (0x0 << 16)
#define	AT91C_MCI_TRCMD_START   (0x1 << 16)
#define	AT91C_MCI_TRCMD_STOP   (0x2 << 16)
#define	AT91C_MCI_TRDIR   (0x1 << 18)
#define	AT91C_MCI_TRDIR_WRITE   (0x0 << 18)
#define	AT91C_MCI_TRDIR_READ   (0x1 << 18)
#define	AT91C_MCI_TRTYP   (0x7 << 19)
#define	AT91C_MCI_TRTYP_BLOCK   (0x0 << 19)
#define	AT91C_MCI_TRTYP_MULTIPLE   (0x1 << 19)
#define	AT91C_MCI_TRTYP_STREAM   (0x2 << 19)
#define	AT91C_MCI_TRTYP_SDIO_BYTE   (0x4 << 19)
#define	AT91C_MCI_TRTYP_SDIO_BLOCK   (0x5 << 19)
#define	AT91C_MCI_IOSPCMD   (0x3 << 24)
#define	AT91C_MCI_IOSPCMD_NONE   (0x0 << 24)
#define	AT91C_MCI_IOSPCMD_SUSPEND   (0x1 << 24)
#define	AT91C_MCI_IOSPCMD_RESUME   (0x2 << 24)
#define	AT91C_MCI_ATACS   (0x1 << 26)
#define	AT91C_MCI_ATACS_NORMAL   (0x0 << 26)
#define	AT91C_MCI_ATACS_COMPLETION   (0x1 << 26)
#define	AT91C_MCI_BCNT   (0xFFFF << 0)
#define	AT91C_MCI_CSTOCYC   (0xF << 0)
#define	AT91C_MCI_CSTOMUL   (0x7 << 4)
#define	AT91C_MCI_CSTOMUL_1   (0x0 << 4)
#define	AT91C_MCI_CSTOMUL_16   (0x1 << 4)
#define	AT91C_MCI_CSTOMUL_128   (0x2 << 4)
#define	AT91C_MCI_CSTOMUL_256   (0x3 << 4)
#define	AT91C_MCI_CSTOMUL_1024   (0x4 << 4)
#define	AT91C_MCI_CSTOMUL_4096   (0x5 << 4)
#define	AT91C_MCI_CSTOMUL_65536   (0x6 << 4)
#define	AT91C_MCI_CSTOMUL_1048576   (0x7 << 4)
#define	AT91C_MCI_CMDRDY   (0x1 << 0)
#define	AT91C_MCI_RXRDY   (0x1 << 1)
#define	AT91C_MCI_TXRDY   (0x1 << 2)
#define	AT91C_MCI_BLKE   (0x1 << 3)
#define	AT91C_MCI_DTIP   (0x1 << 4)
#define	AT91C_MCI_NOTBUSY   (0x1 << 5)
#define	AT91C_MCI_ENDRX   (0x1 << 6)
#define	AT91C_MCI_ENDTX   (0x1 << 7)
#define	AT91C_MCI_SDIOIRQA   (0x1 << 8)
#define	AT91C_MCI_SDIOIRQB   (0x1 << 9)
#define	AT91C_MCI_SDIOIRQC   (0x1 << 10)
#define	AT91C_MCI_SDIOIRQD   (0x1 << 11)
#define	AT91C_MCI_SDIOWAIT   (0x1 << 12)
#define	AT91C_MCI_CSRCV   (0x1 << 13)
#define	AT91C_MCI_RXBUFF   (0x1 << 14)
#define	AT91C_MCI_TXBUFE   (0x1 << 15)
#define	AT91C_MCI_RINDE   (0x1 << 16)
#define	AT91C_MCI_RDIRE   (0x1 << 17)
#define	AT91C_MCI_RCRCE   (0x1 << 18)
#define	AT91C_MCI_RENDE   (0x1 << 19)
#define	AT91C_MCI_RTOE   (0x1 << 20)
#define	AT91C_MCI_DCRCE   (0x1 << 21)
#define	AT91C_MCI_DTOE   (0x1 << 22)
#define	AT91C_MCI_CSTOE   (0x1 << 23)
#define	AT91C_MCI_BLKOVRE   (0x1 << 24)
#define	AT91C_MCI_DMADONE   (0x1 << 25)
#define	AT91C_MCI_FIFOEMPTY   (0x1 << 26)
#define	AT91C_MCI_XFRDONE   (0x1 << 27)
#define	AT91C_MCI_OVRE   (0x1 << 30)
#define	AT91C_MCI_UNRE   (0x1 << 31)
#define	AT91C_MCI_OFFSET   (0x3 << 0)
#define	AT91C_MCI_CHKSIZE   (0x7 << 4)
#define	AT91C_MCI_CHKSIZE_1   (0x0 << 4)
#define	AT91C_MCI_CHKSIZE_4   (0x1 << 4)
#define	AT91C_MCI_CHKSIZE_8   (0x2 << 4)
#define	AT91C_MCI_CHKSIZE_16   (0x3 << 4)
#define	AT91C_MCI_CHKSIZE_32   (0x4 << 4)
#define	AT91C_MCI_DMAEN   (0x1 << 8)
#define	AT91C_MCI_DMAEN_DISABLE   (0x0 << 8)
#define	AT91C_MCI_DMAEN_ENABLE   (0x1 << 8)
#define	AT91C_MCI_FIFOMODE   (0x1 << 0)
#define	AT91C_MCI_FIFOMODE_AMOUNTDATA   (0x0)
#define	AT91C_MCI_FIFOMODE_ONEDATA   (0x1)
#define	AT91C_MCI_FERRCTRL   (0x1 << 4)
#define	AT91C_MCI_FERRCTRL_RWCMD   (0x0 << 4)
#define	AT91C_MCI_FERRCTRL_READSR   (0x1 << 4)
#define	AT91C_MCI_HSMODE   (0x1 << 8)
#define	AT91C_MCI_HSMODE_DISABLE   (0x0 << 8)
#define	AT91C_MCI_HSMODE_ENABLE   (0x1 << 8)
#define	AT91C_MCI_LSYNC   (0x1 << 12)
#define	AT91C_MCI_LSYNC_CURRENT   (0x0 << 12)
#define	AT91C_MCI_LSYNC_INFINITE   (0x1 << 12)
#define	AT91C_MCI_WP_EN   (0x1 << 0)
#define	AT91C_MCI_WP_EN_DISABLE   (0x0)
#define	AT91C_MCI_WP_EN_ENABLE   (0x1)
#define	AT91C_MCI_WP_KEY   (0xFFFFFF << 8)
#define	AT91C_MCI_WP_VS   (0xF << 0)
#define	AT91C_MCI_WP_VS_NO_VIOLATION   (0x0)
#define	AT91C_MCI_WP_VS_ON_WRITE   (0x1)
#define	AT91C_MCI_WP_VS_ON_RESET   (0x2)
#define	AT91C_MCI_WP_VS_ON_BOTH   (0x3)
#define	AT91C_MCI_WP_VSRC   (0xF << 8)
#define	AT91C_MCI_WP_VSRC_NO_VIOLATION   (0x0 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_MR   (0x1 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_DTOR   (0x2 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_SDCR   (0x3 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_CSTOR   (0x4 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_DMA   (0x5 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_CFG   (0x6 << 8)
#define	AT91C_MCI_WP_VSRC_MCI_DEL   (0x7 << 8)
#define	AT91C_MCI_VER   (0xF << 0)
#define	AT91C_TWI_START   (0x1 << 0)
#define	AT91C_TWI_STOP   (0x1 << 1)
#define	AT91C_TWI_MSEN   (0x1 << 2)
#define	AT91C_TWI_MSDIS   (0x1 << 3)
#define	AT91C_TWI_SVEN   (0x1 << 4)
#define	AT91C_TWI_SVDIS   (0x1 << 5)
#define	AT91C_TWI_SWRST   (0x1 << 7)
#define	AT91C_TWI_IADRSZ   (0x3 << 8)
#define	AT91C_TWI_IADRSZ_NO   (0x0 << 8)
#define	AT91C_TWI_IADRSZ_1_BYTE   (0x1 << 8)
#define	AT91C_TWI_IADRSZ_2_BYTE   (0x2 << 8)
#define	AT91C_TWI_IADRSZ_3_BYTE   (0x3 << 8)
#define	AT91C_TWI_MREAD   (0x1 << 12)
#define	AT91C_TWI_DADR   (0x7F << 16)
#define	AT91C_TWI_SADR   (0x7F << 16)
#define	AT91C_TWI_CLDIV   (0xFF << 0)
#define	AT91C_TWI_CHDIV   (0xFF << 8)
#define	AT91C_TWI_CKDIV   (0x7 << 16)
#define	AT91C_TWI_TXCOMP_SLAVE   (0x1 << 0)
#define	AT91C_TWI_TXCOMP_MASTER   (0x1 << 0)
#define	AT91C_TWI_RXRDY   (0x1 << 1)
#define	AT91C_TWI_TXRDY_MASTER   (0x1 << 2)
#define	AT91C_TWI_TXRDY_SLAVE   (0x1 << 2)
#define	AT91C_TWI_SVREAD   (0x1 << 3)
#define	AT91C_TWI_SVACC   (0x1 << 4)
#define	AT91C_TWI_GACC   (0x1 << 5)
#define	AT91C_TWI_OVRE   (0x1 << 6)
#define	AT91C_TWI_NACK_SLAVE   (0x1 << 8)
#define	AT91C_TWI_NACK_MASTER   (0x1 << 8)
#define	AT91C_TWI_ARBLST_MULTI_MASTER   (0x1 << 9)
#define	AT91C_TWI_SCLWS   (0x1 << 10)
#define	AT91C_TWI_EOSACC   (0x1 << 11)
#define	AT91C_TWI_ENDRX   (0x1 << 12)
#define	AT91C_TWI_ENDTX   (0x1 << 13)
#define	AT91C_TWI_RXBUFF   (0x1 << 14)
#define	AT91C_TWI_TXBUFE   (0x1 << 15)
#define	US_CR_OFF   ( 0x00000000)
#define	US_MR_OFF   ( 0x00000004)
#define	US_IER_OFF   ( 0x00000008)
#define	US_IDR_OFF   ( 0x0000000C)
#define	US_IMR_OFF   ( 0x00000010)
#define	US_CSR_OFF   ( 0x00000014)
#define	US_RHR_OFF   ( 0x00000018)
#define	US_THR_OFF   ( 0x0000001C)
#define	US_BRGR_OFF   ( 0x00000020)
#define	US_RTOR_OFF   ( 0x00000024)
#define	US_TTGR_OFF   ( 0x00000028)
#define	US_FIDI_OFF   ( 0x00000040)
#define	US_NER_OFF   ( 0x00000044)
#define	US_IF_OFF   ( 0x0000004C)
#define	US_MAN_OFF   ( 0x00000050)
#define	US_ADDRSIZE_OFF   ( 0x000000EC)
#define	US_IPNAME1_OFF   ( 0x000000F0)
#define	US_IPNAME2_OFF   ( 0x000000F4)
#define	US_FEATURES_OFF   ( 0x000000F8)
#define	US_VER_OFF   ( 0x000000FC)
#define	US_RSTRX   (0x1 << 2)
#define	US_RSTTX   (0x1 << 3)
#define	US_RXEN   (0x1 << 4)
#define	US_RXDIS   (0x1 << 5)
#define	US_TXEN   (0x1 << 6)
#define	US_TXDIS   (0x1 << 7)
#define	US_RSTSTA   (0x1 << 8)
#define	US_STTBRK   (0x1 << 9)
#define	US_STPBRK   (0x1 << 10)
#define	US_STTTO   (0x1 << 11)
#define	US_SENDA   (0x1 << 12)
#define	US_RSTIT   (0x1 << 13)
#define	US_RSTNACK   (0x1 << 14)
#define	US_RETTO   (0x1 << 15)
#define	US_DTREN   (0x1 << 16)
#define	US_DTRDIS   (0x1 << 17)
#define	US_RTSEN   (0x1 << 18)
#define	US_RTSDIS   (0x1 << 19)
#define	US_USMODE   (0xF << 0)
#define	US_USMODE_NORMAL   (0x0)
#define	US_USMODE_RS485   (0x1)
#define	US_USMODE_HWHSH   (0x2)
#define	US_USMODE_MODEM   (0x3)
#define	US_USMODE_ISO7816_0   (0x4)
#define	US_USMODE_ISO7816_1   (0x6)
#define	US_USMODE_IRDA   (0x8)
#define	US_USMODE_SWHSH   (0xC)
#define	US_CLKS   (0x3 << 4)
#define	US_CLKS_MCK   (0x0 << 4)
#define	US_CLKS_MCK8   (0x1 << 4)
#define	US_CLKS_SLCK   (0x2 << 4)
#define	US_CLKS_SCK   (0x3 << 4)
#define	US_CHRL   (0x3 << 6)
#define	US_CHRL_5   (0x0 << 6)
#define	US_CHRL_6   (0x1 << 6)
#define	US_CHRL_7   (0x2 << 6)
#define	US_CHRL_8   (0x3 << 6)
#define	US_SYNC   (0x1 << 8)
#define	US_PAR   (0x7 << 9)
#define	US_PAR_EVEN   (0x0 << 9)
#define	US_PAR_ODD   (0x1 << 9)
#define	US_PAR_SPACE   (0x2 << 9)
#define	US_PAR_MARK   (0x3 << 9)
#define	US_PAR_NO   (0x4 << 9)
#define	US_PAR_MULTIDROP   (0x6 << 9)
#define	US_NBSTOP   (0x3 << 12)
#define	US_NBSTOP_1   (0x0 << 12)
#define	US_NBSTOP_15   (0x1 << 12)
#define	US_NBSTOP_2_BIT   (0x2 << 12)
#define	US_CHMODE   (0x3 << 14)
#define	US_CHMODE_NORMAL   (0x0 << 14)
#define	US_CHMODE_AUTO   (0x1 << 14)
#define	US_CHMODE_LOCAL   (0x2 << 14)
#define	US_CHMODE_REMOTE   (0x3 << 14)
#define	US_MSBF   (0x1 << 16)
#define	US_MODE9   (0x1 << 17)
#define	US_CKLO   (0x1 << 18)
#define	US_OVER   (0x1 << 19)
#define	US_INACK   (0x1 << 20)
#define	US_DSNACK   (0x1 << 21)
#define	US_VAR_SYNC   (0x1 << 22)
#define	US_MAX_ITER   (0x1 << 24)
#define	US_FILTER   (0x1 << 28)
#define	US_MANMODE   (0x1 << 29)
#define	US_MODSYNC   (0x1 << 30)
#define	US_ONEBIT   (0x1 << 31)
#define	US_RXRDY   (0x1 << 0)
#define	US_TXRDY   (0x1 << 1)
#define	US_RXBRK   (0x1 << 2)
#define	US_ENDRX   (0x1 << 3)
#define	US_ENDTX   (0x1 << 4)
#define	US_OVRE   (0x1 << 5)
#define	US_FRAME   (0x1 << 6)
#define	US_PARE   (0x1 << 7)
#define	US_TIMEOUT   (0x1 << 8)
#define	US_TXEMPTY   (0x1 << 9)
#define	US_ITERATION   (0x1 << 10)
#define	US_TXBUFE   (0x1 << 11)
#define	US_RXBUFF   (0x1 << 12)
#define	US_NACK   (0x1 << 13)
#define	US_RIIC   (0x1 << 16)
#define	US_DSRIC   (0x1 << 17)
#define	US_DCDIC   (0x1 << 18)
#define	US_CTSIC   (0x1 << 19)
#define	US_MANE   (0x1 << 20)
#define	US_RI   (0x1 << 20)
#define	US_DSR   (0x1 << 21)
#define	US_DCD   (0x1 << 22)
#define	US_CTS   (0x1 << 23)
#define	US_MANERR   (0x1 << 24)
#define	US_TX_PL   (0xF << 0)
#define	US_TX_PP   (0x3 << 8)
#define	US_TX_PP_ALL_ONE   (0x0 << 8)
#define	US_TX_PP_ALL_ZERO   (0x1 << 8)
#define	US_TX_PP_ZERO_ONE   (0x2 << 8)
#define	US_TX_PP_ONE_ZERO   (0x3 << 8)
#define	US_TX_MPOL   (0x1 << 12)
#define	US_RX_PL   (0xF << 16)
#define	US_RX_PP   (0x3 << 24)
#define	US_RX_PP_ALL_ONE   (0x0 << 24)
#define	US_RX_PP_ALL_ZERO   (0x1 << 24)
#define	US_RX_PP_ZERO_ONE   (0x2 << 24)
#define	US_RX_PP_ONE_ZERO   (0x3 << 24)
#define	US_RX_MPOL   (0x1 << 28)
#define	US_DRIFT   (0x1 << 30)
#define	AT91C_SSC_RXEN   (0x1 << 0)
#define	AT91C_SSC_RXDIS   (0x1 << 1)
#define	AT91C_SSC_TXEN   (0x1 << 8)
#define	AT91C_SSC_TXDIS   (0x1 << 9)
#define	AT91C_SSC_SWRST   (0x1 << 15)
#define	AT91C_SSC_CKS   (0x3 << 0)
#define	AT91C_SSC_CKS_DIV   (0x0)
#define	AT91C_SSC_CKS_TK   (0x1)
#define	AT91C_SSC_CKS_RK   (0x2)
#define	AT91C_SSC_CKO   (0x7 << 2)
#define	AT91C_SSC_CKO_NONE   (0x0 << 2)
#define	AT91C_SSC_CKO_CONTINOUS   (0x1 << 2)
#define	AT91C_SSC_CKO_DATA_TX   (0x2 << 2)
#define	AT91C_SSC_CKI   (0x1 << 5)
#define	AT91C_SSC_CKG   (0x3 << 6)
#define	AT91C_SSC_CKG_NONE   (0x0 << 6)
#define	AT91C_SSC_CKG_LOW   (0x1 << 6)
#define	AT91C_SSC_CKG_HIGH   (0x2 << 6)
#define	AT91C_SSC_START   (0xF << 8)
#define	AT91C_SSC_START_CONTINOUS   (0x0 << 8)
#define	AT91C_SSC_START_TX   (0x1 << 8)
#define	AT91C_SSC_START_LOW_RF   (0x2 << 8)
#define	AT91C_SSC_START_HIGH_RF   (0x3 << 8)
#define	AT91C_SSC_START_FALL_RF   (0x4 << 8)
#define	AT91C_SSC_START_RISE_RF   (0x5 << 8)
#define	AT91C_SSC_START_LEVEL_RF   (0x6 << 8)
#define	AT91C_SSC_START_EDGE_RF   (0x7 << 8)
#define	AT91C_SSC_START_0   (0x8 << 8)
#define	AT91C_SSC_STOP   (0x1 << 12)
#define	AT91C_SSC_STTDLY   (0xFF << 16)
#define	AT91C_SSC_PERIOD   (0xFF << 24)
#define	AT91C_SSC_DATLEN   (0x1F << 0)
#define	AT91C_SSC_LOOP   (0x1 << 5)
#define	AT91C_SSC_MSBF   (0x1 << 7)
#define	AT91C_SSC_DATNB   (0xF << 8)
#define	AT91C_SSC_FSLEN   (0xF << 16)
#define	AT91C_SSC_FSOS   (0x7 << 20)
#define	AT91C_SSC_FSOS_NONE   (0x0 << 20)
#define	AT91C_SSC_FSOS_NEGATIVE   (0x1 << 20)
#define	AT91C_SSC_FSOS_POSITIVE   (0x2 << 20)
#define	AT91C_SSC_FSOS_LOW   (0x3 << 20)
#define	AT91C_SSC_FSOS_HIGH   (0x4 << 20)
#define	AT91C_SSC_FSOS_TOGGLE   (0x5 << 20)
#define	AT91C_SSC_FSEDGE   (0x1 << 24)
#define	AT91C_SSC_DATDEF   (0x1 << 5)
#define	AT91C_SSC_FSDEN   (0x1 << 23)
#define	AT91C_SSC_TXRDY   (0x1 << 0)
#define	AT91C_SSC_TXEMPTY   (0x1 << 1)
#define	AT91C_SSC_ENDTX   (0x1 << 2)
#define	AT91C_SSC_TXBUFE   (0x1 << 3)
#define	AT91C_SSC_RXRDY   (0x1 << 4)
#define	AT91C_SSC_OVRUN   (0x1 << 5)
#define	AT91C_SSC_ENDRX   (0x1 << 6)
#define	AT91C_SSC_RXBUFF   (0x1 << 7)
#define	AT91C_SSC_CP0   (0x1 << 8)
#define	AT91C_SSC_CP1   (0x1 << 9)
#define	AT91C_SSC_TXSYN   (0x1 << 10)
#define	AT91C_SSC_RXSYN   (0x1 << 11)
#define	AT91C_SSC_TXENA   (0x1 << 16)
#define	AT91C_SSC_RXENA   (0x1 << 17)
#define	AT91C_PWMC_CPRE   (0xF << 0)
#define	AT91C_PWMC_CPRE_MCK   (0x0)
#define	AT91C_PWMC_CPRE_MCK_DIV_2   (0x1)
#define	AT91C_PWMC_CPRE_MCK_DIV_4   (0x2)
#define	AT91C_PWMC_CPRE_MCK_DIV_8   (0x3)
#define	AT91C_PWMC_CPRE_MCK_DIV_16   (0x4)
#define	AT91C_PWMC_CPRE_MCK_DIV_32   (0x5)
#define	AT91C_PWMC_CPRE_MCK_DIV_64   (0x6)
#define	AT91C_PWMC_CPRE_MCK_DIV_128   (0x7)
#define	AT91C_PWMC_CPRE_MCK_DIV_256   (0x8)
#define	AT91C_PWMC_CPRE_MCK_DIV_512   (0x9)
#define	AT91C_PWMC_CPRE_MCK_DIV_1024   (0xA)
#define	AT91C_PWMC_CPRE_MCKA   (0xB)
#define	AT91C_PWMC_CPRE_MCKB   (0xC)
#define	AT91C_PWMC_CALG   (0x1 << 8)
#define	AT91C_PWMC_CPOL   (0x1 << 9)
#define	AT91C_PWMC_CES   (0x1 << 10)
#define	AT91C_PWMC_DTE   (0x1 << 16)
#define	AT91C_PWMC_DTHI   (0x1 << 17)
#define	AT91C_PWMC_DTLI   (0x1 << 18)
#define	AT91C_PWMC_CDTY   (0xFFFFFF << 0)
#define	AT91C_PWMC_CDTYUPD   (0xFFFFFF << 0)
#define	AT91C_PWMC_CPRD   (0xFFFFFF << 0)
#define	AT91C_PWMC_CPRDUPD   (0xFFFFFF << 0)
#define	AT91C_PWMC_CCNT   (0xFFFFFF << 0)
#define	AT91C_PWMC_DTL   (0xFFFF << 0)
#define	AT91C_PWMC_DTH   (0xFFFF << 16)
#define	AT91C_PWMC_DTLUPD   (0xFFFF << 0)
#define	AT91C_PWMC_DTHUPD   (0xFFFF << 16)
#define	AT91C_PWMC_DIVA   (0xFF << 0)
#define	AT91C_PWMC_PREA   (0xF << 8)
#define	AT91C_PWMC_PREA_MCK   (0x0 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_2   (0x1 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_4   (0x2 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_8   (0x3 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_16   (0x4 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_32   (0x5 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_64   (0x6 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_128   (0x7 << 8)
#define	AT91C_PWMC_PREA_MCK_DIV_256   (0x8 << 8)
#define	AT91C_PWMC_DIVB   (0xFF << 16)
#define	AT91C_PWMC_PREB   (0xF << 24)
#define	AT91C_PWMC_PREB_MCK   (0x0 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_2   (0x1 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_4   (0x2 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_8   (0x3 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_16   (0x4 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_32   (0x5 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_64   (0x6 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_128   (0x7 << 24)
#define	AT91C_PWMC_PREB_MCK_DIV_256   (0x8 << 24)
#define	AT91C_PWMC_CLKSEL   (0x1 << 31)
#define	AT91C_PWMC_CHID0   (0x1 << 0)
#define	AT91C_PWMC_CHID1   (0x1 << 1)
#define	AT91C_PWMC_CHID2   (0x1 << 2)
#define	AT91C_PWMC_CHID3   (0x1 << 3)
#define	AT91C_PWMC_CHID4   (0x1 << 4)
#define	AT91C_PWMC_CHID5   (0x1 << 5)
#define	AT91C_PWMC_CHID6   (0x1 << 6)
#define	AT91C_PWMC_CHID7   (0x1 << 7)
#define	AT91C_PWMC_CHID8   (0x1 << 8)
#define	AT91C_PWMC_CHID9   (0x1 << 9)
#define	AT91C_PWMC_CHID10   (0x1 << 10)
#define	AT91C_PWMC_CHID11   (0x1 << 11)
#define	AT91C_PWMC_CHID12   (0x1 << 12)
#define	AT91C_PWMC_CHID13   (0x1 << 13)
#define	AT91C_PWMC_CHID14   (0x1 << 14)
#define	AT91C_PWMC_CHID15   (0x1 << 15)
#define	AT91C_PWMC_FCHID0   (0x1 << 16)
#define	AT91C_PWMC_FCHID1   (0x1 << 17)
#define	AT91C_PWMC_FCHID2   (0x1 << 18)
#define	AT91C_PWMC_FCHID3   (0x1 << 19)
#define	AT91C_PWMC_FCHID4   (0x1 << 20)
#define	AT91C_PWMC_FCHID5   (0x1 << 21)
#define	AT91C_PWMC_FCHID6   (0x1 << 22)
#define	AT91C_PWMC_FCHID7   (0x1 << 23)
#define	AT91C_PWMC_FCHID8   (0x1 << 24)
#define	AT91C_PWMC_FCHID9   (0x1 << 25)
#define	AT91C_PWMC_FCHID10   (0x1 << 26)
#define	AT91C_PWMC_FCHID11   (0x1 << 27)
#define	AT91C_PWMC_FCHID12   (0x1 << 28)
#define	AT91C_PWMC_FCHID13   (0x1 << 29)
#define	AT91C_PWMC_FCHID14   (0x1 << 30)
#define	AT91C_PWMC_FCHID15   (0x1 << 31)
#define	AT91C_PWMC_SYNC0   (0x1 << 0)
#define	AT91C_PWMC_SYNC1   (0x1 << 1)
#define	AT91C_PWMC_SYNC2   (0x1 << 2)
#define	AT91C_PWMC_SYNC3   (0x1 << 3)
#define	AT91C_PWMC_SYNC4   (0x1 << 4)
#define	AT91C_PWMC_SYNC5   (0x1 << 5)
#define	AT91C_PWMC_SYNC6   (0x1 << 6)
#define	AT91C_PWMC_SYNC7   (0x1 << 7)
#define	AT91C_PWMC_SYNC8   (0x1 << 8)
#define	AT91C_PWMC_SYNC9   (0x1 << 9)
#define	AT91C_PWMC_SYNC10   (0x1 << 10)
#define	AT91C_PWMC_SYNC11   (0x1 << 11)
#define	AT91C_PWMC_SYNC12   (0x1 << 12)
#define	AT91C_PWMC_SYNC13   (0x1 << 13)
#define	AT91C_PWMC_SYNC14   (0x1 << 14)
#define	AT91C_PWMC_SYNC15   (0x1 << 15)
#define	AT91C_PWMC_UPDM   (0x3 << 16)
#define	AT91C_PWMC_UPDM_MODE0   (0x0 << 16)
#define	AT91C_PWMC_UPDM_MODE1   (0x1 << 16)
#define	AT91C_PWMC_UPDM_MODE2   (0x2 << 16)
#define	AT91C_PWMC_UPDULOCK   (0x1 << 0)
#define	AT91C_PWMC_UPR   (0xF << 0)
#define	AT91C_PWMC_UPRCNT   (0xF << 4)
#define	AT91C_PWMC_UPVUPDAL   (0xF << 0)
#define	AT91C_PWMC_WRDY   (0x1 << 0)
#define	AT91C_PWMC_ENDTX   (0x1 << 1)
#define	AT91C_PWMC_TXBUFE   (0x1 << 2)
#define	AT91C_PWMC_UNRE   (0x1 << 3)
#define	AT91C_PWMC_CMPM0   (0x1 << 8)
#define	AT91C_PWMC_CMPM1   (0x1 << 9)
#define	AT91C_PWMC_CMPM2   (0x1 << 10)
#define	AT91C_PWMC_CMPM3   (0x1 << 11)
#define	AT91C_PWMC_CMPM4   (0x1 << 12)
#define	AT91C_PWMC_CMPM5   (0x1 << 13)
#define	AT91C_PWMC_CMPM6   (0x1 << 14)
#define	AT91C_PWMC_CMPM7   (0x1 << 15)
#define	AT91C_PWMC_CMPU0   (0x1 << 16)
#define	AT91C_PWMC_CMPU1   (0x1 << 17)
#define	AT91C_PWMC_CMPU2   (0x1 << 18)
#define	AT91C_PWMC_CMPU3   (0x1 << 19)
#define	AT91C_PWMC_CMPU4   (0x1 << 20)
#define	AT91C_PWMC_CMPU5   (0x1 << 21)
#define	AT91C_PWMC_CMPU6   (0x1 << 22)
#define	AT91C_PWMC_CMPU7   (0x1 << 23)
#define	AT91C_PWMC_OOVH0   (0x1 << 0)
#define	AT91C_PWMC_OOVH1   (0x1 << 1)
#define	AT91C_PWMC_OOVH2   (0x1 << 2)
#define	AT91C_PWMC_OOVH3   (0x1 << 3)
#define	AT91C_PWMC_OOVH4   (0x1 << 4)
#define	AT91C_PWMC_OOVH5   (0x1 << 5)
#define	AT91C_PWMC_OOVH6   (0x1 << 6)
#define	AT91C_PWMC_OOVH7   (0x1 << 7)
#define	AT91C_PWMC_OOVH8   (0x1 << 8)
#define	AT91C_PWMC_OOVH9   (0x1 << 9)
#define	AT91C_PWMC_OOVH10   (0x1 << 10)
#define	AT91C_PWMC_OOVH11   (0x1 << 11)
#define	AT91C_PWMC_OOVH12   (0x1 << 12)
#define	AT91C_PWMC_OOVH13   (0x1 << 13)
#define	AT91C_PWMC_OOVH14   (0x1 << 14)
#define	AT91C_PWMC_OOVH15   (0x1 << 15)
#define	AT91C_PWMC_OOVL0   (0x1 << 16)
#define	AT91C_PWMC_OOVL1   (0x1 << 17)
#define	AT91C_PWMC_OOVL2   (0x1 << 18)
#define	AT91C_PWMC_OOVL3   (0x1 << 19)
#define	AT91C_PWMC_OOVL4   (0x1 << 20)
#define	AT91C_PWMC_OOVL5   (0x1 << 21)
#define	AT91C_PWMC_OOVL6   (0x1 << 22)
#define	AT91C_PWMC_OOVL7   (0x1 << 23)
#define	AT91C_PWMC_OOVL8   (0x1 << 24)
#define	AT91C_PWMC_OOVL9   (0x1 << 25)
#define	AT91C_PWMC_OOVL10   (0x1 << 26)
#define	AT91C_PWMC_OOVL11   (0x1 << 27)
#define	AT91C_PWMC_OOVL12   (0x1 << 28)
#define	AT91C_PWMC_OOVL13   (0x1 << 29)
#define	AT91C_PWMC_OOVL14   (0x1 << 30)
#define	AT91C_PWMC_OOVL15   (0x1 << 31)
#define	AT91C_PWMC_OSH0   (0x1 << 0)
#define	AT91C_PWMC_OSH1   (0x1 << 1)
#define	AT91C_PWMC_OSH2   (0x1 << 2)
#define	AT91C_PWMC_OSH3   (0x1 << 3)
#define	AT91C_PWMC_OSH4   (0x1 << 4)
#define	AT91C_PWMC_OSH5   (0x1 << 5)
#define	AT91C_PWMC_OSH6   (0x1 << 6)
#define	AT91C_PWMC_OSH7   (0x1 << 7)
#define	AT91C_PWMC_OSH8   (0x1 << 8)
#define	AT91C_PWMC_OSH9   (0x1 << 9)
#define	AT91C_PWMC_OSH10   (0x1 << 10)
#define	AT91C_PWMC_OSH11   (0x1 << 11)
#define	AT91C_PWMC_OSH12   (0x1 << 12)
#define	AT91C_PWMC_OSH13   (0x1 << 13)
#define	AT91C_PWMC_OSH14   (0x1 << 14)
#define	AT91C_PWMC_OSH15   (0x1 << 15)
#define	AT91C_PWMC_OSL0   (0x1 << 16)
#define	AT91C_PWMC_OSL1   (0x1 << 17)
#define	AT91C_PWMC_OSL2   (0x1 << 18)
#define	AT91C_PWMC_OSL3   (0x1 << 19)
#define	AT91C_PWMC_OSL4   (0x1 << 20)
#define	AT91C_PWMC_OSL5   (0x1 << 21)
#define	AT91C_PWMC_OSL6   (0x1 << 22)
#define	AT91C_PWMC_OSL7   (0x1 << 23)
#define	AT91C_PWMC_OSL8   (0x1 << 24)
#define	AT91C_PWMC_OSL9   (0x1 << 25)
#define	AT91C_PWMC_OSL10   (0x1 << 26)
#define	AT91C_PWMC_OSL11   (0x1 << 27)
#define	AT91C_PWMC_OSL12   (0x1 << 28)
#define	AT91C_PWMC_OSL13   (0x1 << 29)
#define	AT91C_PWMC_OSL14   (0x1 << 30)
#define	AT91C_PWMC_OSL15   (0x1 << 31)
#define	AT91C_PWMC_OSSH0   (0x1 << 0)
#define	AT91C_PWMC_OSSH1   (0x1 << 1)
#define	AT91C_PWMC_OSSH2   (0x1 << 2)
#define	AT91C_PWMC_OSSH3   (0x1 << 3)
#define	AT91C_PWMC_OSSH4   (0x1 << 4)
#define	AT91C_PWMC_OSSH5   (0x1 << 5)
#define	AT91C_PWMC_OSSH6   (0x1 << 6)
#define	AT91C_PWMC_OSSH7   (0x1 << 7)
#define	AT91C_PWMC_OSSH8   (0x1 << 8)
#define	AT91C_PWMC_OSSH9   (0x1 << 9)
#define	AT91C_PWMC_OSSH10   (0x1 << 10)
#define	AT91C_PWMC_OSSH11   (0x1 << 11)
#define	AT91C_PWMC_OSSH12   (0x1 << 12)
#define	AT91C_PWMC_OSSH13   (0x1 << 13)
#define	AT91C_PWMC_OSSH14   (0x1 << 14)
#define	AT91C_PWMC_OSSH15   (0x1 << 15)
#define	AT91C_PWMC_OSSL0   (0x1 << 16)
#define	AT91C_PWMC_OSSL1   (0x1 << 17)
#define	AT91C_PWMC_OSSL2   (0x1 << 18)
#define	AT91C_PWMC_OSSL3   (0x1 << 19)
#define	AT91C_PWMC_OSSL4   (0x1 << 20)
#define	AT91C_PWMC_OSSL5   (0x1 << 21)
#define	AT91C_PWMC_OSSL6   (0x1 << 22)
#define	AT91C_PWMC_OSSL7   (0x1 << 23)
#define	AT91C_PWMC_OSSL8   (0x1 << 24)
#define	AT91C_PWMC_OSSL9   (0x1 << 25)
#define	AT91C_PWMC_OSSL10   (0x1 << 26)
#define	AT91C_PWMC_OSSL11   (0x1 << 27)
#define	AT91C_PWMC_OSSL12   (0x1 << 28)
#define	AT91C_PWMC_OSSL13   (0x1 << 29)
#define	AT91C_PWMC_OSSL14   (0x1 << 30)
#define	AT91C_PWMC_OSSL15   (0x1 << 31)
#define	AT91C_PWMC_OSCH0   (0x1 << 0)
#define	AT91C_PWMC_OSCH1   (0x1 << 1)
#define	AT91C_PWMC_OSCH2   (0x1 << 2)
#define	AT91C_PWMC_OSCH3   (0x1 << 3)
#define	AT91C_PWMC_OSCH4   (0x1 << 4)
#define	AT91C_PWMC_OSCH5   (0x1 << 5)
#define	AT91C_PWMC_OSCH6   (0x1 << 6)
#define	AT91C_PWMC_OSCH7   (0x1 << 7)
#define	AT91C_PWMC_OSCH8   (0x1 << 8)
#define	AT91C_PWMC_OSCH9   (0x1 << 9)
#define	AT91C_PWMC_OSCH10   (0x1 << 10)
#define	AT91C_PWMC_OSCH11   (0x1 << 11)
#define	AT91C_PWMC_OSCH12   (0x1 << 12)
#define	AT91C_PWMC_OSCH13   (0x1 << 13)
#define	AT91C_PWMC_OSCH14   (0x1 << 14)
#define	AT91C_PWMC_OSCH15   (0x1 << 15)
#define	AT91C_PWMC_OSCL0   (0x1 << 16)
#define	AT91C_PWMC_OSCL1   (0x1 << 17)
#define	AT91C_PWMC_OSCL2   (0x1 << 18)
#define	AT91C_PWMC_OSCL3   (0x1 << 19)
#define	AT91C_PWMC_OSCL4   (0x1 << 20)
#define	AT91C_PWMC_OSCL5   (0x1 << 21)
#define	AT91C_PWMC_OSCL6   (0x1 << 22)
#define	AT91C_PWMC_OSCL7   (0x1 << 23)
#define	AT91C_PWMC_OSCL8   (0x1 << 24)
#define	AT91C_PWMC_OSCL9   (0x1 << 25)
#define	AT91C_PWMC_OSCL10   (0x1 << 26)
#define	AT91C_PWMC_OSCL11   (0x1 << 27)
#define	AT91C_PWMC_OSCL12   (0x1 << 28)
#define	AT91C_PWMC_OSCL13   (0x1 << 29)
#define	AT91C_PWMC_OSCL14   (0x1 << 30)
#define	AT91C_PWMC_OSCL15   (0x1 << 31)
#define	AT91C_PWMC_OSSUPDH0   (0x1 << 0)
#define	AT91C_PWMC_OSSUPDH1   (0x1 << 1)
#define	AT91C_PWMC_OSSUPDH2   (0x1 << 2)
#define	AT91C_PWMC_OSSUPDH3   (0x1 << 3)
#define	AT91C_PWMC_OSSUPDH4   (0x1 << 4)
#define	AT91C_PWMC_OSSUPDH5   (0x1 << 5)
#define	AT91C_PWMC_OSSUPDH6   (0x1 << 6)
#define	AT91C_PWMC_OSSUPDH7   (0x1 << 7)
#define	AT91C_PWMC_OSSUPDH8   (0x1 << 8)
#define	AT91C_PWMC_OSSUPDH9   (0x1 << 9)
#define	AT91C_PWMC_OSSUPDH10   (0x1 << 10)
#define	AT91C_PWMC_OSSUPDH11   (0x1 << 11)
#define	AT91C_PWMC_OSSUPDH12   (0x1 << 12)
#define	AT91C_PWMC_OSSUPDH13   (0x1 << 13)
#define	AT91C_PWMC_OSSUPDH14   (0x1 << 14)
#define	AT91C_PWMC_OSSUPDH15   (0x1 << 15)
#define	AT91C_PWMC_OSSUPDL0   (0x1 << 16)
#define	AT91C_PWMC_OSSUPDL1   (0x1 << 17)
#define	AT91C_PWMC_OSSUPDL2   (0x1 << 18)
#define	AT91C_PWMC_OSSUPDL3   (0x1 << 19)
#define	AT91C_PWMC_OSSUPDL4   (0x1 << 20)
#define	AT91C_PWMC_OSSUPDL5   (0x1 << 21)
#define	AT91C_PWMC_OSSUPDL6   (0x1 << 22)
#define	AT91C_PWMC_OSSUPDL7   (0x1 << 23)
#define	AT91C_PWMC_OSSUPDL8   (0x1 << 24)
#define	AT91C_PWMC_OSSUPDL9   (0x1 << 25)
#define	AT91C_PWMC_OSSUPDL10   (0x1 << 26)
#define	AT91C_PWMC_OSSUPDL11   (0x1 << 27)
#define	AT91C_PWMC_OSSUPDL12   (0x1 << 28)
#define	AT91C_PWMC_OSSUPDL13   (0x1 << 29)
#define	AT91C_PWMC_OSSUPDL14   (0x1 << 30)
#define	AT91C_PWMC_OSSUPDL15   (0x1 << 31)
#define	AT91C_PWMC_OSCUPDH0   (0x1 << 0)
#define	AT91C_PWMC_OSCUPDH1   (0x1 << 1)
#define	AT91C_PWMC_OSCUPDH2   (0x1 << 2)
#define	AT91C_PWMC_OSCUPDH3   (0x1 << 3)
#define	AT91C_PWMC_OSCUPDH4   (0x1 << 4)
#define	AT91C_PWMC_OSCUPDH5   (0x1 << 5)
#define	AT91C_PWMC_OSCUPDH6   (0x1 << 6)
#define	AT91C_PWMC_OSCUPDH7   (0x1 << 7)
#define	AT91C_PWMC_OSCUPDH8   (0x1 << 8)
#define	AT91C_PWMC_OSCUPDH9   (0x1 << 9)
#define	AT91C_PWMC_OSCUPDH10   (0x1 << 10)
#define	AT91C_PWMC_OSCUPDH11   (0x1 << 11)
#define	AT91C_PWMC_OSCUPDH12   (0x1 << 12)
#define	AT91C_PWMC_OSCUPDH13   (0x1 << 13)
#define	AT91C_PWMC_OSCUPDH14   (0x1 << 14)
#define	AT91C_PWMC_OSCUPDH15   (0x1 << 15)
#define	AT91C_PWMC_OSCUPDL0   (0x1 << 16)
#define	AT91C_PWMC_OSCUPDL1   (0x1 << 17)
#define	AT91C_PWMC_OSCUPDL2   (0x1 << 18)
#define	AT91C_PWMC_OSCUPDL3   (0x1 << 19)
#define	AT91C_PWMC_OSCUPDL4   (0x1 << 20)
#define	AT91C_PWMC_OSCUPDL5   (0x1 << 21)
#define	AT91C_PWMC_OSCUPDL6   (0x1 << 22)
#define	AT91C_PWMC_OSCUPDL7   (0x1 << 23)
#define	AT91C_PWMC_OSCUPDL8   (0x1 << 24)
#define	AT91C_PWMC_OSCUPDL9   (0x1 << 25)
#define	AT91C_PWMC_OSCUPDL10   (0x1 << 26)
#define	AT91C_PWMC_OSCUPDL11   (0x1 << 27)
#define	AT91C_PWMC_OSCUPDL12   (0x1 << 28)
#define	AT91C_PWMC_OSCUPDL13   (0x1 << 29)
#define	AT91C_PWMC_OSCUPDL14   (0x1 << 30)
#define	AT91C_PWMC_OSCUPDL15   (0x1 << 31)
#define	AT91C_PWMC_FPOL0   (0x1 << 0)
#define	AT91C_PWMC_FPOL1   (0x1 << 1)
#define	AT91C_PWMC_FPOL2   (0x1 << 2)
#define	AT91C_PWMC_FPOL3   (0x1 << 3)
#define	AT91C_PWMC_FPOL4   (0x1 << 4)
#define	AT91C_PWMC_FPOL5   (0x1 << 5)
#define	AT91C_PWMC_FPOL6   (0x1 << 6)
#define	AT91C_PWMC_FPOL7   (0x1 << 7)
#define	AT91C_PWMC_FMOD0   (0x1 << 8)
#define	AT91C_PWMC_FMOD1   (0x1 << 9)
#define	AT91C_PWMC_FMOD2   (0x1 << 10)
#define	AT91C_PWMC_FMOD3   (0x1 << 11)
#define	AT91C_PWMC_FMOD4   (0x1 << 12)
#define	AT91C_PWMC_FMOD5   (0x1 << 13)
#define	AT91C_PWMC_FMOD6   (0x1 << 14)
#define	AT91C_PWMC_FMOD7   (0x1 << 15)
#define	AT91C_PWMC_FFIL00   (0x1 << 16)
#define	AT91C_PWMC_FFIL01   (0x1 << 17)
#define	AT91C_PWMC_FFIL02   (0x1 << 18)
#define	AT91C_PWMC_FFIL03   (0x1 << 19)
#define	AT91C_PWMC_FFIL04   (0x1 << 20)
#define	AT91C_PWMC_FFIL05   (0x1 << 21)
#define	AT91C_PWMC_FFIL06   (0x1 << 22)
#define	AT91C_PWMC_FFIL07   (0x1 << 23)
#define	AT91C_PWMC_FIV0   (0x1 << 0)
#define	AT91C_PWMC_FIV1   (0x1 << 1)
#define	AT91C_PWMC_FIV2   (0x1 << 2)
#define	AT91C_PWMC_FIV3   (0x1 << 3)
#define	AT91C_PWMC_FIV4   (0x1 << 4)
#define	AT91C_PWMC_FIV5   (0x1 << 5)
#define	AT91C_PWMC_FIV6   (0x1 << 6)
#define	AT91C_PWMC_FIV7   (0x1 << 7)
#define	AT91C_PWMC_FS0   (0x1 << 8)
#define	AT91C_PWMC_FS1   (0x1 << 9)
#define	AT91C_PWMC_FS2   (0x1 << 10)
#define	AT91C_PWMC_FS3   (0x1 << 11)
#define	AT91C_PWMC_FS4   (0x1 << 12)
#define	AT91C_PWMC_FS5   (0x1 << 13)
#define	AT91C_PWMC_FS6   (0x1 << 14)
#define	AT91C_PWMC_FS7   (0x1 << 15)
#define	AT91C_PWMC_FCLR0   (0x1 << 0)
#define	AT91C_PWMC_FCLR1   (0x1 << 1)
#define	AT91C_PWMC_FCLR2   (0x1 << 2)
#define	AT91C_PWMC_FCLR3   (0x1 << 3)
#define	AT91C_PWMC_FCLR4   (0x1 << 4)
#define	AT91C_PWMC_FCLR5   (0x1 << 5)
#define	AT91C_PWMC_FCLR6   (0x1 << 6)
#define	AT91C_PWMC_FCLR7   (0x1 << 7)
#define	AT91C_PWMC_FPVH0   (0x1 << 0)
#define	AT91C_PWMC_FPVH1   (0x1 << 1)
#define	AT91C_PWMC_FPVH2   (0x1 << 2)
#define	AT91C_PWMC_FPVH3   (0x1 << 3)
#define	AT91C_PWMC_FPVH4   (0x1 << 4)
#define	AT91C_PWMC_FPVH5   (0x1 << 5)
#define	AT91C_PWMC_FPVH6   (0x1 << 6)
#define	AT91C_PWMC_FPVH7   (0x1 << 7)
#define	AT91C_PWMC_FPVL0   (0x1 << 16)
#define	AT91C_PWMC_FPVL1   (0x1 << 17)
#define	AT91C_PWMC_FPVL2   (0x1 << 18)
#define	AT91C_PWMC_FPVL3   (0x1 << 19)
#define	AT91C_PWMC_FPVL4   (0x1 << 20)
#define	AT91C_PWMC_FPVL5   (0x1 << 21)
#define	AT91C_PWMC_FPVL6   (0x1 << 22)
#define	AT91C_PWMC_FPVL7   (0x1 << 23)
#define	AT91C_PWMC_FPE0   (0xFF << 0)
#define	AT91C_PWMC_FPE1   (0xFF << 8)
#define	AT91C_PWMC_FPE2   (0xFF << 16)
#define	AT91C_PWMC_FPE3   (0xFF << 24)
#define	AT91C_PWMC_FPE4   (0xFF << 0)
#define	AT91C_PWMC_FPE5   (0xFF << 8)
#define	AT91C_PWMC_FPE6   (0xFF << 16)
#define	AT91C_PWMC_FPE7   (0xFF << 24)
#define	AT91C_PWMC_FPE8   (0xFF << 0)
#define	AT91C_PWMC_FPE9   (0xFF << 8)
#define	AT91C_PWMC_FPE10   (0xFF << 16)
#define	AT91C_PWMC_FPE11   (0xFF << 24)
#define	AT91C_PWMC_FPE12   (0xFF << 0)
#define	AT91C_PWMC_FPE13   (0xFF << 8)
#define	AT91C_PWMC_FPE14   (0xFF << 16)
#define	AT91C_PWMC_FPE15   (0xFF << 24)
#define	AT91C_PWMC_L0CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L0CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L0CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L0CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L0CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L0CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L0CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L0CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L1CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L1CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L1CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L1CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L1CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L1CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L1CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L1CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L2CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L2CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L2CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L2CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L2CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L2CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L2CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L2CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L3CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L3CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L3CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L3CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L3CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L3CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L3CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L3CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L4CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L4CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L4CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L4CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L4CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L4CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L4CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L4CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L5CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L5CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L5CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L5CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L5CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L5CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L5CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L5CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L6CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L6CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L6CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L6CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L6CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L6CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L6CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L6CSEL7   (0x1 << 7)
#define	AT91C_PWMC_L7CSEL0   (0x1 << 0)
#define	AT91C_PWMC_L7CSEL1   (0x1 << 1)
#define	AT91C_PWMC_L7CSEL2   (0x1 << 2)
#define	AT91C_PWMC_L7CSEL3   (0x1 << 3)
#define	AT91C_PWMC_L7CSEL4   (0x1 << 4)
#define	AT91C_PWMC_L7CSEL5   (0x1 << 5)
#define	AT91C_PWMC_L7CSEL6   (0x1 << 6)
#define	AT91C_PWMC_L7CSEL7   (0x1 << 7)
#define	AT91C_PWMC_WPCMD   (0x3 << 0)
#define	AT91C_PWMC_WPRG0   (0x1 << 2)
#define	AT91C_PWMC_WPRG1   (0x1 << 3)
#define	AT91C_PWMC_WPRG2   (0x1 << 4)
#define	AT91C_PWMC_WPRG3   (0x1 << 5)
#define	AT91C_PWMC_WPRG4   (0x1 << 6)
#define	AT91C_PWMC_WPRG5   (0x1 << 7)
#define	AT91C_PWMC_WPKEY   (0xFFFFFF << 8)
#define	AT91C_PWMC_WPSWS0   (0x1 << 0)
#define	AT91C_PWMC_WPSWS1   (0x1 << 1)
#define	AT91C_PWMC_WPSWS2   (0x1 << 2)
#define	AT91C_PWMC_WPSWS3   (0x1 << 3)
#define	AT91C_PWMC_WPSWS4   (0x1 << 4)
#define	AT91C_PWMC_WPSWS5   (0x1 << 5)
#define	AT91C_PWMC_WPVS   (0x1 << 7)
#define	AT91C_PWMC_WPHWS0   (0x1 << 8)
#define	AT91C_PWMC_WPHWS1   (0x1 << 9)
#define	AT91C_PWMC_WPHWS2   (0x1 << 10)
#define	AT91C_PWMC_WPHWS3   (0x1 << 11)
#define	AT91C_PWMC_WPHWS4   (0x1 << 12)
#define	AT91C_PWMC_WPHWS5   (0x1 << 13)
#define	AT91C_PWMC_WPVSRC   (0xFFFF << 16)
#define	AT91C_PWMC_CV   (0xFFFFFF << 0)
#define	AT91C_PWMC_CVM   (0x1 << 24)
#define	AT91C_PWMC_CVUPD   (0xFFFFFF << 0)
#define	AT91C_PWMC_CVMUPD   (0x1 << 24)
#define	AT91C_PWMC_CEN   (0x1 << 0)
#define	AT91C_PWMC_CTR   (0xF << 4)
#define	AT91C_PWMC_CPR   (0xF << 8)
#define	AT91C_PWMC_CPRCNT   (0xF << 12)
#define	AT91C_PWMC_CUPR   (0xF << 16)
#define	AT91C_PWMC_CUPRCNT   (0xF << 20)
#define	AT91C_PWMC_CENUPD   (0x1 << 0)
#define	AT91C_PWMC_CTRUPD   (0xF << 4)
#define	AT91C_PWMC_CPRUPD   (0xF << 8)
#define	AT91C_PWMC_CUPRUPD   (0xF << 16)
#define	AT91C_SPI_SPIEN   (0x1 << 0)
#define	AT91C_SPI_SPIDIS   (0x1 << 1)
#define	AT91C_SPI_SWRST   (0x1 << 7)
#define	AT91C_SPI_LASTXFER   (0x1 << 24)
#define	AT91C_SPI_MSTR   (0x1 << 0)
#define	AT91C_SPI_PS   (0x1 << 1)
#define	AT91C_SPI_PS_FIXED   (0x0 << 1)
#define	AT91C_SPI_PS_VARIABLE   (0x1 << 1)
#define	AT91C_SPI_PCSDEC   (0x1 << 2)
#define	AT91C_SPI_FDIV   (0x1 << 3)
#define	AT91C_SPI_MODFDIS   (0x1 << 4)
#define	AT91C_SPI_LLB   (0x1 << 7)
#define	AT91C_SPI_PCS   (0xF << 16)
#define	AT91C_SPI_DLYBCS   (0xFF << 24)
#define	AT91C_SPI_RD   (0xFFFF << 0)
#define	AT91C_SPI_RPCS   (0xF << 16)
#define	AT91C_SPI_TD   (0xFFFF << 0)
#define	AT91C_SPI_TPCS   (0xF << 16)
#define	AT91C_SPI_RDRF   (0x1 << 0)
#define	AT91C_SPI_TDRE   (0x1 << 1)
#define	AT91C_SPI_MODF   (0x1 << 2)
#define	AT91C_SPI_OVRES   (0x1 << 3)
#define	AT91C_SPI_ENDRX   (0x1 << 4)
#define	AT91C_SPI_ENDTX   (0x1 << 5)
#define	AT91C_SPI_RXBUFF   (0x1 << 6)
#define	AT91C_SPI_TXBUFE   (0x1 << 7)
#define	AT91C_SPI_NSSR   (0x1 << 8)
#define	AT91C_SPI_TXEMPTY   (0x1 << 9)
#define	AT91C_SPI_SPIENS   (0x1 << 16)
#define	AT91C_SPI_CPOL   (0x1 << 0)
#define	AT91C_SPI_NCPHA   (0x1 << 1)
#define	AT91C_SPI_CSNAAT   (0x1 << 2)
#define	AT91C_SPI_CSAAT   (0x1 << 3)
#define	AT91C_SPI_BITS   (0xF << 4)
#define	AT91C_SPI_BITS_8   (0x0 << 4)
#define	AT91C_SPI_BITS_9   (0x1 << 4)
#define	AT91C_SPI_BITS_10   (0x2 << 4)
#define	AT91C_SPI_BITS_11   (0x3 << 4)
#define	AT91C_SPI_BITS_12   (0x4 << 4)
#define	AT91C_SPI_BITS_13   (0x5 << 4)
#define	AT91C_SPI_BITS_14   (0x6 << 4)
#define	AT91C_SPI_BITS_15   (0x7 << 4)
#define	AT91C_SPI_BITS_16   (0x8 << 4)
#define	AT91C_SPI_SCBR   (0xFF << 8)
#define	AT91C_SPI_DLYBS   (0xFF << 16)
#define	AT91C_SPI_DLYBCT   (0xFF << 24)
#define	AT91C_UDPHS_EPT_SIZE   (0x7 << 0)
#define	AT91C_UDPHS_EPT_SIZE_8   (0x0)
#define	AT91C_UDPHS_EPT_SIZE_16   (0x1)
#define	AT91C_UDPHS_EPT_SIZE_32   (0x2)
#define	AT91C_UDPHS_EPT_SIZE_64   (0x3)
#define	AT91C_UDPHS_EPT_SIZE_128   (0x4)
#define	AT91C_UDPHS_EPT_SIZE_256   (0x5)
#define	AT91C_UDPHS_EPT_SIZE_512   (0x6)
#define	AT91C_UDPHS_EPT_SIZE_1024   (0x7)
#define	AT91C_UDPHS_EPT_DIR   (0x1 << 3)
#define	AT91C_UDPHS_EPT_DIR_OUT   (0x0 << 3)
#define	AT91C_UDPHS_EPT_DIR_IN   (0x1 << 3)
#define	AT91C_UDPHS_EPT_TYPE   (0x3 << 4)
#define	AT91C_UDPHS_EPT_TYPE_CTL_EPT   (0x0 << 4)
#define	AT91C_UDPHS_EPT_TYPE_ISO_EPT   (0x1 << 4)
#define	AT91C_UDPHS_EPT_TYPE_BUL_EPT   (0x2 << 4)
#define	AT91C_UDPHS_EPT_TYPE_INT_EPT   (0x3 << 4)
#define	AT91C_UDPHS_BK_NUMBER   (0x3 << 6)
#define	AT91C_UDPHS_BK_NUMBER_0   (0x0 << 6)
#define	AT91C_UDPHS_BK_NUMBER_1   (0x1 << 6)
#define	AT91C_UDPHS_BK_NUMBER_2   (0x2 << 6)
#define	AT91C_UDPHS_BK_NUMBER_3   (0x3 << 6)
#define	AT91C_UDPHS_NB_TRANS   (0x3 << 8)
#define	AT91C_UDPHS_EPT_MAPD   (0x1 << 31)
#define	AT91C_UDPHS_EPT_ENABL   (0x1 << 0)
#define	AT91C_UDPHS_AUTO_VALID   (0x1 << 1)
#define	AT91C_UDPHS_INTDIS_DMA   (0x1 << 3)
#define	AT91C_UDPHS_NYET_DIS   (0x1 << 4)
#define	AT91C_UDPHS_DATAX_RX   (0x1 << 6)
#define	AT91C_UDPHS_MDATA_RX   (0x1 << 7)
#define	AT91C_UDPHS_ERR_OVFLW   (0x1 << 8)
#define	AT91C_UDPHS_RX_BK_RDY   (0x1 << 9)
#define	AT91C_UDPHS_TX_COMPLT   (0x1 << 10)
#define	AT91C_UDPHS_ERR_TRANS   (0x1 << 11)
#define	AT91C_UDPHS_TX_PK_RDY   (0x1 << 11)
#define	AT91C_UDPHS_RX_SETUP   (0x1 << 12)
#define	AT91C_UDPHS_ERR_FL_ISO   (0x1 << 12)
#define	AT91C_UDPHS_STALL_SNT   (0x1 << 13)
#define	AT91C_UDPHS_ERR_CRISO   (0x1 << 13)
#define	AT91C_UDPHS_NAK_IN   (0x1 << 14)
#define	AT91C_UDPHS_NAK_OUT   (0x1 << 15)
#define	AT91C_UDPHS_BUSY_BANK   (0x1 << 18)
#define	AT91C_UDPHS_SHRT_PCKT   (0x1 << 31)
#define	AT91C_UDPHS_EPT_DISABL   (0x1 << 0)
#define	AT91C_UDPHS_FRCESTALL   (0x1 << 5)
#define	AT91C_UDPHS_KILL_BANK   (0x1 << 9)
#define	AT91C_UDPHS_TOGGLESQ   (0x1 << 6)
#define	AT91C_UDPHS_TOGGLESQ_STA   (0x3 << 6)
#define	AT91C_UDPHS_TOGGLESQ_STA_00   (0x0 << 6)
#define	AT91C_UDPHS_TOGGLESQ_STA_01   (0x1 << 6)
#define	AT91C_UDPHS_TOGGLESQ_STA_10   (0x2 << 6)
#define	AT91C_UDPHS_TOGGLESQ_STA_11   (0x3 << 6)
#define	AT91C_UDPHS_CONTROL_DIR   (0x3 << 16)
#define	AT91C_UDPHS_CONTROL_DIR_00   (0x0 << 16)
#define	AT91C_UDPHS_CONTROL_DIR_01   (0x1 << 16)
#define	AT91C_UDPHS_CONTROL_DIR_10   (0x2 << 16)
#define	AT91C_UDPHS_CONTROL_DIR_11   (0x3 << 16)
#define	AT91C_UDPHS_CURRENT_BANK   (0x3 << 16)
#define	AT91C_UDPHS_CURRENT_BANK_00   (0x0 << 16)
#define	AT91C_UDPHS_CURRENT_BANK_01   (0x1 << 16)
#define	AT91C_UDPHS_CURRENT_BANK_10   (0x2 << 16)
#define	AT91C_UDPHS_CURRENT_BANK_11   (0x3 << 16)
#define	AT91C_UDPHS_BUSY_BANK_STA   (0x3 << 18)
#define	AT91C_UDPHS_BUSY_BANK_STA_00   (0x0 << 18)
#define	AT91C_UDPHS_BUSY_BANK_STA_01   (0x1 << 18)
#define	AT91C_UDPHS_BUSY_BANK_STA_10   (0x2 << 18)
#define	AT91C_UDPHS_BUSY_BANK_STA_11   (0x3 << 18)
#define	AT91C_UDPHS_BYTE_COUNT   (0x7FF << 20)
#define	AT91C_UDPHS_NXT_DSC_ADD   (0xFFFFFFF << 4)
#define	AT91C_UDPHS_BUFF_ADD   (0x0 << 0)
#define	AT91C_UDPHS_CHANN_ENB   (0x1 << 0)
#define	AT91C_UDPHS_LDNXT_DSC   (0x1 << 1)
#define	AT91C_UDPHS_END_TR_EN   (0x1 << 2)
#define	AT91C_UDPHS_END_B_EN   (0x1 << 3)
#define	AT91C_UDPHS_END_TR_IT   (0x1 << 4)
#define	AT91C_UDPHS_END_BUFFIT   (0x1 << 5)
#define	AT91C_UDPHS_DESC_LD_IT   (0x1 << 6)
#define	AT91C_UDPHS_BURST_LCK   (0x1 << 7)
#define	AT91C_UDPHS_BUFF_LENGTH   (0xFFFF << 16)
#define	AT91C_UDPHS_CHANN_ACT   (0x1 << 1)
#define	AT91C_UDPHS_END_TR_ST   (0x1 << 4)
#define	AT91C_UDPHS_END_BF_ST   (0x1 << 5)
#define	AT91C_UDPHS_DESC_LDST   (0x1 << 6)
#define	AT91C_UDPHS_BUFF_COUNT   (0xFFFF << 16)
#define	AT91C_UDPHS_DEV_ADDR   (0x7F << 0)
#define	AT91C_UDPHS_FADDR_EN   (0x1 << 7)
#define	AT91C_UDPHS_EN_UDPHS   (0x1 << 8)
#define	AT91C_UDPHS_DETACH   (0x1 << 9)
#define	AT91C_UDPHS_REWAKEUP   (0x1 << 10)
#define	AT91C_UDPHS_PULLD_DIS   (0x1 << 11)
#define	AT91C_UDPHS_MICRO_FRAME_NUM   (0x7 << 0)
#define	AT91C_UDPHS_FRAME_NUMBER   (0x7FF << 3)
#define	AT91C_UDPHS_FNUM_ERR   (0x1 << 31)
#define	AT91C_UDPHS_DET_SUSPD   (0x1 << 1)
#define	AT91C_UDPHS_MICRO_SOF   (0x1 << 2)
#define	AT91C_UDPHS_IEN_SOF   (0x1 << 3)
#define	AT91C_UDPHS_ENDRESET   (0x1 << 4)
#define	AT91C_UDPHS_WAKE_UP   (0x1 << 5)
#define	AT91C_UDPHS_ENDOFRSM   (0x1 << 6)
#define	AT91C_UDPHS_UPSTR_RES   (0x1 << 7)
#define	AT91C_UDPHS_EPT_INT_0   (0x1 << 8)
#define	AT91C_UDPHS_EPT_INT_1   (0x1 << 9)
#define	AT91C_UDPHS_EPT_INT_2   (0x1 << 10)
#define	AT91C_UDPHS_EPT_INT_3   (0x1 << 11)
#define	AT91C_UDPHS_EPT_INT_4   (0x1 << 12)
#define	AT91C_UDPHS_EPT_INT_5   (0x1 << 13)
#define	AT91C_UDPHS_EPT_INT_6   (0x1 << 14)
#define	AT91C_UDPHS_DMA_INT_1   (0x1 << 25)
#define	AT91C_UDPHS_DMA_INT_2   (0x1 << 26)
#define	AT91C_UDPHS_DMA_INT_3   (0x1 << 27)
#define	AT91C_UDPHS_DMA_INT_4   (0x1 << 28)
#define	AT91C_UDPHS_DMA_INT_5   (0x1 << 29)
#define	AT91C_UDPHS_DMA_INT_6   (0x1 << 30)
#define	AT91C_UDPHS_SPEED   (0x1 << 0)
#define	AT91C_UDPHS_RST_EPT_0   (0x1 << 0)
#define	AT91C_UDPHS_RST_EPT_1   (0x1 << 1)
#define	AT91C_UDPHS_RST_EPT_2   (0x1 << 2)
#define	AT91C_UDPHS_RST_EPT_3   (0x1 << 3)
#define	AT91C_UDPHS_RST_EPT_4   (0x1 << 4)
#define	AT91C_UDPHS_RST_EPT_5   (0x1 << 5)
#define	AT91C_UDPHS_RST_EPT_6   (0x1 << 6)
#define	AT91C_UDPHS_SOFCNTMAX   (0x3 << 0)
#define	AT91C_UDPHS_SOFCTLOAD   (0x1 << 7)
#define	AT91C_UDPHS_CNTAMAX   (0x7FFF << 0)
#define	AT91C_UDPHS_CNTALOAD   (0x1 << 15)
#define	AT91C_UDPHS_CNTBMAX   (0x7FFF << 0)
#define	AT91C_UDPHS_CNTBLOAD   (0x1 << 15)
#define	AT91C_UDPHS_TSTMODE   (0x1F << 1)
#define	AT91C_UDPHS_SPEED_CFG   (0x3 << 0)
#define	AT91C_UDPHS_SPEED_CFG_NM   (0x0)
#define	AT91C_UDPHS_SPEED_CFG_RS   (0x1)
#define	AT91C_UDPHS_SPEED_CFG_HS   (0x2)
#define	AT91C_UDPHS_SPEED_CFG_FS   (0x3)
#define	AT91C_UDPHS_TST_J   (0x1 << 2)
#define	AT91C_UDPHS_TST_K   (0x1 << 3)
#define	AT91C_UDPHS_TST_PKT   (0x1 << 4)
#define	AT91C_UDPHS_OPMODE2   (0x1 << 5)
#define	AT91C_UDPHS_IPPADDRSIZE   (0x0 << 0)
#define	AT91C_UDPHS_IPNAME1   (0x0 << 0)
#define	AT91C_UDPHS_IPNAME2   (0x0 << 0)
#define	AT91C_UDPHS_EPT_NBR_MAX   (0xF << 0)
#define	AT91C_UDPHS_DMA_CHANNEL_NBR   (0x7 << 4)
#define	AT91C_UDPHS_DMA_B_SIZ   (0x1 << 7)
#define	AT91C_UDPHS_DMA_FIFO_WORD_DEPTH   (0xF << 8)
#define	AT91C_UDPHS_FIFO_MAX_SIZE   (0x7 << 12)
#define	AT91C_UDPHS_BW_DPRAM   (0x1 << 15)
#define	AT91C_UDPHS_DATAB16_8   (0x1 << 16)
#define	AT91C_UDPHS_ISO_EPT_1   (0x1 << 17)
#define	AT91C_UDPHS_ISO_EPT_2   (0x1 << 18)
#define	AT91C_UDPHS_ISO_EPT_5   (0x1 << 21)
#define	AT91C_UDPHS_ISO_EPT_6   (0x1 << 22)
#define	AT91C_UDPHS_VERSION_NUM   (0xFFFF << 0)
#define	AT91C_UDPHS_METAL_FIX_NUM   (0x7 << 16)
#define	AT91C_SADDR   (0x0 << 0)
#define	AT91C_DADDR   (0x0 << 0)
#define	AT91C_HDMA_DSCR_IF   (0x3 << 0)
#define	AT91C_HDMA_DSCR_IF_0   (0x0)
#define	AT91C_HDMA_DSCR_IF_1   (0x1)
#define	AT91C_HDMA_DSCR_IF_2   (0x2)
#define	AT91C_HDMA_DSCR_IF_3   (0x3)
#define	AT91C_HDMA_DSCR   (0x3FFFFFFF << 2)
#define	AT91C_HDMA_BTSIZE   (0xFFFF << 0)
#define	AT91C_HDMA_SCSIZE   (0x7 << 16)
#define	AT91C_HDMA_SCSIZE_1   (0x0 << 16)
#define	AT91C_HDMA_SCSIZE_4   (0x1 << 16)
#define	AT91C_HDMA_SCSIZE_8   (0x2 << 16)
#define	AT91C_HDMA_SCSIZE_16   (0x3 << 16)
#define	AT91C_HDMA_SCSIZE_32   (0x4 << 16)
#define	AT91C_HDMA_SCSIZE_64   (0x5 << 16)
#define	AT91C_HDMA_SCSIZE_128   (0x6 << 16)
#define	AT91C_HDMA_SCSIZE_256   (0x7 << 16)
#define	AT91C_HDMA_DCSIZE   (0x7 << 20)
#define	AT91C_HDMA_DCSIZE_1   (0x0 << 20)
#define	AT91C_HDMA_DCSIZE_4   (0x1 << 20)
#define	AT91C_HDMA_DCSIZE_8   (0x2 << 20)
#define	AT91C_HDMA_DCSIZE_16   (0x3 << 20)
#define	AT91C_HDMA_DCSIZE_32   (0x4 << 20)
#define	AT91C_HDMA_DCSIZE_64   (0x5 << 20)
#define	AT91C_HDMA_DCSIZE_128   (0x6 << 20)
#define	AT91C_HDMA_DCSIZE_256   (0x7 << 20)
#define	AT91C_HDMA_SRC_WIDTH   (0x3 << 24)
#define	AT91C_HDMA_SRC_WIDTH_BYTE   (0x0 << 24)
#define	AT91C_HDMA_SRC_WIDTH_HALFWORD   (0x1 << 24)
#define	AT91C_HDMA_SRC_WIDTH_WORD   (0x2 << 24)
#define	AT91C_HDMA_DST_WIDTH   (0x3 << 28)
#define	AT91C_HDMA_DST_WIDTH_BYTE   (0x0 << 28)
#define	AT91C_HDMA_DST_WIDTH_HALFWORD   (0x1 << 28)
#define	AT91C_HDMA_DST_WIDTH_WORD   (0x2 << 28)
#define	AT91C_HDMA_DONE   (0x1 << 31)
#define	AT91C_HDMA_SIF   (0x3 << 0)
#define	AT91C_HDMA_SIF_0   (0x0)
#define	AT91C_HDMA_SIF_1   (0x1)
#define	AT91C_HDMA_SIF_2   (0x2)
#define	AT91C_HDMA_SIF_3   (0x3)
#define	AT91C_HDMA_DIF   (0x3 << 4)
#define	AT91C_HDMA_DIF_0   (0x0 << 4)
#define	AT91C_HDMA_DIF_1   (0x1 << 4)
#define	AT91C_HDMA_DIF_2   (0x2 << 4)
#define	AT91C_HDMA_DIF_3   (0x3 << 4)
#define	AT91C_HDMA_SRC_PIP   (0x1 << 8)
#define	AT91C_HDMA_SRC_PIP_DISABLE   (0x0 << 8)
#define	AT91C_HDMA_SRC_PIP_ENABLE   (0x1 << 8)
#define	AT91C_HDMA_DST_PIP   (0x1 << 12)
#define	AT91C_HDMA_DST_PIP_DISABLE   (0x0 << 12)
#define	AT91C_HDMA_DST_PIP_ENABLE   (0x1 << 12)
#define	AT91C_HDMA_SRC_DSCR   (0x1 << 16)
#define	AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM   (0x0 << 16)
#define	AT91C_HDMA_SRC_DSCR_FETCH_DISABLE   (0x1 << 16)
#define	AT91C_HDMA_DST_DSCR   (0x1 << 20)
#define	AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM   (0x0 << 20)
#define	AT91C_HDMA_DST_DSCR_FETCH_DISABLE   (0x1 << 20)
#define	AT91C_HDMA_FC   (0x7 << 21)
#define	AT91C_HDMA_FC_MEM2MEM   (0x0 << 21)
#define	AT91C_HDMA_FC_MEM2PER   (0x1 << 21)
#define	AT91C_HDMA_FC_PER2MEM   (0x2 << 21)
#define	AT91C_HDMA_FC_PER2PER   (0x3 << 21)
#define	AT91C_HDMA_FC_PER2MEM_PER   (0x4 << 21)
#define	AT91C_HDMA_FC_MEM2PER_PER   (0x5 << 21)
#define	AT91C_HDMA_FC_PER2PER_PER   (0x6 << 21)
#define	AT91C_HDMA_SRC_ADDRESS_MODE   (0x3 << 24)
#define	AT91C_HDMA_SRC_ADDRESS_MODE_INCR   (0x0 << 24)
#define	AT91C_HDMA_SRC_ADDRESS_MODE_DECR   (0x1 << 24)
#define	AT91C_HDMA_SRC_ADDRESS_MODE_FIXED   (0x2 << 24)
#define	AT91C_HDMA_DST_ADDRESS_MODE   (0x3 << 28)
#define	AT91C_HDMA_DST_ADDRESS_MODE_INCR   (0x0 << 28)
#define	AT91C_HDMA_DST_ADDRESS_MODE_DECR   (0x1 << 28)
#define	AT91C_HDMA_DST_ADDRESS_MODE_FIXED   (0x2 << 28)
#define	AT91C_HDMA_AUTO   (0x1 << 31)
#define	AT91C_HDMA_AUTO_DISABLE   (0x0 << 31)
#define	AT91C_HDMA_AUTO_ENABLE   (0x1 << 31)
#define	AT91C_HDMA_SRC_PER   (0xF << 0)
#define	AT91C_HDMA_SRC_PER_0   (0x0)
#define	AT91C_HDMA_SRC_PER_1   (0x1)
#define	AT91C_HDMA_SRC_PER_2   (0x2)
#define	AT91C_HDMA_SRC_PER_3   (0x3)
#define	AT91C_HDMA_SRC_PER_4   (0x4)
#define	AT91C_HDMA_SRC_PER_5   (0x5)
#define	AT91C_HDMA_SRC_PER_6   (0x6)
#define	AT91C_HDMA_SRC_PER_7   (0x7)
#define	AT91C_HDMA_SRC_PER_8   (0x8)
#define	AT91C_HDMA_SRC_PER_9   (0x9)
#define	AT91C_HDMA_SRC_PER_10   (0xA)
#define	AT91C_HDMA_SRC_PER_11   (0xB)
#define	AT91C_HDMA_SRC_PER_12   (0xC)
#define	AT91C_HDMA_SRC_PER_13   (0xD)
#define	AT91C_HDMA_SRC_PER_14   (0xE)
#define	AT91C_HDMA_SRC_PER_15   (0xF)
#define	AT91C_HDMA_DST_PER   (0xF << 4)
#define	AT91C_HDMA_DST_PER_0   (0x0 << 4)
#define	AT91C_HDMA_DST_PER_1   (0x1 << 4)
#define	AT91C_HDMA_DST_PER_2   (0x2 << 4)
#define	AT91C_HDMA_DST_PER_3   (0x3 << 4)
#define	AT91C_HDMA_DST_PER_4   (0x4 << 4)
#define	AT91C_HDMA_DST_PER_5   (0x5 << 4)
#define	AT91C_HDMA_DST_PER_6   (0x6 << 4)
#define	AT91C_HDMA_DST_PER_7   (0x7 << 4)
#define	AT91C_HDMA_DST_PER_8   (0x8 << 4)
#define	AT91C_HDMA_DST_PER_9   (0x9 << 4)
#define	AT91C_HDMA_DST_PER_10   (0xA << 4)
#define	AT91C_HDMA_DST_PER_11   (0xB << 4)
#define	AT91C_HDMA_DST_PER_12   (0xC << 4)
#define	AT91C_HDMA_DST_PER_13   (0xD << 4)
#define	AT91C_HDMA_DST_PER_14   (0xE << 4)
#define	AT91C_HDMA_DST_PER_15   (0xF << 4)
#define	AT91C_HDMA_SRC_REP   (0x1 << 8)
#define	AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR   (0x0 << 8)
#define	AT91C_HDMA_SRC_REP_RELOAD_ADDR   (0x1 << 8)
#define	AT91C_HDMA_SRC_H2SEL   (0x1 << 9)
#define	AT91C_HDMA_SRC_H2SEL_SW   (0x0 << 9)
#define	AT91C_HDMA_SRC_H2SEL_HW   (0x1 << 9)
#define	AT91C_HDMA_DST_REP   (0x1 << 12)
#define	AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR   (0x0 << 12)
#define	AT91C_HDMA_DST_REP_RELOAD_ADDR   (0x1 << 12)
#define	AT91C_HDMA_DST_H2SEL   (0x1 << 13)
#define	AT91C_HDMA_DST_H2SEL_SW   (0x0 << 13)
#define	AT91C_HDMA_DST_H2SEL_HW   (0x1 << 13)
#define	AT91C_HDMA_SOD   (0x1 << 16)
#define	AT91C_HDMA_SOD_DISABLE   (0x0 << 16)
#define	AT91C_HDMA_SOD_ENABLE   (0x1 << 16)
#define	AT91C_HDMA_LOCK_IF   (0x1 << 20)
#define	AT91C_HDMA_LOCK_IF_DISABLE   (0x0 << 20)
#define	AT91C_HDMA_LOCK_IF_ENABLE   (0x1 << 20)
#define	AT91C_HDMA_LOCK_B   (0x1 << 21)
#define	AT91C_HDMA_LOCK_B_DISABLE   (0x0 << 21)
#define	AT91C_HDMA_LOCK_B_ENABLE   (0x1 << 21)
#define	AT91C_HDMA_LOCK_IF_L   (0x1 << 22)
#define	AT91C_HDMA_LOCK_IF_L_CHUNK   (0x0 << 22)
#define	AT91C_HDMA_LOCK_IF_L_BUFFER   (0x1 << 22)
#define	AT91C_HDMA_AHB_PROT   (0x7 << 24)
#define	AT91C_HDMA_FIFOCFG   (0x3 << 28)
#define	AT91C_HDMA_FIFOCFG_LARGESTBURST   (0x0 << 28)
#define	AT91C_HDMA_FIFOCFG_HALFFIFO   (0x1 << 28)
#define	AT91C_HDMA_FIFOCFG_ENOUGHSPACE   (0x2 << 28)
#define	AT91C_SPIP_HOLE   (0xFFFF << 0)
#define	AT91C_SPIP_BOUNDARY   (0x3FF << 16)
#define	AT91C_DPIP_HOLE   (0xFFFF << 0)
#define	AT91C_DPIP_BOUNDARY   (0x3FF << 16)
#define	AT91C_HDMA_IF0_BIGEND   (0x1 << 0)
#define	AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN   (0x0)
#define	AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN   (0x1)
#define	AT91C_HDMA_IF1_BIGEND   (0x1 << 1)
#define	AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 1)
#define	AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN   (0x1 << 1)
#define	AT91C_HDMA_IF2_BIGEND   (0x1 << 2)
#define	AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 2)
#define	AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN   (0x1 << 2)
#define	AT91C_HDMA_IF3_BIGEND   (0x1 << 3)
#define	AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 3)
#define	AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN   (0x1 << 3)
#define	AT91C_HDMA_ARB_CFG   (0x1 << 4)
#define	AT91C_HDMA_ARB_CFG_FIXED   (0x0 << 4)
#define	AT91C_HDMA_ARB_CFG_ROUND_ROBIN   (0x1 << 4)
#define	AT91C_HDMA_ENABLE   (0x1 << 0)
#define	AT91C_HDMA_ENABLE_DISABLE   (0x0)
#define	AT91C_HDMA_ENABLE_ENABLE   (0x1)
#define	AT91C_HDMA_SSREQ0   (0x1 << 0)
#define	AT91C_HDMA_SSREQ0_0   (0x0)
#define	AT91C_HDMA_SSREQ0_1   (0x1)
#define	AT91C_HDMA_DSREQ0   (0x1 << 1)
#define	AT91C_HDMA_DSREQ0_0   (0x0 << 1)
#define	AT91C_HDMA_DSREQ0_1   (0x1 << 1)
#define	AT91C_HDMA_SSREQ1   (0x1 << 2)
#define	AT91C_HDMA_SSREQ1_0   (0x0 << 2)
#define	AT91C_HDMA_SSREQ1_1   (0x1 << 2)
#define	AT91C_HDMA_DSREQ1   (0x1 << 3)
#define	AT91C_HDMA_DSREQ1_0   (0x0 << 3)
#define	AT91C_HDMA_DSREQ1_1   (0x1 << 3)
#define	AT91C_HDMA_SSREQ2   (0x1 << 4)
#define	AT91C_HDMA_SSREQ2_0   (0x0 << 4)
#define	AT91C_HDMA_SSREQ2_1   (0x1 << 4)
#define	AT91C_HDMA_DSREQ2   (0x1 << 5)
#define	AT91C_HDMA_DSREQ2_0   (0x0 << 5)
#define	AT91C_HDMA_DSREQ2_1   (0x1 << 5)
#define	AT91C_HDMA_SSREQ3   (0x1 << 6)
#define	AT91C_HDMA_SSREQ3_0   (0x0 << 6)
#define	AT91C_HDMA_SSREQ3_1   (0x1 << 6)
#define	AT91C_HDMA_DSREQ3   (0x1 << 7)
#define	AT91C_HDMA_DSREQ3_0   (0x0 << 7)
#define	AT91C_HDMA_DSREQ3_1   (0x1 << 7)
#define	AT91C_HDMA_SSREQ4   (0x1 << 8)
#define	AT91C_HDMA_SSREQ4_0   (0x0 << 8)
#define	AT91C_HDMA_SSREQ4_1   (0x1 << 8)
#define	AT91C_HDMA_DSREQ4   (0x1 << 9)
#define	AT91C_HDMA_DSREQ4_0   (0x0 << 9)
#define	AT91C_HDMA_DSREQ4_1   (0x1 << 9)
#define	AT91C_HDMA_SSREQ5   (0x1 << 10)
#define	AT91C_HDMA_SSREQ5_0   (0x0 << 10)
#define	AT91C_HDMA_SSREQ5_1   (0x1 << 10)
#define	AT91C_HDMA_DSREQ6   (0x1 << 11)
#define	AT91C_HDMA_DSREQ6_0   (0x0 << 11)
#define	AT91C_HDMA_DSREQ6_1   (0x1 << 11)
#define	AT91C_HDMA_SSREQ6   (0x1 << 12)
#define	AT91C_HDMA_SSREQ6_0   (0x0 << 12)
#define	AT91C_HDMA_SSREQ6_1   (0x1 << 12)
#define	AT91C_HDMA_SSREQ7   (0x1 << 14)
#define	AT91C_HDMA_SSREQ7_0   (0x0 << 14)
#define	AT91C_HDMA_SSREQ7_1   (0x1 << 14)
#define	AT91C_HDMA_DSREQ7   (0x1 << 15)
#define	AT91C_HDMA_DSREQ7_0   (0x0 << 15)
#define	AT91C_HDMA_DSREQ7_1   (0x1 << 15)
#define	AT91C_HDMA_SCREQ0   (0x1 << 0)
#define	AT91C_HDMA_SCREQ0_0   (0x0)
#define	AT91C_HDMA_SCREQ0_1   (0x1)
#define	AT91C_HDMA_DCREQ0   (0x1 << 1)
#define	AT91C_HDMA_DCREQ0_0   (0x0 << 1)
#define	AT91C_HDMA_DCREQ0_1   (0x1 << 1)
#define	AT91C_HDMA_SCREQ1   (0x1 << 2)
#define	AT91C_HDMA_SCREQ1_0   (0x0 << 2)
#define	AT91C_HDMA_SCREQ1_1   (0x1 << 2)
#define	AT91C_HDMA_DCREQ1   (0x1 << 3)
#define	AT91C_HDMA_DCREQ1_0   (0x0 << 3)
#define	AT91C_HDMA_DCREQ1_1   (0x1 << 3)
#define	AT91C_HDMA_SCREQ2   (0x1 << 4)
#define	AT91C_HDMA_SCREQ2_0   (0x0 << 4)
#define	AT91C_HDMA_SCREQ2_1   (0x1 << 4)
#define	AT91C_HDMA_DCREQ2   (0x1 << 5)
#define	AT91C_HDMA_DCREQ2_0   (0x0 << 5)
#define	AT91C_HDMA_DCREQ2_1   (0x1 << 5)
#define	AT91C_HDMA_SCREQ3   (0x1 << 6)
#define	AT91C_HDMA_SCREQ3_0   (0x0 << 6)
#define	AT91C_HDMA_SCREQ3_1   (0x1 << 6)
#define	AT91C_HDMA_DCREQ3   (0x1 << 7)
#define	AT91C_HDMA_DCREQ3_0   (0x0 << 7)
#define	AT91C_HDMA_DCREQ3_1   (0x1 << 7)
#define	AT91C_HDMA_SCREQ4   (0x1 << 8)
#define	AT91C_HDMA_SCREQ4_0   (0x0 << 8)
#define	AT91C_HDMA_SCREQ4_1   (0x1 << 8)
#define	AT91C_HDMA_DCREQ4   (0x1 << 9)
#define	AT91C_HDMA_DCREQ4_0   (0x0 << 9)
#define	AT91C_HDMA_DCREQ4_1   (0x1 << 9)
#define	AT91C_HDMA_SCREQ5   (0x1 << 10)
#define	AT91C_HDMA_SCREQ5_0   (0x0 << 10)
#define	AT91C_HDMA_SCREQ5_1   (0x1 << 10)
#define	AT91C_HDMA_DCREQ6   (0x1 << 11)
#define	AT91C_HDMA_DCREQ6_0   (0x0 << 11)
#define	AT91C_HDMA_DCREQ6_1   (0x1 << 11)
#define	AT91C_HDMA_SCREQ6   (0x1 << 12)
#define	AT91C_HDMA_SCREQ6_0   (0x0 << 12)
#define	AT91C_HDMA_SCREQ6_1   (0x1 << 12)
#define	AT91C_HDMA_SCREQ7   (0x1 << 14)
#define	AT91C_HDMA_SCREQ7_0   (0x0 << 14)
#define	AT91C_HDMA_SCREQ7_1   (0x1 << 14)
#define	AT91C_HDMA_DCREQ7   (0x1 << 15)
#define	AT91C_HDMA_DCREQ7_0   (0x0 << 15)
#define	AT91C_HDMA_DCREQ7_1   (0x1 << 15)
#define	AT91C_HDMA_SLAST0   (0x1 << 0)
#define	AT91C_HDMA_SLAST0_0   (0x0)
#define	AT91C_HDMA_SLAST0_1   (0x1)
#define	AT91C_HDMA_DLAST0   (0x1 << 1)
#define	AT91C_HDMA_DLAST0_0   (0x0 << 1)
#define	AT91C_HDMA_DLAST0_1   (0x1 << 1)
#define	AT91C_HDMA_SLAST1   (0x1 << 2)
#define	AT91C_HDMA_SLAST1_0   (0x0 << 2)
#define	AT91C_HDMA_SLAST1_1   (0x1 << 2)
#define	AT91C_HDMA_DLAST1   (0x1 << 3)
#define	AT91C_HDMA_DLAST1_0   (0x0 << 3)
#define	AT91C_HDMA_DLAST1_1   (0x1 << 3)
#define	AT91C_HDMA_SLAST2   (0x1 << 4)
#define	AT91C_HDMA_SLAST2_0   (0x0 << 4)
#define	AT91C_HDMA_SLAST2_1   (0x1 << 4)
#define	AT91C_HDMA_DLAST2   (0x1 << 5)
#define	AT91C_HDMA_DLAST2_0   (0x0 << 5)
#define	AT91C_HDMA_DLAST2_1   (0x1 << 5)
#define	AT91C_HDMA_SLAST3   (0x1 << 6)
#define	AT91C_HDMA_SLAST3_0   (0x0 << 6)
#define	AT91C_HDMA_SLAST3_1   (0x1 << 6)
#define	AT91C_HDMA_DLAST3   (0x1 << 7)
#define	AT91C_HDMA_DLAST3_0   (0x0 << 7)
#define	AT91C_HDMA_DLAST3_1   (0x1 << 7)
#define	AT91C_HDMA_SLAST4   (0x1 << 8)
#define	AT91C_HDMA_SLAST4_0   (0x0 << 8)
#define	AT91C_HDMA_SLAST4_1   (0x1 << 8)
#define	AT91C_HDMA_DLAST4   (0x1 << 9)
#define	AT91C_HDMA_DLAST4_0   (0x0 << 9)
#define	AT91C_HDMA_DLAST4_1   (0x1 << 9)
#define	AT91C_HDMA_SLAST5   (0x1 << 10)
#define	AT91C_HDMA_SLAST5_0   (0x0 << 10)
#define	AT91C_HDMA_SLAST5_1   (0x1 << 10)
#define	AT91C_HDMA_DLAST6   (0x1 << 11)
#define	AT91C_HDMA_DLAST6_0   (0x0 << 11)
#define	AT91C_HDMA_DLAST6_1   (0x1 << 11)
#define	AT91C_HDMA_SLAST6   (0x1 << 12)
#define	AT91C_HDMA_SLAST6_0   (0x0 << 12)
#define	AT91C_HDMA_SLAST6_1   (0x1 << 12)
#define	AT91C_HDMA_SLAST7   (0x1 << 14)
#define	AT91C_HDMA_SLAST7_0   (0x0 << 14)
#define	AT91C_HDMA_SLAST7_1   (0x1 << 14)
#define	AT91C_HDMA_DLAST7   (0x1 << 15)
#define	AT91C_HDMA_DLAST7_0   (0x0 << 15)
#define	AT91C_HDMA_DLAST7_1   (0x1 << 15)
#define	AT91C_SYNC_REQ   (0xFFFF << 0)
#define	AT91C_HDMA_BTC0   (0x1 << 0)
#define	AT91C_HDMA_BTC1   (0x1 << 1)
#define	AT91C_HDMA_BTC2   (0x1 << 2)
#define	AT91C_HDMA_BTC3   (0x1 << 3)
#define	AT91C_HDMA_BTC4   (0x1 << 4)
#define	AT91C_HDMA_BTC5   (0x1 << 5)
#define	AT91C_HDMA_BTC6   (0x1 << 6)
#define	AT91C_HDMA_BTC7   (0x1 << 7)
#define	AT91C_HDMA_CBTC0   (0x1 << 8)
#define	AT91C_HDMA_CBTC1   (0x1 << 9)
#define	AT91C_HDMA_CBTC2   (0x1 << 10)
#define	AT91C_HDMA_CBTC3   (0x1 << 11)
#define	AT91C_HDMA_CBTC4   (0x1 << 12)
#define	AT91C_HDMA_CBTC5   (0x1 << 13)
#define	AT91C_HDMA_CBTC6   (0x1 << 14)
#define	AT91C_HDMA_CBTC7   (0x1 << 15)
#define	AT91C_HDMA_ERR0   (0x1 << 16)
#define	AT91C_HDMA_ERR1   (0x1 << 17)
#define	AT91C_HDMA_ERR2   (0x1 << 18)
#define	AT91C_HDMA_ERR3   (0x1 << 19)
#define	AT91C_HDMA_ERR4   (0x1 << 20)
#define	AT91C_HDMA_ERR5   (0x1 << 21)
#define	AT91C_HDMA_ERR6   (0x1 << 22)
#define	AT91C_HDMA_ERR7   (0x1 << 23)
#define	AT91C_HDMA_ENA0   (0x1 << 0)
#define	AT91C_HDMA_ENA0_0   (0x0)
#define	AT91C_HDMA_ENA0_1   (0x1)
#define	AT91C_HDMA_ENA1   (0x1 << 1)
#define	AT91C_HDMA_ENA1_0   (0x0 << 1)
#define	AT91C_HDMA_ENA1_1   (0x1 << 1)
#define	AT91C_HDMA_ENA2   (0x1 << 2)
#define	AT91C_HDMA_ENA2_0   (0x0 << 2)
#define	AT91C_HDMA_ENA2_1   (0x1 << 2)
#define	AT91C_HDMA_ENA3   (0x1 << 3)
#define	AT91C_HDMA_ENA3_0   (0x0 << 3)
#define	AT91C_HDMA_ENA3_1   (0x1 << 3)
#define	AT91C_HDMA_ENA4   (0x1 << 4)
#define	AT91C_HDMA_ENA4_0   (0x0 << 4)
#define	AT91C_HDMA_ENA4_1   (0x1 << 4)
#define	AT91C_HDMA_ENA5   (0x1 << 5)
#define	AT91C_HDMA_ENA5_0   (0x0 << 5)
#define	AT91C_HDMA_ENA5_1   (0x1 << 5)
#define	AT91C_HDMA_ENA6   (0x1 << 6)
#define	AT91C_HDMA_ENA6_0   (0x0 << 6)
#define	AT91C_HDMA_ENA6_1   (0x1 << 6)
#define	AT91C_HDMA_ENA7   (0x1 << 7)
#define	AT91C_HDMA_ENA7_0   (0x0 << 7)
#define	AT91C_HDMA_ENA7_1   (0x1 << 7)
#define	AT91C_HDMA_SUSP0   (0x1 << 8)
#define	AT91C_HDMA_SUSP0_0   (0x0 << 8)
#define	AT91C_HDMA_SUSP0_1   (0x1 << 8)
#define	AT91C_HDMA_SUSP1   (0x1 << 9)
#define	AT91C_HDMA_SUSP1_0   (0x0 << 9)
#define	AT91C_HDMA_SUSP1_1   (0x1 << 9)
#define	AT91C_HDMA_SUSP2   (0x1 << 10)
#define	AT91C_HDMA_SUSP2_0   (0x0 << 10)
#define	AT91C_HDMA_SUSP2_1   (0x1 << 10)
#define	AT91C_HDMA_SUSP3   (0x1 << 11)
#define	AT91C_HDMA_SUSP3_0   (0x0 << 11)
#define	AT91C_HDMA_SUSP3_1   (0x1 << 11)
#define	AT91C_HDMA_SUSP4   (0x1 << 12)
#define	AT91C_HDMA_SUSP4_0   (0x0 << 12)
#define	AT91C_HDMA_SUSP4_1   (0x1 << 12)
#define	AT91C_HDMA_SUSP5   (0x1 << 13)
#define	AT91C_HDMA_SUSP5_0   (0x0 << 13)
#define	AT91C_HDMA_SUSP5_1   (0x1 << 13)
#define	AT91C_HDMA_SUSP6   (0x1 << 14)
#define	AT91C_HDMA_SUSP6_0   (0x0 << 14)
#define	AT91C_HDMA_SUSP6_1   (0x1 << 14)
#define	AT91C_HDMA_SUSP7   (0x1 << 15)
#define	AT91C_HDMA_SUSP7_0   (0x0 << 15)
#define	AT91C_HDMA_SUSP7_1   (0x1 << 15)
#define	AT91C_HDMA_KEEP0   (0x1 << 24)
#define	AT91C_HDMA_KEEP0_0   (0x0 << 24)
#define	AT91C_HDMA_KEEP0_1   (0x1 << 24)
#define	AT91C_HDMA_KEEP1   (0x1 << 25)
#define	AT91C_HDMA_KEEP1_0   (0x0 << 25)
#define	AT91C_HDMA_KEEP1_1   (0x1 << 25)
#define	AT91C_HDMA_KEEP2   (0x1 << 26)
#define	AT91C_HDMA_KEEP2_0   (0x0 << 26)
#define	AT91C_HDMA_KEEP2_1   (0x1 << 26)
#define	AT91C_HDMA_KEEP3   (0x1 << 27)
#define	AT91C_HDMA_KEEP3_0   (0x0 << 27)
#define	AT91C_HDMA_KEEP3_1   (0x1 << 27)
#define	AT91C_HDMA_KEEP4   (0x1 << 28)
#define	AT91C_HDMA_KEEP4_0   (0x0 << 28)
#define	AT91C_HDMA_KEEP4_1   (0x1 << 28)
#define	AT91C_HDMA_KEEP5   (0x1 << 29)
#define	AT91C_HDMA_KEEP5_0   (0x0 << 29)
#define	AT91C_HDMA_KEEP5_1   (0x1 << 29)
#define	AT91C_HDMA_KEEP6   (0x1 << 30)
#define	AT91C_HDMA_KEEP6_0   (0x0 << 30)
#define	AT91C_HDMA_KEEP6_1   (0x1 << 30)
#define	AT91C_HDMA_KEEP7   (0x1 << 31)
#define	AT91C_HDMA_KEEP7_0   (0x0 << 31)
#define	AT91C_HDMA_KEEP7_1   (0x1 << 31)
#define	AT91C_HDMA_DIS0   (0x1 << 0)
#define	AT91C_HDMA_DIS0_0   (0x0)
#define	AT91C_HDMA_DIS0_1   (0x1)
#define	AT91C_HDMA_DIS1   (0x1 << 1)
#define	AT91C_HDMA_DIS1_0   (0x0 << 1)
#define	AT91C_HDMA_DIS1_1   (0x1 << 1)
#define	AT91C_HDMA_DIS2   (0x1 << 2)
#define	AT91C_HDMA_DIS2_0   (0x0 << 2)
#define	AT91C_HDMA_DIS2_1   (0x1 << 2)
#define	AT91C_HDMA_DIS3   (0x1 << 3)
#define	AT91C_HDMA_DIS3_0   (0x0 << 3)
#define	AT91C_HDMA_DIS3_1   (0x1 << 3)
#define	AT91C_HDMA_DIS4   (0x1 << 4)
#define	AT91C_HDMA_DIS4_0   (0x0 << 4)
#define	AT91C_HDMA_DIS4_1   (0x1 << 4)
#define	AT91C_HDMA_DIS5   (0x1 << 5)
#define	AT91C_HDMA_DIS5_0   (0x0 << 5)
#define	AT91C_HDMA_DIS5_1   (0x1 << 5)
#define	AT91C_HDMA_DIS6   (0x1 << 6)
#define	AT91C_HDMA_DIS6_0   (0x0 << 6)
#define	AT91C_HDMA_DIS6_1   (0x1 << 6)
#define	AT91C_HDMA_DIS7   (0x1 << 7)
#define	AT91C_HDMA_DIS7_0   (0x0 << 7)
#define	AT91C_HDMA_DIS7_1   (0x1 << 7)
#define	AT91C_HDMA_RES0   (0x1 << 8)
#define	AT91C_HDMA_RES0_0   (0x0 << 8)
#define	AT91C_HDMA_RES0_1   (0x1 << 8)
#define	AT91C_HDMA_RES1   (0x1 << 9)
#define	AT91C_HDMA_RES1_0   (0x0 << 9)
#define	AT91C_HDMA_RES1_1   (0x1 << 9)
#define	AT91C_HDMA_RES2   (0x1 << 10)
#define	AT91C_HDMA_RES2_0   (0x0 << 10)
#define	AT91C_HDMA_RES2_1   (0x1 << 10)
#define	AT91C_HDMA_RES3   (0x1 << 11)
#define	AT91C_HDMA_RES3_0   (0x0 << 11)
#define	AT91C_HDMA_RES3_1   (0x1 << 11)
#define	AT91C_HDMA_RES4   (0x1 << 12)
#define	AT91C_HDMA_RES4_0   (0x0 << 12)
#define	AT91C_HDMA_RES4_1   (0x1 << 12)
#define	AT91C_HDMA_RES5   (0x1 << 13)
#define	AT91C_HDMA_RES5_0   (0x0 << 13)
#define	AT91C_HDMA_RES5_1   (0x1 << 13)
#define	AT91C_HDMA_RES6   (0x1 << 14)
#define	AT91C_HDMA_RES6_0   (0x0 << 14)
#define	AT91C_HDMA_RES6_1   (0x1 << 14)
#define	AT91C_HDMA_RES7   (0x1 << 15)
#define	AT91C_HDMA_RES7_0   (0x0 << 15)
#define	AT91C_HDMA_RES7_1   (0x1 << 15)
#define	AT91C_HDMA_EMPT0   (0x1 << 16)
#define	AT91C_HDMA_EMPT0_0   (0x0 << 16)
#define	AT91C_HDMA_EMPT0_1   (0x1 << 16)
#define	AT91C_HDMA_EMPT1   (0x1 << 17)
#define	AT91C_HDMA_EMPT1_0   (0x0 << 17)
#define	AT91C_HDMA_EMPT1_1   (0x1 << 17)
#define	AT91C_HDMA_EMPT2   (0x1 << 18)
#define	AT91C_HDMA_EMPT2_0   (0x0 << 18)
#define	AT91C_HDMA_EMPT2_1   (0x1 << 18)
#define	AT91C_HDMA_EMPT3   (0x1 << 19)
#define	AT91C_HDMA_EMPT3_0   (0x0 << 19)
#define	AT91C_HDMA_EMPT3_1   (0x1 << 19)
#define	AT91C_HDMA_EMPT4   (0x1 << 20)
#define	AT91C_HDMA_EMPT4_0   (0x0 << 20)
#define	AT91C_HDMA_EMPT4_1   (0x1 << 20)
#define	AT91C_HDMA_EMPT5   (0x1 << 21)
#define	AT91C_HDMA_EMPT5_0   (0x0 << 21)
#define	AT91C_HDMA_EMPT5_1   (0x1 << 21)
#define	AT91C_HDMA_EMPT6   (0x1 << 22)
#define	AT91C_HDMA_EMPT6_0   (0x0 << 22)
#define	AT91C_HDMA_EMPT6_1   (0x1 << 22)
#define	AT91C_HDMA_EMPT7   (0x1 << 23)
#define	AT91C_HDMA_EMPT7_0   (0x0 << 23)
#define	AT91C_HDMA_EMPT7_1   (0x1 << 23)
#define	AT91C_HDMA_STAL0   (0x1 << 24)
#define	AT91C_HDMA_STAL0_0   (0x0 << 24)
#define	AT91C_HDMA_STAL0_1   (0x1 << 24)
#define	AT91C_HDMA_STAL1   (0x1 << 25)
#define	AT91C_HDMA_STAL1_0   (0x0 << 25)
#define	AT91C_HDMA_STAL1_1   (0x1 << 25)
#define	AT91C_HDMA_STAL2   (0x1 << 26)
#define	AT91C_HDMA_STAL2_0   (0x0 << 26)
#define	AT91C_HDMA_STAL2_1   (0x1 << 26)
#define	AT91C_HDMA_STAL3   (0x1 << 27)
#define	AT91C_HDMA_STAL3_0   (0x0 << 27)
#define	AT91C_HDMA_STAL3_1   (0x1 << 27)
#define	AT91C_HDMA_STAL4   (0x1 << 28)
#define	AT91C_HDMA_STAL4_0   (0x0 << 28)
#define	AT91C_HDMA_STAL4_1   (0x1 << 28)
#define	AT91C_HDMA_STAL5   (0x1 << 29)
#define	AT91C_HDMA_STAL5_0   (0x0 << 29)
#define	AT91C_HDMA_STAL5_1   (0x1 << 29)
#define	AT91C_HDMA_STAL6   (0x1 << 30)
#define	AT91C_HDMA_STAL6_0   (0x0 << 30)
#define	AT91C_HDMA_STAL6_1   (0x1 << 30)
#define	AT91C_HDMA_STAL7   (0x1 << 31)
#define	AT91C_HDMA_STAL7_0   (0x0 << 31)
#define	AT91C_HDMA_STAL7_1   (0x1 << 31)
#define	AT91C_SYS_GPBR   (AT91_CAST(AT91_REG *) 0x400E1290)
#define	AT91C_CS0_MODE   (AT91_CAST(AT91_REG *) 0x400E0080)
#define	AT91C_CS0_PULSE   (AT91_CAST(AT91_REG *) 0x400E0074)
#define	AT91C_CS0_CYCLE   (AT91_CAST(AT91_REG *) 0x400E0078)
#define	AT91C_CS0_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E007C)
#define	AT91C_CS0_SETUP   (AT91_CAST(AT91_REG *) 0x400E0070)
#define	AT91C_CS1_CYCLE   (AT91_CAST(AT91_REG *) 0x400E008C)
#define	AT91C_CS1_PULSE   (AT91_CAST(AT91_REG *) 0x400E0088)
#define	AT91C_CS1_MODE   (AT91_CAST(AT91_REG *) 0x400E0094)
#define	AT91C_CS1_SETUP   (AT91_CAST(AT91_REG *) 0x400E0084)
#define	AT91C_CS1_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E0090)
#define	AT91C_CS2_PULSE   (AT91_CAST(AT91_REG *) 0x400E009C)
#define	AT91C_CS2_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E00A4)
#define	AT91C_CS2_CYCLE   (AT91_CAST(AT91_REG *) 0x400E00A0)
#define	AT91C_CS2_MODE   (AT91_CAST(AT91_REG *) 0x400E00A8)
#define	AT91C_CS2_SETUP   (AT91_CAST(AT91_REG *) 0x400E0098)
#define	AT91C_CS3_MODE   (AT91_CAST(AT91_REG *) 0x400E00BC)
#define	AT91C_CS3_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E00B8)
#define	AT91C_CS3_SETUP   (AT91_CAST(AT91_REG *) 0x400E00AC)
#define	AT91C_CS3_CYCLE   (AT91_CAST(AT91_REG *) 0x400E00B4)
#define	AT91C_CS3_PULSE   (AT91_CAST(AT91_REG *) 0x400E00B0)
#define	AT91C_NFC_MODE   (AT91_CAST(AT91_REG *) 0x400E010C)
#define	AT91C_NFC_CYCLE   (AT91_CAST(AT91_REG *) 0x400E0104)
#define	AT91C_NFC_PULSE   (AT91_CAST(AT91_REG *) 0x400E0100)
#define	AT91C_NFC_SETUP   (AT91_CAST(AT91_REG *) 0x400E00FC)
#define	AT91C_NFC_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E0108)
#define	AT91C_HSMC4_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E01F0)
#define	AT91C_HSMC4_ECCPR6   (AT91_CAST(AT91_REG *) 0x400E0048)
#define	AT91C_HSMC4_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E01EC)
#define	AT91C_HSMC4_ECCPR11   (AT91_CAST(AT91_REG *) 0x400E005C)
#define	AT91C_HSMC4_SR   (AT91_CAST(AT91_REG *) 0x400E0008)
#define	AT91C_HSMC4_IMR   (AT91_CAST(AT91_REG *) 0x400E0014)
#define	AT91C_HSMC4_WPSR   (AT91_CAST(AT91_REG *) 0x400E01E8)
#define	AT91C_HSMC4_BANK   (AT91_CAST(AT91_REG *) 0x400E001C)
#define	AT91C_HSMC4_ECCPR8   (AT91_CAST(AT91_REG *) 0x400E0050)
#define	AT91C_HSMC4_WPCR   (AT91_CAST(AT91_REG *) 0x400E01E4)
#define	AT91C_HSMC4_ECCPR2   (AT91_CAST(AT91_REG *) 0x400E0038)
#define	AT91C_HSMC4_ECCPR1   (AT91_CAST(AT91_REG *) 0x400E0030)
#define	AT91C_HSMC4_ECCSR2   (AT91_CAST(AT91_REG *) 0x400E0034)
#define	AT91C_HSMC4_OCMS   (AT91_CAST(AT91_REG *) 0x400E0110)
#define	AT91C_HSMC4_ECCPR9   (AT91_CAST(AT91_REG *) 0x400E0054)
#define	AT91C_HSMC4_DUMMY   (AT91_CAST(AT91_REG *) 0x400E0200)
#define	AT91C_HSMC4_ECCPR5   (AT91_CAST(AT91_REG *) 0x400E0044)
#define	AT91C_HSMC4_ECCCR   (AT91_CAST(AT91_REG *) 0x400E0020)
#define	AT91C_HSMC4_KEY2   (AT91_CAST(AT91_REG *) 0x400E0118)
#define	AT91C_HSMC4_IER   (AT91_CAST(AT91_REG *) 0x400E000C)
#define	AT91C_HSMC4_ECCSR1   (AT91_CAST(AT91_REG *) 0x400E0028)
#define	AT91C_HSMC4_IDR   (AT91_CAST(AT91_REG *) 0x400E0010)
#define	AT91C_HSMC4_ECCPR0   (AT91_CAST(AT91_REG *) 0x400E002C)
#define	AT91C_HSMC4_FEATURES   (AT91_CAST(AT91_REG *) 0x400E01F8)
#define	AT91C_HSMC4_ECCPR7   (AT91_CAST(AT91_REG *) 0x400E004C)
#define	AT91C_HSMC4_ECCPR12   (AT91_CAST(AT91_REG *) 0x400E0060)
#define	AT91C_HSMC4_ECCPR10   (AT91_CAST(AT91_REG *) 0x400E0058)
#define	AT91C_HSMC4_KEY1   (AT91_CAST(AT91_REG *) 0x400E0114)
#define	AT91C_HSMC4_VER   (AT91_CAST(AT91_REG *) 0x400E01FC)
#define	AT91C_HSMC4_Eccpr15   (AT91_CAST(AT91_REG *) 0x400E006C)
#define	AT91C_HSMC4_ECCPR4   (AT91_CAST(AT91_REG *) 0x400E0040)
#define	AT91C_HSMC4_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E01F4)
#define	AT91C_HSMC4_ECCCMD   (AT91_CAST(AT91_REG *) 0x400E0024)
#define	AT91C_HSMC4_ADDR   (AT91_CAST(AT91_REG *) 0x400E0018)
#define	AT91C_HSMC4_ECCPR3   (AT91_CAST(AT91_REG *) 0x400E003C)
#define	AT91C_HSMC4_CFG   (AT91_CAST(AT91_REG *) 0x400E0000)
#define	AT91C_HSMC4_CTRL   (AT91_CAST(AT91_REG *) 0x400E0004)
#define	AT91C_HSMC4_ECCPR13   (AT91_CAST(AT91_REG *) 0x400E0064)
#define	AT91C_HSMC4_ECCPR14   (AT91_CAST(AT91_REG *) 0x400E0068)
#define	AT91C_MATRIX_SFR2   (AT91_CAST(AT91_REG *) 0x400E0318)
#define	AT91C_MATRIX_SFR3   (AT91_CAST(AT91_REG *) 0x400E031C)
#define	AT91C_MATRIX_SCFG8   (AT91_CAST(AT91_REG *) 0x400E0260)
#define	AT91C_MATRIX_MCFG2   (AT91_CAST(AT91_REG *) 0x400E0208)
#define	AT91C_MATRIX_MCFG7   (AT91_CAST(AT91_REG *) 0x400E021C)
#define	AT91C_MATRIX_SCFG3   (AT91_CAST(AT91_REG *) 0x400E024C)
#define	AT91C_MATRIX_SCFG0   (AT91_CAST(AT91_REG *) 0x400E0240)
#define	AT91C_MATRIX_SFR12   (AT91_CAST(AT91_REG *) 0x400E0340)
#define	AT91C_MATRIX_SCFG1   (AT91_CAST(AT91_REG *) 0x400E0244)
#define	AT91C_MATRIX_SFR8   (AT91_CAST(AT91_REG *) 0x400E0330)
#define	AT91C_MATRIX_VER   (AT91_CAST(AT91_REG *) 0x400E03FC)
#define	AT91C_MATRIX_SFR13   (AT91_CAST(AT91_REG *) 0x400E0344)
#define	AT91C_MATRIX_SFR5   (AT91_CAST(AT91_REG *) 0x400E0324)
#define	AT91C_MATRIX_MCFG0   (AT91_CAST(AT91_REG *) 0x400E0200)
#define	AT91C_MATRIX_SCFG6   (AT91_CAST(AT91_REG *) 0x400E0258)
#define	AT91C_MATRIX_SFR14   (AT91_CAST(AT91_REG *) 0x400E0348)
#define	AT91C_MATRIX_SFR1   (AT91_CAST(AT91_REG *) 0x400E0314)
#define	AT91C_MATRIX_SFR15   (AT91_CAST(AT91_REG *) 0x400E034C)
#define	AT91C_MATRIX_SFR6   (AT91_CAST(AT91_REG *) 0x400E0328)
#define	AT91C_MATRIX_SFR11   (AT91_CAST(AT91_REG *) 0x400E033C)
#define	AT91C_MATRIX_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E03F4)
#define	AT91C_MATRIX_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E03EC)
#define	AT91C_MATRIX_MCFG5   (AT91_CAST(AT91_REG *) 0x400E0214)
#define	AT91C_MATRIX_SFR9   (AT91_CAST(AT91_REG *) 0x400E0334)
#define	AT91C_MATRIX_MCFG3   (AT91_CAST(AT91_REG *) 0x400E020C)
#define	AT91C_MATRIX_SCFG4   (AT91_CAST(AT91_REG *) 0x400E0250)
#define	AT91C_MATRIX_MCFG1   (AT91_CAST(AT91_REG *) 0x400E0204)
#define	AT91C_MATRIX_SCFG7   (AT91_CAST(AT91_REG *) 0x400E025C)
#define	AT91C_MATRIX_SFR10   (AT91_CAST(AT91_REG *) 0x400E0338)
#define	AT91C_MATRIX_SCFG2   (AT91_CAST(AT91_REG *) 0x400E0248)
#define	AT91C_MATRIX_SFR7   (AT91_CAST(AT91_REG *) 0x400E032C)
#define	AT91C_MATRIX_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E03F0)
#define	AT91C_MATRIX_MCFG4   (AT91_CAST(AT91_REG *) 0x400E0210)
#define	AT91C_MATRIX_SFR0   (AT91_CAST(AT91_REG *) 0x400E0310)
#define	AT91C_MATRIX_FEATURES   (AT91_CAST(AT91_REG *) 0x400E03F8)
#define	AT91C_MATRIX_SCFG5   (AT91_CAST(AT91_REG *) 0x400E0254)
#define	AT91C_MATRIX_MCFG6   (AT91_CAST(AT91_REG *) 0x400E0218)
#define	AT91C_MATRIX_SCFG9   (AT91_CAST(AT91_REG *) 0x400E0264)
#define	AT91C_MATRIX_SFR4   (AT91_CAST(AT91_REG *) 0x400E0320)
#define	AT91C_NVIC_MMAR   (AT91_CAST(AT91_REG *) 0xE000ED34)
#define	AT91C_NVIC_STIR   (AT91_CAST(AT91_REG *) 0xE000EF00)
#define	AT91C_NVIC_MMFR2   (AT91_CAST(AT91_REG *) 0xE000ED58)
#define	AT91C_NVIC_CPUID   (AT91_CAST(AT91_REG *) 0xE000ED00)
#define	AT91C_NVIC_DFSR   (AT91_CAST(AT91_REG *) 0xE000ED30)
#define	AT91C_NVIC_HAND4PR   (AT91_CAST(AT91_REG *) 0xE000ED18)
#define	AT91C_NVIC_HFSR   (AT91_CAST(AT91_REG *) 0xE000ED2C)
#define	AT91C_NVIC_PID6   (AT91_CAST(AT91_REG *) 0xE000EFD8)
#define	AT91C_NVIC_PFR0   (AT91_CAST(AT91_REG *) 0xE000ED40)
#define	AT91C_NVIC_VTOFFR   (AT91_CAST(AT91_REG *) 0xE000ED08)
#define	AT91C_NVIC_ISPR   (AT91_CAST(AT91_REG *) 0xE000E200)
#define	AT91C_NVIC_PID0   (AT91_CAST(AT91_REG *) 0xE000EFE0)
#define	AT91C_NVIC_PID7   (AT91_CAST(AT91_REG *) 0xE000EFDC)
#define	AT91C_NVIC_STICKRVR   (AT91_CAST(AT91_REG *) 0xE000E014)
#define	AT91C_NVIC_PID2   (AT91_CAST(AT91_REG *) 0xE000EFE8)
#define	AT91C_NVIC_ISAR0   (AT91_CAST(AT91_REG *) 0xE000ED60)
#define	AT91C_NVIC_SCR   (AT91_CAST(AT91_REG *) 0xE000ED10)
#define	AT91C_NVIC_PID4   (AT91_CAST(AT91_REG *) 0xE000EFD0)
#define	AT91C_NVIC_ISAR2   (AT91_CAST(AT91_REG *) 0xE000ED68)
#define	AT91C_NVIC_ISER   (AT91_CAST(AT91_REG *) 0xE000E100)
#define	AT91C_NVIC_IPR   (AT91_CAST(AT91_REG *) 0xE000E400)
#define	AT91C_NVIC_AIRCR   (AT91_CAST(AT91_REG *) 0xE000ED0C)
#define	AT91C_NVIC_CID2   (AT91_CAST(AT91_REG *) 0xE000EFF8)
#define	AT91C_NVIC_ICPR   (AT91_CAST(AT91_REG *) 0xE000E280)
#define	AT91C_NVIC_CID3   (AT91_CAST(AT91_REG *) 0xE000EFFC)
#define	AT91C_NVIC_CFSR   (AT91_CAST(AT91_REG *) 0xE000ED28)
#define	AT91C_NVIC_AFR0   (AT91_CAST(AT91_REG *) 0xE000ED4C)
#define	AT91C_NVIC_ICSR   (AT91_CAST(AT91_REG *) 0xE000ED04)
#define	AT91C_NVIC_CCR   (AT91_CAST(AT91_REG *) 0xE000ED14)
#define	AT91C_NVIC_CID0   (AT91_CAST(AT91_REG *) 0xE000EFF0)
#define	AT91C_NVIC_ISAR1   (AT91_CAST(AT91_REG *) 0xE000ED64)
#define	AT91C_NVIC_STICKCVR   (AT91_CAST(AT91_REG *) 0xE000E018)
#define	AT91C_NVIC_STICKCSR   (AT91_CAST(AT91_REG *) 0xE000E010)
#define	AT91C_NVIC_CID1   (AT91_CAST(AT91_REG *) 0xE000EFF4)
#define	AT91C_NVIC_DFR0   (AT91_CAST(AT91_REG *) 0xE000ED48)
#define	AT91C_NVIC_MMFR3   (AT91_CAST(AT91_REG *) 0xE000ED5C)
#define	AT91C_NVIC_MMFR0   (AT91_CAST(AT91_REG *) 0xE000ED50)
#define	AT91C_NVIC_STICKCALVR   (AT91_CAST(AT91_REG *) 0xE000E01C)
#define	AT91C_NVIC_PID1   (AT91_CAST(AT91_REG *) 0xE000EFE4)
#define	AT91C_NVIC_HAND12PR   (AT91_CAST(AT91_REG *) 0xE000ED20)
#define	AT91C_NVIC_MMFR1   (AT91_CAST(AT91_REG *) 0xE000ED54)
#define	AT91C_NVIC_AFSR   (AT91_CAST(AT91_REG *) 0xE000ED3C)
#define	AT91C_NVIC_HANDCSR   (AT91_CAST(AT91_REG *) 0xE000ED24)
#define	AT91C_NVIC_ISAR4   (AT91_CAST(AT91_REG *) 0xE000ED70)
#define	AT91C_NVIC_ABR   (AT91_CAST(AT91_REG *) 0xE000E300)
#define	AT91C_NVIC_PFR1   (AT91_CAST(AT91_REG *) 0xE000ED44)
#define	AT91C_NVIC_PID5   (AT91_CAST(AT91_REG *) 0xE000EFD4)
#define	AT91C_NVIC_ICTR   (AT91_CAST(AT91_REG *) 0xE000E004)
#define	AT91C_NVIC_ICER   (AT91_CAST(AT91_REG *) 0xE000E180)
#define	AT91C_NVIC_PID3   (AT91_CAST(AT91_REG *) 0xE000EFEC)
#define	AT91C_NVIC_ISAR3   (AT91_CAST(AT91_REG *) 0xE000ED6C)
#define	AT91C_NVIC_HAND8PR   (AT91_CAST(AT91_REG *) 0xE000ED1C)
#define	AT91C_NVIC_BFAR   (AT91_CAST(AT91_REG *) 0xE000ED38)
#define	AT91C_MPU_REG_BASE_ADDR3   (AT91_CAST(AT91_REG *) 0xE000EDB4)
#define	AT91C_MPU_REG_NB   (AT91_CAST(AT91_REG *) 0xE000ED98)
#define	AT91C_MPU_ATTR_SIZE1   (AT91_CAST(AT91_REG *) 0xE000EDA8)
#define	AT91C_MPU_REG_BASE_ADDR1   (AT91_CAST(AT91_REG *) 0xE000EDA4)
#define	AT91C_MPU_ATTR_SIZE3   (AT91_CAST(AT91_REG *) 0xE000EDB8)
#define	AT91C_MPU_CTRL   (AT91_CAST(AT91_REG *) 0xE000ED94)
#define	AT91C_MPU_ATTR_SIZE2   (AT91_CAST(AT91_REG *) 0xE000EDB0)
#define	AT91C_MPU_REG_BASE_ADDR   (AT91_CAST(AT91_REG *) 0xE000ED9C)
#define	AT91C_MPU_REG_BASE_ADDR2   (AT91_CAST(AT91_REG *) 0xE000EDAC)
#define	AT91C_MPU_ATTR_SIZE   (AT91_CAST(AT91_REG *) 0xE000EDA0)
#define	AT91C_MPU_TYPE   (AT91_CAST(AT91_REG *) 0xE000ED90)
#define	AT91C_CM3_SHCSR   (AT91_CAST(AT91_REG *) 0xE000ED24)
#define	AT91C_CM3_CCR   (AT91_CAST(AT91_REG *) 0xE000ED14)
#define	AT91C_CM3_ICSR   (AT91_CAST(AT91_REG *) 0xE000ED04)
#define	AT91C_CM3_CPUID   (AT91_CAST(AT91_REG *) 0xE000ED00)
#define	AT91C_CM3_SCR   (AT91_CAST(AT91_REG *) 0xE000ED10)
#define	AT91C_CM3_AIRCR   (AT91_CAST(AT91_REG *) 0xE000ED0C)
#define	AT91C_CM3_SHPR   (AT91_CAST(AT91_REG *) 0xE000ED18)
#define	AT91C_CM3_VTOR   (AT91_CAST(AT91_REG *) 0xE000ED08)
#define	AT91C_DBGU_TPR   (AT91_CAST(AT91_REG *) 0x400E0708)
#define	AT91C_DBGU_PTCR   (AT91_CAST(AT91_REG *) 0x400E0720)
#define	AT91C_DBGU_TNCR   (AT91_CAST(AT91_REG *) 0x400E071C)
#define	AT91C_DBGU_PTSR   (AT91_CAST(AT91_REG *) 0x400E0724)
#define	AT91C_DBGU_RNCR   (AT91_CAST(AT91_REG *) 0x400E0714)
#define	AT91C_DBGU_RPR   (AT91_CAST(AT91_REG *) 0x400E0700)
#define	AT91C_DBGU_TCR   (AT91_CAST(AT91_REG *) 0x400E070C)
#define	AT91C_DBGU_RNPR   (AT91_CAST(AT91_REG *) 0x400E0710)
#define	AT91C_DBGU_TNPR   (AT91_CAST(AT91_REG *) 0x400E0718)
#define	AT91C_DBGU_RCR   (AT91_CAST(AT91_REG *) 0x400E0704)
#define	AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 0x400E0600)
#define	AT91C_DBGU_IDR   (AT91_CAST(AT91_REG *) 0x400E060C)
#define	AT91C_DBGU_CIDR   (AT91_CAST(AT91_REG *) 0x400E0740)
#define	AT91C_DBGU_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E06F4)
#define	AT91C_DBGU_FEATURES   (AT91_CAST(AT91_REG *) 0x400E06F8)
#define	AT91C_DBGU_FNTR   (AT91_CAST(AT91_REG *) 0x400E0648)
#define	AT91C_DBGU_RHR   (AT91_CAST(AT91_REG *) 0x400E0618)
#define	AT91C_DBGU_THR   (AT91_CAST(AT91_REG *) 0x400E061C)
#define	AT91C_DBGU_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E06EC)
#define	AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 0x400E0604)
#define	AT91C_DBGU_IER   (AT91_CAST(AT91_REG *) 0x400E0608)
#define	AT91C_DBGU_BRGR   (AT91_CAST(AT91_REG *) 0x400E0620)
#define	AT91C_DBGU_CSR   (AT91_CAST(AT91_REG *) 0x400E0614)
#define	AT91C_DBGU_VER   (AT91_CAST(AT91_REG *) 0x400E06FC)
#define	AT91C_DBGU_IMR   (AT91_CAST(AT91_REG *) 0x400E0610)
#define	AT91C_DBGU_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E06F0)
#define	AT91C_DBGU_EXID   (AT91_CAST(AT91_REG *) 0x400E0744)
#define	AT91C_PIOA_PDR   (AT91_CAST(AT91_REG *) 0x400E0C04)
#define	AT91C_PIOA_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E0CD8)
#define	AT91C_PIOA_KIMR   (AT91_CAST(AT91_REG *) 0x400E0D38)
#define	AT91C_PIOA_LSR   (AT91_CAST(AT91_REG *) 0x400E0CC4)
#define	AT91C_PIOA_IFSR   (AT91_CAST(AT91_REG *) 0x400E0C28)
#define	AT91C_PIOA_KKRR   (AT91_CAST(AT91_REG *) 0x400E0D44)
#define	AT91C_PIOA_ODR   (AT91_CAST(AT91_REG *) 0x400E0C14)
#define	AT91C_PIOA_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E0C80)
#define	AT91C_PIOA_PER   (AT91_CAST(AT91_REG *) 0x400E0C00)
#define	AT91C_PIOA_VER   (AT91_CAST(AT91_REG *) 0x400E0CFC)
#define	AT91C_PIOA_OWSR   (AT91_CAST(AT91_REG *) 0x400E0CA8)
#define	AT91C_PIOA_KSR   (AT91_CAST(AT91_REG *) 0x400E0D3C)
#define	AT91C_PIOA_IMR   (AT91_CAST(AT91_REG *) 0x400E0C48)
#define	AT91C_PIOA_OWDR   (AT91_CAST(AT91_REG *) 0x400E0CA4)
#define	AT91C_PIOA_MDSR   (AT91_CAST(AT91_REG *) 0x400E0C58)
#define	AT91C_PIOA_IFDR   (AT91_CAST(AT91_REG *) 0x400E0C24)
#define	AT91C_PIOA_AIMDR   (AT91_CAST(AT91_REG *) 0x400E0CB4)
#define	AT91C_PIOA_CODR   (AT91_CAST(AT91_REG *) 0x400E0C34)
#define	AT91C_PIOA_SCDR   (AT91_CAST(AT91_REG *) 0x400E0C8C)
#define	AT91C_PIOA_KIER   (AT91_CAST(AT91_REG *) 0x400E0D30)
#define	AT91C_PIOA_REHLSR   (AT91_CAST(AT91_REG *) 0x400E0CD4)
#define	AT91C_PIOA_ISR   (AT91_CAST(AT91_REG *) 0x400E0C4C)
#define	PIOA_ISR   (AT91_CAST(AT91_REG *) 0x400E0C4C)
#define	AT91C_PIOA_ESR   (AT91_CAST(AT91_REG *) 0x400E0CC0)
#define	AT91C_PIOA_PPUDR   (AT91_CAST(AT91_REG *) 0x400E0C60)
#define	AT91C_PIOA_MDDR   (AT91_CAST(AT91_REG *) 0x400E0C54)
#define	AT91C_PIOA_PSR   (AT91_CAST(AT91_REG *) 0x400E0C08)
#define	AT91C_PIOA_PDSR   (AT91_CAST(AT91_REG *) 0x400E0C3C)
#define	AT91C_PIOA_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E0C88)
#define	AT91C_PIOA_FELLSR   (AT91_CAST(AT91_REG *) 0x400E0CD0)
#define	AT91C_PIOA_PPUSR   (AT91_CAST(AT91_REG *) 0x400E0C68)
#define	AT91C_PIOA_OER   (AT91_CAST(AT91_REG *) 0x400E0C10)
#define	AT91C_PIOA_OSR   (AT91_CAST(AT91_REG *) 0x400E0C18)
#define	AT91C_PIOA_KKPR   (AT91_CAST(AT91_REG *) 0x400E0D40)
#define	AT91C_PIOA_AIMMR   (AT91_CAST(AT91_REG *) 0x400E0CB8)
#define	AT91C_PIOA_KRCR   (AT91_CAST(AT91_REG *) 0x400E0D24)
#define	AT91C_PIOA_IER   (AT91_CAST(AT91_REG *) 0x400E0C40)
#define	AT91C_PIOA_KER   (AT91_CAST(AT91_REG *) 0x400E0D20)
#define	AT91C_PIOA_PPUER   (AT91_CAST(AT91_REG *) 0x400E0C64)
#define	AT91C_PIOA_KIDR   (AT91_CAST(AT91_REG *) 0x400E0D34)
#define	AT91C_PIOA_ABSR   (AT91_CAST(AT91_REG *) 0x400E0C70)
#define	AT91C_PIOA_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E0CE0)
#define	AT91C_PIOA_DIFSR   (AT91_CAST(AT91_REG *) 0x400E0C84)
#define	AT91C_PIOA_MDER   (AT91_CAST(AT91_REG *) 0x400E0C50)
#define	AT91C_PIOA_AIMER   (AT91_CAST(AT91_REG *) 0x400E0CB0)
#define	AT91C_PIOA_ELSR   (AT91_CAST(AT91_REG *) 0x400E0CC8)
#define	AT91C_PIOA_IFER   (AT91_CAST(AT91_REG *) 0x400E0C20)
#define	AT91C_PIOA_KDR   (AT91_CAST(AT91_REG *) 0x400E0D28)
#define	AT91C_PIOA_IDR   (AT91_CAST(AT91_REG *) 0x400E0C44)
#define	AT91C_PIOA_OWER   (AT91_CAST(AT91_REG *) 0x400E0CA0)
#define	AT91C_PIOA_ODSR   (AT91_CAST(AT91_REG *) 0x400E0C38)
#define	AT91C_PIOA_SODR   (AT91_CAST(AT91_REG *) 0x400E0C30)
#define	AT91C_PIOB_KIDR   (AT91_CAST(AT91_REG *) 0x400E0F34)
#define	AT91C_PIOB_OWSR   (AT91_CAST(AT91_REG *) 0x400E0EA8)
#define	AT91C_PIOB_PSR   (AT91_CAST(AT91_REG *) 0x400E0E08)
#define	AT91C_PIOB_MDER   (AT91_CAST(AT91_REG *) 0x400E0E50)
#define	AT91C_PIOB_ODR   (AT91_CAST(AT91_REG *) 0x400E0E14)
#define	AT91C_PIOB_IDR   (AT91_CAST(AT91_REG *) 0x400E0E44)
#define	AT91C_PIOB_AIMER   (AT91_CAST(AT91_REG *) 0x400E0EB0)
#define	AT91C_PIOB_DIFSR   (AT91_CAST(AT91_REG *) 0x400E0E84)
#define	AT91C_PIOB_PDR   (AT91_CAST(AT91_REG *) 0x400E0E04)
#define	AT91C_PIOB_REHLSR   (AT91_CAST(AT91_REG *) 0x400E0ED4)
#define	AT91C_PIOB_PDSR   (AT91_CAST(AT91_REG *) 0x400E0E3C)
#define	AT91C_PIOB_PPUDR   (AT91_CAST(AT91_REG *) 0x400E0E60)
#define	AT91C_PIOB_LSR   (AT91_CAST(AT91_REG *) 0x400E0EC4)
#define	AT91C_PIOB_OWDR   (AT91_CAST(AT91_REG *) 0x400E0EA4)
#define	AT91C_PIOB_FELLSR   (AT91_CAST(AT91_REG *) 0x400E0ED0)
#define	AT91C_PIOB_IFER   (AT91_CAST(AT91_REG *) 0x400E0E20)
#define	AT91C_PIOB_ABSR   (AT91_CAST(AT91_REG *) 0x400E0E70)
#define	AT91C_PIOB_KIMR   (AT91_CAST(AT91_REG *) 0x400E0F38)
#define	AT91C_PIOB_KKPR   (AT91_CAST(AT91_REG *) 0x400E0F40)
#define	AT91C_PIOB_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E0ED8)
#define	AT91C_PIOB_AIMDR   (AT91_CAST(AT91_REG *) 0x400E0EB4)
#define	AT91C_PIOB_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E0E80)
#define	AT91C_PIOB_VER   (AT91_CAST(AT91_REG *) 0x400E0EFC)
#define	AT91C_PIOB_PER   (AT91_CAST(AT91_REG *) 0x400E0E00)
#define	AT91C_PIOB_ELSR   (AT91_CAST(AT91_REG *) 0x400E0EC8)
#define	AT91C_PIOB_IMR   (AT91_CAST(AT91_REG *) 0x400E0E48)
#define	AT91C_PIOB_PPUSR   (AT91_CAST(AT91_REG *) 0x400E0E68)
#define	AT91C_PIOB_SCDR   (AT91_CAST(AT91_REG *) 0x400E0E8C)
#define	AT91C_PIOB_KSR   (AT91_CAST(AT91_REG *) 0x400E0F3C)
#define	AT91C_PIOB_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E0E88)
#define	AT91C_PIOB_ESR   (AT91_CAST(AT91_REG *) 0x400E0EC0)
#define	AT91C_PIOB_ODSR   (AT91_CAST(AT91_REG *) 0x400E0E38)
#define	AT91C_PIOB_IFDR   (AT91_CAST(AT91_REG *) 0x400E0E24)
#define	AT91C_PIOB_SODR   (AT91_CAST(AT91_REG *) 0x400E0E30)
#define	AT91C_PIOB_IER   (AT91_CAST(AT91_REG *) 0x400E0E40)
#define	AT91C_PIOB_MDSR   (AT91_CAST(AT91_REG *) 0x400E0E58)
#define	AT91C_PIOB_ISR   (AT91_CAST(AT91_REG *) 0x400E0E4C)
#define	PIOB_ISR   (AT91_CAST(AT91_REG *) 0x400E0E4C)
#define	AT91C_PIOB_IFSR   (AT91_CAST(AT91_REG *) 0x400E0E28)
#define	AT91C_PIOB_KER   (AT91_CAST(AT91_REG *) 0x400E0F20)
#define	AT91C_PIOB_KKRR   (AT91_CAST(AT91_REG *) 0x400E0F44)
#define	AT91C_PIOB_PPUER   (AT91_CAST(AT91_REG *) 0x400E0E64)
#define	AT91C_PIOB_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E0EE0)
#define	AT91C_PIOB_OWER   (AT91_CAST(AT91_REG *) 0x400E0EA0)
#define	AT91C_PIOB_KIER   (AT91_CAST(AT91_REG *) 0x400E0F30)
#define	AT91C_PIOB_MDDR   (AT91_CAST(AT91_REG *) 0x400E0E54)
#define	AT91C_PIOB_KRCR   (AT91_CAST(AT91_REG *) 0x400E0F24)
#define	AT91C_PIOB_CODR   (AT91_CAST(AT91_REG *) 0x400E0E34)
#define	AT91C_PIOB_KDR   (AT91_CAST(AT91_REG *) 0x400E0F28)
#define	AT91C_PIOB_AIMMR   (AT91_CAST(AT91_REG *) 0x400E0EB8)
#define	AT91C_PIOB_OER   (AT91_CAST(AT91_REG *) 0x400E0E10)
#define	AT91C_PIOB_OSR   (AT91_CAST(AT91_REG *) 0x400E0E18)
#define	AT91C_PIOC_FELLSR   (AT91_CAST(AT91_REG *) 0x400E10D0)
#define	AT91C_PIOC_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E10D8)
#define	AT91C_PIOC_MDDR   (AT91_CAST(AT91_REG *) 0x400E1054)
#define	AT91C_PIOC_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E1088)
#define	AT91C_PIOC_ABSR   (AT91_CAST(AT91_REG *) 0x400E1070)
#define	AT91C_PIOC_KIMR   (AT91_CAST(AT91_REG *) 0x400E1138)
#define	AT91C_PIOC_KRCR   (AT91_CAST(AT91_REG *) 0x400E1124)
#define	AT91C_PIOC_ODSR   (AT91_CAST(AT91_REG *) 0x400E1038)
#define	AT91C_PIOC_OSR   (AT91_CAST(AT91_REG *) 0x400E1018)
#define	AT91C_PIOC_IFER   (AT91_CAST(AT91_REG *) 0x400E1020)
#define	AT91C_PIOC_KKPR   (AT91_CAST(AT91_REG *) 0x400E1140)
#define	AT91C_PIOC_MDSR   (AT91_CAST(AT91_REG *) 0x400E1058)
#define	AT91C_PIOC_IFDR   (AT91_CAST(AT91_REG *) 0x400E1024)
#define	AT91C_PIOC_MDER   (AT91_CAST(AT91_REG *) 0x400E1050)
#define	AT91C_PIOC_SCDR   (AT91_CAST(AT91_REG *) 0x400E108C)
#define	AT91C_PIOC_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E1080)
#define	AT91C_PIOC_IER   (AT91_CAST(AT91_REG *) 0x400E1040)
#define	AT91C_PIOC_KDR   (AT91_CAST(AT91_REG *) 0x400E1128)
#define	AT91C_PIOC_OWDR   (AT91_CAST(AT91_REG *) 0x400E10A4)
#define	AT91C_PIOC_IFSR   (AT91_CAST(AT91_REG *) 0x400E1028)
#define	AT91C_PIOC_ISR   (AT91_CAST(AT91_REG *) 0x400E104C)
#define	PIOC_ISR   (AT91_CAST(AT91_REG *) 0x400E104C)
#define	AT91C_PIOC_PPUDR   (AT91_CAST(AT91_REG *) 0x400E1060)
#define	AT91C_PIOC_PDSR   (AT91_CAST(AT91_REG *) 0x400E103C)
#define	AT91C_PIOC_KKRR   (AT91_CAST(AT91_REG *) 0x400E1144)
#define	AT91C_PIOC_AIMDR   (AT91_CAST(AT91_REG *) 0x400E10B4)
#define	AT91C_PIOC_LSR   (AT91_CAST(AT91_REG *) 0x400E10C4)
#define	AT91C_PIOC_PPUER   (AT91_CAST(AT91_REG *) 0x400E1064)
#define	AT91C_PIOC_AIMER   (AT91_CAST(AT91_REG *) 0x400E10B0)
#define	AT91C_PIOC_OER   (AT91_CAST(AT91_REG *) 0x400E1010)
#define	AT91C_PIOC_CODR   (AT91_CAST(AT91_REG *) 0x400E1034)
#define	AT91C_PIOC_AIMMR   (AT91_CAST(AT91_REG *) 0x400E10B8)
#define	AT91C_PIOC_OWER   (AT91_CAST(AT91_REG *) 0x400E10A0)
#define	AT91C_PIOC_VER   (AT91_CAST(AT91_REG *) 0x400E10FC)
#define	AT91C_PIOC_IMR   (AT91_CAST(AT91_REG *) 0x400E1048)
#define	AT91C_PIOC_PPUSR   (AT91_CAST(AT91_REG *) 0x400E1068)
#define	AT91C_PIOC_IDR   (AT91_CAST(AT91_REG *) 0x400E1044)
#define	AT91C_PIOC_DIFSR   (AT91_CAST(AT91_REG *) 0x400E1084)
#define	AT91C_PIOC_KIDR   (AT91_CAST(AT91_REG *) 0x400E1134)
#define	AT91C_PIOC_KSR   (AT91_CAST(AT91_REG *) 0x400E113C)
#define	AT91C_PIOC_REHLSR   (AT91_CAST(AT91_REG *) 0x400E10D4)
#define	AT91C_PIOC_ESR   (AT91_CAST(AT91_REG *) 0x400E10C0)
#define	AT91C_PIOC_KIER   (AT91_CAST(AT91_REG *) 0x400E1130)
#define	AT91C_PIOC_ELSR   (AT91_CAST(AT91_REG *) 0x400E10C8)
#define	AT91C_PIOC_SODR   (AT91_CAST(AT91_REG *) 0x400E1030)
#define	AT91C_PIOC_PSR   (AT91_CAST(AT91_REG *) 0x400E1008)
#define	AT91C_PIOC_KER   (AT91_CAST(AT91_REG *) 0x400E1120)
#define	AT91C_PIOC_ODR   (AT91_CAST(AT91_REG *) 0x400E1014)
#define	AT91C_PIOC_OWSR   (AT91_CAST(AT91_REG *) 0x400E10A8)
#define	AT91C_PIOC_PDR   (AT91_CAST(AT91_REG *) 0x400E1004)
#define	AT91C_PIOC_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E10E0)
#define	AT91C_PIOC_PER   (AT91_CAST(AT91_REG *) 0x400E1000)
#define	AT91C_PMC_PLLAR   (AT91_CAST(AT91_REG *) 0x400E0428)
#define	AT91C_PMC_UCKR   (AT91_CAST(AT91_REG *) 0x400E041C)
#define	AT91C_PMC_FSMR   (AT91_CAST(AT91_REG *) 0x400E0470)
#define	AT91C_PMC_MCKR   (AT91_CAST(AT91_REG *) 0x400E0430)
#define	AT91C_PMC_SCER   (AT91_CAST(AT91_REG *) 0x400E0400)
#define	AT91C_PMC_PCSR   (AT91_CAST(AT91_REG *) 0x400E0418)
#define	AT91C_PMC_MCFR   (AT91_CAST(AT91_REG *) 0x400E0424)
#define	AT91C_PMC_FOCR   (AT91_CAST(AT91_REG *) 0x400E0478)
#define	AT91C_PMC_FSPR   (AT91_CAST(AT91_REG *) 0x400E0474)
#define	AT91C_PMC_SCSR   (AT91_CAST(AT91_REG *) 0x400E0408)
#define	AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 0x400E0464)
#define	AT91C_PMC_VER   (AT91_CAST(AT91_REG *) 0x400E04FC)
#define	AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 0x400E046C)
#define	AT91C_PMC_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E04F4)
#define	AT91C_PMC_SCDR   (AT91_CAST(AT91_REG *) 0x400E0404)
#define	AT91C_PMC_PCKR   (AT91_CAST(AT91_REG *) 0x400E0440)
#define	AT91C_PMC_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E04EC)
#define	AT91C_PMC_PCDR   (AT91_CAST(AT91_REG *) 0x400E0414)
#define	AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 0x400E0420)
#define	AT91C_PMC_SR   (AT91_CAST(AT91_REG *) 0x400E0468)
#define	AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 0x400E0460)
#define	AT91C_PMC_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E04F0)
#define	AT91C_PMC_PCER   (AT91_CAST(AT91_REG *) 0x400E0410)
#define	AT91C_PMC_FEATURES   (AT91_CAST(AT91_REG *) 0x400E04F8)
#define	AT91C_CKGR_PLLAR   (AT91_CAST(AT91_REG *) 0x400E0428)
#define	AT91C_CKGR_UCKR   (AT91_CAST(AT91_REG *) 0x400E041C)
#define	AT91C_CKGR_MOR   (AT91_CAST(AT91_REG *) 0x400E0420)
#define	AT91C_CKGR_MCFR   (AT91_CAST(AT91_REG *) 0x400E0424)
#define	AT91C_RSTC_VER   (AT91_CAST(AT91_REG *) 0x400E12FC)
#define	AT91C_RSTC_RCR   (AT91_CAST(AT91_REG *) 0x400E1200)
#define	AT91C_RSTC_RMR   (AT91_CAST(AT91_REG *) 0x400E1208)
#define	AT91C_RSTC_RSR   (AT91_CAST(AT91_REG *) 0x400E1204)
#define	AT91C_SUPC_CR   (AT91_CAST(AT91_REG *) 0x400E1210)
#define	AT91C_SUPC_SMMR   (AT91_CAST(AT91_REG *) 0x400E1214)
#define	AT91C_SUPC_MR   (AT91_CAST(AT91_REG *) 0x400E1218)
#define	AT91C_SUPC_WUMR   (AT91_CAST(AT91_REG *) 0x400E121C)
#define	AT91C_SUPC_WUIR   (AT91_CAST(AT91_REG *) 0x400E1220)
#define	AT91C_SUPC_SR   (AT91_CAST(AT91_REG *) 0x400E1224)
#define	AT91C_RTTC_RTVR   (AT91_CAST(AT91_REG *) 0x400E1238)
#define	AT91C_RTTC_RTAR   (AT91_CAST(AT91_REG *) 0x400E1234)
#define	AT91C_RTTC_RTMR   (AT91_CAST(AT91_REG *) 0x400E1230)
#define	AT91C_RTTC_RTSR   (AT91_CAST(AT91_REG *) 0x400E123C)
#define	AT91C_WDTC_WDSR   (AT91_CAST(AT91_REG *) 0x400E1258)
#define	AT91C_WDTC_WDMR   (AT91_CAST(AT91_REG *) 0x400E1254)
#define	AT91C_WDTC_WDCR   (AT91_CAST(AT91_REG *) 0x400E1250)
#define	AT91C_RTC_IMR   (AT91_CAST(AT91_REG *) 0x400E1288)
#define	AT91C_RTC_SCCR   (AT91_CAST(AT91_REG *) 0x400E127C)
#define	AT91C_RTC_CALR   (AT91_CAST(AT91_REG *) 0x400E126C)
#define	AT91C_RTC_MR   (AT91_CAST(AT91_REG *) 0x400E1264)
#define	AT91C_RTC_TIMR   (AT91_CAST(AT91_REG *) 0x400E1268)
#define	AT91C_RTC_CALALR   (AT91_CAST(AT91_REG *) 0x400E1274)
#define	AT91C_RTC_VER   (AT91_CAST(AT91_REG *) 0x400E128C)
#define	AT91C_RTC_CR   (AT91_CAST(AT91_REG *) 0x400E1260)
#define	AT91C_RTC_IDR   (AT91_CAST(AT91_REG *) 0x400E1284)
#define	AT91C_RTC_TIMALR   (AT91_CAST(AT91_REG *) 0x400E1270)
#define	AT91C_RTC_IER   (AT91_CAST(AT91_REG *) 0x400E1280)
#define	AT91C_RTC_SR   (AT91_CAST(AT91_REG *) 0x400E1278)
#define	AT91C_ADC0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400AC0F4)
#define	AT91C_ADC0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400AC0EC)
#define	AT91C_ADC0_IDR   (AT91_CAST(AT91_REG *) 0x400AC028)
#define	AT91C_ADC0_CHSR   (AT91_CAST(AT91_REG *) 0x400AC018)
#define	AT91C_ADC0_FEATURES   (AT91_CAST(AT91_REG *) 0x400AC0F8)
#define	AT91C_ADC0_CDR0   (AT91_CAST(AT91_REG *) 0x400AC030)
#define	AT91C_ADC0_LCDR   (AT91_CAST(AT91_REG *) 0x400AC020)
#define	AT91C_ADC0_EMR   (AT91_CAST(AT91_REG *) 0x400AC068)
#define	AT91C_ADC0_CDR3   (AT91_CAST(AT91_REG *) 0x400AC03C)
#define	AT91C_ADC0_CDR7   (AT91_CAST(AT91_REG *) 0x400AC04C)
#define	AT91C_ADC0_SR   (AT91_CAST(AT91_REG *) 0x400AC01C)
#define	AT91C_ADC0_ACR   (AT91_CAST(AT91_REG *) 0x400AC064)
#define	AT91C_ADC0_CDR5   (AT91_CAST(AT91_REG *) 0x400AC044)
#define	AT91C_ADC0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400AC0F0)
#define	AT91C_ADC0_CDR6   (AT91_CAST(AT91_REG *) 0x400AC048)
#define	AT91C_ADC0_MR   (AT91_CAST(AT91_REG *) 0x400AC004)
#define	AT91C_ADC0_CDR1   (AT91_CAST(AT91_REG *) 0x400AC034)
#define	AT91C_ADC0_CDR2   (AT91_CAST(AT91_REG *) 0x400AC038)
#define	AT91C_ADC0_CDR4   (AT91_CAST(AT91_REG *) 0x400AC040)
#define	AT91C_ADC0_CHER   (AT91_CAST(AT91_REG *) 0x400AC010)
#define	AT91C_ADC0_VER   (AT91_CAST(AT91_REG *) 0x400AC0FC)
#define	AT91C_ADC0_CHDR   (AT91_CAST(AT91_REG *) 0x400AC014)
#define	AT91C_ADC0_CR   (AT91_CAST(AT91_REG *) 0x400AC000)
#define	AT91C_ADC0_IMR   (AT91_CAST(AT91_REG *) 0x400AC02C)
#define	AT91C_ADC0_IER   (AT91_CAST(AT91_REG *) 0x400AC024)
#define	AT91C_ADC12B_CR   (AT91_CAST(AT91_REG *) 0x400A8000)
#define	AT91C_ADC12B_MR   (AT91_CAST(AT91_REG *) 0x400A8004)
#define	AT91C_ADC12B_CHER   (AT91_CAST(AT91_REG *) 0x400A8010)
#define	AT91C_ADC12B_CHDR   (AT91_CAST(AT91_REG *) 0x400A8014)
#define	AT91C_ADC12B_CHSR   (AT91_CAST(AT91_REG *) 0x400A8018)
#define	AT91C_ADC12B_SR   (AT91_CAST(AT91_REG *) 0x400A801C)
#define	AT91C_ADC12B_LCDR   (AT91_CAST(AT91_REG *) 0x400A8020)
#define	AT91C_ADC12B_IER   (AT91_CAST(AT91_REG *) 0x400A8024)
#define	AT91C_ADC12B_IDR   (AT91_CAST(AT91_REG *) 0x400A8028)
#define	AT91C_ADC12B_IMR   (AT91_CAST(AT91_REG *) 0x400A802C)
#define	AT91C_ADC12B_CDR   (AT91_CAST(AT91_REG *) 0x400A8030)
#define	AT91C_ADC12B_ACR   (AT91_CAST(AT91_REG *) 0x400A8064)
#define	AT91C_ADC12B_EMR   (AT91_CAST(AT91_REG *) 0x400A8068)
#define	AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 0x40080024)
#define	AT91C_TC0_CV   (AT91_CAST(AT91_REG *) 0x40080010)
#define	AT91C_TC0_RA   (AT91_CAST(AT91_REG *) 0x40080014)
#define	AT91C_TC0_RB   (AT91_CAST(AT91_REG *) 0x40080018)
#define	AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 0x40080028)
#define	AT91C_TC0_SR   (AT91_CAST(AT91_REG *) 0x40080020)
#define	AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 0x4008002C)
#define	AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 0x40080004)
#define	AT91C_TC0_RC   (AT91_CAST(AT91_REG *) 0x4008001C)
#define	AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 0x40080000)
#define	AT91C_TC1_SR   (AT91_CAST(AT91_REG *) 0x40080060)
#define	AT91C_TC1_RA   (AT91_CAST(AT91_REG *) 0x40080054)
#define	AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 0x40080064)
#define	AT91C_TC1_RB   (AT91_CAST(AT91_REG *) 0x40080058)
#define	AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 0x40080068)
#define	AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 0x40080040)
#define	AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 0x4008006C)
#define	AT91C_TC1_RC   (AT91_CAST(AT91_REG *) 0x4008005C)
#define	AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 0x40080044)
#define	AT91C_TC1_CV   (AT91_CAST(AT91_REG *) 0x40080050)
#define	AT91C_TC2_RA   (AT91_CAST(AT91_REG *) 0x40080094)
#define	AT91C_TC2_RB   (AT91_CAST(AT91_REG *) 0x40080098)
#define	AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 0x40080084)
#define	AT91C_TC2_SR   (AT91_CAST(AT91_REG *) 0x400800A0)
#define	AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 0x40080080)
#define	AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 0x400800AC)
#define	AT91C_TC2_CV   (AT91_CAST(AT91_REG *) 0x40080090)
#define	AT91C_TC2_RC   (AT91_CAST(AT91_REG *) 0x4008009C)
#define	AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 0x400800A4)
#define	AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 0x400800A8)
#define	AT91C_TCB0_BCR   (AT91_CAST(AT91_REG *) 0x400800C0)
#define	AT91C_TCB0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400800F4)
#define	AT91C_TCB0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400800F0)
#define	AT91C_TCB0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400800EC)
#define	AT91C_TCB0_FEATURES   (AT91_CAST(AT91_REG *) 0x400800F8)
#define	AT91C_TCB0_BMR   (AT91_CAST(AT91_REG *) 0x400800C4)
#define	AT91C_TCB0_VER   (AT91_CAST(AT91_REG *) 0x400800FC)
#define	AT91C_TCB1_BCR   (AT91_CAST(AT91_REG *) 0x40080100)
#define	AT91C_TCB1_VER   (AT91_CAST(AT91_REG *) 0x4008013C)
#define	AT91C_TCB1_FEATURES   (AT91_CAST(AT91_REG *) 0x40080138)
#define	AT91C_TCB1_IPNAME2   (AT91_CAST(AT91_REG *) 0x40080134)
#define	AT91C_TCB1_BMR   (AT91_CAST(AT91_REG *) 0x40080104)
#define	AT91C_TCB1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008012C)
#define	AT91C_TCB1_IPNAME1   (AT91_CAST(AT91_REG *) 0x40080130)
#define	AT91C_TCB2_FEATURES   (AT91_CAST(AT91_REG *) 0x40080178)
#define	AT91C_TCB2_VER   (AT91_CAST(AT91_REG *) 0x4008017C)
#define	AT91C_TCB2_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008016C)
#define	AT91C_TCB2_IPNAME1   (AT91_CAST(AT91_REG *) 0x40080170)
#define	AT91C_TCB2_IPNAME2   (AT91_CAST(AT91_REG *) 0x40080174)
#define	AT91C_TCB2_BMR   (AT91_CAST(AT91_REG *) 0x40080144)
#define	AT91C_TCB2_BCR   (AT91_CAST(AT91_REG *) 0x40080140)
#define	AT91C_EFC0_FCR   (AT91_CAST(AT91_REG *) 0x400E0804)
#define	AT91C_EFC0_FRR   (AT91_CAST(AT91_REG *) 0x400E080C)
#define	AT91C_EFC0_FMR   (AT91_CAST(AT91_REG *) 0x400E0800)
#define	AT91C_EFC0_FSR   (AT91_CAST(AT91_REG *) 0x400E0808)
#define	AT91C_EFC0_FVR   (AT91_CAST(AT91_REG *) 0x400E0814)
#define	AT91C_EFC1_FMR   (AT91_CAST(AT91_REG *) 0x400E0A00)
#define	AT91C_EFC1_FVR   (AT91_CAST(AT91_REG *) 0x400E0A14)
#define	AT91C_EFC1_FSR   (AT91_CAST(AT91_REG *) 0x400E0A08)
#define	AT91C_EFC1_FCR   (AT91_CAST(AT91_REG *) 0x400E0A04)
#define	AT91C_EFC1_FRR   (AT91_CAST(AT91_REG *) 0x400E0A0C)
#define	AT91C_MCI0_DMA   (AT91_CAST(AT91_REG *) 0x40000050)
#define	AT91C_MCI0_SDCR   (AT91_CAST(AT91_REG *) 0x4000000C)
#define	AT91C_MCI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400000F0)
#define	AT91C_MCI0_CSTOR   (AT91_CAST(AT91_REG *) 0x4000001C)
#define	AT91C_MCI0_RDR   (AT91_CAST(AT91_REG *) 0x40000030)
#define	AT91C_MCI0_CMDR   (AT91_CAST(AT91_REG *) 0x40000014)
#define	AT91C_MCI0_IDR   (AT91_CAST(AT91_REG *) 0x40000048)
#define	AT91C_MCI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400000EC)
#define	AT91C_MCI0_WPCR   (AT91_CAST(AT91_REG *) 0x400000E4)
#define	AT91C_MCI0_RSPR   (AT91_CAST(AT91_REG *) 0x40000020)
#define	AT91C_MCI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400000F4)
#define	AT91C_MCI0_CR   (AT91_CAST(AT91_REG *) 0x40000000)
#define	AT91C_MCI0_IMR   (AT91_CAST(AT91_REG *) 0x4000004C)
#define	AT91C_MCI0_WPSR   (AT91_CAST(AT91_REG *) 0x400000E8)
#define	AT91C_MCI0_DTOR   (AT91_CAST(AT91_REG *) 0x40000008)
#define	AT91C_MCI0_MR   (AT91_CAST(AT91_REG *) 0x40000004)
#define	AT91C_MCI0_SR   (AT91_CAST(AT91_REG *) 0x40000040)
#define	AT91C_MCI0_IER   (AT91_CAST(AT91_REG *) 0x40000044)
#define	AT91C_MCI0_VER   (AT91_CAST(AT91_REG *) 0x400000FC)
#define	AT91C_MCI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400000F8)
#define	AT91C_MCI0_BLKR   (AT91_CAST(AT91_REG *) 0x40000018)
#define	AT91C_MCI0_ARGR   (AT91_CAST(AT91_REG *) 0x40000010)
#define	AT91C_MCI0_FIFO   (AT91_CAST(AT91_REG *) 0x40000200)
#define	AT91C_MCI0_TDR   (AT91_CAST(AT91_REG *) 0x40000034)
#define	AT91C_MCI0_CFG   (AT91_CAST(AT91_REG *) 0x40000054)
#define	AT91C_TWI0_TNCR   (AT91_CAST(AT91_REG *) 0x4008411C)
#define	AT91C_TWI0_PTCR   (AT91_CAST(AT91_REG *) 0x40084120)
#define	AT91C_TWI0_PTSR   (AT91_CAST(AT91_REG *) 0x40084124)
#define	AT91C_TWI0_RCR   (AT91_CAST(AT91_REG *) 0x40084104)
#define	AT91C_TWI0_TNPR   (AT91_CAST(AT91_REG *) 0x40084118)
#define	AT91C_TWI0_RNPR   (AT91_CAST(AT91_REG *) 0x40084110)
#define	AT91C_TWI0_RPR   (AT91_CAST(AT91_REG *) 0x40084100)
#define	AT91C_TWI0_RNCR   (AT91_CAST(AT91_REG *) 0x40084114)
#define	AT91C_TWI0_TPR   (AT91_CAST(AT91_REG *) 0x40084108)
#define	AT91C_TWI0_TCR   (AT91_CAST(AT91_REG *) 0x4008410C)
#define	AT91C_TWI1_TNCR   (AT91_CAST(AT91_REG *) 0x4008811C)
#define	AT91C_TWI1_PTCR   (AT91_CAST(AT91_REG *) 0x40088120)
#define	AT91C_TWI1_RNCR   (AT91_CAST(AT91_REG *) 0x40088114)
#define	AT91C_TWI1_RCR   (AT91_CAST(AT91_REG *) 0x40088104)
#define	AT91C_TWI1_RPR   (AT91_CAST(AT91_REG *) 0x40088100)
#define	AT91C_TWI1_TNPR   (AT91_CAST(AT91_REG *) 0x40088118)
#define	AT91C_TWI1_RNPR   (AT91_CAST(AT91_REG *) 0x40088110)
#define	AT91C_TWI1_TCR   (AT91_CAST(AT91_REG *) 0x4008810C)
#define	AT91C_TWI1_TPR   (AT91_CAST(AT91_REG *) 0x40088108)
#define	AT91C_TWI1_PTSR   (AT91_CAST(AT91_REG *) 0x40088124)
#define	AT91C_TWI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400840F8)
#define	AT91C_TWI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400840F0)
#define	AT91C_TWI0_SMR   (AT91_CAST(AT91_REG *) 0x40084008)
#define	AT91C_TWI0_MMR   (AT91_CAST(AT91_REG *) 0x40084004)
#define	AT91C_TWI0_SR   (AT91_CAST(AT91_REG *) 0x40084020)
#define	AT91C_TWI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400840F4)
#define	AT91C_TWI0_CR   (AT91_CAST(AT91_REG *) 0x40084000)
#define	AT91C_TWI0_IER   (AT91_CAST(AT91_REG *) 0x40084024)
#define	AT91C_TWI0_RHR   (AT91_CAST(AT91_REG *) 0x40084030)
#define	AT91C_TWI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400840EC)
#define	AT91C_TWI0_THR   (AT91_CAST(AT91_REG *) 0x40084034)
#define	AT91C_TWI0_VER   (AT91_CAST(AT91_REG *) 0x400840FC)
#define	AT91C_TWI0_IADR   (AT91_CAST(AT91_REG *) 0x4008400C)
#define	AT91C_TWI0_IMR   (AT91_CAST(AT91_REG *) 0x4008402C)
#define	AT91C_TWI0_CWGR   (AT91_CAST(AT91_REG *) 0x40084010)
#define	AT91C_TWI0_IDR   (AT91_CAST(AT91_REG *) 0x40084028)
#define	AT91C_TWI1_VER   (AT91_CAST(AT91_REG *) 0x400880FC)
#define	AT91C_TWI1_IDR   (AT91_CAST(AT91_REG *) 0x40088028)
#define	AT91C_TWI1_IPNAME2   (AT91_CAST(AT91_REG *) 0x400880F4)
#define	AT91C_TWI1_CWGR   (AT91_CAST(AT91_REG *) 0x40088010)
#define	AT91C_TWI1_CR   (AT91_CAST(AT91_REG *) 0x40088000)
#define	AT91C_TWI1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400880EC)
#define	AT91C_TWI1_IADR   (AT91_CAST(AT91_REG *) 0x4008800C)
#define	AT91C_TWI1_IER   (AT91_CAST(AT91_REG *) 0x40088024)
#define	AT91C_TWI1_SMR   (AT91_CAST(AT91_REG *) 0x40088008)
#define	AT91C_TWI1_RHR   (AT91_CAST(AT91_REG *) 0x40088030)
#define	AT91C_TWI1_FEATURES   (AT91_CAST(AT91_REG *) 0x400880F8)
#define	AT91C_TWI1_IMR   (AT91_CAST(AT91_REG *) 0x4008802C)
#define	AT91C_TWI1_SR   (AT91_CAST(AT91_REG *) 0x40088020)
#define	AT91C_TWI1_THR   (AT91_CAST(AT91_REG *) 0x40088034)
#define	AT91C_TWI1_MMR   (AT91_CAST(AT91_REG *) 0x40088004)
#define	AT91C_TWI1_IPNAME1   (AT91_CAST(AT91_REG *) 0x400880F0)
#define	AT91C_US0_RNCR   (AT91_CAST(AT91_REG *) 0x40090114)
#define	AT91C_US0_TNPR   (AT91_CAST(AT91_REG *) 0x40090118)
#define	AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 0x40090108)
#define	AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 0x40090104)
#define	AT91C_US0_RNPR   (AT91_CAST(AT91_REG *) 0x40090110)
#define	AT91C_US0_TNCR   (AT91_CAST(AT91_REG *) 0x4009011C)
#define	AT91C_US0_PTSR   (AT91_CAST(AT91_REG *) 0x40090124)
#define	AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 0x40090100)
#define	AT91C_US0_PTCR   (AT91_CAST(AT91_REG *) 0x40090120)
#define	AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 0x4009010C)
#define	AT91C_US0_NER   (AT91_CAST(AT91_REG *) 0x40090044)
#define	AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 0x40090018)
#define	AT91C_US0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400900F0)
#define	AT91C_US0_MR   (AT91_CAST(AT91_REG *) 0x40090004)
#define	AT91C_US0_RTOR   (AT91_CAST(AT91_REG *) 0x40090024)
#define	AT91C_US0_IF   (AT91_CAST(AT91_REG *) 0x4009004C)
#define	AT91C_US0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400900EC)
#define	AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 0x4009000C)
#define	AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 0x40090010)
#define	AT91C_US0_IER   (AT91_CAST(AT91_REG *) 0x40090008)
#define	AT91C_US0_TTGR   (AT91_CAST(AT91_REG *) 0x40090028)
#define	AT91C_US0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400900F4)
#define	AT91C_US0_FIDI   (AT91_CAST(AT91_REG *) 0x40090040)
#define	AT91C_US0_CR   (AT91_CAST(AT91_REG *) 0x40090000)
#define	AT91C_US0_BRGR   (AT91_CAST(AT91_REG *) 0x40090020)
#define	AT91C_US0_MAN   (AT91_CAST(AT91_REG *) 0x40090050)
#define	AT91C_US0_VER   (AT91_CAST(AT91_REG *) 0x400900FC)
#define	AT91C_US0_FEATURES   (AT91_CAST(AT91_REG *) 0x400900F8)
#define	AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 0x40090014)
#define	AT91C_US0_THR   (AT91_CAST(AT91_REG *) 0x4009001C)
#define	AT91C_US1_TNPR   (AT91_CAST(AT91_REG *) 0x40094118)
#define	AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 0x40094108)
#define	AT91C_US1_RNCR   (AT91_CAST(AT91_REG *) 0x40094114)
#define	AT91C_US1_TNCR   (AT91_CAST(AT91_REG *) 0x4009411C)
#define	AT91C_US1_RNPR   (AT91_CAST(AT91_REG *) 0x40094110)
#define	AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 0x4009410C)
#define	AT91C_US1_PTSR   (AT91_CAST(AT91_REG *) 0x40094124)
#define	AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 0x40094104)
#define	AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 0x40094100)
#define	AT91C_US1_PTCR   (AT91_CAST(AT91_REG *) 0x40094120)
#define	AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 0x40094010)
#define	AT91C_US1_RTOR   (AT91_CAST(AT91_REG *) 0x40094024)
#define	AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 0x40094018)
#define	AT91C_US1_IPNAME1   (AT91_CAST(AT91_REG *) 0x400940F0)
#define	AT91C_US1_VER   (AT91_CAST(AT91_REG *) 0x400940FC)
#define	AT91C_US1_MR   (AT91_CAST(AT91_REG *) 0x40094004)
#define	AT91C_US1_FEATURES   (AT91_CAST(AT91_REG *) 0x400940F8)
#define	AT91C_US1_NER   (AT91_CAST(AT91_REG *) 0x40094044)
#define	AT91C_US1_IPNAME2   (AT91_CAST(AT91_REG *) 0x400940F4)
#define	AT91C_US1_CR   (AT91_CAST(AT91_REG *) 0x40094000)
#define	AT91C_US1_BRGR   (AT91_CAST(AT91_REG *) 0x40094020)
#define	AT91C_US1_IF   (AT91_CAST(AT91_REG *) 0x4009404C)
#define	AT91C_US1_IER   (AT91_CAST(AT91_REG *) 0x40094008)
#define	AT91C_US1_TTGR   (AT91_CAST(AT91_REG *) 0x40094028)
#define	AT91C_US1_FIDI   (AT91_CAST(AT91_REG *) 0x40094040)
#define	AT91C_US1_MAN   (AT91_CAST(AT91_REG *) 0x40094050)
#define	AT91C_US1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400940EC)
#define	AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 0x40094014)
#define	AT91C_US1_THR   (AT91_CAST(AT91_REG *) 0x4009401C)
#define	AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 0x4009400C)
#define	AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 0x40098100)
#define	AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 0x40098108)
#define	AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 0x4009810C)
#define	AT91C_US2_PTSR   (AT91_CAST(AT91_REG *) 0x40098124)
#define	AT91C_US2_PTCR   (AT91_CAST(AT91_REG *) 0x40098120)
#define	AT91C_US2_RNPR   (AT91_CAST(AT91_REG *) 0x40098110)
#define	AT91C_US2_TNCR   (AT91_CAST(AT91_REG *) 0x4009811C)
#define	AT91C_US2_RNCR   (AT91_CAST(AT91_REG *) 0x40098114)
#define	AT91C_US2_TNPR   (AT91_CAST(AT91_REG *) 0x40098118)
#define	AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 0x40098104)
#define	AT91C_US2_MAN   (AT91_CAST(AT91_REG *) 0x40098050)
#define	AT91C_US2_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400980EC)
#define	AT91C_US2_MR   (AT91_CAST(AT91_REG *) 0x40098004)
#define	AT91C_US2_IPNAME1   (AT91_CAST(AT91_REG *) 0x400980F0)
#define	AT91C_US2_IF   (AT91_CAST(AT91_REG *) 0x4009804C)
#define	AT91C_US2_BRGR   (AT91_CAST(AT91_REG *) 0x40098020)
#define	AT91C_US2_FIDI   (AT91_CAST(AT91_REG *) 0x40098040)
#define	AT91C_US2_IER   (AT91_CAST(AT91_REG *) 0x40098008)
#define	AT91C_US2_RTOR   (AT91_CAST(AT91_REG *) 0x40098024)
#define	AT91C_US2_CR   (AT91_CAST(AT91_REG *) 0x40098000)
#define	AT91C_US2_THR   (AT91_CAST(AT91_REG *) 0x4009801C)
#define	AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 0x40098014)
#define	AT91C_US2_VER   (AT91_CAST(AT91_REG *) 0x400980FC)
#define	AT91C_US2_FEATURES   (AT91_CAST(AT91_REG *) 0x400980F8)
#define	AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 0x4009800C)
#define	AT91C_US2_TTGR   (AT91_CAST(AT91_REG *) 0x40098028)
#define	AT91C_US2_IPNAME2   (AT91_CAST(AT91_REG *) 0x400980F4)
#define	AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 0x40098018)
#define	AT91C_US2_NER   (AT91_CAST(AT91_REG *) 0x40098044)
#define	AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 0x40098010)
#define	AT91C_US3_TPR   (AT91_CAST(AT91_REG *) 0x4009C108)
#define	AT91C_US3_PTCR   (AT91_CAST(AT91_REG *) 0x4009C120)
#define	AT91C_US3_TCR   (AT91_CAST(AT91_REG *) 0x4009C10C)
#define	AT91C_US3_RCR   (AT91_CAST(AT91_REG *) 0x4009C104)
#define	AT91C_US3_RNCR   (AT91_CAST(AT91_REG *) 0x4009C114)
#define	AT91C_US3_RNPR   (AT91_CAST(AT91_REG *) 0x4009C110)
#define	AT91C_US3_RPR   (AT91_CAST(AT91_REG *) 0x4009C100)
#define	AT91C_US3_PTSR   (AT91_CAST(AT91_REG *) 0x4009C124)
#define	AT91C_US3_TNCR   (AT91_CAST(AT91_REG *) 0x4009C11C)
#define	AT91C_US3_TNPR   (AT91_CAST(AT91_REG *) 0x4009C118)
#define	AT91C_US3_MAN   (AT91_CAST(AT91_REG *) 0x4009C050)
#define	AT91C_US3_CSR   (AT91_CAST(AT91_REG *) 0x4009C014)
#define	AT91C_US3_BRGR   (AT91_CAST(AT91_REG *) 0x4009C020)
#define	AT91C_US3_IPNAME2   (AT91_CAST(AT91_REG *) 0x4009C0F4)
#define	AT91C_US3_RTOR   (AT91_CAST(AT91_REG *) 0x4009C024)
#define	AT91C_US3_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4009C0EC)
#define	AT91C_US3_CR   (AT91_CAST(AT91_REG *) 0x4009C000)
#define	AT91C_US3_IF   (AT91_CAST(AT91_REG *) 0x4009C04C)
#define	AT91C_US3_FEATURES   (AT91_CAST(AT91_REG *) 0x4009C0F8)
#define	AT91C_US3_VER   (AT91_CAST(AT91_REG *) 0x4009C0FC)
#define	AT91C_US3_RHR   (AT91_CAST(AT91_REG *) 0x4009C018)
#define	AT91C_US3_TTGR   (AT91_CAST(AT91_REG *) 0x4009C028)
#define	AT91C_US3_NER   (AT91_CAST(AT91_REG *) 0x4009C044)
#define	AT91C_US3_IMR   (AT91_CAST(AT91_REG *) 0x4009C010)
#define	AT91C_US3_THR   (AT91_CAST(AT91_REG *) 0x4009C01C)
#define	AT91C_US3_IDR   (AT91_CAST(AT91_REG *) 0x4009C00C)
#define	AT91C_US3_MR   (AT91_CAST(AT91_REG *) 0x4009C004)
#define	AT91C_US3_IER   (AT91_CAST(AT91_REG *) 0x4009C008)
#define	AT91C_US3_FIDI   (AT91_CAST(AT91_REG *) 0x4009C040)
#define	AT91C_US3_IPNAME1   (AT91_CAST(AT91_REG *) 0x4009C0F0)
#define	AT91C_SSC0_RNCR   (AT91_CAST(AT91_REG *) 0x40004114)
#define	AT91C_SSC0_TPR   (AT91_CAST(AT91_REG *) 0x40004108)
#define	AT91C_SSC0_TCR   (AT91_CAST(AT91_REG *) 0x4000410C)
#define	AT91C_SSC0_PTCR   (AT91_CAST(AT91_REG *) 0x40004120)
#define	AT91C_SSC0_TNPR   (AT91_CAST(AT91_REG *) 0x40004118)
#define	AT91C_SSC0_RPR   (AT91_CAST(AT91_REG *) 0x40004100)
#define	AT91C_SSC0_TNCR   (AT91_CAST(AT91_REG *) 0x4000411C)
#define	AT91C_SSC0_RNPR   (AT91_CAST(AT91_REG *) 0x40004110)
#define	AT91C_SSC0_RCR   (AT91_CAST(AT91_REG *) 0x40004104)
#define	AT91C_SSC0_PTSR   (AT91_CAST(AT91_REG *) 0x40004124)
#define	AT91C_SSC0_FEATURES   (AT91_CAST(AT91_REG *) 0x400040F8)
#define	AT91C_SSC0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400040F0)
#define	AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 0x40004000)
#define	AT91C_SSC0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400040EC)
#define	AT91C_SSC0_RHR   (AT91_CAST(AT91_REG *) 0x40004020)
#define	AT91C_SSC0_VER   (AT91_CAST(AT91_REG *) 0x400040FC)
#define	AT91C_SSC0_TSHR   (AT91_CAST(AT91_REG *) 0x40004034)
#define	AT91C_SSC0_RFMR   (AT91_CAST(AT91_REG *) 0x40004014)
#define	AT91C_SSC0_IDR   (AT91_CAST(AT91_REG *) 0x40004048)
#define	AT91C_SSC0_TFMR   (AT91_CAST(AT91_REG *) 0x4000401C)
#define	AT91C_SSC0_RSHR   (AT91_CAST(AT91_REG *) 0x40004030)
#define	AT91C_SSC0_TCMR   (AT91_CAST(AT91_REG *) 0x40004018)
#define	AT91C_SSC0_RCMR   (AT91_CAST(AT91_REG *) 0x40004010)
#define	AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 0x40004040)
#define	AT91C_SSC0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400040F4)
#define	AT91C_SSC0_THR   (AT91_CAST(AT91_REG *) 0x40004024)
#define	AT91C_SSC0_CMR   (AT91_CAST(AT91_REG *) 0x40004004)
#define	AT91C_SSC0_IER   (AT91_CAST(AT91_REG *) 0x40004044)
#define	AT91C_SSC0_IMR   (AT91_CAST(AT91_REG *) 0x4000404C)
#define	AT91C_PWMC_TNCR   (AT91_CAST(AT91_REG *) 0x4008C11C)
#define	AT91C_PWMC_TPR   (AT91_CAST(AT91_REG *) 0x4008C108)
#define	AT91C_PWMC_RPR   (AT91_CAST(AT91_REG *) 0x4008C100)
#define	AT91C_PWMC_TCR   (AT91_CAST(AT91_REG *) 0x4008C10C)
#define	AT91C_PWMC_PTSR   (AT91_CAST(AT91_REG *) 0x4008C124)
#define	AT91C_PWMC_RNPR   (AT91_CAST(AT91_REG *) 0x4008C110)
#define	AT91C_PWMC_RCR   (AT91_CAST(AT91_REG *) 0x4008C104)
#define	AT91C_PWMC_RNCR   (AT91_CAST(AT91_REG *) 0x4008C114)
#define	AT91C_PWMC_PTCR   (AT91_CAST(AT91_REG *) 0x4008C120)
#define	AT91C_PWMC_TNPR   (AT91_CAST(AT91_REG *) 0x4008C118)
#define	AT91C_PWMC_CH0_DTR   (AT91_CAST(AT91_REG *) 0x4008C218)
#define	AT91C_PWMC_CH0_CMR   (AT91_CAST(AT91_REG *) 0x4008C200)
#define	AT91C_PWMC_CH0_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C214)
#define	AT91C_PWMC_CH0_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C20C)
#define	AT91C_PWMC_CH0_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C21C)
#define	AT91C_PWMC_CH0_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C210)
#define	AT91C_PWMC_CH0_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C208)
#define	AT91C_PWMC_CH0_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C204)
#define	AT91C_PWMC_CH1_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C234)
#define	AT91C_PWMC_CH1_DTR   (AT91_CAST(AT91_REG *) 0x4008C238)
#define	AT91C_PWMC_CH1_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C228)
#define	AT91C_PWMC_CH1_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C23C)
#define	AT91C_PWMC_CH1_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C224)
#define	AT91C_PWMC_CH1_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C22C)
#define	AT91C_PWMC_CH1_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C230)
#define	AT91C_PWMC_CH1_CMR   (AT91_CAST(AT91_REG *) 0x4008C220)
#define	AT91C_PWMC_CH2_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C244)
#define	AT91C_PWMC_CH2_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C25C)
#define	AT91C_PWMC_CH2_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C254)
#define	AT91C_PWMC_CH2_CMR   (AT91_CAST(AT91_REG *) 0x4008C240)
#define	AT91C_PWMC_CH2_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C24C)
#define	AT91C_PWMC_CH2_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C250)
#define	AT91C_PWMC_CH2_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C248)
#define	AT91C_PWMC_CH2_DTR   (AT91_CAST(AT91_REG *) 0x4008C258)
#define	AT91C_PWMC_CH3_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C270)
#define	AT91C_PWMC_CH3_DTR   (AT91_CAST(AT91_REG *) 0x4008C278)
#define	AT91C_PWMC_CH3_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C264)
#define	AT91C_PWMC_CH3_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C27C)
#define	AT91C_PWMC_CH3_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C268)
#define	AT91C_PWMC_CH3_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C274)
#define	AT91C_PWMC_CH3_CMR   (AT91_CAST(AT91_REG *) 0x4008C260)
#define	AT91C_PWMC_CH3_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C26C)
#define	AT91C_PWMC_CMP6MUPD   (AT91_CAST(AT91_REG *) 0x4008C19C)
#define	AT91C_PWMC_ISR1   (AT91_CAST(AT91_REG *) 0x4008C01C)
#define	AT91C_PWMC_CMP5V   (AT91_CAST(AT91_REG *) 0x4008C180)
#define	AT91C_PWMC_CMP4MUPD   (AT91_CAST(AT91_REG *) 0x4008C17C)
#define	AT91C_PWMC_FMR   (AT91_CAST(AT91_REG *) 0x4008C05C)
#define	AT91C_PWMC_CMP6V   (AT91_CAST(AT91_REG *) 0x4008C190)
#define	AT91C_PWMC_EL4MR   (AT91_CAST(AT91_REG *) 0x4008C08C)
#define	AT91C_PWMC_UPCR   (AT91_CAST(AT91_REG *) 0x4008C028)
#define	AT91C_PWMC_CMP1VUPD   (AT91_CAST(AT91_REG *) 0x4008C144)
#define	AT91C_PWMC_CMP0M   (AT91_CAST(AT91_REG *) 0x4008C138)
#define	AT91C_PWMC_CMP5VUPD   (AT91_CAST(AT91_REG *) 0x4008C184)
#define	AT91C_PWMC_FPER3   (AT91_CAST(AT91_REG *) 0x4008C074)
#define	AT91C_PWMC_OSCUPD   (AT91_CAST(AT91_REG *) 0x4008C058)
#define	AT91C_PWMC_FPER1   (AT91_CAST(AT91_REG *) 0x4008C06C)
#define	AT91C_PWMC_SCUPUPD   (AT91_CAST(AT91_REG *) 0x4008C030)
#define	AT91C_PWMC_DIS   (AT91_CAST(AT91_REG *) 0x4008C008)
#define	AT91C_PWMC_IER1   (AT91_CAST(AT91_REG *) 0x4008C010)
#define	AT91C_PWMC_IMR2   (AT91_CAST(AT91_REG *) 0x4008C03C)
#define	AT91C_PWMC_CMP0V   (AT91_CAST(AT91_REG *) 0x4008C130)
#define	AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 0x4008C00C)
#define	AT91C_PWMC_CMP4M   (AT91_CAST(AT91_REG *) 0x4008C178)
#define	AT91C_PWMC_CMP3M   (AT91_CAST(AT91_REG *) 0x4008C168)
#define	AT91C_PWMC_IER2   (AT91_CAST(AT91_REG *) 0x4008C034)
#define	AT91C_PWMC_CMP3VUPD   (AT91_CAST(AT91_REG *) 0x4008C164)
#define	AT91C_PWMC_CMP2M   (AT91_CAST(AT91_REG *) 0x4008C158)
#define	AT91C_PWMC_IDR2   (AT91_CAST(AT91_REG *) 0x4008C038)
#define	AT91C_PWMC_EL2MR   (AT91_CAST(AT91_REG *) 0x4008C084)
#define	AT91C_PWMC_CMP7V   (AT91_CAST(AT91_REG *) 0x4008C1A0)
#define	AT91C_PWMC_CMP1M   (AT91_CAST(AT91_REG *) 0x4008C148)
#define	AT91C_PWMC_CMP0VUPD   (AT91_CAST(AT91_REG *) 0x4008C134)
#define	AT91C_PWMC_WPSR   (AT91_CAST(AT91_REG *) 0x4008C0E8)
#define	AT91C_PWMC_CMP6VUPD   (AT91_CAST(AT91_REG *) 0x4008C194)
#define	AT91C_PWMC_CMP1MUPD   (AT91_CAST(AT91_REG *) 0x4008C14C)
#define	AT91C_PWMC_CMP1V   (AT91_CAST(AT91_REG *) 0x4008C140)
#define	AT91C_PWMC_FCR   (AT91_CAST(AT91_REG *) 0x4008C064)
#define	AT91C_PWMC_VER   (AT91_CAST(AT91_REG *) 0x4008C0FC)
#define	AT91C_PWMC_EL1MR   (AT91_CAST(AT91_REG *) 0x4008C080)
#define	AT91C_PWMC_EL6MR   (AT91_CAST(AT91_REG *) 0x4008C094)
#define	AT91C_PWMC_ISR2   (AT91_CAST(AT91_REG *) 0x4008C040)
#define	AT91C_PWMC_CMP4VUPD   (AT91_CAST(AT91_REG *) 0x4008C174)
#define	AT91C_PWMC_CMP5MUPD   (AT91_CAST(AT91_REG *) 0x4008C18C)
#define	AT91C_PWMC_OS   (AT91_CAST(AT91_REG *) 0x4008C048)
#define	AT91C_PWMC_FPV   (AT91_CAST(AT91_REG *) 0x4008C068)
#define	AT91C_PWMC_FPER2   (AT91_CAST(AT91_REG *) 0x4008C070)
#define	AT91C_PWMC_EL7MR   (AT91_CAST(AT91_REG *) 0x4008C098)
#define	AT91C_PWMC_OSSUPD   (AT91_CAST(AT91_REG *) 0x4008C054)
#define	AT91C_PWMC_FEATURES   (AT91_CAST(AT91_REG *) 0x4008C0F8)
#define	AT91C_PWMC_CMP2V   (AT91_CAST(AT91_REG *) 0x4008C150)
#define	AT91C_PWMC_FSR   (AT91_CAST(AT91_REG *) 0x4008C060)
#define	AT91C_PWMC_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008C0EC)
#define	AT91C_PWMC_OSC   (AT91_CAST(AT91_REG *) 0x4008C050)
#define	AT91C_PWMC_SCUP   (AT91_CAST(AT91_REG *) 0x4008C02C)
#define	AT91C_PWMC_CMP7MUPD   (AT91_CAST(AT91_REG *) 0x4008C1AC)
#define	AT91C_PWMC_CMP2VUPD   (AT91_CAST(AT91_REG *) 0x4008C154)
#define	AT91C_PWMC_FPER4   (AT91_CAST(AT91_REG *) 0x4008C078)
#define	AT91C_PWMC_IMR1   (AT91_CAST(AT91_REG *) 0x4008C018)
#define	AT91C_PWMC_EL3MR   (AT91_CAST(AT91_REG *) 0x4008C088)
#define	AT91C_PWMC_CMP3V   (AT91_CAST(AT91_REG *) 0x4008C160)
#define	AT91C_PWMC_IPNAME1   (AT91_CAST(AT91_REG *) 0x4008C0F0)
#define	AT91C_PWMC_OSS   (AT91_CAST(AT91_REG *) 0x4008C04C)
#define	AT91C_PWMC_CMP0MUPD   (AT91_CAST(AT91_REG *) 0x4008C13C)
#define	AT91C_PWMC_CMP2MUPD   (AT91_CAST(AT91_REG *) 0x4008C15C)
#define	AT91C_PWMC_CMP4V   (AT91_CAST(AT91_REG *) 0x4008C170)
#define	AT91C_PWMC_ENA   (AT91_CAST(AT91_REG *) 0x4008C004)
#define	AT91C_PWMC_CMP3MUPD   (AT91_CAST(AT91_REG *) 0x4008C16C)
#define	AT91C_PWMC_EL0MR   (AT91_CAST(AT91_REG *) 0x4008C07C)
#define	AT91C_PWMC_OOV   (AT91_CAST(AT91_REG *) 0x4008C044)
#define	AT91C_PWMC_WPCR   (AT91_CAST(AT91_REG *) 0x4008C0E4)
#define	AT91C_PWMC_CMP7M   (AT91_CAST(AT91_REG *) 0x4008C1A8)
#define	AT91C_PWMC_CMP6M   (AT91_CAST(AT91_REG *) 0x4008C198)
#define	AT91C_PWMC_CMP5M   (AT91_CAST(AT91_REG *) 0x4008C188)
#define	AT91C_PWMC_IPNAME2   (AT91_CAST(AT91_REG *) 0x4008C0F4)
#define	AT91C_PWMC_CMP7VUPD   (AT91_CAST(AT91_REG *) 0x4008C1A4)
#define	AT91C_PWMC_SYNC   (AT91_CAST(AT91_REG *) 0x4008C020)
#define	AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 0x4008C000)
#define	AT91C_PWMC_IDR1   (AT91_CAST(AT91_REG *) 0x4008C014)
#define	AT91C_PWMC_EL5MR   (AT91_CAST(AT91_REG *) 0x4008C090)
#define	AT91C_SPI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400080EC)
#define	AT91C_SPI0_RDR   (AT91_CAST(AT91_REG *) 0x40008008)
#define	AT91C_SPI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400080F8)
#define	AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 0x40008000)
#define	AT91C_SPI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400080F0)
#define	AT91C_SPI0_VER   (AT91_CAST(AT91_REG *) 0x400080FC)
#define	AT91C_SPI0_IDR   (AT91_CAST(AT91_REG *) 0x40008018)
#define	AT91C_SPI0_TDR   (AT91_CAST(AT91_REG *) 0x4000800C)
#define	AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 0x40008004)
#define	AT91C_SPI0_IER   (AT91_CAST(AT91_REG *) 0x40008014)
#define	AT91C_SPI0_IMR   (AT91_CAST(AT91_REG *) 0x4000801C)
#define	AT91C_SPI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400080F4)
#define	AT91C_SPI0_CSR   (AT91_CAST(AT91_REG *) 0x40008030)
#define	AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 0x40008010)
#define	AT91C_UDPHS_EPTFIFO_READEPT6   (AT91_CAST(AT91_REG *) 0x201E0000)
#define	AT91C_UDPHS_EPTFIFO_READEPT2   (AT91_CAST(AT91_REG *) 0x201A0000)
#define	AT91C_UDPHS_EPTFIFO_READEPT1   (AT91_CAST(AT91_REG *) 0x20190000)
#define	AT91C_UDPHS_EPTFIFO_READEPT0   (AT91_CAST(AT91_REG *) 0x20180000)
#define	AT91C_UDPHS_EPTFIFO_READEPT5   (AT91_CAST(AT91_REG *) 0x201D0000)
#define	AT91C_UDPHS_EPTFIFO_READEPT4   (AT91_CAST(AT91_REG *) 0x201C0000)
#define	AT91C_UDPHS_EPTFIFO_READEPT3   (AT91_CAST(AT91_REG *) 0x201B0000)
#define	AT91C_UDPHS_EPT_0_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A410C)
#define	AT91C_UDPHS_EPT_0_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A411C)
#define	AT91C_UDPHS_EPT_0_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4118)
#define	AT91C_UDPHS_EPT_0_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4108)
#define	AT91C_UDPHS_EPT_0_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4100)
#define	AT91C_UDPHS_EPT_0_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4114)
#define	AT91C_UDPHS_EPT_0_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4104)
#define	AT91C_UDPHS_EPT_1_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A413C)
#define	AT91C_UDPHS_EPT_1_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4134)
#define	AT91C_UDPHS_EPT_1_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A412C)
#define	AT91C_UDPHS_EPT_1_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4120)
#define	AT91C_UDPHS_EPT_1_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4128)
#define	AT91C_UDPHS_EPT_1_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4138)
#define	AT91C_UDPHS_EPT_1_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4124)
#define	AT91C_UDPHS_EPT_2_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4144)
#define	AT91C_UDPHS_EPT_2_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4158)
#define	AT91C_UDPHS_EPT_2_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4140)
#define	AT91C_UDPHS_EPT_2_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A414C)
#define	AT91C_UDPHS_EPT_2_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4154)
#define	AT91C_UDPHS_EPT_2_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A415C)
#define	AT91C_UDPHS_EPT_2_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4148)
#define	AT91C_UDPHS_EPT_3_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4168)
#define	AT91C_UDPHS_EPT_3_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4164)
#define	AT91C_UDPHS_EPT_3_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4174)
#define	AT91C_UDPHS_EPT_3_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4178)
#define	AT91C_UDPHS_EPT_3_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4160)
#define	AT91C_UDPHS_EPT_3_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A417C)
#define	AT91C_UDPHS_EPT_3_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A416C)
#define	AT91C_UDPHS_EPT_4_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4194)
#define	AT91C_UDPHS_EPT_4_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4188)
#define	AT91C_UDPHS_EPT_4_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A418C)
#define	AT91C_UDPHS_EPT_4_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4180)
#define	AT91C_UDPHS_EPT_4_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4184)
#define	AT91C_UDPHS_EPT_4_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A419C)
#define	AT91C_UDPHS_EPT_4_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4198)
#define	AT91C_UDPHS_EPT_5_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A41A0)
#define	AT91C_UDPHS_EPT_5_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A41AC)
#define	AT91C_UDPHS_EPT_5_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A41A4)
#define	AT91C_UDPHS_EPT_5_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A41BC)
#define	AT91C_UDPHS_EPT_5_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A41B4)
#define	AT91C_UDPHS_EPT_5_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A41A8)
#define	AT91C_UDPHS_EPT_5_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A41B8)
#define	AT91C_UDPHS_EPT_6_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A41D8)
#define	AT91C_UDPHS_EPT_6_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A41CC)
#define	AT91C_UDPHS_EPT_6_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A41C0)
#define	AT91C_UDPHS_EPT_6_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A41C8)
#define	AT91C_UDPHS_EPT_6_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A41DC)
#define	AT91C_UDPHS_EPT_6_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A41C4)
#define	AT91C_UDPHS_EPT_6_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A41D4)
#define	AT91C_UDPHS_DMA_1_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A431C)
#define	AT91C_UDPHS_DMA_1_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4318)
#define	AT91C_UDPHS_DMA_1_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4310)
#define	AT91C_UDPHS_DMA_1_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4314)
#define	AT91C_UDPHS_DMA_2_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A432C)
#define	AT91C_UDPHS_DMA_2_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4320)
#define	AT91C_UDPHS_DMA_2_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4328)
#define	AT91C_UDPHS_DMA_2_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4324)
#define	AT91C_UDPHS_DMA_3_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4338)
#define	AT91C_UDPHS_DMA_3_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4330)
#define	AT91C_UDPHS_DMA_3_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A433C)
#define	AT91C_UDPHS_DMA_3_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4334)
#define	AT91C_UDPHS_DMA_4_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4344)
#define	AT91C_UDPHS_DMA_4_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4340)
#define	AT91C_UDPHS_DMA_4_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A434C)
#define	AT91C_UDPHS_DMA_4_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4348)
#define	AT91C_UDPHS_DMA_5_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4358)
#define	AT91C_UDPHS_DMA_5_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4354)
#define	AT91C_UDPHS_DMA_5_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4350)
#define	AT91C_UDPHS_DMA_5_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A435C)
#define	AT91C_UDPHS_DMA_6_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A436C)
#define	AT91C_UDPHS_DMA_6_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4368)
#define	AT91C_UDPHS_DMA_6_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4360)
#define	AT91C_UDPHS_DMA_6_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4364)
#define	AT91C_UDPHS_EPTRST   (AT91_CAST(AT91_REG *) 0x400A401C)
#define	AT91C_UDPHS_IEN   (AT91_CAST(AT91_REG *) 0x400A4010)
#define	AT91C_UDPHS_TSTCNTB   (AT91_CAST(AT91_REG *) 0x400A40D8)
#define	AT91C_UDPHS_RIPNAME2   (AT91_CAST(AT91_REG *) 0x400A40F4)
#define	AT91C_UDPHS_RIPPADDRSIZE   (AT91_CAST(AT91_REG *) 0x400A40EC)
#define	AT91C_UDPHS_TSTMODREG   (AT91_CAST(AT91_REG *) 0x400A40DC)
#define	AT91C_UDPHS_TST   (AT91_CAST(AT91_REG *) 0x400A40E0)
#define	AT91C_UDPHS_TSTSOFCNT   (AT91_CAST(AT91_REG *) 0x400A40D0)
#define	AT91C_UDPHS_FNUM   (AT91_CAST(AT91_REG *) 0x400A4004)
#define	AT91C_UDPHS_TSTCNTA   (AT91_CAST(AT91_REG *) 0x400A40D4)
#define	AT91C_UDPHS_INTSTA   (AT91_CAST(AT91_REG *) 0x400A4014)
#define	AT91C_UDPHS_IPFEATURES   (AT91_CAST(AT91_REG *) 0x400A40F8)
#define	AT91C_UDPHS_CLRINT   (AT91_CAST(AT91_REG *) 0x400A4018)
#define	AT91C_UDPHS_RIPNAME1   (AT91_CAST(AT91_REG *) 0x400A40F0)
#define	AT91C_UDPHS_CTRL   (AT91_CAST(AT91_REG *) 0x400A4000)
#define	AT91C_UDPHS_IPVERSION   (AT91_CAST(AT91_REG *) 0x400A40FC)
#define	AT91C_HDMA_CH_0_CADDR   (AT91_CAST(AT91_REG *) 0x400B0060)
#define	AT91C_HDMA_CH_0_DADDR   (AT91_CAST(AT91_REG *) 0x400B0040)
#define	AT91C_HDMA_CH_0_BDSCR   (AT91_CAST(AT91_REG *) 0x400B005C)
#define	AT91C_HDMA_CH_0_CFG   (AT91_CAST(AT91_REG *) 0x400B0050)
#define	AT91C_HDMA_CH_0_CTRLB   (AT91_CAST(AT91_REG *) 0x400B004C)
#define	AT91C_HDMA_CH_0_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0048)
#define	AT91C_HDMA_CH_0_DSCR   (AT91_CAST(AT91_REG *) 0x400B0044)
#define	AT91C_HDMA_CH_0_SADDR   (AT91_CAST(AT91_REG *) 0x400B003C)
#define	AT91C_HDMA_CH_0_DPIP   (AT91_CAST(AT91_REG *) 0x400B0058)
#define	AT91C_HDMA_CH_0_SPIP   (AT91_CAST(AT91_REG *) 0x400B0054)
#define	AT91C_HDMA_CH_1_DSCR   (AT91_CAST(AT91_REG *) 0x400B006C)
#define	AT91C_HDMA_CH_1_BDSCR   (AT91_CAST(AT91_REG *) 0x400B0084)
#define	AT91C_HDMA_CH_1_CTRLB   (AT91_CAST(AT91_REG *) 0x400B0074)
#define	AT91C_HDMA_CH_1_SPIP   (AT91_CAST(AT91_REG *) 0x400B007C)
#define	AT91C_HDMA_CH_1_SADDR   (AT91_CAST(AT91_REG *) 0x400B0064)
#define	AT91C_HDMA_CH_1_DPIP   (AT91_CAST(AT91_REG *) 0x400B0080)
#define	AT91C_HDMA_CH_1_CFG   (AT91_CAST(AT91_REG *) 0x400B0078)
#define	AT91C_HDMA_CH_1_DADDR   (AT91_CAST(AT91_REG *) 0x400B0068)
#define	AT91C_HDMA_CH_1_CADDR   (AT91_CAST(AT91_REG *) 0x400B0088)
#define	AT91C_HDMA_CH_1_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0070)
#define	AT91C_HDMA_CH_2_BDSCR   (AT91_CAST(AT91_REG *) 0x400B00AC)
#define	AT91C_HDMA_CH_2_CTRLB   (AT91_CAST(AT91_REG *) 0x400B009C)
#define	AT91C_HDMA_CH_2_CADDR   (AT91_CAST(AT91_REG *) 0x400B00B0)
#define	AT91C_HDMA_CH_2_CFG   (AT91_CAST(AT91_REG *) 0x400B00A0)
#define	AT91C_HDMA_CH_2_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0098)
#define	AT91C_HDMA_CH_2_SADDR   (AT91_CAST(AT91_REG *) 0x400B008C)
#define	AT91C_HDMA_CH_2_DPIP   (AT91_CAST(AT91_REG *) 0x400B00A8)
#define	AT91C_HDMA_CH_2_DADDR   (AT91_CAST(AT91_REG *) 0x400B0090)
#define	AT91C_HDMA_CH_2_SPIP   (AT91_CAST(AT91_REG *) 0x400B00A4)
#define	AT91C_HDMA_CH_2_DSCR   (AT91_CAST(AT91_REG *) 0x400B0094)
#define	AT91C_HDMA_CH_3_DSCR   (AT91_CAST(AT91_REG *) 0x400B00BC)
#define	AT91C_HDMA_CH_3_SADDR   (AT91_CAST(AT91_REG *) 0x400B00B4)
#define	AT91C_HDMA_CH_3_BDSCR   (AT91_CAST(AT91_REG *) 0x400B00D4)
#define	AT91C_HDMA_CH_3_CTRLA   (AT91_CAST(AT91_REG *) 0x400B00C0)
#define	AT91C_HDMA_CH_3_DPIP   (AT91_CAST(AT91_REG *) 0x400B00D0)
#define	AT91C_HDMA_CH_3_CTRLB   (AT91_CAST(AT91_REG *) 0x400B00C4)
#define	AT91C_HDMA_CH_3_SPIP   (AT91_CAST(AT91_REG *) 0x400B00CC)
#define	AT91C_HDMA_CH_3_CFG   (AT91_CAST(AT91_REG *) 0x400B00C8)
#define	AT91C_HDMA_CH_3_CADDR   (AT91_CAST(AT91_REG *) 0x400B00D8)
#define	AT91C_HDMA_CH_3_DADDR   (AT91_CAST(AT91_REG *) 0x400B00B8)
#define	AT91C_HDMA_SYNC   (AT91_CAST(AT91_REG *) 0x400B0014)
#define	AT91C_HDMA_VER   (AT91_CAST(AT91_REG *) 0x400B01FC)
#define	AT91C_HDMA_RSVD0   (AT91_CAST(AT91_REG *) 0x400B0034)
#define	AT91C_HDMA_CHSR   (AT91_CAST(AT91_REG *) 0x400B0030)
#define	AT91C_HDMA_IPNAME2   (AT91_CAST(AT91_REG *) 0x400B01F4)
#define	AT91C_HDMA_EBCIMR   (AT91_CAST(AT91_REG *) 0x400B0020)
#define	AT91C_HDMA_CHDR   (AT91_CAST(AT91_REG *) 0x400B002C)
#define	AT91C_HDMA_EN   (AT91_CAST(AT91_REG *) 0x400B0004)
#define	AT91C_HDMA_GCFG   (AT91_CAST(AT91_REG *) 0x400B0000)
#define	AT91C_HDMA_IPNAME1   (AT91_CAST(AT91_REG *) 0x400B01F0)
#define	AT91C_HDMA_LAST   (AT91_CAST(AT91_REG *) 0x400B0010)
#define	AT91C_HDMA_FEATURES   (AT91_CAST(AT91_REG *) 0x400B01F8)
#define	AT91C_HDMA_CREQ   (AT91_CAST(AT91_REG *) 0x400B000C)
#define	AT91C_HDMA_EBCIER   (AT91_CAST(AT91_REG *) 0x400B0018)
#define	AT91C_HDMA_CHER   (AT91_CAST(AT91_REG *) 0x400B0028)
#define	AT91C_HDMA_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400B01EC)
#define	AT91C_HDMA_EBCISR   (AT91_CAST(AT91_REG *) 0x400B0024)
#define	AT91C_HDMA_SREQ   (AT91_CAST(AT91_REG *) 0x400B0008)
#define	AT91C_HDMA_EBCIDR   (AT91_CAST(AT91_REG *) 0x400B001C)
#define	AT91C_HDMA_RSVD1   (AT91_CAST(AT91_REG *) 0x400B0038)
#define	AT91C_PIO_PA0   (1 << 0)
#define	AT91C_PA0_TIOB0   (AT91C_PIO_PA0)
#define	AT91C_PA0_SPI0_NPCS1   (AT91C_PIO_PA0)
#define	AT91C_PIO_PA1   (1 << 1)
#define	AT91C_PA1_TIOA0   (AT91C_PIO_PA1)
#define	AT91C_PA1_SPI0_NPCS2   (AT91C_PIO_PA1)
#define	AT91C_PIO_PA10   (1 << 10)
#define	AT91C_PA10_TWCK0   (AT91C_PIO_PA10)
#define	AT91C_PA10_PWML3   (AT91C_PIO_PA10)
#define	AT91C_PIO_PA11   (1 << 11)
#define	AT91C_PA11_DRXD   (AT91C_PIO_PA11)
#define	AT91C_PIO_PA12   (1 << 12)
#define	AT91C_PA12_DTXD   (AT91C_PIO_PA12)
#define	AT91C_PIO_PA13   (1 << 13)
#define	AT91C_PA13_SPI0_MISO   (AT91C_PIO_PA13)
#define	AT91C_PIO_PA14   (1 << 14)
#define	AT91C_PA14_SPI0_MOSI   (AT91C_PIO_PA14)
#define	AT91C_PIO_PA15   (1 << 15)
#define	AT91C_PA15_SPI0_SPCK   (AT91C_PIO_PA15)
#define	AT91C_PA15_PWMH2   (AT91C_PIO_PA15)
#define	AT91C_PIO_PA16   (1 << 16)
#define	AT91C_PA16_SPI0_NPCS0   (AT91C_PIO_PA16)
#define	AT91C_PA16_NCS1   (AT91C_PIO_PA16)
#define	AT91C_PIO_PA17   (1 << 17)
#define	AT91C_PA17_SCK0   (AT91C_PIO_PA17)
#define	AT91C_PIO_PA18   (1 << 18)
#define	AT91C_PA18_TXD0   (AT91C_PIO_PA18)
#define	AT91C_PIO_PA19   (1 << 19)
#define	AT91C_PA19_RXD0   (AT91C_PIO_PA19)
#define	AT91C_PA19_SPI0_NPCS3   (AT91C_PIO_PA19)
#define	AT91C_PIO_PA2   (1 << 2)
#define	AT91C_PA2_TCLK0   (AT91C_PIO_PA2)
#define	AT91C_PA2_ADTRG1   (AT91C_PIO_PA2)
#define	AT91C_PIO_PA20   (1 << 20)
#define	AT91C_PA20_TXD1   (AT91C_PIO_PA20)
#define	AT91C_PA20_PWMH3   (AT91C_PIO_PA20)
#define	AT91C_PIO_PA21   (1 << 21)
#define	AT91C_PA21_RXD1   (AT91C_PIO_PA21)
#define	AT91C_PA21_PCK0   (AT91C_PIO_PA21)
#define	AT91C_PIO_PA22   (1 << 22)
#define	AT91C_PA22_TXD2   (AT91C_PIO_PA22)
#define	AT91C_PA22_RTS1   (AT91C_PIO_PA22)
#define	AT91C_PIO_PA23   (1 << 23)
#define	AT91C_PA23_RXD2   (AT91C_PIO_PA23)
#define	AT91C_PA23_CTS1   (AT91C_PIO_PA23)
#define	AT91C_PIO_PA24   (1 << 24)
#define	AT91C_PA24_TWD1   (AT91C_PIO_PA24)
#define	AT91C_PA24_SCK1   (AT91C_PIO_PA24)
#define	AT91C_PIO_PA25   (1 << 25)
#define	AT91C_PA25_TWCK1   (AT91C_PIO_PA25)
#define	AT91C_PA25_SCK2   (AT91C_PIO_PA25)
#define	AT91C_PIO_PA26   (1 << 26)
#define	AT91C_PA26_TD0   (AT91C_PIO_PA26)
#define	AT91C_PA26_TCLK2   (AT91C_PIO_PA26)
#define	AT91C_PIO_PA27   (1 << 27)
#define	AT91C_PA27_RD0   (AT91C_PIO_PA27)
#define	AT91C_PA27_PCK0   (AT91C_PIO_PA27)
#define	AT91C_PIO_PA28   (1 << 28)
#define	AT91C_PA28_TK0   (AT91C_PIO_PA28)
#define	AT91C_PA28_PWMH0   (AT91C_PIO_PA28)
#define	AT91C_PIO_PA29   (1 << 29)
#define	AT91C_PA29_RK0   (AT91C_PIO_PA29)
#define	AT91C_PA29_PWMH1   (AT91C_PIO_PA29)
#define	AT91C_PIO_PA3   (1 << 3)
#define	AT91C_PA3_MCI0_CK   (AT91C_PIO_PA3)
#define	AT91C_PA3_PCK1   (AT91C_PIO_PA3)
#define	AT91C_PIO_PA30   (1 << 30)
#define	AT91C_PA30_TF0   (AT91C_PIO_PA30)
#define	AT91C_PA30_TIOA2   (AT91C_PIO_PA30)
#define	AT91C_PIO_PA31   (1 << 31)
#define	AT91C_PA31_RF0   (AT91C_PIO_PA31)
#define	AT91C_PA31_TIOB2   (AT91C_PIO_PA31)
#define	AT91C_PIO_PA4   (1 << 4)
#define	AT91C_PA4_MCI0_CDA   (AT91C_PIO_PA4)
#define	AT91C_PA4_PWMH0   (AT91C_PIO_PA4)
#define	AT91C_PIO_PA5   (1 << 5)
#define	AT91C_PA5_MCI0_DA0   (AT91C_PIO_PA5)
#define	AT91C_PA5_PWMH1   (AT91C_PIO_PA5)
#define	AT91C_PIO_PA6   (1 << 6)
#define	AT91C_PA6_MCI0_DA1   (AT91C_PIO_PA6)
#define	AT91C_PA6_PWMH2   (AT91C_PIO_PA6)
#define	AT91C_PIO_PA7   (1 << 7)
#define	AT91C_PA7_MCI0_DA2   (AT91C_PIO_PA7)
#define	AT91C_PA7_PWML0   (AT91C_PIO_PA7)
#define	AT91C_PIO_PA8   (1 << 8)
#define	AT91C_PA8_MCI0_DA3   (AT91C_PIO_PA8)
#define	AT91C_PA8_PWML1   (AT91C_PIO_PA8)
#define	AT91C_PIO_PA9   (1 << 9)
#define	AT91C_PA9_TWD0   (AT91C_PIO_PA9)
#define	AT91C_PA9_PWML2   (AT91C_PIO_PA9)
#define	AT91C_PIO_PB0   (1 << 0)
#define	AT91C_PB0_PWMH0   (AT91C_PIO_PB0)
#define	AT91C_PB0_A2   (AT91C_PIO_PB0)
#define	AT91C_PIO_PB1   (1 << 1)
#define	AT91C_PB1_PWMH1   (AT91C_PIO_PB1)
#define	AT91C_PB1_A3   (AT91C_PIO_PB1)
#define	AT91C_PIO_PB10   (1 << 10)
#define	AT91C_PB10_D1   (AT91C_PIO_PB10)
#define	AT91C_PB10_DSR0   (AT91C_PIO_PB10)
#define	AT91C_PIO_PB11   (1 << 11)
#define	AT91C_PB11_D2   (AT91C_PIO_PB11)
#define	AT91C_PB11_DCD0   (AT91C_PIO_PB11)
#define	AT91C_PIO_PB12   (1 << 12)
#define	AT91C_PB12_D3   (AT91C_PIO_PB12)
#define	AT91C_PB12_RI0   (AT91C_PIO_PB12)
#define	AT91C_PIO_PB13   (1 << 13)
#define	AT91C_PB13_D4   (AT91C_PIO_PB13)
#define	AT91C_PB13_PWMH0   (AT91C_PIO_PB13)
#define	AT91C_PIO_PB14   (1 << 14)
#define	AT91C_PB14_D5   (AT91C_PIO_PB14)
#define	AT91C_PB14_PWMH1   (AT91C_PIO_PB14)
#define	AT91C_PIO_PB15   (1 << 15)
#define	AT91C_PB15_D6   (AT91C_PIO_PB15)
#define	AT91C_PB15_PWMH2   (AT91C_PIO_PB15)
#define	AT91C_PIO_PB16   (1 << 16)
#define	AT91C_PB16_D7   (AT91C_PIO_PB16)
#define	AT91C_PB16_PWMH3   (AT91C_PIO_PB16)
#define	AT91C_PIO_PB17   (1 << 17)
#define	AT91C_PB17_NANDOE   (AT91C_PIO_PB17)
#define	AT91C_PB17_PWML0   (AT91C_PIO_PB17)
#define	AT91C_PIO_PB18   (1 << 18)
#define	AT91C_PB18_NANDWE   (AT91C_PIO_PB18)
#define	AT91C_PB18_PWML1   (AT91C_PIO_PB18)
#define	AT91C_PIO_PB19   (1 << 19)
#define	AT91C_PB19_NRD   (AT91C_PIO_PB19)
#define	AT91C_PB19_PWML2   (AT91C_PIO_PB19)
#define	AT91C_PIO_PB2   (1 << 2)
#define	AT91C_PB2_PWMH2   (AT91C_PIO_PB2)
#define	AT91C_PB2_A4   (AT91C_PIO_PB2)
#define	AT91C_PIO_PB20   (1 << 20)
#define	AT91C_PB20_NCS0   (AT91C_PIO_PB20)
#define	AT91C_PB20_PWML3   (AT91C_PIO_PB20)
#define	AT91C_PIO_PB21   (1 << 21)
#define	AT91C_PB21_A21_NANDALE   (AT91C_PIO_PB21)
#define	AT91C_PB21_RTS2   (AT91C_PIO_PB21)
#define	AT91C_PIO_PB22   (1 << 22)
#define	AT91C_PB22_A22_NANDCLE   (AT91C_PIO_PB22)
#define	AT91C_PB22_CTS2   (AT91C_PIO_PB22)
#define	AT91C_PIO_PB23   (1 << 23)
#define	AT91C_PB23_NWR0_NWE   (AT91C_PIO_PB23)
#define	AT91C_PB23_PCK2   (AT91C_PIO_PB23)
#define	AT91C_PIO_PB24   (1 << 24)
#define	AT91C_PB24_NANDRDY   (AT91C_PIO_PB24)
#define	AT91C_PB24_PCK1   (AT91C_PIO_PB24)
#define	AT91C_PIO_PB25   (1 << 25)
#define	AT91C_PB25_D8   (AT91C_PIO_PB25)
#define	AT91C_PB25_PWML0   (AT91C_PIO_PB25)
#define	AT91C_PIO_PB26   (1 << 26)
#define	AT91C_PB26_D9   (AT91C_PIO_PB26)
#define	AT91C_PB26_PWML1   (AT91C_PIO_PB26)
#define	AT91C_PIO_PB27   (1 << 27)
#define	AT91C_PB27_D10   (AT91C_PIO_PB27)
#define	AT91C_PB27_PWML2   (AT91C_PIO_PB27)
#define	AT91C_PIO_PB28   (1 << 28)
#define	AT91C_PB28_D11   (AT91C_PIO_PB28)
#define	AT91C_PB28_PWML3   (AT91C_PIO_PB28)
#define	AT91C_PIO_PB29   (1 << 29)
#define	AT91C_PB29_D12   (AT91C_PIO_PB29)
#define	AT91C_PIO_PB3   (1 << 3)
#define	AT91C_PB3_PWMH3   (AT91C_PIO_PB3)
#define	AT91C_PB3_A5   (AT91C_PIO_PB3)
#define	AT91C_PIO_PB30   (1 << 30)
#define	AT91C_PB30_D13   (AT91C_PIO_PB30)
#define	AT91C_PIO_PB31   (1 << 31)
#define	AT91C_PB31_D14   (AT91C_PIO_PB31)
#define	AT91C_PIO_PB4   (1 << 4)
#define	AT91C_PB4_TCLK1   (AT91C_PIO_PB4)
#define	AT91C_PB4_A6   (AT91C_PIO_PB4)
#define	AT91C_PIO_PB5   (1 << 5)
#define	AT91C_PB5_TIOA1   (AT91C_PIO_PB5)
#define	AT91C_PB5_A7   (AT91C_PIO_PB5)
#define	AT91C_PIO_PB6   (1 << 6)
#define	AT91C_PB6_TIOB1   (AT91C_PIO_PB6)
#define	AT91C_PB6_D15   (AT91C_PIO_PB6)
#define	AT91C_PIO_PB7   (1 << 7)
#define	AT91C_PB7_RTS0   (AT91C_PIO_PB7)
#define	AT91C_PB7_A0_NBS0   (AT91C_PIO_PB7)
#define	AT91C_PIO_PB8   (1 << 8)
#define	AT91C_PB8_CTS0   (AT91C_PIO_PB8)
#define	AT91C_PB8_A1   (AT91C_PIO_PB8)
#define	AT91C_PIO_PB9   (1 << 9)
#define	AT91C_PB9_D0   (AT91C_PIO_PB9)
#define	AT91C_PB9_DTR0   (AT91C_PIO_PB9)
#define	AT91C_PIO_PC0   (1 << 0)
#define	AT91C_PC0_A2   (AT91C_PIO_PC0)
#define	AT91C_PIO_PC1   (1 << 1)
#define	AT91C_PC1_A3   (AT91C_PIO_PC1)
#define	AT91C_PIO_PC10   (1 << 10)
#define	AT91C_PC10_A12   (AT91C_PIO_PC10)
#define	AT91C_PC10_CTS3   (AT91C_PIO_PC10)
#define	AT91C_PIO_PC11   (1 << 11)
#define	AT91C_PC11_A13   (AT91C_PIO_PC11)
#define	AT91C_PC11_RTS3   (AT91C_PIO_PC11)
#define	AT91C_PIO_PC12   (1 << 12)
#define	AT91C_PC12_NCS1   (AT91C_PIO_PC12)
#define	AT91C_PC12_TXD3   (AT91C_PIO_PC12)
#define	AT91C_PIO_PC13   (1 << 13)
#define	AT91C_PC13_A2   (AT91C_PIO_PC13)
#define	AT91C_PC13_RXD3   (AT91C_PIO_PC13)
#define	AT91C_PIO_PC14   (1 << 14)
#define	AT91C_PC14_A3   (AT91C_PIO_PC14)
#define	AT91C_PC14_SPI0_NPCS2   (AT91C_PIO_PC14)
#define	AT91C_PIO_PC15   (1 << 15)
#define	AT91C_PC15_NWR1_NBS1   (AT91C_PIO_PC15)
#define	AT91C_PIO_PC16   (1 << 16)
#define	AT91C_PC16_NCS2   (AT91C_PIO_PC16)
#define	AT91C_PC16_PWML3   (AT91C_PIO_PC16)
#define	AT91C_PIO_PC17   (1 << 17)
#define	AT91C_PC17_NCS3   (AT91C_PIO_PC17)
#define	AT91C_PC17_A24   (AT91C_PIO_PC17)
#define	AT91C_PIO_PC18   (1 << 18)
#define	AT91C_PC18_NWAIT   (AT91C_PIO_PC18)
#define	AT91C_PIO_PC19   (1 << 19)
#define	AT91C_PC19_SCK3   (AT91C_PIO_PC19)
#define	AT91C_PC19_NPCS1   (AT91C_PIO_PC19)
#define	AT91C_PIO_PC2   (1 << 2)
#define	AT91C_PC2_A4   (AT91C_PIO_PC2)
#define	AT91C_PIO_PC20   (1 << 20)
#define	AT91C_PC20_A14   (AT91C_PIO_PC20)
#define	AT91C_PIO_PC21   (1 << 21)
#define	AT91C_PC21_A15   (AT91C_PIO_PC21)
#define	AT91C_PIO_PC22   (1 << 22)
#define	AT91C_PC22_A16   (AT91C_PIO_PC22)
#define	AT91C_PIO_PC23   (1 << 23)
#define	AT91C_PC23_A17   (AT91C_PIO_PC23)
#define	AT91C_PIO_PC24   (1 << 24)
#define	AT91C_PC24_A18   (AT91C_PIO_PC24)
#define	AT91C_PC24_PWMH0   (AT91C_PIO_PC24)
#define	AT91C_PIO_PC25   (1 << 25)
#define	AT91C_PC25_A19   (AT91C_PIO_PC25)
#define	AT91C_PC25_PWMH1   (AT91C_PIO_PC25)
#define	AT91C_PIO_PC26   (1 << 26)
#define	AT91C_PC26_A20   (AT91C_PIO_PC26)
#define	AT91C_PC26_PWMH2   (AT91C_PIO_PC26)
#define	AT91C_PIO_PC27   (1 << 27)
#define	AT91C_PC27_A23   (AT91C_PIO_PC27)
#define	AT91C_PC27_PWMH3   (AT91C_PIO_PC27)
#define	AT91C_PIO_PC28   (1 << 28)
#define	AT91C_PC28_A24   (AT91C_PIO_PC28)
#define	AT91C_PC28_MCI0_DA4   (AT91C_PIO_PC28)
#define	AT91C_PIO_PC29   (1 << 29)
#define	AT91C_PC29_PWML0   (AT91C_PIO_PC29)
#define	AT91C_PC29_MCI0_DA5   (AT91C_PIO_PC29)
#define	AT91C_PIO_PC3   (1 << 3)
#define	AT91C_PC3_A5   (AT91C_PIO_PC3)
#define	AT91C_PC3_SPI0_NPCS1   (AT91C_PIO_PC3)
#define	AT91C_PIO_PC30   (1 << 30)
#define	AT91C_PC30_PWML1   (AT91C_PIO_PC30)
#define	AT91C_PC30_MCI0_DA6   (AT91C_PIO_PC30)
#define	AT91C_PIO_PC31   (1 << 31)
#define	AT91C_PC31_PWML2   (AT91C_PIO_PC31)
#define	AT91C_PC31_MCI0_DA7   (AT91C_PIO_PC31)
#define	AT91C_PIO_PC4   (1 << 4)
#define	AT91C_PC4_A6   (AT91C_PIO_PC4)
#define	AT91C_PC4_SPI0_NPCS2   (AT91C_PIO_PC4)
#define	AT91C_PIO_PC5   (1 << 5)
#define	AT91C_PC5_A7   (AT91C_PIO_PC5)
#define	AT91C_PC5_SPI0_NPCS3   (AT91C_PIO_PC5)
#define	AT91C_PIO_PC6   (1 << 6)
#define	AT91C_PC6_A8   (AT91C_PIO_PC6)
#define	AT91C_PC6_PWML0   (AT91C_PIO_PC6)
#define	AT91C_PIO_PC7   (1 << 7)
#define	AT91C_PC7_A9   (AT91C_PIO_PC7)
#define	AT91C_PC7_PWML1   (AT91C_PIO_PC7)
#define	AT91C_PIO_PC8   (1 << 8)
#define	AT91C_PC8_A10   (AT91C_PIO_PC8)
#define	AT91C_PC8_PWML2   (AT91C_PIO_PC8)
#define	AT91C_PIO_PC9   (1 << 9)
#define	AT91C_PC9_A11   (AT91C_PIO_PC9)
#define	AT91C_PC9_PWML3   (AT91C_PIO_PC9)
#define	AT91C_ID_SUPC   ( 0)
#define	AT91C_ID_RSTC   ( 1)
#define	AT91C_ID_RTC   ( 2)
#define	AT91C_ID_RTT   ( 3)
#define	AT91C_ID_WDG   ( 4)
#define	AT91C_ID_PMC   ( 5)
#define	AT91C_ID_EFC0   ( 6)
#define	AT91C_ID_EFC1   ( 7)
#define	AT91C_ID_DBGU   ( 8)
#define	AT91C_ID_HSMC4   ( 9)
#define	AT91C_ID_PIOA   (10)
#define	AT91C_ID_PIOB   (11)
#define	AT91C_ID_PIOC   (12)
#define	AT91C_ID_US0   (13)
#define	AT91C_ID_US1   (14)
#define	AT91C_ID_US2   (15)
#define	AT91C_ID_US3   (16)
#define	AT91C_ID_MCI0   (17)
#define	AT91C_ID_TWI0   (18)
#define	AT91C_ID_TWI1   (19)
#define	AT91C_ID_SPI0   (20)
#define	AT91C_ID_SSC0   (21)
#define	AT91C_ID_TC0   (22)
#define	AT91C_ID_TC1   (23)
#define	AT91C_ID_TC2   (24)
#define	AT91C_ID_PWMC   (25)
#define	AT91C_ID_ADC12B   (26)
#define	AT91C_ID_ADC   (27)
#define	AT91C_ID_HDMA   (28)
#define	AT91C_ID_UDPHS   (29)
#define	AT91C_ALL_INT   (0x3FFFFFFF)
#define	AT91C_BASE_SYS   (AT91_CAST(AT91PS_SYS) 0x400E0000)
#define	AT91C_BASE_HSMC4_CS0   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0070)
#define	AT91C_BASE_HSMC4_CS1   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0084)
#define	AT91C_BASE_HSMC4_CS2   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0098)
#define	AT91C_BASE_HSMC4_CS3   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00AC)
#define	AT91C_BASE_HSMC4_NFC   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00FC)
#define	AT91C_BASE_HSMC4   (AT91_CAST(AT91PS_HSMC4) 0x400E0000)
#define	AT91C_BASE_MATRIX   (AT91_CAST(AT91PS_HMATRIX2) 0x400E0200)
#define	AT91C_BASE_NVIC   (AT91_CAST(AT91PS_NVIC) 0xE000E000)
#define	AT91C_BASE_MPU   (AT91_CAST(AT91PS_MPU) 0xE000ED90)
#define	AT91C_BASE_CM3   (AT91_CAST(AT91PS_CM3) 0xE000ED00)
#define	AT91C_BASE_PDC_DBGU   (AT91_CAST(AT91PS_PDC) 0x400E0700)
#define	AT91C_BASE_DBGU   ( 0x400E0600)
#define	AT91C_BASE_PIOA   (AT91_CAST(AT91PS_PIO) 0x400E0C00)
#define	AT91C_BASE_PIOB   (AT91_CAST(AT91PS_PIO) 0x400E0E00)
#define	AT91C_BASE_PIOC   (AT91_CAST(AT91PS_PIO) 0x400E1000)
#define	AT91C_BASE_PMC   (AT91_CAST(AT91PS_PMC) 0x400E0400)
#define	AT91C_BASE_CKGR   (AT91_CAST(AT91PS_CKGR) 0x400E041C)
#define	AT91C_BASE_RSTC   (AT91_CAST(AT91PS_RSTC) 0x400E1200)
#define	AT91C_BASE_SUPC   (AT91_CAST(AT91PS_SUPC) 0x400E1210)
#define	AT91C_BASE_RTTC   (AT91_CAST(AT91PS_RTTC) 0x400E1230)
#define	AT91C_BASE_WDTC   (AT91_CAST(AT91PS_WDTC) 0x400E1250)
#define	AT91C_BASE_RTC   (AT91_CAST(AT91PS_RTC) 0x400E1260)
#define	AT91C_BASE_ADC0   (AT91_CAST(AT91PS_ADC) 0x400AC000)
#define	AT91C_BASE_ADC12B   (AT91_CAST(AT91PS_ADC12B ) 0x400A8000)
#define	AT91C_BASE_TC0   (AT91_CAST(AT91PS_TC) 0x40080000)
#define	AT91C_BASE_TC1   (AT91_CAST(AT91PS_TC) 0x40080040)
#define	AT91C_BASE_TC2   (AT91_CAST(AT91PS_TC) 0x40080080)
#define	AT91C_BASE_TCB0   (AT91_CAST(AT91PS_TCB) 0x40080000)
#define	AT91C_BASE_TCB1   (AT91_CAST(AT91PS_TCB) 0x40080040)
#define	AT91C_BASE_TCB2   (AT91_CAST(AT91PS_TCB) 0x40080080)
#define	AT91C_BASE_EFC0   (AT91_CAST(AT91PS_EFC) 0x400E0800)
#define	AT91C_BASE_EFC1   (AT91_CAST(AT91PS_EFC) 0x400E0A00)
#define	AT91C_BASE_MCI0   (AT91_CAST(AT91PS_MCI) 0x40000000)
#define	AT91C_BASE_PDC_TWI0   (AT91_CAST(AT91PS_PDC) 0x40084100)
#define	AT91C_BASE_PDC_TWI1   (AT91_CAST(AT91PS_PDC) 0x40088100)
#define	AT91C_BASE_TWI0   (AT91_CAST(AT91PS_TWI) 0x40084000)
#define	AT91C_BASE_TWI1   (AT91_CAST(AT91PS_TWI) 0x40088000)
#define	AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 0x40090100)
#define	AT91C_BASE_US0   (AT91_CAST(AT91PS_USART) 0x40090000)
#define	AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 0x40094100)
#define	AT91C_BASE_US1   (AT91_CAST(AT91PS_USART) 0x40094000)
#define	AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 0x40098100)
#define	AT91C_BASE_US2   (AT91_CAST(AT91PS_USART) 0x40098000)
#define	AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC) 0x4009C100)
#define	AT91C_BASE_US3   (AT91_CAST(AT91PS_USART) 0x4009C000)
#define	AT91C_BASE_PDC_SSC0   (AT91_CAST(AT91PS_PDC) 0x40004100)
#define	AT91C_BASE_SSC0   (AT91_CAST(AT91PS_SSC) 0x40004000)
#define	AT91C_BASE_PDC_PWMC   (AT91_CAST(AT91PS_PDC) 0x4008C100)
#define	AT91C_BASE_PWMC_CH0   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C200)
#define	AT91C_BASE_PWMC_CH1   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C220)
#define	AT91C_BASE_PWMC_CH2   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C240)
#define	AT91C_BASE_PWMC_CH3   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C260)
#define	AT91C_BASE_PWMC   (AT91_CAST(AT91PS_PWMC) 0x4008C000)
#define	AT91C_BASE_SPI0   (AT91_CAST(AT91PS_SPI) 0x40008000)
#define	AT91C_BASE_UDPHS_EPTFIFO   (AT91_CAST(AT91PS_UDPHS_EPTFIFO) 0x20180000)
#define	AT91C_BASE_UDPHS_EPT_0   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4100)
#define	AT91C_BASE_UDPHS_EPT_1   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4120)
#define	AT91C_BASE_UDPHS_EPT_2   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4140)
#define	AT91C_BASE_UDPHS_EPT_3   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4160)
#define	AT91C_BASE_UDPHS_EPT_4   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4180)
#define	AT91C_BASE_UDPHS_EPT_5   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41A0)
#define	AT91C_BASE_UDPHS_EPT_6   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41C0)
#define	AT91C_BASE_UDPHS_DMA_1   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4310)
#define	AT91C_BASE_UDPHS_DMA_2   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4320)
#define	AT91C_BASE_UDPHS_DMA_3   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4330)
#define	AT91C_BASE_UDPHS_DMA_4   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4340)
#define	AT91C_BASE_UDPHS_DMA_5   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4350)
#define	AT91C_BASE_UDPHS_DMA_6   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4360)
#define	AT91C_BASE_UDPHS   (AT91_CAST(AT91PS_UDPHS) 0x400A4000)
#define	AT91C_BASE_HDMA_CH_0   (AT91_CAST(AT91PS_HDMA_CH) 0x400B003C)
#define	AT91C_BASE_HDMA_CH_1   (AT91_CAST(AT91PS_HDMA_CH) 0x400B0064)
#define	AT91C_BASE_HDMA_CH_2   (AT91_CAST(AT91PS_HDMA_CH) 0x400B008C)
#define	AT91C_BASE_HDMA_CH_3   (AT91_CAST(AT91PS_HDMA_CH) 0x400B00B4)
#define	AT91C_BASE_HDMA   (AT91_CAST(AT91PS_HDMA) 0x400B0000)
#define	AT91C_ITCM   (0x00100000)
#define	AT91C_ITCM_SIZE   (0x00010000)
#define	AT91C_DTCM   (0x00200000)
#define	AT91C_DTCM_SIZE   (0x00010000)
#define	AT91C_IRAM   (0x20000000)
#define	AT91C_IRAM_SIZE   (0x00008000)
#define	AT91C_IRAM_MIN   (0x00300000)
#define	AT91C_IRAM_MIN_SIZE   (0x00004000)
#define	AT91C_IROM   (0x00180000)
#define	AT91C_IROM_SIZE   (0x00008000)
#define	AT91C_IFLASH0   (0x00080000)
#define	AT91C_IFLASH0_SIZE   (0x00020000)
#define	AT91C_IFLASH0_PAGE_SIZE   (256)
#define	AT91C_IFLASH0_LOCK_REGION_SIZE   (8192)
#define	AT91C_IFLASH0_NB_OF_PAGES   (512)
#define	AT91C_IFLASH0_NB_OF_LOCK_BITS   (16)
#define	AT91C_IFLASH1   (0x00100000)
#define	AT91C_IFLASH1_SIZE   (0x00020000)
#define	AT91C_IFLASH1_PAGE_SIZE   (256)
#define	AT91C_IFLASH1_LOCK_REGION_SIZE   (8192)
#define	AT91C_IFLASH1_NB_OF_PAGES   (512)
#define	AT91C_IFLASH1_NB_OF_LOCK_BITS   (16)
#define	AT91C_EBI_CS0   (0x10000000)
#define	AT91C_EBI_CS0_SIZE   (0x10000000)
#define	AT91C_EBI_CS1   (0x20000000)
#define	AT91C_EBI_CS1_SIZE   (0x10000000)
#define	AT91C_EBI_SDRAM   (0x20000000)
#define	AT91C_EBI_SDRAM_SIZE   (0x10000000)
#define	AT91C_EBI_SDRAM_16BIT   (0x20000000)
#define	AT91C_EBI_SDRAM_16BIT_SIZE   (0x02000000)
#define	AT91C_EBI_SDRAM_32BIT   (0x20000000)
#define	AT91C_EBI_SDRAM_32BIT_SIZE   (0x04000000)
#define	AT91C_EBI_CS2   (0x30000000)
#define	AT91C_EBI_CS2_SIZE   (0x10000000)
#define	AT91C_EBI_CS3   (0x40000000)
#define	AT91C_EBI_CS3_SIZE   (0x10000000)
#define	AT91C_EBI_SM   (0x40000000)
#define	AT91C_EBI_SM_SIZE   (0x10000000)
#define	AT91C_EBI_CS4   (0x50000000)
#define	AT91C_EBI_CS4_SIZE   (0x10000000)
#define	AT91C_EBI_CF0   (0x50000000)
#define	AT91C_EBI_CF0_SIZE   (0x10000000)
#define	AT91C_EBI_CS5   (0x60000000)
#define	AT91C_EBI_CS5_SIZE   (0x10000000)
#define	AT91C_EBI_CF1   (0x60000000)
#define	AT91C_EBI_CF1_SIZE   (0x10000000)
Typedefs
typedef volatile unsigned int	AT91_REG
typedef struct _AT91S_UDPHS_EPTFIFO	AT91S_UDPHS_EPTFIFO
typedef struct _AT91S_UDPHS_EPTFIFO *	AT91PS_UDPHS_EPTFIFO
typedef struct _AT91S_UDPHS_EPT	AT91S_UDPHS_EPT
typedef struct _AT91S_UDPHS_EPT *	AT91PS_UDPHS_EPT
typedef struct _AT91S_UDPHS_DMA	AT91S_UDPHS_DMA
typedef struct _AT91S_UDPHS_DMA *	AT91PS_UDPHS_DMA
typedef struct _AT91S_UDPHS	AT91S_UDPHS
typedef struct _AT91S_UDPHS *	AT91PS_UDPHS
typedef enum IRQn	IRQn_Type
	Interrupt source.
Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   IROn_SUPC = AT91C_ID_SUPC, IROn_RSTC = AT91C_ID_RSTC, IROn_RTC = AT91C_ID_RTC, IROn_RTT = AT91C_ID_RTT,   IROn_WDG = AT91C_ID_WDG, IROn_PMC = AT91C_ID_PMC, IROn_EFC0 = AT91C_ID_EFC0, IROn_EFC1 = AT91C_ID_EFC1,   IROn_DBGU = AT91C_ID_DBGU, IROn_HSMC4 = AT91C_ID_HSMC4, IROn_PIOA = AT91C_ID_PIOA, IROn_PIOB = AT91C_ID_PIOB,   IROn_PIOC = AT91C_ID_PIOC, IROn_US0 = AT91C_ID_US0, IROn_US1 = AT91C_ID_US1, IROn_US2 = AT91C_ID_US2,   IROn_US3 = AT91C_ID_US3, IROn_MCI0 = AT91C_ID_MCI0, IROn_TWI0 = AT91C_ID_TWI0, IROn_TWI1 = AT91C_ID_TWI1,   IROn_SPI0 = AT91C_ID_SPI0, IROn_SSC0 = AT91C_ID_SSC0, IROn_TC0 = AT91C_ID_TC0, IROn_TC1 = AT91C_ID_TC1,   IROn_TC2 = AT91C_ID_TC2, IROn_PWMC = AT91C_ID_PWMC, IROn_ADCC0 = AT91C_ID_ADCC0, IROn_ADCC1 = AT91C_ID_ADCC1,   IROn_HDMA = AT91C_ID_HDMA, IROn_UDPHS = AT91C_ID_UDPHS, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,   MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,   DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WDT_IRQn = 0,   TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3, TIMER3_IRQn = 4,   UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7, UART3_IRQn = 8,   PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11, I2C2_IRQn = 12,   SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15, PLL0_IRQn = 16,   RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19, EINT2_IRQn = 20,   EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23, USB_IRQn = 24,   CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27, ENET_IRQn = 28,   RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31, PLL1_IRQn = 32,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2,   TIMER2_IRQn = 3, TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6,   UART2_IRQn = 7, UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10,   I2C1_IRQn = 11, I2C2_IRQn = 12, Reserved0_IRQn = 13, SSP0_IRQn = 14,   SSP1_IRQn = 15, PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18,   EINT1_IRQn = 19, EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22,   BOD_IRQn = 23, USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26,   I2S_IRQn = 27, ENET_IRQn = 28, MCI_IRQn = 29, MCPWM_IRQn = 30,   QEI_IRQn = 31, PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34,   UART4_IRQn = 35, SSP2_IRQn = 36, LCD_IRQn = 37, GPIO_IRQn = 38,   PWM0_IRQn = 39, EEPROM_IRQn = 40, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,   MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,   DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0,   PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4,   RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8,   EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12,   DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16,   DMA1_Channel7_IRQn = 17, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2,   RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6,   EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10,   DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14,   DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18,   CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22,   EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26,   TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30,   I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34,   SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38,   USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42,   TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46,   DMA1_Stream7_IRQn = 47, FSMC_IRQn = 48, SDIO_IRQn = 49, TIM5_IRQn = 50,   SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54,   TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58,   DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62,   CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66,   OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70,   USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74,   OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78,   CRYP_IRQn = 79, HASH_RNG_IRQn = 80, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12,   BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,   PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1,   TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5,   EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9,   EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13,   DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17,   ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21,   CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25,   TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29,   TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33,   I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37,   USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41,   OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45,   TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FSMC_IRQn = 48, SDIO_IRQn = 49,   TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53,   TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57,   DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61,   ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65,   CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69,   DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73,   OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77,   DCMI_IRQn = 78, CRYP_IRQn = 79, HASH_RNG_IRQn = 80, FPU_IRQn = 81,   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVC_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3,   FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,   EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,   DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,   DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_IRQn = 18, USB_HP_IRQn = 19,   USB_LP_IRQn = 20, DAC_IRQn = 21, COMP_IRQn = 22, EXTI9_5_IRQn = 23,   LCD_IRQn = 24, TIM9_IRQn = 25, TIM10_IRQn = 26, TIM11_IRQn = 27,   TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31,   I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35,   SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39,   EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, USB_FS_WKUP_IRQn = 42, TIM6_IRQn = 43,   TIM7_IRQn = 44, SDIO_IRQn = 45, TIM5_IRQn = 46, SPI3_IRQn = 47,   UART4_IRQn = 48, UART5_IRQn = 49, DMA2_Channel1_IRQn = 50, DMA2_Channel2_IRQn = 51,   DMA2_Channel3_IRQn = 52, DMA2_Channel4_IRQn = 53, DMA2_Channel5_IRQn = 54, AES_IRQn = 55,   COMP_ACQ_IRQn = 56 }
	Interrupt source. More...

---

Define Documentation

#define AT91_CAST

(

a

)

(a)

#define AT91C_GPBR_GPRV   (0x0 << 0)

#define AT91C_HSMC4_NWE_SETUP   (0x3F << 0)

#define AT91C_HSMC4_NCS_WR_SETUP   (0x3F << 8)

#define AT91C_HSMC4_NRD_SETUP   (0x3F << 16)

#define AT91C_HSMC4_NCS_RD_SETUP   (0x3F << 24)

#define AT91C_HSMC4_NWE_PULSE   (0x3F << 0)

#define AT91C_HSMC4_NCS_WR_PULSE   (0x3F << 8)

#define AT91C_HSMC4_NRD_PULSE   (0x3F << 16)

#define AT91C_HSMC4_NCS_RD_PULSE   (0x3F << 24)

#define AT91C_HSMC4_NWE_CYCLE   (0x1FF << 0)

#define AT91C_HSMC4_NRD_CYCLE   (0x1FF << 16)

#define AT91C_HSMC4_TCLR   (0xF << 0)

#define AT91C_HSMC4_TADL   (0xF << 4)

#define AT91C_HSMC4_TAR   (0xF << 8)

#define AT91C_HSMC4_OCMSEN   (0x1 << 12)

#define AT91C_HSMC4_TRR   (0xF << 16)

#define AT91C_HSMC4_TWB   (0xF << 24)

#define AT91C_HSMC4_RBNSEL   (0x7 << 28)

#define AT91C_HSMC4_NFSEL   (0x1 << 31)

#define AT91C_HSMC4_READ_MODE   (0x1 << 0)

#define AT91C_HSMC4_WRITE_MODE   (0x1 << 1)

#define AT91C_HSMC4_EXNW_MODE   (0x3 << 4)

#define AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE   (0x0 << 4)

#define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN   (0x2 << 4)

#define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY   (0x3 << 4)

#define AT91C_HSMC4_BAT   (0x1 << 8)

#define AT91C_HSMC4_BAT_BYTE_SELECT   (0x0 << 8)

#define AT91C_HSMC4_BAT_BYTE_WRITE   (0x1 << 8)

#define AT91C_HSMC4_DBW   (0x3 << 12)

#define AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS   (0x0 << 12)

#define AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS   (0x1 << 12)

#define AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS   (0x2 << 12)

#define AT91C_HSMC4_TDF_CYCLES   (0xF << 16)

#define AT91C_HSMC4_TDF_MODE   (0x1 << 20)

#define AT91C_HSMC4_PMEN   (0x1 << 24)

#define AT91C_HSMC4_PS   (0x3 << 28)

#define AT91C_HSMC4_PS_SIZE_FOUR_BYTES   (0x0 << 28)

#define AT91C_HSMC4_PS_SIZE_EIGHT_BYTES   (0x1 << 28)

#define AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES   (0x2 << 28)

#define AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES   (0x3 << 28)

#define AT91C_HSMC4_PAGESIZE   (0x3 << 0)

#define AT91C_HSMC4_PAGESIZE_528_Bytes   (0x0)

#define AT91C_HSMC4_PAGESIZE_1056_Bytes   (0x1)

#define AT91C_HSMC4_PAGESIZE_2112_Bytes   (0x2)

#define AT91C_HSMC4_PAGESIZE_4224_Bytes   (0x3)

#define AT91C_HSMC4_WSPARE   (0x1 << 8)

#define AT91C_HSMC4_RSPARE   (0x1 << 9)

#define AT91C_HSMC4_EDGECTRL   (0x1 << 12)

#define AT91C_HSMC4_RBEDGE   (0x1 << 13)

#define AT91C_HSMC4_DTOCYC   (0xF << 16)

#define AT91C_HSMC4_DTOMUL   (0x7 << 20)

#define AT91C_HSMC4_DTOMUL_1   (0x0 << 20)

#define AT91C_HSMC4_DTOMUL_16   (0x1 << 20)

#define AT91C_HSMC4_DTOMUL_128   (0x2 << 20)

#define AT91C_HSMC4_DTOMUL_256   (0x3 << 20)

#define AT91C_HSMC4_DTOMUL_1024   (0x4 << 20)

#define AT91C_HSMC4_DTOMUL_4096   (0x5 << 20)

#define AT91C_HSMC4_DTOMUL_65536   (0x6 << 20)

#define AT91C_HSMC4_DTOMUL_1048576   (0x7 << 20)

#define AT91C_HSMC4_NFCEN   (0x1 << 0)

#define AT91C_HSMC4_NFCDIS   (0x1 << 1)

#define AT91C_HSMC4_HOSTEN   (0x1 << 8)

#define AT91C_HSMC4_HOSTWR   (0x1 << 11)

#define AT91C_HSMC4_HOSTCSID   (0x7 << 12)

#define AT91C_HSMC4_HOSTCSID_0   (0x0 << 12)

#define AT91C_HSMC4_HOSTCSID_1   (0x1 << 12)

#define AT91C_HSMC4_HOSTCSID_2   (0x2 << 12)

#define AT91C_HSMC4_HOSTCSID_3   (0x3 << 12)

#define AT91C_HSMC4_HOSTCSID_4   (0x4 << 12)

#define AT91C_HSMC4_HOSTCSID_5   (0x5 << 12)

#define AT91C_HSMC4_HOSTCSID_6   (0x6 << 12)

#define AT91C_HSMC4_HOSTCSID_7   (0x7 << 12)

#define AT91C_HSMC4_VALID   (0x1 << 15)

#define AT91C_HSMC4_NFCSTS   (0x1 << 0)

#define AT91C_HSMC4_RBRISE   (0x1 << 4)

#define AT91C_HSMC4_RBFALL   (0x1 << 5)

#define AT91C_HSMC4_HOSTBUSY   (0x1 << 8)

#define AT91C_HSMC4_HOSTW   (0x1 << 11)

#define AT91C_HSMC4_HOSTCS   (0x7 << 12)

#define AT91C_HSMC4_HOSTCS_0   (0x0 << 12)

#define AT91C_HSMC4_HOSTCS_1   (0x1 << 12)

#define AT91C_HSMC4_HOSTCS_2   (0x2 << 12)

#define AT91C_HSMC4_HOSTCS_3   (0x3 << 12)

#define AT91C_HSMC4_HOSTCS_4   (0x4 << 12)

#define AT91C_HSMC4_HOSTCS_5   (0x5 << 12)

#define AT91C_HSMC4_HOSTCS_6   (0x6 << 12)

#define AT91C_HSMC4_HOSTCS_7   (0x7 << 12)

#define AT91C_HSMC4_XFRDONE   (0x1 << 16)

#define AT91C_HSMC4_CMDDONE   (0x1 << 17)

#define AT91C_HSMC4_ECCRDY   (0x1 << 18)

#define AT91C_HSMC4_DTOE   (0x1 << 20)

#define AT91C_HSMC4_UNDEF   (0x1 << 21)

#define AT91C_HSMC4_AWB   (0x1 << 22)

#define AT91C_HSMC4_HASE   (0x1 << 23)

#define AT91C_HSMC4_RBEDGE0   (0x1 << 24)

#define AT91C_HSMC4_RBEDGE1   (0x1 << 25)

#define AT91C_HSMC4_RBEDGE2   (0x1 << 26)

#define AT91C_HSMC4_RBEDGE3   (0x1 << 27)

#define AT91C_HSMC4_RBEDGE4   (0x1 << 28)

#define AT91C_HSMC4_RBEDGE5   (0x1 << 29)

#define AT91C_HSMC4_RBEDGE6   (0x1 << 30)

#define AT91C_HSMC4_RBEDGE7   (0x1 << 31)

#define AT91C_HSMC4_ADDRCYCLE0   (0xFF << 0)

#define AT91C_BANK   (0x7 << 0)

#define AT91C_BANK_0   (0x0)

#define AT91C_BANK_1   (0x1)

#define AT91C_BANK_2   (0x2)

#define AT91C_BANK_3   (0x3)

#define AT91C_BANK_4   (0x4)

#define AT91C_BANK_5   (0x5)

#define AT91C_BANK_6   (0x6)

#define AT91C_BANK_7   (0x7)

#define AT91C_HSMC4_ECCRESET   (0x1 << 0)

#define AT91C_ECC_PAGE_SIZE   (0x3 << 0)

#define AT91C_ECC_TYPCORRECT   (0x3 << 4)

#define AT91C_ECC_TYPCORRECT_ONE_PER_PAGE   (0x0 << 4)

#define AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES   (0x1 << 4)

#define AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES   (0x2 << 4)

#define AT91C_HSMC4_ECC_RECERR0   (0x1 << 0)

#define AT91C_HSMC4_ECC_ECCERR0   (0x1 << 1)

#define AT91C_HSMC4_ECC_MULERR0   (0x1 << 2)

#define AT91C_HSMC4_ECC_RECERR1   (0x1 << 4)

#define AT91C_HSMC4_ECC_ECCERR1   (0x1 << 5)

#define AT91C_HSMC4_ECC_MULERR1   (0x1 << 6)

#define AT91C_HSMC4_ECC_RECERR2   (0x1 << 8)

#define AT91C_HSMC4_ECC_ECCERR2   (0x1 << 9)

#define AT91C_HSMC4_ECC_MULERR2   (0x1 << 10)

#define AT91C_HSMC4_ECC_RECERR3   (0x1 << 12)

#define AT91C_HSMC4_ECC_ECCERR3   (0x1 << 13)

#define AT91C_HSMC4_ECC_MULERR3   (0x1 << 14)

#define AT91C_HSMC4_ECC_RECERR4   (0x1 << 16)

#define AT91C_HSMC4_ECC_ECCERR4   (0x1 << 17)

#define AT91C_HSMC4_ECC_MULERR4   (0x1 << 18)

#define AT91C_HSMC4_ECC_RECERR5   (0x1 << 20)

#define AT91C_HSMC4_ECC_ECCERR5   (0x1 << 21)

#define AT91C_HSMC4_ECC_MULERR5   (0x1 << 22)

#define AT91C_HSMC4_ECC_RECERR6   (0x1 << 24)

#define AT91C_HSMC4_ECC_ECCERR6   (0x1 << 25)

#define AT91C_HSMC4_ECC_MULERR6   (0x1 << 26)

#define AT91C_HSMC4_ECC_RECERR7   (0x1 << 28)

#define AT91C_HSMC4_ECC_ECCERR7   (0x1 << 29)

#define AT91C_HSMC4_ECC_MULERR7   (0x1 << 30)

#define AT91C_HSMC4_ECC_BITADDR   (0x7 << 0)

#define AT91C_HSMC4_ECC_WORDADDR   (0xFF << 3)

#define AT91C_HSMC4_ECC_NPARITY   (0x7FF << 12)

#define AT91C_HSMC4_ECC_RECERR8   (0x1 << 0)

#define AT91C_HSMC4_ECC_ECCERR8   (0x1 << 1)

#define AT91C_HSMC4_ECC_MULERR8   (0x1 << 2)

#define AT91C_HSMC4_ECC_RECERR9   (0x1 << 4)

#define AT91C_HSMC4_ECC_ECCERR9   (0x1 << 5)

#define AT91C_HSMC4_ECC_MULERR9   (0x1 << 6)

#define AT91C_HSMC4_ECC_RECERR10   (0x1 << 8)

#define AT91C_HSMC4_ECC_ECCERR10   (0x1 << 9)

#define AT91C_HSMC4_ECC_MULERR10   (0x1 << 10)

#define AT91C_HSMC4_ECC_RECERR11   (0x1 << 12)

#define AT91C_HSMC4_ECC_ECCERR11   (0x1 << 13)

#define AT91C_HSMC4_ECC_MULERR11   (0x1 << 14)

#define AT91C_HSMC4_ECC_RECERR12   (0x1 << 16)

#define AT91C_HSMC4_ECC_ECCERR12   (0x1 << 17)

#define AT91C_HSMC4_ECC_MULERR12   (0x1 << 18)

#define AT91C_HSMC4_ECC_RECERR13   (0x1 << 20)

#define AT91C_HSMC4_ECC_ECCERR13   (0x1 << 21)

#define AT91C_HSMC4_ECC_MULERR13   (0x1 << 22)

#define AT91C_HSMC4_ECC_RECERR14   (0x1 << 24)

#define AT91C_HSMC4_ECC_ECCERR14   (0x1 << 25)

#define AT91C_HSMC4_ECC_MULERR14   (0x1 << 26)

#define AT91C_HSMC4_ECC_RECERR15   (0x1 << 28)

#define AT91C_HSMC4_ECC_ECCERR15   (0x1 << 29)

#define AT91C_HSMC4_ECC_MULERR15   (0x1 << 30)

#define AT91C_HSMC4_OCMS_SRSE   (0x1 << 0)

#define AT91C_HSMC4_OCMS_SMSE   (0x1 << 1)

#define AT91C_HSMC4_OCMS_KEY1   (0x0 << 0)

#define AT91C_HSMC4_OCMS_KEY2   (0x0 << 0)

#define AT91C_HSMC4_WP_EN   (0x1 << 0)

#define AT91C_HSMC4_WP_KEY   (0xFFFFFF << 8)

#define AT91C_HSMC4_WP_VS   (0xF << 0)

#define AT91C_HSMC4_WP_VS_WP_VS0   (0x0)

#define AT91C_HSMC4_WP_VS_WP_VS1   (0x1)

#define AT91C_HSMC4_WP_VS_WP_VS2   (0x2)

#define AT91C_HSMC4_WP_VS_WP_VS3   (0x3)

#define AT91C_   (0x0 << 8)

#define AT91C_HSMC4_CMD1   (0xFF << 2)

#define AT91C_HSMC4_CMD2   (0xFF << 10)

#define AT91C_HSMC4_VCMD2   (0x1 << 18)

#define AT91C_HSMC4_ACYCLE   (0x7 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE   (0x0 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE   (0x1 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO   (0x2 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE   (0x3 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR   (0x4 << 19)

#define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE   (0x5 << 19)

#define AT91C_HSMC4_CSID   (0x7 << 22)

#define AT91C_HSMC4_CSID_0   (0x0 << 22)

#define AT91C_HSMC4_CSID_1   (0x1 << 22)

#define AT91C_HSMC4_CSID_2   (0x2 << 22)

#define AT91C_HSMC4_CSID_3   (0x3 << 22)

#define AT91C_HSMC4_CSID_4   (0x4 << 22)

#define AT91C_HSMC4_CSID_5   (0x5 << 22)

#define AT91C_HSMC4_CSID_6   (0x6 << 22)

#define AT91C_HSMC4_CSID_7   (0x7 << 22)

#define AT91C_HSMC4_HOST_EN   (0x1 << 25)

#define AT91C_HSMC4_HOST_WR   (0x1 << 26)

#define AT91C_HSMC4_HOSTCMD   (0x1 << 27)

#define AT91C_MATRIX_ULBT   (0x7 << 0)

#define AT91C_MATRIX_ULBT_INFINIT_LENGTH   (0x0)

#define AT91C_MATRIX_ULBT_SINGLE_ACCESS   (0x1)

#define AT91C_MATRIX_ULBT_4_BEAT   (0x2)

#define AT91C_MATRIX_ULBT_8_BEAT   (0x3)

#define AT91C_MATRIX_ULBT_16_BEAT   (0x4)

#define AT91C_MATRIX_ULBT_32_BEAT   (0x5)

#define AT91C_MATRIX_ULBT_64_BEAT   (0x6)

#define AT91C_MATRIX_ULBT_128_BEAT   (0x7)

#define AT91C_MATRIX_SLOT_CYCLE   (0x1FF << 0)

#define AT91C_MATRIX_DEFMSTR_TYPE   (0x3 << 16)

#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR   (0x0 << 16)

#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR   (0x1 << 16)

#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR   (0x2 << 16)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC   (0x0 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMC   (0x0 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA   (0x4 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9   (0x7 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_ARMS   (0x1 << 18)

#define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_HDMA   (0x4 << 18)

#define AT91C_HMATRIX2_VER   (0xF << 0)

#define AT91C_NVIC_INTLINESNUM   (0xF << 0)

#define AT91C_NVIC_INTLINESNUM_32   (0x0)

#define AT91C_NVIC_INTLINESNUM_64   (0x1)

#define AT91C_NVIC_INTLINESNUM_96   (0x2)

#define AT91C_NVIC_INTLINESNUM_128   (0x3)

#define AT91C_NVIC_INTLINESNUM_160   (0x4)

#define AT91C_NVIC_INTLINESNUM_192   (0x5)

#define AT91C_NVIC_INTLINESNUM_224   (0x6)

#define AT91C_NVIC_INTLINESNUM_256   (0x7)

#define AT91C_NVIC_INTLINESNUM_288   (0x8)

#define AT91C_NVIC_INTLINESNUM_320   (0x9)

#define AT91C_NVIC_INTLINESNUM_352   (0xA)

#define AT91C_NVIC_INTLINESNUM_384   (0xB)

#define AT91C_NVIC_INTLINESNUM_416   (0xC)

#define AT91C_NVIC_INTLINESNUM_448   (0xD)

#define AT91C_NVIC_INTLINESNUM_480   (0xE)

#define AT91C_NVIC_INTLINESNUM_496   (0xF)

#define AT91C_NVIC_STICKENABLE   (0x1 << 0)

#define AT91C_NVIC_STICKINT   (0x1 << 1)

#define AT91C_NVIC_STICKCLKSOURCE   (0x1 << 2)

#define AT91C_NVIC_STICKCOUNTFLAG   (0x1 << 16)

#define AT91C_NVIC_STICKRELOAD   (0xFFFFFF << 0)

#define AT91C_NVIC_STICKCURRENT   (0x7FFFFFFF << 0)

#define AT91C_NVIC_STICKTENMS   (0xFFFFFF << 0)

#define AT91C_NVIC_STICKSKEW   (0x1 << 30)

#define AT91C_NVIC_STICKNOREF   (0x1 << 31)

#define AT91C_NVIC_PRI_N   (0xFF << 0)

#define AT91C_NVIC_PRI_N1   (0xFF << 8)

#define AT91C_NVIC_PRI_N2   (0xFF << 16)

#define AT91C_NVIC_PRI_N3   (0xFF << 24)

#define AT91C_NVIC_REVISION   (0xF << 0)

#define AT91C_NVIC_PARTNO   (0xFFF << 4)

#define AT91C_NVIC_CONSTANT   (0xF << 16)

#define AT91C_NVIC_VARIANT   (0xF << 20)

#define AT91C_NVIC_IMPLEMENTER   (0xFF << 24)

#define AT91C_NVIC_VECTACTIVE   (0x1FF << 0)

#define AT91C_NVIC_RETTOBASE   (0x1 << 11)

#define AT91C_NVIC_VECTPENDING   (0x1FF << 12)

#define AT91C_NVIC_ISRPENDING   (0x1 << 22)

#define AT91C_NVIC_ISRPREEMPT   (0x1 << 23)

#define AT91C_NVIC_PENDSTCLR   (0x1 << 25)

#define AT91C_NVIC_PENDSTSET   (0x1 << 26)

#define AT91C_NVIC_PENDSVCLR   (0x1 << 27)

#define AT91C_NVIC_PENDSVSET   (0x1 << 28)

#define AT91C_NVIC_NMIPENDSET   (0x1 << 31)

#define AT91C_NVIC_TBLOFF   (0x3FFFFF << 7)

#define AT91C_NVIC_TBLBASE   (0x1 << 29)

#define AT91C_NVIC_TBLBASE_CODE   (0x0 << 29)

#define AT91C_NVIC_TBLBASE_RAM   (0x1 << 29)

#define AT91C_NVIC_VECTRESET   (0x1 << 0)

#define AT91C_NVIC_VECTCLRACTIVE   (0x1 << 1)

#define AT91C_NVIC_SYSRESETREQ   (0x1 << 2)

#define AT91C_NVIC_PRIGROUP   (0x7 << 8)

#define AT91C_NVIC_PRIGROUP_0   (0x0 << 8)

#define AT91C_NVIC_PRIGROUP_1   (0x1 << 8)

#define AT91C_NVIC_PRIGROUP_2   (0x2 << 8)

#define AT91C_NVIC_PRIGROUP_3   (0x3 << 8)

#define AT91C_NVIC_PRIGROUP_4   (0x4 << 8)

#define AT91C_NVIC_PRIGROUP_5   (0x5 << 8)

#define AT91C_NVIC_PRIGROUP_6   (0x6 << 8)

#define AT91C_NVIC_PRIGROUP_7   (0x7 << 8)

#define AT91C_NVIC_ENDIANESS   (0x1 << 15)

#define AT91C_NVIC_VECTKEY   (0xFFFF << 16)

#define AT91C_NVIC_SLEEPONEXIT   (0x1 << 1)

#define AT91C_NVIC_SLEEPDEEP   (0x1 << 2)

#define AT91C_NVIC_SEVONPEND   (0x1 << 4)

#define AT91C_NVIC_NONEBASETHRDENA   (0x1 << 0)

#define AT91C_NVIC_USERSETMPEND   (0x1 << 1)

#define AT91C_NVIC_UNALIGN_TRP   (0x1 << 3)

#define AT91C_NVIC_DIV_0_TRP   (0x1 << 4)

#define AT91C_NVIC_BFHFNMIGN   (0x1 << 8)

#define AT91C_NVIC_STKALIGN   (0x1 << 9)

#define AT91C_NVIC_PRI_4   (0xFF << 0)

#define AT91C_NVIC_PRI_5   (0xFF << 8)

#define AT91C_NVIC_PRI_6   (0xFF << 16)

#define AT91C_NVIC_PRI_7   (0xFF << 24)

#define AT91C_NVIC_PRI_8   (0xFF << 0)

#define AT91C_NVIC_PRI_9   (0xFF << 8)

#define AT91C_NVIC_PRI_10   (0xFF << 16)

#define AT91C_NVIC_PRI_11   (0xFF << 24)

#define AT91C_NVIC_PRI_12   (0xFF << 0)

#define AT91C_NVIC_PRI_13   (0xFF << 8)

#define AT91C_NVIC_PRI_14   (0xFF << 16)

#define AT91C_NVIC_PRI_15   (0xFF << 24)

#define AT91C_NVIC_MEMFAULTACT   (0x1 << 0)

#define AT91C_NVIC_BUSFAULTACT   (0x1 << 1)

#define AT91C_NVIC_USGFAULTACT   (0x1 << 3)

#define AT91C_NVIC_SVCALLACT   (0x1 << 7)

#define AT91C_NVIC_MONITORACT   (0x1 << 8)

#define AT91C_NVIC_PENDSVACT   (0x1 << 10)

#define AT91C_NVIC_SYSTICKACT   (0x1 << 11)

#define AT91C_NVIC_USGFAULTPENDED   (0x1 << 12)

#define AT91C_NVIC_MEMFAULTPENDED   (0x1 << 13)

#define AT91C_NVIC_BUSFAULTPENDED   (0x1 << 14)

#define AT91C_NVIC_SVCALLPENDED   (0x1 << 15)

#define AT91C_NVIC_MEMFAULTENA   (0x1 << 16)

#define AT91C_NVIC_BUSFAULTENA   (0x1 << 17)

#define AT91C_NVIC_USGFAULTENA   (0x1 << 18)

#define AT91C_NVIC_MEMMANAGE   (0xFF << 0)

#define AT91C_NVIC_BUSFAULT   (0xFF << 8)

#define AT91C_NVIC_USAGEFAULT   (0xFF << 16)

#define AT91C_NVIC_IBUSERR   (0x1 << 0)

#define AT91C_NVIC_PRECISERR   (0x1 << 1)

#define AT91C_NVIC_IMPRECISERR   (0x1 << 2)

#define AT91C_NVIC_UNSTKERR   (0x1 << 3)

#define AT91C_NVIC_STKERR   (0x1 << 4)

#define AT91C_NVIC_BFARVALID   (0x1 << 7)

#define AT91C_NVIC_ID_PFR0_0   (0xF << 0)

#define AT91C_NVIC_ID_PRF0_1   (0xF << 4)

#define AT91C_NVIC_ID_PRF1_MODEL   (0xF << 8)

#define AT91C_NVIC_ID_DFR0_MODEL   (0xF << 20)

#define AT91C_NVIC_ID_MMFR0_PMSA   (0xF << 4)

#define AT91C_NVIC_ID_MMFR0_CACHE   (0xF << 8)

#define AT91C_MPU_SEPARATE   (0x1 << 0)

#define AT91C_MPU_DREGION   (0xFF << 8)

#define AT91C_MPU_IREGION   (0xFF << 16)

#define AT91C_MPU_ENABLE   (0x1 << 0)

#define AT91C_MPU_HFNMIENA   (0x1 << 1)

#define AT91C_MPU_PRIVDEFENA   (0x1 << 2)

#define AT91C_MPU_REGION   (0xFF << 0)

#define AT91C_MPU_REG   (0xF << 0)

#define AT91C_MPU_VALID   (0x1 << 4)

#define AT91C_MPU_ADDR   (0x3FFFFFF << 5)

#define AT91C_MPU_ENA   (0x1 << 0)

#define AT91C_MPU_SIZE   (0xF << 1)

#define AT91C_MPU_SRD   (0xFF << 8)

#define AT91C_MPU_B   (0x1 << 16)

#define AT91C_MPU_C   (0x1 << 17)

#define AT91C_MPU_S   (0x1 << 18)

#define AT91C_MPU_TEX   (0x7 << 19)

#define AT91C_MPU_AP   (0x7 << 24)

#define AT91C_MPU_XN   (0x7 << 28)

#define AT91C_CM3_SYSRESETREQ   (0x1 << 2)

#define AT91C_CM3_SLEEPONEXIT   (0x1 << 1)

#define AT91C_CM3_SLEEPDEEP   (0x1 << 2)

#define AT91C_CM3_SEVONPEND   (0x1 << 4)

#define AT91C_CM3_SYSTICKACT   (0x1 << 11)

#define AT91C_PDC_RXTEN   (0x1 << 0)

#define AT91C_PDC_RXTDIS   (0x1 << 1)

#define AT91C_PDC_TXTEN   (0x1 << 8)

#define AT91C_PDC_TXTDIS   (0x1 << 9)

#define AT91C_DBGU_RSTRX   (0x1 << 2)

#define AT91C_DBGU_RSTTX   (0x1 << 3)

#define AT91C_DBGU_RXEN   (0x1 << 4)

#define AT91C_DBGU_RXDIS   (0x1 << 5)

#define AT91C_DBGU_TXEN   (0x1 << 6)

#define AT91C_DBGU_TXDIS   (0x1 << 7)

#define AT91C_DBGU_RSTSTA   (0x1 << 8)

#define AT91C_DBGU_PAR   (0x7 << 9)

#define AT91C_DBGU_PAR_EVEN   (0x0 << 9)

#define AT91C_DBGU_PAR_ODD   (0x1 << 9)

#define AT91C_DBGU_PAR_SPACE   (0x2 << 9)

#define AT91C_DBGU_PAR_MARK   (0x3 << 9)

#define AT91C_DBGU_PAR_NONE   (0x4 << 9)

#define AT91C_DBGU_CHMODE   (0x3 << 14)

#define AT91C_DBGU_CHMODE_NORMAL   (0x0 << 14)

#define AT91C_DBGU_CHMODE_AUTO   (0x1 << 14)

#define AT91C_DBGU_CHMODE_LOCAL   (0x2 << 14)

#define AT91C_DBGU_CHMODE_REMOTE   (0x3 << 14)

#define AT91C_DBGU_RXRDY   (0x1 << 0)

#define AT91C_DBGU_TXRDY   (0x1 << 1)

#define AT91C_DBGU_ENDRX   (0x1 << 3)

#define AT91C_DBGU_ENDTX   (0x1 << 4)

#define AT91C_DBGU_OVRE   (0x1 << 5)

#define AT91C_DBGU_FRAME   (0x1 << 6)

#define AT91C_DBGU_PARE   (0x1 << 7)

#define AT91C_DBGU_TXEMPTY   (0x1 << 9)

#define AT91C_DBGU_TXBUFE   (0x1 << 11)

#define AT91C_DBGU_RXBUFF   (0x1 << 12)

#define AT91C_DBGU_COMM_TX   (0x1 << 30)

#define AT91C_DBGU_COMM_RX   (0x1 << 31)

#define AT91C_DBGU_FORCE_NTRST   (0x1 << 0)

#define AT91C_PIO_KCE   (0x1 << 0)

#define AT91C_PIO_NBR   (0x7 << 0)

#define AT91C_PIO_NBC   (0x7 << 8)

#define AT91C_PIO_DBC   (0x3FF << 0)

#define AT91C_PIO_KPR   (0x1 << 0)

#define AT91C_PIO_KRL   (0x1 << 1)

#define AT91C_PIO_NBKPR   (0x3 << 8)

#define AT91C_PIO_NBKRL   (0x3 << 16)

#define AT91C_KEY0ROW   (0x7 << 0)

#define AT91C_KEY0COL   (0x7 << 4)

#define AT91C_KEY1ROW   (0x7 << 8)

#define AT91C_KEY1COL   (0x7 << 12)

#define AT91C_KEY2ROW   (0x7 << 16)

#define AT91C_KEY2COL   (0x7 << 20)

#define AT91C_KEY3ROW   (0x7 << 24)

#define AT91C_KEY3COL   (0x7 << 28)

#define AT91C_PMC_PCK   (0x1 << 0)

#define AT91C_PMC_PCK0   (0x1 << 8)

#define AT91C_PMC_PCK1   (0x1 << 9)

#define AT91C_PMC_PCK2   (0x1 << 10)

#define AT91C_CKGR_UPLLEN   (0x1 << 16)

#define AT91C_CKGR_UPLLEN_DISABLED   (0x0 << 16)

#define AT91C_CKGR_UPLLEN_ENABLED   (0x1 << 16)

#define AT91C_CKGR_UPLLCOUNT   (0xF << 20)

#define AT91C_CKGR_BIASEN   (0x1 << 24)

#define AT91C_CKGR_BIASEN_DISABLED   (0x0 << 24)

#define AT91C_CKGR_BIASEN_ENABLED   (0x1 << 24)

#define AT91C_CKGR_BIASCOUNT   (0xF << 28)

#define AT91C_CKGR_MOSCXTEN   (0x1 << 0)

#define AT91C_CKGR_MOSCXTBY   (0x1 << 1)

#define AT91C_CKGR_WAITMODE   (0x1 << 2)

#define AT91C_CKGR_MOSCRCEN   (0x1 << 3)

#define AT91C_CKGR_MOSCRCF   (0x7 << 4)

#define AT91C_CKGR_MOSCXTST   (0xFF << 8)

#define AT91C_CKGR_KEY   (0xFF << 16)

#define AT91C_CKGR_MOSCSEL   (0x1 << 24)

#define AT91C_CKGR_CFDEN   (0x1 << 25)

#define AT91C_CKGR_MAINF   (0xFFFF << 0)

#define AT91C_CKGR_MAINRDY   (0x1 << 16)

#define AT91C_CKGR_DIVA   (0xFF << 0)

#define AT91C_CKGR_DIVA_0   (0x0)

#define AT91C_CKGR_DIVA_BYPASS   (0x1)

#define AT91C_CKGR_PLLACOUNT   (0x3F << 8)

#define AT91C_CKGR_STMODE   (0x3 << 14)

#define AT91C_CKGR_STMODE_0   (0x0 << 14)

#define AT91C_CKGR_STMODE_1   (0x1 << 14)

#define AT91C_CKGR_STMODE_2   (0x2 << 14)

#define AT91C_CKGR_STMODE_3   (0x3 << 14)

#define AT91C_CKGR_MULA   (0x7FF << 16)

#define AT91C_CKGR_SRC   (0x1 << 29)

#define AT91C_PMC_CSS   (0x7 << 0)

#define AT91C_PMC_CSS_SLOW_CLK   (0x0)

#define AT91C_PMC_CSS_MAIN_CLK   (0x1)

#define AT91C_PMC_CSS_PLLA_CLK   (0x2)

#define AT91C_PMC_CSS_UPLL_CLK   (0x3)

#define AT91C_PMC_CSS_SYS_CLK   (0x4)

#define AT91C_PMC_PRES   (0x7 << 4)

#define AT91C_PMC_PRES_CLK   (0x0 << 4)

#define AT91C_PMC_PRES_CLK_2   (0x1 << 4)

#define AT91C_PMC_PRES_CLK_4   (0x2 << 4)

#define AT91C_PMC_PRES_CLK_8   (0x3 << 4)

#define AT91C_PMC_PRES_CLK_16   (0x4 << 4)

#define AT91C_PMC_PRES_CLK_32   (0x5 << 4)

#define AT91C_PMC_PRES_CLK_64   (0x6 << 4)

#define AT91C_PMC_PRES_CLK_6   (0x7 << 4)

#define AT91C_PMC_MOSCXTS   (0x1 << 0)

#define AT91C_PMC_LOCKA   (0x1 << 1)

#define AT91C_PMC_MCKRDY   (0x1 << 3)

#define AT91C_PMC_LOCKU   (0x1 << 6)

#define AT91C_PMC_PCKRDY0   (0x1 << 8)

#define AT91C_PMC_PCKRDY1   (0x1 << 9)

#define AT91C_PMC_PCKRDY2   (0x1 << 10)

#define AT91C_PMC_MOSCSELS   (0x1 << 16)

#define AT91C_PMC_MOSCRCS   (0x1 << 17)

#define AT91C_PMC_CFDEV   (0x1 << 18)

#define AT91C_PMC_OSCSELS   (0x1 << 7)

#define AT91C_PMC_CFDS   (0x1 << 19)

#define AT91C_PMC_FOS   (0x1 << 20)

#define AT91C_PMC_FSTT   (0xFFFF << 0)

#define AT91C_PMC_RTTAL   (0x1 << 16)

#define AT91C_PMC_RTCAL   (0x1 << 17)

#define AT91C_PMC_USBAL   (0x1 << 18)

#define AT91C_PMC_LPM   (0x1 << 20)

#define AT91C_PMC_FSTP   (0xFFFF << 0)

#define AT91C_PMC_FOCLR   (0x1 << 0)

#define AT91C_RSTC_PROCRST   (0x1 << 0)

#define AT91C_RSTC_ICERST   (0x1 << 1)

#define AT91C_RSTC_PERRST   (0x1 << 2)

#define AT91C_RSTC_EXTRST   (0x1 << 3)

#define AT91C_RSTC_KEY   (0xFF << 24)

#define AT91C_RSTC_URSTS   (0x1 << 0)

#define AT91C_RSTC_RSTTYP   (0x7 << 8)

#define AT91C_RSTC_RSTTYP_GENERAL   (0x0 << 8)

#define AT91C_RSTC_RSTTYP_WAKEUP   (0x1 << 8)

#define AT91C_RSTC_RSTTYP_WATCHDOG   (0x2 << 8)

#define AT91C_RSTC_RSTTYP_SOFTWARE   (0x3 << 8)

#define AT91C_RSTC_RSTTYP_USER   (0x4 << 8)

#define AT91C_RSTC_NRSTL   (0x1 << 16)

#define AT91C_RSTC_SRCMP   (0x1 << 17)

#define AT91C_RSTC_URSTEN   (0x1 << 0)

#define AT91C_RSTC_URSTIEN   (0x1 << 4)

#define AT91C_RSTC_ERSTL   (0xF << 8)

#define AT91C_SUPC_CR_VROFF   (0x1 << 2)

#define AT91C_SUPC_CR_VROFF_NO_EFFECT   (0x0 << 2)

#define AT91C_SUPC_CR_VROFF_STOP_VREG   (0x1 << 2)

#define AT91C_SUPC_CR_XTALSEL   (0x1 << 3)

#define AT91C_SUPC_CR_XTALSEL_NO_EFFECT   (0x0 << 3)

#define AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL   (0x1 << 3)

#define AT91C_SUPC_CR_KEY   (0xff << 24)

#define AT91C_SUPC_SMMR_SMTH   (0xf << 0)

#define AT91C_SUPC_SMMR_SMTH_1_9V   (0x0 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_0V   (0x1 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_1V   (0x2 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_2V   (0x3 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_3V   (0x4 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_4V   (0x5 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_5V   (0x6 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_6V   (0x7 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_7V   (0x8 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_8V   (0x9 << 0)

#define AT91C_SUPC_SMMR_SMTH_2_9V   (0xA << 0)

#define AT91C_SUPC_SMMR_SMTH_3_0V   (0xB << 0)

#define AT91C_SUPC_SMMR_SMTH_3_1V   (0xC << 0)

#define AT91C_SUPC_SMMR_SMTH_3_2V   (0xD << 0)

#define AT91C_SUPC_SMMR_SMTH_3_3V   (0xE << 0)

#define AT91C_SUPC_SMMR_SMTH_3_4V   (0xF << 0)

#define AT91C_SUPC_SMMR_SMSMPL   (0x7 << 8)

#define AT91C_SUPC_SMMR_SMSMPL_SMD   (0x0 << 8)

#define AT91C_SUPC_SMMR_SMSMPL_CSM   (0x1 << 8)

#define AT91C_SUPC_SMMR_SMSMPL_32SLCK   (0x2 << 8)

#define AT91C_SUPC_SMMR_SMSMPL_256SLCK   (0x3 << 8)

#define AT91C_SUPC_SMMR_SMSMPL_2048SLCK   (0x4 << 8)

#define AT91C_SUPC_SMMR_SMRSTEN   (0x1 << 12)

#define AT91C_SUPC_SMMR_SMRSTEN_NOT_ENABLE   (0x0 << 12)

#define AT91C_SUPC_SMMR_SMRSTEN_ENABLE   (0x1 << 12)

#define AT91C_SUPC_SMMR_SMIEN   (0x1 << 13)

#define AT91C_SUPC_SMMR_SMIEN_NOT_ENABLE   (0x0 << 13)

#define AT91C_SUPC_SMMR_SMIEN_ENABLE   (0x1 << 13)

#define AT91C_SUPC_MR_BODRSTEN   (0x1 << 12)

#define AT91C_SUPC_MR_BODRSTEN_NOT_ENABLE   (0x0 << 12)

#define AT91C_SUPC_MR_BODRSTEN_ENABLE   (0x1 << 12)

#define AT91C_SUPC_MR_BODDIS   (0x1 << 13)

#define AT91C_SUPC_MR_BODDIS_ENABLE   (0x0 << 13)

#define AT91C_SUPC_MR_BODDIS_DISABLE   (0x1 << 13)

#define AT91C_SUPC_MR_VDDIORDY   (0x1 << 14)

#define AT91C_SUPC_MR_VDDIORDY_VDDIO_REMOVED   (0x0 << 14)

#define AT91C_SUPC_MR_VDDIORDY_VDDIO_PRESENT   (0x1 << 14)

#define AT91C_SUPC_MR_OSCBYPASS   (0x1 << 20)

#define AT91C_SUPC_MR_OSCBYPASS_NO_EFFECT   (0x0 << 20)

#define AT91C_SUPC_MR_OSCBYPASS_BYPASS   (0x1 << 20)

#define AT91C_SUPC_MR_KEY   (0xff << 24)

#define AT91C_SUPC_WUMR_FWUPEN   (0x1 << 0)

#define AT91C_SUPC_WUMR_FWUPEN_NOT_ENABLE   (0x0 << 0)

#define AT91C_SUPC_WUMR_FWUPEN_ENABLE   (0x1 << 0)

#define AT91C_SUPC_WUMR_SMEN   (0x1 << 1)

#define AT91C_SUPC_WUMR_SMEN_NOT_ENABLE   (0x0 << 1)

#define AT91C_SUPC_WUMR_SMEN_ENABLE   (0x1 << 1)

#define AT91C_SUPC_WUMR_RTTEN   (0x1 << 2)

#define AT91C_SUPC_WUMR_RTTEN_NOT_ENABLE   (0x0 << 2)

#define AT91C_SUPC_WUMR_RTTEN_ENABLE   (0x1 << 2)

#define AT91C_SUPC_WUMR_RTCEN   (0x1 << 3)

#define AT91C_SUPC_WUMR_RTCEN_NOT_ENABLE   (0x0 << 3)

#define AT91C_SUPC_WUMR_RTCEN_ENABLE   (0x1 << 3)

#define AT91C_SUPC_WUMR_FWUPDBC   (0x7 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_1SCLK   (0x0 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_3SCLK   (0x1 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_32SCLK   (0x2 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_512SCLK   (0x3 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_4096SCLK   (0x4 << 8)

#define AT91C_SUPC_WUMR_FWUPDBC_32768SCLK   (0x5 << 8)

#define AT91C_SUPC_WUMR_WKUPDBC   (0x7 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_1SCLK   (0x0 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_3SCLK   (0x1 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_32SCLK   (0x2 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_512SCLK   (0x3 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_4096SCLK   (0x4 << 12)

#define AT91C_SUPC_WUMR_WKUPDBC_32768SCLK   (0x5 << 12)

#define AT91C_SUPC_WUIR_WKUPEN0   (0x1 << 0)

#define AT91C_SUPC_WUIR_WKUPEN0_NOT_ENABLE   (0x0 << 0)

#define AT91C_SUPC_WUIR_WKUPEN0_ENABLE   (0x1 << 0)

#define AT91C_SUPC_WUIR_WKUPEN1   (0x1 << 1)

#define AT91C_SUPC_WUIR_WKUPEN1_NOT_ENABLE   (0x0 << 1)

#define AT91C_SUPC_WUIR_WKUPEN1_ENABLE   (0x1 << 1)

#define AT91C_SUPC_WUIR_WKUPEN2   (0x1 << 2)

#define AT91C_SUPC_WUIR_WKUPEN2_NOT_ENABLE   (0x0 << 2)

#define AT91C_SUPC_WUIR_WKUPEN2_ENABLE   (0x1 << 2)

#define AT91C_SUPC_WUIR_WKUPEN3   (0x1 << 3)

#define AT91C_SUPC_WUIR_WKUPEN3_NOT_ENABLE   (0x0 << 3)

#define AT91C_SUPC_WUIR_WKUPEN3_ENABLE   (0x1 << 3)

#define AT91C_SUPC_WUIR_WKUPEN4   (0x1 << 4)

#define AT91C_SUPC_WUIR_WKUPEN4_NOT_ENABLE   (0x0 << 4)

#define AT91C_SUPC_WUIR_WKUPEN4_ENABLE   (0x1 << 4)

#define AT91C_SUPC_WUIR_WKUPEN5   (0x1 << 5)

#define AT91C_SUPC_WUIR_WKUPEN5_NOT_ENABLE   (0x0 << 5)

#define AT91C_SUPC_WUIR_WKUPEN5_ENABLE   (0x1 << 5)

#define AT91C_SUPC_WUIR_WKUPEN6   (0x1 << 6)

#define AT91C_SUPC_WUIR_WKUPEN6_NOT_ENABLE   (0x0 << 6)

#define AT91C_SUPC_WUIR_WKUPEN6_ENABLE   (0x1 << 6)

#define AT91C_SUPC_WUIR_WKUPEN7   (0x1 << 7)

#define AT91C_SUPC_WUIR_WKUPEN7_NOT_ENABLE   (0x0 << 7)

#define AT91C_SUPC_WUIR_WKUPEN7_ENABLE   (0x1 << 7)

#define AT91C_SUPC_WUIR_WKUPEN8   (0x1 << 8)

#define AT91C_SUPC_WUIR_WKUPEN8_NOT_ENABLE   (0x0 << 8)

#define AT91C_SUPC_WUIR_WKUPEN8_ENABLE   (0x1 << 8)

#define AT91C_SUPC_WUIR_WKUPEN9   (0x1 << 9)

#define AT91C_SUPC_WUIR_WKUPEN9_NOT_ENABLE   (0x0 << 9)

#define AT91C_SUPC_WUIR_WKUPEN9_ENABLE   (0x1 << 9)

#define AT91C_SUPC_WUIR_WKUPEN10   (0x1 << 10)

#define AT91C_SUPC_WUIR_WKUPEN10_NOT_ENABLE   (0x0 << 10)

#define AT91C_SUPC_WUIR_WKUPEN10_ENABLE   (0x1 << 10)

#define AT91C_SUPC_WUIR_WKUPEN11   (0x1 << 11)

#define AT91C_SUPC_WUIR_WKUPEN11_NOT_ENABLE   (0x0 << 11)

#define AT91C_SUPC_WUIR_WKUPEN11_ENABLE   (0x1 << 11)

#define AT91C_SUPC_WUIR_WKUPEN12   (0x1 << 12)

#define AT91C_SUPC_WUIR_WKUPEN12_NOT_ENABLE   (0x0 << 12)

#define AT91C_SUPC_WUIR_WKUPEN12_ENABLE   (0x1 << 12)

#define AT91C_SUPC_WUIR_WKUPEN13   (0x1 << 13)

#define AT91C_SUPC_WUIR_WKUPEN13_NOT_ENABLE   (0x0 << 13)

#define AT91C_SUPC_WUIR_WKUPEN13_ENABLE   (0x1 << 13)

#define AT91C_SUPC_WUIR_WKUPEN14   (0x1 << 14)

#define AT91C_SUPC_WUIR_WKUPEN14_NOT_ENABLE   (0x0 << 14)

#define AT91C_SUPC_WUIR_WKUPEN14_ENABLE   (0x1 << 14)

#define AT91C_SUPC_WUIR_WKUPEN15   (0x1 << 15)

#define AT91C_SUPC_WUIR_WKUPEN15_NOT_ENABLE   (0x0 << 15)

#define AT91C_SUPC_WUIR_WKUPEN15_ENABLE   (0x1 << 15)

#define AT91C_SUPC_WUIR_WKUPT0   (0x1 << 16)

#define AT91C_SUPC_WUIR_WKUPT0_HIGH_TO_LOW   (0x0 << 16)

#define AT91C_SUPC_WUIR_WKUPT0_LOW_TO_HIGH   (0x1 << 16)

#define AT91C_SUPC_WUIR_WKUPT1   (0x1 << 17)

#define AT91C_SUPC_WUIR_WKUPT1_HIGH_TO_LOW   (0x0 << 17)

#define AT91C_SUPC_WUIR_WKUPT1_LOW_TO_HIGH   (0x1 << 17)

#define AT91C_SUPC_WUIR_WKUPT2   (0x1 << 18)

#define AT91C_SUPC_WUIR_WKUPT2_HIGH_TO_LOW   (0x0 << 18)

#define AT91C_SUPC_WUIR_WKUPT2_LOW_TO_HIGH   (0x1 << 18)

#define AT91C_SUPC_WUIR_WKUPT3   (0x1 << 19)

#define AT91C_SUPC_WUIR_WKUPT3_HIGH_TO_LOW   (0x0 << 19)

#define AT91C_SUPC_WUIR_WKUPT3_LOW_TO_HIGH   (0x1 << 19)

#define AT91C_SUPC_WUIR_WKUPT4   (0x1 << 20)

#define AT91C_SUPC_WUIR_WKUPT4_HIGH_TO_LOW   (0x0 << 20)

#define AT91C_SUPC_WUIR_WKUPT4_LOW_TO_HIGH   (0x1 << 20)

#define AT91C_SUPC_WUIR_WKUPT5   (0x1 << 21)

#define AT91C_SUPC_WUIR_WKUPT5_HIGH_TO_LOW   (0x0 << 21)

#define AT91C_SUPC_WUIR_WKUPT5_LOW_TO_HIGH   (0x1 << 21)

#define AT91C_SUPC_WUIR_WKUPT6   (0x1 << 22)

#define AT91C_SUPC_WUIR_WKUPT6_HIGH_TO_LOW   (0x0 << 22)

#define AT91C_SUPC_WUIR_WKUPT6_LOW_TO_HIGH   (0x1 << 22)

#define AT91C_SUPC_WUIR_WKUPT7   (0x1 << 23)

#define AT91C_SUPC_WUIR_WKUPT7_HIGH_TO_LOW   (0x0 << 23)

#define AT91C_SUPC_WUIR_WKUPT7_LOW_TO_HIGH   (0x1 << 23)

#define AT91C_SUPC_WUIR_WKUPT8   (0x1 << 24)

#define AT91C_SUPC_WUIR_WKUPT8_HIGH_TO_LOW   (0x0 << 24)

#define AT91C_SUPC_WUIR_WKUPT8_LOW_TO_HIGH   (0x1 << 24)

#define AT91C_SUPC_WUIR_WKUPT9   (0x1 << 25)

#define AT91C_SUPC_WUIR_WKUPT9_HIGH_TO_LOW   (0x0 << 25)

#define AT91C_SUPC_WUIR_WKUPT9_LOW_TO_HIGH   (0x1 << 25)

#define AT91C_SUPC_WUIR_WKUPT10   (0x1 << 26)

#define AT91C_SUPC_WUIR_WKUPT10_HIGH_TO_LOW   (0x0 << 26)

#define AT91C_SUPC_WUIR_WKUPT10_LOW_TO_HIGH   (0x1 << 26)

#define AT91C_SUPC_WUIR_WKUPT11   (0x1 << 27)

#define AT91C_SUPC_WUIR_WKUPT11_HIGH_TO_LOW   (0x0 << 27)

#define AT91C_SUPC_WUIR_WKUPT11_LOW_TO_HIGH   (0x1 << 27)

#define AT91C_SUPC_WUIR_WKUPT12   (0x1 << 28)

#define AT91C_SUPC_WUIR_WKUPT12_HIGH_TO_LOW   (0x0 << 28)

#define AT91C_SUPC_WUIR_WKUPT12_LOW_TO_HIGH   (0x1 << 28)

#define AT91C_SUPC_WUIR_WKUPT13   (0x1 << 29)

#define AT91C_SUPC_WUIR_WKUPT13_HIGH_TO_LOW   (0x0 << 29)

#define AT91C_SUPC_WUIR_WKUPT13_LOW_TO_HIGH   (0x1 << 29)

#define AT91C_SUPC_WUIR_WKUPT14   (0x1 << 30)

#define AT91C_SUPC_WUIR_WKUPT14_HIGH_TO_LOW   (0x0 << 30)

#define AT91C_SUPC_WUIR_WKUPT14_LOW_TO_HIGH   (0x1 << 30)

#define AT91C_SUPC_WUIR_WKUPT15   (0x1 << 31)

#define AT91C_SUPC_WUIR_WKUPT15_HIGH_TO_LOW   (0x0 << 31)

#define AT91C_SUPC_WUIR_WKUPT15_LOW_TO_HIGH   (0x1 << 31)

#define AT91C_SUPC_SR_FWUPS   (0x1 << 0)

#define AT91C_SUPC_SR_FWUPS_NO   (0x0 << 0)

#define AT91C_SUPC_SR_FWUPS_PRESENT   (0x1 << 0)

#define AT91C_SUPC_SR_WKUPS   (0x1 << 1)

#define AT91C_SUPC_SR_WKUPS_NO   (0x0 << 1)

#define AT91C_SUPC_SR_WKUPS_PRESENT   (0x1 << 1)

#define AT91C_SUPC_SR_SMWS   (0x1 << 2)

#define AT91C_SUPC_SR_SMWS_NO   (0x0 << 2)

#define AT91C_SUPC_SR_SMWS_PRESENT   (0x1 << 2)

#define AT91C_SUPC_SR_BODRSTS   (0x1 << 3)

#define AT91C_SUPC_SR_BODRSTS_NO   (0x0 << 3)

#define AT91C_SUPC_SR_BODRSTS_PRESENT   (0x1 << 3)

#define AT91C_SUPC_SR_SMRSTS   (0x1 << 4)

#define AT91C_SUPC_SR_SMRSTS_NO   (0x0 << 4)

#define AT91C_SUPC_SR_SMRSTS_PRESENT   (0x1 << 4)

#define AT91C_SUPC_SR_SMS   (0x1 << 5)

#define AT91C_SUPC_SR_SMS_NO   (0x0 << 5)

#define AT91C_SUPC_SR_SMS_PRESENT   (0x1 << 5)

#define AT91C_SUPC_SR_SMOS   (0x1 << 6)

#define AT91C_SUPC_SR_SMOS_HIGH   (0x0 << 6)

#define AT91C_SUPC_SR_SMOS_LOW   (0x1 << 6)

#define AT91C_SUPC_SR_OSCSEL   (0x1 << 7)

#define AT91C_SUPC_SR_OSCSEL_RC   (0x0 << 7)

#define AT91C_SUPC_SR_OSCSEL_CRYST   (0x1 << 7)

#define AT91C_SUPC_SR_FWUPIS   (0x1 << 12)

#define AT91C_SUPC_SR_FWUPIS_LOW   (0x0 << 12)

#define AT91C_SUPC_SR_FWUPIS_HIGH   (0x1 << 12)

#define AT91C_SUPC_SR_WKUPIS0   (0x1 << 16)

#define AT91C_SUPC_SR_WKUPIS0_DIS   (0x0 << 16)

#define AT91C_SUPC_SR_WKUPIS0_EN   (0x1 << 16)

#define AT91C_SUPC_SR_WKUPIS1   (0x1 << 17)

#define AT91C_SUPC_SR_WKUPIS1_DIS   (0x0 << 17)

#define AT91C_SUPC_SR_WKUPIS1_EN   (0x1 << 17)

#define AT91C_SUPC_SR_WKUPIS2   (0x1 << 18)

#define AT91C_SUPC_SR_WKUPIS2_DIS   (0x0 << 18)

#define AT91C_SUPC_SR_WKUPIS2_EN   (0x1 << 18)

#define AT91C_SUPC_SR_WKUPIS3   (0x1 << 19)

#define AT91C_SUPC_SR_WKUPIS3_DIS   (0x0 << 19)

#define AT91C_SUPC_SR_WKUPIS3_EN   (0x1 << 19)

#define AT91C_SUPC_SR_WKUPIS4   (0x1 << 20)

#define AT91C_SUPC_SR_WKUPIS4_DIS   (0x0 << 20)

#define AT91C_SUPC_SR_WKUPIS4_EN   (0x1 << 20)

#define AT91C_SUPC_SR_WKUPIS5   (0x1 << 21)

#define AT91C_SUPC_SR_WKUPIS5_DIS   (0x0 << 21)

#define AT91C_SUPC_SR_WKUPIS5_EN   (0x1 << 21)

#define AT91C_SUPC_SR_WKUPIS6   (0x1 << 22)

#define AT91C_SUPC_SR_WKUPIS6_DIS   (0x0 << 22)

#define AT91C_SUPC_SR_WKUPIS6_EN   (0x1 << 22)

#define AT91C_SUPC_SR_WKUPIS7   (0x1 << 23)

#define AT91C_SUPC_SR_WKUPIS7_DIS   (0x0 << 23)

#define AT91C_SUPC_SR_WKUPIS7_EN   (0x1 << 23)

#define AT91C_SUPC_SR_WKUPIS8   (0x1 << 24)

#define AT91C_SUPC_SR_WKUPIS8_DIS   (0x0 << 24)

#define AT91C_SUPC_SR_WKUPIS8_EN   (0x1 << 24)

#define AT91C_SUPC_SR_WKUPIS9   (0x1 << 25)

#define AT91C_SUPC_SR_WKUPIS9_DIS   (0x0 << 25)

#define AT91C_SUPC_SR_WKUPIS9_EN   (0x1 << 25)

#define AT91C_SUPC_SR_WKUPIS10   (0x1 << 26)

#define AT91C_SUPC_SR_WKUPIS10_DIS   (0x0 << 26)

#define AT91C_SUPC_SR_WKUPIS10_EN   (0x1 << 26)

#define AT91C_SUPC_SR_WKUPIS11   (0x1 << 27)

#define AT91C_SUPC_SR_WKUPIS11_DIS   (0x0 << 27)

#define AT91C_SUPC_SR_WKUPIS11_EN   (0x1 << 27)

#define AT91C_SUPC_SR_WKUPIS12   (0x1 << 28)

#define AT91C_SUPC_SR_WKUPIS12_DIS   (0x0 << 28)

#define AT91C_SUPC_SR_WKUPIS12_EN   (0x1 << 28)

#define AT91C_SUPC_SR_WKUPIS13   (0x1 << 29)

#define AT91C_SUPC_SR_WKUPIS13_DIS   (0x0 << 29)

#define AT91C_SUPC_SR_WKUPIS13_EN   (0x1 << 29)

#define AT91C_SUPC_SR_WKUPIS14   (0x1 << 30)

#define AT91C_SUPC_SR_WKUPIS14_DIS   (0x0 << 30)

#define AT91C_SUPC_SR_WKUPIS14_EN   (0x1 << 30)

#define AT91C_SUPC_SR_WKUPIS15   (0x1 << 31)

#define AT91C_SUPC_SR_WKUPIS15_DIS   (0x0 << 31)

#define AT91C_SUPC_SR_WKUPIS15_EN   (0x1 << 31)

#define AT91C_RTTC_RTPRES   (0xFFFF << 0)

#define AT91C_RTTC_ALMIEN   (0x1 << 16)

#define AT91C_RTTC_RTTINCIEN   (0x1 << 17)

#define AT91C_RTTC_RTTRST   (0x1 << 18)

#define AT91C_RTTC_ALMV   (0x0 << 0)

#define AT91C_RTTC_CRTV   (0x0 << 0)

#define AT91C_RTTC_ALMS   (0x1 << 0)

#define AT91C_RTTC_RTTINC   (0x1 << 1)

#define AT91C_WDTC_WDRSTT   (0x1 << 0)

#define AT91C_WDTC_KEY   (0xFF << 24)

#define AT91C_WDTC_WDV   (0xFFF << 0)

#define AT91C_WDTC_WDFIEN   (0x1 << 12)

#define AT91C_WDTC_WDRSTEN   (0x1 << 13)

#define AT91C_WDTC_WDRPROC   (0x1 << 14)

#define AT91C_WDTC_WDDIS   (0x1 << 15)

#define AT91C_WDTC_WDD   (0xFFF << 16)

#define AT91C_WDTC_WDDBGHLT   (0x1 << 28)

#define AT91C_WDTC_WDIDLEHLT   (0x1 << 29)

#define AT91C_WDTC_WDUNF   (0x1 << 0)

#define AT91C_WDTC_WDERR   (0x1 << 1)

#define AT91C_RTC_UPDTIM   (0x1 << 0)

#define AT91C_RTC_UPDCAL   (0x1 << 1)

#define AT91C_RTC_TIMEVSEL   (0x3 << 8)

#define AT91C_RTC_TIMEVSEL_MINUTE   (0x0 << 8)

#define AT91C_RTC_TIMEVSEL_HOUR   (0x1 << 8)

#define AT91C_RTC_TIMEVSEL_DAY24   (0x2 << 8)

#define AT91C_RTC_TIMEVSEL_DAY12   (0x3 << 8)

#define AT91C_RTC_CALEVSEL   (0x3 << 16)

#define AT91C_RTC_CALEVSEL_WEEK   (0x0 << 16)

#define AT91C_RTC_CALEVSEL_MONTH   (0x1 << 16)

#define AT91C_RTC_CALEVSEL_YEAR   (0x2 << 16)

#define AT91C_RTC_HRMOD   (0x1 << 0)

#define AT91C_RTC_SEC   (0x7F << 0)

#define AT91C_RTC_MIN   (0x7F << 8)

#define AT91C_RTC_HOUR   (0x3F << 16)

#define AT91C_RTC_AMPM   (0x1 << 22)

#define AT91C_RTC_CENT   (0x3F << 0)

#define AT91C_RTC_YEAR   (0xFF << 8)

#define AT91C_RTC_MONTH   (0x1F << 16)

#define AT91C_RTC_DAY   (0x7 << 21)

#define AT91C_RTC_DATE   (0x3F << 24)

#define AT91C_RTC_SECEN   (0x1 << 7)

#define AT91C_RTC_MINEN   (0x1 << 15)

#define AT91C_RTC_HOUREN   (0x1 << 23)

#define AT91C_RTC_MONTHEN   (0x1 << 23)

#define AT91C_RTC_DATEEN   (0x1 << 31)

#define AT91C_RTC_ACKUPD   (0x1 << 0)

#define AT91C_RTC_ALARM   (0x1 << 1)

#define AT91C_RTC_SECEV   (0x1 << 2)

#define AT91C_RTC_TIMEV   (0x1 << 3)

#define AT91C_RTC_CALEV   (0x1 << 4)

#define AT91C_RTC_NVTIM   (0x1 << 0)

#define AT91C_RTC_NVCAL   (0x1 << 1)

#define AT91C_RTC_NVTIMALR   (0x1 << 2)

#define AT91C_RTC_NVCALALR   (0x1 << 3)

#define AT91C_ADC_SWRST   (0x1 << 0)

#define AT91C_ADC_START   (0x1 << 1)

#define AT91C_ADC_TRGEN   (0x1 << 0)

#define AT91C_ADC_TRGEN_DIS   (0x0)

#define AT91C_ADC_TRGEN_EN   (0x1)

#define AT91C_ADC_TRGSEL   (0x7 << 1)

#define AT91C_ADC_TRGSEL_EXT   (0x0 << 1)

#define AT91C_ADC_TRGSEL_TIOA0   (0x1 << 1)

#define AT91C_ADC_TRGSEL_TIOA1   (0x2 << 1)

#define AT91C_ADC_TRGSEL_TIOA2   (0x3 << 1)

#define AT91C_ADC_TRGSEL_PWM0_TRIG   (0x4 << 1)

#define AT91C_ADC_TRGSEL_PWM1_TRIG   (0x5 << 1)

#define AT91C_ADC_TRGSEL_RESERVED   (0x6 << 1)

#define AT91C_ADC_LOWRES   (0x1 << 4)

#define AT91C_ADC_LOWRES_12_BIT   (0x0 << 4)

#define AT91C_ADC_LOWRES_10_BIT   (0x1 << 4)

#define AT91C_ADC_SLEEP   (0x1 << 5)

#define AT91C_ADC_SLEEP_NORMAL_MODE   (0x0 << 5)

#define AT91C_ADC_SLEEP_MODE   (0x1 << 5)

#define AT91C_ADC_PRESCAL   (0x3F << 8)

#define AT91C_ADC_STARTUP   (0x1F << 16)

#define AT91C_ADC_SHTIM   (0xF << 24)

#define AT91C_ADC_CH0   (0x1 << 0)

#define AT91C_ADC_CH1   (0x1 << 1)

#define AT91C_ADC_CH2   (0x1 << 2)

#define AT91C_ADC_CH3   (0x1 << 3)

#define AT91C_ADC_CH4   (0x1 << 4)

#define AT91C_ADC_CH5   (0x1 << 5)

#define AT91C_ADC_CH6   (0x1 << 6)

#define AT91C_ADC_CH7   (0x1 << 7)

#define AT91C_ADC_EOC0   (0x1 << 0)

#define AT91C_ADC_EOC1   (0x1 << 1)

#define AT91C_ADC_EOC2   (0x1 << 2)

#define AT91C_ADC_EOC3   (0x1 << 3)

#define AT91C_ADC_EOC4   (0x1 << 4)

#define AT91C_ADC_EOC5   (0x1 << 5)

#define AT91C_ADC_EOC6   (0x1 << 6)

#define AT91C_ADC_EOC7   (0x1 << 7)

#define AT91C_ADC_OVRE0   (0x1 << 8)

#define AT91C_ADC_OVRE1   (0x1 << 9)

#define AT91C_ADC_OVRE2   (0x1 << 10)

#define AT91C_ADC_OVRE3   (0x1 << 11)

#define AT91C_ADC_OVRE4   (0x1 << 12)

#define AT91C_ADC_OVRE5   (0x1 << 13)

#define AT91C_ADC_OVRE6   (0x1 << 14)

#define AT91C_ADC_OVRE7   (0x1 << 15)

#define AT91C_ADC_DRDY   (0x1 << 16)

#define AT91C_ADC_GOVRE   (0x1 << 17)

#define AT91C_ADC_ENDRX   (0x1 << 18)

#define AT91C_ADC_RXBUFF   (0x1 << 19)

#define AT91C_ADC_LDATA   (0x3FF << 0)

#define AT91C_ADC_DATA   (0x3FF << 0)

#define AT91C_ADC_GAIN   (0x3 << 0)

#define AT91C_ADC_IBCTL   (0x3 << 6)

#define AT91C_ADC_IBCTL_00   (0x0 << 6)

#define AT91C_ADC_IBCTL_01   (0x1 << 6)

#define AT91C_ADC_IBCTL_10   (0x2 << 6)

#define AT91C_ADC_IBCTL_11   (0x3 << 6)

#define AT91C_ADC_DIFF   (0x1 << 16)

#define AT91C_ADC_OFFSET   (0x1 << 17)

#define AT91C_OFFMODES   (0x1 << 0)

#define AT91C_OFF_MODE_STARTUP_TIME   (0x1 << 16)

#define AT91C_ADC_VER   (0xF << 0)

#define AT91C_ADC12B_CR_SWRST   (0x1 << 0)

#define AT91C_ADC12B_CR_SWRST_NO_EFFECT   (0x0 << 0)

#define AT91C_ADC12B_CR_SWRST_RESET   (0x1 << 0)

#define AT91C_ADC12B_CR_START   (0x1 << 1)

#define AT91C_ADC12B_CR_START_NO_EFFECT   (0x0 << 1)

#define AT91C_ADC12B_CR_START_BEGIN_ADC   (0x1 << 1)

#define AT91C_ADC12B_MR_TRGEN   (0x1 << 0)

#define AT91C_ADC12B_MR_TRGEN_DIS   (0x0 << 0)

#define AT91C_ADC12B_MR_TRGEN_EN   (0x1 << 0)

#define AT91C_ADC12B_MR_TRGSEL   (0x7 << 1)

#define AT91C_ADC12B_MR_TRGSEL_EXT_TRIG   (0x0 << 1)

#define AT91C_ADC12B_MR_TRGSEL_TIOA_0   (0x1 << 1)

#define AT91C_ADC12B_MR_TRGSEL_TIOA_1   (0x2 << 1)

#define AT91C_ADC12B_MR_TRGSEL_TIOA_2   (0x3 << 1)

#define AT91C_ADC12B_MR_TRGSEL_TIOA_3   (0x4 << 1)

#define AT91C_ADC12B_MR_TRGSEL_TIOA_4   (0x5 << 1)

#define AT91C_ADC12B_MR_LOWRES   (0x1 << 4)

#define AT91C_ADC12B_MR_LOWRES_12_BIT   (0x0 << 4)

#define AT91C_ADC12B_MR_LOWRES_10_BIT   (0x1 << 4)

#define AT91C_ADC12B_MR_SLEEP   (0x1 << 5)

#define AT91C_ADC12B_MR_SLEEP_NORMAL   (0x0 << 5)

#define AT91C_ADC12B_MR_SLEEP_SLEEP   (0x1 << 5)

#define AT91C_ADC12B_MR_PRESCAL   (0xff << 8)

#define AT91C_ADC12B_MR_STARTUP   (0xff << 16)

#define AT91C_ADC12B_MR_SHTIM   (0xf << 24)

#define AT91C_ADC12B_CHER_CH0   (0x1 << 0)

#define AT91C_ADC12B_CHER_CH0_NO_EFFECT   (0x0 << 0)

#define AT91C_ADC12B_CHER_CH0_ENABLE   (0x1 << 0)

#define AT91C_ADC12B_CHER_CH1   (0x1 << 1)

#define AT91C_ADC12B_CHER_CH1_NO_EFFECT   (0x0 << 1)

#define AT91C_ADC12B_CHER_CH1_ENABLE   (0x1 << 1)

#define AT91C_ADC12B_CHER_CH2   (0x1 << 2)

#define AT91C_ADC12B_CHER_CH2_NO_EFFECT   (0x0 << 2)

#define AT91C_ADC12B_CHER_CH2_ENABLE   (0x1 << 2)

#define AT91C_ADC12B_CHER_CH3   (0x1 << 3)

#define AT91C_ADC12B_CHER_CH3_NO_EFFECT   (0x0 << 3)

#define AT91C_ADC12B_CHER_CH3_ENABLE   (0x1 << 3)

#define AT91C_ADC12B_CHER_CH4   (0x1 << 4)

#define AT91C_ADC12B_CHER_CH4_NO_EFFECT   (0x0 << 4)

#define AT91C_ADC12B_CHER_CH4_ENABLE   (0x1 << 4)

#define AT91C_ADC12B_CHER_CH5   (0x1 << 5)

#define AT91C_ADC12B_CHER_CH5_NO_EFFECT   (0x0 << 5)

#define AT91C_ADC12B_CHER_CH5_ENABLE   (0x1 << 5)

#define AT91C_ADC12B_CHER_CH6   (0x1 << 6)

#define AT91C_ADC12B_CHER_CH6_NO_EFFECT   (0x0 << 6)

#define AT91C_ADC12B_CHER_CH6_ENABLE   (0x1 << 6)

#define AT91C_ADC12B_CHER_CH7   (0x1 << 7)

#define AT91C_ADC12B_CHER_CH7_NO_EFFECT   (0x0 << 7)

#define AT91C_ADC12B_CHER_CH7_ENABLE   (0x1 << 7)

#define AT91C_ADC12B_CHDR_CH0   (0x1 << 0)

#define AT91C_ADC12B_CHDR_CH0_NO_EFFECT   (0x0 << 0)

#define AT91C_ADC12B_CHDR_CH0_DISABLE   (0x1 << 0)

#define AT91C_ADC12B_CHDR_CH1   (0x1 << 1)

#define AT91C_ADC12B_CHDR_CH1_NO_EFFECT   (0x0 << 1)

#define AT91C_ADC12B_CHDR_CH1_DISABLE   (0x1 << 1)

#define AT91C_ADC12B_CHDR_CH2   (0x1 << 2)

#define AT91C_ADC12B_CHDR_CH2_NO_EFFECT   (0x0 << 2)

#define AT91C_ADC12B_CHDR_CH2_DISABLE   (0x1 << 2)

#define AT91C_ADC12B_CHDR_CH3   (0x1 << 3)

#define AT91C_ADC12B_CHDR_CH3_NO_EFFECT   (0x0 << 3)

#define AT91C_ADC12B_CHDR_CH3_DISABLE   (0x1 << 3)

#define AT91C_ADC12B_CHDR_CH4   (0x1 << 4)

#define AT91C_ADC12B_CHDR_CH4_NO_EFFECT   (0x0 << 4)

#define AT91C_ADC12B_CHDR_CH4_DISABLE   (0x1 << 4)

#define AT91C_ADC12B_CHDR_CH5   (0x1 << 5)

#define AT91C_ADC12B_CHDR_CH5_NO_EFFECT   (0x0 << 5)

#define AT91C_ADC12B_CHDR_CH5_DISABLE   (0x1 << 5)

#define AT91C_ADC12B_CHDR_CH6   (0x1 << 6)

#define AT91C_ADC12B_CHDR_CH6_NO_EFFECT   (0x0 << 6)

#define AT91C_ADC12B_CHDR_CH6_DISABLE   (0x1 << 6)

#define AT91C_ADC12B_CHDR_CH7   (0x1 << 7)

#define AT91C_ADC12B_CHDR_CH7_NO_EFFECT   (0x0 << 7)

#define AT91C_ADC12B_CHDR_CH7_DISABLE   (0x1 << 7)

#define AT91C_ADC12B_CHSR_CH0   (0x1 << 0)

#define AT91C_ADC12B_CHSR_CH0_DISABLED   (0x0 << 0)

#define AT91C_ADC12B_CHSR_CH0_ENABLED   (0x1 << 0)

#define AT91C_ADC12B_CHSR_CH1   (0x1 << 1)

#define AT91C_ADC12B_CHSR_CH1_DISABLED   (0x0 << 1)

#define AT91C_ADC12B_CHSR_CH1_ENABLED   (0x1 << 1)

#define AT91C_ADC12B_CHSR_CH2   (0x1 << 2)

#define AT91C_ADC12B_CHSR_CH2_DISABLED   (0x0 << 2)

#define AT91C_ADC12B_CHSR_CH2_ENABLED   (0x1 << 2)

#define AT91C_ADC12B_CHSR_CH3   (0x1 << 3)

#define AT91C_ADC12B_CHSR_CH3_DISABLED   (0x0 << 3)

#define AT91C_ADC12B_CHSR_CH3_ENABLED   (0x1 << 3)

#define AT91C_ADC12B_CHSR_CH4   (0x1 << 4)

#define AT91C_ADC12B_CHSR_CH4_DISABLED   (0x0 << 4)

#define AT91C_ADC12B_CHSR_CH4_ENABLED   (0x1 << 4)

#define AT91C_ADC12B_CHSR_CH5   (0x1 << 5)

#define AT91C_ADC12B_CHSR_CH5_DISABLED   (0x0 << 5)

#define AT91C_ADC12B_CHSR_CH5_ENABLED   (0x1 << 5)

#define AT91C_ADC12B_CHSR_CH6   (0x1 << 6)

#define AT91C_ADC12B_CHSR_CH6_DISABLED   (0x0 << 6)

#define AT91C_ADC12B_CHSR_CH6_ENABLED   (0x1 << 6)

#define AT91C_ADC12B_CHSR_CH7   (0x1 << 7)

#define AT91C_ADC12B_CHSR_CH7_DISABLED   (0x0 << 7)

#define AT91C_ADC12B_CHSR_CH7_ENABLED   (0x1 << 7)

#define AT91C_ADC12B_SR_EOC0   (0x1 << 0)

#define AT91C_ADC12B_SR_EOC0_DISABLE   (0x0 << 0)

#define AT91C_ADC12B_SR_EOC0_ENABLE   (0x1 << 0)

#define AT91C_ADC12B_SR_EOC1   (0x1 << 1)

#define AT91C_ADC12B_SR_EOC1_DISABLE   (0x0 << 1)

#define AT91C_ADC12B_SR_EOC1_ENABLE   (0x1 << 1)

#define AT91C_ADC12B_SR_EOC2   (0x1 << 2)

#define AT91C_ADC12B_SR_EOC2_DISABLE   (0x0 << 2)

#define AT91C_ADC12B_SR_EOC2_ENABLE   (0x1 << 2)

#define AT91C_ADC12B_SR_EOC3   (0x1 << 3)

#define AT91C_ADC12B_SR_EOC3_DISABLE   (0x0 << 3)

#define AT91C_ADC12B_SR_EOC3_ENABLE   (0x1 << 3)

#define AT91C_ADC12B_SR_EOC4   (0x1 << 4)

#define AT91C_ADC12B_SR_EOC4_DISABLE   (0x0 << 4)

#define AT91C_ADC12B_SR_EOC4_ENABLE   (0x1 << 4)

#define AT91C_ADC12B_SR_EOC5   (0x1 << 5)

#define AT91C_ADC12B_SR_EOC5_DISABLE   (0x0 << 5)

#define AT91C_ADC12B_SR_EOC5_ENABLE   (0x1 << 5)

#define AT91C_ADC12B_SR_EOC6   (0x1 << 6)

#define AT91C_ADC12B_SR_EOC6_DISABLE   (0x0 << 6)

#define AT91C_ADC12B_SR_EOC6_ENABLE   (0x1 << 6)

#define AT91C_ADC12B_SR_EOC7   (0x1 << 7)

#define AT91C_ADC12B_SR_EOC7_DISABLE   (0x0 << 7)

#define AT91C_ADC12B_SR_EOC7_ENABLE   (0x1 << 7)

#define AT91C_ADC12B_SR_OVRE0   (0x1 << 8)

#define AT91C_ADC12B_SR_OVRE0_NO_ERROR   (0x0 << 8)

#define AT91C_ADC12B_SR_OVRE0_ERROR   (0x1 << 8)

#define AT91C_ADC12B_SR_OVRE1   (0x1 << 9)

#define AT91C_ADC12B_SR_OVRE1_NO_ERROR   (0x0 << 9)

#define AT91C_ADC12B_SR_OVRE1_ERROR   (0x1 << 9)

#define AT91C_ADC12B_SR_OVRE2   (0x1 << 10)

#define AT91C_ADC12B_SR_OVRE2_NO_ERROR   (0x0 << 10)

#define AT91C_ADC12B_SR_OVRE2_ERROR   (0x1 << 10)

#define AT91C_ADC12B_SR_OVRE3   (0x1 << 11)

#define AT91C_ADC12B_SR_OVRE3_NO_ERROR   (0x0 << 11)

#define AT91C_ADC12B_SR_OVRE3_ERROR   (0x1 << 11)

#define AT91C_ADC12B_SR_OVRE4   (0x1 << 12)

#define AT91C_ADC12B_SR_OVRE4_NO_ERROR   (0x0 << 12)

#define AT91C_ADC12B_SR_OVRE4_ERROR   (0x1 << 12)

#define AT91C_ADC12B_SR_OVRE5   (0x1 << 13)

#define AT91C_ADC12B_SR_OVRE5_NO_ERROR   (0x0 << 13)

#define AT91C_ADC12B_SR_OVRE5_ERROR   (0x1 << 13)

#define AT91C_ADC12B_SR_OVRE6   (0x1 << 14)

#define AT91C_ADC12B_SR_OVRE6_NO_ERROR   (0x0 << 14)

#define AT91C_ADC12B_SR_OVRE6_ERROR   (0x1 << 14)

#define AT91C_ADC12B_SR_OVRE7   (0x1 << 15)

#define AT91C_ADC12B_SR_OVRE7_NO_ERROR   (0x0 << 15)

#define AT91C_ADC12B_SR_OVRE7_ERROR   (0x1 << 15)

#define AT91C_ADC12B_SR_DRDY   (0x1 << 16)

#define AT91C_ADC12B_SR_DRDY_NO_CONV   (0x0 << 16)

#define AT91C_ADC12B_SR_DRDY_CONV   (0x1 << 16)

#define AT91C_ADC12B_SR_GOVRE   (0x1 << 17)

#define AT91C_ADC12B_SR_GOVRE_NO_ERROR   (0x0 << 17)

#define AT91C_ADC12B_SR_GOVRE_ERROR   (0x1 << 17)

#define AT91C_ADC12B_SR_ENDRX   (0x1 << 18)

#define AT91C_ADC12B_SR_ENDRX_NOT_REACH   (0x0 << 18)

#define AT91C_ADC12B_SR_ENDRX_REACH_0   (0x1 << 18)

#define AT91C_ADC12B_SR_RXBUFF   (0x1 << 19)

#define AT91C_ADC12B_SR_RXBUFF_NO_ZERO   (0x0 << 19)

#define AT91C_ADC12B_SR_RXBUFF_ZERO   (0x1 << 19)

#define AT91C_ADC12B_LCDR_LDATA   (0xfff << 0)

#define AT91C_ADC12B_IER_EOC0   (0x1 << 0)

#define AT91C_ADC12B_IER_EOC0_NO_EFFECT   (0x0 << 0)

#define AT91C_ADC12B_IER_EOC0_ENABLE   (0x1 << 0)

#define AT91C_ADC12B_IER_EOC1   (0x1 << 1)

#define AT91C_ADC12B_IER_EOC1_NO_EFFECT   (0x0 << 1)

#define AT91C_ADC12B_IER_EOC1_ENABLE   (0x1 << 1)

#define AT91C_ADC12B_IER_EOC2   (0x1 << 2)

#define AT91C_ADC12B_IER_EOC2_NO_EFFECT   (0x0 << 2)

#define AT91C_ADC12B_IER_EOC2_ENABLE   (0x1 << 2)

#define AT91C_ADC12B_IER_EOC3   (0x1 << 3)

#define AT91C_ADC12B_IER_EOC3_NO_EFFECT   (0x0 << 3)

#define AT91C_ADC12B_IER_EOC3_ENABLE   (0x1 << 3)

#define AT91C_ADC12B_IER_EOC4   (0x1 << 4)

#define AT91C_ADC12B_IER_EOC4_NO_EFFECT   (0x0 << 4)

#define AT91C_ADC12B_IER_EOC4_ENABLE   (0x1 << 4)

#define AT91C_ADC12B_IER_EOC5   (0x1 << 5)

#define AT91C_ADC12B_IER_EOC5_NO_EFFECT   (0x0 << 5)

#define AT91C_ADC12B_IER_EOC5_ENABLE   (0x1 << 5)

#define AT91C_ADC12B_IER_EOC6   (0x1 << 6)

#define AT91C_ADC12B_IER_EOC6_NO_EFFECT   (0x0 << 6)

#define AT91C_ADC12B_IER_EOC6_ENABLE   (0x1 << 6)

#define AT91C_ADC12B_IER_EOC7   (0x1 << 7)

#define AT91C_ADC12B_IER_EOC7_NO_EFFECT   (0x0 << 7)

#define AT91C_ADC12B_IER_EOC7_ENABLE   (0x1 << 7)

#define AT91C_ADC12B_IER_OVRE0   (0x1 << 8)

#define AT91C_ADC12B_IER_OVRE0_NO_EFFECT   (0x0 << 8)

#define AT91C_ADC12B_IER_OVRE0_ENABLE   (0x1 << 8)

#define AT91C_ADC12B_IER_OVRE1   (0x1 << 9)

#define AT91C_ADC12B_IER_OVRE1_NO_EFFECT   (0x0 << 9)

#define AT91C_ADC12B_IER_OVRE1_ENABLE   (0x1 << 9)

#define AT91C_ADC12B_IER_OVRE2   (0x1 << 10)

#define AT91C_ADC12B_IER_OVRE2_NO_EFFECT   (0x0 << 10)

#define AT91C_ADC12B_IER_OVRE2_ENABLE   (0x1 << 10)

#define AT91C_ADC12B_IER_OVRE3   (0x1 << 11)

#define AT91C_ADC12B_IER_OVRE3_NO_EFFECT   (0x0 << 11)

#define AT91C_ADC12B_IER_OVRE3_ENABLE   (0x1 << 11)

#define AT91C_ADC12B_IER_OVRE4   (0x1 << 12)

#define AT91C_ADC12B_IER_OVRE4_NO_EFFECT   (0x0 << 12)

#define AT91C_ADC12B_IER_OVRE4_ENABLE   (0x1 << 12)

#define AT91C_ADC12B_IER_OVRE5   (0x1 << 13)

#define AT91C_ADC12B_IER_OVRE5_NO_EFFECT   (0x0 << 13)

#define AT91C_ADC12B_IER_OVRE5_ENABLE   (0x1 << 13)

#define AT91C_ADC12B_IER_OVRE6   (0x1 << 14)

#define AT91C_ADC12B_IER_OVRE6_NO_EFFECT   (0x0 << 14)

#define AT91C_ADC12B_IER_OVRE6_ENABLE   (0x1 << 14)

#define AT91C_ADC12B_IER_OVRE7   (0x1 << 15)

#define AT91C_ADC12B_IER_OVRE7_NO_EFFECT   (0x0 << 15)

#define AT91C_ADC12B_IER_OVRE7_ENABLE   (0x1 << 15)

#define AT91C_ADC12B_IER_DRDY   (0x1 << 16)

#define AT91C_ADC12B_IER_DRDY_NO_EFFECT   (0x0 << 16)

#define AT91C_ADC12B_IER_DRDY_ENABLE   (0x1 << 16)

#define AT91C_ADC12B_IER_GOVRE   (0x1 << 17)

#define AT91C_ADC12B_IER_GOVRE_NO_EFFECT   (0x0 << 17)

#define AT91C_ADC12B_IER_GOVRE_ENABLE   (0x1 << 17)

#define AT91C_ADC12B_IER_ENDRX   (0x1 << 18)

#define AT91C_ADC12B_IER_ENDRX_NO_EFFECT   (0x0 << 18)

#define AT91C_ADC12B_IER_ENDRX_ENABLE   (0x1 << 18)

#define AT91C_ADC12B_IER_RXBUFF   (0x1 << 19)

#define AT91C_ADC12B_IER_RXBUFF_NO_EFFECT   (0x0 << 19)

#define AT91C_ADC12B_IER_RXBUFF_ENABLE   (0x1 << 19)

#define AT91C_ADC12B_IDR_EOC0   (0x1 << 0)

#define AT91C_ADC12B_IDR_EOC0_NO_EFFECT   (0x0 << 0)

#define AT91C_ADC12B_IDR_EOC0_DISABLE   (0x1 << 0)

#define AT91C_ADC12B_IDR_EOC1   (0x1 << 1)

#define AT91C_ADC12B_IDR_EOC1_NO_EFFECT   (0x0 << 1)

#define AT91C_ADC12B_IDR_EOC1_DISABLE   (0x1 << 1)

#define AT91C_ADC12B_IDR_EOC2   (0x1 << 2)

#define AT91C_ADC12B_IDR_EOC2_NO_EFFECT   (0x0 << 2)

#define AT91C_ADC12B_IDR_EOC2_DISABLE   (0x1 << 2)

#define AT91C_ADC12B_IDR_EOC3   (0x1 << 3)

#define AT91C_ADC12B_IDR_EOC3_NO_EFFECT   (0x0 << 3)

#define AT91C_ADC12B_IDR_EOC3_DISABLE   (0x1 << 3)

#define AT91C_ADC12B_IDR_EOC4   (0x1 << 4)

#define AT91C_ADC12B_IDR_EOC4_NO_EFFECT   (0x0 << 4)

#define AT91C_ADC12B_IDR_EOC4_DISABLE   (0x1 << 4)

#define AT91C_ADC12B_IDR_EOC5   (0x1 << 5)

#define AT91C_ADC12B_IDR_EOC5_NO_EFFECT   (0x0 << 5)

#define AT91C_ADC12B_IDR_EOC5_DISABLE   (0x1 << 5)

#define AT91C_ADC12B_IDR_EOC6   (0x1 << 6)

#define AT91C_ADC12B_IDR_EOC6_NO_EFFECT   (0x0 << 6)

#define AT91C_ADC12B_IDR_EOC6_DISABLE   (0x1 << 6)

#define AT91C_ADC12B_IDR_EOC7   (0x1 << 7)

#define AT91C_ADC12B_IDR_EOC7_NO_EFFECT   (0x0 << 7)

#define AT91C_ADC12B_IDR_EOC7_DISABLE   (0x1 << 7)

#define AT91C_ADC12B_IDR_OVRE0   (0x1 << 8)

#define AT91C_ADC12B_IDR_OVRE0_NO_EFFECT   (0x0 << 8)

#define AT91C_ADC12B_IDR_OVRE0_DISABLE   (0x1 << 8)

#define AT91C_ADC12B_IDR_OVRE1   (0x1 << 9)

#define AT91C_ADC12B_IDR_OVRE1_NO_EFFECT   (0x0 << 9)

#define AT91C_ADC12B_IDR_OVRE1_DISABLE   (0x1 << 9)

#define AT91C_ADC12B_IDR_OVRE2   (0x1 << 10)

#define AT91C_ADC12B_IDR_OVRE2_NO_EFFECT   (0x0 << 10)

#define AT91C_ADC12B_IDR_OVRE2_DISABLE   (0x1 << 10)

#define AT91C_ADC12B_IDR_OVRE3   (0x1 << 11)

#define AT91C_ADC12B_IDR_OVRE3_NO_EFFECT   (0x0 << 11)

#define AT91C_ADC12B_IDR_OVRE3_DISABLE   (0x1 << 11)

#define AT91C_ADC12B_IDR_OVRE4   (0x1 << 12)

#define AT91C_ADC12B_IDR_OVRE4_NO_EFFECT   (0x0 << 12)

#define AT91C_ADC12B_IDR_OVRE4_DISABLE   (0x1 << 12)

#define AT91C_ADC12B_IDR_OVRE5   (0x1 << 13)

#define AT91C_ADC12B_IDR_OVRE5_NO_EFFECT   (0x0 << 13)

#define AT91C_ADC12B_IDR_OVRE5_DISABLE   (0x1 << 13)

#define AT91C_ADC12B_IDR_OVRE6   (0x1 << 14)

#define AT91C_ADC12B_IDR_OVRE6_NO_EFFECT   (0x0 << 14)

#define AT91C_ADC12B_IDR_OVRE6_DISABLE   (0x1 << 14)

#define AT91C_ADC12B_IDR_OVRE7   (0x1 << 15)

#define AT91C_ADC12B_IDR_OVRE7_NO_EFFECT   (0x0 << 15)

#define AT91C_ADC12B_IDR_OVRE7_DISABLE   (0x1 << 15)

#define AT91C_ADC12B_IDR_DRDY   (0x1 << 16)

#define AT91C_ADC12B_IDR_DRDY_NO_EFFECT   (0x0 << 16)

#define AT91C_ADC12B_IDR_DRDY_DISABLE   (0x1 << 16)

#define AT91C_ADC12B_IDR_GOVRE   (0x1 << 17)

#define AT91C_ADC12B_IDR_GOVRE_NO_EFFECT   (0x0 << 17)

#define AT91C_ADC12B_IDR_GOVRE_DISABLE   (0x1 << 17)

#define AT91C_ADC12B_IDR_ENDRX   (0x1 << 18)

#define AT91C_ADC12B_IDR_ENDRX_NO_EFFECT   (0x0 << 18)

#define AT91C_ADC12B_IDR_ENDRX_DISABLE   (0x1 << 18)

#define AT91C_ADC12B_IDR_RXBUFF   (0x1 << 19)

#define AT91C_ADC12B_IDR_RXBUFF_NO_EFFECT   (0x0 << 19)

#define AT91C_ADC12B_IDR_RXBUFF_DISABLE   (0x1 << 19)

#define AT91C_ADC12B_IMR_EOC0   (0x1 << 0)

#define AT91C_ADC12B_IMR_EOC0_DIS   (0x0 << 0)

#define AT91C_ADC12B_IMR_EOC0_EN   (0x1 << 0)

#define AT91C_ADC12B_IMR_EOC1   (0x1 << 1)

#define AT91C_ADC12B_IMR_EOC1_DIS   (0x0 << 1)

#define AT91C_ADC12B_IMR_EOC1_EN   (0x1 << 1)

#define AT91C_ADC12B_IMR_EOC2   (0x1 << 2)

#define AT91C_ADC12B_IMR_EOC2_DIS   (0x0 << 2)

#define AT91C_ADC12B_IMR_EOC2_EN   (0x1 << 2)

#define AT91C_ADC12B_IMR_EOC3   (0x1 << 3)

#define AT91C_ADC12B_IMR_EOC3_DIS   (0x0 << 3)

#define AT91C_ADC12B_IMR_EOC3_EN   (0x1 << 3)

#define AT91C_ADC12B_IMR_EOC4   (0x1 << 4)

#define AT91C_ADC12B_IMR_EOC4_DIS   (0x0 << 4)

#define AT91C_ADC12B_IMR_EOC4_EN   (0x1 << 4)

#define AT91C_ADC12B_IMR_EOC5   (0x1 << 5)

#define AT91C_ADC12B_IMR_EOC5_DIS   (0x0 << 5)

#define AT91C_ADC12B_IMR_EOC5_EN   (0x1 << 5)

#define AT91C_ADC12B_IMR_EOC6   (0x1 << 6)

#define AT91C_ADC12B_IMR_EOC6_DIS   (0x0 << 6)

#define AT91C_ADC12B_IMR_EOC6_EN   (0x1 << 6)

#define AT91C_ADC12B_IMR_EOC7   (0x1 << 7)

#define AT91C_ADC12B_IMR_EOC7_DIS   (0x0 << 7)

#define AT91C_ADC12B_IMR_EOC7_EN   (0x1 << 7)

#define AT91C_ADC12B_IMR_OVRE0   (0x1 << 8)

#define AT91C_ADC12B_IMR_OVRE0_DIS   (0x0 << 8)

#define AT91C_ADC12B_IMR_OVRE0_EN   (0x1 << 8)

#define AT91C_ADC12B_IMR_OVRE1   (0x1 << 9)

#define AT91C_ADC12B_IMR_OVRE1_DIS   (0x0 << 9)

#define AT91C_ADC12B_IMR_OVRE1_EN   (0x1 << 9)

#define AT91C_ADC12B_IMR_OVRE2   (0x1 << 10)

#define AT91C_ADC12B_IMR_OVRE2_DIS   (0x0 << 10)

#define AT91C_ADC12B_IMR_OVRE2_EN   (0x1 << 10)

#define AT91C_ADC12B_IMR_OVRE3   (0x1 << 11)

#define AT91C_ADC12B_IMR_OVRE3_DIS   (0x0 << 11)

#define AT91C_ADC12B_IMR_OVRE3_EN   (0x1 << 11)

#define AT91C_ADC12B_IMR_OVRE4   (0x1 << 12)

#define AT91C_ADC12B_IMR_OVRE4_DIS   (0x0 << 12)

#define AT91C_ADC12B_IMR_OVRE4_EN   (0x1 << 12)

#define AT91C_ADC12B_IMR_OVRE5   (0x1 << 13)

#define AT91C_ADC12B_IMR_OVRE5_DIS   (0x0 << 13)

#define AT91C_ADC12B_IMR_OVRE5_EN   (0x1 << 13)

#define AT91C_ADC12B_IMR_OVRE6   (0x1 << 14)

#define AT91C_ADC12B_IMR_OVRE6_DIS   (0x0 << 14)

#define AT91C_ADC12B_IMR_OVRE6_EN   (0x1 << 14)

#define AT91C_ADC12B_IMR_OVRE7   (0x1 << 15)

#define AT91C_ADC12B_IMR_OVRE7_DIS   (0x0 << 15)

#define AT91C_ADC12B_IMR_OVRE7_EN   (0x1 << 15)

#define AT91C_ADC12B_IMR_DRDY   (0x1 << 16)

#define AT91C_ADC12B_IMR_DRDY_DIS   (0x0 << 16)

#define AT91C_ADC12B_IMR_DRDY_EN   (0x1 << 16)

#define AT91C_ADC12B_IMR_GOVRE   (0x1 << 17)

#define AT91C_ADC12B_IMR_GOVRE_DIS   (0x0 << 17)

#define AT91C_ADC12B_IMR_GOVRE_EN   (0x1 << 17)

#define AT91C_ADC12B_IMR_ENDRX   (0x1 << 18)

#define AT91C_ADC12B_IMR_ENDRX_DIS   (0x0 << 18)

#define AT91C_ADC12B_IMR_ENDRX_EN   (0x1 << 18)

#define AT91C_ADC12B_IMR_RXBUFF   (0x1 << 19)

#define AT91C_ADC12B_IMR_RXBUFF_DIS   (0x0 << 19)

#define AT91C_ADC12B_IMR_RXBUFF_EN   (0x1 << 19)

#define AT91C_ADC12B_CDR_DATA   (0xfff << 0)

#define AT91C_ADC12B_ACR_GAIN   (0x3 << 0)

#define AT91C_ADC12B_ACR_IBCTL   (0x3 << 6)

#define AT91C_ADC12B_ACR_IBCTL_MIN20   (0x0 << 6)

#define AT91C_ADC12B_ACR_IBCTL_TYP   (0x1 << 6)

#define AT91C_ADC12B_ACR_IBCTL_PLUS20   (0x2 << 6)

#define AT91C_ADC12B_ACR_IBCTL_PLUS40   (0x3 << 6)

#define AT91C_ADC12B_ACR_DIFF   (0x1 << 16)

#define AT91C_ADC12B_ACR_DIFF_SINGLE   (0x0 << 16)

#define AT91C_ADC12B_ACR_DIFF_FULLY   (0x1 << 16)

#define AT91C_ADC12B_ACR_OFFSET   (0x1 << 17)

#define AT91C_ADC12B_EMR_OFFMODES   (0x1 << 0)

#define AT91C_ADC12B_EMR_OFFMODES_STBY   (0x0 << 0)

#define AT91C_ADC12B_EMR_OFFMODES_OFF   (0x1 << 0)

#define AT91C_ADC12B_EMR_OFF_MODE_STARTUP_TIME   (0xff << 16)

#define AT91C_TC_CLKEN   (0x1 << 0)

#define AT91C_TC_CLKDIS   (0x1 << 1)

#define AT91C_TC_SWTRG   (0x1 << 2)

#define AT91C_TC_CLKS   (0x7 << 0)

#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK   (0x0)

#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK   (0x1)

#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK   (0x2)

#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK   (0x3)

#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK   (0x4)

#define AT91C_TC_CLKS_XC0   (0x5)

#define AT91C_TC_CLKS_XC1   (0x6)

#define AT91C_TC_CLKS_XC2   (0x7)

#define AT91C_TC_CLKI   (0x1 << 3)

#define AT91C_TC_BURST   (0x3 << 4)

#define AT91C_TC_BURST_NONE   (0x0 << 4)

#define AT91C_TC_BURST_XC0   (0x1 << 4)

#define AT91C_TC_BURST_XC1   (0x2 << 4)

#define AT91C_TC_BURST_XC2   (0x3 << 4)

#define AT91C_TC_CPCSTOP   (0x1 << 6)

#define AT91C_TC_LDBSTOP   (0x1 << 6)

#define AT91C_TC_CPCDIS   (0x1 << 7)

#define AT91C_TC_LDBDIS   (0x1 << 7)

#define AT91C_TC_ETRGEDG   (0x3 << 8)

#define AT91C_TC_ETRGEDG_NONE   (0x0 << 8)

#define AT91C_TC_ETRGEDG_RISING   (0x1 << 8)

#define AT91C_TC_ETRGEDG_FALLING   (0x2 << 8)

#define AT91C_TC_ETRGEDG_BOTH   (0x3 << 8)

#define AT91C_TC_EEVTEDG   (0x3 << 8)

#define AT91C_TC_EEVTEDG_NONE   (0x0 << 8)

#define AT91C_TC_EEVTEDG_RISING   (0x1 << 8)

#define AT91C_TC_EEVTEDG_FALLING   (0x2 << 8)

#define AT91C_TC_EEVTEDG_BOTH   (0x3 << 8)

#define AT91C_TC_EEVT   (0x3 << 10)

#define AT91C_TC_EEVT_TIOB   (0x0 << 10)

#define AT91C_TC_EEVT_XC0   (0x1 << 10)

#define AT91C_TC_EEVT_XC1   (0x2 << 10)

#define AT91C_TC_EEVT_XC2   (0x3 << 10)

#define AT91C_TC_ABETRG   (0x1 << 10)

#define AT91C_TC_ENETRG   (0x1 << 12)

#define AT91C_TC_WAVESEL   (0x3 << 13)

#define AT91C_TC_WAVESEL_UP   (0x0 << 13)

#define AT91C_TC_WAVESEL_UPDOWN   (0x1 << 13)

#define AT91C_TC_WAVESEL_UP_AUTO   (0x2 << 13)

#define AT91C_TC_WAVESEL_UPDOWN_AUTO   (0x3 << 13)

#define AT91C_TC_CPCTRG   (0x1 << 14)

#define AT91C_TC_WAVE   (0x1 << 15)

#define AT91C_TC_ACPA   (0x3 << 16)

#define AT91C_TC_ACPA_NONE   (0x0 << 16)

#define AT91C_TC_ACPA_SET   (0x1 << 16)

#define AT91C_TC_ACPA_CLEAR   (0x2 << 16)

#define AT91C_TC_ACPA_TOGGLE   (0x3 << 16)

#define AT91C_TC_LDRA   (0x3 << 16)

#define AT91C_TC_LDRA_NONE   (0x0 << 16)

#define AT91C_TC_LDRA_RISING   (0x1 << 16)

#define AT91C_TC_LDRA_FALLING   (0x2 << 16)

#define AT91C_TC_LDRA_BOTH   (0x3 << 16)

#define AT91C_TC_ACPC   (0x3 << 18)

#define AT91C_TC_ACPC_NONE   (0x0 << 18)

#define AT91C_TC_ACPC_SET   (0x1 << 18)

#define AT91C_TC_ACPC_CLEAR   (0x2 << 18)

#define AT91C_TC_ACPC_TOGGLE   (0x3 << 18)

#define AT91C_TC_LDRB   (0x3 << 18)

#define AT91C_TC_LDRB_NONE   (0x0 << 18)

#define AT91C_TC_LDRB_RISING   (0x1 << 18)

#define AT91C_TC_LDRB_FALLING   (0x2 << 18)

#define AT91C_TC_LDRB_BOTH   (0x3 << 18)

#define AT91C_TC_AEEVT   (0x3 << 20)

#define AT91C_TC_AEEVT_NONE   (0x0 << 20)

#define AT91C_TC_AEEVT_SET   (0x1 << 20)

#define AT91C_TC_AEEVT_CLEAR   (0x2 << 20)

#define AT91C_TC_AEEVT_TOGGLE   (0x3 << 20)

#define AT91C_TC_ASWTRG   (0x3 << 22)

#define AT91C_TC_ASWTRG_NONE   (0x0 << 22)

#define AT91C_TC_ASWTRG_SET   (0x1 << 22)

#define AT91C_TC_ASWTRG_CLEAR   (0x2 << 22)

#define AT91C_TC_ASWTRG_TOGGLE   (0x3 << 22)

#define AT91C_TC_BCPB   (0x3 << 24)

#define AT91C_TC_BCPB_NONE   (0x0 << 24)

#define AT91C_TC_BCPB_SET   (0x1 << 24)

#define AT91C_TC_BCPB_CLEAR   (0x2 << 24)

#define AT91C_TC_BCPB_TOGGLE   (0x3 << 24)

#define AT91C_TC_BCPC   (0x3 << 26)

#define AT91C_TC_BCPC_NONE   (0x0 << 26)

#define AT91C_TC_BCPC_SET   (0x1 << 26)

#define AT91C_TC_BCPC_CLEAR   (0x2 << 26)

#define AT91C_TC_BCPC_TOGGLE   (0x3 << 26)

#define AT91C_TC_BEEVT   (0x3 << 28)

#define AT91C_TC_BEEVT_NONE   (0x0 << 28)

#define AT91C_TC_BEEVT_SET   (0x1 << 28)

#define AT91C_TC_BEEVT_CLEAR   (0x2 << 28)

#define AT91C_TC_BEEVT_TOGGLE   (0x3 << 28)

#define AT91C_TC_BSWTRG   (0x3 << 30)

#define AT91C_TC_BSWTRG_NONE   (0x0 << 30)

#define AT91C_TC_BSWTRG_SET   (0x1 << 30)

#define AT91C_TC_BSWTRG_CLEAR   (0x2 << 30)

#define AT91C_TC_BSWTRG_TOGGLE   (0x3 << 30)

#define AT91C_TC_COVFS   (0x1 << 0)

#define AT91C_TC_LOVRS   (0x1 << 1)

#define AT91C_TC_CPAS   (0x1 << 2)

#define AT91C_TC_CPBS   (0x1 << 3)

#define AT91C_TC_CPCS   (0x1 << 4)

#define AT91C_TC_LDRAS   (0x1 << 5)

#define AT91C_TC_LDRBS   (0x1 << 6)

#define AT91C_TC_ETRGS   (0x1 << 7)

#define AT91C_TC_CLKSTA   (0x1 << 16)

#define AT91C_TC_MTIOA   (0x1 << 17)

#define AT91C_TC_MTIOB   (0x1 << 18)

#define AT91C_TCB_SYNC   (0x1 << 0)

#define AT91C_TCB_TC0XC0S   (0x3 << 0)

#define AT91C_TCB_TC0XC0S_TCLK0   (0x0)

#define AT91C_TCB_TC0XC0S_NONE   (0x1)

#define AT91C_TCB_TC0XC0S_TIOA1   (0x2)

#define AT91C_TCB_TC0XC0S_TIOA2   (0x3)

#define AT91C_TCB_TC1XC1S   (0x3 << 2)

#define AT91C_TCB_TC1XC1S_TCLK1   (0x0 << 2)

#define AT91C_TCB_TC1XC1S_NONE   (0x1 << 2)

#define AT91C_TCB_TC1XC1S_TIOA0   (0x2 << 2)

#define AT91C_TCB_TC1XC1S_TIOA2   (0x3 << 2)

#define AT91C_TCB_TC2XC2S   (0x3 << 4)

#define AT91C_TCB_TC2XC2S_TCLK2   (0x0 << 4)

#define AT91C_TCB_TC2XC2S_NONE   (0x1 << 4)

#define AT91C_TCB_TC2XC2S_TIOA0   (0x2 << 4)

#define AT91C_TCB_TC2XC2S_TIOA1   (0x3 << 4)

#define AT91C_EFC_FRDY   (0x1 << 0)

#define AT91C_EFC_FWS   (0xF << 8)

#define AT91C_EFC_FWS_0WS   (0x0 << 8)

#define AT91C_EFC_FWS_1WS   (0x1 << 8)

#define AT91C_EFC_FWS_2WS   (0x2 << 8)

#define AT91C_EFC_FWS_3WS   (0x3 << 8)

#define AT91C_EFC_FCMD   (0xFF << 0)

#define AT91C_EFC_FCMD_GETD   (0x0)

#define AT91C_EFC_FCMD_WP   (0x1)

#define AT91C_EFC_FCMD_WPL   (0x2)

#define AT91C_EFC_FCMD_EWP   (0x3)

#define AT91C_EFC_FCMD_EWPL   (0x4)

#define AT91C_EFC_FCMD_EA   (0x5)

#define AT91C_EFC_FCMD_EPL   (0x6)

#define AT91C_EFC_FCMD_EPA   (0x7)

#define AT91C_EFC_FCMD_SLB   (0x8)

#define AT91C_EFC_FCMD_CLB   (0x9)

#define AT91C_EFC_FCMD_GLB   (0xA)

#define AT91C_EFC_FCMD_SFB   (0xB)

#define AT91C_EFC_FCMD_CFB   (0xC)

#define AT91C_EFC_FCMD_GFB   (0xD)

#define AT91C_EFC_FCMD_STUI   (0xE)

#define AT91C_EFC_FCMD_SPUI   (0xF)

#define AT91C_EFC_FARG   (0xFFFF << 8)

#define AT91C_EFC_FKEY   (0xFF << 24)

#define AT91C_EFC_FRDY_S   (0x1 << 0)

#define AT91C_EFC_FCMDE   (0x1 << 1)

#define AT91C_EFC_LOCKE   (0x1 << 2)

#define AT91C_EFC_FVALUE   (0x0 << 0)

#define AT91C_MCI_MCIEN   (0x1 << 0)

#define AT91C_MCI_MCIEN_0   (0x0)

#define AT91C_MCI_MCIEN_1   (0x1)

#define AT91C_MCI_MCIDIS   (0x1 << 1)

#define AT91C_MCI_MCIDIS_0   (0x0 << 1)

#define AT91C_MCI_MCIDIS_1   (0x1 << 1)

#define AT91C_MCI_PWSEN   (0x1 << 2)

#define AT91C_MCI_PWSEN_0   (0x0 << 2)

#define AT91C_MCI_PWSEN_1   (0x1 << 2)

#define AT91C_MCI_PWSDIS   (0x1 << 3)

#define AT91C_MCI_PWSDIS_0   (0x0 << 3)

#define AT91C_MCI_PWSDIS_1   (0x1 << 3)

#define AT91C_MCI_IOWAITEN   (0x1 << 4)

#define AT91C_MCI_IOWAITEN_0   (0x0 << 4)

#define AT91C_MCI_IOWAITEN_1   (0x1 << 4)

#define AT91C_MCI_IOWAITDIS   (0x1 << 5)

#define AT91C_MCI_IOWAITDIS_0   (0x0 << 5)

#define AT91C_MCI_IOWAITDIS_1   (0x1 << 5)

#define AT91C_MCI_SWRST   (0x1 << 7)

#define AT91C_MCI_SWRST_0   (0x0 << 7)

#define AT91C_MCI_SWRST_1   (0x1 << 7)

#define AT91C_MCI_CLKDIV   (0xFF << 0)

#define AT91C_MCI_PWSDIV   (0x7 << 8)

#define AT91C_MCI_RDPROOF   (0x1 << 11)

#define AT91C_MCI_RDPROOF_DISABLE   (0x0 << 11)

#define AT91C_MCI_RDPROOF_ENABLE   (0x1 << 11)

#define AT91C_MCI_WRPROOF   (0x1 << 12)

#define AT91C_MCI_WRPROOF_DISABLE   (0x0 << 12)

#define AT91C_MCI_WRPROOF_ENABLE   (0x1 << 12)

#define AT91C_MCI_PDCFBYTE   (0x1 << 13)

#define AT91C_MCI_PDCFBYTE_DISABLE   (0x0 << 13)

#define AT91C_MCI_PDCFBYTE_ENABLE   (0x1 << 13)

#define AT91C_MCI_PDCPADV   (0x1 << 14)

#define AT91C_MCI_PDCMODE   (0x1 << 15)

#define AT91C_MCI_PDCMODE_DISABLE   (0x0 << 15)

#define AT91C_MCI_PDCMODE_ENABLE   (0x1 << 15)

#define AT91C_MCI_BLKLEN   (0xFFFF << 16)

#define AT91C_MCI_DTOCYC   (0xF << 0)

#define AT91C_MCI_DTOMUL   (0x7 << 4)

#define AT91C_MCI_DTOMUL_1   (0x0 << 4)

#define AT91C_MCI_DTOMUL_16   (0x1 << 4)

#define AT91C_MCI_DTOMUL_128   (0x2 << 4)

#define AT91C_MCI_DTOMUL_256   (0x3 << 4)

#define AT91C_MCI_DTOMUL_1024   (0x4 << 4)

#define AT91C_MCI_DTOMUL_4096   (0x5 << 4)

#define AT91C_MCI_DTOMUL_65536   (0x6 << 4)

#define AT91C_MCI_DTOMUL_1048576   (0x7 << 4)

#define AT91C_MCI_SCDSEL   (0x3 << 0)

#define AT91C_MCI_SCDSEL_SLOTA   (0x0)

#define AT91C_MCI_SCDSEL_SLOTB   (0x1)

#define AT91C_MCI_SCDSEL_SLOTC   (0x2)

#define AT91C_MCI_SCDSEL_SLOTD   (0x3)

#define AT91C_MCI_SCDBUS   (0x3 << 6)

#define AT91C_MCI_SCDBUS_1BIT   (0x0 << 6)

#define AT91C_MCI_SCDBUS_4BITS   (0x2 << 6)

#define AT91C_MCI_SCDBUS_8BITS   (0x3 << 6)

#define AT91C_MCI_CMDNB   (0x3F << 0)

#define AT91C_MCI_RSPTYP   (0x3 << 6)

#define AT91C_MCI_RSPTYP_NO   (0x0 << 6)

#define AT91C_MCI_RSPTYP_48   (0x1 << 6)

#define AT91C_MCI_RSPTYP_136   (0x2 << 6)

#define AT91C_MCI_RSPTYP_R1B   (0x3 << 6)

#define AT91C_MCI_SPCMD   (0x7 << 8)

#define AT91C_MCI_SPCMD_NONE   (0x0 << 8)

#define AT91C_MCI_SPCMD_INIT   (0x1 << 8)

#define AT91C_MCI_SPCMD_SYNC   (0x2 << 8)

#define AT91C_MCI_SPCMD_CE_ATA   (0x3 << 8)

#define AT91C_MCI_SPCMD_IT_CMD   (0x4 << 8)

#define AT91C_MCI_SPCMD_IT_REP   (0x5 << 8)

#define AT91C_MCI_OPDCMD   (0x1 << 11)

#define AT91C_MCI_OPDCMD_PUSHPULL   (0x0 << 11)

#define AT91C_MCI_OPDCMD_OPENDRAIN   (0x1 << 11)

#define AT91C_MCI_MAXLAT   (0x1 << 12)

#define AT91C_MCI_MAXLAT_5   (0x0 << 12)

#define AT91C_MCI_MAXLAT_64   (0x1 << 12)

#define AT91C_MCI_TRCMD   (0x3 << 16)

#define AT91C_MCI_TRCMD_NO   (0x0 << 16)

#define AT91C_MCI_TRCMD_START   (0x1 << 16)

#define AT91C_MCI_TRCMD_STOP   (0x2 << 16)

#define AT91C_MCI_TRDIR   (0x1 << 18)

#define AT91C_MCI_TRDIR_WRITE   (0x0 << 18)

#define AT91C_MCI_TRDIR_READ   (0x1 << 18)

#define AT91C_MCI_TRTYP   (0x7 << 19)

#define AT91C_MCI_TRTYP_BLOCK   (0x0 << 19)

#define AT91C_MCI_TRTYP_MULTIPLE   (0x1 << 19)

#define AT91C_MCI_TRTYP_STREAM   (0x2 << 19)

#define AT91C_MCI_TRTYP_SDIO_BYTE   (0x4 << 19)

#define AT91C_MCI_TRTYP_SDIO_BLOCK   (0x5 << 19)

#define AT91C_MCI_IOSPCMD   (0x3 << 24)

#define AT91C_MCI_IOSPCMD_NONE   (0x0 << 24)

#define AT91C_MCI_IOSPCMD_SUSPEND   (0x1 << 24)

#define AT91C_MCI_IOSPCMD_RESUME   (0x2 << 24)

#define AT91C_MCI_ATACS   (0x1 << 26)

#define AT91C_MCI_ATACS_NORMAL   (0x0 << 26)

#define AT91C_MCI_ATACS_COMPLETION   (0x1 << 26)

#define AT91C_MCI_BCNT   (0xFFFF << 0)

#define AT91C_MCI_CSTOCYC   (0xF << 0)

#define AT91C_MCI_CSTOMUL   (0x7 << 4)

#define AT91C_MCI_CSTOMUL_1   (0x0 << 4)

#define AT91C_MCI_CSTOMUL_16   (0x1 << 4)

#define AT91C_MCI_CSTOMUL_128   (0x2 << 4)

#define AT91C_MCI_CSTOMUL_256   (0x3 << 4)

#define AT91C_MCI_CSTOMUL_1024   (0x4 << 4)

#define AT91C_MCI_CSTOMUL_4096   (0x5 << 4)

#define AT91C_MCI_CSTOMUL_65536   (0x6 << 4)

#define AT91C_MCI_CSTOMUL_1048576   (0x7 << 4)

#define AT91C_MCI_CMDRDY   (0x1 << 0)

#define AT91C_MCI_RXRDY   (0x1 << 1)

#define AT91C_MCI_TXRDY   (0x1 << 2)

#define AT91C_MCI_BLKE   (0x1 << 3)

#define AT91C_MCI_DTIP   (0x1 << 4)

#define AT91C_MCI_NOTBUSY   (0x1 << 5)

#define AT91C_MCI_ENDRX   (0x1 << 6)

#define AT91C_MCI_ENDTX   (0x1 << 7)

#define AT91C_MCI_SDIOIRQA   (0x1 << 8)

#define AT91C_MCI_SDIOIRQB   (0x1 << 9)

#define AT91C_MCI_SDIOIRQC   (0x1 << 10)

#define AT91C_MCI_SDIOIRQD   (0x1 << 11)

#define AT91C_MCI_SDIOWAIT   (0x1 << 12)

#define AT91C_MCI_CSRCV   (0x1 << 13)

#define AT91C_MCI_RXBUFF   (0x1 << 14)

#define AT91C_MCI_TXBUFE   (0x1 << 15)

#define AT91C_MCI_RINDE   (0x1 << 16)

#define AT91C_MCI_RDIRE   (0x1 << 17)

#define AT91C_MCI_RCRCE   (0x1 << 18)

#define AT91C_MCI_RENDE   (0x1 << 19)

#define AT91C_MCI_RTOE   (0x1 << 20)

#define AT91C_MCI_DCRCE   (0x1 << 21)

#define AT91C_MCI_DTOE   (0x1 << 22)

#define AT91C_MCI_CSTOE   (0x1 << 23)

#define AT91C_MCI_BLKOVRE   (0x1 << 24)

#define AT91C_MCI_DMADONE   (0x1 << 25)

#define AT91C_MCI_FIFOEMPTY   (0x1 << 26)

#define AT91C_MCI_XFRDONE   (0x1 << 27)

#define AT91C_MCI_OVRE   (0x1 << 30)

#define AT91C_MCI_UNRE   (0x1 << 31)

#define AT91C_MCI_OFFSET   (0x3 << 0)

#define AT91C_MCI_CHKSIZE   (0x7 << 4)

#define AT91C_MCI_CHKSIZE_1   (0x0 << 4)

#define AT91C_MCI_CHKSIZE_4   (0x1 << 4)

#define AT91C_MCI_CHKSIZE_8   (0x2 << 4)

#define AT91C_MCI_CHKSIZE_16   (0x3 << 4)

#define AT91C_MCI_CHKSIZE_32   (0x4 << 4)

#define AT91C_MCI_DMAEN   (0x1 << 8)

#define AT91C_MCI_DMAEN_DISABLE   (0x0 << 8)

#define AT91C_MCI_DMAEN_ENABLE   (0x1 << 8)

#define AT91C_MCI_FIFOMODE   (0x1 << 0)

#define AT91C_MCI_FIFOMODE_AMOUNTDATA   (0x0)

#define AT91C_MCI_FIFOMODE_ONEDATA   (0x1)

#define AT91C_MCI_FERRCTRL   (0x1 << 4)

#define AT91C_MCI_FERRCTRL_RWCMD   (0x0 << 4)

#define AT91C_MCI_FERRCTRL_READSR   (0x1 << 4)

#define AT91C_MCI_HSMODE   (0x1 << 8)

#define AT91C_MCI_HSMODE_DISABLE   (0x0 << 8)

#define AT91C_MCI_HSMODE_ENABLE   (0x1 << 8)

#define AT91C_MCI_LSYNC   (0x1 << 12)

#define AT91C_MCI_LSYNC_CURRENT   (0x0 << 12)

#define AT91C_MCI_LSYNC_INFINITE   (0x1 << 12)

#define AT91C_MCI_WP_EN   (0x1 << 0)

#define AT91C_MCI_WP_EN_DISABLE   (0x0)

#define AT91C_MCI_WP_EN_ENABLE   (0x1)

#define AT91C_MCI_WP_KEY   (0xFFFFFF << 8)

#define AT91C_MCI_WP_VS   (0xF << 0)

#define AT91C_MCI_WP_VS_NO_VIOLATION   (0x0)

#define AT91C_MCI_WP_VS_ON_WRITE   (0x1)

#define AT91C_MCI_WP_VS_ON_RESET   (0x2)

#define AT91C_MCI_WP_VS_ON_BOTH   (0x3)

#define AT91C_MCI_WP_VSRC   (0xF << 8)

#define AT91C_MCI_WP_VSRC_NO_VIOLATION   (0x0 << 8)

#define AT91C_MCI_WP_VSRC_MCI_MR   (0x1 << 8)

#define AT91C_MCI_WP_VSRC_MCI_DTOR   (0x2 << 8)

#define AT91C_MCI_WP_VSRC_MCI_SDCR   (0x3 << 8)

#define AT91C_MCI_WP_VSRC_MCI_CSTOR   (0x4 << 8)

#define AT91C_MCI_WP_VSRC_MCI_DMA   (0x5 << 8)

#define AT91C_MCI_WP_VSRC_MCI_CFG   (0x6 << 8)

#define AT91C_MCI_WP_VSRC_MCI_DEL   (0x7 << 8)

#define AT91C_MCI_VER   (0xF << 0)

#define AT91C_TWI_START   (0x1 << 0)

#define AT91C_TWI_STOP   (0x1 << 1)

#define AT91C_TWI_MSEN   (0x1 << 2)

#define AT91C_TWI_MSDIS   (0x1 << 3)

#define AT91C_TWI_SVEN   (0x1 << 4)

#define AT91C_TWI_SVDIS   (0x1 << 5)

#define AT91C_TWI_SWRST   (0x1 << 7)

#define AT91C_TWI_IADRSZ   (0x3 << 8)

#define AT91C_TWI_IADRSZ_NO   (0x0 << 8)

#define AT91C_TWI_IADRSZ_1_BYTE   (0x1 << 8)

#define AT91C_TWI_IADRSZ_2_BYTE   (0x2 << 8)

#define AT91C_TWI_IADRSZ_3_BYTE   (0x3 << 8)

#define AT91C_TWI_MREAD   (0x1 << 12)

#define AT91C_TWI_DADR   (0x7F << 16)

#define AT91C_TWI_SADR   (0x7F << 16)

#define AT91C_TWI_CLDIV   (0xFF << 0)

#define AT91C_TWI_CHDIV   (0xFF << 8)

#define AT91C_TWI_CKDIV   (0x7 << 16)

#define AT91C_TWI_TXCOMP_SLAVE   (0x1 << 0)

#define AT91C_TWI_TXCOMP_MASTER   (0x1 << 0)

#define AT91C_TWI_RXRDY   (0x1 << 1)

#define AT91C_TWI_TXRDY_MASTER   (0x1 << 2)

#define AT91C_TWI_TXRDY_SLAVE   (0x1 << 2)

#define AT91C_TWI_SVREAD   (0x1 << 3)

#define AT91C_TWI_SVACC   (0x1 << 4)

#define AT91C_TWI_GACC   (0x1 << 5)

#define AT91C_TWI_OVRE   (0x1 << 6)

#define AT91C_TWI_NACK_SLAVE   (0x1 << 8)

#define AT91C_TWI_NACK_MASTER   (0x1 << 8)

#define AT91C_TWI_ARBLST_MULTI_MASTER   (0x1 << 9)

#define AT91C_TWI_SCLWS   (0x1 << 10)

#define AT91C_TWI_EOSACC   (0x1 << 11)

#define AT91C_TWI_ENDRX   (0x1 << 12)

#define AT91C_TWI_ENDTX   (0x1 << 13)

#define AT91C_TWI_RXBUFF   (0x1 << 14)

#define AT91C_TWI_TXBUFE   (0x1 << 15)

#define US_CR_OFF   ( 0x00000000)

#define US_MR_OFF   ( 0x00000004)

#define US_IER_OFF   ( 0x00000008)

#define US_IDR_OFF   ( 0x0000000C)

#define US_IMR_OFF   ( 0x00000010)

#define US_CSR_OFF   ( 0x00000014)

#define US_RHR_OFF   ( 0x00000018)

#define US_THR_OFF   ( 0x0000001C)

#define US_BRGR_OFF   ( 0x00000020)

#define US_RTOR_OFF   ( 0x00000024)

#define US_TTGR_OFF   ( 0x00000028)

#define US_FIDI_OFF   ( 0x00000040)

#define US_NER_OFF   ( 0x00000044)

#define US_IF_OFF   ( 0x0000004C)

#define US_MAN_OFF   ( 0x00000050)

#define US_ADDRSIZE_OFF   ( 0x000000EC)

#define US_IPNAME1_OFF   ( 0x000000F0)

#define US_IPNAME2_OFF   ( 0x000000F4)

#define US_FEATURES_OFF   ( 0x000000F8)

#define US_VER_OFF   ( 0x000000FC)

#define US_RSTRX   (0x1 << 2)

#define US_RSTTX   (0x1 << 3)

#define US_RXEN   (0x1 << 4)

#define US_RXDIS   (0x1 << 5)

#define US_TXEN   (0x1 << 6)

#define US_TXDIS   (0x1 << 7)

#define US_RSTSTA   (0x1 << 8)

#define US_STTBRK   (0x1 << 9)

#define US_STPBRK   (0x1 << 10)

#define US_STTTO   (0x1 << 11)

#define US_SENDA   (0x1 << 12)

#define US_RSTIT   (0x1 << 13)

#define US_RSTNACK   (0x1 << 14)

#define US_RETTO   (0x1 << 15)

#define US_DTREN   (0x1 << 16)

#define US_DTRDIS   (0x1 << 17)

#define US_RTSEN   (0x1 << 18)

#define US_RTSDIS   (0x1 << 19)

#define US_USMODE   (0xF << 0)

#define US_USMODE_NORMAL   (0x0)

#define US_USMODE_RS485   (0x1)

#define US_USMODE_HWHSH   (0x2)

#define US_USMODE_MODEM   (0x3)

#define US_USMODE_ISO7816_0   (0x4)

#define US_USMODE_ISO7816_1   (0x6)

#define US_USMODE_IRDA   (0x8)

#define US_USMODE_SWHSH   (0xC)

#define US_CLKS   (0x3 << 4)

#define US_CLKS_MCK   (0x0 << 4)

#define US_CLKS_MCK8   (0x1 << 4)

#define US_CLKS_SLCK   (0x2 << 4)

#define US_CLKS_SCK   (0x3 << 4)

#define US_CHRL   (0x3 << 6)

#define US_CHRL_5   (0x0 << 6)

#define US_CHRL_6   (0x1 << 6)

#define US_CHRL_7   (0x2 << 6)

#define US_CHRL_8   (0x3 << 6)

#define US_SYNC   (0x1 << 8)

#define US_PAR   (0x7 << 9)

#define US_PAR_EVEN   (0x0 << 9)

#define US_PAR_ODD   (0x1 << 9)

#define US_PAR_SPACE   (0x2 << 9)

#define US_PAR_MARK   (0x3 << 9)

#define US_PAR_NO   (0x4 << 9)

#define US_PAR_MULTIDROP   (0x6 << 9)

#define US_NBSTOP   (0x3 << 12)

#define US_NBSTOP_1   (0x0 << 12)

#define US_NBSTOP_15   (0x1 << 12)

#define US_NBSTOP_2_BIT   (0x2 << 12)

#define US_CHMODE   (0x3 << 14)

#define US_CHMODE_NORMAL   (0x0 << 14)

#define US_CHMODE_AUTO   (0x1 << 14)

#define US_CHMODE_LOCAL   (0x2 << 14)

#define US_CHMODE_REMOTE   (0x3 << 14)

#define US_MSBF   (0x1 << 16)

#define US_MODE9   (0x1 << 17)

#define US_CKLO   (0x1 << 18)

#define US_OVER   (0x1 << 19)

#define US_INACK   (0x1 << 20)

#define US_DSNACK   (0x1 << 21)

#define US_VAR_SYNC   (0x1 << 22)

#define US_MAX_ITER   (0x1 << 24)

#define US_FILTER   (0x1 << 28)

#define US_MANMODE   (0x1 << 29)

#define US_MODSYNC   (0x1 << 30)

#define US_ONEBIT   (0x1 << 31)

#define US_RXRDY   (0x1 << 0)

#define US_TXRDY   (0x1 << 1)

#define US_RXBRK   (0x1 << 2)

#define US_ENDRX   (0x1 << 3)

#define US_ENDTX   (0x1 << 4)

#define US_OVRE   (0x1 << 5)

#define US_FRAME   (0x1 << 6)

#define US_PARE   (0x1 << 7)

#define US_TIMEOUT   (0x1 << 8)

#define US_TXEMPTY   (0x1 << 9)

#define US_ITERATION   (0x1 << 10)

#define US_TXBUFE   (0x1 << 11)

#define US_RXBUFF   (0x1 << 12)

#define US_NACK   (0x1 << 13)

#define US_RIIC   (0x1 << 16)

#define US_DSRIC   (0x1 << 17)

#define US_DCDIC   (0x1 << 18)

#define US_CTSIC   (0x1 << 19)

#define US_MANE   (0x1 << 20)

#define US_RI   (0x1 << 20)

#define US_DSR   (0x1 << 21)

#define US_DCD   (0x1 << 22)

#define US_CTS   (0x1 << 23)

#define US_MANERR   (0x1 << 24)

#define US_TX_PL   (0xF << 0)

#define US_TX_PP   (0x3 << 8)

#define US_TX_PP_ALL_ONE   (0x0 << 8)

#define US_TX_PP_ALL_ZERO   (0x1 << 8)

#define US_TX_PP_ZERO_ONE   (0x2 << 8)

#define US_TX_PP_ONE_ZERO   (0x3 << 8)

#define US_TX_MPOL   (0x1 << 12)

#define US_RX_PL   (0xF << 16)

#define US_RX_PP   (0x3 << 24)

#define US_RX_PP_ALL_ONE   (0x0 << 24)

#define US_RX_PP_ALL_ZERO   (0x1 << 24)

#define US_RX_PP_ZERO_ONE   (0x2 << 24)

#define US_RX_PP_ONE_ZERO   (0x3 << 24)

#define US_RX_MPOL   (0x1 << 28)

#define US_DRIFT   (0x1 << 30)

#define AT91C_SSC_RXEN   (0x1 << 0)

#define AT91C_SSC_RXDIS   (0x1 << 1)

#define AT91C_SSC_TXEN   (0x1 << 8)

#define AT91C_SSC_TXDIS   (0x1 << 9)

#define AT91C_SSC_SWRST   (0x1 << 15)

#define AT91C_SSC_CKS   (0x3 << 0)

#define AT91C_SSC_CKS_DIV   (0x0)

#define AT91C_SSC_CKS_TK   (0x1)

#define AT91C_SSC_CKS_RK   (0x2)

#define AT91C_SSC_CKO   (0x7 << 2)

#define AT91C_SSC_CKO_NONE   (0x0 << 2)

#define AT91C_SSC_CKO_CONTINOUS   (0x1 << 2)

#define AT91C_SSC_CKO_DATA_TX   (0x2 << 2)

#define AT91C_SSC_CKI   (0x1 << 5)

#define AT91C_SSC_CKG   (0x3 << 6)

#define AT91C_SSC_CKG_NONE   (0x0 << 6)

#define AT91C_SSC_CKG_LOW   (0x1 << 6)

#define AT91C_SSC_CKG_HIGH   (0x2 << 6)

#define AT91C_SSC_START   (0xF << 8)

#define AT91C_SSC_START_CONTINOUS   (0x0 << 8)

#define AT91C_SSC_START_TX   (0x1 << 8)

#define AT91C_SSC_START_LOW_RF   (0x2 << 8)

#define AT91C_SSC_START_HIGH_RF   (0x3 << 8)

#define AT91C_SSC_START_FALL_RF   (0x4 << 8)

#define AT91C_SSC_START_RISE_RF   (0x5 << 8)

#define AT91C_SSC_START_LEVEL_RF   (0x6 << 8)

#define AT91C_SSC_START_EDGE_RF   (0x7 << 8)

#define AT91C_SSC_START_0   (0x8 << 8)

#define AT91C_SSC_STOP   (0x1 << 12)

#define AT91C_SSC_STTDLY   (0xFF << 16)

#define AT91C_SSC_PERIOD   (0xFF << 24)

#define AT91C_SSC_DATLEN   (0x1F << 0)

#define AT91C_SSC_LOOP   (0x1 << 5)

#define AT91C_SSC_MSBF   (0x1 << 7)

#define AT91C_SSC_DATNB   (0xF << 8)

#define AT91C_SSC_FSLEN   (0xF << 16)

#define AT91C_SSC_FSOS   (0x7 << 20)

#define AT91C_SSC_FSOS_NONE   (0x0 << 20)

#define AT91C_SSC_FSOS_NEGATIVE   (0x1 << 20)

#define AT91C_SSC_FSOS_POSITIVE   (0x2 << 20)

#define AT91C_SSC_FSOS_LOW   (0x3 << 20)

#define AT91C_SSC_FSOS_HIGH   (0x4 << 20)

#define AT91C_SSC_FSOS_TOGGLE   (0x5 << 20)

#define AT91C_SSC_FSEDGE   (0x1 << 24)

#define AT91C_SSC_DATDEF   (0x1 << 5)

#define AT91C_SSC_FSDEN   (0x1 << 23)

#define AT91C_SSC_TXRDY   (0x1 << 0)

#define AT91C_SSC_TXEMPTY   (0x1 << 1)

#define AT91C_SSC_ENDTX   (0x1 << 2)

#define AT91C_SSC_TXBUFE   (0x1 << 3)

#define AT91C_SSC_RXRDY   (0x1 << 4)

#define AT91C_SSC_OVRUN   (0x1 << 5)

#define AT91C_SSC_ENDRX   (0x1 << 6)

#define AT91C_SSC_RXBUFF   (0x1 << 7)

#define AT91C_SSC_CP0   (0x1 << 8)

#define AT91C_SSC_CP1   (0x1 << 9)

#define AT91C_SSC_TXSYN   (0x1 << 10)

#define AT91C_SSC_RXSYN   (0x1 << 11)

#define AT91C_SSC_TXENA   (0x1 << 16)

#define AT91C_SSC_RXENA   (0x1 << 17)

#define AT91C_PWMC_CPRE   (0xF << 0)

#define AT91C_PWMC_CPRE_MCK   (0x0)

#define AT91C_PWMC_CPRE_MCK_DIV_2   (0x1)

#define AT91C_PWMC_CPRE_MCK_DIV_4   (0x2)

#define AT91C_PWMC_CPRE_MCK_DIV_8   (0x3)

#define AT91C_PWMC_CPRE_MCK_DIV_16   (0x4)

#define AT91C_PWMC_CPRE_MCK_DIV_32   (0x5)

#define AT91C_PWMC_CPRE_MCK_DIV_64   (0x6)

#define AT91C_PWMC_CPRE_MCK_DIV_128   (0x7)

#define AT91C_PWMC_CPRE_MCK_DIV_256   (0x8)

#define AT91C_PWMC_CPRE_MCK_DIV_512   (0x9)

#define AT91C_PWMC_CPRE_MCK_DIV_1024   (0xA)

#define AT91C_PWMC_CPRE_MCKA   (0xB)

#define AT91C_PWMC_CPRE_MCKB   (0xC)

#define AT91C_PWMC_CALG   (0x1 << 8)

#define AT91C_PWMC_CPOL   (0x1 << 9)

#define AT91C_PWMC_CES   (0x1 << 10)

#define AT91C_PWMC_DTE   (0x1 << 16)

#define AT91C_PWMC_DTHI   (0x1 << 17)

#define AT91C_PWMC_DTLI   (0x1 << 18)

#define AT91C_PWMC_CDTY   (0xFFFFFF << 0)

#define AT91C_PWMC_CDTYUPD   (0xFFFFFF << 0)

#define AT91C_PWMC_CPRD   (0xFFFFFF << 0)

#define AT91C_PWMC_CPRDUPD   (0xFFFFFF << 0)

#define AT91C_PWMC_CCNT   (0xFFFFFF << 0)

#define AT91C_PWMC_DTL   (0xFFFF << 0)

#define AT91C_PWMC_DTH   (0xFFFF << 16)

#define AT91C_PWMC_DTLUPD   (0xFFFF << 0)

#define AT91C_PWMC_DTHUPD   (0xFFFF << 16)

#define AT91C_PWMC_DIVA   (0xFF << 0)

#define AT91C_PWMC_PREA   (0xF << 8)

#define AT91C_PWMC_PREA_MCK   (0x0 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_2   (0x1 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_4   (0x2 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_8   (0x3 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_16   (0x4 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_32   (0x5 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_64   (0x6 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_128   (0x7 << 8)

#define AT91C_PWMC_PREA_MCK_DIV_256   (0x8 << 8)

#define AT91C_PWMC_DIVB   (0xFF << 16)

#define AT91C_PWMC_PREB   (0xF << 24)

#define AT91C_PWMC_PREB_MCK   (0x0 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_2   (0x1 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_4   (0x2 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_8   (0x3 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_16   (0x4 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_32   (0x5 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_64   (0x6 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_128   (0x7 << 24)

#define AT91C_PWMC_PREB_MCK_DIV_256   (0x8 << 24)

#define AT91C_PWMC_CLKSEL   (0x1 << 31)

#define AT91C_PWMC_CHID0   (0x1 << 0)

#define AT91C_PWMC_CHID1   (0x1 << 1)

#define AT91C_PWMC_CHID2   (0x1 << 2)

#define AT91C_PWMC_CHID3   (0x1 << 3)

#define AT91C_PWMC_CHID4   (0x1 << 4)

#define AT91C_PWMC_CHID5   (0x1 << 5)

#define AT91C_PWMC_CHID6   (0x1 << 6)

#define AT91C_PWMC_CHID7   (0x1 << 7)

#define AT91C_PWMC_CHID8   (0x1 << 8)

#define AT91C_PWMC_CHID9   (0x1 << 9)

#define AT91C_PWMC_CHID10   (0x1 << 10)

#define AT91C_PWMC_CHID11   (0x1 << 11)

#define AT91C_PWMC_CHID12   (0x1 << 12)

#define AT91C_PWMC_CHID13   (0x1 << 13)

#define AT91C_PWMC_CHID14   (0x1 << 14)

#define AT91C_PWMC_CHID15   (0x1 << 15)

#define AT91C_PWMC_FCHID0   (0x1 << 16)

#define AT91C_PWMC_FCHID1   (0x1 << 17)

#define AT91C_PWMC_FCHID2   (0x1 << 18)

#define AT91C_PWMC_FCHID3   (0x1 << 19)

#define AT91C_PWMC_FCHID4   (0x1 << 20)

#define AT91C_PWMC_FCHID5   (0x1 << 21)

#define AT91C_PWMC_FCHID6   (0x1 << 22)

#define AT91C_PWMC_FCHID7   (0x1 << 23)

#define AT91C_PWMC_FCHID8   (0x1 << 24)

#define AT91C_PWMC_FCHID9   (0x1 << 25)

#define AT91C_PWMC_FCHID10   (0x1 << 26)

#define AT91C_PWMC_FCHID11   (0x1 << 27)

#define AT91C_PWMC_FCHID12   (0x1 << 28)

#define AT91C_PWMC_FCHID13   (0x1 << 29)

#define AT91C_PWMC_FCHID14   (0x1 << 30)

#define AT91C_PWMC_FCHID15   (0x1 << 31)

#define AT91C_PWMC_SYNC0   (0x1 << 0)

#define AT91C_PWMC_SYNC1   (0x1 << 1)

#define AT91C_PWMC_SYNC2   (0x1 << 2)

#define AT91C_PWMC_SYNC3   (0x1 << 3)

#define AT91C_PWMC_SYNC4   (0x1 << 4)

#define AT91C_PWMC_SYNC5   (0x1 << 5)

#define AT91C_PWMC_SYNC6   (0x1 << 6)

#define AT91C_PWMC_SYNC7   (0x1 << 7)

#define AT91C_PWMC_SYNC8   (0x1 << 8)

#define AT91C_PWMC_SYNC9   (0x1 << 9)

#define AT91C_PWMC_SYNC10   (0x1 << 10)

#define AT91C_PWMC_SYNC11   (0x1 << 11)

#define AT91C_PWMC_SYNC12   (0x1 << 12)

#define AT91C_PWMC_SYNC13   (0x1 << 13)

#define AT91C_PWMC_SYNC14   (0x1 << 14)

#define AT91C_PWMC_SYNC15   (0x1 << 15)

#define AT91C_PWMC_UPDM   (0x3 << 16)

#define AT91C_PWMC_UPDM_MODE0   (0x0 << 16)

#define AT91C_PWMC_UPDM_MODE1   (0x1 << 16)

#define AT91C_PWMC_UPDM_MODE2   (0x2 << 16)

#define AT91C_PWMC_UPDULOCK   (0x1 << 0)

#define AT91C_PWMC_UPR   (0xF << 0)

#define AT91C_PWMC_UPRCNT   (0xF << 4)

#define AT91C_PWMC_UPVUPDAL   (0xF << 0)

#define AT91C_PWMC_WRDY   (0x1 << 0)

#define AT91C_PWMC_ENDTX   (0x1 << 1)

#define AT91C_PWMC_TXBUFE   (0x1 << 2)

#define AT91C_PWMC_UNRE   (0x1 << 3)

#define AT91C_PWMC_CMPM0   (0x1 << 8)

#define AT91C_PWMC_CMPM1   (0x1 << 9)

#define AT91C_PWMC_CMPM2   (0x1 << 10)

#define AT91C_PWMC_CMPM3   (0x1 << 11)

#define AT91C_PWMC_CMPM4   (0x1 << 12)

#define AT91C_PWMC_CMPM5   (0x1 << 13)

#define AT91C_PWMC_CMPM6   (0x1 << 14)

#define AT91C_PWMC_CMPM7   (0x1 << 15)

#define AT91C_PWMC_CMPU0   (0x1 << 16)

#define AT91C_PWMC_CMPU1   (0x1 << 17)

#define AT91C_PWMC_CMPU2   (0x1 << 18)

#define AT91C_PWMC_CMPU3   (0x1 << 19)

#define AT91C_PWMC_CMPU4   (0x1 << 20)

#define AT91C_PWMC_CMPU5   (0x1 << 21)

#define AT91C_PWMC_CMPU6   (0x1 << 22)

#define AT91C_PWMC_CMPU7   (0x1 << 23)

#define AT91C_PWMC_OOVH0   (0x1 << 0)

#define AT91C_PWMC_OOVH1   (0x1 << 1)

#define AT91C_PWMC_OOVH2   (0x1 << 2)

#define AT91C_PWMC_OOVH3   (0x1 << 3)

#define AT91C_PWMC_OOVH4   (0x1 << 4)

#define AT91C_PWMC_OOVH5   (0x1 << 5)

#define AT91C_PWMC_OOVH6   (0x1 << 6)

#define AT91C_PWMC_OOVH7   (0x1 << 7)

#define AT91C_PWMC_OOVH8   (0x1 << 8)

#define AT91C_PWMC_OOVH9   (0x1 << 9)

#define AT91C_PWMC_OOVH10   (0x1 << 10)

#define AT91C_PWMC_OOVH11   (0x1 << 11)

#define AT91C_PWMC_OOVH12   (0x1 << 12)

#define AT91C_PWMC_OOVH13   (0x1 << 13)

#define AT91C_PWMC_OOVH14   (0x1 << 14)

#define AT91C_PWMC_OOVH15   (0x1 << 15)

#define AT91C_PWMC_OOVL0   (0x1 << 16)

#define AT91C_PWMC_OOVL1   (0x1 << 17)

#define AT91C_PWMC_OOVL2   (0x1 << 18)

#define AT91C_PWMC_OOVL3   (0x1 << 19)

#define AT91C_PWMC_OOVL4   (0x1 << 20)

#define AT91C_PWMC_OOVL5   (0x1 << 21)

#define AT91C_PWMC_OOVL6   (0x1 << 22)

#define AT91C_PWMC_OOVL7   (0x1 << 23)

#define AT91C_PWMC_OOVL8   (0x1 << 24)

#define AT91C_PWMC_OOVL9   (0x1 << 25)

#define AT91C_PWMC_OOVL10   (0x1 << 26)

#define AT91C_PWMC_OOVL11   (0x1 << 27)

#define AT91C_PWMC_OOVL12   (0x1 << 28)

#define AT91C_PWMC_OOVL13   (0x1 << 29)

#define AT91C_PWMC_OOVL14   (0x1 << 30)

#define AT91C_PWMC_OOVL15   (0x1 << 31)

#define AT91C_PWMC_OSH0   (0x1 << 0)

#define AT91C_PWMC_OSH1   (0x1 << 1)

#define AT91C_PWMC_OSH2   (0x1 << 2)

#define AT91C_PWMC_OSH3   (0x1 << 3)

#define AT91C_PWMC_OSH4   (0x1 << 4)

#define AT91C_PWMC_OSH5   (0x1 << 5)

#define AT91C_PWMC_OSH6   (0x1 << 6)

#define AT91C_PWMC_OSH7   (0x1 << 7)

#define AT91C_PWMC_OSH8   (0x1 << 8)

#define AT91C_PWMC_OSH9   (0x1 << 9)

#define AT91C_PWMC_OSH10   (0x1 << 10)

#define AT91C_PWMC_OSH11   (0x1 << 11)

#define AT91C_PWMC_OSH12   (0x1 << 12)

#define AT91C_PWMC_OSH13   (0x1 << 13)

#define AT91C_PWMC_OSH14   (0x1 << 14)

#define AT91C_PWMC_OSH15   (0x1 << 15)

#define AT91C_PWMC_OSL0   (0x1 << 16)

#define AT91C_PWMC_OSL1   (0x1 << 17)

#define AT91C_PWMC_OSL2   (0x1 << 18)

#define AT91C_PWMC_OSL3   (0x1 << 19)

#define AT91C_PWMC_OSL4   (0x1 << 20)

#define AT91C_PWMC_OSL5   (0x1 << 21)

#define AT91C_PWMC_OSL6   (0x1 << 22)

#define AT91C_PWMC_OSL7   (0x1 << 23)

#define AT91C_PWMC_OSL8   (0x1 << 24)

#define AT91C_PWMC_OSL9   (0x1 << 25)

#define AT91C_PWMC_OSL10   (0x1 << 26)

#define AT91C_PWMC_OSL11   (0x1 << 27)

#define AT91C_PWMC_OSL12   (0x1 << 28)

#define AT91C_PWMC_OSL13   (0x1 << 29)

#define AT91C_PWMC_OSL14   (0x1 << 30)

#define AT91C_PWMC_OSL15   (0x1 << 31)

#define AT91C_PWMC_OSSH0   (0x1 << 0)

#define AT91C_PWMC_OSSH1   (0x1 << 1)

#define AT91C_PWMC_OSSH2   (0x1 << 2)

#define AT91C_PWMC_OSSH3   (0x1 << 3)

#define AT91C_PWMC_OSSH4   (0x1 << 4)

#define AT91C_PWMC_OSSH5   (0x1 << 5)

#define AT91C_PWMC_OSSH6   (0x1 << 6)

#define AT91C_PWMC_OSSH7   (0x1 << 7)

#define AT91C_PWMC_OSSH8   (0x1 << 8)

#define AT91C_PWMC_OSSH9   (0x1 << 9)

#define AT91C_PWMC_OSSH10   (0x1 << 10)

#define AT91C_PWMC_OSSH11   (0x1 << 11)

#define AT91C_PWMC_OSSH12   (0x1 << 12)

#define AT91C_PWMC_OSSH13   (0x1 << 13)

#define AT91C_PWMC_OSSH14   (0x1 << 14)

#define AT91C_PWMC_OSSH15   (0x1 << 15)

#define AT91C_PWMC_OSSL0   (0x1 << 16)

#define AT91C_PWMC_OSSL1   (0x1 << 17)

#define AT91C_PWMC_OSSL2   (0x1 << 18)

#define AT91C_PWMC_OSSL3   (0x1 << 19)

#define AT91C_PWMC_OSSL4   (0x1 << 20)

#define AT91C_PWMC_OSSL5   (0x1 << 21)

#define AT91C_PWMC_OSSL6   (0x1 << 22)

#define AT91C_PWMC_OSSL7   (0x1 << 23)

#define AT91C_PWMC_OSSL8   (0x1 << 24)

#define AT91C_PWMC_OSSL9   (0x1 << 25)

#define AT91C_PWMC_OSSL10   (0x1 << 26)

#define AT91C_PWMC_OSSL11   (0x1 << 27)

#define AT91C_PWMC_OSSL12   (0x1 << 28)

#define AT91C_PWMC_OSSL13   (0x1 << 29)

#define AT91C_PWMC_OSSL14   (0x1 << 30)

#define AT91C_PWMC_OSSL15   (0x1 << 31)

#define AT91C_PWMC_OSCH0   (0x1 << 0)

#define AT91C_PWMC_OSCH1   (0x1 << 1)

#define AT91C_PWMC_OSCH2   (0x1 << 2)

#define AT91C_PWMC_OSCH3   (0x1 << 3)

#define AT91C_PWMC_OSCH4   (0x1 << 4)

#define AT91C_PWMC_OSCH5   (0x1 << 5)

#define AT91C_PWMC_OSCH6   (0x1 << 6)

#define AT91C_PWMC_OSCH7   (0x1 << 7)

#define AT91C_PWMC_OSCH8   (0x1 << 8)

#define AT91C_PWMC_OSCH9   (0x1 << 9)

#define AT91C_PWMC_OSCH10   (0x1 << 10)

#define AT91C_PWMC_OSCH11   (0x1 << 11)

#define AT91C_PWMC_OSCH12   (0x1 << 12)

#define AT91C_PWMC_OSCH13   (0x1 << 13)

#define AT91C_PWMC_OSCH14   (0x1 << 14)

#define AT91C_PWMC_OSCH15   (0x1 << 15)

#define AT91C_PWMC_OSCL0   (0x1 << 16)

#define AT91C_PWMC_OSCL1   (0x1 << 17)

#define AT91C_PWMC_OSCL2   (0x1 << 18)

#define AT91C_PWMC_OSCL3   (0x1 << 19)

#define AT91C_PWMC_OSCL4   (0x1 << 20)

#define AT91C_PWMC_OSCL5   (0x1 << 21)

#define AT91C_PWMC_OSCL6   (0x1 << 22)

#define AT91C_PWMC_OSCL7   (0x1 << 23)

#define AT91C_PWMC_OSCL8   (0x1 << 24)

#define AT91C_PWMC_OSCL9   (0x1 << 25)

#define AT91C_PWMC_OSCL10   (0x1 << 26)

#define AT91C_PWMC_OSCL11   (0x1 << 27)

#define AT91C_PWMC_OSCL12   (0x1 << 28)

#define AT91C_PWMC_OSCL13   (0x1 << 29)

#define AT91C_PWMC_OSCL14   (0x1 << 30)

#define AT91C_PWMC_OSCL15   (0x1 << 31)

#define AT91C_PWMC_OSSUPDH0   (0x1 << 0)

#define AT91C_PWMC_OSSUPDH1   (0x1 << 1)

#define AT91C_PWMC_OSSUPDH2   (0x1 << 2)

#define AT91C_PWMC_OSSUPDH3   (0x1 << 3)

#define AT91C_PWMC_OSSUPDH4   (0x1 << 4)

#define AT91C_PWMC_OSSUPDH5   (0x1 << 5)

#define AT91C_PWMC_OSSUPDH6   (0x1 << 6)

#define AT91C_PWMC_OSSUPDH7   (0x1 << 7)

#define AT91C_PWMC_OSSUPDH8   (0x1 << 8)

#define AT91C_PWMC_OSSUPDH9   (0x1 << 9)

#define AT91C_PWMC_OSSUPDH10   (0x1 << 10)

#define AT91C_PWMC_OSSUPDH11   (0x1 << 11)

#define AT91C_PWMC_OSSUPDH12   (0x1 << 12)

#define AT91C_PWMC_OSSUPDH13   (0x1 << 13)

#define AT91C_PWMC_OSSUPDH14   (0x1 << 14)

#define AT91C_PWMC_OSSUPDH15   (0x1 << 15)

#define AT91C_PWMC_OSSUPDL0   (0x1 << 16)

#define AT91C_PWMC_OSSUPDL1   (0x1 << 17)

#define AT91C_PWMC_OSSUPDL2   (0x1 << 18)

#define AT91C_PWMC_OSSUPDL3   (0x1 << 19)

#define AT91C_PWMC_OSSUPDL4   (0x1 << 20)

#define AT91C_PWMC_OSSUPDL5   (0x1 << 21)

#define AT91C_PWMC_OSSUPDL6   (0x1 << 22)

#define AT91C_PWMC_OSSUPDL7   (0x1 << 23)

#define AT91C_PWMC_OSSUPDL8   (0x1 << 24)

#define AT91C_PWMC_OSSUPDL9   (0x1 << 25)

#define AT91C_PWMC_OSSUPDL10   (0x1 << 26)

#define AT91C_PWMC_OSSUPDL11   (0x1 << 27)

#define AT91C_PWMC_OSSUPDL12   (0x1 << 28)

#define AT91C_PWMC_OSSUPDL13   (0x1 << 29)

#define AT91C_PWMC_OSSUPDL14   (0x1 << 30)

#define AT91C_PWMC_OSSUPDL15   (0x1 << 31)

#define AT91C_PWMC_OSCUPDH0   (0x1 << 0)

#define AT91C_PWMC_OSCUPDH1   (0x1 << 1)

#define AT91C_PWMC_OSCUPDH2   (0x1 << 2)

#define AT91C_PWMC_OSCUPDH3   (0x1 << 3)

#define AT91C_PWMC_OSCUPDH4   (0x1 << 4)

#define AT91C_PWMC_OSCUPDH5   (0x1 << 5)

#define AT91C_PWMC_OSCUPDH6   (0x1 << 6)

#define AT91C_PWMC_OSCUPDH7   (0x1 << 7)

#define AT91C_PWMC_OSCUPDH8   (0x1 << 8)

#define AT91C_PWMC_OSCUPDH9   (0x1 << 9)

#define AT91C_PWMC_OSCUPDH10   (0x1 << 10)

#define AT91C_PWMC_OSCUPDH11   (0x1 << 11)

#define AT91C_PWMC_OSCUPDH12   (0x1 << 12)

#define AT91C_PWMC_OSCUPDH13   (0x1 << 13)

#define AT91C_PWMC_OSCUPDH14   (0x1 << 14)

#define AT91C_PWMC_OSCUPDH15   (0x1 << 15)

#define AT91C_PWMC_OSCUPDL0   (0x1 << 16)

#define AT91C_PWMC_OSCUPDL1   (0x1 << 17)

#define AT91C_PWMC_OSCUPDL2   (0x1 << 18)

#define AT91C_PWMC_OSCUPDL3   (0x1 << 19)

#define AT91C_PWMC_OSCUPDL4   (0x1 << 20)

#define AT91C_PWMC_OSCUPDL5   (0x1 << 21)

#define AT91C_PWMC_OSCUPDL6   (0x1 << 22)

#define AT91C_PWMC_OSCUPDL7   (0x1 << 23)

#define AT91C_PWMC_OSCUPDL8   (0x1 << 24)

#define AT91C_PWMC_OSCUPDL9   (0x1 << 25)

#define AT91C_PWMC_OSCUPDL10   (0x1 << 26)

#define AT91C_PWMC_OSCUPDL11   (0x1 << 27)

#define AT91C_PWMC_OSCUPDL12   (0x1 << 28)

#define AT91C_PWMC_OSCUPDL13   (0x1 << 29)

#define AT91C_PWMC_OSCUPDL14   (0x1 << 30)

#define AT91C_PWMC_OSCUPDL15   (0x1 << 31)

#define AT91C_PWMC_FPOL0   (0x1 << 0)

#define AT91C_PWMC_FPOL1   (0x1 << 1)

#define AT91C_PWMC_FPOL2   (0x1 << 2)

#define AT91C_PWMC_FPOL3   (0x1 << 3)

#define AT91C_PWMC_FPOL4   (0x1 << 4)

#define AT91C_PWMC_FPOL5   (0x1 << 5)

#define AT91C_PWMC_FPOL6   (0x1 << 6)

#define AT91C_PWMC_FPOL7   (0x1 << 7)

#define AT91C_PWMC_FMOD0   (0x1 << 8)

#define AT91C_PWMC_FMOD1   (0x1 << 9)

#define AT91C_PWMC_FMOD2   (0x1 << 10)

#define AT91C_PWMC_FMOD3   (0x1 << 11)

#define AT91C_PWMC_FMOD4   (0x1 << 12)

#define AT91C_PWMC_FMOD5   (0x1 << 13)

#define AT91C_PWMC_FMOD6   (0x1 << 14)

#define AT91C_PWMC_FMOD7   (0x1 << 15)

#define AT91C_PWMC_FFIL00   (0x1 << 16)

#define AT91C_PWMC_FFIL01   (0x1 << 17)

#define AT91C_PWMC_FFIL02   (0x1 << 18)

#define AT91C_PWMC_FFIL03   (0x1 << 19)

#define AT91C_PWMC_FFIL04   (0x1 << 20)

#define AT91C_PWMC_FFIL05   (0x1 << 21)

#define AT91C_PWMC_FFIL06   (0x1 << 22)

#define AT91C_PWMC_FFIL07   (0x1 << 23)

#define AT91C_PWMC_FIV0   (0x1 << 0)

#define AT91C_PWMC_FIV1   (0x1 << 1)

#define AT91C_PWMC_FIV2   (0x1 << 2)

#define AT91C_PWMC_FIV3   (0x1 << 3)

#define AT91C_PWMC_FIV4   (0x1 << 4)

#define AT91C_PWMC_FIV5   (0x1 << 5)

#define AT91C_PWMC_FIV6   (0x1 << 6)

#define AT91C_PWMC_FIV7   (0x1 << 7)

#define AT91C_PWMC_FS0   (0x1 << 8)

#define AT91C_PWMC_FS1   (0x1 << 9)

#define AT91C_PWMC_FS2   (0x1 << 10)

#define AT91C_PWMC_FS3   (0x1 << 11)

#define AT91C_PWMC_FS4   (0x1 << 12)

#define AT91C_PWMC_FS5   (0x1 << 13)

#define AT91C_PWMC_FS6   (0x1 << 14)

#define AT91C_PWMC_FS7   (0x1 << 15)

#define AT91C_PWMC_FCLR0   (0x1 << 0)

#define AT91C_PWMC_FCLR1   (0x1 << 1)

#define AT91C_PWMC_FCLR2   (0x1 << 2)

#define AT91C_PWMC_FCLR3   (0x1 << 3)

#define AT91C_PWMC_FCLR4   (0x1 << 4)

#define AT91C_PWMC_FCLR5   (0x1 << 5)

#define AT91C_PWMC_FCLR6   (0x1 << 6)

#define AT91C_PWMC_FCLR7   (0x1 << 7)

#define AT91C_PWMC_FPVH0   (0x1 << 0)

#define AT91C_PWMC_FPVH1   (0x1 << 1)

#define AT91C_PWMC_FPVH2   (0x1 << 2)

#define AT91C_PWMC_FPVH3   (0x1 << 3)

#define AT91C_PWMC_FPVH4   (0x1 << 4)

#define AT91C_PWMC_FPVH5   (0x1 << 5)

#define AT91C_PWMC_FPVH6   (0x1 << 6)

#define AT91C_PWMC_FPVH7   (0x1 << 7)

#define AT91C_PWMC_FPVL0   (0x1 << 16)

#define AT91C_PWMC_FPVL1   (0x1 << 17)

#define AT91C_PWMC_FPVL2   (0x1 << 18)

#define AT91C_PWMC_FPVL3   (0x1 << 19)

#define AT91C_PWMC_FPVL4   (0x1 << 20)

#define AT91C_PWMC_FPVL5   (0x1 << 21)

#define AT91C_PWMC_FPVL6   (0x1 << 22)

#define AT91C_PWMC_FPVL7   (0x1 << 23)

#define AT91C_PWMC_FPE0   (0xFF << 0)

#define AT91C_PWMC_FPE1   (0xFF << 8)

#define AT91C_PWMC_FPE2   (0xFF << 16)

#define AT91C_PWMC_FPE3   (0xFF << 24)

#define AT91C_PWMC_FPE4   (0xFF << 0)

#define AT91C_PWMC_FPE5   (0xFF << 8)

#define AT91C_PWMC_FPE6   (0xFF << 16)

#define AT91C_PWMC_FPE7   (0xFF << 24)

#define AT91C_PWMC_FPE8   (0xFF << 0)

#define AT91C_PWMC_FPE9   (0xFF << 8)

#define AT91C_PWMC_FPE10   (0xFF << 16)

#define AT91C_PWMC_FPE11   (0xFF << 24)

#define AT91C_PWMC_FPE12   (0xFF << 0)

#define AT91C_PWMC_FPE13   (0xFF << 8)

#define AT91C_PWMC_FPE14   (0xFF << 16)

#define AT91C_PWMC_FPE15   (0xFF << 24)

#define AT91C_PWMC_L0CSEL0   (0x1 << 0)

#define AT91C_PWMC_L0CSEL1   (0x1 << 1)

#define AT91C_PWMC_L0CSEL2   (0x1 << 2)

#define AT91C_PWMC_L0CSEL3   (0x1 << 3)

#define AT91C_PWMC_L0CSEL4   (0x1 << 4)

#define AT91C_PWMC_L0CSEL5   (0x1 << 5)

#define AT91C_PWMC_L0CSEL6   (0x1 << 6)

#define AT91C_PWMC_L0CSEL7   (0x1 << 7)

#define AT91C_PWMC_L1CSEL0   (0x1 << 0)

#define AT91C_PWMC_L1CSEL1   (0x1 << 1)

#define AT91C_PWMC_L1CSEL2   (0x1 << 2)

#define AT91C_PWMC_L1CSEL3   (0x1 << 3)

#define AT91C_PWMC_L1CSEL4   (0x1 << 4)

#define AT91C_PWMC_L1CSEL5   (0x1 << 5)

#define AT91C_PWMC_L1CSEL6   (0x1 << 6)

#define AT91C_PWMC_L1CSEL7   (0x1 << 7)

#define AT91C_PWMC_L2CSEL0   (0x1 << 0)

#define AT91C_PWMC_L2CSEL1   (0x1 << 1)

#define AT91C_PWMC_L2CSEL2   (0x1 << 2)

#define AT91C_PWMC_L2CSEL3   (0x1 << 3)

#define AT91C_PWMC_L2CSEL4   (0x1 << 4)

#define AT91C_PWMC_L2CSEL5   (0x1 << 5)

#define AT91C_PWMC_L2CSEL6   (0x1 << 6)

#define AT91C_PWMC_L2CSEL7   (0x1 << 7)

#define AT91C_PWMC_L3CSEL0   (0x1 << 0)

#define AT91C_PWMC_L3CSEL1   (0x1 << 1)

#define AT91C_PWMC_L3CSEL2   (0x1 << 2)

#define AT91C_PWMC_L3CSEL3   (0x1 << 3)

#define AT91C_PWMC_L3CSEL4   (0x1 << 4)

#define AT91C_PWMC_L3CSEL5   (0x1 << 5)

#define AT91C_PWMC_L3CSEL6   (0x1 << 6)

#define AT91C_PWMC_L3CSEL7   (0x1 << 7)

#define AT91C_PWMC_L4CSEL0   (0x1 << 0)

#define AT91C_PWMC_L4CSEL1   (0x1 << 1)

#define AT91C_PWMC_L4CSEL2   (0x1 << 2)

#define AT91C_PWMC_L4CSEL3   (0x1 << 3)

#define AT91C_PWMC_L4CSEL4   (0x1 << 4)

#define AT91C_PWMC_L4CSEL5   (0x1 << 5)

#define AT91C_PWMC_L4CSEL6   (0x1 << 6)

#define AT91C_PWMC_L4CSEL7   (0x1 << 7)

#define AT91C_PWMC_L5CSEL0   (0x1 << 0)

#define AT91C_PWMC_L5CSEL1   (0x1 << 1)

#define AT91C_PWMC_L5CSEL2   (0x1 << 2)

#define AT91C_PWMC_L5CSEL3   (0x1 << 3)

#define AT91C_PWMC_L5CSEL4   (0x1 << 4)

#define AT91C_PWMC_L5CSEL5   (0x1 << 5)

#define AT91C_PWMC_L5CSEL6   (0x1 << 6)

#define AT91C_PWMC_L5CSEL7   (0x1 << 7)

#define AT91C_PWMC_L6CSEL0   (0x1 << 0)

#define AT91C_PWMC_L6CSEL1   (0x1 << 1)

#define AT91C_PWMC_L6CSEL2   (0x1 << 2)

#define AT91C_PWMC_L6CSEL3   (0x1 << 3)

#define AT91C_PWMC_L6CSEL4   (0x1 << 4)

#define AT91C_PWMC_L6CSEL5   (0x1 << 5)

#define AT91C_PWMC_L6CSEL6   (0x1 << 6)

#define AT91C_PWMC_L6CSEL7   (0x1 << 7)

#define AT91C_PWMC_L7CSEL0   (0x1 << 0)

#define AT91C_PWMC_L7CSEL1   (0x1 << 1)

#define AT91C_PWMC_L7CSEL2   (0x1 << 2)

#define AT91C_PWMC_L7CSEL3   (0x1 << 3)

#define AT91C_PWMC_L7CSEL4   (0x1 << 4)

#define AT91C_PWMC_L7CSEL5   (0x1 << 5)

#define AT91C_PWMC_L7CSEL6   (0x1 << 6)

#define AT91C_PWMC_L7CSEL7   (0x1 << 7)

#define AT91C_PWMC_WPCMD   (0x3 << 0)

#define AT91C_PWMC_WPRG0   (0x1 << 2)

#define AT91C_PWMC_WPRG1   (0x1 << 3)

#define AT91C_PWMC_WPRG2   (0x1 << 4)

#define AT91C_PWMC_WPRG3   (0x1 << 5)

#define AT91C_PWMC_WPRG4   (0x1 << 6)

#define AT91C_PWMC_WPRG5   (0x1 << 7)

#define AT91C_PWMC_WPKEY   (0xFFFFFF << 8)

#define AT91C_PWMC_WPSWS0   (0x1 << 0)

#define AT91C_PWMC_WPSWS1   (0x1 << 1)

#define AT91C_PWMC_WPSWS2   (0x1 << 2)

#define AT91C_PWMC_WPSWS3   (0x1 << 3)

#define AT91C_PWMC_WPSWS4   (0x1 << 4)

#define AT91C_PWMC_WPSWS5   (0x1 << 5)

#define AT91C_PWMC_WPVS   (0x1 << 7)

#define AT91C_PWMC_WPHWS0   (0x1 << 8)

#define AT91C_PWMC_WPHWS1   (0x1 << 9)

#define AT91C_PWMC_WPHWS2   (0x1 << 10)

#define AT91C_PWMC_WPHWS3   (0x1 << 11)

#define AT91C_PWMC_WPHWS4   (0x1 << 12)

#define AT91C_PWMC_WPHWS5   (0x1 << 13)

#define AT91C_PWMC_WPVSRC   (0xFFFF << 16)

#define AT91C_PWMC_CV   (0xFFFFFF << 0)

#define AT91C_PWMC_CVM   (0x1 << 24)

#define AT91C_PWMC_CVUPD   (0xFFFFFF << 0)

#define AT91C_PWMC_CVMUPD   (0x1 << 24)

#define AT91C_PWMC_CEN   (0x1 << 0)

#define AT91C_PWMC_CTR   (0xF << 4)

#define AT91C_PWMC_CPR   (0xF << 8)

#define AT91C_PWMC_CPRCNT   (0xF << 12)

#define AT91C_PWMC_CUPR   (0xF << 16)

#define AT91C_PWMC_CUPRCNT   (0xF << 20)

#define AT91C_PWMC_CENUPD   (0x1 << 0)

#define AT91C_PWMC_CTRUPD   (0xF << 4)

#define AT91C_PWMC_CPRUPD   (0xF << 8)

#define AT91C_PWMC_CUPRUPD   (0xF << 16)

#define AT91C_SPI_SPIEN   (0x1 << 0)

#define AT91C_SPI_SPIDIS   (0x1 << 1)

#define AT91C_SPI_SWRST   (0x1 << 7)

#define AT91C_SPI_LASTXFER   (0x1 << 24)

#define AT91C_SPI_MSTR   (0x1 << 0)

#define AT91C_SPI_PS   (0x1 << 1)

#define AT91C_SPI_PS_FIXED   (0x0 << 1)

#define AT91C_SPI_PS_VARIABLE   (0x1 << 1)

#define AT91C_SPI_PCSDEC   (0x1 << 2)

#define AT91C_SPI_FDIV   (0x1 << 3)

#define AT91C_SPI_MODFDIS   (0x1 << 4)

#define AT91C_SPI_LLB   (0x1 << 7)

#define AT91C_SPI_PCS   (0xF << 16)

#define AT91C_SPI_DLYBCS   (0xFF << 24)

#define AT91C_SPI_RD   (0xFFFF << 0)

#define AT91C_SPI_RPCS   (0xF << 16)

#define AT91C_SPI_TD   (0xFFFF << 0)

#define AT91C_SPI_TPCS   (0xF << 16)

#define AT91C_SPI_RDRF   (0x1 << 0)

#define AT91C_SPI_TDRE   (0x1 << 1)

#define AT91C_SPI_MODF   (0x1 << 2)

#define AT91C_SPI_OVRES   (0x1 << 3)

#define AT91C_SPI_ENDRX   (0x1 << 4)

#define AT91C_SPI_ENDTX   (0x1 << 5)

#define AT91C_SPI_RXBUFF   (0x1 << 6)

#define AT91C_SPI_TXBUFE   (0x1 << 7)

#define AT91C_SPI_NSSR   (0x1 << 8)

#define AT91C_SPI_TXEMPTY   (0x1 << 9)

#define AT91C_SPI_SPIENS   (0x1 << 16)

#define AT91C_SPI_CPOL   (0x1 << 0)

#define AT91C_SPI_NCPHA   (0x1 << 1)

#define AT91C_SPI_CSNAAT   (0x1 << 2)

#define AT91C_SPI_CSAAT   (0x1 << 3)

#define AT91C_SPI_BITS   (0xF << 4)

#define AT91C_SPI_BITS_8   (0x0 << 4)

#define AT91C_SPI_BITS_9   (0x1 << 4)

#define AT91C_SPI_BITS_10   (0x2 << 4)

#define AT91C_SPI_BITS_11   (0x3 << 4)

#define AT91C_SPI_BITS_12   (0x4 << 4)

#define AT91C_SPI_BITS_13   (0x5 << 4)

#define AT91C_SPI_BITS_14   (0x6 << 4)

#define AT91C_SPI_BITS_15   (0x7 << 4)

#define AT91C_SPI_BITS_16   (0x8 << 4)

#define AT91C_SPI_SCBR   (0xFF << 8)

#define AT91C_SPI_DLYBS   (0xFF << 16)

#define AT91C_SPI_DLYBCT   (0xFF << 24)

#define AT91C_UDPHS_EPT_SIZE   (0x7 << 0)

#define AT91C_UDPHS_EPT_SIZE_8   (0x0)

#define AT91C_UDPHS_EPT_SIZE_16   (0x1)

#define AT91C_UDPHS_EPT_SIZE_32   (0x2)

#define AT91C_UDPHS_EPT_SIZE_64   (0x3)

#define AT91C_UDPHS_EPT_SIZE_128   (0x4)

#define AT91C_UDPHS_EPT_SIZE_256   (0x5)

#define AT91C_UDPHS_EPT_SIZE_512   (0x6)

#define AT91C_UDPHS_EPT_SIZE_1024   (0x7)

#define AT91C_UDPHS_EPT_DIR   (0x1 << 3)

#define AT91C_UDPHS_EPT_DIR_OUT   (0x0 << 3)

#define AT91C_UDPHS_EPT_DIR_IN   (0x1 << 3)

#define AT91C_UDPHS_EPT_TYPE   (0x3 << 4)

#define AT91C_UDPHS_EPT_TYPE_CTL_EPT   (0x0 << 4)

#define AT91C_UDPHS_EPT_TYPE_ISO_EPT   (0x1 << 4)

#define AT91C_UDPHS_EPT_TYPE_BUL_EPT   (0x2 << 4)

#define AT91C_UDPHS_EPT_TYPE_INT_EPT   (0x3 << 4)

#define AT91C_UDPHS_BK_NUMBER   (0x3 << 6)

#define AT91C_UDPHS_BK_NUMBER_0   (0x0 << 6)

#define AT91C_UDPHS_BK_NUMBER_1   (0x1 << 6)

#define AT91C_UDPHS_BK_NUMBER_2   (0x2 << 6)

#define AT91C_UDPHS_BK_NUMBER_3   (0x3 << 6)

#define AT91C_UDPHS_NB_TRANS   (0x3 << 8)

#define AT91C_UDPHS_EPT_MAPD   (0x1 << 31)

#define AT91C_UDPHS_EPT_ENABL   (0x1 << 0)

#define AT91C_UDPHS_AUTO_VALID   (0x1 << 1)

#define AT91C_UDPHS_INTDIS_DMA   (0x1 << 3)

#define AT91C_UDPHS_NYET_DIS   (0x1 << 4)

#define AT91C_UDPHS_DATAX_RX   (0x1 << 6)

#define AT91C_UDPHS_MDATA_RX   (0x1 << 7)

#define AT91C_UDPHS_ERR_OVFLW   (0x1 << 8)

#define AT91C_UDPHS_RX_BK_RDY   (0x1 << 9)

#define AT91C_UDPHS_TX_COMPLT   (0x1 << 10)

#define AT91C_UDPHS_ERR_TRANS   (0x1 << 11)

#define AT91C_UDPHS_TX_PK_RDY   (0x1 << 11)

#define AT91C_UDPHS_RX_SETUP   (0x1 << 12)

#define AT91C_UDPHS_ERR_FL_ISO   (0x1 << 12)

#define AT91C_UDPHS_STALL_SNT   (0x1 << 13)

#define AT91C_UDPHS_ERR_CRISO   (0x1 << 13)

#define AT91C_UDPHS_NAK_IN   (0x1 << 14)

#define AT91C_UDPHS_NAK_OUT   (0x1 << 15)

#define AT91C_UDPHS_BUSY_BANK   (0x1 << 18)

#define AT91C_UDPHS_SHRT_PCKT   (0x1 << 31)

#define AT91C_UDPHS_EPT_DISABL   (0x1 << 0)

#define AT91C_UDPHS_FRCESTALL   (0x1 << 5)

#define AT91C_UDPHS_KILL_BANK   (0x1 << 9)

#define AT91C_UDPHS_TOGGLESQ   (0x1 << 6)

#define AT91C_UDPHS_TOGGLESQ_STA   (0x3 << 6)

#define AT91C_UDPHS_TOGGLESQ_STA_00   (0x0 << 6)

#define AT91C_UDPHS_TOGGLESQ_STA_01   (0x1 << 6)

#define AT91C_UDPHS_TOGGLESQ_STA_10   (0x2 << 6)

#define AT91C_UDPHS_TOGGLESQ_STA_11   (0x3 << 6)

#define AT91C_UDPHS_CONTROL_DIR   (0x3 << 16)

#define AT91C_UDPHS_CONTROL_DIR_00   (0x0 << 16)

#define AT91C_UDPHS_CONTROL_DIR_01   (0x1 << 16)

#define AT91C_UDPHS_CONTROL_DIR_10   (0x2 << 16)

#define AT91C_UDPHS_CONTROL_DIR_11   (0x3 << 16)

#define AT91C_UDPHS_CURRENT_BANK   (0x3 << 16)

#define AT91C_UDPHS_CURRENT_BANK_00   (0x0 << 16)

#define AT91C_UDPHS_CURRENT_BANK_01   (0x1 << 16)

#define AT91C_UDPHS_CURRENT_BANK_10   (0x2 << 16)

#define AT91C_UDPHS_CURRENT_BANK_11   (0x3 << 16)

#define AT91C_UDPHS_BUSY_BANK_STA   (0x3 << 18)

#define AT91C_UDPHS_BUSY_BANK_STA_00   (0x0 << 18)

#define AT91C_UDPHS_BUSY_BANK_STA_01   (0x1 << 18)

#define AT91C_UDPHS_BUSY_BANK_STA_10   (0x2 << 18)

#define AT91C_UDPHS_BUSY_BANK_STA_11   (0x3 << 18)

#define AT91C_UDPHS_BYTE_COUNT   (0x7FF << 20)

#define AT91C_UDPHS_NXT_DSC_ADD   (0xFFFFFFF << 4)

#define AT91C_UDPHS_BUFF_ADD   (0x0 << 0)

#define AT91C_UDPHS_CHANN_ENB   (0x1 << 0)

#define AT91C_UDPHS_LDNXT_DSC   (0x1 << 1)

#define AT91C_UDPHS_END_TR_EN   (0x1 << 2)

#define AT91C_UDPHS_END_B_EN   (0x1 << 3)

#define AT91C_UDPHS_END_TR_IT   (0x1 << 4)

#define AT91C_UDPHS_END_BUFFIT   (0x1 << 5)

#define AT91C_UDPHS_DESC_LD_IT   (0x1 << 6)

#define AT91C_UDPHS_BURST_LCK   (0x1 << 7)

#define AT91C_UDPHS_BUFF_LENGTH   (0xFFFF << 16)

#define AT91C_UDPHS_CHANN_ACT   (0x1 << 1)

#define AT91C_UDPHS_END_TR_ST   (0x1 << 4)

#define AT91C_UDPHS_END_BF_ST   (0x1 << 5)

#define AT91C_UDPHS_DESC_LDST   (0x1 << 6)

#define AT91C_UDPHS_BUFF_COUNT   (0xFFFF << 16)

#define AT91C_UDPHS_DEV_ADDR   (0x7F << 0)

#define AT91C_UDPHS_FADDR_EN   (0x1 << 7)

#define AT91C_UDPHS_EN_UDPHS   (0x1 << 8)

#define AT91C_UDPHS_DETACH   (0x1 << 9)

#define AT91C_UDPHS_REWAKEUP   (0x1 << 10)

#define AT91C_UDPHS_PULLD_DIS   (0x1 << 11)

#define AT91C_UDPHS_MICRO_FRAME_NUM   (0x7 << 0)

#define AT91C_UDPHS_FRAME_NUMBER   (0x7FF << 3)

#define AT91C_UDPHS_FNUM_ERR   (0x1 << 31)

#define AT91C_UDPHS_DET_SUSPD   (0x1 << 1)

#define AT91C_UDPHS_MICRO_SOF   (0x1 << 2)

#define AT91C_UDPHS_IEN_SOF   (0x1 << 3)

#define AT91C_UDPHS_ENDRESET   (0x1 << 4)

#define AT91C_UDPHS_WAKE_UP   (0x1 << 5)

#define AT91C_UDPHS_ENDOFRSM   (0x1 << 6)

#define AT91C_UDPHS_UPSTR_RES   (0x1 << 7)

#define AT91C_UDPHS_EPT_INT_0   (0x1 << 8)

#define AT91C_UDPHS_EPT_INT_1   (0x1 << 9)

#define AT91C_UDPHS_EPT_INT_2   (0x1 << 10)

#define AT91C_UDPHS_EPT_INT_3   (0x1 << 11)

#define AT91C_UDPHS_EPT_INT_4   (0x1 << 12)

#define AT91C_UDPHS_EPT_INT_5   (0x1 << 13)

#define AT91C_UDPHS_EPT_INT_6   (0x1 << 14)

#define AT91C_UDPHS_DMA_INT_1   (0x1 << 25)

#define AT91C_UDPHS_DMA_INT_2   (0x1 << 26)

#define AT91C_UDPHS_DMA_INT_3   (0x1 << 27)

#define AT91C_UDPHS_DMA_INT_4   (0x1 << 28)

#define AT91C_UDPHS_DMA_INT_5   (0x1 << 29)

#define AT91C_UDPHS_DMA_INT_6   (0x1 << 30)

#define AT91C_UDPHS_SPEED   (0x1 << 0)

#define AT91C_UDPHS_RST_EPT_0   (0x1 << 0)

#define AT91C_UDPHS_RST_EPT_1   (0x1 << 1)

#define AT91C_UDPHS_RST_EPT_2   (0x1 << 2)

#define AT91C_UDPHS_RST_EPT_3   (0x1 << 3)

#define AT91C_UDPHS_RST_EPT_4   (0x1 << 4)

#define AT91C_UDPHS_RST_EPT_5   (0x1 << 5)

#define AT91C_UDPHS_RST_EPT_6   (0x1 << 6)

#define AT91C_UDPHS_SOFCNTMAX   (0x3 << 0)

#define AT91C_UDPHS_SOFCTLOAD   (0x1 << 7)

#define AT91C_UDPHS_CNTAMAX   (0x7FFF << 0)

#define AT91C_UDPHS_CNTALOAD   (0x1 << 15)

#define AT91C_UDPHS_CNTBMAX   (0x7FFF << 0)

#define AT91C_UDPHS_CNTBLOAD   (0x1 << 15)

#define AT91C_UDPHS_TSTMODE   (0x1F << 1)

#define AT91C_UDPHS_SPEED_CFG   (0x3 << 0)

#define AT91C_UDPHS_SPEED_CFG_NM   (0x0)

#define AT91C_UDPHS_SPEED_CFG_RS   (0x1)

#define AT91C_UDPHS_SPEED_CFG_HS   (0x2)

#define AT91C_UDPHS_SPEED_CFG_FS   (0x3)

#define AT91C_UDPHS_TST_J   (0x1 << 2)

#define AT91C_UDPHS_TST_K   (0x1 << 3)

#define AT91C_UDPHS_TST_PKT   (0x1 << 4)

#define AT91C_UDPHS_OPMODE2   (0x1 << 5)

#define AT91C_UDPHS_IPPADDRSIZE   (0x0 << 0)

#define AT91C_UDPHS_IPNAME1   (0x0 << 0)

#define AT91C_UDPHS_IPNAME2   (0x0 << 0)

#define AT91C_UDPHS_EPT_NBR_MAX   (0xF << 0)

#define AT91C_UDPHS_DMA_CHANNEL_NBR   (0x7 << 4)

#define AT91C_UDPHS_DMA_B_SIZ   (0x1 << 7)

#define AT91C_UDPHS_DMA_FIFO_WORD_DEPTH   (0xF << 8)

#define AT91C_UDPHS_FIFO_MAX_SIZE   (0x7 << 12)

#define AT91C_UDPHS_BW_DPRAM   (0x1 << 15)

#define AT91C_UDPHS_DATAB16_8   (0x1 << 16)

#define AT91C_UDPHS_ISO_EPT_1   (0x1 << 17)

#define AT91C_UDPHS_ISO_EPT_2   (0x1 << 18)

#define AT91C_UDPHS_ISO_EPT_5   (0x1 << 21)

#define AT91C_UDPHS_ISO_EPT_6   (0x1 << 22)

#define AT91C_UDPHS_VERSION_NUM   (0xFFFF << 0)

#define AT91C_UDPHS_METAL_FIX_NUM   (0x7 << 16)

#define AT91C_SADDR   (0x0 << 0)

#define AT91C_DADDR   (0x0 << 0)

#define AT91C_HDMA_DSCR_IF   (0x3 << 0)

#define AT91C_HDMA_DSCR_IF_0   (0x0)

#define AT91C_HDMA_DSCR_IF_1   (0x1)

#define AT91C_HDMA_DSCR_IF_2   (0x2)

#define AT91C_HDMA_DSCR_IF_3   (0x3)

#define AT91C_HDMA_DSCR   (0x3FFFFFFF << 2)

#define AT91C_HDMA_BTSIZE   (0xFFFF << 0)

#define AT91C_HDMA_SCSIZE   (0x7 << 16)

#define AT91C_HDMA_SCSIZE_1   (0x0 << 16)

#define AT91C_HDMA_SCSIZE_4   (0x1 << 16)

#define AT91C_HDMA_SCSIZE_8   (0x2 << 16)

#define AT91C_HDMA_SCSIZE_16   (0x3 << 16)

#define AT91C_HDMA_SCSIZE_32   (0x4 << 16)

#define AT91C_HDMA_SCSIZE_64   (0x5 << 16)

#define AT91C_HDMA_SCSIZE_128   (0x6 << 16)

#define AT91C_HDMA_SCSIZE_256   (0x7 << 16)

#define AT91C_HDMA_DCSIZE   (0x7 << 20)

#define AT91C_HDMA_DCSIZE_1   (0x0 << 20)

#define AT91C_HDMA_DCSIZE_4   (0x1 << 20)

#define AT91C_HDMA_DCSIZE_8   (0x2 << 20)

#define AT91C_HDMA_DCSIZE_16   (0x3 << 20)

#define AT91C_HDMA_DCSIZE_32   (0x4 << 20)

#define AT91C_HDMA_DCSIZE_64   (0x5 << 20)

#define AT91C_HDMA_DCSIZE_128   (0x6 << 20)

#define AT91C_HDMA_DCSIZE_256   (0x7 << 20)

#define AT91C_HDMA_SRC_WIDTH   (0x3 << 24)

#define AT91C_HDMA_SRC_WIDTH_BYTE   (0x0 << 24)

#define AT91C_HDMA_SRC_WIDTH_HALFWORD   (0x1 << 24)

#define AT91C_HDMA_SRC_WIDTH_WORD   (0x2 << 24)

#define AT91C_HDMA_DST_WIDTH   (0x3 << 28)

#define AT91C_HDMA_DST_WIDTH_BYTE   (0x0 << 28)

#define AT91C_HDMA_DST_WIDTH_HALFWORD   (0x1 << 28)

#define AT91C_HDMA_DST_WIDTH_WORD   (0x2 << 28)

#define AT91C_HDMA_DONE   (0x1 << 31)

#define AT91C_HDMA_SIF   (0x3 << 0)

#define AT91C_HDMA_SIF_0   (0x0)

#define AT91C_HDMA_SIF_1   (0x1)

#define AT91C_HDMA_SIF_2   (0x2)

#define AT91C_HDMA_SIF_3   (0x3)

#define AT91C_HDMA_DIF   (0x3 << 4)

#define AT91C_HDMA_DIF_0   (0x0 << 4)

#define AT91C_HDMA_DIF_1   (0x1 << 4)

#define AT91C_HDMA_DIF_2   (0x2 << 4)

#define AT91C_HDMA_DIF_3   (0x3 << 4)

#define AT91C_HDMA_SRC_PIP   (0x1 << 8)

#define AT91C_HDMA_SRC_PIP_DISABLE   (0x0 << 8)

#define AT91C_HDMA_SRC_PIP_ENABLE   (0x1 << 8)

#define AT91C_HDMA_DST_PIP   (0x1 << 12)

#define AT91C_HDMA_DST_PIP_DISABLE   (0x0 << 12)

#define AT91C_HDMA_DST_PIP_ENABLE   (0x1 << 12)

#define AT91C_HDMA_SRC_DSCR   (0x1 << 16)

#define AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM   (0x0 << 16)

#define AT91C_HDMA_SRC_DSCR_FETCH_DISABLE   (0x1 << 16)

#define AT91C_HDMA_DST_DSCR   (0x1 << 20)

#define AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM   (0x0 << 20)

#define AT91C_HDMA_DST_DSCR_FETCH_DISABLE   (0x1 << 20)

#define AT91C_HDMA_FC   (0x7 << 21)

#define AT91C_HDMA_FC_MEM2MEM   (0x0 << 21)

#define AT91C_HDMA_FC_MEM2PER   (0x1 << 21)

#define AT91C_HDMA_FC_PER2MEM   (0x2 << 21)

#define AT91C_HDMA_FC_PER2PER   (0x3 << 21)

#define AT91C_HDMA_FC_PER2MEM_PER   (0x4 << 21)

#define AT91C_HDMA_FC_MEM2PER_PER   (0x5 << 21)

#define AT91C_HDMA_FC_PER2PER_PER   (0x6 << 21)

#define AT91C_HDMA_SRC_ADDRESS_MODE   (0x3 << 24)

#define AT91C_HDMA_SRC_ADDRESS_MODE_INCR   (0x0 << 24)

#define AT91C_HDMA_SRC_ADDRESS_MODE_DECR   (0x1 << 24)

#define AT91C_HDMA_SRC_ADDRESS_MODE_FIXED   (0x2 << 24)

#define AT91C_HDMA_DST_ADDRESS_MODE   (0x3 << 28)

#define AT91C_HDMA_DST_ADDRESS_MODE_INCR   (0x0 << 28)

#define AT91C_HDMA_DST_ADDRESS_MODE_DECR   (0x1 << 28)

#define AT91C_HDMA_DST_ADDRESS_MODE_FIXED   (0x2 << 28)

#define AT91C_HDMA_AUTO   (0x1 << 31)

#define AT91C_HDMA_AUTO_DISABLE   (0x0 << 31)

#define AT91C_HDMA_AUTO_ENABLE   (0x1 << 31)

#define AT91C_HDMA_SRC_PER   (0xF << 0)

#define AT91C_HDMA_SRC_PER_0   (0x0)

#define AT91C_HDMA_SRC_PER_1   (0x1)

#define AT91C_HDMA_SRC_PER_2   (0x2)

#define AT91C_HDMA_SRC_PER_3   (0x3)

#define AT91C_HDMA_SRC_PER_4   (0x4)

#define AT91C_HDMA_SRC_PER_5   (0x5)

#define AT91C_HDMA_SRC_PER_6   (0x6)

#define AT91C_HDMA_SRC_PER_7   (0x7)

#define AT91C_HDMA_SRC_PER_8   (0x8)

#define AT91C_HDMA_SRC_PER_9   (0x9)

#define AT91C_HDMA_SRC_PER_10   (0xA)

#define AT91C_HDMA_SRC_PER_11   (0xB)

#define AT91C_HDMA_SRC_PER_12   (0xC)

#define AT91C_HDMA_SRC_PER_13   (0xD)

#define AT91C_HDMA_SRC_PER_14   (0xE)

#define AT91C_HDMA_SRC_PER_15   (0xF)

#define AT91C_HDMA_DST_PER   (0xF << 4)

#define AT91C_HDMA_DST_PER_0   (0x0 << 4)

#define AT91C_HDMA_DST_PER_1   (0x1 << 4)

#define AT91C_HDMA_DST_PER_2   (0x2 << 4)

#define AT91C_HDMA_DST_PER_3   (0x3 << 4)

#define AT91C_HDMA_DST_PER_4   (0x4 << 4)

#define AT91C_HDMA_DST_PER_5   (0x5 << 4)

#define AT91C_HDMA_DST_PER_6   (0x6 << 4)

#define AT91C_HDMA_DST_PER_7   (0x7 << 4)

#define AT91C_HDMA_DST_PER_8   (0x8 << 4)

#define AT91C_HDMA_DST_PER_9   (0x9 << 4)

#define AT91C_HDMA_DST_PER_10   (0xA << 4)

#define AT91C_HDMA_DST_PER_11   (0xB << 4)

#define AT91C_HDMA_DST_PER_12   (0xC << 4)

#define AT91C_HDMA_DST_PER_13   (0xD << 4)

#define AT91C_HDMA_DST_PER_14   (0xE << 4)

#define AT91C_HDMA_DST_PER_15   (0xF << 4)

#define AT91C_HDMA_SRC_REP   (0x1 << 8)

#define AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR   (0x0 << 8)

#define AT91C_HDMA_SRC_REP_RELOAD_ADDR   (0x1 << 8)

#define AT91C_HDMA_SRC_H2SEL   (0x1 << 9)

#define AT91C_HDMA_SRC_H2SEL_SW   (0x0 << 9)

#define AT91C_HDMA_SRC_H2SEL_HW   (0x1 << 9)

#define AT91C_HDMA_DST_REP   (0x1 << 12)

#define AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR   (0x0 << 12)

#define AT91C_HDMA_DST_REP_RELOAD_ADDR   (0x1 << 12)

#define AT91C_HDMA_DST_H2SEL   (0x1 << 13)

#define AT91C_HDMA_DST_H2SEL_SW   (0x0 << 13)

#define AT91C_HDMA_DST_H2SEL_HW   (0x1 << 13)

#define AT91C_HDMA_SOD   (0x1 << 16)

#define AT91C_HDMA_SOD_DISABLE   (0x0 << 16)

#define AT91C_HDMA_SOD_ENABLE   (0x1 << 16)

#define AT91C_HDMA_LOCK_IF   (0x1 << 20)

#define AT91C_HDMA_LOCK_IF_DISABLE   (0x0 << 20)

#define AT91C_HDMA_LOCK_IF_ENABLE   (0x1 << 20)

#define AT91C_HDMA_LOCK_B   (0x1 << 21)

#define AT91C_HDMA_LOCK_B_DISABLE   (0x0 << 21)

#define AT91C_HDMA_LOCK_B_ENABLE   (0x1 << 21)

#define AT91C_HDMA_LOCK_IF_L   (0x1 << 22)

#define AT91C_HDMA_LOCK_IF_L_CHUNK   (0x0 << 22)

#define AT91C_HDMA_LOCK_IF_L_BUFFER   (0x1 << 22)

#define AT91C_HDMA_AHB_PROT   (0x7 << 24)

#define AT91C_HDMA_FIFOCFG   (0x3 << 28)

#define AT91C_HDMA_FIFOCFG_LARGESTBURST   (0x0 << 28)

#define AT91C_HDMA_FIFOCFG_HALFFIFO   (0x1 << 28)

#define AT91C_HDMA_FIFOCFG_ENOUGHSPACE   (0x2 << 28)

#define AT91C_SPIP_HOLE   (0xFFFF << 0)

#define AT91C_SPIP_BOUNDARY   (0x3FF << 16)

#define AT91C_DPIP_HOLE   (0xFFFF << 0)

#define AT91C_DPIP_BOUNDARY   (0x3FF << 16)

#define AT91C_HDMA_IF0_BIGEND   (0x1 << 0)

#define AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN   (0x0)

#define AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN   (0x1)

#define AT91C_HDMA_IF1_BIGEND   (0x1 << 1)

#define AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 1)

#define AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN   (0x1 << 1)

#define AT91C_HDMA_IF2_BIGEND   (0x1 << 2)

#define AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 2)

#define AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN   (0x1 << 2)

#define AT91C_HDMA_IF3_BIGEND   (0x1 << 3)

#define AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN   (0x0 << 3)

#define AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN   (0x1 << 3)

#define AT91C_HDMA_ARB_CFG   (0x1 << 4)

#define AT91C_HDMA_ARB_CFG_FIXED   (0x0 << 4)

#define AT91C_HDMA_ARB_CFG_ROUND_ROBIN   (0x1 << 4)

#define AT91C_HDMA_ENABLE   (0x1 << 0)

#define AT91C_HDMA_ENABLE_DISABLE   (0x0)

#define AT91C_HDMA_ENABLE_ENABLE   (0x1)

#define AT91C_HDMA_SSREQ0   (0x1 << 0)

#define AT91C_HDMA_SSREQ0_0   (0x0)

#define AT91C_HDMA_SSREQ0_1   (0x1)

#define AT91C_HDMA_DSREQ0   (0x1 << 1)

#define AT91C_HDMA_DSREQ0_0   (0x0 << 1)

#define AT91C_HDMA_DSREQ0_1   (0x1 << 1)

#define AT91C_HDMA_SSREQ1   (0x1 << 2)

#define AT91C_HDMA_SSREQ1_0   (0x0 << 2)

#define AT91C_HDMA_SSREQ1_1   (0x1 << 2)

#define AT91C_HDMA_DSREQ1   (0x1 << 3)

#define AT91C_HDMA_DSREQ1_0   (0x0 << 3)

#define AT91C_HDMA_DSREQ1_1   (0x1 << 3)

#define AT91C_HDMA_SSREQ2   (0x1 << 4)

#define AT91C_HDMA_SSREQ2_0   (0x0 << 4)

#define AT91C_HDMA_SSREQ2_1   (0x1 << 4)

#define AT91C_HDMA_DSREQ2   (0x1 << 5)

#define AT91C_HDMA_DSREQ2_0   (0x0 << 5)

#define AT91C_HDMA_DSREQ2_1   (0x1 << 5)

#define AT91C_HDMA_SSREQ3   (0x1 << 6)

#define AT91C_HDMA_SSREQ3_0   (0x0 << 6)

#define AT91C_HDMA_SSREQ3_1   (0x1 << 6)

#define AT91C_HDMA_DSREQ3   (0x1 << 7)

#define AT91C_HDMA_DSREQ3_0   (0x0 << 7)

#define AT91C_HDMA_DSREQ3_1   (0x1 << 7)

#define AT91C_HDMA_SSREQ4   (0x1 << 8)

#define AT91C_HDMA_SSREQ4_0   (0x0 << 8)

#define AT91C_HDMA_SSREQ4_1   (0x1 << 8)

#define AT91C_HDMA_DSREQ4   (0x1 << 9)

#define AT91C_HDMA_DSREQ4_0   (0x0 << 9)

#define AT91C_HDMA_DSREQ4_1   (0x1 << 9)

#define AT91C_HDMA_SSREQ5   (0x1 << 10)

#define AT91C_HDMA_SSREQ5_0   (0x0 << 10)

#define AT91C_HDMA_SSREQ5_1   (0x1 << 10)

#define AT91C_HDMA_DSREQ6   (0x1 << 11)

#define AT91C_HDMA_DSREQ6_0   (0x0 << 11)

#define AT91C_HDMA_DSREQ6_1   (0x1 << 11)

#define AT91C_HDMA_SSREQ6   (0x1 << 12)

#define AT91C_HDMA_SSREQ6_0   (0x0 << 12)

#define AT91C_HDMA_SSREQ6_1   (0x1 << 12)

#define AT91C_HDMA_SSREQ7   (0x1 << 14)

#define AT91C_HDMA_SSREQ7_0   (0x0 << 14)

#define AT91C_HDMA_SSREQ7_1   (0x1 << 14)

#define AT91C_HDMA_DSREQ7   (0x1 << 15)

#define AT91C_HDMA_DSREQ7_0   (0x0 << 15)

#define AT91C_HDMA_DSREQ7_1   (0x1 << 15)

#define AT91C_HDMA_SCREQ0   (0x1 << 0)

#define AT91C_HDMA_SCREQ0_0   (0x0)

#define AT91C_HDMA_SCREQ0_1   (0x1)

#define AT91C_HDMA_DCREQ0   (0x1 << 1)

#define AT91C_HDMA_DCREQ0_0   (0x0 << 1)

#define AT91C_HDMA_DCREQ0_1   (0x1 << 1)

#define AT91C_HDMA_SCREQ1   (0x1 << 2)

#define AT91C_HDMA_SCREQ1_0   (0x0 << 2)

#define AT91C_HDMA_SCREQ1_1   (0x1 << 2)

#define AT91C_HDMA_DCREQ1   (0x1 << 3)

#define AT91C_HDMA_DCREQ1_0   (0x0 << 3)

#define AT91C_HDMA_DCREQ1_1   (0x1 << 3)

#define AT91C_HDMA_SCREQ2   (0x1 << 4)

#define AT91C_HDMA_SCREQ2_0   (0x0 << 4)

#define AT91C_HDMA_SCREQ2_1   (0x1 << 4)

#define AT91C_HDMA_DCREQ2   (0x1 << 5)

#define AT91C_HDMA_DCREQ2_0   (0x0 << 5)

#define AT91C_HDMA_DCREQ2_1   (0x1 << 5)

#define AT91C_HDMA_SCREQ3   (0x1 << 6)

#define AT91C_HDMA_SCREQ3_0   (0x0 << 6)

#define AT91C_HDMA_SCREQ3_1   (0x1 << 6)

#define AT91C_HDMA_DCREQ3   (0x1 << 7)

#define AT91C_HDMA_DCREQ3_0   (0x0 << 7)

#define AT91C_HDMA_DCREQ3_1   (0x1 << 7)

#define AT91C_HDMA_SCREQ4   (0x1 << 8)

#define AT91C_HDMA_SCREQ4_0   (0x0 << 8)

#define AT91C_HDMA_SCREQ4_1   (0x1 << 8)

#define AT91C_HDMA_DCREQ4   (0x1 << 9)

#define AT91C_HDMA_DCREQ4_0   (0x0 << 9)

#define AT91C_HDMA_DCREQ4_1   (0x1 << 9)

#define AT91C_HDMA_SCREQ5   (0x1 << 10)

#define AT91C_HDMA_SCREQ5_0   (0x0 << 10)

#define AT91C_HDMA_SCREQ5_1   (0x1 << 10)

#define AT91C_HDMA_DCREQ6   (0x1 << 11)

#define AT91C_HDMA_DCREQ6_0   (0x0 << 11)

#define AT91C_HDMA_DCREQ6_1   (0x1 << 11)

#define AT91C_HDMA_SCREQ6   (0x1 << 12)

#define AT91C_HDMA_SCREQ6_0   (0x0 << 12)

#define AT91C_HDMA_SCREQ6_1   (0x1 << 12)

#define AT91C_HDMA_SCREQ7   (0x1 << 14)

#define AT91C_HDMA_SCREQ7_0   (0x0 << 14)

#define AT91C_HDMA_SCREQ7_1   (0x1 << 14)

#define AT91C_HDMA_DCREQ7   (0x1 << 15)

#define AT91C_HDMA_DCREQ7_0   (0x0 << 15)

#define AT91C_HDMA_DCREQ7_1   (0x1 << 15)

#define AT91C_HDMA_SLAST0   (0x1 << 0)

#define AT91C_HDMA_SLAST0_0   (0x0)

#define AT91C_HDMA_SLAST0_1   (0x1)

#define AT91C_HDMA_DLAST0   (0x1 << 1)

#define AT91C_HDMA_DLAST0_0   (0x0 << 1)

#define AT91C_HDMA_DLAST0_1   (0x1 << 1)

#define AT91C_HDMA_SLAST1   (0x1 << 2)

#define AT91C_HDMA_SLAST1_0   (0x0 << 2)

#define AT91C_HDMA_SLAST1_1   (0x1 << 2)

#define AT91C_HDMA_DLAST1   (0x1 << 3)

#define AT91C_HDMA_DLAST1_0   (0x0 << 3)

#define AT91C_HDMA_DLAST1_1   (0x1 << 3)

#define AT91C_HDMA_SLAST2   (0x1 << 4)

#define AT91C_HDMA_SLAST2_0   (0x0 << 4)

#define AT91C_HDMA_SLAST2_1   (0x1 << 4)

#define AT91C_HDMA_DLAST2   (0x1 << 5)

#define AT91C_HDMA_DLAST2_0   (0x0 << 5)

#define AT91C_HDMA_DLAST2_1   (0x1 << 5)

#define AT91C_HDMA_SLAST3   (0x1 << 6)

#define AT91C_HDMA_SLAST3_0   (0x0 << 6)

#define AT91C_HDMA_SLAST3_1   (0x1 << 6)

#define AT91C_HDMA_DLAST3   (0x1 << 7)

#define AT91C_HDMA_DLAST3_0   (0x0 << 7)

#define AT91C_HDMA_DLAST3_1   (0x1 << 7)

#define AT91C_HDMA_SLAST4   (0x1 << 8)

#define AT91C_HDMA_SLAST4_0   (0x0 << 8)

#define AT91C_HDMA_SLAST4_1   (0x1 << 8)

#define AT91C_HDMA_DLAST4   (0x1 << 9)

#define AT91C_HDMA_DLAST4_0   (0x0 << 9)

#define AT91C_HDMA_DLAST4_1   (0x1 << 9)

#define AT91C_HDMA_SLAST5   (0x1 << 10)

#define AT91C_HDMA_SLAST5_0   (0x0 << 10)

#define AT91C_HDMA_SLAST5_1   (0x1 << 10)

#define AT91C_HDMA_DLAST6   (0x1 << 11)

#define AT91C_HDMA_DLAST6_0   (0x0 << 11)

#define AT91C_HDMA_DLAST6_1   (0x1 << 11)

#define AT91C_HDMA_SLAST6   (0x1 << 12)

#define AT91C_HDMA_SLAST6_0   (0x0 << 12)

#define AT91C_HDMA_SLAST6_1   (0x1 << 12)

#define AT91C_HDMA_SLAST7   (0x1 << 14)

#define AT91C_HDMA_SLAST7_0   (0x0 << 14)

#define AT91C_HDMA_SLAST7_1   (0x1 << 14)

#define AT91C_HDMA_DLAST7   (0x1 << 15)

#define AT91C_HDMA_DLAST7_0   (0x0 << 15)

#define AT91C_HDMA_DLAST7_1   (0x1 << 15)

#define AT91C_SYNC_REQ   (0xFFFF << 0)

#define AT91C_HDMA_BTC0   (0x1 << 0)

#define AT91C_HDMA_BTC1   (0x1 << 1)

#define AT91C_HDMA_BTC2   (0x1 << 2)

#define AT91C_HDMA_BTC3   (0x1 << 3)

#define AT91C_HDMA_BTC4   (0x1 << 4)

#define AT91C_HDMA_BTC5   (0x1 << 5)

#define AT91C_HDMA_BTC6   (0x1 << 6)

#define AT91C_HDMA_BTC7   (0x1 << 7)

#define AT91C_HDMA_CBTC0   (0x1 << 8)

#define AT91C_HDMA_CBTC1   (0x1 << 9)

#define AT91C_HDMA_CBTC2   (0x1 << 10)

#define AT91C_HDMA_CBTC3   (0x1 << 11)

#define AT91C_HDMA_CBTC4   (0x1 << 12)

#define AT91C_HDMA_CBTC5   (0x1 << 13)

#define AT91C_HDMA_CBTC6   (0x1 << 14)

#define AT91C_HDMA_CBTC7   (0x1 << 15)

#define AT91C_HDMA_ERR0   (0x1 << 16)

#define AT91C_HDMA_ERR1   (0x1 << 17)

#define AT91C_HDMA_ERR2   (0x1 << 18)

#define AT91C_HDMA_ERR3   (0x1 << 19)

#define AT91C_HDMA_ERR4   (0x1 << 20)

#define AT91C_HDMA_ERR5   (0x1 << 21)

#define AT91C_HDMA_ERR6   (0x1 << 22)

#define AT91C_HDMA_ERR7   (0x1 << 23)

#define AT91C_HDMA_ENA0   (0x1 << 0)

#define AT91C_HDMA_ENA0_0   (0x0)

#define AT91C_HDMA_ENA0_1   (0x1)

#define AT91C_HDMA_ENA1   (0x1 << 1)

#define AT91C_HDMA_ENA1_0   (0x0 << 1)

#define AT91C_HDMA_ENA1_1   (0x1 << 1)

#define AT91C_HDMA_ENA2   (0x1 << 2)

#define AT91C_HDMA_ENA2_0   (0x0 << 2)

#define AT91C_HDMA_ENA2_1   (0x1 << 2)

#define AT91C_HDMA_ENA3   (0x1 << 3)

#define AT91C_HDMA_ENA3_0   (0x0 << 3)

#define AT91C_HDMA_ENA3_1   (0x1 << 3)

#define AT91C_HDMA_ENA4   (0x1 << 4)

#define AT91C_HDMA_ENA4_0   (0x0 << 4)

#define AT91C_HDMA_ENA4_1   (0x1 << 4)

#define AT91C_HDMA_ENA5   (0x1 << 5)

#define AT91C_HDMA_ENA5_0   (0x0 << 5)

#define AT91C_HDMA_ENA5_1   (0x1 << 5)

#define AT91C_HDMA_ENA6   (0x1 << 6)

#define AT91C_HDMA_ENA6_0   (0x0 << 6)

#define AT91C_HDMA_ENA6_1   (0x1 << 6)

#define AT91C_HDMA_ENA7   (0x1 << 7)

#define AT91C_HDMA_ENA7_0   (0x0 << 7)

#define AT91C_HDMA_ENA7_1   (0x1 << 7)

#define AT91C_HDMA_SUSP0   (0x1 << 8)

#define AT91C_HDMA_SUSP0_0   (0x0 << 8)

#define AT91C_HDMA_SUSP0_1   (0x1 << 8)

#define AT91C_HDMA_SUSP1   (0x1 << 9)

#define AT91C_HDMA_SUSP1_0   (0x0 << 9)

#define AT91C_HDMA_SUSP1_1   (0x1 << 9)

#define AT91C_HDMA_SUSP2   (0x1 << 10)

#define AT91C_HDMA_SUSP2_0   (0x0 << 10)

#define AT91C_HDMA_SUSP2_1   (0x1 << 10)

#define AT91C_HDMA_SUSP3   (0x1 << 11)

#define AT91C_HDMA_SUSP3_0   (0x0 << 11)

#define AT91C_HDMA_SUSP3_1   (0x1 << 11)

#define AT91C_HDMA_SUSP4   (0x1 << 12)

#define AT91C_HDMA_SUSP4_0   (0x0 << 12)

#define AT91C_HDMA_SUSP4_1   (0x1 << 12)

#define AT91C_HDMA_SUSP5   (0x1 << 13)

#define AT91C_HDMA_SUSP5_0   (0x0 << 13)

#define AT91C_HDMA_SUSP5_1   (0x1 << 13)

#define AT91C_HDMA_SUSP6   (0x1 << 14)

#define AT91C_HDMA_SUSP6_0   (0x0 << 14)

#define AT91C_HDMA_SUSP6_1   (0x1 << 14)

#define AT91C_HDMA_SUSP7   (0x1 << 15)

#define AT91C_HDMA_SUSP7_0   (0x0 << 15)

#define AT91C_HDMA_SUSP7_1   (0x1 << 15)

#define AT91C_HDMA_KEEP0   (0x1 << 24)

#define AT91C_HDMA_KEEP0_0   (0x0 << 24)

#define AT91C_HDMA_KEEP0_1   (0x1 << 24)

#define AT91C_HDMA_KEEP1   (0x1 << 25)

#define AT91C_HDMA_KEEP1_0   (0x0 << 25)

#define AT91C_HDMA_KEEP1_1   (0x1 << 25)

#define AT91C_HDMA_KEEP2   (0x1 << 26)

#define AT91C_HDMA_KEEP2_0   (0x0 << 26)

#define AT91C_HDMA_KEEP2_1   (0x1 << 26)

#define AT91C_HDMA_KEEP3   (0x1 << 27)

#define AT91C_HDMA_KEEP3_0   (0x0 << 27)

#define AT91C_HDMA_KEEP3_1   (0x1 << 27)

#define AT91C_HDMA_KEEP4   (0x1 << 28)

#define AT91C_HDMA_KEEP4_0   (0x0 << 28)

#define AT91C_HDMA_KEEP4_1   (0x1 << 28)

#define AT91C_HDMA_KEEP5   (0x1 << 29)

#define AT91C_HDMA_KEEP5_0   (0x0 << 29)

#define AT91C_HDMA_KEEP5_1   (0x1 << 29)

#define AT91C_HDMA_KEEP6   (0x1 << 30)

#define AT91C_HDMA_KEEP6_0   (0x0 << 30)

#define AT91C_HDMA_KEEP6_1   (0x1 << 30)

#define AT91C_HDMA_KEEP7   (0x1 << 31)

#define AT91C_HDMA_KEEP7_0   (0x0 << 31)

#define AT91C_HDMA_KEEP7_1   (0x1 << 31)

#define AT91C_HDMA_DIS0   (0x1 << 0)

#define AT91C_HDMA_DIS0_0   (0x0)

#define AT91C_HDMA_DIS0_1   (0x1)

#define AT91C_HDMA_DIS1   (0x1 << 1)

#define AT91C_HDMA_DIS1_0   (0x0 << 1)

#define AT91C_HDMA_DIS1_1   (0x1 << 1)

#define AT91C_HDMA_DIS2   (0x1 << 2)

#define AT91C_HDMA_DIS2_0   (0x0 << 2)

#define AT91C_HDMA_DIS2_1   (0x1 << 2)

#define AT91C_HDMA_DIS3   (0x1 << 3)

#define AT91C_HDMA_DIS3_0   (0x0 << 3)

#define AT91C_HDMA_DIS3_1   (0x1 << 3)

#define AT91C_HDMA_DIS4   (0x1 << 4)

#define AT91C_HDMA_DIS4_0   (0x0 << 4)

#define AT91C_HDMA_DIS4_1   (0x1 << 4)

#define AT91C_HDMA_DIS5   (0x1 << 5)

#define AT91C_HDMA_DIS5_0   (0x0 << 5)

#define AT91C_HDMA_DIS5_1   (0x1 << 5)

#define AT91C_HDMA_DIS6   (0x1 << 6)

#define AT91C_HDMA_DIS6_0   (0x0 << 6)

#define AT91C_HDMA_DIS6_1   (0x1 << 6)

#define AT91C_HDMA_DIS7   (0x1 << 7)

#define AT91C_HDMA_DIS7_0   (0x0 << 7)

#define AT91C_HDMA_DIS7_1   (0x1 << 7)

#define AT91C_HDMA_RES0   (0x1 << 8)

#define AT91C_HDMA_RES0_0   (0x0 << 8)

#define AT91C_HDMA_RES0_1   (0x1 << 8)

#define AT91C_HDMA_RES1   (0x1 << 9)

#define AT91C_HDMA_RES1_0   (0x0 << 9)

#define AT91C_HDMA_RES1_1   (0x1 << 9)

#define AT91C_HDMA_RES2   (0x1 << 10)

#define AT91C_HDMA_RES2_0   (0x0 << 10)

#define AT91C_HDMA_RES2_1   (0x1 << 10)

#define AT91C_HDMA_RES3   (0x1 << 11)

#define AT91C_HDMA_RES3_0   (0x0 << 11)

#define AT91C_HDMA_RES3_1   (0x1 << 11)

#define AT91C_HDMA_RES4   (0x1 << 12)

#define AT91C_HDMA_RES4_0   (0x0 << 12)

#define AT91C_HDMA_RES4_1   (0x1 << 12)

#define AT91C_HDMA_RES5   (0x1 << 13)

#define AT91C_HDMA_RES5_0   (0x0 << 13)

#define AT91C_HDMA_RES5_1   (0x1 << 13)

#define AT91C_HDMA_RES6   (0x1 << 14)

#define AT91C_HDMA_RES6_0   (0x0 << 14)

#define AT91C_HDMA_RES6_1   (0x1 << 14)

#define AT91C_HDMA_RES7   (0x1 << 15)

#define AT91C_HDMA_RES7_0   (0x0 << 15)

#define AT91C_HDMA_RES7_1   (0x1 << 15)

#define AT91C_HDMA_EMPT0   (0x1 << 16)

#define AT91C_HDMA_EMPT0_0   (0x0 << 16)

#define AT91C_HDMA_EMPT0_1   (0x1 << 16)

#define AT91C_HDMA_EMPT1   (0x1 << 17)

#define AT91C_HDMA_EMPT1_0   (0x0 << 17)

#define AT91C_HDMA_EMPT1_1   (0x1 << 17)

#define AT91C_HDMA_EMPT2   (0x1 << 18)

#define AT91C_HDMA_EMPT2_0   (0x0 << 18)

#define AT91C_HDMA_EMPT2_1   (0x1 << 18)

#define AT91C_HDMA_EMPT3   (0x1 << 19)

#define AT91C_HDMA_EMPT3_0   (0x0 << 19)

#define AT91C_HDMA_EMPT3_1   (0x1 << 19)

#define AT91C_HDMA_EMPT4   (0x1 << 20)

#define AT91C_HDMA_EMPT4_0   (0x0 << 20)

#define AT91C_HDMA_EMPT4_1   (0x1 << 20)

#define AT91C_HDMA_EMPT5   (0x1 << 21)

#define AT91C_HDMA_EMPT5_0   (0x0 << 21)

#define AT91C_HDMA_EMPT5_1   (0x1 << 21)

#define AT91C_HDMA_EMPT6   (0x1 << 22)

#define AT91C_HDMA_EMPT6_0   (0x0 << 22)

#define AT91C_HDMA_EMPT6_1   (0x1 << 22)

#define AT91C_HDMA_EMPT7   (0x1 << 23)

#define AT91C_HDMA_EMPT7_0   (0x0 << 23)

#define AT91C_HDMA_EMPT7_1   (0x1 << 23)

#define AT91C_HDMA_STAL0   (0x1 << 24)

#define AT91C_HDMA_STAL0_0   (0x0 << 24)

#define AT91C_HDMA_STAL0_1   (0x1 << 24)

#define AT91C_HDMA_STAL1   (0x1 << 25)

#define AT91C_HDMA_STAL1_0   (0x0 << 25)

#define AT91C_HDMA_STAL1_1   (0x1 << 25)

#define AT91C_HDMA_STAL2   (0x1 << 26)

#define AT91C_HDMA_STAL2_0   (0x0 << 26)

#define AT91C_HDMA_STAL2_1   (0x1 << 26)

#define AT91C_HDMA_STAL3   (0x1 << 27)

#define AT91C_HDMA_STAL3_0   (0x0 << 27)

#define AT91C_HDMA_STAL3_1   (0x1 << 27)

#define AT91C_HDMA_STAL4   (0x1 << 28)

#define AT91C_HDMA_STAL4_0   (0x0 << 28)

#define AT91C_HDMA_STAL4_1   (0x1 << 28)

#define AT91C_HDMA_STAL5   (0x1 << 29)

#define AT91C_HDMA_STAL5_0   (0x0 << 29)

#define AT91C_HDMA_STAL5_1   (0x1 << 29)

#define AT91C_HDMA_STAL6   (0x1 << 30)

#define AT91C_HDMA_STAL6_0   (0x0 << 30)

#define AT91C_HDMA_STAL6_1   (0x1 << 30)

#define AT91C_HDMA_STAL7   (0x1 << 31)

#define AT91C_HDMA_STAL7_0   (0x0 << 31)

#define AT91C_HDMA_STAL7_1   (0x1 << 31)

#define AT91C_SYS_GPBR   (AT91_CAST(AT91_REG *) 0x400E1290)

#define AT91C_CS0_MODE   (AT91_CAST(AT91_REG *) 0x400E0080)

#define AT91C_CS0_PULSE   (AT91_CAST(AT91_REG *) 0x400E0074)

#define AT91C_CS0_CYCLE   (AT91_CAST(AT91_REG *) 0x400E0078)

#define AT91C_CS0_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E007C)

#define AT91C_CS0_SETUP   (AT91_CAST(AT91_REG *) 0x400E0070)

#define AT91C_CS1_CYCLE   (AT91_CAST(AT91_REG *) 0x400E008C)

#define AT91C_CS1_PULSE   (AT91_CAST(AT91_REG *) 0x400E0088)

#define AT91C_CS1_MODE   (AT91_CAST(AT91_REG *) 0x400E0094)

#define AT91C_CS1_SETUP   (AT91_CAST(AT91_REG *) 0x400E0084)

#define AT91C_CS1_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E0090)

#define AT91C_CS2_PULSE   (AT91_CAST(AT91_REG *) 0x400E009C)

#define AT91C_CS2_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E00A4)

#define AT91C_CS2_CYCLE   (AT91_CAST(AT91_REG *) 0x400E00A0)

#define AT91C_CS2_MODE   (AT91_CAST(AT91_REG *) 0x400E00A8)

#define AT91C_CS2_SETUP   (AT91_CAST(AT91_REG *) 0x400E0098)

#define AT91C_CS3_MODE   (AT91_CAST(AT91_REG *) 0x400E00BC)

#define AT91C_CS3_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E00B8)

#define AT91C_CS3_SETUP   (AT91_CAST(AT91_REG *) 0x400E00AC)

#define AT91C_CS3_CYCLE   (AT91_CAST(AT91_REG *) 0x400E00B4)

#define AT91C_CS3_PULSE   (AT91_CAST(AT91_REG *) 0x400E00B0)

#define AT91C_NFC_MODE   (AT91_CAST(AT91_REG *) 0x400E010C)

#define AT91C_NFC_CYCLE   (AT91_CAST(AT91_REG *) 0x400E0104)

#define AT91C_NFC_PULSE   (AT91_CAST(AT91_REG *) 0x400E0100)

#define AT91C_NFC_SETUP   (AT91_CAST(AT91_REG *) 0x400E00FC)

#define AT91C_NFC_TIMINGS   (AT91_CAST(AT91_REG *) 0x400E0108)

#define AT91C_HSMC4_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E01F0)

#define AT91C_HSMC4_ECCPR6   (AT91_CAST(AT91_REG *) 0x400E0048)

#define AT91C_HSMC4_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E01EC)

#define AT91C_HSMC4_ECCPR11   (AT91_CAST(AT91_REG *) 0x400E005C)

#define AT91C_HSMC4_SR   (AT91_CAST(AT91_REG *) 0x400E0008)

#define AT91C_HSMC4_IMR   (AT91_CAST(AT91_REG *) 0x400E0014)

#define AT91C_HSMC4_WPSR   (AT91_CAST(AT91_REG *) 0x400E01E8)

#define AT91C_HSMC4_BANK   (AT91_CAST(AT91_REG *) 0x400E001C)

#define AT91C_HSMC4_ECCPR8   (AT91_CAST(AT91_REG *) 0x400E0050)

#define AT91C_HSMC4_WPCR   (AT91_CAST(AT91_REG *) 0x400E01E4)

#define AT91C_HSMC4_ECCPR2   (AT91_CAST(AT91_REG *) 0x400E0038)

#define AT91C_HSMC4_ECCPR1   (AT91_CAST(AT91_REG *) 0x400E0030)

#define AT91C_HSMC4_ECCSR2   (AT91_CAST(AT91_REG *) 0x400E0034)

#define AT91C_HSMC4_OCMS   (AT91_CAST(AT91_REG *) 0x400E0110)

#define AT91C_HSMC4_ECCPR9   (AT91_CAST(AT91_REG *) 0x400E0054)

#define AT91C_HSMC4_DUMMY   (AT91_CAST(AT91_REG *) 0x400E0200)

#define AT91C_HSMC4_ECCPR5   (AT91_CAST(AT91_REG *) 0x400E0044)

#define AT91C_HSMC4_ECCCR   (AT91_CAST(AT91_REG *) 0x400E0020)

#define AT91C_HSMC4_KEY2   (AT91_CAST(AT91_REG *) 0x400E0118)

#define AT91C_HSMC4_IER   (AT91_CAST(AT91_REG *) 0x400E000C)

#define AT91C_HSMC4_ECCSR1   (AT91_CAST(AT91_REG *) 0x400E0028)

#define AT91C_HSMC4_IDR   (AT91_CAST(AT91_REG *) 0x400E0010)

#define AT91C_HSMC4_ECCPR0   (AT91_CAST(AT91_REG *) 0x400E002C)

#define AT91C_HSMC4_FEATURES   (AT91_CAST(AT91_REG *) 0x400E01F8)

#define AT91C_HSMC4_ECCPR7   (AT91_CAST(AT91_REG *) 0x400E004C)

#define AT91C_HSMC4_ECCPR12   (AT91_CAST(AT91_REG *) 0x400E0060)

#define AT91C_HSMC4_ECCPR10   (AT91_CAST(AT91_REG *) 0x400E0058)

#define AT91C_HSMC4_KEY1   (AT91_CAST(AT91_REG *) 0x400E0114)

#define AT91C_HSMC4_VER   (AT91_CAST(AT91_REG *) 0x400E01FC)

#define AT91C_HSMC4_Eccpr15   (AT91_CAST(AT91_REG *) 0x400E006C)

#define AT91C_HSMC4_ECCPR4   (AT91_CAST(AT91_REG *) 0x400E0040)

#define AT91C_HSMC4_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E01F4)

#define AT91C_HSMC4_ECCCMD   (AT91_CAST(AT91_REG *) 0x400E0024)

#define AT91C_HSMC4_ADDR   (AT91_CAST(AT91_REG *) 0x400E0018)

#define AT91C_HSMC4_ECCPR3   (AT91_CAST(AT91_REG *) 0x400E003C)

#define AT91C_HSMC4_CFG   (AT91_CAST(AT91_REG *) 0x400E0000)

#define AT91C_HSMC4_CTRL   (AT91_CAST(AT91_REG *) 0x400E0004)

#define AT91C_HSMC4_ECCPR13   (AT91_CAST(AT91_REG *) 0x400E0064)

#define AT91C_HSMC4_ECCPR14   (AT91_CAST(AT91_REG *) 0x400E0068)

#define AT91C_MATRIX_SFR2   (AT91_CAST(AT91_REG *) 0x400E0318)

#define AT91C_MATRIX_SFR3   (AT91_CAST(AT91_REG *) 0x400E031C)

#define AT91C_MATRIX_SCFG8   (AT91_CAST(AT91_REG *) 0x400E0260)

#define AT91C_MATRIX_MCFG2   (AT91_CAST(AT91_REG *) 0x400E0208)

#define AT91C_MATRIX_MCFG7   (AT91_CAST(AT91_REG *) 0x400E021C)

#define AT91C_MATRIX_SCFG3   (AT91_CAST(AT91_REG *) 0x400E024C)

#define AT91C_MATRIX_SCFG0   (AT91_CAST(AT91_REG *) 0x400E0240)

#define AT91C_MATRIX_SFR12   (AT91_CAST(AT91_REG *) 0x400E0340)

#define AT91C_MATRIX_SCFG1   (AT91_CAST(AT91_REG *) 0x400E0244)

#define AT91C_MATRIX_SFR8   (AT91_CAST(AT91_REG *) 0x400E0330)

#define AT91C_MATRIX_VER   (AT91_CAST(AT91_REG *) 0x400E03FC)

#define AT91C_MATRIX_SFR13   (AT91_CAST(AT91_REG *) 0x400E0344)

#define AT91C_MATRIX_SFR5   (AT91_CAST(AT91_REG *) 0x400E0324)

#define AT91C_MATRIX_MCFG0   (AT91_CAST(AT91_REG *) 0x400E0200)

#define AT91C_MATRIX_SCFG6   (AT91_CAST(AT91_REG *) 0x400E0258)

#define AT91C_MATRIX_SFR14   (AT91_CAST(AT91_REG *) 0x400E0348)

#define AT91C_MATRIX_SFR1   (AT91_CAST(AT91_REG *) 0x400E0314)

#define AT91C_MATRIX_SFR15   (AT91_CAST(AT91_REG *) 0x400E034C)

#define AT91C_MATRIX_SFR6   (AT91_CAST(AT91_REG *) 0x400E0328)

#define AT91C_MATRIX_SFR11   (AT91_CAST(AT91_REG *) 0x400E033C)

#define AT91C_MATRIX_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E03F4)

#define AT91C_MATRIX_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E03EC)

#define AT91C_MATRIX_MCFG5   (AT91_CAST(AT91_REG *) 0x400E0214)

#define AT91C_MATRIX_SFR9   (AT91_CAST(AT91_REG *) 0x400E0334)

#define AT91C_MATRIX_MCFG3   (AT91_CAST(AT91_REG *) 0x400E020C)

#define AT91C_MATRIX_SCFG4   (AT91_CAST(AT91_REG *) 0x400E0250)

#define AT91C_MATRIX_MCFG1   (AT91_CAST(AT91_REG *) 0x400E0204)

#define AT91C_MATRIX_SCFG7   (AT91_CAST(AT91_REG *) 0x400E025C)

#define AT91C_MATRIX_SFR10   (AT91_CAST(AT91_REG *) 0x400E0338)

#define AT91C_MATRIX_SCFG2   (AT91_CAST(AT91_REG *) 0x400E0248)

#define AT91C_MATRIX_SFR7   (AT91_CAST(AT91_REG *) 0x400E032C)

#define AT91C_MATRIX_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E03F0)

#define AT91C_MATRIX_MCFG4   (AT91_CAST(AT91_REG *) 0x400E0210)

#define AT91C_MATRIX_SFR0   (AT91_CAST(AT91_REG *) 0x400E0310)

#define AT91C_MATRIX_FEATURES   (AT91_CAST(AT91_REG *) 0x400E03F8)

#define AT91C_MATRIX_SCFG5   (AT91_CAST(AT91_REG *) 0x400E0254)

#define AT91C_MATRIX_MCFG6   (AT91_CAST(AT91_REG *) 0x400E0218)

#define AT91C_MATRIX_SCFG9   (AT91_CAST(AT91_REG *) 0x400E0264)

#define AT91C_MATRIX_SFR4   (AT91_CAST(AT91_REG *) 0x400E0320)

#define AT91C_NVIC_MMAR   (AT91_CAST(AT91_REG *) 0xE000ED34)

#define AT91C_NVIC_STIR   (AT91_CAST(AT91_REG *) 0xE000EF00)

#define AT91C_NVIC_MMFR2   (AT91_CAST(AT91_REG *) 0xE000ED58)

#define AT91C_NVIC_CPUID   (AT91_CAST(AT91_REG *) 0xE000ED00)

#define AT91C_NVIC_DFSR   (AT91_CAST(AT91_REG *) 0xE000ED30)

#define AT91C_NVIC_HAND4PR   (AT91_CAST(AT91_REG *) 0xE000ED18)

#define AT91C_NVIC_HFSR   (AT91_CAST(AT91_REG *) 0xE000ED2C)

#define AT91C_NVIC_PID6   (AT91_CAST(AT91_REG *) 0xE000EFD8)

#define AT91C_NVIC_PFR0   (AT91_CAST(AT91_REG *) 0xE000ED40)

#define AT91C_NVIC_VTOFFR   (AT91_CAST(AT91_REG *) 0xE000ED08)

#define AT91C_NVIC_ISPR   (AT91_CAST(AT91_REG *) 0xE000E200)

#define AT91C_NVIC_PID0   (AT91_CAST(AT91_REG *) 0xE000EFE0)

#define AT91C_NVIC_PID7   (AT91_CAST(AT91_REG *) 0xE000EFDC)

#define AT91C_NVIC_STICKRVR   (AT91_CAST(AT91_REG *) 0xE000E014)

#define AT91C_NVIC_PID2   (AT91_CAST(AT91_REG *) 0xE000EFE8)

#define AT91C_NVIC_ISAR0   (AT91_CAST(AT91_REG *) 0xE000ED60)

#define AT91C_NVIC_SCR   (AT91_CAST(AT91_REG *) 0xE000ED10)

#define AT91C_NVIC_PID4   (AT91_CAST(AT91_REG *) 0xE000EFD0)

#define AT91C_NVIC_ISAR2   (AT91_CAST(AT91_REG *) 0xE000ED68)

#define AT91C_NVIC_ISER   (AT91_CAST(AT91_REG *) 0xE000E100)

#define AT91C_NVIC_IPR   (AT91_CAST(AT91_REG *) 0xE000E400)

#define AT91C_NVIC_AIRCR   (AT91_CAST(AT91_REG *) 0xE000ED0C)

#define AT91C_NVIC_CID2   (AT91_CAST(AT91_REG *) 0xE000EFF8)

#define AT91C_NVIC_ICPR   (AT91_CAST(AT91_REG *) 0xE000E280)

#define AT91C_NVIC_CID3   (AT91_CAST(AT91_REG *) 0xE000EFFC)

#define AT91C_NVIC_CFSR   (AT91_CAST(AT91_REG *) 0xE000ED28)

#define AT91C_NVIC_AFR0   (AT91_CAST(AT91_REG *) 0xE000ED4C)

#define AT91C_NVIC_ICSR   (AT91_CAST(AT91_REG *) 0xE000ED04)

#define AT91C_NVIC_CCR   (AT91_CAST(AT91_REG *) 0xE000ED14)

#define AT91C_NVIC_CID0   (AT91_CAST(AT91_REG *) 0xE000EFF0)

#define AT91C_NVIC_ISAR1   (AT91_CAST(AT91_REG *) 0xE000ED64)

#define AT91C_NVIC_STICKCVR   (AT91_CAST(AT91_REG *) 0xE000E018)

#define AT91C_NVIC_STICKCSR   (AT91_CAST(AT91_REG *) 0xE000E010)

#define AT91C_NVIC_CID1   (AT91_CAST(AT91_REG *) 0xE000EFF4)

#define AT91C_NVIC_DFR0   (AT91_CAST(AT91_REG *) 0xE000ED48)

#define AT91C_NVIC_MMFR3   (AT91_CAST(AT91_REG *) 0xE000ED5C)

#define AT91C_NVIC_MMFR0   (AT91_CAST(AT91_REG *) 0xE000ED50)

#define AT91C_NVIC_STICKCALVR   (AT91_CAST(AT91_REG *) 0xE000E01C)

#define AT91C_NVIC_PID1   (AT91_CAST(AT91_REG *) 0xE000EFE4)

#define AT91C_NVIC_HAND12PR   (AT91_CAST(AT91_REG *) 0xE000ED20)

#define AT91C_NVIC_MMFR1   (AT91_CAST(AT91_REG *) 0xE000ED54)

#define AT91C_NVIC_AFSR   (AT91_CAST(AT91_REG *) 0xE000ED3C)

#define AT91C_NVIC_HANDCSR   (AT91_CAST(AT91_REG *) 0xE000ED24)

#define AT91C_NVIC_ISAR4   (AT91_CAST(AT91_REG *) 0xE000ED70)

#define AT91C_NVIC_ABR   (AT91_CAST(AT91_REG *) 0xE000E300)

#define AT91C_NVIC_PFR1   (AT91_CAST(AT91_REG *) 0xE000ED44)

#define AT91C_NVIC_PID5   (AT91_CAST(AT91_REG *) 0xE000EFD4)

#define AT91C_NVIC_ICTR   (AT91_CAST(AT91_REG *) 0xE000E004)

#define AT91C_NVIC_ICER   (AT91_CAST(AT91_REG *) 0xE000E180)

#define AT91C_NVIC_PID3   (AT91_CAST(AT91_REG *) 0xE000EFEC)

#define AT91C_NVIC_ISAR3   (AT91_CAST(AT91_REG *) 0xE000ED6C)

#define AT91C_NVIC_HAND8PR   (AT91_CAST(AT91_REG *) 0xE000ED1C)

#define AT91C_NVIC_BFAR   (AT91_CAST(AT91_REG *) 0xE000ED38)

#define AT91C_MPU_REG_BASE_ADDR3   (AT91_CAST(AT91_REG *) 0xE000EDB4)

#define AT91C_MPU_REG_NB   (AT91_CAST(AT91_REG *) 0xE000ED98)

#define AT91C_MPU_ATTR_SIZE1   (AT91_CAST(AT91_REG *) 0xE000EDA8)

#define AT91C_MPU_REG_BASE_ADDR1   (AT91_CAST(AT91_REG *) 0xE000EDA4)

#define AT91C_MPU_ATTR_SIZE3   (AT91_CAST(AT91_REG *) 0xE000EDB8)

#define AT91C_MPU_CTRL   (AT91_CAST(AT91_REG *) 0xE000ED94)

#define AT91C_MPU_ATTR_SIZE2   (AT91_CAST(AT91_REG *) 0xE000EDB0)

#define AT91C_MPU_REG_BASE_ADDR   (AT91_CAST(AT91_REG *) 0xE000ED9C)

#define AT91C_MPU_REG_BASE_ADDR2   (AT91_CAST(AT91_REG *) 0xE000EDAC)

#define AT91C_MPU_ATTR_SIZE   (AT91_CAST(AT91_REG *) 0xE000EDA0)

#define AT91C_MPU_TYPE   (AT91_CAST(AT91_REG *) 0xE000ED90)

#define AT91C_CM3_SHCSR   (AT91_CAST(AT91_REG *) 0xE000ED24)

#define AT91C_CM3_CCR   (AT91_CAST(AT91_REG *) 0xE000ED14)

#define AT91C_CM3_ICSR   (AT91_CAST(AT91_REG *) 0xE000ED04)

#define AT91C_CM3_CPUID   (AT91_CAST(AT91_REG *) 0xE000ED00)

#define AT91C_CM3_SCR   (AT91_CAST(AT91_REG *) 0xE000ED10)

#define AT91C_CM3_AIRCR   (AT91_CAST(AT91_REG *) 0xE000ED0C)

#define AT91C_CM3_SHPR   (AT91_CAST(AT91_REG *) 0xE000ED18)

#define AT91C_CM3_VTOR   (AT91_CAST(AT91_REG *) 0xE000ED08)

#define AT91C_DBGU_TPR   (AT91_CAST(AT91_REG *) 0x400E0708)

#define AT91C_DBGU_PTCR   (AT91_CAST(AT91_REG *) 0x400E0720)

#define AT91C_DBGU_TNCR   (AT91_CAST(AT91_REG *) 0x400E071C)

#define AT91C_DBGU_PTSR   (AT91_CAST(AT91_REG *) 0x400E0724)

#define AT91C_DBGU_RNCR   (AT91_CAST(AT91_REG *) 0x400E0714)

#define AT91C_DBGU_RPR   (AT91_CAST(AT91_REG *) 0x400E0700)

#define AT91C_DBGU_TCR   (AT91_CAST(AT91_REG *) 0x400E070C)

#define AT91C_DBGU_RNPR   (AT91_CAST(AT91_REG *) 0x400E0710)

#define AT91C_DBGU_TNPR   (AT91_CAST(AT91_REG *) 0x400E0718)

#define AT91C_DBGU_RCR   (AT91_CAST(AT91_REG *) 0x400E0704)

#define AT91C_DBGU_CR   (AT91_CAST(AT91_REG *) 0x400E0600)

#define AT91C_DBGU_IDR   (AT91_CAST(AT91_REG *) 0x400E060C)

#define AT91C_DBGU_CIDR   (AT91_CAST(AT91_REG *) 0x400E0740)

#define AT91C_DBGU_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E06F4)

#define AT91C_DBGU_FEATURES   (AT91_CAST(AT91_REG *) 0x400E06F8)

#define AT91C_DBGU_FNTR   (AT91_CAST(AT91_REG *) 0x400E0648)

#define AT91C_DBGU_RHR   (AT91_CAST(AT91_REG *) 0x400E0618)

#define AT91C_DBGU_THR   (AT91_CAST(AT91_REG *) 0x400E061C)

#define AT91C_DBGU_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E06EC)

#define AT91C_DBGU_MR   (AT91_CAST(AT91_REG *) 0x400E0604)

#define AT91C_DBGU_IER   (AT91_CAST(AT91_REG *) 0x400E0608)

#define AT91C_DBGU_BRGR   (AT91_CAST(AT91_REG *) 0x400E0620)

#define AT91C_DBGU_CSR   (AT91_CAST(AT91_REG *) 0x400E0614)

#define AT91C_DBGU_VER   (AT91_CAST(AT91_REG *) 0x400E06FC)

#define AT91C_DBGU_IMR   (AT91_CAST(AT91_REG *) 0x400E0610)

#define AT91C_DBGU_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E06F0)

#define AT91C_DBGU_EXID   (AT91_CAST(AT91_REG *) 0x400E0744)

#define AT91C_PIOA_PDR   (AT91_CAST(AT91_REG *) 0x400E0C04)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E0CD8)

#define AT91C_PIOA_KIMR   (AT91_CAST(AT91_REG *) 0x400E0D38)

#define AT91C_PIOA_LSR   (AT91_CAST(AT91_REG *) 0x400E0CC4)

#define AT91C_PIOA_IFSR   (AT91_CAST(AT91_REG *) 0x400E0C28)

Referenced by GpioPinConfigGet().

#define AT91C_PIOA_KKRR   (AT91_CAST(AT91_REG *) 0x400E0D44)

#define AT91C_PIOA_ODR   (AT91_CAST(AT91_REG *) 0x400E0C14)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E0C80)

#define AT91C_PIOA_PER   (AT91_CAST(AT91_REG *) 0x400E0C00)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_VER   (AT91_CAST(AT91_REG *) 0x400E0CFC)

#define AT91C_PIOA_OWSR   (AT91_CAST(AT91_REG *) 0x400E0CA8)

#define AT91C_PIOA_KSR   (AT91_CAST(AT91_REG *) 0x400E0D3C)

#define AT91C_PIOA_IMR   (AT91_CAST(AT91_REG *) 0x400E0C48)

#define AT91C_PIOA_OWDR   (AT91_CAST(AT91_REG *) 0x400E0CA4)

#define AT91C_PIOA_MDSR   (AT91_CAST(AT91_REG *) 0x400E0C58)

Referenced by GpioPinConfigGet().

#define AT91C_PIOA_IFDR   (AT91_CAST(AT91_REG *) 0x400E0C24)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_AIMDR   (AT91_CAST(AT91_REG *) 0x400E0CB4)

#define AT91C_PIOA_CODR   (AT91_CAST(AT91_REG *) 0x400E0C34)

Referenced by GpioPinSetLow(), and GpioPortSetLow().

#define AT91C_PIOA_SCDR   (AT91_CAST(AT91_REG *) 0x400E0C8C)

#define AT91C_PIOA_KIER   (AT91_CAST(AT91_REG *) 0x400E0D30)

#define AT91C_PIOA_REHLSR   (AT91_CAST(AT91_REG *) 0x400E0CD4)

#define AT91C_PIOA_ISR   (AT91_CAST(AT91_REG *) 0x400E0C4C)

#define PIOA_ISR   (AT91_CAST(AT91_REG *) 0x400E0C4C)

#define AT91C_PIOA_ESR   (AT91_CAST(AT91_REG *) 0x400E0CC0)

#define AT91C_PIOA_PPUDR   (AT91_CAST(AT91_REG *) 0x400E0C60)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_MDDR   (AT91_CAST(AT91_REG *) 0x400E0C54)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_PSR   (AT91_CAST(AT91_REG *) 0x400E0C08)

Referenced by GpioPinConfigGet().

#define AT91C_PIOA_PDSR   (AT91_CAST(AT91_REG *) 0x400E0C3C)

Referenced by GpioPinGet(), and GpioPortGet().

#define AT91C_PIOA_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E0C88)

#define AT91C_PIOA_FELLSR   (AT91_CAST(AT91_REG *) 0x400E0CD0)

#define AT91C_PIOA_PPUSR   (AT91_CAST(AT91_REG *) 0x400E0C68)

Referenced by GpioPinConfigGet().

#define AT91C_PIOA_OER   (AT91_CAST(AT91_REG *) 0x400E0C10)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_OSR   (AT91_CAST(AT91_REG *) 0x400E0C18)

Referenced by GpioPinConfigGet().

#define AT91C_PIOA_KKPR   (AT91_CAST(AT91_REG *) 0x400E0D40)

#define AT91C_PIOA_AIMMR   (AT91_CAST(AT91_REG *) 0x400E0CB8)

#define AT91C_PIOA_KRCR   (AT91_CAST(AT91_REG *) 0x400E0D24)

#define AT91C_PIOA_IER   (AT91_CAST(AT91_REG *) 0x400E0C40)

#define AT91C_PIOA_KER   (AT91_CAST(AT91_REG *) 0x400E0D20)

#define AT91C_PIOA_PPUER   (AT91_CAST(AT91_REG *) 0x400E0C64)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_KIDR   (AT91_CAST(AT91_REG *) 0x400E0D34)

#define AT91C_PIOA_ABSR   (AT91_CAST(AT91_REG *) 0x400E0C70)

#define AT91C_PIOA_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E0CE0)

#define AT91C_PIOA_DIFSR   (AT91_CAST(AT91_REG *) 0x400E0C84)

#define AT91C_PIOA_MDER   (AT91_CAST(AT91_REG *) 0x400E0C50)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_AIMER   (AT91_CAST(AT91_REG *) 0x400E0CB0)

#define AT91C_PIOA_ELSR   (AT91_CAST(AT91_REG *) 0x400E0CC8)

#define AT91C_PIOA_IFER   (AT91_CAST(AT91_REG *) 0x400E0C20)

Referenced by GpioPortConfigSet().

#define AT91C_PIOA_KDR   (AT91_CAST(AT91_REG *) 0x400E0D28)

#define AT91C_PIOA_IDR   (AT91_CAST(AT91_REG *) 0x400E0C44)

#define AT91C_PIOA_OWER   (AT91_CAST(AT91_REG *) 0x400E0CA0)

#define AT91C_PIOA_ODSR   (AT91_CAST(AT91_REG *) 0x400E0C38)

#define AT91C_PIOA_SODR   (AT91_CAST(AT91_REG *) 0x400E0C30)

Referenced by GpioPinSetHigh(), and GpioPortSetHigh().

#define AT91C_PIOB_KIDR   (AT91_CAST(AT91_REG *) 0x400E0F34)

#define AT91C_PIOB_OWSR   (AT91_CAST(AT91_REG *) 0x400E0EA8)

#define AT91C_PIOB_PSR   (AT91_CAST(AT91_REG *) 0x400E0E08)

Referenced by GpioPinConfigGet().

#define AT91C_PIOB_MDER   (AT91_CAST(AT91_REG *) 0x400E0E50)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_ODR   (AT91_CAST(AT91_REG *) 0x400E0E14)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_IDR   (AT91_CAST(AT91_REG *) 0x400E0E44)

#define AT91C_PIOB_AIMER   (AT91_CAST(AT91_REG *) 0x400E0EB0)

#define AT91C_PIOB_DIFSR   (AT91_CAST(AT91_REG *) 0x400E0E84)

#define AT91C_PIOB_PDR   (AT91_CAST(AT91_REG *) 0x400E0E04)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_REHLSR   (AT91_CAST(AT91_REG *) 0x400E0ED4)

#define AT91C_PIOB_PDSR   (AT91_CAST(AT91_REG *) 0x400E0E3C)

Referenced by GpioPinGet(), and GpioPortGet().

#define AT91C_PIOB_PPUDR   (AT91_CAST(AT91_REG *) 0x400E0E60)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_LSR   (AT91_CAST(AT91_REG *) 0x400E0EC4)

#define AT91C_PIOB_OWDR   (AT91_CAST(AT91_REG *) 0x400E0EA4)

#define AT91C_PIOB_FELLSR   (AT91_CAST(AT91_REG *) 0x400E0ED0)

#define AT91C_PIOB_IFER   (AT91_CAST(AT91_REG *) 0x400E0E20)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_ABSR   (AT91_CAST(AT91_REG *) 0x400E0E70)

#define AT91C_PIOB_KIMR   (AT91_CAST(AT91_REG *) 0x400E0F38)

#define AT91C_PIOB_KKPR   (AT91_CAST(AT91_REG *) 0x400E0F40)

#define AT91C_PIOB_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E0ED8)

#define AT91C_PIOB_AIMDR   (AT91_CAST(AT91_REG *) 0x400E0EB4)

#define AT91C_PIOB_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E0E80)

#define AT91C_PIOB_VER   (AT91_CAST(AT91_REG *) 0x400E0EFC)

#define AT91C_PIOB_PER   (AT91_CAST(AT91_REG *) 0x400E0E00)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_ELSR   (AT91_CAST(AT91_REG *) 0x400E0EC8)

#define AT91C_PIOB_IMR   (AT91_CAST(AT91_REG *) 0x400E0E48)

#define AT91C_PIOB_PPUSR   (AT91_CAST(AT91_REG *) 0x400E0E68)

Referenced by GpioPinConfigGet().

#define AT91C_PIOB_SCDR   (AT91_CAST(AT91_REG *) 0x400E0E8C)

#define AT91C_PIOB_KSR   (AT91_CAST(AT91_REG *) 0x400E0F3C)

#define AT91C_PIOB_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E0E88)

#define AT91C_PIOB_ESR   (AT91_CAST(AT91_REG *) 0x400E0EC0)

#define AT91C_PIOB_ODSR   (AT91_CAST(AT91_REG *) 0x400E0E38)

#define AT91C_PIOB_IFDR   (AT91_CAST(AT91_REG *) 0x400E0E24)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_SODR   (AT91_CAST(AT91_REG *) 0x400E0E30)

Referenced by GpioPinSetHigh(), and GpioPortSetHigh().

#define AT91C_PIOB_IER   (AT91_CAST(AT91_REG *) 0x400E0E40)

#define AT91C_PIOB_MDSR   (AT91_CAST(AT91_REG *) 0x400E0E58)

Referenced by GpioPinConfigGet().

#define AT91C_PIOB_ISR   (AT91_CAST(AT91_REG *) 0x400E0E4C)

#define PIOB_ISR   (AT91_CAST(AT91_REG *) 0x400E0E4C)

#define AT91C_PIOB_IFSR   (AT91_CAST(AT91_REG *) 0x400E0E28)

Referenced by GpioPinConfigGet().

#define AT91C_PIOB_KER   (AT91_CAST(AT91_REG *) 0x400E0F20)

#define AT91C_PIOB_KKRR   (AT91_CAST(AT91_REG *) 0x400E0F44)

#define AT91C_PIOB_PPUER   (AT91_CAST(AT91_REG *) 0x400E0E64)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E0EE0)

#define AT91C_PIOB_OWER   (AT91_CAST(AT91_REG *) 0x400E0EA0)

#define AT91C_PIOB_KIER   (AT91_CAST(AT91_REG *) 0x400E0F30)

#define AT91C_PIOB_MDDR   (AT91_CAST(AT91_REG *) 0x400E0E54)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_KRCR   (AT91_CAST(AT91_REG *) 0x400E0F24)

#define AT91C_PIOB_CODR   (AT91_CAST(AT91_REG *) 0x400E0E34)

Referenced by GpioPinSetLow(), and GpioPortSetLow().

#define AT91C_PIOB_KDR   (AT91_CAST(AT91_REG *) 0x400E0F28)

#define AT91C_PIOB_AIMMR   (AT91_CAST(AT91_REG *) 0x400E0EB8)

#define AT91C_PIOB_OER   (AT91_CAST(AT91_REG *) 0x400E0E10)

Referenced by GpioPortConfigSet().

#define AT91C_PIOB_OSR   (AT91_CAST(AT91_REG *) 0x400E0E18)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_FELLSR   (AT91_CAST(AT91_REG *) 0x400E10D0)

#define AT91C_PIOC_FRLHSR   (AT91_CAST(AT91_REG *) 0x400E10D8)

#define AT91C_PIOC_MDDR   (AT91_CAST(AT91_REG *) 0x400E1054)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_IFDGSR   (AT91_CAST(AT91_REG *) 0x400E1088)

#define AT91C_PIOC_ABSR   (AT91_CAST(AT91_REG *) 0x400E1070)

#define AT91C_PIOC_KIMR   (AT91_CAST(AT91_REG *) 0x400E1138)

#define AT91C_PIOC_KRCR   (AT91_CAST(AT91_REG *) 0x400E1124)

#define AT91C_PIOC_ODSR   (AT91_CAST(AT91_REG *) 0x400E1038)

#define AT91C_PIOC_OSR   (AT91_CAST(AT91_REG *) 0x400E1018)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_IFER   (AT91_CAST(AT91_REG *) 0x400E1020)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_KKPR   (AT91_CAST(AT91_REG *) 0x400E1140)

#define AT91C_PIOC_MDSR   (AT91_CAST(AT91_REG *) 0x400E1058)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_IFDR   (AT91_CAST(AT91_REG *) 0x400E1024)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_MDER   (AT91_CAST(AT91_REG *) 0x400E1050)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_SCDR   (AT91_CAST(AT91_REG *) 0x400E108C)

#define AT91C_PIOC_SCIFSR   (AT91_CAST(AT91_REG *) 0x400E1080)

#define AT91C_PIOC_IER   (AT91_CAST(AT91_REG *) 0x400E1040)

#define AT91C_PIOC_KDR   (AT91_CAST(AT91_REG *) 0x400E1128)

#define AT91C_PIOC_OWDR   (AT91_CAST(AT91_REG *) 0x400E10A4)

#define AT91C_PIOC_IFSR   (AT91_CAST(AT91_REG *) 0x400E1028)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_ISR   (AT91_CAST(AT91_REG *) 0x400E104C)

#define PIOC_ISR   (AT91_CAST(AT91_REG *) 0x400E104C)

#define AT91C_PIOC_PPUDR   (AT91_CAST(AT91_REG *) 0x400E1060)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_PDSR   (AT91_CAST(AT91_REG *) 0x400E103C)

Referenced by GpioPinGet(), and GpioPortGet().

#define AT91C_PIOC_KKRR   (AT91_CAST(AT91_REG *) 0x400E1144)

#define AT91C_PIOC_AIMDR   (AT91_CAST(AT91_REG *) 0x400E10B4)

#define AT91C_PIOC_LSR   (AT91_CAST(AT91_REG *) 0x400E10C4)

#define AT91C_PIOC_PPUER   (AT91_CAST(AT91_REG *) 0x400E1064)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_AIMER   (AT91_CAST(AT91_REG *) 0x400E10B0)

#define AT91C_PIOC_OER   (AT91_CAST(AT91_REG *) 0x400E1010)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_CODR   (AT91_CAST(AT91_REG *) 0x400E1034)

Referenced by GpioPinSetLow(), and GpioPortSetLow().

#define AT91C_PIOC_AIMMR   (AT91_CAST(AT91_REG *) 0x400E10B8)

#define AT91C_PIOC_OWER   (AT91_CAST(AT91_REG *) 0x400E10A0)

#define AT91C_PIOC_VER   (AT91_CAST(AT91_REG *) 0x400E10FC)

#define AT91C_PIOC_IMR   (AT91_CAST(AT91_REG *) 0x400E1048)

#define AT91C_PIOC_PPUSR   (AT91_CAST(AT91_REG *) 0x400E1068)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_IDR   (AT91_CAST(AT91_REG *) 0x400E1044)

#define AT91C_PIOC_DIFSR   (AT91_CAST(AT91_REG *) 0x400E1084)

#define AT91C_PIOC_KIDR   (AT91_CAST(AT91_REG *) 0x400E1134)

#define AT91C_PIOC_KSR   (AT91_CAST(AT91_REG *) 0x400E113C)

#define AT91C_PIOC_REHLSR   (AT91_CAST(AT91_REG *) 0x400E10D4)

#define AT91C_PIOC_ESR   (AT91_CAST(AT91_REG *) 0x400E10C0)

#define AT91C_PIOC_KIER   (AT91_CAST(AT91_REG *) 0x400E1130)

#define AT91C_PIOC_ELSR   (AT91_CAST(AT91_REG *) 0x400E10C8)

#define AT91C_PIOC_SODR   (AT91_CAST(AT91_REG *) 0x400E1030)

Referenced by GpioPinSetHigh(), and GpioPortSetHigh().

#define AT91C_PIOC_PSR   (AT91_CAST(AT91_REG *) 0x400E1008)

Referenced by GpioPinConfigGet().

#define AT91C_PIOC_KER   (AT91_CAST(AT91_REG *) 0x400E1120)

#define AT91C_PIOC_ODR   (AT91_CAST(AT91_REG *) 0x400E1014)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_OWSR   (AT91_CAST(AT91_REG *) 0x400E10A8)

#define AT91C_PIOC_PDR   (AT91_CAST(AT91_REG *) 0x400E1004)

Referenced by GpioPortConfigSet().

#define AT91C_PIOC_LOCKSR   (AT91_CAST(AT91_REG *) 0x400E10E0)

#define AT91C_PIOC_PER   (AT91_CAST(AT91_REG *) 0x400E1000)

Referenced by GpioPortConfigSet().

#define AT91C_PMC_PLLAR   (AT91_CAST(AT91_REG *) 0x400E0428)

#define AT91C_PMC_UCKR   (AT91_CAST(AT91_REG *) 0x400E041C)

#define AT91C_PMC_FSMR   (AT91_CAST(AT91_REG *) 0x400E0470)

#define AT91C_PMC_MCKR   (AT91_CAST(AT91_REG *) 0x400E0430)

#define AT91C_PMC_SCER   (AT91_CAST(AT91_REG *) 0x400E0400)

#define AT91C_PMC_PCSR   (AT91_CAST(AT91_REG *) 0x400E0418)

#define AT91C_PMC_MCFR   (AT91_CAST(AT91_REG *) 0x400E0424)

#define AT91C_PMC_FOCR   (AT91_CAST(AT91_REG *) 0x400E0478)

#define AT91C_PMC_FSPR   (AT91_CAST(AT91_REG *) 0x400E0474)

#define AT91C_PMC_SCSR   (AT91_CAST(AT91_REG *) 0x400E0408)

#define AT91C_PMC_IDR   (AT91_CAST(AT91_REG *) 0x400E0464)

#define AT91C_PMC_VER   (AT91_CAST(AT91_REG *) 0x400E04FC)

#define AT91C_PMC_IMR   (AT91_CAST(AT91_REG *) 0x400E046C)

#define AT91C_PMC_IPNAME2   (AT91_CAST(AT91_REG *) 0x400E04F4)

#define AT91C_PMC_SCDR   (AT91_CAST(AT91_REG *) 0x400E0404)

#define AT91C_PMC_PCKR   (AT91_CAST(AT91_REG *) 0x400E0440)

#define AT91C_PMC_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400E04EC)

#define AT91C_PMC_PCDR   (AT91_CAST(AT91_REG *) 0x400E0414)

#define AT91C_PMC_MOR   (AT91_CAST(AT91_REG *) 0x400E0420)

#define AT91C_PMC_SR   (AT91_CAST(AT91_REG *) 0x400E0468)

#define AT91C_PMC_IER   (AT91_CAST(AT91_REG *) 0x400E0460)

#define AT91C_PMC_IPNAME1   (AT91_CAST(AT91_REG *) 0x400E04F0)

#define AT91C_PMC_PCER   (AT91_CAST(AT91_REG *) 0x400E0410)

Referenced by GpioPortConfigSet().

#define AT91C_PMC_FEATURES   (AT91_CAST(AT91_REG *) 0x400E04F8)

#define AT91C_CKGR_PLLAR   (AT91_CAST(AT91_REG *) 0x400E0428)

#define AT91C_CKGR_UCKR   (AT91_CAST(AT91_REG *) 0x400E041C)

#define AT91C_CKGR_MOR   (AT91_CAST(AT91_REG *) 0x400E0420)

#define AT91C_CKGR_MCFR   (AT91_CAST(AT91_REG *) 0x400E0424)

#define AT91C_RSTC_VER   (AT91_CAST(AT91_REG *) 0x400E12FC)

#define AT91C_RSTC_RCR   (AT91_CAST(AT91_REG *) 0x400E1200)

#define AT91C_RSTC_RMR   (AT91_CAST(AT91_REG *) 0x400E1208)

#define AT91C_RSTC_RSR   (AT91_CAST(AT91_REG *) 0x400E1204)

#define AT91C_SUPC_CR   (AT91_CAST(AT91_REG *) 0x400E1210)

#define AT91C_SUPC_SMMR   (AT91_CAST(AT91_REG *) 0x400E1214)

#define AT91C_SUPC_MR   (AT91_CAST(AT91_REG *) 0x400E1218)

#define AT91C_SUPC_WUMR   (AT91_CAST(AT91_REG *) 0x400E121C)

#define AT91C_SUPC_WUIR   (AT91_CAST(AT91_REG *) 0x400E1220)

#define AT91C_SUPC_SR   (AT91_CAST(AT91_REG *) 0x400E1224)

#define AT91C_RTTC_RTVR   (AT91_CAST(AT91_REG *) 0x400E1238)

#define AT91C_RTTC_RTAR   (AT91_CAST(AT91_REG *) 0x400E1234)

#define AT91C_RTTC_RTMR   (AT91_CAST(AT91_REG *) 0x400E1230)

#define AT91C_RTTC_RTSR   (AT91_CAST(AT91_REG *) 0x400E123C)

#define AT91C_WDTC_WDSR   (AT91_CAST(AT91_REG *) 0x400E1258)

#define AT91C_WDTC_WDMR   (AT91_CAST(AT91_REG *) 0x400E1254)

#define AT91C_WDTC_WDCR   (AT91_CAST(AT91_REG *) 0x400E1250)

#define AT91C_RTC_IMR   (AT91_CAST(AT91_REG *) 0x400E1288)

#define AT91C_RTC_SCCR   (AT91_CAST(AT91_REG *) 0x400E127C)

#define AT91C_RTC_CALR   (AT91_CAST(AT91_REG *) 0x400E126C)

#define AT91C_RTC_MR   (AT91_CAST(AT91_REG *) 0x400E1264)

#define AT91C_RTC_TIMR   (AT91_CAST(AT91_REG *) 0x400E1268)

#define AT91C_RTC_CALALR   (AT91_CAST(AT91_REG *) 0x400E1274)

#define AT91C_RTC_VER   (AT91_CAST(AT91_REG *) 0x400E128C)

#define AT91C_RTC_CR   (AT91_CAST(AT91_REG *) 0x400E1260)

#define AT91C_RTC_IDR   (AT91_CAST(AT91_REG *) 0x400E1284)

#define AT91C_RTC_TIMALR   (AT91_CAST(AT91_REG *) 0x400E1270)

#define AT91C_RTC_IER   (AT91_CAST(AT91_REG *) 0x400E1280)

#define AT91C_RTC_SR   (AT91_CAST(AT91_REG *) 0x400E1278)

#define AT91C_ADC0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400AC0F4)

#define AT91C_ADC0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400AC0EC)

#define AT91C_ADC0_IDR   (AT91_CAST(AT91_REG *) 0x400AC028)

#define AT91C_ADC0_CHSR   (AT91_CAST(AT91_REG *) 0x400AC018)

#define AT91C_ADC0_FEATURES   (AT91_CAST(AT91_REG *) 0x400AC0F8)

#define AT91C_ADC0_CDR0   (AT91_CAST(AT91_REG *) 0x400AC030)

#define AT91C_ADC0_LCDR   (AT91_CAST(AT91_REG *) 0x400AC020)

#define AT91C_ADC0_EMR   (AT91_CAST(AT91_REG *) 0x400AC068)

#define AT91C_ADC0_CDR3   (AT91_CAST(AT91_REG *) 0x400AC03C)

#define AT91C_ADC0_CDR7   (AT91_CAST(AT91_REG *) 0x400AC04C)

#define AT91C_ADC0_SR   (AT91_CAST(AT91_REG *) 0x400AC01C)

#define AT91C_ADC0_ACR   (AT91_CAST(AT91_REG *) 0x400AC064)

#define AT91C_ADC0_CDR5   (AT91_CAST(AT91_REG *) 0x400AC044)

#define AT91C_ADC0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400AC0F0)

#define AT91C_ADC0_CDR6   (AT91_CAST(AT91_REG *) 0x400AC048)

#define AT91C_ADC0_MR   (AT91_CAST(AT91_REG *) 0x400AC004)

#define AT91C_ADC0_CDR1   (AT91_CAST(AT91_REG *) 0x400AC034)

#define AT91C_ADC0_CDR2   (AT91_CAST(AT91_REG *) 0x400AC038)

#define AT91C_ADC0_CDR4   (AT91_CAST(AT91_REG *) 0x400AC040)

#define AT91C_ADC0_CHER   (AT91_CAST(AT91_REG *) 0x400AC010)

#define AT91C_ADC0_VER   (AT91_CAST(AT91_REG *) 0x400AC0FC)

#define AT91C_ADC0_CHDR   (AT91_CAST(AT91_REG *) 0x400AC014)

#define AT91C_ADC0_CR   (AT91_CAST(AT91_REG *) 0x400AC000)

#define AT91C_ADC0_IMR   (AT91_CAST(AT91_REG *) 0x400AC02C)

#define AT91C_ADC0_IER   (AT91_CAST(AT91_REG *) 0x400AC024)

#define AT91C_ADC12B_CR   (AT91_CAST(AT91_REG *) 0x400A8000)

#define AT91C_ADC12B_MR   (AT91_CAST(AT91_REG *) 0x400A8004)

#define AT91C_ADC12B_CHER   (AT91_CAST(AT91_REG *) 0x400A8010)

#define AT91C_ADC12B_CHDR   (AT91_CAST(AT91_REG *) 0x400A8014)

#define AT91C_ADC12B_CHSR   (AT91_CAST(AT91_REG *) 0x400A8018)

#define AT91C_ADC12B_SR   (AT91_CAST(AT91_REG *) 0x400A801C)

#define AT91C_ADC12B_LCDR   (AT91_CAST(AT91_REG *) 0x400A8020)

#define AT91C_ADC12B_IER   (AT91_CAST(AT91_REG *) 0x400A8024)

#define AT91C_ADC12B_IDR   (AT91_CAST(AT91_REG *) 0x400A8028)

#define AT91C_ADC12B_IMR   (AT91_CAST(AT91_REG *) 0x400A802C)

#define AT91C_ADC12B_CDR   (AT91_CAST(AT91_REG *) 0x400A8030)

#define AT91C_ADC12B_ACR   (AT91_CAST(AT91_REG *) 0x400A8064)

#define AT91C_ADC12B_EMR   (AT91_CAST(AT91_REG *) 0x400A8068)

#define AT91C_TC0_IER   (AT91_CAST(AT91_REG *) 0x40080024)

#define AT91C_TC0_CV   (AT91_CAST(AT91_REG *) 0x40080010)

#define AT91C_TC0_RA   (AT91_CAST(AT91_REG *) 0x40080014)

#define AT91C_TC0_RB   (AT91_CAST(AT91_REG *) 0x40080018)

#define AT91C_TC0_IDR   (AT91_CAST(AT91_REG *) 0x40080028)

#define AT91C_TC0_SR   (AT91_CAST(AT91_REG *) 0x40080020)

#define AT91C_TC0_IMR   (AT91_CAST(AT91_REG *) 0x4008002C)

#define AT91C_TC0_CMR   (AT91_CAST(AT91_REG *) 0x40080004)

#define AT91C_TC0_RC   (AT91_CAST(AT91_REG *) 0x4008001C)

#define AT91C_TC0_CCR   (AT91_CAST(AT91_REG *) 0x40080000)

#define AT91C_TC1_SR   (AT91_CAST(AT91_REG *) 0x40080060)

#define AT91C_TC1_RA   (AT91_CAST(AT91_REG *) 0x40080054)

#define AT91C_TC1_IER   (AT91_CAST(AT91_REG *) 0x40080064)

#define AT91C_TC1_RB   (AT91_CAST(AT91_REG *) 0x40080058)

#define AT91C_TC1_IDR   (AT91_CAST(AT91_REG *) 0x40080068)

#define AT91C_TC1_CCR   (AT91_CAST(AT91_REG *) 0x40080040)

#define AT91C_TC1_IMR   (AT91_CAST(AT91_REG *) 0x4008006C)

#define AT91C_TC1_RC   (AT91_CAST(AT91_REG *) 0x4008005C)

#define AT91C_TC1_CMR   (AT91_CAST(AT91_REG *) 0x40080044)

#define AT91C_TC1_CV   (AT91_CAST(AT91_REG *) 0x40080050)

#define AT91C_TC2_RA   (AT91_CAST(AT91_REG *) 0x40080094)

#define AT91C_TC2_RB   (AT91_CAST(AT91_REG *) 0x40080098)

#define AT91C_TC2_CMR   (AT91_CAST(AT91_REG *) 0x40080084)

#define AT91C_TC2_SR   (AT91_CAST(AT91_REG *) 0x400800A0)

#define AT91C_TC2_CCR   (AT91_CAST(AT91_REG *) 0x40080080)

#define AT91C_TC2_IMR   (AT91_CAST(AT91_REG *) 0x400800AC)

#define AT91C_TC2_CV   (AT91_CAST(AT91_REG *) 0x40080090)

#define AT91C_TC2_RC   (AT91_CAST(AT91_REG *) 0x4008009C)

#define AT91C_TC2_IER   (AT91_CAST(AT91_REG *) 0x400800A4)

#define AT91C_TC2_IDR   (AT91_CAST(AT91_REG *) 0x400800A8)

#define AT91C_TCB0_BCR   (AT91_CAST(AT91_REG *) 0x400800C0)

#define AT91C_TCB0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400800F4)

#define AT91C_TCB0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400800F0)

#define AT91C_TCB0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400800EC)

#define AT91C_TCB0_FEATURES   (AT91_CAST(AT91_REG *) 0x400800F8)

#define AT91C_TCB0_BMR   (AT91_CAST(AT91_REG *) 0x400800C4)

#define AT91C_TCB0_VER   (AT91_CAST(AT91_REG *) 0x400800FC)

#define AT91C_TCB1_BCR   (AT91_CAST(AT91_REG *) 0x40080100)

#define AT91C_TCB1_VER   (AT91_CAST(AT91_REG *) 0x4008013C)

#define AT91C_TCB1_FEATURES   (AT91_CAST(AT91_REG *) 0x40080138)

#define AT91C_TCB1_IPNAME2   (AT91_CAST(AT91_REG *) 0x40080134)

#define AT91C_TCB1_BMR   (AT91_CAST(AT91_REG *) 0x40080104)

#define AT91C_TCB1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008012C)

#define AT91C_TCB1_IPNAME1   (AT91_CAST(AT91_REG *) 0x40080130)

#define AT91C_TCB2_FEATURES   (AT91_CAST(AT91_REG *) 0x40080178)

#define AT91C_TCB2_VER   (AT91_CAST(AT91_REG *) 0x4008017C)

#define AT91C_TCB2_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008016C)

#define AT91C_TCB2_IPNAME1   (AT91_CAST(AT91_REG *) 0x40080170)

#define AT91C_TCB2_IPNAME2   (AT91_CAST(AT91_REG *) 0x40080174)

#define AT91C_TCB2_BMR   (AT91_CAST(AT91_REG *) 0x40080144)

#define AT91C_TCB2_BCR   (AT91_CAST(AT91_REG *) 0x40080140)

#define AT91C_EFC0_FCR   (AT91_CAST(AT91_REG *) 0x400E0804)

#define AT91C_EFC0_FRR   (AT91_CAST(AT91_REG *) 0x400E080C)

#define AT91C_EFC0_FMR   (AT91_CAST(AT91_REG *) 0x400E0800)

#define AT91C_EFC0_FSR   (AT91_CAST(AT91_REG *) 0x400E0808)

#define AT91C_EFC0_FVR   (AT91_CAST(AT91_REG *) 0x400E0814)

#define AT91C_EFC1_FMR   (AT91_CAST(AT91_REG *) 0x400E0A00)

#define AT91C_EFC1_FVR   (AT91_CAST(AT91_REG *) 0x400E0A14)

#define AT91C_EFC1_FSR   (AT91_CAST(AT91_REG *) 0x400E0A08)

#define AT91C_EFC1_FCR   (AT91_CAST(AT91_REG *) 0x400E0A04)

#define AT91C_EFC1_FRR   (AT91_CAST(AT91_REG *) 0x400E0A0C)

#define AT91C_MCI0_DMA   (AT91_CAST(AT91_REG *) 0x40000050)

#define AT91C_MCI0_SDCR   (AT91_CAST(AT91_REG *) 0x4000000C)

#define AT91C_MCI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400000F0)

#define AT91C_MCI0_CSTOR   (AT91_CAST(AT91_REG *) 0x4000001C)

#define AT91C_MCI0_RDR   (AT91_CAST(AT91_REG *) 0x40000030)

#define AT91C_MCI0_CMDR   (AT91_CAST(AT91_REG *) 0x40000014)

#define AT91C_MCI0_IDR   (AT91_CAST(AT91_REG *) 0x40000048)

#define AT91C_MCI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400000EC)

#define AT91C_MCI0_WPCR   (AT91_CAST(AT91_REG *) 0x400000E4)

#define AT91C_MCI0_RSPR   (AT91_CAST(AT91_REG *) 0x40000020)

#define AT91C_MCI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400000F4)

#define AT91C_MCI0_CR   (AT91_CAST(AT91_REG *) 0x40000000)

#define AT91C_MCI0_IMR   (AT91_CAST(AT91_REG *) 0x4000004C)

#define AT91C_MCI0_WPSR   (AT91_CAST(AT91_REG *) 0x400000E8)

#define AT91C_MCI0_DTOR   (AT91_CAST(AT91_REG *) 0x40000008)

#define AT91C_MCI0_MR   (AT91_CAST(AT91_REG *) 0x40000004)

#define AT91C_MCI0_SR   (AT91_CAST(AT91_REG *) 0x40000040)

#define AT91C_MCI0_IER   (AT91_CAST(AT91_REG *) 0x40000044)

#define AT91C_MCI0_VER   (AT91_CAST(AT91_REG *) 0x400000FC)

#define AT91C_MCI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400000F8)

#define AT91C_MCI0_BLKR   (AT91_CAST(AT91_REG *) 0x40000018)

#define AT91C_MCI0_ARGR   (AT91_CAST(AT91_REG *) 0x40000010)

#define AT91C_MCI0_FIFO   (AT91_CAST(AT91_REG *) 0x40000200)

#define AT91C_MCI0_TDR   (AT91_CAST(AT91_REG *) 0x40000034)

#define AT91C_MCI0_CFG   (AT91_CAST(AT91_REG *) 0x40000054)

#define AT91C_TWI0_TNCR   (AT91_CAST(AT91_REG *) 0x4008411C)

#define AT91C_TWI0_PTCR   (AT91_CAST(AT91_REG *) 0x40084120)

#define AT91C_TWI0_PTSR   (AT91_CAST(AT91_REG *) 0x40084124)

#define AT91C_TWI0_RCR   (AT91_CAST(AT91_REG *) 0x40084104)

#define AT91C_TWI0_TNPR   (AT91_CAST(AT91_REG *) 0x40084118)

#define AT91C_TWI0_RNPR   (AT91_CAST(AT91_REG *) 0x40084110)

#define AT91C_TWI0_RPR   (AT91_CAST(AT91_REG *) 0x40084100)

#define AT91C_TWI0_RNCR   (AT91_CAST(AT91_REG *) 0x40084114)

#define AT91C_TWI0_TPR   (AT91_CAST(AT91_REG *) 0x40084108)

#define AT91C_TWI0_TCR   (AT91_CAST(AT91_REG *) 0x4008410C)

#define AT91C_TWI1_TNCR   (AT91_CAST(AT91_REG *) 0x4008811C)

#define AT91C_TWI1_PTCR   (AT91_CAST(AT91_REG *) 0x40088120)

#define AT91C_TWI1_RNCR   (AT91_CAST(AT91_REG *) 0x40088114)

#define AT91C_TWI1_RCR   (AT91_CAST(AT91_REG *) 0x40088104)

#define AT91C_TWI1_RPR   (AT91_CAST(AT91_REG *) 0x40088100)

#define AT91C_TWI1_TNPR   (AT91_CAST(AT91_REG *) 0x40088118)

#define AT91C_TWI1_RNPR   (AT91_CAST(AT91_REG *) 0x40088110)

#define AT91C_TWI1_TCR   (AT91_CAST(AT91_REG *) 0x4008810C)

#define AT91C_TWI1_TPR   (AT91_CAST(AT91_REG *) 0x40088108)

#define AT91C_TWI1_PTSR   (AT91_CAST(AT91_REG *) 0x40088124)

#define AT91C_TWI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400840F8)

#define AT91C_TWI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400840F0)

#define AT91C_TWI0_SMR   (AT91_CAST(AT91_REG *) 0x40084008)

#define AT91C_TWI0_MMR   (AT91_CAST(AT91_REG *) 0x40084004)

#define AT91C_TWI0_SR   (AT91_CAST(AT91_REG *) 0x40084020)

#define AT91C_TWI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400840F4)

#define AT91C_TWI0_CR   (AT91_CAST(AT91_REG *) 0x40084000)

#define AT91C_TWI0_IER   (AT91_CAST(AT91_REG *) 0x40084024)

#define AT91C_TWI0_RHR   (AT91_CAST(AT91_REG *) 0x40084030)

#define AT91C_TWI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400840EC)

#define AT91C_TWI0_THR   (AT91_CAST(AT91_REG *) 0x40084034)

#define AT91C_TWI0_VER   (AT91_CAST(AT91_REG *) 0x400840FC)

#define AT91C_TWI0_IADR   (AT91_CAST(AT91_REG *) 0x4008400C)

#define AT91C_TWI0_IMR   (AT91_CAST(AT91_REG *) 0x4008402C)

#define AT91C_TWI0_CWGR   (AT91_CAST(AT91_REG *) 0x40084010)

#define AT91C_TWI0_IDR   (AT91_CAST(AT91_REG *) 0x40084028)

#define AT91C_TWI1_VER   (AT91_CAST(AT91_REG *) 0x400880FC)

#define AT91C_TWI1_IDR   (AT91_CAST(AT91_REG *) 0x40088028)

#define AT91C_TWI1_IPNAME2   (AT91_CAST(AT91_REG *) 0x400880F4)

#define AT91C_TWI1_CWGR   (AT91_CAST(AT91_REG *) 0x40088010)

#define AT91C_TWI1_CR   (AT91_CAST(AT91_REG *) 0x40088000)

#define AT91C_TWI1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400880EC)

#define AT91C_TWI1_IADR   (AT91_CAST(AT91_REG *) 0x4008800C)

#define AT91C_TWI1_IER   (AT91_CAST(AT91_REG *) 0x40088024)

#define AT91C_TWI1_SMR   (AT91_CAST(AT91_REG *) 0x40088008)

#define AT91C_TWI1_RHR   (AT91_CAST(AT91_REG *) 0x40088030)

#define AT91C_TWI1_FEATURES   (AT91_CAST(AT91_REG *) 0x400880F8)

#define AT91C_TWI1_IMR   (AT91_CAST(AT91_REG *) 0x4008802C)

#define AT91C_TWI1_SR   (AT91_CAST(AT91_REG *) 0x40088020)

#define AT91C_TWI1_THR   (AT91_CAST(AT91_REG *) 0x40088034)

#define AT91C_TWI1_MMR   (AT91_CAST(AT91_REG *) 0x40088004)

#define AT91C_TWI1_IPNAME1   (AT91_CAST(AT91_REG *) 0x400880F0)

#define AT91C_US0_RNCR   (AT91_CAST(AT91_REG *) 0x40090114)

#define AT91C_US0_TNPR   (AT91_CAST(AT91_REG *) 0x40090118)

#define AT91C_US0_TPR   (AT91_CAST(AT91_REG *) 0x40090108)

#define AT91C_US0_RCR   (AT91_CAST(AT91_REG *) 0x40090104)

#define AT91C_US0_RNPR   (AT91_CAST(AT91_REG *) 0x40090110)

#define AT91C_US0_TNCR   (AT91_CAST(AT91_REG *) 0x4009011C)

#define AT91C_US0_PTSR   (AT91_CAST(AT91_REG *) 0x40090124)

#define AT91C_US0_RPR   (AT91_CAST(AT91_REG *) 0x40090100)

#define AT91C_US0_PTCR   (AT91_CAST(AT91_REG *) 0x40090120)

#define AT91C_US0_TCR   (AT91_CAST(AT91_REG *) 0x4009010C)

#define AT91C_US0_NER   (AT91_CAST(AT91_REG *) 0x40090044)

#define AT91C_US0_RHR   (AT91_CAST(AT91_REG *) 0x40090018)

#define AT91C_US0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400900F0)

#define AT91C_US0_MR   (AT91_CAST(AT91_REG *) 0x40090004)

#define AT91C_US0_RTOR   (AT91_CAST(AT91_REG *) 0x40090024)

#define AT91C_US0_IF   (AT91_CAST(AT91_REG *) 0x4009004C)

#define AT91C_US0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400900EC)

#define AT91C_US0_IDR   (AT91_CAST(AT91_REG *) 0x4009000C)

#define AT91C_US0_IMR   (AT91_CAST(AT91_REG *) 0x40090010)

#define AT91C_US0_IER   (AT91_CAST(AT91_REG *) 0x40090008)

#define AT91C_US0_TTGR   (AT91_CAST(AT91_REG *) 0x40090028)

#define AT91C_US0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400900F4)

#define AT91C_US0_FIDI   (AT91_CAST(AT91_REG *) 0x40090040)

#define AT91C_US0_CR   (AT91_CAST(AT91_REG *) 0x40090000)

#define AT91C_US0_BRGR   (AT91_CAST(AT91_REG *) 0x40090020)

#define AT91C_US0_MAN   (AT91_CAST(AT91_REG *) 0x40090050)

#define AT91C_US0_VER   (AT91_CAST(AT91_REG *) 0x400900FC)

#define AT91C_US0_FEATURES   (AT91_CAST(AT91_REG *) 0x400900F8)

#define AT91C_US0_CSR   (AT91_CAST(AT91_REG *) 0x40090014)

#define AT91C_US0_THR   (AT91_CAST(AT91_REG *) 0x4009001C)

#define AT91C_US1_TNPR   (AT91_CAST(AT91_REG *) 0x40094118)

#define AT91C_US1_TPR   (AT91_CAST(AT91_REG *) 0x40094108)

#define AT91C_US1_RNCR   (AT91_CAST(AT91_REG *) 0x40094114)

#define AT91C_US1_TNCR   (AT91_CAST(AT91_REG *) 0x4009411C)

#define AT91C_US1_RNPR   (AT91_CAST(AT91_REG *) 0x40094110)

#define AT91C_US1_TCR   (AT91_CAST(AT91_REG *) 0x4009410C)

#define AT91C_US1_PTSR   (AT91_CAST(AT91_REG *) 0x40094124)

#define AT91C_US1_RCR   (AT91_CAST(AT91_REG *) 0x40094104)

#define AT91C_US1_RPR   (AT91_CAST(AT91_REG *) 0x40094100)

#define AT91C_US1_PTCR   (AT91_CAST(AT91_REG *) 0x40094120)

#define AT91C_US1_IMR   (AT91_CAST(AT91_REG *) 0x40094010)

#define AT91C_US1_RTOR   (AT91_CAST(AT91_REG *) 0x40094024)

#define AT91C_US1_RHR   (AT91_CAST(AT91_REG *) 0x40094018)

#define AT91C_US1_IPNAME1   (AT91_CAST(AT91_REG *) 0x400940F0)

#define AT91C_US1_VER   (AT91_CAST(AT91_REG *) 0x400940FC)

#define AT91C_US1_MR   (AT91_CAST(AT91_REG *) 0x40094004)

#define AT91C_US1_FEATURES   (AT91_CAST(AT91_REG *) 0x400940F8)

#define AT91C_US1_NER   (AT91_CAST(AT91_REG *) 0x40094044)

#define AT91C_US1_IPNAME2   (AT91_CAST(AT91_REG *) 0x400940F4)

#define AT91C_US1_CR   (AT91_CAST(AT91_REG *) 0x40094000)

#define AT91C_US1_BRGR   (AT91_CAST(AT91_REG *) 0x40094020)

#define AT91C_US1_IF   (AT91_CAST(AT91_REG *) 0x4009404C)

#define AT91C_US1_IER   (AT91_CAST(AT91_REG *) 0x40094008)

#define AT91C_US1_TTGR   (AT91_CAST(AT91_REG *) 0x40094028)

#define AT91C_US1_FIDI   (AT91_CAST(AT91_REG *) 0x40094040)

#define AT91C_US1_MAN   (AT91_CAST(AT91_REG *) 0x40094050)

#define AT91C_US1_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400940EC)

#define AT91C_US1_CSR   (AT91_CAST(AT91_REG *) 0x40094014)

#define AT91C_US1_THR   (AT91_CAST(AT91_REG *) 0x4009401C)

#define AT91C_US1_IDR   (AT91_CAST(AT91_REG *) 0x4009400C)

#define AT91C_US2_RPR   (AT91_CAST(AT91_REG *) 0x40098100)

#define AT91C_US2_TPR   (AT91_CAST(AT91_REG *) 0x40098108)

#define AT91C_US2_TCR   (AT91_CAST(AT91_REG *) 0x4009810C)

#define AT91C_US2_PTSR   (AT91_CAST(AT91_REG *) 0x40098124)

#define AT91C_US2_PTCR   (AT91_CAST(AT91_REG *) 0x40098120)

#define AT91C_US2_RNPR   (AT91_CAST(AT91_REG *) 0x40098110)

#define AT91C_US2_TNCR   (AT91_CAST(AT91_REG *) 0x4009811C)

#define AT91C_US2_RNCR   (AT91_CAST(AT91_REG *) 0x40098114)

#define AT91C_US2_TNPR   (AT91_CAST(AT91_REG *) 0x40098118)

#define AT91C_US2_RCR   (AT91_CAST(AT91_REG *) 0x40098104)

#define AT91C_US2_MAN   (AT91_CAST(AT91_REG *) 0x40098050)

#define AT91C_US2_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400980EC)

#define AT91C_US2_MR   (AT91_CAST(AT91_REG *) 0x40098004)

#define AT91C_US2_IPNAME1   (AT91_CAST(AT91_REG *) 0x400980F0)

#define AT91C_US2_IF   (AT91_CAST(AT91_REG *) 0x4009804C)

#define AT91C_US2_BRGR   (AT91_CAST(AT91_REG *) 0x40098020)

#define AT91C_US2_FIDI   (AT91_CAST(AT91_REG *) 0x40098040)

#define AT91C_US2_IER   (AT91_CAST(AT91_REG *) 0x40098008)

#define AT91C_US2_RTOR   (AT91_CAST(AT91_REG *) 0x40098024)

#define AT91C_US2_CR   (AT91_CAST(AT91_REG *) 0x40098000)

#define AT91C_US2_THR   (AT91_CAST(AT91_REG *) 0x4009801C)

#define AT91C_US2_CSR   (AT91_CAST(AT91_REG *) 0x40098014)

#define AT91C_US2_VER   (AT91_CAST(AT91_REG *) 0x400980FC)

#define AT91C_US2_FEATURES   (AT91_CAST(AT91_REG *) 0x400980F8)

#define AT91C_US2_IDR   (AT91_CAST(AT91_REG *) 0x4009800C)

#define AT91C_US2_TTGR   (AT91_CAST(AT91_REG *) 0x40098028)

#define AT91C_US2_IPNAME2   (AT91_CAST(AT91_REG *) 0x400980F4)

#define AT91C_US2_RHR   (AT91_CAST(AT91_REG *) 0x40098018)

#define AT91C_US2_NER   (AT91_CAST(AT91_REG *) 0x40098044)

#define AT91C_US2_IMR   (AT91_CAST(AT91_REG *) 0x40098010)

#define AT91C_US3_TPR   (AT91_CAST(AT91_REG *) 0x4009C108)

#define AT91C_US3_PTCR   (AT91_CAST(AT91_REG *) 0x4009C120)

#define AT91C_US3_TCR   (AT91_CAST(AT91_REG *) 0x4009C10C)

#define AT91C_US3_RCR   (AT91_CAST(AT91_REG *) 0x4009C104)

#define AT91C_US3_RNCR   (AT91_CAST(AT91_REG *) 0x4009C114)

#define AT91C_US3_RNPR   (AT91_CAST(AT91_REG *) 0x4009C110)

#define AT91C_US3_RPR   (AT91_CAST(AT91_REG *) 0x4009C100)

#define AT91C_US3_PTSR   (AT91_CAST(AT91_REG *) 0x4009C124)

#define AT91C_US3_TNCR   (AT91_CAST(AT91_REG *) 0x4009C11C)

#define AT91C_US3_TNPR   (AT91_CAST(AT91_REG *) 0x4009C118)

#define AT91C_US3_MAN   (AT91_CAST(AT91_REG *) 0x4009C050)

#define AT91C_US3_CSR   (AT91_CAST(AT91_REG *) 0x4009C014)

#define AT91C_US3_BRGR   (AT91_CAST(AT91_REG *) 0x4009C020)

#define AT91C_US3_IPNAME2   (AT91_CAST(AT91_REG *) 0x4009C0F4)

#define AT91C_US3_RTOR   (AT91_CAST(AT91_REG *) 0x4009C024)

#define AT91C_US3_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4009C0EC)

#define AT91C_US3_CR   (AT91_CAST(AT91_REG *) 0x4009C000)

#define AT91C_US3_IF   (AT91_CAST(AT91_REG *) 0x4009C04C)

#define AT91C_US3_FEATURES   (AT91_CAST(AT91_REG *) 0x4009C0F8)

#define AT91C_US3_VER   (AT91_CAST(AT91_REG *) 0x4009C0FC)

#define AT91C_US3_RHR   (AT91_CAST(AT91_REG *) 0x4009C018)

#define AT91C_US3_TTGR   (AT91_CAST(AT91_REG *) 0x4009C028)

#define AT91C_US3_NER   (AT91_CAST(AT91_REG *) 0x4009C044)

#define AT91C_US3_IMR   (AT91_CAST(AT91_REG *) 0x4009C010)

#define AT91C_US3_THR   (AT91_CAST(AT91_REG *) 0x4009C01C)

#define AT91C_US3_IDR   (AT91_CAST(AT91_REG *) 0x4009C00C)

#define AT91C_US3_MR   (AT91_CAST(AT91_REG *) 0x4009C004)

#define AT91C_US3_IER   (AT91_CAST(AT91_REG *) 0x4009C008)

#define AT91C_US3_FIDI   (AT91_CAST(AT91_REG *) 0x4009C040)

#define AT91C_US3_IPNAME1   (AT91_CAST(AT91_REG *) 0x4009C0F0)

#define AT91C_SSC0_RNCR   (AT91_CAST(AT91_REG *) 0x40004114)

#define AT91C_SSC0_TPR   (AT91_CAST(AT91_REG *) 0x40004108)

#define AT91C_SSC0_TCR   (AT91_CAST(AT91_REG *) 0x4000410C)

#define AT91C_SSC0_PTCR   (AT91_CAST(AT91_REG *) 0x40004120)

#define AT91C_SSC0_TNPR   (AT91_CAST(AT91_REG *) 0x40004118)

#define AT91C_SSC0_RPR   (AT91_CAST(AT91_REG *) 0x40004100)

#define AT91C_SSC0_TNCR   (AT91_CAST(AT91_REG *) 0x4000411C)

#define AT91C_SSC0_RNPR   (AT91_CAST(AT91_REG *) 0x40004110)

#define AT91C_SSC0_RCR   (AT91_CAST(AT91_REG *) 0x40004104)

#define AT91C_SSC0_PTSR   (AT91_CAST(AT91_REG *) 0x40004124)

#define AT91C_SSC0_FEATURES   (AT91_CAST(AT91_REG *) 0x400040F8)

#define AT91C_SSC0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400040F0)

#define AT91C_SSC0_CR   (AT91_CAST(AT91_REG *) 0x40004000)

#define AT91C_SSC0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400040EC)

#define AT91C_SSC0_RHR   (AT91_CAST(AT91_REG *) 0x40004020)

#define AT91C_SSC0_VER   (AT91_CAST(AT91_REG *) 0x400040FC)

#define AT91C_SSC0_TSHR   (AT91_CAST(AT91_REG *) 0x40004034)

#define AT91C_SSC0_RFMR   (AT91_CAST(AT91_REG *) 0x40004014)

#define AT91C_SSC0_IDR   (AT91_CAST(AT91_REG *) 0x40004048)

#define AT91C_SSC0_TFMR   (AT91_CAST(AT91_REG *) 0x4000401C)

#define AT91C_SSC0_RSHR   (AT91_CAST(AT91_REG *) 0x40004030)

#define AT91C_SSC0_TCMR   (AT91_CAST(AT91_REG *) 0x40004018)

#define AT91C_SSC0_RCMR   (AT91_CAST(AT91_REG *) 0x40004010)

#define AT91C_SSC0_SR   (AT91_CAST(AT91_REG *) 0x40004040)

#define AT91C_SSC0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400040F4)

#define AT91C_SSC0_THR   (AT91_CAST(AT91_REG *) 0x40004024)

#define AT91C_SSC0_CMR   (AT91_CAST(AT91_REG *) 0x40004004)

#define AT91C_SSC0_IER   (AT91_CAST(AT91_REG *) 0x40004044)

#define AT91C_SSC0_IMR   (AT91_CAST(AT91_REG *) 0x4000404C)

#define AT91C_PWMC_TNCR   (AT91_CAST(AT91_REG *) 0x4008C11C)

#define AT91C_PWMC_TPR   (AT91_CAST(AT91_REG *) 0x4008C108)

#define AT91C_PWMC_RPR   (AT91_CAST(AT91_REG *) 0x4008C100)

#define AT91C_PWMC_TCR   (AT91_CAST(AT91_REG *) 0x4008C10C)

#define AT91C_PWMC_PTSR   (AT91_CAST(AT91_REG *) 0x4008C124)

#define AT91C_PWMC_RNPR   (AT91_CAST(AT91_REG *) 0x4008C110)

#define AT91C_PWMC_RCR   (AT91_CAST(AT91_REG *) 0x4008C104)

#define AT91C_PWMC_RNCR   (AT91_CAST(AT91_REG *) 0x4008C114)

#define AT91C_PWMC_PTCR   (AT91_CAST(AT91_REG *) 0x4008C120)

#define AT91C_PWMC_TNPR   (AT91_CAST(AT91_REG *) 0x4008C118)

#define AT91C_PWMC_CH0_DTR   (AT91_CAST(AT91_REG *) 0x4008C218)

#define AT91C_PWMC_CH0_CMR   (AT91_CAST(AT91_REG *) 0x4008C200)

#define AT91C_PWMC_CH0_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C214)

#define AT91C_PWMC_CH0_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C20C)

#define AT91C_PWMC_CH0_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C21C)

#define AT91C_PWMC_CH0_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C210)

#define AT91C_PWMC_CH0_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C208)

#define AT91C_PWMC_CH0_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C204)

#define AT91C_PWMC_CH1_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C234)

#define AT91C_PWMC_CH1_DTR   (AT91_CAST(AT91_REG *) 0x4008C238)

#define AT91C_PWMC_CH1_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C228)

#define AT91C_PWMC_CH1_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C23C)

#define AT91C_PWMC_CH1_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C224)

#define AT91C_PWMC_CH1_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C22C)

#define AT91C_PWMC_CH1_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C230)

#define AT91C_PWMC_CH1_CMR   (AT91_CAST(AT91_REG *) 0x4008C220)

#define AT91C_PWMC_CH2_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C244)

#define AT91C_PWMC_CH2_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C25C)

#define AT91C_PWMC_CH2_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C254)

#define AT91C_PWMC_CH2_CMR   (AT91_CAST(AT91_REG *) 0x4008C240)

#define AT91C_PWMC_CH2_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C24C)

#define AT91C_PWMC_CH2_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C250)

#define AT91C_PWMC_CH2_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C248)

#define AT91C_PWMC_CH2_DTR   (AT91_CAST(AT91_REG *) 0x4008C258)

#define AT91C_PWMC_CH3_CPRDUPDR   (AT91_CAST(AT91_REG *) 0x4008C270)

#define AT91C_PWMC_CH3_DTR   (AT91_CAST(AT91_REG *) 0x4008C278)

#define AT91C_PWMC_CH3_CDTYR   (AT91_CAST(AT91_REG *) 0x4008C264)

#define AT91C_PWMC_CH3_DTUPDR   (AT91_CAST(AT91_REG *) 0x4008C27C)

#define AT91C_PWMC_CH3_CDTYUPDR   (AT91_CAST(AT91_REG *) 0x4008C268)

#define AT91C_PWMC_CH3_CCNTR   (AT91_CAST(AT91_REG *) 0x4008C274)

#define AT91C_PWMC_CH3_CMR   (AT91_CAST(AT91_REG *) 0x4008C260)

#define AT91C_PWMC_CH3_CPRDR   (AT91_CAST(AT91_REG *) 0x4008C26C)

#define AT91C_PWMC_CMP6MUPD   (AT91_CAST(AT91_REG *) 0x4008C19C)

#define AT91C_PWMC_ISR1   (AT91_CAST(AT91_REG *) 0x4008C01C)

#define AT91C_PWMC_CMP5V   (AT91_CAST(AT91_REG *) 0x4008C180)

#define AT91C_PWMC_CMP4MUPD   (AT91_CAST(AT91_REG *) 0x4008C17C)

#define AT91C_PWMC_FMR   (AT91_CAST(AT91_REG *) 0x4008C05C)

#define AT91C_PWMC_CMP6V   (AT91_CAST(AT91_REG *) 0x4008C190)

#define AT91C_PWMC_EL4MR   (AT91_CAST(AT91_REG *) 0x4008C08C)

#define AT91C_PWMC_UPCR   (AT91_CAST(AT91_REG *) 0x4008C028)

#define AT91C_PWMC_CMP1VUPD   (AT91_CAST(AT91_REG *) 0x4008C144)

#define AT91C_PWMC_CMP0M   (AT91_CAST(AT91_REG *) 0x4008C138)

#define AT91C_PWMC_CMP5VUPD   (AT91_CAST(AT91_REG *) 0x4008C184)

#define AT91C_PWMC_FPER3   (AT91_CAST(AT91_REG *) 0x4008C074)

#define AT91C_PWMC_OSCUPD   (AT91_CAST(AT91_REG *) 0x4008C058)

#define AT91C_PWMC_FPER1   (AT91_CAST(AT91_REG *) 0x4008C06C)

#define AT91C_PWMC_SCUPUPD   (AT91_CAST(AT91_REG *) 0x4008C030)

#define AT91C_PWMC_DIS   (AT91_CAST(AT91_REG *) 0x4008C008)

#define AT91C_PWMC_IER1   (AT91_CAST(AT91_REG *) 0x4008C010)

#define AT91C_PWMC_IMR2   (AT91_CAST(AT91_REG *) 0x4008C03C)

#define AT91C_PWMC_CMP0V   (AT91_CAST(AT91_REG *) 0x4008C130)

#define AT91C_PWMC_SR   (AT91_CAST(AT91_REG *) 0x4008C00C)

#define AT91C_PWMC_CMP4M   (AT91_CAST(AT91_REG *) 0x4008C178)

#define AT91C_PWMC_CMP3M   (AT91_CAST(AT91_REG *) 0x4008C168)

#define AT91C_PWMC_IER2   (AT91_CAST(AT91_REG *) 0x4008C034)

#define AT91C_PWMC_CMP3VUPD   (AT91_CAST(AT91_REG *) 0x4008C164)

#define AT91C_PWMC_CMP2M   (AT91_CAST(AT91_REG *) 0x4008C158)

#define AT91C_PWMC_IDR2   (AT91_CAST(AT91_REG *) 0x4008C038)

#define AT91C_PWMC_EL2MR   (AT91_CAST(AT91_REG *) 0x4008C084)

#define AT91C_PWMC_CMP7V   (AT91_CAST(AT91_REG *) 0x4008C1A0)

#define AT91C_PWMC_CMP1M   (AT91_CAST(AT91_REG *) 0x4008C148)

#define AT91C_PWMC_CMP0VUPD   (AT91_CAST(AT91_REG *) 0x4008C134)

#define AT91C_PWMC_WPSR   (AT91_CAST(AT91_REG *) 0x4008C0E8)

#define AT91C_PWMC_CMP6VUPD   (AT91_CAST(AT91_REG *) 0x4008C194)

#define AT91C_PWMC_CMP1MUPD   (AT91_CAST(AT91_REG *) 0x4008C14C)

#define AT91C_PWMC_CMP1V   (AT91_CAST(AT91_REG *) 0x4008C140)

#define AT91C_PWMC_FCR   (AT91_CAST(AT91_REG *) 0x4008C064)

#define AT91C_PWMC_VER   (AT91_CAST(AT91_REG *) 0x4008C0FC)

#define AT91C_PWMC_EL1MR   (AT91_CAST(AT91_REG *) 0x4008C080)

#define AT91C_PWMC_EL6MR   (AT91_CAST(AT91_REG *) 0x4008C094)

#define AT91C_PWMC_ISR2   (AT91_CAST(AT91_REG *) 0x4008C040)

#define AT91C_PWMC_CMP4VUPD   (AT91_CAST(AT91_REG *) 0x4008C174)

#define AT91C_PWMC_CMP5MUPD   (AT91_CAST(AT91_REG *) 0x4008C18C)

#define AT91C_PWMC_OS   (AT91_CAST(AT91_REG *) 0x4008C048)

#define AT91C_PWMC_FPV   (AT91_CAST(AT91_REG *) 0x4008C068)

#define AT91C_PWMC_FPER2   (AT91_CAST(AT91_REG *) 0x4008C070)

#define AT91C_PWMC_EL7MR   (AT91_CAST(AT91_REG *) 0x4008C098)

#define AT91C_PWMC_OSSUPD   (AT91_CAST(AT91_REG *) 0x4008C054)

#define AT91C_PWMC_FEATURES   (AT91_CAST(AT91_REG *) 0x4008C0F8)

#define AT91C_PWMC_CMP2V   (AT91_CAST(AT91_REG *) 0x4008C150)

#define AT91C_PWMC_FSR   (AT91_CAST(AT91_REG *) 0x4008C060)

#define AT91C_PWMC_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x4008C0EC)

#define AT91C_PWMC_OSC   (AT91_CAST(AT91_REG *) 0x4008C050)

#define AT91C_PWMC_SCUP   (AT91_CAST(AT91_REG *) 0x4008C02C)

#define AT91C_PWMC_CMP7MUPD   (AT91_CAST(AT91_REG *) 0x4008C1AC)

#define AT91C_PWMC_CMP2VUPD   (AT91_CAST(AT91_REG *) 0x4008C154)

#define AT91C_PWMC_FPER4   (AT91_CAST(AT91_REG *) 0x4008C078)

#define AT91C_PWMC_IMR1   (AT91_CAST(AT91_REG *) 0x4008C018)

#define AT91C_PWMC_EL3MR   (AT91_CAST(AT91_REG *) 0x4008C088)

#define AT91C_PWMC_CMP3V   (AT91_CAST(AT91_REG *) 0x4008C160)

#define AT91C_PWMC_IPNAME1   (AT91_CAST(AT91_REG *) 0x4008C0F0)

#define AT91C_PWMC_OSS   (AT91_CAST(AT91_REG *) 0x4008C04C)

#define AT91C_PWMC_CMP0MUPD   (AT91_CAST(AT91_REG *) 0x4008C13C)

#define AT91C_PWMC_CMP2MUPD   (AT91_CAST(AT91_REG *) 0x4008C15C)

#define AT91C_PWMC_CMP4V   (AT91_CAST(AT91_REG *) 0x4008C170)

#define AT91C_PWMC_ENA   (AT91_CAST(AT91_REG *) 0x4008C004)

#define AT91C_PWMC_CMP3MUPD   (AT91_CAST(AT91_REG *) 0x4008C16C)

#define AT91C_PWMC_EL0MR   (AT91_CAST(AT91_REG *) 0x4008C07C)

#define AT91C_PWMC_OOV   (AT91_CAST(AT91_REG *) 0x4008C044)

#define AT91C_PWMC_WPCR   (AT91_CAST(AT91_REG *) 0x4008C0E4)

#define AT91C_PWMC_CMP7M   (AT91_CAST(AT91_REG *) 0x4008C1A8)

#define AT91C_PWMC_CMP6M   (AT91_CAST(AT91_REG *) 0x4008C198)

#define AT91C_PWMC_CMP5M   (AT91_CAST(AT91_REG *) 0x4008C188)

#define AT91C_PWMC_IPNAME2   (AT91_CAST(AT91_REG *) 0x4008C0F4)

#define AT91C_PWMC_CMP7VUPD   (AT91_CAST(AT91_REG *) 0x4008C1A4)

#define AT91C_PWMC_SYNC   (AT91_CAST(AT91_REG *) 0x4008C020)

#define AT91C_PWMC_MR   (AT91_CAST(AT91_REG *) 0x4008C000)

#define AT91C_PWMC_IDR1   (AT91_CAST(AT91_REG *) 0x4008C014)

#define AT91C_PWMC_EL5MR   (AT91_CAST(AT91_REG *) 0x4008C090)

#define AT91C_SPI0_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400080EC)

#define AT91C_SPI0_RDR   (AT91_CAST(AT91_REG *) 0x40008008)

#define AT91C_SPI0_FEATURES   (AT91_CAST(AT91_REG *) 0x400080F8)

#define AT91C_SPI0_CR   (AT91_CAST(AT91_REG *) 0x40008000)

#define AT91C_SPI0_IPNAME1   (AT91_CAST(AT91_REG *) 0x400080F0)

#define AT91C_SPI0_VER   (AT91_CAST(AT91_REG *) 0x400080FC)

#define AT91C_SPI0_IDR   (AT91_CAST(AT91_REG *) 0x40008018)

#define AT91C_SPI0_TDR   (AT91_CAST(AT91_REG *) 0x4000800C)

#define AT91C_SPI0_MR   (AT91_CAST(AT91_REG *) 0x40008004)

#define AT91C_SPI0_IER   (AT91_CAST(AT91_REG *) 0x40008014)

#define AT91C_SPI0_IMR   (AT91_CAST(AT91_REG *) 0x4000801C)

#define AT91C_SPI0_IPNAME2   (AT91_CAST(AT91_REG *) 0x400080F4)

#define AT91C_SPI0_CSR   (AT91_CAST(AT91_REG *) 0x40008030)

#define AT91C_SPI0_SR   (AT91_CAST(AT91_REG *) 0x40008010)

#define AT91C_UDPHS_EPTFIFO_READEPT6   (AT91_CAST(AT91_REG *) 0x201E0000)

#define AT91C_UDPHS_EPTFIFO_READEPT2   (AT91_CAST(AT91_REG *) 0x201A0000)

#define AT91C_UDPHS_EPTFIFO_READEPT1   (AT91_CAST(AT91_REG *) 0x20190000)

#define AT91C_UDPHS_EPTFIFO_READEPT0   (AT91_CAST(AT91_REG *) 0x20180000)

#define AT91C_UDPHS_EPTFIFO_READEPT5   (AT91_CAST(AT91_REG *) 0x201D0000)

#define AT91C_UDPHS_EPTFIFO_READEPT4   (AT91_CAST(AT91_REG *) 0x201C0000)

#define AT91C_UDPHS_EPTFIFO_READEPT3   (AT91_CAST(AT91_REG *) 0x201B0000)

#define AT91C_UDPHS_EPT_0_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A410C)

#define AT91C_UDPHS_EPT_0_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A411C)

#define AT91C_UDPHS_EPT_0_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4118)

#define AT91C_UDPHS_EPT_0_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4108)

#define AT91C_UDPHS_EPT_0_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4100)

#define AT91C_UDPHS_EPT_0_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4114)

#define AT91C_UDPHS_EPT_0_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4104)

#define AT91C_UDPHS_EPT_1_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A413C)

#define AT91C_UDPHS_EPT_1_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4134)

#define AT91C_UDPHS_EPT_1_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A412C)

#define AT91C_UDPHS_EPT_1_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4120)

#define AT91C_UDPHS_EPT_1_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4128)

#define AT91C_UDPHS_EPT_1_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4138)

#define AT91C_UDPHS_EPT_1_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4124)

#define AT91C_UDPHS_EPT_2_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4144)

#define AT91C_UDPHS_EPT_2_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4158)

#define AT91C_UDPHS_EPT_2_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4140)

#define AT91C_UDPHS_EPT_2_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A414C)

#define AT91C_UDPHS_EPT_2_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4154)

#define AT91C_UDPHS_EPT_2_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A415C)

#define AT91C_UDPHS_EPT_2_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4148)

#define AT91C_UDPHS_EPT_3_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4168)

#define AT91C_UDPHS_EPT_3_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4164)

#define AT91C_UDPHS_EPT_3_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4174)

#define AT91C_UDPHS_EPT_3_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4178)

#define AT91C_UDPHS_EPT_3_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4160)

#define AT91C_UDPHS_EPT_3_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A417C)

#define AT91C_UDPHS_EPT_3_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A416C)

#define AT91C_UDPHS_EPT_4_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A4194)

#define AT91C_UDPHS_EPT_4_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A4188)

#define AT91C_UDPHS_EPT_4_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A418C)

#define AT91C_UDPHS_EPT_4_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A4180)

#define AT91C_UDPHS_EPT_4_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A4184)

#define AT91C_UDPHS_EPT_4_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A419C)

#define AT91C_UDPHS_EPT_4_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A4198)

#define AT91C_UDPHS_EPT_5_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A41A0)

#define AT91C_UDPHS_EPT_5_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A41AC)

#define AT91C_UDPHS_EPT_5_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A41A4)

#define AT91C_UDPHS_EPT_5_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A41BC)

#define AT91C_UDPHS_EPT_5_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A41B4)

#define AT91C_UDPHS_EPT_5_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A41A8)

#define AT91C_UDPHS_EPT_5_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A41B8)

#define AT91C_UDPHS_EPT_6_EPTCLRSTA   (AT91_CAST(AT91_REG *) 0x400A41D8)

#define AT91C_UDPHS_EPT_6_EPTCTL   (AT91_CAST(AT91_REG *) 0x400A41CC)

#define AT91C_UDPHS_EPT_6_EPTCFG   (AT91_CAST(AT91_REG *) 0x400A41C0)

#define AT91C_UDPHS_EPT_6_EPTCTLDIS   (AT91_CAST(AT91_REG *) 0x400A41C8)

#define AT91C_UDPHS_EPT_6_EPTSTA   (AT91_CAST(AT91_REG *) 0x400A41DC)

#define AT91C_UDPHS_EPT_6_EPTCTLENB   (AT91_CAST(AT91_REG *) 0x400A41C4)

#define AT91C_UDPHS_EPT_6_EPTSETSTA   (AT91_CAST(AT91_REG *) 0x400A41D4)

#define AT91C_UDPHS_DMA_1_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A431C)

#define AT91C_UDPHS_DMA_1_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4318)

#define AT91C_UDPHS_DMA_1_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4310)

#define AT91C_UDPHS_DMA_1_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4314)

#define AT91C_UDPHS_DMA_2_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A432C)

#define AT91C_UDPHS_DMA_2_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4320)

#define AT91C_UDPHS_DMA_2_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4328)

#define AT91C_UDPHS_DMA_2_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4324)

#define AT91C_UDPHS_DMA_3_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4338)

#define AT91C_UDPHS_DMA_3_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4330)

#define AT91C_UDPHS_DMA_3_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A433C)

#define AT91C_UDPHS_DMA_3_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4334)

#define AT91C_UDPHS_DMA_4_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4344)

#define AT91C_UDPHS_DMA_4_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4340)

#define AT91C_UDPHS_DMA_4_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A434C)

#define AT91C_UDPHS_DMA_4_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4348)

#define AT91C_UDPHS_DMA_5_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4358)

#define AT91C_UDPHS_DMA_5_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4354)

#define AT91C_UDPHS_DMA_5_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4350)

#define AT91C_UDPHS_DMA_5_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A435C)

#define AT91C_UDPHS_DMA_6_DMASTATUS   (AT91_CAST(AT91_REG *) 0x400A436C)

#define AT91C_UDPHS_DMA_6_DMACONTROL   (AT91_CAST(AT91_REG *) 0x400A4368)

#define AT91C_UDPHS_DMA_6_DMANXTDSC   (AT91_CAST(AT91_REG *) 0x400A4360)

#define AT91C_UDPHS_DMA_6_DMAADDRESS   (AT91_CAST(AT91_REG *) 0x400A4364)

#define AT91C_UDPHS_EPTRST   (AT91_CAST(AT91_REG *) 0x400A401C)

#define AT91C_UDPHS_IEN   (AT91_CAST(AT91_REG *) 0x400A4010)

#define AT91C_UDPHS_TSTCNTB   (AT91_CAST(AT91_REG *) 0x400A40D8)

#define AT91C_UDPHS_RIPNAME2   (AT91_CAST(AT91_REG *) 0x400A40F4)

#define AT91C_UDPHS_RIPPADDRSIZE   (AT91_CAST(AT91_REG *) 0x400A40EC)

#define AT91C_UDPHS_TSTMODREG   (AT91_CAST(AT91_REG *) 0x400A40DC)

#define AT91C_UDPHS_TST   (AT91_CAST(AT91_REG *) 0x400A40E0)

#define AT91C_UDPHS_TSTSOFCNT   (AT91_CAST(AT91_REG *) 0x400A40D0)

#define AT91C_UDPHS_FNUM   (AT91_CAST(AT91_REG *) 0x400A4004)

#define AT91C_UDPHS_TSTCNTA   (AT91_CAST(AT91_REG *) 0x400A40D4)

#define AT91C_UDPHS_INTSTA   (AT91_CAST(AT91_REG *) 0x400A4014)

#define AT91C_UDPHS_IPFEATURES   (AT91_CAST(AT91_REG *) 0x400A40F8)

#define AT91C_UDPHS_CLRINT   (AT91_CAST(AT91_REG *) 0x400A4018)

#define AT91C_UDPHS_RIPNAME1   (AT91_CAST(AT91_REG *) 0x400A40F0)

#define AT91C_UDPHS_CTRL   (AT91_CAST(AT91_REG *) 0x400A4000)

#define AT91C_UDPHS_IPVERSION   (AT91_CAST(AT91_REG *) 0x400A40FC)

#define AT91C_HDMA_CH_0_CADDR   (AT91_CAST(AT91_REG *) 0x400B0060)

#define AT91C_HDMA_CH_0_DADDR   (AT91_CAST(AT91_REG *) 0x400B0040)

#define AT91C_HDMA_CH_0_BDSCR   (AT91_CAST(AT91_REG *) 0x400B005C)

#define AT91C_HDMA_CH_0_CFG   (AT91_CAST(AT91_REG *) 0x400B0050)

#define AT91C_HDMA_CH_0_CTRLB   (AT91_CAST(AT91_REG *) 0x400B004C)

#define AT91C_HDMA_CH_0_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0048)

#define AT91C_HDMA_CH_0_DSCR   (AT91_CAST(AT91_REG *) 0x400B0044)

#define AT91C_HDMA_CH_0_SADDR   (AT91_CAST(AT91_REG *) 0x400B003C)

#define AT91C_HDMA_CH_0_DPIP   (AT91_CAST(AT91_REG *) 0x400B0058)

#define AT91C_HDMA_CH_0_SPIP   (AT91_CAST(AT91_REG *) 0x400B0054)

#define AT91C_HDMA_CH_1_DSCR   (AT91_CAST(AT91_REG *) 0x400B006C)

#define AT91C_HDMA_CH_1_BDSCR   (AT91_CAST(AT91_REG *) 0x400B0084)

#define AT91C_HDMA_CH_1_CTRLB   (AT91_CAST(AT91_REG *) 0x400B0074)

#define AT91C_HDMA_CH_1_SPIP   (AT91_CAST(AT91_REG *) 0x400B007C)

#define AT91C_HDMA_CH_1_SADDR   (AT91_CAST(AT91_REG *) 0x400B0064)

#define AT91C_HDMA_CH_1_DPIP   (AT91_CAST(AT91_REG *) 0x400B0080)

#define AT91C_HDMA_CH_1_CFG   (AT91_CAST(AT91_REG *) 0x400B0078)

#define AT91C_HDMA_CH_1_DADDR   (AT91_CAST(AT91_REG *) 0x400B0068)

#define AT91C_HDMA_CH_1_CADDR   (AT91_CAST(AT91_REG *) 0x400B0088)

#define AT91C_HDMA_CH_1_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0070)

#define AT91C_HDMA_CH_2_BDSCR   (AT91_CAST(AT91_REG *) 0x400B00AC)

#define AT91C_HDMA_CH_2_CTRLB   (AT91_CAST(AT91_REG *) 0x400B009C)

#define AT91C_HDMA_CH_2_CADDR   (AT91_CAST(AT91_REG *) 0x400B00B0)

#define AT91C_HDMA_CH_2_CFG   (AT91_CAST(AT91_REG *) 0x400B00A0)

#define AT91C_HDMA_CH_2_CTRLA   (AT91_CAST(AT91_REG *) 0x400B0098)

#define AT91C_HDMA_CH_2_SADDR   (AT91_CAST(AT91_REG *) 0x400B008C)

#define AT91C_HDMA_CH_2_DPIP   (AT91_CAST(AT91_REG *) 0x400B00A8)

#define AT91C_HDMA_CH_2_DADDR   (AT91_CAST(AT91_REG *) 0x400B0090)

#define AT91C_HDMA_CH_2_SPIP   (AT91_CAST(AT91_REG *) 0x400B00A4)

#define AT91C_HDMA_CH_2_DSCR   (AT91_CAST(AT91_REG *) 0x400B0094)

#define AT91C_HDMA_CH_3_DSCR   (AT91_CAST(AT91_REG *) 0x400B00BC)

#define AT91C_HDMA_CH_3_SADDR   (AT91_CAST(AT91_REG *) 0x400B00B4)

#define AT91C_HDMA_CH_3_BDSCR   (AT91_CAST(AT91_REG *) 0x400B00D4)

#define AT91C_HDMA_CH_3_CTRLA   (AT91_CAST(AT91_REG *) 0x400B00C0)

#define AT91C_HDMA_CH_3_DPIP   (AT91_CAST(AT91_REG *) 0x400B00D0)

#define AT91C_HDMA_CH_3_CTRLB   (AT91_CAST(AT91_REG *) 0x400B00C4)

#define AT91C_HDMA_CH_3_SPIP   (AT91_CAST(AT91_REG *) 0x400B00CC)

#define AT91C_HDMA_CH_3_CFG   (AT91_CAST(AT91_REG *) 0x400B00C8)

#define AT91C_HDMA_CH_3_CADDR   (AT91_CAST(AT91_REG *) 0x400B00D8)

#define AT91C_HDMA_CH_3_DADDR   (AT91_CAST(AT91_REG *) 0x400B00B8)

#define AT91C_HDMA_SYNC   (AT91_CAST(AT91_REG *) 0x400B0014)

#define AT91C_HDMA_VER   (AT91_CAST(AT91_REG *) 0x400B01FC)

#define AT91C_HDMA_RSVD0   (AT91_CAST(AT91_REG *) 0x400B0034)

#define AT91C_HDMA_CHSR   (AT91_CAST(AT91_REG *) 0x400B0030)

#define AT91C_HDMA_IPNAME2   (AT91_CAST(AT91_REG *) 0x400B01F4)

#define AT91C_HDMA_EBCIMR   (AT91_CAST(AT91_REG *) 0x400B0020)

#define AT91C_HDMA_CHDR   (AT91_CAST(AT91_REG *) 0x400B002C)

#define AT91C_HDMA_EN   (AT91_CAST(AT91_REG *) 0x400B0004)

#define AT91C_HDMA_GCFG   (AT91_CAST(AT91_REG *) 0x400B0000)

#define AT91C_HDMA_IPNAME1   (AT91_CAST(AT91_REG *) 0x400B01F0)

#define AT91C_HDMA_LAST   (AT91_CAST(AT91_REG *) 0x400B0010)

#define AT91C_HDMA_FEATURES   (AT91_CAST(AT91_REG *) 0x400B01F8)

#define AT91C_HDMA_CREQ   (AT91_CAST(AT91_REG *) 0x400B000C)

#define AT91C_HDMA_EBCIER   (AT91_CAST(AT91_REG *) 0x400B0018)

#define AT91C_HDMA_CHER   (AT91_CAST(AT91_REG *) 0x400B0028)

#define AT91C_HDMA_ADDRSIZE   (AT91_CAST(AT91_REG *) 0x400B01EC)

#define AT91C_HDMA_EBCISR   (AT91_CAST(AT91_REG *) 0x400B0024)

#define AT91C_HDMA_SREQ   (AT91_CAST(AT91_REG *) 0x400B0008)

#define AT91C_HDMA_EBCIDR   (AT91_CAST(AT91_REG *) 0x400B001C)

#define AT91C_HDMA_RSVD1   (AT91_CAST(AT91_REG *) 0x400B0038)

#define AT91C_PIO_PA0   (1 << 0)

#define AT91C_PA0_TIOB0   (AT91C_PIO_PA0)

#define AT91C_PA0_SPI0_NPCS1   (AT91C_PIO_PA0)

#define AT91C_PIO_PA1   (1 << 1)

#define AT91C_PA1_TIOA0   (AT91C_PIO_PA1)

#define AT91C_PA1_SPI0_NPCS2   (AT91C_PIO_PA1)

#define AT91C_PIO_PA10   (1 << 10)

#define AT91C_PA10_TWCK0   (AT91C_PIO_PA10)

#define AT91C_PA10_PWML3   (AT91C_PIO_PA10)

#define AT91C_PIO_PA11   (1 << 11)

#define AT91C_PA11_DRXD   (AT91C_PIO_PA11)

#define AT91C_PIO_PA12   (1 << 12)

#define AT91C_PA12_DTXD   (AT91C_PIO_PA12)

#define AT91C_PIO_PA13   (1 << 13)

#define AT91C_PA13_SPI0_MISO   (AT91C_PIO_PA13)

#define AT91C_PIO_PA14   (1 << 14)

#define AT91C_PA14_SPI0_MOSI   (AT91C_PIO_PA14)

#define AT91C_PIO_PA15   (1 << 15)

#define AT91C_PA15_SPI0_SPCK   (AT91C_PIO_PA15)

#define AT91C_PA15_PWMH2   (AT91C_PIO_PA15)

#define AT91C_PIO_PA16   (1 << 16)

#define AT91C_PA16_SPI0_NPCS0   (AT91C_PIO_PA16)

#define AT91C_PA16_NCS1   (AT91C_PIO_PA16)

#define AT91C_PIO_PA17   (1 << 17)

#define AT91C_PA17_SCK0   (AT91C_PIO_PA17)

#define AT91C_PIO_PA18   (1 << 18)

#define AT91C_PA18_TXD0   (AT91C_PIO_PA18)

#define AT91C_PIO_PA19   (1 << 19)

#define AT91C_PA19_RXD0   (AT91C_PIO_PA19)

#define AT91C_PA19_SPI0_NPCS3   (AT91C_PIO_PA19)

#define AT91C_PIO_PA2   (1 << 2)

#define AT91C_PA2_TCLK0   (AT91C_PIO_PA2)

#define AT91C_PA2_ADTRG1   (AT91C_PIO_PA2)

#define AT91C_PIO_PA20   (1 << 20)

#define AT91C_PA20_TXD1   (AT91C_PIO_PA20)

#define AT91C_PA20_PWMH3   (AT91C_PIO_PA20)

#define AT91C_PIO_PA21   (1 << 21)

#define AT91C_PA21_RXD1   (AT91C_PIO_PA21)

#define AT91C_PA21_PCK0   (AT91C_PIO_PA21)

#define AT91C_PIO_PA22   (1 << 22)

#define AT91C_PA22_TXD2   (AT91C_PIO_PA22)

#define AT91C_PA22_RTS1   (AT91C_PIO_PA22)

#define AT91C_PIO_PA23   (1 << 23)

#define AT91C_PA23_RXD2   (AT91C_PIO_PA23)

#define AT91C_PA23_CTS1   (AT91C_PIO_PA23)

#define AT91C_PIO_PA24   (1 << 24)

#define AT91C_PA24_TWD1   (AT91C_PIO_PA24)

#define AT91C_PA24_SCK1   (AT91C_PIO_PA24)

#define AT91C_PIO_PA25   (1 << 25)

#define AT91C_PA25_TWCK1   (AT91C_PIO_PA25)

#define AT91C_PA25_SCK2   (AT91C_PIO_PA25)

#define AT91C_PIO_PA26   (1 << 26)

#define AT91C_PA26_TD0   (AT91C_PIO_PA26)

#define AT91C_PA26_TCLK2   (AT91C_PIO_PA26)

#define AT91C_PIO_PA27   (1 << 27)

#define AT91C_PA27_RD0   (AT91C_PIO_PA27)

#define AT91C_PA27_PCK0   (AT91C_PIO_PA27)

#define AT91C_PIO_PA28   (1 << 28)

#define AT91C_PA28_TK0   (AT91C_PIO_PA28)

#define AT91C_PA28_PWMH0   (AT91C_PIO_PA28)

#define AT91C_PIO_PA29   (1 << 29)

#define AT91C_PA29_RK0   (AT91C_PIO_PA29)

#define AT91C_PA29_PWMH1   (AT91C_PIO_PA29)

#define AT91C_PIO_PA3   (1 << 3)

#define AT91C_PA3_MCI0_CK   (AT91C_PIO_PA3)

#define AT91C_PA3_PCK1   (AT91C_PIO_PA3)

#define AT91C_PIO_PA30   (1 << 30)

#define AT91C_PA30_TF0   (AT91C_PIO_PA30)

#define AT91C_PA30_TIOA2   (AT91C_PIO_PA30)

#define AT91C_PIO_PA31   (1 << 31)

#define AT91C_PA31_RF0   (AT91C_PIO_PA31)

#define AT91C_PA31_TIOB2   (AT91C_PIO_PA31)

#define AT91C_PIO_PA4   (1 << 4)

#define AT91C_PA4_MCI0_CDA   (AT91C_PIO_PA4)

#define AT91C_PA4_PWMH0   (AT91C_PIO_PA4)

#define AT91C_PIO_PA5   (1 << 5)

#define AT91C_PA5_MCI0_DA0   (AT91C_PIO_PA5)

#define AT91C_PA5_PWMH1   (AT91C_PIO_PA5)

#define AT91C_PIO_PA6   (1 << 6)

#define AT91C_PA6_MCI0_DA1   (AT91C_PIO_PA6)

#define AT91C_PA6_PWMH2   (AT91C_PIO_PA6)

#define AT91C_PIO_PA7   (1 << 7)

#define AT91C_PA7_MCI0_DA2   (AT91C_PIO_PA7)

#define AT91C_PA7_PWML0   (AT91C_PIO_PA7)

#define AT91C_PIO_PA8   (1 << 8)

#define AT91C_PA8_MCI0_DA3   (AT91C_PIO_PA8)

#define AT91C_PA8_PWML1   (AT91C_PIO_PA8)

#define AT91C_PIO_PA9   (1 << 9)

#define AT91C_PA9_TWD0   (AT91C_PIO_PA9)

#define AT91C_PA9_PWML2   (AT91C_PIO_PA9)

#define AT91C_PIO_PB0   (1 << 0)

#define AT91C_PB0_PWMH0   (AT91C_PIO_PB0)

#define AT91C_PB0_A2   (AT91C_PIO_PB0)

#define AT91C_PIO_PB1   (1 << 1)

#define AT91C_PB1_PWMH1   (AT91C_PIO_PB1)

#define AT91C_PB1_A3   (AT91C_PIO_PB1)

#define AT91C_PIO_PB10   (1 << 10)

#define AT91C_PB10_D1   (AT91C_PIO_PB10)

#define AT91C_PB10_DSR0   (AT91C_PIO_PB10)

#define AT91C_PIO_PB11   (1 << 11)

#define AT91C_PB11_D2   (AT91C_PIO_PB11)

#define AT91C_PB11_DCD0   (AT91C_PIO_PB11)

#define AT91C_PIO_PB12   (1 << 12)

#define AT91C_PB12_D3   (AT91C_PIO_PB12)

#define AT91C_PB12_RI0   (AT91C_PIO_PB12)

#define AT91C_PIO_PB13   (1 << 13)

#define AT91C_PB13_D4   (AT91C_PIO_PB13)

#define AT91C_PB13_PWMH0   (AT91C_PIO_PB13)

#define AT91C_PIO_PB14   (1 << 14)

#define AT91C_PB14_D5   (AT91C_PIO_PB14)

#define AT91C_PB14_PWMH1   (AT91C_PIO_PB14)

#define AT91C_PIO_PB15   (1 << 15)

#define AT91C_PB15_D6   (AT91C_PIO_PB15)

#define AT91C_PB15_PWMH2   (AT91C_PIO_PB15)

#define AT91C_PIO_PB16   (1 << 16)

#define AT91C_PB16_D7   (AT91C_PIO_PB16)

#define AT91C_PB16_PWMH3   (AT91C_PIO_PB16)

#define AT91C_PIO_PB17   (1 << 17)

#define AT91C_PB17_NANDOE   (AT91C_PIO_PB17)

#define AT91C_PB17_PWML0   (AT91C_PIO_PB17)

#define AT91C_PIO_PB18   (1 << 18)

#define AT91C_PB18_NANDWE   (AT91C_PIO_PB18)

#define AT91C_PB18_PWML1   (AT91C_PIO_PB18)

#define AT91C_PIO_PB19   (1 << 19)

#define AT91C_PB19_NRD   (AT91C_PIO_PB19)

#define AT91C_PB19_PWML2   (AT91C_PIO_PB19)

#define AT91C_PIO_PB2   (1 << 2)

#define AT91C_PB2_PWMH2   (AT91C_PIO_PB2)

#define AT91C_PB2_A4   (AT91C_PIO_PB2)

#define AT91C_PIO_PB20   (1 << 20)

#define AT91C_PB20_NCS0   (AT91C_PIO_PB20)

#define AT91C_PB20_PWML3   (AT91C_PIO_PB20)

#define AT91C_PIO_PB21   (1 << 21)

#define AT91C_PB21_A21_NANDALE   (AT91C_PIO_PB21)

#define AT91C_PB21_RTS2   (AT91C_PIO_PB21)

#define AT91C_PIO_PB22   (1 << 22)

#define AT91C_PB22_A22_NANDCLE   (AT91C_PIO_PB22)

#define AT91C_PB22_CTS2   (AT91C_PIO_PB22)

#define AT91C_PIO_PB23   (1 << 23)

#define AT91C_PB23_NWR0_NWE   (AT91C_PIO_PB23)

#define AT91C_PB23_PCK2   (AT91C_PIO_PB23)

#define AT91C_PIO_PB24   (1 << 24)

#define AT91C_PB24_NANDRDY   (AT91C_PIO_PB24)

#define AT91C_PB24_PCK1   (AT91C_PIO_PB24)

#define AT91C_PIO_PB25   (1 << 25)

#define AT91C_PB25_D8   (AT91C_PIO_PB25)

#define AT91C_PB25_PWML0   (AT91C_PIO_PB25)

#define AT91C_PIO_PB26   (1 << 26)

#define AT91C_PB26_D9   (AT91C_PIO_PB26)

#define AT91C_PB26_PWML1   (AT91C_PIO_PB26)

#define AT91C_PIO_PB27   (1 << 27)

#define AT91C_PB27_D10   (AT91C_PIO_PB27)

#define AT91C_PB27_PWML2   (AT91C_PIO_PB27)

#define AT91C_PIO_PB28   (1 << 28)

#define AT91C_PB28_D11   (AT91C_PIO_PB28)

#define AT91C_PB28_PWML3   (AT91C_PIO_PB28)

#define AT91C_PIO_PB29   (1 << 29)

#define AT91C_PB29_D12   (AT91C_PIO_PB29)

#define AT91C_PIO_PB3   (1 << 3)

#define AT91C_PB3_PWMH3   (AT91C_PIO_PB3)

#define AT91C_PB3_A5   (AT91C_PIO_PB3)

#define AT91C_PIO_PB30   (1 << 30)

#define AT91C_PB30_D13   (AT91C_PIO_PB30)

#define AT91C_PIO_PB31   (1 << 31)

#define AT91C_PB31_D14   (AT91C_PIO_PB31)

#define AT91C_PIO_PB4   (1 << 4)

#define AT91C_PB4_TCLK1   (AT91C_PIO_PB4)

#define AT91C_PB4_A6   (AT91C_PIO_PB4)

#define AT91C_PIO_PB5   (1 << 5)

#define AT91C_PB5_TIOA1   (AT91C_PIO_PB5)

#define AT91C_PB5_A7   (AT91C_PIO_PB5)

#define AT91C_PIO_PB6   (1 << 6)

#define AT91C_PB6_TIOB1   (AT91C_PIO_PB6)

#define AT91C_PB6_D15   (AT91C_PIO_PB6)

#define AT91C_PIO_PB7   (1 << 7)

#define AT91C_PB7_RTS0   (AT91C_PIO_PB7)

#define AT91C_PB7_A0_NBS0   (AT91C_PIO_PB7)

#define AT91C_PIO_PB8   (1 << 8)

#define AT91C_PB8_CTS0   (AT91C_PIO_PB8)

#define AT91C_PB8_A1   (AT91C_PIO_PB8)

#define AT91C_PIO_PB9   (1 << 9)

#define AT91C_PB9_D0   (AT91C_PIO_PB9)

#define AT91C_PB9_DTR0   (AT91C_PIO_PB9)

#define AT91C_PIO_PC0   (1 << 0)

#define AT91C_PC0_A2   (AT91C_PIO_PC0)

#define AT91C_PIO_PC1   (1 << 1)

#define AT91C_PC1_A3   (AT91C_PIO_PC1)

#define AT91C_PIO_PC10   (1 << 10)

#define AT91C_PC10_A12   (AT91C_PIO_PC10)

#define AT91C_PC10_CTS3   (AT91C_PIO_PC10)

#define AT91C_PIO_PC11   (1 << 11)

#define AT91C_PC11_A13   (AT91C_PIO_PC11)

#define AT91C_PC11_RTS3   (AT91C_PIO_PC11)

#define AT91C_PIO_PC12   (1 << 12)

#define AT91C_PC12_NCS1   (AT91C_PIO_PC12)

#define AT91C_PC12_TXD3   (AT91C_PIO_PC12)

#define AT91C_PIO_PC13   (1 << 13)

#define AT91C_PC13_A2   (AT91C_PIO_PC13)

#define AT91C_PC13_RXD3   (AT91C_PIO_PC13)

#define AT91C_PIO_PC14   (1 << 14)

#define AT91C_PC14_A3   (AT91C_PIO_PC14)

#define AT91C_PC14_SPI0_NPCS2   (AT91C_PIO_PC14)

#define AT91C_PIO_PC15   (1 << 15)

#define AT91C_PC15_NWR1_NBS1   (AT91C_PIO_PC15)

#define AT91C_PIO_PC16   (1 << 16)

#define AT91C_PC16_NCS2   (AT91C_PIO_PC16)

#define AT91C_PC16_PWML3   (AT91C_PIO_PC16)

#define AT91C_PIO_PC17   (1 << 17)

#define AT91C_PC17_NCS3   (AT91C_PIO_PC17)

#define AT91C_PC17_A24   (AT91C_PIO_PC17)

#define AT91C_PIO_PC18   (1 << 18)

#define AT91C_PC18_NWAIT   (AT91C_PIO_PC18)

#define AT91C_PIO_PC19   (1 << 19)

#define AT91C_PC19_SCK3   (AT91C_PIO_PC19)

#define AT91C_PC19_NPCS1   (AT91C_PIO_PC19)

#define AT91C_PIO_PC2   (1 << 2)

#define AT91C_PC2_A4   (AT91C_PIO_PC2)

#define AT91C_PIO_PC20   (1 << 20)

#define AT91C_PC20_A14   (AT91C_PIO_PC20)

#define AT91C_PIO_PC21   (1 << 21)

#define AT91C_PC21_A15   (AT91C_PIO_PC21)

#define AT91C_PIO_PC22   (1 << 22)

#define AT91C_PC22_A16   (AT91C_PIO_PC22)

#define AT91C_PIO_PC23   (1 << 23)

#define AT91C_PC23_A17   (AT91C_PIO_PC23)

#define AT91C_PIO_PC24   (1 << 24)

#define AT91C_PC24_A18   (AT91C_PIO_PC24)

#define AT91C_PC24_PWMH0   (AT91C_PIO_PC24)

#define AT91C_PIO_PC25   (1 << 25)

#define AT91C_PC25_A19   (AT91C_PIO_PC25)

#define AT91C_PC25_PWMH1   (AT91C_PIO_PC25)

#define AT91C_PIO_PC26   (1 << 26)

#define AT91C_PC26_A20   (AT91C_PIO_PC26)

#define AT91C_PC26_PWMH2   (AT91C_PIO_PC26)

#define AT91C_PIO_PC27   (1 << 27)

#define AT91C_PC27_A23   (AT91C_PIO_PC27)

#define AT91C_PC27_PWMH3   (AT91C_PIO_PC27)

#define AT91C_PIO_PC28   (1 << 28)

#define AT91C_PC28_A24   (AT91C_PIO_PC28)

#define AT91C_PC28_MCI0_DA4   (AT91C_PIO_PC28)

#define AT91C_PIO_PC29   (1 << 29)

#define AT91C_PC29_PWML0   (AT91C_PIO_PC29)

#define AT91C_PC29_MCI0_DA5   (AT91C_PIO_PC29)

#define AT91C_PIO_PC3   (1 << 3)

#define AT91C_PC3_A5   (AT91C_PIO_PC3)

#define AT91C_PC3_SPI0_NPCS1   (AT91C_PIO_PC3)

#define AT91C_PIO_PC30   (1 << 30)

#define AT91C_PC30_PWML1   (AT91C_PIO_PC30)

#define AT91C_PC30_MCI0_DA6   (AT91C_PIO_PC30)

#define AT91C_PIO_PC31   (1 << 31)

#define AT91C_PC31_PWML2   (AT91C_PIO_PC31)

#define AT91C_PC31_MCI0_DA7   (AT91C_PIO_PC31)

#define AT91C_PIO_PC4   (1 << 4)

#define AT91C_PC4_A6   (AT91C_PIO_PC4)

#define AT91C_PC4_SPI0_NPCS2   (AT91C_PIO_PC4)

#define AT91C_PIO_PC5   (1 << 5)

#define AT91C_PC5_A7   (AT91C_PIO_PC5)

#define AT91C_PC5_SPI0_NPCS3   (AT91C_PIO_PC5)

#define AT91C_PIO_PC6   (1 << 6)

#define AT91C_PC6_A8   (AT91C_PIO_PC6)

#define AT91C_PC6_PWML0   (AT91C_PIO_PC6)

#define AT91C_PIO_PC7   (1 << 7)

#define AT91C_PC7_A9   (AT91C_PIO_PC7)

#define AT91C_PC7_PWML1   (AT91C_PIO_PC7)

#define AT91C_PIO_PC8   (1 << 8)

#define AT91C_PC8_A10   (AT91C_PIO_PC8)

#define AT91C_PC8_PWML2   (AT91C_PIO_PC8)

#define AT91C_PIO_PC9   (1 << 9)

#define AT91C_PC9_A11   (AT91C_PIO_PC9)

#define AT91C_PC9_PWML3   (AT91C_PIO_PC9)

#define AT91C_ID_SUPC   ( 0)

#define AT91C_ID_RSTC   ( 1)

#define AT91C_ID_RTC   ( 2)

#define AT91C_ID_RTT   ( 3)

#define AT91C_ID_WDG   ( 4)

#define AT91C_ID_PMC   ( 5)

#define AT91C_ID_EFC0   ( 6)

#define AT91C_ID_EFC1   ( 7)

#define AT91C_ID_DBGU   ( 8)

#define AT91C_ID_HSMC4   ( 9)

#define AT91C_ID_PIOA   (10)

Referenced by GpioPortConfigSet().

#define AT91C_ID_PIOB   (11)

Referenced by GpioPortConfigSet().

#define AT91C_ID_PIOC   (12)

Referenced by GpioPortConfigSet().

#define AT91C_ID_US0   (13)

#define AT91C_ID_US1   (14)

#define AT91C_ID_US2   (15)

#define AT91C_ID_US3   (16)

#define AT91C_ID_MCI0   (17)

#define AT91C_ID_TWI0   (18)

#define AT91C_ID_TWI1   (19)

#define AT91C_ID_SPI0   (20)

#define AT91C_ID_SSC0   (21)

#define AT91C_ID_TC0   (22)

#define AT91C_ID_TC1   (23)

#define AT91C_ID_TC2   (24)

#define AT91C_ID_PWMC   (25)

#define AT91C_ID_ADC12B   (26)

#define AT91C_ID_ADC   (27)

#define AT91C_ID_HDMA   (28)

#define AT91C_ID_UDPHS   (29)

#define AT91C_ALL_INT   (0x3FFFFFFF)

#define AT91C_BASE_SYS   (AT91_CAST(AT91PS_SYS) 0x400E0000)

#define AT91C_BASE_HSMC4_CS0   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0070)

#define AT91C_BASE_HSMC4_CS1   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0084)

#define AT91C_BASE_HSMC4_CS2   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0098)

#define AT91C_BASE_HSMC4_CS3   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00AC)

#define AT91C_BASE_HSMC4_NFC   (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00FC)

#define AT91C_BASE_HSMC4   (AT91_CAST(AT91PS_HSMC4) 0x400E0000)

#define AT91C_BASE_MATRIX   (AT91_CAST(AT91PS_HMATRIX2) 0x400E0200)

#define AT91C_BASE_NVIC   (AT91_CAST(AT91PS_NVIC) 0xE000E000)

#define AT91C_BASE_MPU   (AT91_CAST(AT91PS_MPU) 0xE000ED90)

#define AT91C_BASE_CM3   (AT91_CAST(AT91PS_CM3) 0xE000ED00)

#define AT91C_BASE_PDC_DBGU   (AT91_CAST(AT91PS_PDC) 0x400E0700)

#define AT91C_BASE_DBGU   ( 0x400E0600)

#define AT91C_BASE_PIOA   (AT91_CAST(AT91PS_PIO) 0x400E0C00)

#define AT91C_BASE_PIOB   (AT91_CAST(AT91PS_PIO) 0x400E0E00)

#define AT91C_BASE_PIOC   (AT91_CAST(AT91PS_PIO) 0x400E1000)

#define AT91C_BASE_PMC   (AT91_CAST(AT91PS_PMC) 0x400E0400)

#define AT91C_BASE_CKGR   (AT91_CAST(AT91PS_CKGR) 0x400E041C)

#define AT91C_BASE_RSTC   (AT91_CAST(AT91PS_RSTC) 0x400E1200)

#define AT91C_BASE_SUPC   (AT91_CAST(AT91PS_SUPC) 0x400E1210)

#define AT91C_BASE_RTTC   (AT91_CAST(AT91PS_RTTC) 0x400E1230)

#define AT91C_BASE_WDTC   (AT91_CAST(AT91PS_WDTC) 0x400E1250)

#define AT91C_BASE_RTC   (AT91_CAST(AT91PS_RTC) 0x400E1260)

#define AT91C_BASE_ADC0   (AT91_CAST(AT91PS_ADC) 0x400AC000)

#define AT91C_BASE_ADC12B   (AT91_CAST(AT91PS_ADC12B ) 0x400A8000)

#define AT91C_BASE_TC0   (AT91_CAST(AT91PS_TC) 0x40080000)

#define AT91C_BASE_TC1   (AT91_CAST(AT91PS_TC) 0x40080040)

#define AT91C_BASE_TC2   (AT91_CAST(AT91PS_TC) 0x40080080)

#define AT91C_BASE_TCB0   (AT91_CAST(AT91PS_TCB) 0x40080000)

#define AT91C_BASE_TCB1   (AT91_CAST(AT91PS_TCB) 0x40080040)

#define AT91C_BASE_TCB2   (AT91_CAST(AT91PS_TCB) 0x40080080)

#define AT91C_BASE_EFC0   (AT91_CAST(AT91PS_EFC) 0x400E0800)

#define AT91C_BASE_EFC1   (AT91_CAST(AT91PS_EFC) 0x400E0A00)

#define AT91C_BASE_MCI0   (AT91_CAST(AT91PS_MCI) 0x40000000)

#define AT91C_BASE_PDC_TWI0   (AT91_CAST(AT91PS_PDC) 0x40084100)

#define AT91C_BASE_PDC_TWI1   (AT91_CAST(AT91PS_PDC) 0x40088100)

#define AT91C_BASE_TWI0   (AT91_CAST(AT91PS_TWI) 0x40084000)

#define AT91C_BASE_TWI1   (AT91_CAST(AT91PS_TWI) 0x40088000)

#define AT91C_BASE_PDC_US0   (AT91_CAST(AT91PS_PDC) 0x40090100)

#define AT91C_BASE_US0   (AT91_CAST(AT91PS_USART) 0x40090000)

#define AT91C_BASE_PDC_US1   (AT91_CAST(AT91PS_PDC) 0x40094100)

#define AT91C_BASE_US1   (AT91_CAST(AT91PS_USART) 0x40094000)

#define AT91C_BASE_PDC_US2   (AT91_CAST(AT91PS_PDC) 0x40098100)

#define AT91C_BASE_US2   (AT91_CAST(AT91PS_USART) 0x40098000)

#define AT91C_BASE_PDC_US3   (AT91_CAST(AT91PS_PDC) 0x4009C100)

#define AT91C_BASE_US3   (AT91_CAST(AT91PS_USART) 0x4009C000)

#define AT91C_BASE_PDC_SSC0   (AT91_CAST(AT91PS_PDC) 0x40004100)

#define AT91C_BASE_SSC0   (AT91_CAST(AT91PS_SSC) 0x40004000)

#define AT91C_BASE_PDC_PWMC   (AT91_CAST(AT91PS_PDC) 0x4008C100)

#define AT91C_BASE_PWMC_CH0   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C200)

#define AT91C_BASE_PWMC_CH1   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C220)

#define AT91C_BASE_PWMC_CH2   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C240)

#define AT91C_BASE_PWMC_CH3   (AT91_CAST(AT91PS_PWMC_CH) 0x4008C260)

#define AT91C_BASE_PWMC   (AT91_CAST(AT91PS_PWMC) 0x4008C000)

#define AT91C_BASE_SPI0   (AT91_CAST(AT91PS_SPI) 0x40008000)

#define AT91C_BASE_UDPHS_EPTFIFO   (AT91_CAST(AT91PS_UDPHS_EPTFIFO) 0x20180000)

#define AT91C_BASE_UDPHS_EPT_0   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4100)

#define AT91C_BASE_UDPHS_EPT_1   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4120)

#define AT91C_BASE_UDPHS_EPT_2   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4140)

#define AT91C_BASE_UDPHS_EPT_3   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4160)

#define AT91C_BASE_UDPHS_EPT_4   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4180)

#define AT91C_BASE_UDPHS_EPT_5   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41A0)

#define AT91C_BASE_UDPHS_EPT_6   (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41C0)

#define AT91C_BASE_UDPHS_DMA_1   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4310)

#define AT91C_BASE_UDPHS_DMA_2   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4320)

#define AT91C_BASE_UDPHS_DMA_3   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4330)

#define AT91C_BASE_UDPHS_DMA_4   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4340)

#define AT91C_BASE_UDPHS_DMA_5   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4350)

#define AT91C_BASE_UDPHS_DMA_6   (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4360)

#define AT91C_BASE_UDPHS   (AT91_CAST(AT91PS_UDPHS) 0x400A4000)

#define AT91C_BASE_HDMA_CH_0   (AT91_CAST(AT91PS_HDMA_CH) 0x400B003C)

#define AT91C_BASE_HDMA_CH_1   (AT91_CAST(AT91PS_HDMA_CH) 0x400B0064)

#define AT91C_BASE_HDMA_CH_2   (AT91_CAST(AT91PS_HDMA_CH) 0x400B008C)

#define AT91C_BASE_HDMA_CH_3   (AT91_CAST(AT91PS_HDMA_CH) 0x400B00B4)

#define AT91C_BASE_HDMA   (AT91_CAST(AT91PS_HDMA) 0x400B0000)

#define AT91C_ITCM   (0x00100000)

#define AT91C_ITCM_SIZE   (0x00010000)

#define AT91C_DTCM   (0x00200000)

#define AT91C_DTCM_SIZE   (0x00010000)

#define AT91C_IRAM   (0x20000000)

#define AT91C_IRAM_SIZE   (0x00008000)

#define AT91C_IRAM_MIN   (0x00300000)

#define AT91C_IRAM_MIN_SIZE   (0x00004000)

#define AT91C_IROM   (0x00180000)

#define AT91C_IROM_SIZE   (0x00008000)

#define AT91C_IFLASH0   (0x00080000)

#define AT91C_IFLASH0_SIZE   (0x00020000)

#define AT91C_IFLASH0_PAGE_SIZE   (256)

#define AT91C_IFLASH0_LOCK_REGION_SIZE   (8192)

#define AT91C_IFLASH0_NB_OF_PAGES   (512)

#define AT91C_IFLASH0_NB_OF_LOCK_BITS   (16)

#define AT91C_IFLASH1   (0x00100000)

#define AT91C_IFLASH1_SIZE   (0x00020000)

#define AT91C_IFLASH1_PAGE_SIZE   (256)

#define AT91C_IFLASH1_LOCK_REGION_SIZE   (8192)

#define AT91C_IFLASH1_NB_OF_PAGES   (512)

#define AT91C_IFLASH1_NB_OF_LOCK_BITS   (16)

#define AT91C_EBI_CS0   (0x10000000)

#define AT91C_EBI_CS0_SIZE   (0x10000000)

#define AT91C_EBI_CS1   (0x20000000)

#define AT91C_EBI_CS1_SIZE   (0x10000000)

#define AT91C_EBI_SDRAM   (0x20000000)

#define AT91C_EBI_SDRAM_SIZE   (0x10000000)

#define AT91C_EBI_SDRAM_16BIT   (0x20000000)

#define AT91C_EBI_SDRAM_16BIT_SIZE   (0x02000000)

#define AT91C_EBI_SDRAM_32BIT   (0x20000000)

#define AT91C_EBI_SDRAM_32BIT_SIZE   (0x04000000)

#define AT91C_EBI_CS2   (0x30000000)

#define AT91C_EBI_CS2_SIZE   (0x10000000)

#define AT91C_EBI_CS3   (0x40000000)

#define AT91C_EBI_CS3_SIZE   (0x10000000)

#define AT91C_EBI_SM   (0x40000000)

#define AT91C_EBI_SM_SIZE   (0x10000000)

#define AT91C_EBI_CS4   (0x50000000)

#define AT91C_EBI_CS4_SIZE   (0x10000000)

#define AT91C_EBI_CF0   (0x50000000)

#define AT91C_EBI_CF0_SIZE   (0x10000000)

#define AT91C_EBI_CS5   (0x60000000)

#define AT91C_EBI_CS5_SIZE   (0x10000000)

#define AT91C_EBI_CF1   (0x60000000)

#define AT91C_EBI_CF1_SIZE   (0x10000000)

---

Typedef Documentation

typedef volatile unsigned int AT91_REG

typedef struct _AT91S_UDPHS_EPTFIFO AT91S_UDPHS_EPTFIFO

typedef struct _AT91S_UDPHS_EPTFIFO * AT91PS_UDPHS_EPTFIFO

typedef struct _AT91S_UDPHS_EPT AT91S_UDPHS_EPT

typedef struct _AT91S_UDPHS_EPT * AT91PS_UDPHS_EPT

typedef struct _AT91S_UDPHS_DMA AT91S_UDPHS_DMA

typedef struct _AT91S_UDPHS_DMA * AT91PS_UDPHS_DMA

typedef struct _AT91S_UDPHS AT91S_UDPHS

typedef struct _AT91S_UDPHS * AT91PS_UDPHS

typedef enum IRQn IRQn_Type

Interrupt source.

---

Enumeration Type Documentation

enum IRQn

Interrupt source.

Enumerator:

NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
IROn_SUPC
IROn_RSTC
IROn_RTC
IROn_RTT
IROn_WDG
IROn_PMC
IROn_EFC0
IROn_EFC1
IROn_DBGU
IROn_HSMC4
IROn_PIOA
IROn_PIOB
IROn_PIOC
IROn_US0
IROn_US1
IROn_US2
IROn_US3
IROn_MCI0
IROn_TWI0
IROn_TWI1
IROn_SPI0
IROn_SSC0
IROn_TC0
IROn_TC1
IROn_TC2
IROn_PWMC
IROn_ADCC0
IROn_ADCC1
IROn_HDMA
IROn_UDPHS
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
SPI_IRQn	SPI Interrupt
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
RIT_IRQn	Repetitive Interrupt Timer Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
Reserved0_IRQn	Reserved
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
MCI_IRQn	SD/MMC card I/F Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt
USBActivity_IRQn	USB Activity interrupt
CANActivity_IRQn	CAN Activity interrupt
UART4_IRQn	UART4 Interrupt
SSP2_IRQn	SSP2 Interrupt
LCD_IRQn	LCD Interrupt
GPIO_IRQn	GPIO Interrupt
PWM0_IRQn	PWM0 Interrupt
EEPROM_IRQn	EEPROM Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMPER_IRQn	Tamper Interrupt
RTC_IRQn	RTC global Interrupt
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn	DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn	DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn	DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn	DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn	DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn	DMA1 Channel 7 global Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMP_STAMP_IRQn	Tamper and TimeStamp interrupts through the EXTI line
RTC_WKUP_IRQn	RTC Wakeup interrupt through the EXTI line
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Stream0_IRQn	DMA1 Stream 0 global Interrupt
DMA1_Stream1_IRQn	DMA1 Stream 1 global Interrupt
DMA1_Stream2_IRQn	DMA1 Stream 2 global Interrupt
DMA1_Stream3_IRQn	DMA1 Stream 3 global Interrupt
DMA1_Stream4_IRQn	DMA1 Stream 4 global Interrupt
DMA1_Stream5_IRQn	DMA1 Stream 5 global Interrupt
DMA1_Stream6_IRQn	DMA1 Stream 6 global Interrupt
ADC_IRQn	ADC1, ADC2 and ADC3 global Interrupts
CAN1_TX_IRQn	CAN1 TX Interrupt
CAN1_RX0_IRQn	CAN1 RX0 Interrupt
CAN1_RX1_IRQn	CAN1 RX1 Interrupt
CAN1_SCE_IRQn	CAN1 SCE Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
TIM1_BRK_TIM9_IRQn	TIM1 Break interrupt and TIM9 global interrupt
TIM1_UP_TIM10_IRQn	TIM1 Update Interrupt and TIM10 global interrupt
TIM1_TRG_COM_TIM11_IRQn	TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt
TIM1_CC_IRQn	TIM1 Capture Compare Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm (A and B) through EXTI Line Interrupt
OTG_FS_WKUP_IRQn	USB OTG FS Wakeup through EXTI line interrupt
TIM8_BRK_TIM12_IRQn	TIM8 Break Interrupt and TIM12 global interrupt
TIM8_UP_TIM13_IRQn	TIM8 Update Interrupt and TIM13 global interrupt
TIM8_TRG_COM_TIM14_IRQn	TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
TIM8_CC_IRQn	TIM8 Capture Compare Interrupt
DMA1_Stream7_IRQn	DMA1 Stream7 Interrupt
FSMC_IRQn	FSMC global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
TIM6_DAC_IRQn	TIM6 global and DAC1&2 underrun error interrupts
TIM7_IRQn	TIM7 global interrupt
DMA2_Stream0_IRQn	DMA2 Stream 0 global Interrupt
DMA2_Stream1_IRQn	DMA2 Stream 1 global Interrupt
DMA2_Stream2_IRQn	DMA2 Stream 2 global Interrupt
DMA2_Stream3_IRQn	DMA2 Stream 3 global Interrupt
DMA2_Stream4_IRQn	DMA2 Stream 4 global Interrupt
ETH_IRQn	Ethernet global Interrupt
ETH_WKUP_IRQn	Ethernet Wakeup through EXTI line Interrupt
CAN2_TX_IRQn	CAN2 TX Interrupt
CAN2_RX0_IRQn	CAN2 RX0 Interrupt
CAN2_RX1_IRQn	CAN2 RX1 Interrupt
CAN2_SCE_IRQn	CAN2 SCE Interrupt
OTG_FS_IRQn	USB OTG FS global Interrupt
DMA2_Stream5_IRQn	DMA2 Stream 5 global interrupt
DMA2_Stream6_IRQn	DMA2 Stream 6 global interrupt
DMA2_Stream7_IRQn	DMA2 Stream 7 global interrupt
USART6_IRQn	USART6 global interrupt
I2C3_EV_IRQn	I2C3 event interrupt
I2C3_ER_IRQn	I2C3 error interrupt
OTG_HS_EP1_OUT_IRQn	USB OTG HS End Point 1 Out global interrupt
OTG_HS_EP1_IN_IRQn	USB OTG HS End Point 1 In global interrupt
OTG_HS_WKUP_IRQn	USB OTG HS Wakeup through EXTI interrupt
OTG_HS_IRQn	USB OTG HS global interrupt
DCMI_IRQn	DCMI global interrupt
CRYP_IRQn	CRYP crypto global interrupt
HASH_RNG_IRQn	Hash and Rng global interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M4 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMP_STAMP_IRQn	Tamper and TimeStamp interrupts through the EXTI line
RTC_WKUP_IRQn	RTC Wakeup interrupt through the EXTI line
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Stream0_IRQn	DMA1 Stream 0 global Interrupt
DMA1_Stream1_IRQn	DMA1 Stream 1 global Interrupt
DMA1_Stream2_IRQn	DMA1 Stream 2 global Interrupt
DMA1_Stream3_IRQn	DMA1 Stream 3 global Interrupt
DMA1_Stream4_IRQn	DMA1 Stream 4 global Interrupt
DMA1_Stream5_IRQn	DMA1 Stream 5 global Interrupt
DMA1_Stream6_IRQn	DMA1 Stream 6 global Interrupt
ADC_IRQn	ADC1, ADC2 and ADC3 global Interrupts
CAN1_TX_IRQn	CAN1 TX Interrupt
CAN1_RX0_IRQn	CAN1 RX0 Interrupt
CAN1_RX1_IRQn	CAN1 RX1 Interrupt
CAN1_SCE_IRQn	CAN1 SCE Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
TIM1_BRK_TIM9_IRQn	TIM1 Break interrupt and TIM9 global interrupt
TIM1_UP_TIM10_IRQn	TIM1 Update Interrupt and TIM10 global interrupt
TIM1_TRG_COM_TIM11_IRQn	TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt
TIM1_CC_IRQn	TIM1 Capture Compare Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm (A and B) through EXTI Line Interrupt
OTG_FS_WKUP_IRQn	USB OTG FS Wakeup through EXTI line interrupt
TIM8_BRK_TIM12_IRQn	TIM8 Break Interrupt and TIM12 global interrupt
TIM8_UP_TIM13_IRQn	TIM8 Update Interrupt and TIM13 global interrupt
TIM8_TRG_COM_TIM14_IRQn	TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
TIM8_CC_IRQn	TIM8 Capture Compare Interrupt
DMA1_Stream7_IRQn	DMA1 Stream7 Interrupt
FSMC_IRQn	FSMC global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
TIM6_DAC_IRQn	TIM6 global and DAC1&2 underrun error interrupts
TIM7_IRQn	TIM7 global interrupt
DMA2_Stream0_IRQn	DMA2 Stream 0 global Interrupt
DMA2_Stream1_IRQn	DMA2 Stream 1 global Interrupt
DMA2_Stream2_IRQn	DMA2 Stream 2 global Interrupt
DMA2_Stream3_IRQn	DMA2 Stream 3 global Interrupt
DMA2_Stream4_IRQn	DMA2 Stream 4 global Interrupt
ETH_IRQn	Ethernet global Interrupt
ETH_WKUP_IRQn	Ethernet Wakeup through EXTI line Interrupt
CAN2_TX_IRQn	CAN2 TX Interrupt
CAN2_RX0_IRQn	CAN2 RX0 Interrupt
CAN2_RX1_IRQn	CAN2 RX1 Interrupt
CAN2_SCE_IRQn	CAN2 SCE Interrupt
OTG_FS_IRQn	USB OTG FS global Interrupt
DMA2_Stream5_IRQn	DMA2 Stream 5 global interrupt
DMA2_Stream6_IRQn	DMA2 Stream 6 global interrupt
DMA2_Stream7_IRQn	DMA2 Stream 7 global interrupt
USART6_IRQn	USART6 global interrupt
I2C3_EV_IRQn	I2C3 event interrupt
I2C3_ER_IRQn	I2C3 error interrupt
OTG_HS_EP1_OUT_IRQn	USB OTG HS End Point 1 Out global interrupt
OTG_HS_EP1_IN_IRQn	USB OTG HS End Point 1 In global interrupt
OTG_HS_WKUP_IRQn	USB OTG HS Wakeup through EXTI interrupt
OTG_HS_IRQn	USB OTG HS global interrupt
DCMI_IRQn	DCMI global interrupt
CRYP_IRQn	CRYP crypto global interrupt
HASH_RNG_IRQn	Hash and Rng global interrupt
FPU_IRQn	FPU global interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVC_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMPER_STAMP_IRQn	Tamper and Time Stamp through EXTI Line Interrupts
RTC_WKUP_IRQn	RTC Wakeup Timer through EXTI Line Interrupt
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn	DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn	DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn	DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn	DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn	DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn	DMA1 Channel 7 global Interrupt
ADC1_IRQn	ADC1 global Interrupt
USB_HP_IRQn	USB High Priority Interrupt
USB_LP_IRQn	USB Low Priority Interrupt
DAC_IRQn	DAC Interrupt
COMP_IRQn	Comparator through EXTI Line Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
LCD_IRQn	LCD Interrupt
TIM9_IRQn	TIM9 global Interrupt
TIM10_IRQn	TIM10 global Interrupt
TIM11_IRQn	TIM11 global Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm through EXTI Line Interrupt
USB_FS_WKUP_IRQn	USB FS WakeUp from suspend through EXTI Line Interrupt
TIM6_IRQn	TIM6 global Interrupt
TIM7_IRQn	TIM7 global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
DMA2_Channel1_IRQn	DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn	DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn	DMA2 Channel 3 global Interrupt
DMA2_Channel4_IRQn	DMA2 Channel 4 global Interrupt
DMA2_Channel5_IRQn	DMA2 Channel 5 global Interrupt
AES_IRQn	AES global Interrupt
COMP_ACQ_IRQn	Comparator Channel Acquisition global Interrupt