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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 // ---------------------------------------------------------------------------- 00002 // ATMEL Microcontroller Software Support - ROUSSET - 00003 // ---------------------------------------------------------------------------- 00004 // Copyright (c) 2008, Atmel Corporation 00005 // 00006 // All rights reserved. 00007 // 00008 // Redistribution and use in source and binary forms, with or without 00009 // modification, are permitted provided that the following conditions are met: 00010 // 00011 // - Redistributions of source code must retain the above copyright notice, 00012 // this list of conditions and the disclaimer below. 00013 // 00014 // Atmel's name may not be used to endorse or promote products derived from 00015 // this software without specific prior written permission. 00016 // 00017 // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR 00018 // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 00019 // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 00020 // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, 00021 // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 00022 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 00023 // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 00024 // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 00025 // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 00026 // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00027 // ---------------------------------------------------------------------------- 00028 // File Name : AT91SAM3U4.h 00029 // Object : AT91SAM3U4 definitions 00030 // Generated : AT91 SW Application Group 05/27/2009 (14:19:03) 00031 // 00032 // ---------------------------------------------------------------------------- 00033 00034 #ifndef __SAM3U4_H__ 00035 #define __SAM3U4_H__ 00036 00037 #ifndef __ASSEMBLY__ 00038 typedef volatile unsigned int AT91_REG;// Hardware register definition 00039 #define AT91_CAST(a) (a) 00040 #else 00041 #define AT91_CAST(a) 00042 #endif 00043 00044 // ***************************************************************************** 00045 // SOFTWARE API DEFINITION FOR System Peripherals 00046 // ***************************************************************************** 00047 #ifndef __ASSEMBLY__ 00048 #else 00049 #define GPBR (AT91_CAST(AT91_REG *) 0x00001290) // (GPBR) General Purpose Register 00050 00051 #endif 00052 // -------- GPBR : (SYS Offset: 0x1290) GPBR General Purpose Register -------- 00053 #define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value 00054 00055 // ***************************************************************************** 00056 // SOFTWARE API DEFINITION FOR HSMC4 Chip Select interface 00057 // ***************************************************************************** 00058 #ifndef __ASSEMBLY__ 00059 #else 00060 #define HSMC4_SETUP (AT91_CAST(AT91_REG *) 0x00000000) // (HSMC4_SETUP) Setup Register 00061 #define HSMC4_PULSE (AT91_CAST(AT91_REG *) 0x00000004) // (HSMC4_PULSE) Pulse Register 00062 #define HSMC4_CYCLE (AT91_CAST(AT91_REG *) 0x00000008) // (HSMC4_CYCLE) Cycle Register 00063 #define HSMC4_TIMINGS (AT91_CAST(AT91_REG *) 0x0000000C) // (HSMC4_TIMINGS) Timmings Register 00064 #define HSMC4_MODE (AT91_CAST(AT91_REG *) 0x00000010) // (HSMC4_MODE) Mode Register 00065 00066 #endif 00067 // -------- HSMC4_SETUP : (HSMC4_CS Offset: 0x0) HSMC4 SETUP -------- 00068 #define AT91C_HSMC4_NWE_SETUP (0x3F << 0) // (HSMC4_CS) NWE Setup length 00069 #define AT91C_HSMC4_NCS_WR_SETUP (0x3F << 8) // (HSMC4_CS) NCS Setup length in Write access 00070 #define AT91C_HSMC4_NRD_SETUP (0x3F << 16) // (HSMC4_CS) NRD Setup length 00071 #define AT91C_HSMC4_NCS_RD_SETUP (0x3F << 24) // (HSMC4_CS) NCS Setup legnth in Read access 00072 // -------- HSMC4_PULSE : (HSMC4_CS Offset: 0x4) HSMC4 PULSE -------- 00073 #define AT91C_HSMC4_NWE_PULSE (0x3F << 0) // (HSMC4_CS) NWE Pulse Length 00074 #define AT91C_HSMC4_NCS_WR_PULSE (0x3F << 8) // (HSMC4_CS) NCS Pulse length in WRITE access 00075 #define AT91C_HSMC4_NRD_PULSE (0x3F << 16) // (HSMC4_CS) NRD Pulse length 00076 #define AT91C_HSMC4_NCS_RD_PULSE (0x3F << 24) // (HSMC4_CS) NCS Pulse length in READ access 00077 // -------- HSMC4_CYCLE : (HSMC4_CS Offset: 0x8) HSMC4 CYCLE -------- 00078 #define AT91C_HSMC4_NWE_CYCLE (0x1FF << 0) // (HSMC4_CS) Total Write Cycle Length 00079 #define AT91C_HSMC4_NRD_CYCLE (0x1FF << 16) // (HSMC4_CS) Total Read Cycle Length 00080 // -------- HSMC4_TIMINGS : (HSMC4_CS Offset: 0xc) HSMC4 TIMINGS -------- 00081 #define AT91C_HSMC4_TCLR (0xF << 0) // (HSMC4_CS) CLE to REN low delay 00082 #define AT91C_HSMC4_TADL (0xF << 4) // (HSMC4_CS) ALE to data start 00083 #define AT91C_HSMC4_TAR (0xF << 8) // (HSMC4_CS) ALE to REN low delay 00084 #define AT91C_HSMC4_OCMSEN (0x1 << 12) // (HSMC4_CS) Off Chip Memory Scrambling Enable 00085 #define AT91C_HSMC4_TRR (0xF << 16) // (HSMC4_CS) Ready to REN low delay 00086 #define AT91C_HSMC4_TWB (0xF << 24) // (HSMC4_CS) WEN high to REN to busy 00087 #define AT91C_HSMC4_RBNSEL (0x7 << 28) // (HSMC4_CS) Ready/Busy Line Selection 00088 #define AT91C_HSMC4_NFSEL (0x1 << 31) // (HSMC4_CS) Nand Flash Selection 00089 // -------- HSMC4_MODE : (HSMC4_CS Offset: 0x10) HSMC4 MODE -------- 00090 #define AT91C_HSMC4_READ_MODE (0x1 << 0) // (HSMC4_CS) Read Mode 00091 #define AT91C_HSMC4_WRITE_MODE (0x1 << 1) // (HSMC4_CS) Write Mode 00092 #define AT91C_HSMC4_EXNW_MODE (0x3 << 4) // (HSMC4_CS) NWAIT Mode 00093 #define AT91C_HSMC4_EXNW_MODE_NWAIT_DISABLE (0x0 << 4) // (HSMC4_CS) External NWAIT disabled. 00094 #define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_FROZEN (0x2 << 4) // (HSMC4_CS) External NWAIT enabled in frozen mode. 00095 #define AT91C_HSMC4_EXNW_MODE_NWAIT_ENABLE_READY (0x3 << 4) // (HSMC4_CS) External NWAIT enabled in ready mode. 00096 #define AT91C_HSMC4_BAT (0x1 << 8) // (HSMC4_CS) Byte Access Type 00097 #define AT91C_HSMC4_BAT_BYTE_SELECT (0x0 << 8) // (HSMC4_CS) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. 00098 #define AT91C_HSMC4_BAT_BYTE_WRITE (0x1 << 8) // (HSMC4_CS) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. 00099 #define AT91C_HSMC4_DBW (0x3 << 12) // (HSMC4_CS) Data Bus Width 00100 #define AT91C_HSMC4_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (HSMC4_CS) 8 bits. 00101 #define AT91C_HSMC4_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (HSMC4_CS) 16 bits. 00102 #define AT91C_HSMC4_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (HSMC4_CS) 32 bits. 00103 #define AT91C_HSMC4_TDF_CYCLES (0xF << 16) // (HSMC4_CS) Data Float Time. 00104 #define AT91C_HSMC4_TDF_MODE (0x1 << 20) // (HSMC4_CS) TDF Enabled. 00105 #define AT91C_HSMC4_PMEN (0x1 << 24) // (HSMC4_CS) Page Mode Enabled. 00106 #define AT91C_HSMC4_PS (0x3 << 28) // (HSMC4_CS) Page Size 00107 #define AT91C_HSMC4_PS_SIZE_FOUR_BYTES (0x0 << 28) // (HSMC4_CS) 4 bytes. 00108 #define AT91C_HSMC4_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (HSMC4_CS) 8 bytes. 00109 #define AT91C_HSMC4_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (HSMC4_CS) 16 bytes. 00110 #define AT91C_HSMC4_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (HSMC4_CS) 32 bytes. 00111 00112 // ***************************************************************************** 00113 // SOFTWARE API DEFINITION FOR AHB Static Memory Controller 4 Interface 00114 // ***************************************************************************** 00115 #ifndef __ASSEMBLY__ 00116 #else 00117 #define HSMC4_CFG (AT91_CAST(AT91_REG *) 0x00000000) // (HSMC4_CFG) Configuration Register 00118 #define HSMC4_CTRL (AT91_CAST(AT91_REG *) 0x00000004) // (HSMC4_CTRL) Control Register 00119 #define HSMC4_SR (AT91_CAST(AT91_REG *) 0x00000008) // (HSMC4_SR) Status Register 00120 #define HSMC4_IER (AT91_CAST(AT91_REG *) 0x0000000C) // (HSMC4_IER) Interrupt Enable Register 00121 #define HSMC4_IDR (AT91_CAST(AT91_REG *) 0x00000010) // (HSMC4_IDR) Interrupt Disable Register 00122 #define HSMC4_IMR (AT91_CAST(AT91_REG *) 0x00000014) // (HSMC4_IMR) Interrupt Mask Register 00123 #define HSMC4_ADDR (AT91_CAST(AT91_REG *) 0x00000018) // (HSMC4_ADDR) Address Cycle Zero Register 00124 #define HSMC4_BANK (AT91_CAST(AT91_REG *) 0x0000001C) // (HSMC4_BANK) Bank Register 00125 #define HSMC4_ECCCR (AT91_CAST(AT91_REG *) 0x00000020) // (HSMC4_ECCCR) ECC reset register 00126 #define HSMC4_ECCCMD (AT91_CAST(AT91_REG *) 0x00000024) // (HSMC4_ECCCMD) ECC Page size register 00127 #define HSMC4_ECCSR1 (AT91_CAST(AT91_REG *) 0x00000028) // (HSMC4_ECCSR1) ECC Status register 1 00128 #define HSMC4_ECCPR0 (AT91_CAST(AT91_REG *) 0x0000002C) // (HSMC4_ECCPR0) ECC Parity register 0 00129 #define HSMC4_ECCPR1 (AT91_CAST(AT91_REG *) 0x00000030) // (HSMC4_ECCPR1) ECC Parity register 1 00130 #define HSMC4_ECCSR2 (AT91_CAST(AT91_REG *) 0x00000034) // (HSMC4_ECCSR2) ECC Status register 2 00131 #define HSMC4_ECCPR2 (AT91_CAST(AT91_REG *) 0x00000038) // (HSMC4_ECCPR2) ECC Parity register 2 00132 #define HSMC4_ECCPR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (HSMC4_ECCPR3) ECC Parity register 3 00133 #define HSMC4_ECCPR4 (AT91_CAST(AT91_REG *) 0x00000040) // (HSMC4_ECCPR4) ECC Parity register 4 00134 #define HSMC4_ECCPR5 (AT91_CAST(AT91_REG *) 0x00000044) // (HSMC4_ECCPR5) ECC Parity register 5 00135 #define HSMC4_ECCPR6 (AT91_CAST(AT91_REG *) 0x00000048) // (HSMC4_ECCPR6) ECC Parity register 6 00136 #define HSMC4_ECCPR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (HSMC4_ECCPR7) ECC Parity register 7 00137 #define HSMC4_ECCPR8 (AT91_CAST(AT91_REG *) 0x00000050) // (HSMC4_ECCPR8) ECC Parity register 8 00138 #define HSMC4_ECCPR9 (AT91_CAST(AT91_REG *) 0x00000054) // (HSMC4_ECCPR9) ECC Parity register 9 00139 #define HSMC4_ECCPR10 (AT91_CAST(AT91_REG *) 0x00000058) // (HSMC4_ECCPR10) ECC Parity register 10 00140 #define HSMC4_ECCPR11 (AT91_CAST(AT91_REG *) 0x0000005C) // (HSMC4_ECCPR11) ECC Parity register 11 00141 #define HSMC4_ECCPR12 (AT91_CAST(AT91_REG *) 0x00000060) // (HSMC4_ECCPR12) ECC Parity register 12 00142 #define HSMC4_ECCPR13 (AT91_CAST(AT91_REG *) 0x00000064) // (HSMC4_ECCPR13) ECC Parity register 13 00143 #define HSMC4_ECCPR14 (AT91_CAST(AT91_REG *) 0x00000068) // (HSMC4_ECCPR14) ECC Parity register 14 00144 #define Hsmc4_Eccpr15 (AT91_CAST(AT91_REG *) 0x0000006C) // (Hsmc4_Eccpr15) ECC Parity register 15 00145 #define HSMC4_OCMS (AT91_CAST(AT91_REG *) 0x00000110) // (HSMC4_OCMS) OCMS MODE register 00146 #define HSMC4_KEY1 (AT91_CAST(AT91_REG *) 0x00000114) // (HSMC4_KEY1) KEY1 Register 00147 #define HSMC4_KEY2 (AT91_CAST(AT91_REG *) 0x00000118) // (HSMC4_KEY2) KEY2 Register 00148 #define HSMC4_WPCR (AT91_CAST(AT91_REG *) 0x000001E4) // (HSMC4_WPCR) Write Protection Control register 00149 #define HSMC4_WPSR (AT91_CAST(AT91_REG *) 0x000001E8) // (HSMC4_WPSR) Write Protection Status Register 00150 #define HSMC4_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000001EC) // (HSMC4_ADDRSIZE) Write Protection Status Register 00151 #define HSMC4_IPNAME1 (AT91_CAST(AT91_REG *) 0x000001F0) // (HSMC4_IPNAME1) Write Protection Status Register 00152 #define HSMC4_IPNAME2 (AT91_CAST(AT91_REG *) 0x000001F4) // (HSMC4_IPNAME2) Write Protection Status Register 00153 #define HSMC4_FEATURES (AT91_CAST(AT91_REG *) 0x000001F8) // (HSMC4_FEATURES) Write Protection Status Register 00154 #define HSMC4_VER (AT91_CAST(AT91_REG *) 0x000001FC) // (HSMC4_VER) HSMC4 Version Register 00155 #define HSMC4_DUMMY (AT91_CAST(AT91_REG *) 0x00000200) // (HSMC4_DUMMY) This rtegister was created only ti have AHB constants 00156 00157 #endif 00158 // -------- HSMC4_CFG : (HSMC4 Offset: 0x0) Configuration Register -------- 00159 #define AT91C_HSMC4_PAGESIZE (0x3 << 0) // (HSMC4) PAGESIZE field description 00160 #define AT91C_HSMC4_PAGESIZE_528_Bytes (0x0) // (HSMC4) 512 bytes plus 16 bytes page size 00161 #define AT91C_HSMC4_PAGESIZE_1056_Bytes (0x1) // (HSMC4) 1024 bytes plus 32 bytes page size 00162 #define AT91C_HSMC4_PAGESIZE_2112_Bytes (0x2) // (HSMC4) 2048 bytes plus 64 bytes page size 00163 #define AT91C_HSMC4_PAGESIZE_4224_Bytes (0x3) // (HSMC4) 4096 bytes plus 128 bytes page size 00164 #define AT91C_HSMC4_WSPARE (0x1 << 8) // (HSMC4) Spare area access in Write Mode 00165 #define AT91C_HSMC4_RSPARE (0x1 << 9) // (HSMC4) Spare area access in Read Mode 00166 #define AT91C_HSMC4_EDGECTRL (0x1 << 12) // (HSMC4) Rising/Falling Edge Detection Control 00167 #define AT91C_HSMC4_RBEDGE (0x1 << 13) // (HSMC4) Ready/Busy Signal edge Detection 00168 #define AT91C_HSMC4_DTOCYC (0xF << 16) // (HSMC4) Data Timeout Cycle Number 00169 #define AT91C_HSMC4_DTOMUL (0x7 << 20) // (HSMC4) Data Timeout Multiplier 00170 #define AT91C_HSMC4_DTOMUL_1 (0x0 << 20) // (HSMC4) DTOCYC x 1 00171 #define AT91C_HSMC4_DTOMUL_16 (0x1 << 20) // (HSMC4) DTOCYC x 16 00172 #define AT91C_HSMC4_DTOMUL_128 (0x2 << 20) // (HSMC4) DTOCYC x 128 00173 #define AT91C_HSMC4_DTOMUL_256 (0x3 << 20) // (HSMC4) DTOCYC x 256 00174 #define AT91C_HSMC4_DTOMUL_1024 (0x4 << 20) // (HSMC4) DTOCYC x 1024 00175 #define AT91C_HSMC4_DTOMUL_4096 (0x5 << 20) // (HSMC4) DTOCYC x 4096 00176 #define AT91C_HSMC4_DTOMUL_65536 (0x6 << 20) // (HSMC4) DTOCYC x 65536 00177 #define AT91C_HSMC4_DTOMUL_1048576 (0x7 << 20) // (HSMC4) DTOCYC x 1048576 00178 // -------- HSMC4_CTRL : (HSMC4 Offset: 0x4) Control Register -------- 00179 #define AT91C_HSMC4_NFCEN (0x1 << 0) // (HSMC4) Nand Flash Controller Host Enable 00180 #define AT91C_HSMC4_NFCDIS (0x1 << 1) // (HSMC4) Nand Flash Controller Host Disable 00181 #define AT91C_HSMC4_HOSTEN (0x1 << 8) // (HSMC4) If set to one, the Host controller is activated and perform a data transfer phase. 00182 #define AT91C_HSMC4_HOSTWR (0x1 << 11) // (HSMC4) If this field is set to one, the host transfers data from the internal SRAM to the Memory Device. 00183 #define AT91C_HSMC4_HOSTCSID (0x7 << 12) // (HSMC4) Host Controller Chip select Id 00184 #define AT91C_HSMC4_HOSTCSID_0 (0x0 << 12) // (HSMC4) CS0 00185 #define AT91C_HSMC4_HOSTCSID_1 (0x1 << 12) // (HSMC4) CS1 00186 #define AT91C_HSMC4_HOSTCSID_2 (0x2 << 12) // (HSMC4) CS2 00187 #define AT91C_HSMC4_HOSTCSID_3 (0x3 << 12) // (HSMC4) CS3 00188 #define AT91C_HSMC4_HOSTCSID_4 (0x4 << 12) // (HSMC4) CS4 00189 #define AT91C_HSMC4_HOSTCSID_5 (0x5 << 12) // (HSMC4) CS5 00190 #define AT91C_HSMC4_HOSTCSID_6 (0x6 << 12) // (HSMC4) CS6 00191 #define AT91C_HSMC4_HOSTCSID_7 (0x7 << 12) // (HSMC4) CS7 00192 #define AT91C_HSMC4_VALID (0x1 << 15) // (HSMC4) When set to 1, a write operation modifies both HOSTCSID and HOSTWR fields. 00193 // -------- HSMC4_SR : (HSMC4 Offset: 0x8) HSMC4 Status Register -------- 00194 #define AT91C_HSMC4_NFCSTS (0x1 << 0) // (HSMC4) Nand Flash Controller status 00195 #define AT91C_HSMC4_RBRISE (0x1 << 4) // (HSMC4) Selected Ready Busy Rising Edge Detected flag 00196 #define AT91C_HSMC4_RBFALL (0x1 << 5) // (HSMC4) Selected Ready Busy Falling Edge Detected flag 00197 #define AT91C_HSMC4_HOSTBUSY (0x1 << 8) // (HSMC4) Host Busy 00198 #define AT91C_HSMC4_HOSTW (0x1 << 11) // (HSMC4) Host Write/Read Operation 00199 #define AT91C_HSMC4_HOSTCS (0x7 << 12) // (HSMC4) Host Controller Chip select Id 00200 #define AT91C_HSMC4_HOSTCS_0 (0x0 << 12) // (HSMC4) CS0 00201 #define AT91C_HSMC4_HOSTCS_1 (0x1 << 12) // (HSMC4) CS1 00202 #define AT91C_HSMC4_HOSTCS_2 (0x2 << 12) // (HSMC4) CS2 00203 #define AT91C_HSMC4_HOSTCS_3 (0x3 << 12) // (HSMC4) CS3 00204 #define AT91C_HSMC4_HOSTCS_4 (0x4 << 12) // (HSMC4) CS4 00205 #define AT91C_HSMC4_HOSTCS_5 (0x5 << 12) // (HSMC4) CS5 00206 #define AT91C_HSMC4_HOSTCS_6 (0x6 << 12) // (HSMC4) CS6 00207 #define AT91C_HSMC4_HOSTCS_7 (0x7 << 12) // (HSMC4) CS7 00208 #define AT91C_HSMC4_XFRDONE (0x1 << 16) // (HSMC4) Host Data Transfer Terminated 00209 #define AT91C_HSMC4_CMDDONE (0x1 << 17) // (HSMC4) Command Done 00210 #define AT91C_HSMC4_ECCRDY (0x1 << 18) // (HSMC4) ECC ready 00211 #define AT91C_HSMC4_DTOE (0x1 << 20) // (HSMC4) Data timeout Error 00212 #define AT91C_HSMC4_UNDEF (0x1 << 21) // (HSMC4) Undefined Area Error 00213 #define AT91C_HSMC4_AWB (0x1 << 22) // (HSMC4) Accessing While Busy Error 00214 #define AT91C_HSMC4_HASE (0x1 << 23) // (HSMC4) Host Controller Access Size Error 00215 #define AT91C_HSMC4_RBEDGE0 (0x1 << 24) // (HSMC4) Ready Busy line 0 Edge detected 00216 #define AT91C_HSMC4_RBEDGE1 (0x1 << 25) // (HSMC4) Ready Busy line 1 Edge detected 00217 #define AT91C_HSMC4_RBEDGE2 (0x1 << 26) // (HSMC4) Ready Busy line 2 Edge detected 00218 #define AT91C_HSMC4_RBEDGE3 (0x1 << 27) // (HSMC4) Ready Busy line 3 Edge detected 00219 #define AT91C_HSMC4_RBEDGE4 (0x1 << 28) // (HSMC4) Ready Busy line 4 Edge detected 00220 #define AT91C_HSMC4_RBEDGE5 (0x1 << 29) // (HSMC4) Ready Busy line 5 Edge detected 00221 #define AT91C_HSMC4_RBEDGE6 (0x1 << 30) // (HSMC4) Ready Busy line 6 Edge detected 00222 #define AT91C_HSMC4_RBEDGE7 (0x1 << 31) // (HSMC4) Ready Busy line 7 Edge detected 00223 // -------- HSMC4_IER : (HSMC4 Offset: 0xc) HSMC4 Interrupt Enable Register -------- 00224 // -------- HSMC4_IDR : (HSMC4 Offset: 0x10) HSMC4 Interrupt Disable Register -------- 00225 // -------- HSMC4_IMR : (HSMC4 Offset: 0x14) HSMC4 Interrupt Mask Register -------- 00226 // -------- HSMC4_ADDR : (HSMC4 Offset: 0x18) Address Cycle Zero Register -------- 00227 #define AT91C_HSMC4_ADDRCYCLE0 (0xFF << 0) // (HSMC4) Nand Flash Array Address cycle 0 00228 // -------- HSMC4_BANK : (HSMC4 Offset: 0x1c) Bank Register -------- 00229 #define AT91C_BANK (0x7 << 0) // (HSMC4) Bank identifier 00230 #define AT91C_BANK_0 (0x0) // (HSMC4) BANK0 00231 #define AT91C_BANK_1 (0x1) // (HSMC4) BANK1 00232 #define AT91C_BANK_2 (0x2) // (HSMC4) BANK2 00233 #define AT91C_BANK_3 (0x3) // (HSMC4) BANK3 00234 #define AT91C_BANK_4 (0x4) // (HSMC4) BANK4 00235 #define AT91C_BANK_5 (0x5) // (HSMC4) BANK5 00236 #define AT91C_BANK_6 (0x6) // (HSMC4) BANK6 00237 #define AT91C_BANK_7 (0x7) // (HSMC4) BANK7 00238 // -------- HSMC4_ECCCR : (HSMC4 Offset: 0x20) ECC Control Register -------- 00239 #define AT91C_HSMC4_ECCRESET (0x1 << 0) // (HSMC4) Reset ECC 00240 // -------- HSMC4_ECCCMD : (HSMC4 Offset: 0x24) ECC mode register -------- 00241 #define AT91C_ECC_PAGE_SIZE (0x3 << 0) // (HSMC4) Nand Flash page size 00242 #define AT91C_ECC_TYPCORRECT (0x3 << 4) // (HSMC4) Nand Flash page size 00243 #define AT91C_ECC_TYPCORRECT_ONE_PER_PAGE (0x0 << 4) // (HSMC4) 00244 #define AT91C_ECC_TYPCORRECT_ONE_EVERY_256_BYTES (0x1 << 4) // (HSMC4) 00245 #define AT91C_ECC_TYPCORRECT_ONE_EVERY_512_BYTES (0x2 << 4) // (HSMC4) 00246 // -------- HSMC4_ECCSR1 : (HSMC4 Offset: 0x28) ECC Status Register 1 -------- 00247 #define AT91C_HSMC4_ECC_RECERR0 (0x1 << 0) // (HSMC4) Recoverable Error 00248 #define AT91C_HSMC4_ECC_ECCERR0 (0x1 << 1) // (HSMC4) ECC Error 00249 #define AT91C_HSMC4_ECC_MULERR0 (0x1 << 2) // (HSMC4) Multiple Error 00250 #define AT91C_HSMC4_ECC_RECERR1 (0x1 << 4) // (HSMC4) Recoverable Error 00251 #define AT91C_HSMC4_ECC_ECCERR1 (0x1 << 5) // (HSMC4) ECC Error 00252 #define AT91C_HSMC4_ECC_MULERR1 (0x1 << 6) // (HSMC4) Multiple Error 00253 #define AT91C_HSMC4_ECC_RECERR2 (0x1 << 8) // (HSMC4) Recoverable Error 00254 #define AT91C_HSMC4_ECC_ECCERR2 (0x1 << 9) // (HSMC4) ECC Error 00255 #define AT91C_HSMC4_ECC_MULERR2 (0x1 << 10) // (HSMC4) Multiple Error 00256 #define AT91C_HSMC4_ECC_RECERR3 (0x1 << 12) // (HSMC4) Recoverable Error 00257 #define AT91C_HSMC4_ECC_ECCERR3 (0x1 << 13) // (HSMC4) ECC Error 00258 #define AT91C_HSMC4_ECC_MULERR3 (0x1 << 14) // (HSMC4) Multiple Error 00259 #define AT91C_HSMC4_ECC_RECERR4 (0x1 << 16) // (HSMC4) Recoverable Error 00260 #define AT91C_HSMC4_ECC_ECCERR4 (0x1 << 17) // (HSMC4) ECC Error 00261 #define AT91C_HSMC4_ECC_MULERR4 (0x1 << 18) // (HSMC4) Multiple Error 00262 #define AT91C_HSMC4_ECC_RECERR5 (0x1 << 20) // (HSMC4) Recoverable Error 00263 #define AT91C_HSMC4_ECC_ECCERR5 (0x1 << 21) // (HSMC4) ECC Error 00264 #define AT91C_HSMC4_ECC_MULERR5 (0x1 << 22) // (HSMC4) Multiple Error 00265 #define AT91C_HSMC4_ECC_RECERR6 (0x1 << 24) // (HSMC4) Recoverable Error 00266 #define AT91C_HSMC4_ECC_ECCERR6 (0x1 << 25) // (HSMC4) ECC Error 00267 #define AT91C_HSMC4_ECC_MULERR6 (0x1 << 26) // (HSMC4) Multiple Error 00268 #define AT91C_HSMC4_ECC_RECERR7 (0x1 << 28) // (HSMC4) Recoverable Error 00269 #define AT91C_HSMC4_ECC_ECCERR7 (0x1 << 29) // (HSMC4) ECC Error 00270 #define AT91C_HSMC4_ECC_MULERR7 (0x1 << 30) // (HSMC4) Multiple Error 00271 // -------- HSMC4_ECCPR0 : (HSMC4 Offset: 0x2c) HSMC4 ECC parity Register 0 -------- 00272 #define AT91C_HSMC4_ECC_BITADDR (0x7 << 0) // (HSMC4) Corrupted Bit Address in the page 00273 #define AT91C_HSMC4_ECC_WORDADDR (0xFF << 3) // (HSMC4) Corrupted Word Address in the page 00274 #define AT91C_HSMC4_ECC_NPARITY (0x7FF << 12) // (HSMC4) Parity N 00275 // -------- HSMC4_ECCPR1 : (HSMC4 Offset: 0x30) HSMC4 ECC parity Register 1 -------- 00276 // -------- HSMC4_ECCSR2 : (HSMC4 Offset: 0x34) ECC Status Register 2 -------- 00277 #define AT91C_HSMC4_ECC_RECERR8 (0x1 << 0) // (HSMC4) Recoverable Error 00278 #define AT91C_HSMC4_ECC_ECCERR8 (0x1 << 1) // (HSMC4) ECC Error 00279 #define AT91C_HSMC4_ECC_MULERR8 (0x1 << 2) // (HSMC4) Multiple Error 00280 #define AT91C_HSMC4_ECC_RECERR9 (0x1 << 4) // (HSMC4) Recoverable Error 00281 #define AT91C_HSMC4_ECC_ECCERR9 (0x1 << 5) // (HSMC4) ECC Error 00282 #define AT91C_HSMC4_ECC_MULERR9 (0x1 << 6) // (HSMC4) Multiple Error 00283 #define AT91C_HSMC4_ECC_RECERR10 (0x1 << 8) // (HSMC4) Recoverable Error 00284 #define AT91C_HSMC4_ECC_ECCERR10 (0x1 << 9) // (HSMC4) ECC Error 00285 #define AT91C_HSMC4_ECC_MULERR10 (0x1 << 10) // (HSMC4) Multiple Error 00286 #define AT91C_HSMC4_ECC_RECERR11 (0x1 << 12) // (HSMC4) Recoverable Error 00287 #define AT91C_HSMC4_ECC_ECCERR11 (0x1 << 13) // (HSMC4) ECC Error 00288 #define AT91C_HSMC4_ECC_MULERR11 (0x1 << 14) // (HSMC4) Multiple Error 00289 #define AT91C_HSMC4_ECC_RECERR12 (0x1 << 16) // (HSMC4) Recoverable Error 00290 #define AT91C_HSMC4_ECC_ECCERR12 (0x1 << 17) // (HSMC4) ECC Error 00291 #define AT91C_HSMC4_ECC_MULERR12 (0x1 << 18) // (HSMC4) Multiple Error 00292 #define AT91C_HSMC4_ECC_RECERR13 (0x1 << 20) // (HSMC4) Recoverable Error 00293 #define AT91C_HSMC4_ECC_ECCERR13 (0x1 << 21) // (HSMC4) ECC Error 00294 #define AT91C_HSMC4_ECC_MULERR13 (0x1 << 22) // (HSMC4) Multiple Error 00295 #define AT91C_HSMC4_ECC_RECERR14 (0x1 << 24) // (HSMC4) Recoverable Error 00296 #define AT91C_HSMC4_ECC_ECCERR14 (0x1 << 25) // (HSMC4) ECC Error 00297 #define AT91C_HSMC4_ECC_MULERR14 (0x1 << 26) // (HSMC4) Multiple Error 00298 #define AT91C_HSMC4_ECC_RECERR15 (0x1 << 28) // (HSMC4) Recoverable Error 00299 #define AT91C_HSMC4_ECC_ECCERR15 (0x1 << 29) // (HSMC4) ECC Error 00300 #define AT91C_HSMC4_ECC_MULERR15 (0x1 << 30) // (HSMC4) Multiple Error 00301 // -------- HSMC4_ECCPR2 : (HSMC4 Offset: 0x38) HSMC4 ECC parity Register 2 -------- 00302 // -------- HSMC4_ECCPR3 : (HSMC4 Offset: 0x3c) HSMC4 ECC parity Register 3 -------- 00303 // -------- HSMC4_ECCPR4 : (HSMC4 Offset: 0x40) HSMC4 ECC parity Register 4 -------- 00304 // -------- HSMC4_ECCPR5 : (HSMC4 Offset: 0x44) HSMC4 ECC parity Register 5 -------- 00305 // -------- HSMC4_ECCPR6 : (HSMC4 Offset: 0x48) HSMC4 ECC parity Register 6 -------- 00306 // -------- HSMC4_ECCPR7 : (HSMC4 Offset: 0x4c) HSMC4 ECC parity Register 7 -------- 00307 // -------- HSMC4_ECCPR8 : (HSMC4 Offset: 0x50) HSMC4 ECC parity Register 8 -------- 00308 // -------- HSMC4_ECCPR9 : (HSMC4 Offset: 0x54) HSMC4 ECC parity Register 9 -------- 00309 // -------- HSMC4_ECCPR10 : (HSMC4 Offset: 0x58) HSMC4 ECC parity Register 10 -------- 00310 // -------- HSMC4_ECCPR11 : (HSMC4 Offset: 0x5c) HSMC4 ECC parity Register 11 -------- 00311 // -------- HSMC4_ECCPR12 : (HSMC4 Offset: 0x60) HSMC4 ECC parity Register 12 -------- 00312 // -------- HSMC4_ECCPR13 : (HSMC4 Offset: 0x64) HSMC4 ECC parity Register 13 -------- 00313 // -------- HSMC4_ECCPR14 : (HSMC4 Offset: 0x68) HSMC4 ECC parity Register 14 -------- 00314 // -------- HSMC4_ECCPR15 : (HSMC4 Offset: 0x6c) HSMC4 ECC parity Register 15 -------- 00315 // -------- HSMC4_OCMS : (HSMC4 Offset: 0x110) HSMC4 OCMS Register -------- 00316 #define AT91C_HSMC4_OCMS_SRSE (0x1 << 0) // (HSMC4) Static Memory Controller Scrambling Enable 00317 #define AT91C_HSMC4_OCMS_SMSE (0x1 << 1) // (HSMC4) SRAM Scramling Enable 00318 // -------- HSMC4_KEY1 : (HSMC4 Offset: 0x114) HSMC4 OCMS KEY1 Register -------- 00319 #define AT91C_HSMC4_OCMS_KEY1 (0x0 << 0) // (HSMC4) OCMS Key 2 00320 // -------- HSMC4_OCMS_KEY2 : (HSMC4 Offset: 0x118) HSMC4 OCMS KEY2 Register -------- 00321 #define AT91C_HSMC4_OCMS_KEY2 (0x0 << 0) // (HSMC4) OCMS Key 2 00322 // -------- HSMC4_WPCR : (HSMC4 Offset: 0x1e4) HSMC4 Witre Protection Control Register -------- 00323 #define AT91C_HSMC4_WP_EN (0x1 << 0) // (HSMC4) Write Protection Enable 00324 #define AT91C_HSMC4_WP_KEY (0xFFFFFF << 8) // (HSMC4) Protection Password 00325 // -------- HSMC4_WPSR : (HSMC4 Offset: 0x1e8) HSMC4 WPSR Register -------- 00326 #define AT91C_HSMC4_WP_VS (0xF << 0) // (HSMC4) Write Protection Violation Status 00327 #define AT91C_HSMC4_WP_VS_WP_VS0 (0x0) // (HSMC4) No write protection violation since the last read of this register 00328 #define AT91C_HSMC4_WP_VS_WP_VS1 (0x1) // (HSMC4) write protection detected unauthorized attempt to write a control register had occured (since the last read) 00329 #define AT91C_HSMC4_WP_VS_WP_VS2 (0x2) // (HSMC4) Software reset had been performed while write protection was enabled (since the last read) 00330 #define AT91C_HSMC4_WP_VS_WP_VS3 (0x3) // (HSMC4) Both write protection violation and software reset with write protection enabled had occured since the last read 00331 #define AT91C_ (0x0 << 8) // (HSMC4) 00332 // -------- HSMC4_VER : (HSMC4 Offset: 0x1fc) HSMC4 VERSION Register -------- 00333 // -------- HSMC4_DUMMY : (HSMC4 Offset: 0x200) HSMC4 DUMMY REGISTER -------- 00334 #define AT91C_HSMC4_CMD1 (0xFF << 2) // (HSMC4) Command Register Value for Cycle 1 00335 #define AT91C_HSMC4_CMD2 (0xFF << 10) // (HSMC4) Command Register Value for Cycle 2 00336 #define AT91C_HSMC4_VCMD2 (0x1 << 18) // (HSMC4) Valid Cycle 2 Command 00337 #define AT91C_HSMC4_ACYCLE (0x7 << 19) // (HSMC4) Number of Address required for the current command 00338 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_NONE (0x0 << 19) // (HSMC4) No address cycle 00339 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_ONE (0x1 << 19) // (HSMC4) One address cycle 00340 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_TWO (0x2 << 19) // (HSMC4) Two address cycles 00341 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_THREE (0x3 << 19) // (HSMC4) Three address cycles 00342 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FOUR (0x4 << 19) // (HSMC4) Four address cycles 00343 #define AT91C_HSMC4_ACYCLE_HSMC4_ACYCLE_FIVE (0x5 << 19) // (HSMC4) Five address cycles 00344 #define AT91C_HSMC4_CSID (0x7 << 22) // (HSMC4) Chip Select Identifier 00345 #define AT91C_HSMC4_CSID_0 (0x0 << 22) // (HSMC4) CS0 00346 #define AT91C_HSMC4_CSID_1 (0x1 << 22) // (HSMC4) CS1 00347 #define AT91C_HSMC4_CSID_2 (0x2 << 22) // (HSMC4) CS2 00348 #define AT91C_HSMC4_CSID_3 (0x3 << 22) // (HSMC4) CS3 00349 #define AT91C_HSMC4_CSID_4 (0x4 << 22) // (HSMC4) CS4 00350 #define AT91C_HSMC4_CSID_5 (0x5 << 22) // (HSMC4) CS5 00351 #define AT91C_HSMC4_CSID_6 (0x6 << 22) // (HSMC4) CS6 00352 #define AT91C_HSMC4_CSID_7 (0x7 << 22) // (HSMC4) CS7 00353 #define AT91C_HSMC4_HOST_EN (0x1 << 25) // (HSMC4) Host Main Controller Enable 00354 #define AT91C_HSMC4_HOST_WR (0x1 << 26) // (HSMC4) HOSTWR : Host Main Controller Write Enable 00355 #define AT91C_HSMC4_HOSTCMD (0x1 << 27) // (HSMC4) Host Command Enable 00356 00357 // ***************************************************************************** 00358 // SOFTWARE API DEFINITION FOR AHB Matrix2 Interface 00359 // ***************************************************************************** 00360 #ifndef __ASSEMBLY__ 00361 #else 00362 #define MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG0) Master Configuration Register 0 : ARM I and D 00363 #define MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_MCFG1) Master Configuration Register 1 : ARM S 00364 #define MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_MCFG2) Master Configuration Register 2 00365 #define MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_MCFG3) Master Configuration Register 3 00366 #define MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_MCFG4) Master Configuration Register 4 00367 #define MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_MCFG5) Master Configuration Register 5 00368 #define MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x00000018) // (MATRIX_MCFG6) Master Configuration Register 6 00369 #define MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x0000001C) // (MATRIX_MCFG7) Master Configuration Register 7 00370 #define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG0) Slave Configuration Register 0 00371 #define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_SCFG1) Slave Configuration Register 1 00372 #define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x00000048) // (MATRIX_SCFG2) Slave Configuration Register 2 00373 #define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x0000004C) // (MATRIX_SCFG3) Slave Configuration Register 3 00374 #define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000050) // (MATRIX_SCFG4) Slave Configuration Register 4 00375 #define MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x00000054) // (MATRIX_SCFG5) Slave Configuration Register 5 00376 #define MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x00000058) // (MATRIX_SCFG6) Slave Configuration Register 6 00377 #define MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x0000005C) // (MATRIX_SCFG7) Slave Configuration Register 5 00378 #define MATRIX_SCFG8 (AT91_CAST(AT91_REG *) 0x00000060) // (MATRIX_SCFG8) Slave Configuration Register 8 00379 #define MATRIX_SCFG9 (AT91_CAST(AT91_REG *) 0x00000064) // (MATRIX_SCFG9) Slave Configuration Register 9 00380 #define MATRIX_SFR0 (AT91_CAST(AT91_REG *) 0x00000110) // (MATRIX_SFR0 ) Special Function Register 0 00381 #define MATRIX_SFR1 (AT91_CAST(AT91_REG *) 0x00000114) // (MATRIX_SFR1 ) Special Function Register 1 00382 #define MATRIX_SFR2 (AT91_CAST(AT91_REG *) 0x00000118) // (MATRIX_SFR2 ) Special Function Register 2 00383 #define MATRIX_SFR3 (AT91_CAST(AT91_REG *) 0x0000011C) // (MATRIX_SFR3 ) Special Function Register 3 00384 #define MATRIX_SFR4 (AT91_CAST(AT91_REG *) 0x00000120) // (MATRIX_SFR4 ) Special Function Register 4 00385 #define MATRIX_SFR5 (AT91_CAST(AT91_REG *) 0x00000124) // (MATRIX_SFR5 ) Special Function Register 5 00386 #define MATRIX_SFR6 (AT91_CAST(AT91_REG *) 0x00000128) // (MATRIX_SFR6 ) Special Function Register 6 00387 #define MATRIX_SFR7 (AT91_CAST(AT91_REG *) 0x0000012C) // (MATRIX_SFR7 ) Special Function Register 7 00388 #define MATRIX_SFR8 (AT91_CAST(AT91_REG *) 0x00000130) // (MATRIX_SFR8 ) Special Function Register 8 00389 #define MATRIX_SFR9 (AT91_CAST(AT91_REG *) 0x00000134) // (MATRIX_SFR9 ) Special Function Register 9 00390 #define MATRIX_SFR10 (AT91_CAST(AT91_REG *) 0x00000138) // (MATRIX_SFR10) Special Function Register 10 00391 #define MATRIX_SFR11 (AT91_CAST(AT91_REG *) 0x0000013C) // (MATRIX_SFR11) Special Function Register 11 00392 #define MATRIX_SFR12 (AT91_CAST(AT91_REG *) 0x00000140) // (MATRIX_SFR12) Special Function Register 12 00393 #define MATRIX_SFR13 (AT91_CAST(AT91_REG *) 0x00000144) // (MATRIX_SFR13) Special Function Register 13 00394 #define MATRIX_SFR14 (AT91_CAST(AT91_REG *) 0x00000148) // (MATRIX_SFR14) Special Function Register 14 00395 #define MATRIX_SFR15 (AT91_CAST(AT91_REG *) 0x0000014C) // (MATRIX_SFR15) Special Function Register 15 00396 #define HMATRIX2_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000001EC) // (HMATRIX2_ADDRSIZE) HMATRIX2 ADDRSIZE REGISTER 00397 #define HMATRIX2_IPNAME1 (AT91_CAST(AT91_REG *) 0x000001F0) // (HMATRIX2_IPNAME1) HMATRIX2 IPNAME1 REGISTER 00398 #define HMATRIX2_IPNAME2 (AT91_CAST(AT91_REG *) 0x000001F4) // (HMATRIX2_IPNAME2) HMATRIX2 IPNAME2 REGISTER 00399 #define HMATRIX2_FEATURES (AT91_CAST(AT91_REG *) 0x000001F8) // (HMATRIX2_FEATURES) HMATRIX2 FEATURES REGISTER 00400 #define HMATRIX2_VER (AT91_CAST(AT91_REG *) 0x000001FC) // (HMATRIX2_VER) HMATRIX2 VERSION REGISTER 00401 00402 #endif 00403 // -------- MATRIX_MCFG0 : (HMATRIX2 Offset: 0x0) Master Configuration Register ARM bus I and D -------- 00404 #define AT91C_MATRIX_ULBT (0x7 << 0) // (HMATRIX2) Undefined Length Burst Type 00405 #define AT91C_MATRIX_ULBT_INFINIT_LENGTH (0x0) // (HMATRIX2) infinite length burst 00406 #define AT91C_MATRIX_ULBT_SINGLE_ACCESS (0x1) // (HMATRIX2) Single Access 00407 #define AT91C_MATRIX_ULBT_4_BEAT (0x2) // (HMATRIX2) 4 Beat Burst 00408 #define AT91C_MATRIX_ULBT_8_BEAT (0x3) // (HMATRIX2) 8 Beat Burst 00409 #define AT91C_MATRIX_ULBT_16_BEAT (0x4) // (HMATRIX2) 16 Beat Burst 00410 #define AT91C_MATRIX_ULBT_32_BEAT (0x5) // (HMATRIX2) 32 Beat Burst 00411 #define AT91C_MATRIX_ULBT_64_BEAT (0x6) // (HMATRIX2) 64 Beat Burst 00412 #define AT91C_MATRIX_ULBT_128_BEAT (0x7) // (HMATRIX2) 128 Beat Burst 00413 // -------- MATRIX_MCFG1 : (HMATRIX2 Offset: 0x4) Master Configuration Register ARM bus S -------- 00414 // -------- MATRIX_MCFG2 : (HMATRIX2 Offset: 0x8) Master Configuration Register -------- 00415 // -------- MATRIX_MCFG3 : (HMATRIX2 Offset: 0xc) Master Configuration Register -------- 00416 // -------- MATRIX_MCFG4 : (HMATRIX2 Offset: 0x10) Master Configuration Register -------- 00417 // -------- MATRIX_MCFG5 : (HMATRIX2 Offset: 0x14) Master Configuration Register -------- 00418 // -------- MATRIX_MCFG6 : (HMATRIX2 Offset: 0x18) Master Configuration Register -------- 00419 // -------- MATRIX_MCFG7 : (HMATRIX2 Offset: 0x1c) Master Configuration Register -------- 00420 // -------- MATRIX_SCFG0 : (HMATRIX2 Offset: 0x40) Slave Configuration Register 0 -------- 00421 #define AT91C_MATRIX_SLOT_CYCLE (0x1FF << 0) // (HMATRIX2) Maximum Number of Allowed Cycles for a Burst 00422 #define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (HMATRIX2) Default Master Type 00423 #define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (HMATRIX2) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst. 00424 #define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (HMATRIX2) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave. 00425 #define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (HMATRIX2) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave. 00426 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00427 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG0_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00428 // -------- MATRIX_SCFG1 : (HMATRIX2 Offset: 0x44) Slave Configuration Register 1 -------- 00429 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00430 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG1_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00431 // -------- MATRIX_SCFG2 : (HMATRIX2 Offset: 0x48) Slave Configuration Register 2 -------- 00432 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00433 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG2_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00434 // -------- MATRIX_SCFG3 : (HMATRIX2 Offset: 0x4c) Slave Configuration Register 3 -------- 00435 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00436 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG3_ARMC (0x0 << 18) // (HMATRIX2) ARMC is Default Master 00437 // -------- MATRIX_SCFG4 : (HMATRIX2 Offset: 0x50) Slave Configuration Register 4 -------- 00438 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00439 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG4_ARMC (0x0 << 18) // (HMATRIX2) ARMC is Default Master 00440 // -------- MATRIX_SCFG5 : (HMATRIX2 Offset: 0x54) Slave Configuration Register 5 -------- 00441 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00442 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG5_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00443 // -------- MATRIX_SCFG6 : (HMATRIX2 Offset: 0x58) Slave Configuration Register 6 -------- 00444 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00445 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG6_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00446 // -------- MATRIX_SCFG7 : (HMATRIX2 Offset: 0x5c) Slave Configuration Register 7 -------- 00447 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00448 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG7_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00449 // -------- MATRIX_SCFG8 : (HMATRIX2 Offset: 0x60) Slave Configuration Register 8 -------- 00450 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00451 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00452 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG8_HDMA (0x4 << 18) // (HMATRIX2) HDMA is Default Master 00453 // -------- MATRIX_SCFG9 : (HMATRIX2 Offset: 0x64) Slave Configuration Register 9 -------- 00454 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9 (0x7 << 18) // (HMATRIX2) Fixed Index of Default Master 00455 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_ARMS (0x1 << 18) // (HMATRIX2) ARMS is Default Master 00456 #define AT91C_MATRIX_FIXED_DEFMSTR_SCFG9_HDMA (0x4 << 18) // (HMATRIX2) HDMA is Default Master 00457 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x110) Special Function Register 0 -------- 00458 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x114) Special Function Register 0 -------- 00459 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x118) Special Function Register 0 -------- 00460 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x11c) Special Function Register 0 -------- 00461 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x120) Special Function Register 0 -------- 00462 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x124) Special Function Register 0 -------- 00463 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x128) Special Function Register 0 -------- 00464 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x12c) Special Function Register 0 -------- 00465 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x130) Special Function Register 0 -------- 00466 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x134) Special Function Register 0 -------- 00467 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x138) Special Function Register 0 -------- 00468 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x13c) Special Function Register 0 -------- 00469 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x140) Special Function Register 0 -------- 00470 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x144) Special Function Register 0 -------- 00471 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x148) Special Function Register 0 -------- 00472 // -------- MATRIX_SFR0 : (HMATRIX2 Offset: 0x14c) Special Function Register 0 -------- 00473 // -------- HMATRIX2_VER : (HMATRIX2 Offset: 0x1fc) VERSION Register -------- 00474 #define AT91C_HMATRIX2_VER (0xF << 0) // (HMATRIX2) VERSION Register 00475 00476 // ***************************************************************************** 00477 // SOFTWARE API DEFINITION FOR NESTED vector Interrupt Controller 00478 // ***************************************************************************** 00479 #ifndef __ASSEMBLY__ 00480 #else 00481 #define NVIC_ICTR (AT91_CAST(AT91_REG *) 0x00000004) // (NVIC_ICTR) Interrupt Control Type Register 00482 #define NVIC_STICKCSR (AT91_CAST(AT91_REG *) 0x00000010) // (NVIC_STICKCSR) SysTick Control and Status Register 00483 #define NVIC_STICKRVR (AT91_CAST(AT91_REG *) 0x00000014) // (NVIC_STICKRVR) SysTick Reload Value Register 00484 #define NVIC_STICKCVR (AT91_CAST(AT91_REG *) 0x00000018) // (NVIC_STICKCVR) SysTick Current Value Register 00485 #define NVIC_STICKCALVR (AT91_CAST(AT91_REG *) 0x0000001C) // (NVIC_STICKCALVR) SysTick Calibration Value Register 00486 #define NVIC_ISER (AT91_CAST(AT91_REG *) 0x00000100) // (NVIC_ISER) Set Enable Register 00487 #define NVIC_ICER (AT91_CAST(AT91_REG *) 0x00000180) // (NVIC_ICER) Clear enable Register 00488 #define NVIC_ISPR (AT91_CAST(AT91_REG *) 0x00000200) // (NVIC_ISPR) Set Pending Register 00489 #define NVIC_ICPR (AT91_CAST(AT91_REG *) 0x00000280) // (NVIC_ICPR) Clear Pending Register 00490 #define NVIC_IABR (AT91_CAST(AT91_REG *) 0x00000300) // (NVIC_IABR) Active Bit Register 00491 #define NVIC_IPR (AT91_CAST(AT91_REG *) 0x00000400) // (NVIC_IPR) Interrupt Mask Register 00492 #define NVIC_CPUID (AT91_CAST(AT91_REG *) 0x00000D00) // (NVIC_CPUID) CPUID Base Register 00493 #define NVIC_ICSR (AT91_CAST(AT91_REG *) 0x00000D04) // (NVIC_ICSR) Interrupt Control State Register 00494 #define NVIC_VTOFFR (AT91_CAST(AT91_REG *) 0x00000D08) // (NVIC_VTOFFR) Vector Table Offset Register 00495 #define NVIC_AIRCR (AT91_CAST(AT91_REG *) 0x00000D0C) // (NVIC_AIRCR) Application Interrupt/Reset Control Reg 00496 #define NVIC_SCR (AT91_CAST(AT91_REG *) 0x00000D10) // (NVIC_SCR) System Control Register 00497 #define NVIC_CCR (AT91_CAST(AT91_REG *) 0x00000D14) // (NVIC_CCR) Configuration Control Register 00498 #define NVIC_HAND4PR (AT91_CAST(AT91_REG *) 0x00000D18) // (NVIC_HAND4PR) System Handlers 4-7 Priority Register 00499 #define NVIC_HAND8PR (AT91_CAST(AT91_REG *) 0x00000D1C) // (NVIC_HAND8PR) System Handlers 8-11 Priority Register 00500 #define NVIC_HAND12PR (AT91_CAST(AT91_REG *) 0x00000D20) // (NVIC_HAND12PR) System Handlers 12-15 Priority Register 00501 #define NVIC_HANDCSR (AT91_CAST(AT91_REG *) 0x00000D24) // (NVIC_HANDCSR) System Handler Control and State Register 00502 #define NVIC_CFSR (AT91_CAST(AT91_REG *) 0x00000D28) // (NVIC_CFSR) Configurable Fault Status Register 00503 #define NVIC_HFSR (AT91_CAST(AT91_REG *) 0x00000D2C) // (NVIC_HFSR) Hard Fault Status Register 00504 #define NVIC_DFSR (AT91_CAST(AT91_REG *) 0x00000D30) // (NVIC_DFSR) Debug Fault Status Register 00505 #define NVIC_MMAR (AT91_CAST(AT91_REG *) 0x00000D34) // (NVIC_MMAR) Mem Manage Address Register 00506 #define NVIC_BFAR (AT91_CAST(AT91_REG *) 0x00000D38) // (NVIC_BFAR) Bus Fault Address Register 00507 #define NVIC_AFSR (AT91_CAST(AT91_REG *) 0x00000D3C) // (NVIC_AFSR) Auxiliary Fault Status Register 00508 #define NVIC_PFR0 (AT91_CAST(AT91_REG *) 0x00000D40) // (NVIC_PFR0) Processor Feature register0 00509 #define NVIC_PFR1 (AT91_CAST(AT91_REG *) 0x00000D44) // (NVIC_PFR1) Processor Feature register1 00510 #define NVIC_DFR0 (AT91_CAST(AT91_REG *) 0x00000D48) // (NVIC_DFR0) Debug Feature register0 00511 #define NVIC_AFR0 (AT91_CAST(AT91_REG *) 0x00000D4C) // (NVIC_AFR0) Auxiliary Feature register0 00512 #define NVIC_MMFR0 (AT91_CAST(AT91_REG *) 0x00000D50) // (NVIC_MMFR0) Memory Model Feature register0 00513 #define NVIC_MMFR1 (AT91_CAST(AT91_REG *) 0x00000D54) // (NVIC_MMFR1) Memory Model Feature register1 00514 #define NVIC_MMFR2 (AT91_CAST(AT91_REG *) 0x00000D58) // (NVIC_MMFR2) Memory Model Feature register2 00515 #define NVIC_MMFR3 (AT91_CAST(AT91_REG *) 0x00000D5C) // (NVIC_MMFR3) Memory Model Feature register3 00516 #define NVIC_ISAR0 (AT91_CAST(AT91_REG *) 0x00000D60) // (NVIC_ISAR0) ISA Feature register0 00517 #define NVIC_ISAR1 (AT91_CAST(AT91_REG *) 0x00000D64) // (NVIC_ISAR1) ISA Feature register1 00518 #define NVIC_ISAR2 (AT91_CAST(AT91_REG *) 0x00000D68) // (NVIC_ISAR2) ISA Feature register2 00519 #define NVIC_ISAR3 (AT91_CAST(AT91_REG *) 0x00000D6C) // (NVIC_ISAR3) ISA Feature register3 00520 #define NVIC_ISAR4 (AT91_CAST(AT91_REG *) 0x00000D70) // (NVIC_ISAR4) ISA Feature register4 00521 #define NVIC_STIR (AT91_CAST(AT91_REG *) 0x00000F00) // (NVIC_STIR) Software Trigger Interrupt Register 00522 #define NVIC_PID4 (AT91_CAST(AT91_REG *) 0x00000FD0) // (NVIC_PID4) Peripheral identification register 00523 #define NVIC_PID5 (AT91_CAST(AT91_REG *) 0x00000FD4) // (NVIC_PID5) Peripheral identification register 00524 #define NVIC_PID6 (AT91_CAST(AT91_REG *) 0x00000FD8) // (NVIC_PID6) Peripheral identification register 00525 #define NVIC_PID7 (AT91_CAST(AT91_REG *) 0x00000FDC) // (NVIC_PID7) Peripheral identification register 00526 #define NVIC_PID0 (AT91_CAST(AT91_REG *) 0x00000FE0) // (NVIC_PID0) Peripheral identification register b7:0 00527 #define NVIC_PID1 (AT91_CAST(AT91_REG *) 0x00000FE4) // (NVIC_PID1) Peripheral identification register b15:8 00528 #define NVIC_PID2 (AT91_CAST(AT91_REG *) 0x00000FE8) // (NVIC_PID2) Peripheral identification register b23:16 00529 #define NVIC_PID3 (AT91_CAST(AT91_REG *) 0x00000FEC) // (NVIC_PID3) Peripheral identification register b31:24 00530 #define NVIC_CID0 (AT91_CAST(AT91_REG *) 0x00000FF0) // (NVIC_CID0) Component identification register b7:0 00531 #define NVIC_CID1 (AT91_CAST(AT91_REG *) 0x00000FF4) // (NVIC_CID1) Component identification register b15:8 00532 #define NVIC_CID2 (AT91_CAST(AT91_REG *) 0x00000FF8) // (NVIC_CID2) Component identification register b23:16 00533 #define NVIC_CID3 (AT91_CAST(AT91_REG *) 0x00000FFC) // (NVIC_CID3) Component identification register b31:24 00534 00535 #endif 00536 // -------- NVIC_ICTR : (NVIC Offset: 0x4) Interrupt Controller Type Register -------- 00537 #define AT91C_NVIC_INTLINESNUM (0xF << 0) // (NVIC) Total number of interrupt lines 00538 #define AT91C_NVIC_INTLINESNUM_32 (0x0) // (NVIC) up to 32 interrupt lines supported 00539 #define AT91C_NVIC_INTLINESNUM_64 (0x1) // (NVIC) up to 64 interrupt lines supported 00540 #define AT91C_NVIC_INTLINESNUM_96 (0x2) // (NVIC) up to 96 interrupt lines supported 00541 #define AT91C_NVIC_INTLINESNUM_128 (0x3) // (NVIC) up to 128 interrupt lines supported 00542 #define AT91C_NVIC_INTLINESNUM_160 (0x4) // (NVIC) up to 160 interrupt lines supported 00543 #define AT91C_NVIC_INTLINESNUM_192 (0x5) // (NVIC) up to 192 interrupt lines supported 00544 #define AT91C_NVIC_INTLINESNUM_224 (0x6) // (NVIC) up to 224 interrupt lines supported 00545 #define AT91C_NVIC_INTLINESNUM_256 (0x7) // (NVIC) up to 256 interrupt lines supported 00546 #define AT91C_NVIC_INTLINESNUM_288 (0x8) // (NVIC) up to 288 interrupt lines supported 00547 #define AT91C_NVIC_INTLINESNUM_320 (0x9) // (NVIC) up to 320 interrupt lines supported 00548 #define AT91C_NVIC_INTLINESNUM_352 (0xA) // (NVIC) up to 352 interrupt lines supported 00549 #define AT91C_NVIC_INTLINESNUM_384 (0xB) // (NVIC) up to 384 interrupt lines supported 00550 #define AT91C_NVIC_INTLINESNUM_416 (0xC) // (NVIC) up to 416 interrupt lines supported 00551 #define AT91C_NVIC_INTLINESNUM_448 (0xD) // (NVIC) up to 448 interrupt lines supported 00552 #define AT91C_NVIC_INTLINESNUM_480 (0xE) // (NVIC) up to 480 interrupt lines supported 00553 #define AT91C_NVIC_INTLINESNUM_496 (0xF) // (NVIC) up to 496 interrupt lines supported) 00554 // -------- NVIC_STICKCSR : (NVIC Offset: 0x10) SysTick Control and Status Register -------- 00555 #define AT91C_NVIC_STICKENABLE (0x1 << 0) // (NVIC) SysTick counter enable. 00556 #define AT91C_NVIC_STICKINT (0x1 << 1) // (NVIC) SysTick interrupt enable. 00557 #define AT91C_NVIC_STICKCLKSOURCE (0x1 << 2) // (NVIC) Reference clock selection. 00558 #define AT91C_NVIC_STICKCOUNTFLAG (0x1 << 16) // (NVIC) Return 1 if timer counted to 0 since last read. 00559 // -------- NVIC_STICKRVR : (NVIC Offset: 0x14) SysTick Reload Value Register -------- 00560 #define AT91C_NVIC_STICKRELOAD (0xFFFFFF << 0) // (NVIC) SysTick reload value. 00561 // -------- NVIC_STICKCVR : (NVIC Offset: 0x18) SysTick Current Value Register -------- 00562 #define AT91C_NVIC_STICKCURRENT (0x7FFFFFFF << 0) // (NVIC) SysTick current value. 00563 // -------- NVIC_STICKCALVR : (NVIC Offset: 0x1c) SysTick Calibration Value Register -------- 00564 #define AT91C_NVIC_STICKTENMS (0xFFFFFF << 0) // (NVIC) Reload value to use for 10ms timing. 00565 #define AT91C_NVIC_STICKSKEW (0x1 << 30) // (NVIC) Read as 1 if the calibration value is not exactly 10ms because of clock frequency. 00566 #define AT91C_NVIC_STICKNOREF (0x1 << 31) // (NVIC) Read as 1 if the reference clock is not provided. 00567 // -------- NVIC_IPR : (NVIC Offset: 0x400) Interrupt Priority Registers -------- 00568 #define AT91C_NVIC_PRI_N (0xFF << 0) // (NVIC) Priority of interrupt N (0, 4, 8, etc) 00569 #define AT91C_NVIC_PRI_N1 (0xFF << 8) // (NVIC) Priority of interrupt N+1 (1, 5, 9, etc) 00570 #define AT91C_NVIC_PRI_N2 (0xFF << 16) // (NVIC) Priority of interrupt N+2 (2, 6, 10, etc) 00571 #define AT91C_NVIC_PRI_N3 (0xFF << 24) // (NVIC) Priority of interrupt N+3 (3, 7, 11, etc) 00572 // -------- NVIC_CPUID : (NVIC Offset: 0xd00) CPU ID Base Register -------- 00573 #define AT91C_NVIC_REVISION (0xF << 0) // (NVIC) Implementation defined revision number. 00574 #define AT91C_NVIC_PARTNO (0xFFF << 4) // (NVIC) Number of processor within family 00575 #define AT91C_NVIC_CONSTANT (0xF << 16) // (NVIC) Reads as 0xF 00576 #define AT91C_NVIC_VARIANT (0xF << 20) // (NVIC) Implementation defined variant number. 00577 #define AT91C_NVIC_IMPLEMENTER (0xFF << 24) // (NVIC) Implementer code. ARM is 0x41 00578 // -------- NVIC_ICSR : (NVIC Offset: 0xd04) Interrupt Control State Register -------- 00579 #define AT91C_NVIC_VECTACTIVE (0x1FF << 0) // (NVIC) Read-only Active ISR number field 00580 #define AT91C_NVIC_RETTOBASE (0x1 << 11) // (NVIC) Read-only 00581 #define AT91C_NVIC_VECTPENDING (0x1FF << 12) // (NVIC) Read-only Pending ISR number field 00582 #define AT91C_NVIC_ISRPENDING (0x1 << 22) // (NVIC) Read-only Interrupt pending flag. 00583 #define AT91C_NVIC_ISRPREEMPT (0x1 << 23) // (NVIC) Read-only You must only use this at debug time 00584 #define AT91C_NVIC_PENDSTCLR (0x1 << 25) // (NVIC) Write-only Clear pending SysTick bit 00585 #define AT91C_NVIC_PENDSTSET (0x1 << 26) // (NVIC) Read/write Set a pending SysTick bit 00586 #define AT91C_NVIC_PENDSVCLR (0x1 << 27) // (NVIC) Write-only Clear pending pendSV bit 00587 #define AT91C_NVIC_PENDSVSET (0x1 << 28) // (NVIC) Read/write Set pending pendSV bit 00588 #define AT91C_NVIC_NMIPENDSET (0x1 << 31) // (NVIC) Read/write Set pending NMI 00589 // -------- NVIC_VTOFFR : (NVIC Offset: 0xd08) Vector Table Offset Register -------- 00590 #define AT91C_NVIC_TBLOFF (0x3FFFFF << 7) // (NVIC) Vector table base offset field 00591 #define AT91C_NVIC_TBLBASE (0x1 << 29) // (NVIC) Table base is in Code (0) or RAM (1) 00592 #define AT91C_NVIC_TBLBASE_CODE (0x0 << 29) // (NVIC) Table base is in CODE 00593 #define AT91C_NVIC_TBLBASE_RAM (0x1 << 29) // (NVIC) Table base is in RAM 00594 // -------- NVIC_AIRCR : (NVIC Offset: 0xd0c) Application Interrupt and Reset Control Register -------- 00595 #define AT91C_NVIC_VECTRESET (0x1 << 0) // (NVIC) System Reset bit 00596 #define AT91C_NVIC_VECTCLRACTIVE (0x1 << 1) // (NVIC) Clear active vector bit 00597 #define AT91C_NVIC_SYSRESETREQ (0x1 << 2) // (NVIC) Causes a signal to be asserted to the outer system that indicates a reset is requested 00598 #define AT91C_NVIC_PRIGROUP (0x7 << 8) // (NVIC) Interrupt priority grouping field 00599 #define AT91C_NVIC_PRIGROUP_0 (0x0 << 8) // (NVIC) indicates seven bits of pre-emption priority, one bit of subpriority 00600 #define AT91C_NVIC_PRIGROUP_1 (0x1 << 8) // (NVIC) indicates six bits of pre-emption priority, two bits of subpriority 00601 #define AT91C_NVIC_PRIGROUP_2 (0x2 << 8) // (NVIC) indicates five bits of pre-emption priority, three bits of subpriority 00602 #define AT91C_NVIC_PRIGROUP_3 (0x3 << 8) // (NVIC) indicates four bits of pre-emption priority, four bits of subpriority 00603 #define AT91C_NVIC_PRIGROUP_4 (0x4 << 8) // (NVIC) indicates three bits of pre-emption priority, five bits of subpriority 00604 #define AT91C_NVIC_PRIGROUP_5 (0x5 << 8) // (NVIC) indicates two bits of pre-emption priority, six bits of subpriority 00605 #define AT91C_NVIC_PRIGROUP_6 (0x6 << 8) // (NVIC) indicates one bit of pre-emption priority, seven bits of subpriority 00606 #define AT91C_NVIC_PRIGROUP_7 (0x7 << 8) // (NVIC) indicates no pre-emption priority, eight bits of subpriority 00607 #define AT91C_NVIC_ENDIANESS (0x1 << 15) // (NVIC) Data endianness bit 00608 #define AT91C_NVIC_VECTKEY (0xFFFF << 16) // (NVIC) Register key 00609 // -------- NVIC_SCR : (NVIC Offset: 0xd10) System Control Register -------- 00610 #define AT91C_NVIC_SLEEPONEXIT (0x1 << 1) // (NVIC) Sleep on exit when returning from Handler mode to Thread mode 00611 #define AT91C_NVIC_SLEEPDEEP (0x1 << 2) // (NVIC) Sleep deep bit 00612 #define AT91C_NVIC_SEVONPEND (0x1 << 4) // (NVIC) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended 00613 // -------- NVIC_CCR : (NVIC Offset: 0xd14) Configuration Control Register -------- 00614 #define AT91C_NVIC_NONEBASETHRDENA (0x1 << 0) // (NVIC) When 0, default, It is only possible to enter Thread mode when returning from the last exception 00615 #define AT91C_NVIC_USERSETMPEND (0x1 << 1) // (NVIC) 00616 #define AT91C_NVIC_UNALIGN_TRP (0x1 << 3) // (NVIC) Trap for unaligned access 00617 #define AT91C_NVIC_DIV_0_TRP (0x1 << 4) // (NVIC) Trap on Divide by 0 00618 #define AT91C_NVIC_BFHFNMIGN (0x1 << 8) // (NVIC) 00619 #define AT91C_NVIC_STKALIGN (0x1 << 9) // (NVIC) 00620 // -------- NVIC_HAND4PR : (NVIC Offset: 0xd18) System Handlers 4-7 Priority Register -------- 00621 #define AT91C_NVIC_PRI_4 (0xFF << 0) // (NVIC) 00622 #define AT91C_NVIC_PRI_5 (0xFF << 8) // (NVIC) 00623 #define AT91C_NVIC_PRI_6 (0xFF << 16) // (NVIC) 00624 #define AT91C_NVIC_PRI_7 (0xFF << 24) // (NVIC) 00625 // -------- NVIC_HAND8PR : (NVIC Offset: 0xd1c) System Handlers 8-11 Priority Register -------- 00626 #define AT91C_NVIC_PRI_8 (0xFF << 0) // (NVIC) 00627 #define AT91C_NVIC_PRI_9 (0xFF << 8) // (NVIC) 00628 #define AT91C_NVIC_PRI_10 (0xFF << 16) // (NVIC) 00629 #define AT91C_NVIC_PRI_11 (0xFF << 24) // (NVIC) 00630 // -------- NVIC_HAND12PR : (NVIC Offset: 0xd20) System Handlers 12-15 Priority Register -------- 00631 #define AT91C_NVIC_PRI_12 (0xFF << 0) // (NVIC) 00632 #define AT91C_NVIC_PRI_13 (0xFF << 8) // (NVIC) 00633 #define AT91C_NVIC_PRI_14 (0xFF << 16) // (NVIC) 00634 #define AT91C_NVIC_PRI_15 (0xFF << 24) // (NVIC) 00635 // -------- NVIC_HANDCSR : (NVIC Offset: 0xd24) System Handler Control and State Register -------- 00636 #define AT91C_NVIC_MEMFAULTACT (0x1 << 0) // (NVIC) 00637 #define AT91C_NVIC_BUSFAULTACT (0x1 << 1) // (NVIC) 00638 #define AT91C_NVIC_USGFAULTACT (0x1 << 3) // (NVIC) 00639 #define AT91C_NVIC_SVCALLACT (0x1 << 7) // (NVIC) 00640 #define AT91C_NVIC_MONITORACT (0x1 << 8) // (NVIC) 00641 #define AT91C_NVIC_PENDSVACT (0x1 << 10) // (NVIC) 00642 #define AT91C_NVIC_SYSTICKACT (0x1 << 11) // (NVIC) 00643 #define AT91C_NVIC_USGFAULTPENDED (0x1 << 12) // (NVIC) 00644 #define AT91C_NVIC_MEMFAULTPENDED (0x1 << 13) // (NVIC) 00645 #define AT91C_NVIC_BUSFAULTPENDED (0x1 << 14) // (NVIC) 00646 #define AT91C_NVIC_SVCALLPENDED (0x1 << 15) // (NVIC) 00647 #define AT91C_NVIC_MEMFAULTENA (0x1 << 16) // (NVIC) 00648 #define AT91C_NVIC_BUSFAULTENA (0x1 << 17) // (NVIC) 00649 #define AT91C_NVIC_USGFAULTENA (0x1 << 18) // (NVIC) 00650 // -------- NVIC_CFSR : (NVIC Offset: 0xd28) Configurable Fault Status Registers -------- 00651 #define AT91C_NVIC_MEMMANAGE (0xFF << 0) // (NVIC) 00652 #define AT91C_NVIC_BUSFAULT (0xFF << 8) // (NVIC) 00653 #define AT91C_NVIC_USAGEFAULT (0xFF << 16) // (NVIC) 00654 // -------- NVIC_BFAR : (NVIC Offset: 0xd38) Bus Fault Address Register -------- 00655 #define AT91C_NVIC_IBUSERR (0x1 << 0) // (NVIC) This bit indicates a bus fault on an instruction prefetch 00656 #define AT91C_NVIC_PRECISERR (0x1 << 1) // (NVIC) Precise data access error. The BFAR is written with the faulting address 00657 #define AT91C_NVIC_IMPRECISERR (0x1 << 2) // (NVIC) Imprecise data access error 00658 #define AT91C_NVIC_UNSTKERR (0x1 << 3) // (NVIC) This bit indicates a derived bus fault has occurred on exception return 00659 #define AT91C_NVIC_STKERR (0x1 << 4) // (NVIC) This bit indicates a derived bus fault has occurred on exception entry 00660 #define AT91C_NVIC_BFARVALID (0x1 << 7) // (NVIC) This bit is set if the BFAR register has valid contents 00661 // -------- NVIC_PFR0 : (NVIC Offset: 0xd40) Processor Feature register0 (ID_PFR0) -------- 00662 #define AT91C_NVIC_ID_PFR0_0 (0xF << 0) // (NVIC) State0 (T-bit == 0) 00663 #define AT91C_NVIC_ID_PRF0_1 (0xF << 4) // (NVIC) State1 (T-bit == 1) 00664 // -------- NVIC_PFR1 : (NVIC Offset: 0xd44) Processor Feature register1 (ID_PFR1) -------- 00665 #define AT91C_NVIC_ID_PRF1_MODEL (0xF << 8) // (NVIC) Microcontroller programmer’s model 00666 // -------- NVIC_DFR0 : (NVIC Offset: 0xd48) Debug Feature register0 (ID_DFR0) -------- 00667 #define AT91C_NVIC_ID_DFR0_MODEL (0xF << 20) // (NVIC) Microcontroller Debug Model – memory mapped 00668 // -------- NVIC_MMFR0 : (NVIC Offset: 0xd50) Memory Model Feature register0 (ID_MMFR0) -------- 00669 #define AT91C_NVIC_ID_MMFR0_PMSA (0xF << 4) // (NVIC) Microcontroller Debug Model – memory mapped 00670 #define AT91C_NVIC_ID_MMFR0_CACHE (0xF << 8) // (NVIC) Microcontroller Debug Model – memory mapped 00671 00672 // ***************************************************************************** 00673 // SOFTWARE API DEFINITION FOR NESTED vector Interrupt Controller 00674 // ***************************************************************************** 00675 #ifndef __ASSEMBLY__ 00676 #else 00677 #define MPU_TYPE (AT91_CAST(AT91_REG *) 0x00000000) // (MPU_TYPE) MPU Type Register 00678 #define MPU_CTRL (AT91_CAST(AT91_REG *) 0x00000004) // (MPU_CTRL) MPU Control Register 00679 #define MPU_REG_NB (AT91_CAST(AT91_REG *) 0x00000008) // (MPU_REG_NB) MPU Region Number Register 00680 #define MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *) 0x0000000C) // (MPU_REG_BASE_ADDR) MPU Region Base Address Register 00681 #define MPU_ATTR_SIZE (AT91_CAST(AT91_REG *) 0x00000010) // (MPU_ATTR_SIZE) MPU Attribute and Size Register 00682 #define MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *) 0x00000014) // (MPU_REG_BASE_ADDR1) MPU Region Base Address Register alias 1 00683 #define MPU_ATTR_SIZE1 (AT91_CAST(AT91_REG *) 0x00000018) // (MPU_ATTR_SIZE1) MPU Attribute and Size Register alias 1 00684 #define MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *) 0x0000001C) // (MPU_REG_BASE_ADDR2) MPU Region Base Address Register alias 2 00685 #define MPU_ATTR_SIZE2 (AT91_CAST(AT91_REG *) 0x00000020) // (MPU_ATTR_SIZE2) MPU Attribute and Size Register alias 2 00686 #define MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *) 0x00000024) // (MPU_REG_BASE_ADDR3) MPU Region Base Address Register alias 3 00687 #define MPU_ATTR_SIZE3 (AT91_CAST(AT91_REG *) 0x00000028) // (MPU_ATTR_SIZE3) MPU Attribute and Size Register alias 3 00688 00689 #endif 00690 // -------- MPU_TYPE : (MPU Offset: 0x0) -------- 00691 #define AT91C_MPU_SEPARATE (0x1 << 0) // (MPU) 00692 #define AT91C_MPU_DREGION (0xFF << 8) // (MPU) 00693 #define AT91C_MPU_IREGION (0xFF << 16) // (MPU) 00694 // -------- MPU_CTRL : (MPU Offset: 0x4) -------- 00695 #define AT91C_MPU_ENABLE (0x1 << 0) // (MPU) 00696 #define AT91C_MPU_HFNMIENA (0x1 << 1) // (MPU) 00697 #define AT91C_MPU_PRIVDEFENA (0x1 << 2) // (MPU) 00698 // -------- MPU_REG_NB : (MPU Offset: 0x8) -------- 00699 #define AT91C_MPU_REGION (0xFF << 0) // (MPU) 00700 // -------- MPU_REG_BASE_ADDR : (MPU Offset: 0xc) -------- 00701 #define AT91C_MPU_REG (0xF << 0) // (MPU) 00702 #define AT91C_MPU_VALID (0x1 << 4) // (MPU) 00703 #define AT91C_MPU_ADDR (0x3FFFFFF << 5) // (MPU) 00704 // -------- MPU_ATTR_SIZE : (MPU Offset: 0x10) -------- 00705 #define AT91C_MPU_ENA (0x1 << 0) // (MPU) 00706 #define AT91C_MPU_SIZE (0xF << 1) // (MPU) 00707 #define AT91C_MPU_SRD (0xFF << 8) // (MPU) 00708 #define AT91C_MPU_B (0x1 << 16) // (MPU) 00709 #define AT91C_MPU_C (0x1 << 17) // (MPU) 00710 #define AT91C_MPU_S (0x1 << 18) // (MPU) 00711 #define AT91C_MPU_TEX (0x7 << 19) // (MPU) 00712 #define AT91C_MPU_AP (0x7 << 24) // (MPU) 00713 #define AT91C_MPU_XN (0x7 << 28) // (MPU) 00714 00715 // ***************************************************************************** 00716 // SOFTWARE API DEFINITION FOR CORTEX_M3 Registers 00717 // ***************************************************************************** 00718 #ifndef __ASSEMBLY__ 00719 #else 00720 #define CM3_CPUID (AT91_CAST(AT91_REG *) 0x00000000) // (CM3_CPUID) CPU ID Base Register 00721 #define CM3_ICSR (AT91_CAST(AT91_REG *) 0x00000004) // (CM3_ICSR) Interrupt Control State Register 00722 #define CM3_VTOR (AT91_CAST(AT91_REG *) 0x00000008) // (CM3_VTOR) Vector Table Offset Register 00723 #define CM3_AIRCR (AT91_CAST(AT91_REG *) 0x0000000C) // (CM3_AIRCR) Application Interrupt and Reset Control Register 00724 #define CM3_SCR (AT91_CAST(AT91_REG *) 0x00000010) // (CM3_SCR) System Controller Register 00725 #define CM3_CCR (AT91_CAST(AT91_REG *) 0x00000014) // (CM3_CCR) Configuration Control Register 00726 #define CM3_SHPR (AT91_CAST(AT91_REG *) 0x00000018) // (CM3_SHPR) System Handler Priority Register 00727 #define CM3_SHCSR (AT91_CAST(AT91_REG *) 0x00000024) // (CM3_SHCSR) System Handler Control and State Register 00728 00729 #endif 00730 // -------- CM3_CPUID : (CM3 Offset: 0x0) -------- 00731 // -------- CM3_AIRCR : (CM3 Offset: 0xc) -------- 00732 #define AT91C_CM3_SYSRESETREQ (0x1 << 2) // (CM3) A reset is requested by the processor. 00733 // -------- CM3_SCR : (CM3 Offset: 0x10) -------- 00734 #define AT91C_CM3_SLEEPONEXIT (0x1 << 1) // (CM3) Sleep on exit when returning from Handler mode to Thread mode. Enables interrupt driven applications to avoid returning to empty main application. 00735 #define AT91C_CM3_SLEEPDEEP (0x1 << 2) // (CM3) Sleep deep bit. 00736 #define AT91C_CM3_SEVONPEND (0x1 << 4) // (CM3) When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. 00737 // -------- CM3_SHCSR : (CM3 Offset: 0x24) -------- 00738 #define AT91C_CM3_SYSTICKACT (0x1 << 11) // (CM3) Reads as 1 if SysTick is active. 00739 00740 // ***************************************************************************** 00741 // SOFTWARE API DEFINITION FOR Peripheral DMA Controller 00742 // ***************************************************************************** 00743 #ifndef __ASSEMBLY__ 00744 #else 00745 #define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register 00746 #define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register 00747 #define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register 00748 #define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register 00749 #define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register 00750 #define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register 00751 #define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register 00752 #define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register 00753 #define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register 00754 #define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register 00755 00756 #endif 00757 // -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 00758 #define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable 00759 #define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable 00760 #define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable 00761 #define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable 00762 // -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 00763 00764 // ***************************************************************************** 00765 // SOFTWARE API DEFINITION FOR Debug Unit 00766 // ***************************************************************************** 00767 #ifndef __ASSEMBLY__ 00768 #else 00769 #define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register 00770 #define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register 00771 #define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register 00772 #define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register 00773 #define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register 00774 #define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register 00775 #define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register 00776 #define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register 00777 #define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register 00778 #define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register 00779 #define DBGU_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (DBGU_ADDRSIZE) DBGU ADDRSIZE REGISTER 00780 #define DBGU_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (DBGU_IPNAME1) DBGU IPNAME1 REGISTER 00781 #define DBGU_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (DBGU_IPNAME2) DBGU IPNAME2 REGISTER 00782 #define DBGU_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (DBGU_FEATURES) DBGU FEATURES REGISTER 00783 #define DBGU_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (DBGU_VER) DBGU VERSION REGISTER 00784 #define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000140) // (DBGU_CIDR) Chip ID Register 00785 #define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000144) // (DBGU_EXID) Chip ID Extension Register 00786 00787 #endif 00788 // -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 00789 #define AT91C_DBGU_RSTRX (0x1 << 2) // (DBGU) Reset Receiver 00790 #define AT91C_DBGU_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter 00791 #define AT91C_DBGU_RXEN (0x1 << 4) // (DBGU) Receiver Enable 00792 #define AT91C_DBGU_RXDIS (0x1 << 5) // (DBGU) Receiver Disable 00793 #define AT91C_DBGU_TXEN (0x1 << 6) // (DBGU) Transmitter Enable 00794 #define AT91C_DBGU_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable 00795 #define AT91C_DBGU_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits 00796 // -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 00797 #define AT91C_DBGU_PAR (0x7 << 9) // (DBGU) Parity type 00798 #define AT91C_DBGU_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity 00799 #define AT91C_DBGU_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity 00800 #define AT91C_DBGU_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) 00801 #define AT91C_DBGU_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) 00802 #define AT91C_DBGU_PAR_NONE (0x4 << 9) // (DBGU) No Parity 00803 #define AT91C_DBGU_CHMODE (0x3 << 14) // (DBGU) Channel Mode 00804 #define AT91C_DBGU_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The debug unit channel operates as an RX/TX debug unit. 00805 #define AT91C_DBGU_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. 00806 #define AT91C_DBGU_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 00807 #define AT91C_DBGU_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. 00808 // -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 00809 #define AT91C_DBGU_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt 00810 #define AT91C_DBGU_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt 00811 #define AT91C_DBGU_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt 00812 #define AT91C_DBGU_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt 00813 #define AT91C_DBGU_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt 00814 #define AT91C_DBGU_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt 00815 #define AT91C_DBGU_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt 00816 #define AT91C_DBGU_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt 00817 #define AT91C_DBGU_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt 00818 #define AT91C_DBGU_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt 00819 #define AT91C_DBGU_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt 00820 #define AT91C_DBGU_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt 00821 // -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 00822 // -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 00823 // -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 00824 // -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 00825 #define AT91C_DBGU_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG 00826 00827 // ***************************************************************************** 00828 // SOFTWARE API DEFINITION FOR Parallel Input Output Controler 00829 // ***************************************************************************** 00830 #ifndef __ASSEMBLY__ 00831 #else 00832 #define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register 00833 #define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register 00834 #define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register 00835 #define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register 00836 #define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr 00837 #define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register 00838 #define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register 00839 #define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register 00840 #define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register 00841 #define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register 00842 #define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register 00843 #define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register 00844 #define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register 00845 #define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register 00846 #define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register 00847 #define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register 00848 #define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register 00849 #define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register 00850 #define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register 00851 #define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register 00852 #define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register 00853 #define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register 00854 #define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register 00855 #define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ABSR) Peripheral AB Select Register 00856 #define PIO_SCIFSR (AT91_CAST(AT91_REG *) 0x00000080) // (PIO_SCIFSR) System Clock Glitch Input Filter Select Register 00857 #define PIO_DIFSR (AT91_CAST(AT91_REG *) 0x00000084) // (PIO_DIFSR) Debouncing Input Filter Select Register 00858 #define PIO_IFDGSR (AT91_CAST(AT91_REG *) 0x00000088) // (PIO_IFDGSR) Glitch or Debouncing Input Filter Clock Selection Status Register 00859 #define PIO_SCDR (AT91_CAST(AT91_REG *) 0x0000008C) // (PIO_SCDR) Slow Clock Divider Debouncing Register 00860 #define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register 00861 #define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register 00862 #define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register 00863 #define PIO_AIMER (AT91_CAST(AT91_REG *) 0x000000B0) // (PIO_AIMER) Additional Interrupt Modes Enable Register 00864 #define PIO_AIMDR (AT91_CAST(AT91_REG *) 0x000000B4) // (PIO_AIMDR) Additional Interrupt Modes Disables Register 00865 #define PIO_AIMMR (AT91_CAST(AT91_REG *) 0x000000B8) // (PIO_AIMMR) Additional Interrupt Modes Mask Register 00866 #define PIO_ESR (AT91_CAST(AT91_REG *) 0x000000C0) // (PIO_ESR) Edge Select Register 00867 #define PIO_LSR (AT91_CAST(AT91_REG *) 0x000000C4) // (PIO_LSR) Level Select Register 00868 #define PIO_ELSR (AT91_CAST(AT91_REG *) 0x000000C8) // (PIO_ELSR) Edge/Level Status Register 00869 #define PIO_FELLSR (AT91_CAST(AT91_REG *) 0x000000D0) // (PIO_FELLSR) Falling Edge/Low Level Select Register 00870 #define PIO_REHLSR (AT91_CAST(AT91_REG *) 0x000000D4) // (PIO_REHLSR) Rising Edge/ High Level Select Register 00871 #define PIO_FRLHSR (AT91_CAST(AT91_REG *) 0x000000D8) // (PIO_FRLHSR) Fall/Rise - Low/High Status Register 00872 #define PIO_LOCKSR (AT91_CAST(AT91_REG *) 0x000000E0) // (PIO_LOCKSR) Lock Status Register 00873 #define PIO_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (PIO_VER) PIO VERSION REGISTER 00874 #define PIO_KER (AT91_CAST(AT91_REG *) 0x00000120) // (PIO_KER) Keypad Controller Enable Register 00875 #define PIO_KRCR (AT91_CAST(AT91_REG *) 0x00000124) // (PIO_KRCR) Keypad Controller Row Column Register 00876 #define PIO_KDR (AT91_CAST(AT91_REG *) 0x00000128) // (PIO_KDR) Keypad Controller Debouncing Register 00877 #define PIO_KIER (AT91_CAST(AT91_REG *) 0x00000130) // (PIO_KIER) Keypad Controller Interrupt Enable Register 00878 #define PIO_KIDR (AT91_CAST(AT91_REG *) 0x00000134) // (PIO_KIDR) Keypad Controller Interrupt Disable Register 00879 #define PIO_KIMR (AT91_CAST(AT91_REG *) 0x00000138) // (PIO_KIMR) Keypad Controller Interrupt Mask Register 00880 #define PIO_KSR (AT91_CAST(AT91_REG *) 0x0000013C) // (PIO_KSR) Keypad Controller Status Register 00881 #define PIO_KKPR (AT91_CAST(AT91_REG *) 0x00000140) // (PIO_KKPR) Keypad Controller Key Press Register 00882 #define PIO_KKRR (AT91_CAST(AT91_REG *) 0x00000144) // (PIO_KKRR) Keypad Controller Key Release Register 00883 00884 #endif 00885 // -------- PIO_KER : (PIO Offset: 0x120) Keypad Controller Enable Register -------- 00886 #define AT91C_PIO_KCE (0x1 << 0) // (PIO) Keypad Controller Enable 00887 // -------- PIO_KRCR : (PIO Offset: 0x124) Keypad Controller Row Column Register -------- 00888 #define AT91C_PIO_NBR (0x7 << 0) // (PIO) Number of Columns of the Keypad Matrix 00889 #define AT91C_PIO_NBC (0x7 << 8) // (PIO) Number of Rows of the Keypad Matrix 00890 // -------- PIO_KDR : (PIO Offset: 0x128) Keypad Controller Debouncing Register -------- 00891 #define AT91C_PIO_DBC (0x3FF << 0) // (PIO) Debouncing Value 00892 // -------- PIO_KIER : (PIO Offset: 0x130) Keypad Controller Interrupt Enable Register -------- 00893 #define AT91C_PIO_KPR (0x1 << 0) // (PIO) Key Press Interrupt Enable 00894 #define AT91C_PIO_KRL (0x1 << 1) // (PIO) Key Release Interrupt Enable 00895 // -------- PIO_KIDR : (PIO Offset: 0x134) Keypad Controller Interrupt Disable Register -------- 00896 // -------- PIO_KIMR : (PIO Offset: 0x138) Keypad Controller Interrupt Mask Register -------- 00897 // -------- PIO_KSR : (PIO Offset: 0x13c) Keypad Controller Status Register -------- 00898 #define AT91C_PIO_NBKPR (0x3 << 8) // (PIO) Number of Simultaneous Key Presses 00899 #define AT91C_PIO_NBKRL (0x3 << 16) // (PIO) Number of Simultaneous Key Releases 00900 // -------- PIO_KKPR : (PIO Offset: 0x140) Keypad Controller Key Press Register -------- 00901 #define AT91C_KEY0ROW (0x7 << 0) // (PIO) Row index of the first detected Key Press 00902 #define AT91C_KEY0COL (0x7 << 4) // (PIO) Column index of the first detected Key Press 00903 #define AT91C_KEY1ROW (0x7 << 8) // (PIO) Row index of the second detected Key Press 00904 #define AT91C_KEY1COL (0x7 << 12) // (PIO) Column index of the second detected Key Press 00905 #define AT91C_KEY2ROW (0x7 << 16) // (PIO) Row index of the third detected Key Press 00906 #define AT91C_KEY2COL (0x7 << 20) // (PIO) Column index of the third detected Key Press 00907 #define AT91C_KEY3ROW (0x7 << 24) // (PIO) Row index of the fourth detected Key Press 00908 #define AT91C_KEY3COL (0x7 << 28) // (PIO) Column index of the fourth detected Key Press 00909 // -------- PIO_KKRR : (PIO Offset: 0x144) Keypad Controller Key Release Register -------- 00910 00911 // ***************************************************************************** 00912 // SOFTWARE API DEFINITION FOR Power Management Controler 00913 // ***************************************************************************** 00914 #ifndef __ASSEMBLY__ 00915 #else 00916 #define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register 00917 #define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register 00918 #define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register 00919 #define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register 00920 #define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register 00921 #define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register 00922 #define CKGR_UCKR (AT91_CAST(AT91_REG *) 0x0000001C) // (CKGR_UCKR) UTMI Clock Configuration Register 00923 #define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000020) // (CKGR_MOR) Main Oscillator Register 00924 #define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000024) // (CKGR_MCFR) Main Clock Frequency Register 00925 #define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000028) // (CKGR_PLLAR) PLL Register 00926 #define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register 00927 #define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register 00928 #define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register 00929 #define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register 00930 #define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register 00931 #define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register 00932 #define PMC_FSMR (AT91_CAST(AT91_REG *) 0x00000070) // (PMC_FSMR) Fast Startup Mode Register 00933 #define PMC_FSPR (AT91_CAST(AT91_REG *) 0x00000074) // (PMC_FSPR) Fast Startup Polarity Register 00934 #define PMC_FOCR (AT91_CAST(AT91_REG *) 0x00000078) // (PMC_FOCR) Fault Output Clear Register 00935 #define PMC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (PMC_ADDRSIZE) PMC ADDRSIZE REGISTER 00936 #define PMC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (PMC_IPNAME1) PMC IPNAME1 REGISTER 00937 #define PMC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (PMC_IPNAME2) PMC IPNAME2 REGISTER 00938 #define PMC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (PMC_FEATURES) PMC FEATURES REGISTER 00939 #define PMC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (PMC_VER) APMC VERSION REGISTER 00940 00941 #endif 00942 // -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 00943 #define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock 00944 #define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output 00945 #define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output 00946 #define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output 00947 // -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 00948 // -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 00949 // -------- CKGR_UCKR : (PMC Offset: 0x1c) UTMI Clock Configuration Register -------- 00950 #define AT91C_CKGR_UPLLEN (0x1 << 16) // (PMC) UTMI PLL Enable 00951 #define AT91C_CKGR_UPLLEN_DISABLED (0x0 << 16) // (PMC) The UTMI PLL is disabled 00952 #define AT91C_CKGR_UPLLEN_ENABLED (0x1 << 16) // (PMC) The UTMI PLL is enabled 00953 #define AT91C_CKGR_UPLLCOUNT (0xF << 20) // (PMC) UTMI Oscillator Start-up Time 00954 #define AT91C_CKGR_BIASEN (0x1 << 24) // (PMC) UTMI BIAS Enable 00955 #define AT91C_CKGR_BIASEN_DISABLED (0x0 << 24) // (PMC) The UTMI BIAS is disabled 00956 #define AT91C_CKGR_BIASEN_ENABLED (0x1 << 24) // (PMC) The UTMI BIAS is enabled 00957 #define AT91C_CKGR_BIASCOUNT (0xF << 28) // (PMC) UTMI BIAS Start-up Time 00958 // -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 00959 #define AT91C_CKGR_MOSCXTEN (0x1 << 0) // (PMC) Main Crystal Oscillator Enable 00960 #define AT91C_CKGR_MOSCXTBY (0x1 << 1) // (PMC) Main Crystal Oscillator Bypass 00961 #define AT91C_CKGR_WAITMODE (0x1 << 2) // (PMC) Main Crystal Oscillator Bypass 00962 #define AT91C_CKGR_MOSCRCEN (0x1 << 3) // (PMC) Main On-Chip RC Oscillator Enable 00963 #define AT91C_CKGR_MOSCRCF (0x7 << 4) // (PMC) Main On-Chip RC Oscillator Frequency Selection 00964 #define AT91C_CKGR_MOSCXTST (0xFF << 8) // (PMC) Main Crystal Oscillator Start-up Time 00965 #define AT91C_CKGR_KEY (0xFF << 16) // (PMC) Clock Generator Controller Writing Protection Key 00966 #define AT91C_CKGR_MOSCSEL (0x1 << 24) // (PMC) Main Oscillator Selection 00967 #define AT91C_CKGR_CFDEN (0x1 << 25) // (PMC) Clock Failure Detector Enable 00968 // -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 00969 #define AT91C_CKGR_MAINF (0xFFFF << 0) // (PMC) Main Clock Frequency 00970 #define AT91C_CKGR_MAINRDY (0x1 << 16) // (PMC) Main Clock Ready 00971 // -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register -------- 00972 #define AT91C_CKGR_DIVA (0xFF << 0) // (PMC) Divider Selected 00973 #define AT91C_CKGR_DIVA_0 (0x0) // (PMC) Divider output is 0 00974 #define AT91C_CKGR_DIVA_BYPASS (0x1) // (PMC) Divider is bypassed 00975 #define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (PMC) PLLA Counter 00976 #define AT91C_CKGR_STMODE (0x3 << 14) // (PMC) Start Mode 00977 #define AT91C_CKGR_STMODE_0 (0x0 << 14) // (PMC) Fast startup 00978 #define AT91C_CKGR_STMODE_1 (0x1 << 14) // (PMC) Reserved 00979 #define AT91C_CKGR_STMODE_2 (0x2 << 14) // (PMC) Normal startup 00980 #define AT91C_CKGR_STMODE_3 (0x3 << 14) // (PMC) Reserved 00981 #define AT91C_CKGR_MULA (0x7FF << 16) // (PMC) PLL Multiplier 00982 #define AT91C_CKGR_SRC (0x1 << 29) // (PMC) 00983 // -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 00984 #define AT91C_PMC_CSS (0x7 << 0) // (PMC) Programmable Clock Selection 00985 #define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected 00986 #define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected 00987 #define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected 00988 #define AT91C_PMC_CSS_UPLL_CLK (0x3) // (PMC) Clock from UPLL is selected 00989 #define AT91C_PMC_CSS_SYS_CLK (0x4) // (PMC) System clock is selected 00990 #define AT91C_PMC_PRES (0x7 << 4) // (PMC) Programmable Clock Prescaler 00991 #define AT91C_PMC_PRES_CLK (0x0 << 4) // (PMC) Selected clock 00992 #define AT91C_PMC_PRES_CLK_2 (0x1 << 4) // (PMC) Selected clock divided by 2 00993 #define AT91C_PMC_PRES_CLK_4 (0x2 << 4) // (PMC) Selected clock divided by 4 00994 #define AT91C_PMC_PRES_CLK_8 (0x3 << 4) // (PMC) Selected clock divided by 8 00995 #define AT91C_PMC_PRES_CLK_16 (0x4 << 4) // (PMC) Selected clock divided by 16 00996 #define AT91C_PMC_PRES_CLK_32 (0x5 << 4) // (PMC) Selected clock divided by 32 00997 #define AT91C_PMC_PRES_CLK_64 (0x6 << 4) // (PMC) Selected clock divided by 64 00998 #define AT91C_PMC_PRES_CLK_6 (0x7 << 4) // (PMC) Selected clock divided by 6 00999 // -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 01000 // -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 01001 #define AT91C_PMC_MOSCXTS (0x1 << 0) // (PMC) Main Crystal Oscillator Status/Enable/Disable/Mask 01002 #define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask 01003 #define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask 01004 #define AT91C_PMC_LOCKU (0x1 << 6) // (PMC) PLL UTMI Status/Enable/Disable/Mask 01005 #define AT91C_PMC_PCKRDY0 (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask 01006 #define AT91C_PMC_PCKRDY1 (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask 01007 #define AT91C_PMC_PCKRDY2 (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask 01008 #define AT91C_PMC_MOSCSELS (0x1 << 16) // (PMC) Main Oscillator Selection Status 01009 #define AT91C_PMC_MOSCRCS (0x1 << 17) // (PMC) Main On-Chip RC Oscillator Status 01010 #define AT91C_PMC_CFDEV (0x1 << 18) // (PMC) Clock Failure Detector Event 01011 // -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 01012 // -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 01013 #define AT91C_PMC_OSCSELS (0x1 << 7) // (PMC) Slow Clock Oscillator Selection 01014 #define AT91C_PMC_CFDS (0x1 << 19) // (PMC) Clock Failure Detector Status 01015 #define AT91C_PMC_FOS (0x1 << 20) // (PMC) Clock Failure Detector Fault Output Status 01016 // -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 01017 // -------- PMC_FSMR : (PMC Offset: 0x70) Fast Startup Mode Register -------- 01018 #define AT91C_PMC_FSTT (0xFFFF << 0) // (PMC) Fast Start-up Input Enable 0 to 15 01019 #define AT91C_PMC_RTTAL (0x1 << 16) // (PMC) RTT Alarm Enable 01020 #define AT91C_PMC_RTCAL (0x1 << 17) // (PMC) RTC Alarm Enable 01021 #define AT91C_PMC_USBAL (0x1 << 18) // (PMC) USB Alarm Enable 01022 #define AT91C_PMC_LPM (0x1 << 20) // (PMC) Low Power Mode 01023 // -------- PMC_FSPR : (PMC Offset: 0x74) Fast Startup Polarity Register -------- 01024 #define AT91C_PMC_FSTP (0xFFFF << 0) // (PMC) Fast Start-up Input Polarity 0 to 15 01025 // -------- PMC_FOCR : (PMC Offset: 0x78) Fault Output Clear Register -------- 01026 #define AT91C_PMC_FOCLR (0x1 << 0) // (PMC) Fault Output Clear 01027 01028 // ***************************************************************************** 01029 // SOFTWARE API DEFINITION FOR Clock Generator Controler 01030 // ***************************************************************************** 01031 // -------- CKGR_UCKR : (CKGR Offset: 0x0) UTMI Clock Configuration Register -------- 01032 // -------- CKGR_MOR : (CKGR Offset: 0x4) Main Oscillator Register -------- 01033 // -------- CKGR_MCFR : (CKGR Offset: 0x8) Main Clock Frequency Register -------- 01034 // -------- CKGR_PLLAR : (CKGR Offset: 0xc) PLL A Register -------- 01035 01036 // ***************************************************************************** 01037 // SOFTWARE API DEFINITION FOR Reset Controller Interface 01038 // ***************************************************************************** 01039 #ifndef __ASSEMBLY__ 01040 #else 01041 #define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register 01042 #define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register 01043 #define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register 01044 #define RSTC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (RSTC_VER) Version Register 01045 01046 #endif 01047 // -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 01048 #define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset 01049 #define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset 01050 #define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset 01051 #define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset 01052 #define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password 01053 // -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 01054 #define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status 01055 #define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type 01056 #define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising. 01057 #define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. 01058 #define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. 01059 #define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. 01060 #define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. 01061 #define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level 01062 #define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. 01063 // -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 01064 #define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable 01065 #define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable 01066 #define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable 01067 01068 // ***************************************************************************** 01069 // SOFTWARE API DEFINITION FOR Supply Controller Interface 01070 // ***************************************************************************** 01071 #ifndef __ASSEMBLY__ 01072 #else 01073 #define SUPC_CR (AT91_CAST(AT91_REG *) 0x00000000) // Supply Controller Control Register 01074 #define SUPC_SMMR (AT91_CAST(AT91_REG *) 0x00000004) // Supply Controller Supply Monitor Mode Register 01075 #define SUPC_MR (AT91_CAST(AT91_REG *) 0x00000008) // Supply Controller Mode Register 01076 #define SUPC_WUMR (AT91_CAST(AT91_REG *) 0x0000000C) // Supply Controller Wake Up Mode Register 01077 #define SUPC_WUIR (AT91_CAST(AT91_REG *) 0x00000010) // Supply Controller Wake Up Inputs Register 01078 #define SUPC_SR (AT91_CAST(AT91_REG *) 0x00000014) // Supply Controller Status Register 01079 #endif 01080 // -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- 01081 #define AT91C_SUPC_CR_VROFF (0x1 << 2) // (SUPC) Voltage Regulator Off 01082 #define AT91C_SUPC_CR_VROFF_NO_EFFECT (0x0 << 2) // (SUPC) no effect. 01083 #define AT91C_SUPC_CR_VROFF_STOP_VREG (0x1 << 2) // (SUPC) if KEY is correct, asserts vddcore_nreset and stops the voltage regulator. 01084 #define AT91C_SUPC_CR_XTALSEL (0x1 << 3) // (SUPC) Crystal Oscillator Select 01085 #define AT91C_SUPC_CR_XTALSEL_NO_EFFECT (0x0 << 3) // (SUPC) no effect. 01086 #define AT91C_SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1 << 3) // (SUPC) if KEY is correct, switches the slow clock on the crystal oscillator output. 01087 #define AT91C_SUPC_CR_KEY (0xff << 24) // (SUPC) Password 01088 // -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- 01089 #define AT91C_SUPC_SMMR_SMTH (0xf << 0) // (SUPC) Supply Monitor Threshold 01090 #define AT91C_SUPC_SMMR_SMTH_1_9V (0x0 << 0) // (SUPC) 1.9 V 01091 #define AT91C_SUPC_SMMR_SMTH_2_0V (0x1 << 0) // (SUPC) 2.0 V 01092 #define AT91C_SUPC_SMMR_SMTH_2_1V (0x2 << 0) // (SUPC) 2.1 V 01093 #define AT91C_SUPC_SMMR_SMTH_2_2V (0x3 << 0) // (SUPC) 2.2 V 01094 #define AT91C_SUPC_SMMR_SMTH_2_3V (0x4 << 0) // (SUPC) 2.3 V 01095 #define AT91C_SUPC_SMMR_SMTH_2_4V (0x5 << 0) // (SUPC) 2.4 V 01096 #define AT91C_SUPC_SMMR_SMTH_2_5V (0x6 << 0) // (SUPC) 2.5 V 01097 #define AT91C_SUPC_SMMR_SMTH_2_6V (0x7 << 0) // (SUPC) 2.6 V 01098 #define AT91C_SUPC_SMMR_SMTH_2_7V (0x8 << 0) // (SUPC) 2.7 V 01099 #define AT91C_SUPC_SMMR_SMTH_2_8V (0x9 << 0) // (SUPC) 2.8 V 01100 #define AT91C_SUPC_SMMR_SMTH_2_9V (0xA << 0) // (SUPC) 2.9 V 01101 #define AT91C_SUPC_SMMR_SMTH_3_0V (0xB << 0) // (SUPC) 3.0 V 01102 #define AT91C_SUPC_SMMR_SMTH_3_1V (0xC << 0) // (SUPC) 3.1 V 01103 #define AT91C_SUPC_SMMR_SMTH_3_2V (0xD << 0) // (SUPC) 3.2 V 01104 #define AT91C_SUPC_SMMR_SMTH_3_3V (0xE << 0) // (SUPC) 3.3 V 01105 #define AT91C_SUPC_SMMR_SMTH_3_4V (0xF << 0) // (SUPC) 3.4 V 01106 #define AT91C_SUPC_SMMR_SMSMPL (0x7 << 8) // (SUPC) Supply Monitor Sampling Period 01107 #define AT91C_SUPC_SMMR_SMSMPL_SMD (0x0 << 8) // (SUPC) Supply Monitor disabled 01108 #define AT91C_SUPC_SMMR_SMSMPL_CSM (0x1 << 8) // (SUPC) Continuous Supply Monitor 01109 #define AT91C_SUPC_SMMR_SMSMPL_32SLCK (0x2 << 8) // (SUPC) Supply Monitor enabled one SLCK period every 32 SLCK periods 01110 #define AT91C_SUPC_SMMR_SMSMPL_256SLCK (0x3 << 8) // (SUPC) Supply Monitor enabled one SLCK period every 256 SLCK periods 01111 #define AT91C_SUPC_SMMR_SMSMPL_2048SLCK (0x4 << 8) // (SUPC) Supply Monitor enabled one SLCK period every 2,048 SLCK periods 01112 #define AT91C_SUPC_SMMR_SMRSTEN (0x1 << 12) // (SUPC) Supply Monitor Reset Enable 01113 #define AT91C_SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0 << 12) // (SUPC) the core reset signal "vddcore_nreset" is not affected when a supply monitor detection occurs. 01114 #define AT91C_SUPC_SMMR_SMRSTEN_ENABLE (0x1 << 12) // (SUPC) the core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 01115 #define AT91C_SUPC_SMMR_SMIEN (0x1 << 13) // (SUPC) Supply Monitor Interrupt Enable 01116 #define AT91C_SUPC_SMMR_SMIEN_NOT_ENABLE (0x0 << 13) // (SUPC) the SUPC interrupt signal is not affected when a supply monitor detection occurs. 01117 #define AT91C_SUPC_SMMR_SMIEN_ENABLE (0x1 << 13) // (SUPC) the SUPC interrupt signal is asserted when a supply monitor detection occurs. 01118 // -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- 01119 #define AT91C_SUPC_MR_BODRSTEN (0x1 << 12) // (SUPC) Brownout Detector Reset Enable 01120 #define AT91C_SUPC_MR_BODRSTEN_NOT_ENABLE (0x0 << 12) // (SUPC) the core reset signal "vddcore_nreset" is not affected when a brownout detection occurs. 01121 #define AT91C_SUPC_MR_BODRSTEN_ENABLE (0x1 << 12) // (SUPC) the core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 01122 #define AT91C_SUPC_MR_BODDIS (0x1 << 13) // (SUPC) Brownout Detector Disable 01123 #define AT91C_SUPC_MR_BODDIS_ENABLE (0x0 << 13) // (SUPC) the core brownout detector is enabled. 01124 #define AT91C_SUPC_MR_BODDIS_DISABLE (0x1 << 13) // (SUPC) the core brownout detector is disabled. 01125 #define AT91C_SUPC_MR_VDDIORDY (0x1 << 14) // (SUPC) VDDIO Ready 01126 #define AT91C_SUPC_MR_VDDIORDY_VDDIO_REMOVED (0x0 << 14) // (SUPC) VDDIO is removed (used before going to backup mode when backup batteries are used) 01127 #define AT91C_SUPC_MR_VDDIORDY_VDDIO_PRESENT (0x1 << 14) // (SUPC) VDDIO is present (used before going to backup mode when backup batteries are used) 01128 #define AT91C_SUPC_MR_OSCBYPASS (0x1 << 20) // (SUPC) Oscillator Bypass 01129 #define AT91C_SUPC_MR_OSCBYPASS_NO_EFFECT (0x0 << 20) // (SUPC) no effect. Clock selection depends on XTALSEL value. 01130 #define AT91C_SUPC_MR_OSCBYPASS_BYPASS (0x1 << 20) // (SUPC) the 32-KHz XTAL oscillator is selected and is put in bypass mode. 01131 #define AT91C_SUPC_MR_KEY (0xff << 24) // (SUPC) Password Key 01132 // -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake Up Mode Register -------- 01133 #define AT91C_SUPC_WUMR_FWUPEN (0x1 << 0) // (SUPC) Force Wake Up Enable 01134 #define AT91C_SUPC_WUMR_FWUPEN_NOT_ENABLE (0x0 << 0) // (SUPC) the Force Wake Up pin has no wake up effect. 01135 #define AT91C_SUPC_WUMR_FWUPEN_ENABLE (0x1 << 0) // (SUPC) the Force Wake Up pin low forces the wake up of the core power supply. 01136 #define AT91C_SUPC_WUMR_SMEN (0x1 << 1) // (SUPC) Supply Monitor Wake Up Enable 01137 #define AT91C_SUPC_WUMR_SMEN_NOT_ENABLE (0x0 << 1) // (SUPC) the supply monitor detection has no wake up effect. 01138 #define AT91C_SUPC_WUMR_SMEN_ENABLE (0x1 << 1) // (SUPC) the supply monitor detection forces the wake up of the core power supply. 01139 #define AT91C_SUPC_WUMR_RTTEN (0x1 << 2) // (SUPC) Real Time Timer Wake Up Enable 01140 #define AT91C_SUPC_WUMR_RTTEN_NOT_ENABLE (0x0 << 2) // (SUPC) the RTT alarm signal has no wake up effect. 01141 #define AT91C_SUPC_WUMR_RTTEN_ENABLE (0x1 << 2) // (SUPC) the RTT alarm signal forces the wake up of the core power supply. 01142 #define AT91C_SUPC_WUMR_RTCEN (0x1 << 3) // (SUPC) Real Time Clock Wake Up Enable 01143 #define AT91C_SUPC_WUMR_RTCEN_NOT_ENABLE (0x0 << 3) // (SUPC) the RTC alarm signal has no wake up effect. 01144 #define AT91C_SUPC_WUMR_RTCEN_ENABLE (0x1 << 3) // (SUPC) the RTC alarm signal forces the wake up of the core power supply. 01145 #define AT91C_SUPC_WUMR_FWUPDBC (0x7 << 8) // (SUPC) Force Wake Up Debouncer 01146 #define AT91C_SUPC_WUMR_FWUPDBC_1SCLK (0x0 << 8) // (SUPC) Immediate, no debouncing, detected active at least on one Slow Clock edge. 01147 #define AT91C_SUPC_WUMR_FWUPDBC_3SCLK (0x1 << 8) // (SUPC) FWUP shall be low for at least 3 SLCK periods 01148 #define AT91C_SUPC_WUMR_FWUPDBC_32SCLK (0x2 << 8) // (SUPC) FWUP shall be low for at least 32 SLCK periods 01149 #define AT91C_SUPC_WUMR_FWUPDBC_512SCLK (0x3 << 8) // (SUPC) FWUP shall be low for at least 512 SLCK periods 01150 #define AT91C_SUPC_WUMR_FWUPDBC_4096SCLK (0x4 << 8) // (SUPC) FWUP shall be low for at least 4,096 SLCK periods 01151 #define AT91C_SUPC_WUMR_FWUPDBC_32768SCLK (0x5 << 8) // (SUPC) FWUP shall be low for at least 32,768 SLCK periods 01152 #define AT91C_SUPC_WUMR_WKUPDBC (0x7 << 12) // (SUPC) Wake Up Inputs Debouncer 01153 #define AT91C_SUPC_WUMR_WKUPDBC_1SCLK (0x0 << 12) // (SUPC) Immediate, no debouncing, detected active at least on one Slow Clock edge. 01154 #define AT91C_SUPC_WUMR_WKUPDBC_3SCLK (0x1 << 12) // (SUPC) An enabled wake-up input shall be active for at least 3 SLCK periods 01155 #define AT91C_SUPC_WUMR_WKUPDBC_32SCLK (0x2 << 12) // (SUPC) An enabled wake-up input shall be active for at least 32 SLCK periods 01156 #define AT91C_SUPC_WUMR_WKUPDBC_512SCLK (0x3 << 12) // (SUPC) An enabled wake-up input shall be active for at least 512 SLCK periods 01157 #define AT91C_SUPC_WUMR_WKUPDBC_4096SCLK (0x4 << 12) // (SUPC) An enabled wake-up input shall be active for at least 4,096 SLCK periods 01158 #define AT91C_SUPC_WUMR_WKUPDBC_32768SCLK (0x5 << 12) // (SUPC) An enabled wake-up input shall be active for at least 32,768 SLCK periods 01159 // -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake Up Inputs Register -------- 01160 #define AT91C_SUPC_WUIR_WKUPEN0 (0x1 << 0) // (SUPC) Wake Up Input Enable 0 01161 #define AT91C_SUPC_WUIR_WKUPEN0_NOT_ENABLE (0x0 << 0) // (SUPC) the corresponding wake-up input has no wake up effect. 01162 #define AT91C_SUPC_WUIR_WKUPEN0_ENABLE (0x1 << 0) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01163 #define AT91C_SUPC_WUIR_WKUPEN1 (0x1 << 1) // (SUPC) Wake Up Input Enable 1 01164 #define AT91C_SUPC_WUIR_WKUPEN1_NOT_ENABLE (0x0 << 1) // (SUPC) the corresponding wake-up input has no wake up effect. 01165 #define AT91C_SUPC_WUIR_WKUPEN1_ENABLE (0x1 << 1) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01166 #define AT91C_SUPC_WUIR_WKUPEN2 (0x1 << 2) // (SUPC) Wake Up Input Enable 2 01167 #define AT91C_SUPC_WUIR_WKUPEN2_NOT_ENABLE (0x0 << 2) // (SUPC) the corresponding wake-up input has no wake up effect. 01168 #define AT91C_SUPC_WUIR_WKUPEN2_ENABLE (0x1 << 2) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01169 #define AT91C_SUPC_WUIR_WKUPEN3 (0x1 << 3) // (SUPC) Wake Up Input Enable 3 01170 #define AT91C_SUPC_WUIR_WKUPEN3_NOT_ENABLE (0x0 << 3) // (SUPC) the corresponding wake-up input has no wake up effect. 01171 #define AT91C_SUPC_WUIR_WKUPEN3_ENABLE (0x1 << 3) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01172 #define AT91C_SUPC_WUIR_WKUPEN4 (0x1 << 4) // (SUPC) Wake Up Input Enable 4 01173 #define AT91C_SUPC_WUIR_WKUPEN4_NOT_ENABLE (0x0 << 4) // (SUPC) the corresponding wake-up input has no wake up effect. 01174 #define AT91C_SUPC_WUIR_WKUPEN4_ENABLE (0x1 << 4) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01175 #define AT91C_SUPC_WUIR_WKUPEN5 (0x1 << 5) // (SUPC) Wake Up Input Enable 5 01176 #define AT91C_SUPC_WUIR_WKUPEN5_NOT_ENABLE (0x0 << 5) // (SUPC) the corresponding wake-up input has no wake up effect. 01177 #define AT91C_SUPC_WUIR_WKUPEN5_ENABLE (0x1 << 5) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01178 #define AT91C_SUPC_WUIR_WKUPEN6 (0x1 << 6) // (SUPC) Wake Up Input Enable 6 01179 #define AT91C_SUPC_WUIR_WKUPEN6_NOT_ENABLE (0x0 << 6) // (SUPC) the corresponding wake-up input has no wake up effect. 01180 #define AT91C_SUPC_WUIR_WKUPEN6_ENABLE (0x1 << 6) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01181 #define AT91C_SUPC_WUIR_WKUPEN7 (0x1 << 7) // (SUPC) Wake Up Input Enable 7 01182 #define AT91C_SUPC_WUIR_WKUPEN7_NOT_ENABLE (0x0 << 7) // (SUPC) the corresponding wake-up input has no wake up effect. 01183 #define AT91C_SUPC_WUIR_WKUPEN7_ENABLE (0x1 << 7) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01184 #define AT91C_SUPC_WUIR_WKUPEN8 (0x1 << 8) // (SUPC) Wake Up Input Enable 8 01185 #define AT91C_SUPC_WUIR_WKUPEN8_NOT_ENABLE (0x0 << 8) // (SUPC) the corresponding wake-up input has no wake up effect. 01186 #define AT91C_SUPC_WUIR_WKUPEN8_ENABLE (0x1 << 8) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01187 #define AT91C_SUPC_WUIR_WKUPEN9 (0x1 << 9) // (SUPC) Wake Up Input Enable 9 01188 #define AT91C_SUPC_WUIR_WKUPEN9_NOT_ENABLE (0x0 << 9) // (SUPC) the corresponding wake-up input has no wake up effect. 01189 #define AT91C_SUPC_WUIR_WKUPEN9_ENABLE (0x1 << 9) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01190 #define AT91C_SUPC_WUIR_WKUPEN10 (0x1 << 10) // (SUPC) Wake Up Input Enable 10 01191 #define AT91C_SUPC_WUIR_WKUPEN10_NOT_ENABLE (0x0 << 10) // (SUPC) the corresponding wake-up input has no wake up effect. 01192 #define AT91C_SUPC_WUIR_WKUPEN10_ENABLE (0x1 << 10) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01193 #define AT91C_SUPC_WUIR_WKUPEN11 (0x1 << 11) // (SUPC) Wake Up Input Enable 11 01194 #define AT91C_SUPC_WUIR_WKUPEN11_NOT_ENABLE (0x0 << 11) // (SUPC) the corresponding wake-up input has no wake up effect. 01195 #define AT91C_SUPC_WUIR_WKUPEN11_ENABLE (0x1 << 11) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01196 #define AT91C_SUPC_WUIR_WKUPEN12 (0x1 << 12) // (SUPC) Wake Up Input Enable 12 01197 #define AT91C_SUPC_WUIR_WKUPEN12_NOT_ENABLE (0x0 << 12) // (SUPC) the corresponding wake-up input has no wake up effect. 01198 #define AT91C_SUPC_WUIR_WKUPEN12_ENABLE (0x1 << 12) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01199 #define AT91C_SUPC_WUIR_WKUPEN13 (0x1 << 13) // (SUPC) Wake Up Input Enable 13 01200 #define AT91C_SUPC_WUIR_WKUPEN13_NOT_ENABLE (0x0 << 13) // (SUPC) the corresponding wake-up input has no wake up effect. 01201 #define AT91C_SUPC_WUIR_WKUPEN13_ENABLE (0x1 << 13) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01202 #define AT91C_SUPC_WUIR_WKUPEN14 (0x1 << 14) // (SUPC) Wake Up Input Enable 14 01203 #define AT91C_SUPC_WUIR_WKUPEN14_NOT_ENABLE (0x0 << 14) // (SUPC) the corresponding wake-up input has no wake up effect. 01204 #define AT91C_SUPC_WUIR_WKUPEN14_ENABLE (0x1 << 14) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01205 #define AT91C_SUPC_WUIR_WKUPEN15 (0x1 << 15) // (SUPC) Wake Up Input Enable 15 01206 #define AT91C_SUPC_WUIR_WKUPEN15_NOT_ENABLE (0x0 << 15) // (SUPC) the corresponding wake-up input has no wake up effect. 01207 #define AT91C_SUPC_WUIR_WKUPEN15_ENABLE (0x1 << 15) // (SUPC) the corresponding wake-up input forces the wake up of the core power supply. 01208 #define AT91C_SUPC_WUIR_WKUPT0 (0x1 << 16) // (SUPC) Wake Up Input Transition 0 01209 #define AT91C_SUPC_WUIR_WKUPT0_HIGH_TO_LOW (0x0 << 16) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01210 #define AT91C_SUPC_WUIR_WKUPT0_LOW_TO_HIGH (0x1 << 16) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01211 #define AT91C_SUPC_WUIR_WKUPT1 (0x1 << 17) // (SUPC) Wake Up Input Transition 1 01212 #define AT91C_SUPC_WUIR_WKUPT1_HIGH_TO_LOW (0x0 << 17) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01213 #define AT91C_SUPC_WUIR_WKUPT1_LOW_TO_HIGH (0x1 << 17) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01214 #define AT91C_SUPC_WUIR_WKUPT2 (0x1 << 18) // (SUPC) Wake Up Input Transition 2 01215 #define AT91C_SUPC_WUIR_WKUPT2_HIGH_TO_LOW (0x0 << 18) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01216 #define AT91C_SUPC_WUIR_WKUPT2_LOW_TO_HIGH (0x1 << 18) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01217 #define AT91C_SUPC_WUIR_WKUPT3 (0x1 << 19) // (SUPC) Wake Up Input Transition 3 01218 #define AT91C_SUPC_WUIR_WKUPT3_HIGH_TO_LOW (0x0 << 19) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01219 #define AT91C_SUPC_WUIR_WKUPT3_LOW_TO_HIGH (0x1 << 19) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01220 #define AT91C_SUPC_WUIR_WKUPT4 (0x1 << 20) // (SUPC) Wake Up Input Transition 4 01221 #define AT91C_SUPC_WUIR_WKUPT4_HIGH_TO_LOW (0x0 << 20) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01222 #define AT91C_SUPC_WUIR_WKUPT4_LOW_TO_HIGH (0x1 << 20) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01223 #define AT91C_SUPC_WUIR_WKUPT5 (0x1 << 21) // (SUPC) Wake Up Input Transition 5 01224 #define AT91C_SUPC_WUIR_WKUPT5_HIGH_TO_LOW (0x0 << 21) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01225 #define AT91C_SUPC_WUIR_WKUPT5_LOW_TO_HIGH (0x1 << 21) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01226 #define AT91C_SUPC_WUIR_WKUPT6 (0x1 << 22) // (SUPC) Wake Up Input Transition 6 01227 #define AT91C_SUPC_WUIR_WKUPT6_HIGH_TO_LOW (0x0 << 22) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01228 #define AT91C_SUPC_WUIR_WKUPT6_LOW_TO_HIGH (0x1 << 22) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01229 #define AT91C_SUPC_WUIR_WKUPT7 (0x1 << 23) // (SUPC) Wake Up Input Transition 7 01230 #define AT91C_SUPC_WUIR_WKUPT7_HIGH_TO_LOW (0x0 << 23) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01231 #define AT91C_SUPC_WUIR_WKUPT7_LOW_TO_HIGH (0x1 << 23) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01232 #define AT91C_SUPC_WUIR_WKUPT8 (0x1 << 24) // (SUPC) Wake Up Input Transition 8 01233 #define AT91C_SUPC_WUIR_WKUPT8_HIGH_TO_LOW (0x0 << 24) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01234 #define AT91C_SUPC_WUIR_WKUPT8_LOW_TO_HIGH (0x1 << 24) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01235 #define AT91C_SUPC_WUIR_WKUPT9 (0x1 << 25) // (SUPC) Wake Up Input Transition 9 01236 #define AT91C_SUPC_WUIR_WKUPT9_HIGH_TO_LOW (0x0 << 25) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01237 #define AT91C_SUPC_WUIR_WKUPT9_LOW_TO_HIGH (0x1 << 25) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01238 #define AT91C_SUPC_WUIR_WKUPT10 (0x1 << 26) // (SUPC) Wake Up Input Transition 10 01239 #define AT91C_SUPC_WUIR_WKUPT10_HIGH_TO_LOW (0x0 << 26) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01240 #define AT91C_SUPC_WUIR_WKUPT10_LOW_TO_HIGH (0x1 << 26) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01241 #define AT91C_SUPC_WUIR_WKUPT11 (0x1 << 27) // (SUPC) Wake Up Input Transition 11 01242 #define AT91C_SUPC_WUIR_WKUPT11_HIGH_TO_LOW (0x0 << 27) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01243 #define AT91C_SUPC_WUIR_WKUPT11_LOW_TO_HIGH (0x1 << 27) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01244 #define AT91C_SUPC_WUIR_WKUPT12 (0x1 << 28) // (SUPC) Wake Up Input Transition 12 01245 #define AT91C_SUPC_WUIR_WKUPT12_HIGH_TO_LOW (0x0 << 28) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01246 #define AT91C_SUPC_WUIR_WKUPT12_LOW_TO_HIGH (0x1 << 28) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01247 #define AT91C_SUPC_WUIR_WKUPT13 (0x1 << 29) // (SUPC) Wake Up Input Transition 13 01248 #define AT91C_SUPC_WUIR_WKUPT13_HIGH_TO_LOW (0x0 << 29) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01249 #define AT91C_SUPC_WUIR_WKUPT13_LOW_TO_HIGH (0x1 << 29) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01250 #define AT91C_SUPC_WUIR_WKUPT14 (0x1 << 30) // (SUPC) Wake Up Input Transition 14 01251 #define AT91C_SUPC_WUIR_WKUPT14_HIGH_TO_LOW (0x0 << 30) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01252 #define AT91C_SUPC_WUIR_WKUPT14_LOW_TO_HIGH (0x1 << 30) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01253 #define AT91C_SUPC_WUIR_WKUPT15 (0x1 << 31) // (SUPC) Wake Up Input Transition 15 01254 #define AT91C_SUPC_WUIR_WKUPT15_HIGH_TO_LOW (0x0 << 31) // (SUPC) a high to low level transition on the corresponding wake-up input forces the wake up of the core power supply. 01255 #define AT91C_SUPC_WUIR_WKUPT15_LOW_TO_HIGH (0x1 << 31) // (SUPC) a low to high level transition on the corresponding wake-up input forces the wake up of the core power supply. 01256 // -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- 01257 #define AT91C_SUPC_SR_FWUPS (0x1 << 0) // (SUPC) FWUP Wake Up Status 01258 #define AT91C_SUPC_SR_FWUPS_NO (0x0 << 0) // (SUPC) no wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 01259 #define AT91C_SUPC_SR_FWUPS_PRESENT (0x1 << 0) // (SUPC) at least one wake up due to the assertion of the FWUP pin has occurred since the last read of SUPC_SR. 01260 #define AT91C_SUPC_SR_WKUPS (0x1 << 1) // (SUPC) WKUP Wake Up Status 01261 #define AT91C_SUPC_SR_WKUPS_NO (0x0 << 1) // (SUPC) no wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 01262 #define AT91C_SUPC_SR_WKUPS_PRESENT (0x1 << 1) // (SUPC) at least one wake up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 01263 #define AT91C_SUPC_SR_SMWS (0x1 << 2) // (SUPC) Supply Monitor Detection Wake Up Status 01264 #define AT91C_SUPC_SR_SMWS_NO (0x0 << 2) // (SUPC) no wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. 01265 #define AT91C_SUPC_SR_SMWS_PRESENT (0x1 << 2) // (SUPC) at least one wake up due to a supply monitor detection has occurred since the last read of SUPC_SR. 01266 #define AT91C_SUPC_SR_BODRSTS (0x1 << 3) // (SUPC) Brownout Detector Reset Status 01267 #define AT91C_SUPC_SR_BODRSTS_NO (0x0 << 3) // (SUPC) no core brownout detection has generated a core reset since the last read of the SUPC_SR. 01268 #define AT91C_SUPC_SR_BODRSTS_PRESENT (0x1 << 3) // (SUPC) at least one core brownout detection has generated a core reset since the last read of the SUPC_SR. 01269 #define AT91C_SUPC_SR_SMRSTS (0x1 << 4) // (SUPC) Supply Monitor Reset Status 01270 #define AT91C_SUPC_SR_SMRSTS_NO (0x0 << 4) // (SUPC) no supply monitor detection has generated a core reset since the last read of the SUPC_SR. 01271 #define AT91C_SUPC_SR_SMRSTS_PRESENT (0x1 << 4) // (SUPC) at least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 01272 #define AT91C_SUPC_SR_SMS (0x1 << 5) // (SUPC) Supply Monitor Status 01273 #define AT91C_SUPC_SR_SMS_NO (0x0 << 5) // (SUPC) no supply monitor detection since the last read of SUPC_SR. 01274 #define AT91C_SUPC_SR_SMS_PRESENT (0x1 << 5) // (SUPC) at least one supply monitor detection since the last read of SUPC_SR. 01275 #define AT91C_SUPC_SR_SMOS (0x1 << 6) // (SUPC) Supply Monitor Output Status 01276 #define AT91C_SUPC_SR_SMOS_HIGH (0x0 << 6) // (SUPC) the supply monitor detected VDDUTMI higher than its threshold at its last measurement. 01277 #define AT91C_SUPC_SR_SMOS_LOW (0x1 << 6) // (SUPC) the supply monitor detected VDDUTMI lower than its threshold at its last measurement. 01278 #define AT91C_SUPC_SR_OSCSEL (0x1 << 7) // (SUPC) 32-kHz Oscillator Selection Status 01279 #define AT91C_SUPC_SR_OSCSEL_RC (0x0 << 7) // (SUPC) the slow clock, SLCK is generated by the embedded 32-kHz RC oscillator. 01280 #define AT91C_SUPC_SR_OSCSEL_CRYST (0x1 << 7) // (SUPC) the slow clock, SLCK is generated by the 32-kHz crystal oscillator. 01281 #define AT91C_SUPC_SR_FWUPIS (0x1 << 12) // (SUPC) FWUP Input Status 01282 #define AT91C_SUPC_SR_FWUPIS_LOW (0x0 << 12) // (SUPC) FWUP input is tied low. 01283 #define AT91C_SUPC_SR_FWUPIS_HIGH (0x1 << 12) // (SUPC) FWUP input is tied high. 01284 #define AT91C_SUPC_SR_WKUPIS0 (0x1 << 16) // (SUPC) WKUP Input Status 0 01285 #define AT91C_SUPC_SR_WKUPIS0_DIS (0x0 << 16) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01286 #define AT91C_SUPC_SR_WKUPIS0_EN (0x1 << 16) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01287 #define AT91C_SUPC_SR_WKUPIS1 (0x1 << 17) // (SUPC) WKUP Input Status 1 01288 #define AT91C_SUPC_SR_WKUPIS1_DIS (0x0 << 17) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01289 #define AT91C_SUPC_SR_WKUPIS1_EN (0x1 << 17) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01290 #define AT91C_SUPC_SR_WKUPIS2 (0x1 << 18) // (SUPC) WKUP Input Status 2 01291 #define AT91C_SUPC_SR_WKUPIS2_DIS (0x0 << 18) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01292 #define AT91C_SUPC_SR_WKUPIS2_EN (0x1 << 18) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01293 #define AT91C_SUPC_SR_WKUPIS3 (0x1 << 19) // (SUPC) WKUP Input Status 3 01294 #define AT91C_SUPC_SR_WKUPIS3_DIS (0x0 << 19) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01295 #define AT91C_SUPC_SR_WKUPIS3_EN (0x1 << 19) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01296 #define AT91C_SUPC_SR_WKUPIS4 (0x1 << 20) // (SUPC) WKUP Input Status 4 01297 #define AT91C_SUPC_SR_WKUPIS4_DIS (0x0 << 20) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01298 #define AT91C_SUPC_SR_WKUPIS4_EN (0x1 << 20) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01299 #define AT91C_SUPC_SR_WKUPIS5 (0x1 << 21) // (SUPC) WKUP Input Status 5 01300 #define AT91C_SUPC_SR_WKUPIS5_DIS (0x0 << 21) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01301 #define AT91C_SUPC_SR_WKUPIS5_EN (0x1 << 21) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01302 #define AT91C_SUPC_SR_WKUPIS6 (0x1 << 22) // (SUPC) WKUP Input Status 6 01303 #define AT91C_SUPC_SR_WKUPIS6_DIS (0x0 << 22) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01304 #define AT91C_SUPC_SR_WKUPIS6_EN (0x1 << 22) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01305 #define AT91C_SUPC_SR_WKUPIS7 (0x1 << 23) // (SUPC) WKUP Input Status 7 01306 #define AT91C_SUPC_SR_WKUPIS7_DIS (0x0 << 23) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01307 #define AT91C_SUPC_SR_WKUPIS7_EN (0x1 << 23) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01308 #define AT91C_SUPC_SR_WKUPIS8 (0x1 << 24) // (SUPC) WKUP Input Status 8 01309 #define AT91C_SUPC_SR_WKUPIS8_DIS (0x0 << 24) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01310 #define AT91C_SUPC_SR_WKUPIS8_EN (0x1 << 24) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01311 #define AT91C_SUPC_SR_WKUPIS9 (0x1 << 25) // (SUPC) WKUP Input Status 9 01312 #define AT91C_SUPC_SR_WKUPIS9_DIS (0x0 << 25) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01313 #define AT91C_SUPC_SR_WKUPIS9_EN (0x1 << 25) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01314 #define AT91C_SUPC_SR_WKUPIS10 (0x1 << 26) // (SUPC) WKUP Input Status 10 01315 #define AT91C_SUPC_SR_WKUPIS10_DIS (0x0 << 26) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01316 #define AT91C_SUPC_SR_WKUPIS10_EN (0x1 << 26) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01317 #define AT91C_SUPC_SR_WKUPIS11 (0x1 << 27) // (SUPC) WKUP Input Status 11 01318 #define AT91C_SUPC_SR_WKUPIS11_DIS (0x0 << 27) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01319 #define AT91C_SUPC_SR_WKUPIS11_EN (0x1 << 27) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01320 #define AT91C_SUPC_SR_WKUPIS12 (0x1 << 28) // (SUPC) WKUP Input Status 12 01321 #define AT91C_SUPC_SR_WKUPIS12_DIS (0x0 << 28) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01322 #define AT91C_SUPC_SR_WKUPIS12_EN (0x1 << 28) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01323 #define AT91C_SUPC_SR_WKUPIS13 (0x1 << 29) // (SUPC) WKUP Input Status 13 01324 #define AT91C_SUPC_SR_WKUPIS13_DIS (0x0 << 29) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01325 #define AT91C_SUPC_SR_WKUPIS13_EN (0x1 << 29) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01326 #define AT91C_SUPC_SR_WKUPIS14 (0x1 << 30) // (SUPC) WKUP Input Status 14 01327 #define AT91C_SUPC_SR_WKUPIS14_DIS (0x0 << 30) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01328 #define AT91C_SUPC_SR_WKUPIS14_EN (0x1 << 30) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01329 #define AT91C_SUPC_SR_WKUPIS15 (0x1 << 31) // (SUPC) WKUP Input Status 15 01330 #define AT91C_SUPC_SR_WKUPIS15_DIS (0x0 << 31) // (SUPC) the corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake up event. 01331 #define AT91C_SUPC_SR_WKUPIS15_EN (0x1 << 31) // (SUPC) the corresponding wake-up input was active at the time the debouncer triggered a wake up event. 01332 01333 // ***************************************************************************** 01334 // SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface 01335 // ***************************************************************************** 01336 #ifndef __ASSEMBLY__ 01337 #else 01338 #define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register 01339 #define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register 01340 #define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register 01341 #define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register 01342 01343 #endif 01344 // -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 01345 #define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value 01346 #define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable 01347 #define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable 01348 #define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart 01349 // -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 01350 #define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value 01351 // -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 01352 #define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value 01353 // -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 01354 #define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status 01355 #define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment 01356 01357 // ***************************************************************************** 01358 // SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface 01359 // ***************************************************************************** 01360 #ifndef __ASSEMBLY__ 01361 #else 01362 #define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register 01363 #define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register 01364 #define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register 01365 01366 #endif 01367 // -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 01368 #define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart 01369 #define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password 01370 // -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 01371 #define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart 01372 #define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable 01373 #define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable 01374 #define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart 01375 #define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable 01376 #define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value 01377 #define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt 01378 #define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt 01379 // -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 01380 #define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow 01381 #define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error 01382 01383 // ***************************************************************************** 01384 // SOFTWARE API DEFINITION FOR Real-time Clock Alarm and Parallel Load Interface 01385 // ***************************************************************************** 01386 #ifndef __ASSEMBLY__ 01387 #else 01388 #define RTC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (RTC_CR) Control Register 01389 #define RTC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (RTC_MR) Mode Register 01390 #define RTC_TIMR (AT91_CAST(AT91_REG *) 0x00000008) // (RTC_TIMR) Time Register 01391 #define RTC_CALR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTC_CALR) Calendar Register 01392 #define RTC_TIMALR (AT91_CAST(AT91_REG *) 0x00000010) // (RTC_TIMALR) Time Alarm Register 01393 #define RTC_CALALR (AT91_CAST(AT91_REG *) 0x00000014) // (RTC_CALALR) Calendar Alarm Register 01394 #define RTC_SR (AT91_CAST(AT91_REG *) 0x00000018) // (RTC_SR) Status Register 01395 #define RTC_SCCR (AT91_CAST(AT91_REG *) 0x0000001C) // (RTC_SCCR) Status Clear Command Register 01396 #define RTC_IER (AT91_CAST(AT91_REG *) 0x00000020) // (RTC_IER) Interrupt Enable Register 01397 #define RTC_IDR (AT91_CAST(AT91_REG *) 0x00000024) // (RTC_IDR) Interrupt Disable Register 01398 #define RTC_IMR (AT91_CAST(AT91_REG *) 0x00000028) // (RTC_IMR) Interrupt Mask Register 01399 #define RTC_VER (AT91_CAST(AT91_REG *) 0x0000002C) // (RTC_VER) Valid Entry Register 01400 01401 #endif 01402 // -------- RTC_CR : (RTC Offset: 0x0) RTC Control Register -------- 01403 #define AT91C_RTC_UPDTIM (0x1 << 0) // (RTC) Update Request Time Register 01404 #define AT91C_RTC_UPDCAL (0x1 << 1) // (RTC) Update Request Calendar Register 01405 #define AT91C_RTC_TIMEVSEL (0x3 << 8) // (RTC) Time Event Selection 01406 #define AT91C_RTC_TIMEVSEL_MINUTE (0x0 << 8) // (RTC) Minute change. 01407 #define AT91C_RTC_TIMEVSEL_HOUR (0x1 << 8) // (RTC) Hour change. 01408 #define AT91C_RTC_TIMEVSEL_DAY24 (0x2 << 8) // (RTC) Every day at midnight. 01409 #define AT91C_RTC_TIMEVSEL_DAY12 (0x3 << 8) // (RTC) Every day at noon. 01410 #define AT91C_RTC_CALEVSEL (0x3 << 16) // (RTC) Calendar Event Selection 01411 #define AT91C_RTC_CALEVSEL_WEEK (0x0 << 16) // (RTC) Week change (every Monday at time 00:00:00). 01412 #define AT91C_RTC_CALEVSEL_MONTH (0x1 << 16) // (RTC) Month change (every 01 of each month at time 00:00:00). 01413 #define AT91C_RTC_CALEVSEL_YEAR (0x2 << 16) // (RTC) Year change (every January 1 at time 00:00:00). 01414 // -------- RTC_MR : (RTC Offset: 0x4) RTC Mode Register -------- 01415 #define AT91C_RTC_HRMOD (0x1 << 0) // (RTC) 12-24 hour Mode 01416 // -------- RTC_TIMR : (RTC Offset: 0x8) RTC Time Register -------- 01417 #define AT91C_RTC_SEC (0x7F << 0) // (RTC) Current Second 01418 #define AT91C_RTC_MIN (0x7F << 8) // (RTC) Current Minute 01419 #define AT91C_RTC_HOUR (0x3F << 16) // (RTC) Current Hour 01420 #define AT91C_RTC_AMPM (0x1 << 22) // (RTC) Ante Meridiem, Post Meridiem Indicator 01421 // -------- RTC_CALR : (RTC Offset: 0xc) RTC Calendar Register -------- 01422 #define AT91C_RTC_CENT (0x3F << 0) // (RTC) Current Century 01423 #define AT91C_RTC_YEAR (0xFF << 8) // (RTC) Current Year 01424 #define AT91C_RTC_MONTH (0x1F << 16) // (RTC) Current Month 01425 #define AT91C_RTC_DAY (0x7 << 21) // (RTC) Current Day 01426 #define AT91C_RTC_DATE (0x3F << 24) // (RTC) Current Date 01427 // -------- RTC_TIMALR : (RTC Offset: 0x10) RTC Time Alarm Register -------- 01428 #define AT91C_RTC_SECEN (0x1 << 7) // (RTC) Second Alarm Enable 01429 #define AT91C_RTC_MINEN (0x1 << 15) // (RTC) Minute Alarm 01430 #define AT91C_RTC_HOUREN (0x1 << 23) // (RTC) Current Hour 01431 // -------- RTC_CALALR : (RTC Offset: 0x14) RTC Calendar Alarm Register -------- 01432 #define AT91C_RTC_MONTHEN (0x1 << 23) // (RTC) Month Alarm Enable 01433 #define AT91C_RTC_DATEEN (0x1 << 31) // (RTC) Date Alarm Enable 01434 // -------- RTC_SR : (RTC Offset: 0x18) RTC Status Register -------- 01435 #define AT91C_RTC_ACKUPD (0x1 << 0) // (RTC) Acknowledge for Update 01436 #define AT91C_RTC_ALARM (0x1 << 1) // (RTC) Alarm Flag 01437 #define AT91C_RTC_SECEV (0x1 << 2) // (RTC) Second Event 01438 #define AT91C_RTC_TIMEV (0x1 << 3) // (RTC) Time Event 01439 #define AT91C_RTC_CALEV (0x1 << 4) // (RTC) Calendar event 01440 // -------- RTC_SCCR : (RTC Offset: 0x1c) RTC Status Clear Command Register -------- 01441 // -------- RTC_IER : (RTC Offset: 0x20) RTC Interrupt Enable Register -------- 01442 // -------- RTC_IDR : (RTC Offset: 0x24) RTC Interrupt Disable Register -------- 01443 // -------- RTC_IMR : (RTC Offset: 0x28) RTC Interrupt Mask Register -------- 01444 // -------- RTC_VER : (RTC Offset: 0x2c) RTC Valid Entry Register -------- 01445 #define AT91C_RTC_NVTIM (0x1 << 0) // (RTC) Non valid Time 01446 #define AT91C_RTC_NVCAL (0x1 << 1) // (RTC) Non valid Calendar 01447 #define AT91C_RTC_NVTIMALR (0x1 << 2) // (RTC) Non valid time Alarm 01448 #define AT91C_RTC_NVCALALR (0x1 << 3) // (RTC) Nonvalid Calendar Alarm 01449 01450 // ***************************************************************************** 01451 // SOFTWARE API DEFINITION FOR Analog to Digital Convertor 01452 // ***************************************************************************** 01453 #ifndef __ASSEMBLY__ 01454 #else 01455 #define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register 01456 #define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register 01457 #define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register 01458 #define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register 01459 #define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register 01460 #define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register 01461 #define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register 01462 #define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register 01463 #define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register 01464 #define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register 01465 #define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0 01466 #define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1 01467 #define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2 01468 #define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3 01469 #define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4 01470 #define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5 01471 #define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6 01472 #define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7 01473 #define ADC_ACR (AT91_CAST(AT91_REG *) 0x00000064) // (ADC_ACR) Analog Control Register 01474 #define ADC_EMR (AT91_CAST(AT91_REG *) 0x00000068) // (ADC_EMR) Extended Mode Register 01475 #define ADC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (ADC_ADDRSIZE) ADC ADDRSIZE REGISTER 01476 #define ADC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (ADC_IPNAME1) ADC IPNAME1 REGISTER 01477 #define ADC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (ADC_IPNAME2) ADC IPNAME2 REGISTER 01478 #define ADC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (ADC_FEATURES) ADC FEATURES REGISTER 01479 #define ADC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (ADC_VER) ADC VERSION REGISTER 01480 01481 #endif 01482 // -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 01483 #define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset 01484 #define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion 01485 // -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 01486 #define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable 01487 #define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software 01488 #define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. 01489 #define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection 01490 #define AT91C_ADC_TRGSEL_EXT (0x0 << 1) // (ADC) Selected TRGSEL = External Trigger 01491 #define AT91C_ADC_TRGSEL_TIOA0 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO0 01492 #define AT91C_ADC_TRGSEL_TIOA1 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO1 01493 #define AT91C_ADC_TRGSEL_TIOA2 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO2 01494 #define AT91C_ADC_TRGSEL_PWM0_TRIG (0x4 << 1) // (ADC) Selected TRGSEL = PWM trigger 01495 #define AT91C_ADC_TRGSEL_PWM1_TRIG (0x5 << 1) // (ADC) Selected TRGSEL = PWM Trigger 01496 #define AT91C_ADC_TRGSEL_RESERVED (0x6 << 1) // (ADC) Selected TRGSEL = Reserved 01497 #define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. 01498 #define AT91C_ADC_LOWRES_12_BIT (0x0 << 4) // (ADC) 10-bit resolution 01499 #define AT91C_ADC_LOWRES_10_BIT (0x1 << 4) // (ADC) 8-bit resolution 01500 #define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode 01501 #define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode 01502 #define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode 01503 #define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection 01504 #define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time 01505 #define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time 01506 // -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 01507 #define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 01508 #define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 01509 #define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 01510 #define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 01511 #define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 01512 #define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 01513 #define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 01514 #define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 01515 // -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 01516 // -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 01517 // -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 01518 #define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion 01519 #define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion 01520 #define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion 01521 #define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion 01522 #define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion 01523 #define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion 01524 #define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion 01525 #define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion 01526 #define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error 01527 #define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error 01528 #define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error 01529 #define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error 01530 #define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error 01531 #define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error 01532 #define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error 01533 #define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error 01534 #define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready 01535 #define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun 01536 #define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer 01537 #define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt 01538 // -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 01539 #define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted 01540 // -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 01541 // -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 01542 // -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 01543 // -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 01544 #define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data 01545 // -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 01546 // -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 01547 // -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 01548 // -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 01549 // -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 01550 // -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 01551 // -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 01552 // -------- ADC_ACR : (ADC Offset: 0x64) ADC Analog Controler Register -------- 01553 #define AT91C_ADC_GAIN (0x3 << 0) // (ADC) Input Gain 01554 #define AT91C_ADC_IBCTL (0x3 << 6) // (ADC) Bias Current Control 01555 #define AT91C_ADC_IBCTL_00 (0x0 << 6) // (ADC) typ - 20% 01556 #define AT91C_ADC_IBCTL_01 (0x1 << 6) // (ADC) typ 01557 #define AT91C_ADC_IBCTL_10 (0x2 << 6) // (ADC) typ + 20% 01558 #define AT91C_ADC_IBCTL_11 (0x3 << 6) // (ADC) typ + 40% 01559 #define AT91C_ADC_DIFF (0x1 << 16) // (ADC) Differential Mode 01560 #define AT91C_ADC_OFFSET (0x1 << 17) // (ADC) Input OFFSET 01561 // -------- ADC_EMR : (ADC Offset: 0x68) ADC Extended Mode Register -------- 01562 #define AT91C_OFFMODES (0x1 << 0) // (ADC) Off Mode if 01563 #define AT91C_OFF_MODE_STARTUP_TIME (0x1 << 16) // (ADC) Startup Time 01564 // -------- ADC_VER : (ADC Offset: 0xfc) ADC VER -------- 01565 #define AT91C_ADC_VER (0xF << 0) // (ADC) ADC VER 01566 01567 // ***************************************************************************** 01568 // SOFTWARE API DEFINITION FOR Analog-to Digital Converter 01569 // ***************************************************************************** 01570 01571 #ifndef __ASSEMBLY__ 01572 #else 01573 #define ADC12B_CR (AT91_CAST(AT91_REG *) 0x00000000) // Control Register 01574 #define ADC12B_MR (AT91_CAST(AT91_REG *) 0x00000004) // Mode Register 01575 #define ADC12B_CHER (AT91_CAST(AT91_REG *) 0x00000010) // Channel Enable Register 01576 #define ADC12B_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // Channel Disable Register 01577 #define ADC12B_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // Channel Status Register 01578 #define ADC12B_SR (AT91_CAST(AT91_REG *) 0x0000001C) // Status Register 01579 #define ADC12B_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // Last Converted Data Register 01580 #define ADC12B_IER (AT91_CAST(AT91_REG *) 0x00000024) // Interrupt Enable Register 01581 #define ADC12B_IDR (AT91_CAST(AT91_REG *) 0x00000028) // Interrupt Disable Register 01582 #define ADC12B_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // Interrupt Mask Register 01583 #define ADC12B_CDR (AT91_CAST(AT91_REG *) 0x00000030) // Channel Data Register 01584 #define ADC12B_ACR (AT91_CAST(AT91_REG *) 0x00000064) // Analog Control Register 01585 #define ADC12B_EMR (AT91_CAST(AT91_REG *) 0x00000068) // Extended Mode Register 01586 #endif 01587 // -------- ADC12B_CR : (ADC12B Offset: 0x00) Control Register -------- 01588 #define AT91C_ADC12B_CR_SWRST (0x1 << 0) // (ADC12B) Software Reset 01589 #define AT91C_ADC12B_CR_SWRST_NO_EFFECT (0x0 << 0) // (ADC12B) No effect. 01590 #define AT91C_ADC12B_CR_SWRST_RESET (0x1 << 0) // (ADC12B) Resets the ADC12B simulating a hardware reset. 01591 #define AT91C_ADC12B_CR_START (0x1 << 1) // (ADC12B) Start Conversion 01592 #define AT91C_ADC12B_CR_START_NO_EFFECT (0x0 << 1) // (ADC12B) No effect. 01593 #define AT91C_ADC12B_CR_START_BEGIN_ADC (0x1 << 1) // (ADC12B) Begins analog-to-digital conversion. 01594 // -------- ADC12B_MR : (ADC12B Offset: 0x04) Mode Register -------- 01595 #define AT91C_ADC12B_MR_TRGEN (0x1 << 0) // (ADC12B) Trigger Enable 01596 #define AT91C_ADC12B_MR_TRGEN_DIS (0x0 << 0) // (ADC12B) Hardware triggers are disabled. Starting a conversion is only possible by software. 01597 #define AT91C_ADC12B_MR_TRGEN_EN (0x1 << 0) // (ADC12B) Hardware trigger selected by TRGSEL field is enabled. 01598 #define AT91C_ADC12B_MR_TRGSEL (0x7 << 1) // (ADC12B) Trigger Selection 01599 #define AT91C_ADC12B_MR_TRGSEL_EXT_TRIG (0x0 << 1) // (ADC12B) External trigger 01600 #define AT91C_ADC12B_MR_TRGSEL_TIOA_0 (0x1 << 1) // (ADC12B) TIO Output of the Timer Counter Channel 0 01601 #define AT91C_ADC12B_MR_TRGSEL_TIOA_1 (0x2 << 1) // (ADC12B) TIO Output of the Timer Counter Channel 1 01602 #define AT91C_ADC12B_MR_TRGSEL_TIOA_2 (0x3 << 1) // (ADC12B) TIO Output of the Timer Counter Channel 2 01603 #define AT91C_ADC12B_MR_TRGSEL_TIOA_3 (0x4 << 1) // (ADC12B) PWM Event Line 0 01604 #define AT91C_ADC12B_MR_TRGSEL_TIOA_4 (0x5 << 1) // (ADC12B) PWM Event Line 1 01605 #define AT91C_ADC12B_MR_LOWRES (0x1 << 4) // (ADC12B) Resolution 01606 #define AT91C_ADC12B_MR_LOWRES_12_BIT (0x0 << 4) // (ADC12B) 12-bit resolution 01607 #define AT91C_ADC12B_MR_LOWRES_10_BIT (0x1 << 4) // (ADC12B) 10-bit resolution 01608 #define AT91C_ADC12B_MR_SLEEP (0x1 << 5) // (ADC12B) Sleep Mode 01609 #define AT91C_ADC12B_MR_SLEEP_NORMAL (0x0 << 5) // (ADC12B) Normal Mode 01610 #define AT91C_ADC12B_MR_SLEEP_SLEEP (0x1 << 5) // (ADC12B) Sleep Modes (see OFFMODES register) 01611 #define AT91C_ADC12B_MR_PRESCAL (0xff << 8) // (ADC12B) Prescaler Rate Selection 01612 #define AT91C_ADC12B_MR_STARTUP (0xff << 16) // (ADC12B) Start Up Time 01613 #define AT91C_ADC12B_MR_SHTIM (0xf << 24) // (ADC12B) Sample & Hold Time 01614 // -------- ADC12B_CHER : (ADC12B Offset: 0x10) Channel Enable Register -------- 01615 #define AT91C_ADC12B_CHER_CH0 (0x1 << 0) // (ADC12B) Channel 0 Enable 01616 #define AT91C_ADC12B_CHER_CH0_NO_EFFECT (0x0 << 0) // (ADC12B) No effect. 01617 #define AT91C_ADC12B_CHER_CH0_ENABLE (0x1 << 0) // (ADC12B) Enables the corresponding channel. 01618 #define AT91C_ADC12B_CHER_CH1 (0x1 << 1) // (ADC12B) Channel 1 Enable 01619 #define AT91C_ADC12B_CHER_CH1_NO_EFFECT (0x0 << 1) // (ADC12B) No effect. 01620 #define AT91C_ADC12B_CHER_CH1_ENABLE (0x1 << 1) // (ADC12B) Enables the corresponding channel. 01621 #define AT91C_ADC12B_CHER_CH2 (0x1 << 2) // (ADC12B) Channel 2 Enable 01622 #define AT91C_ADC12B_CHER_CH2_NO_EFFECT (0x0 << 2) // (ADC12B) No effect. 01623 #define AT91C_ADC12B_CHER_CH2_ENABLE (0x1 << 2) // (ADC12B) Enables the corresponding channel. 01624 #define AT91C_ADC12B_CHER_CH3 (0x1 << 3) // (ADC12B) Channel 3 Enable 01625 #define AT91C_ADC12B_CHER_CH3_NO_EFFECT (0x0 << 3) // (ADC12B) No effect. 01626 #define AT91C_ADC12B_CHER_CH3_ENABLE (0x1 << 3) // (ADC12B) Enables the corresponding channel. 01627 #define AT91C_ADC12B_CHER_CH4 (0x1 << 4) // (ADC12B) Channel 4 Enable 01628 #define AT91C_ADC12B_CHER_CH4_NO_EFFECT (0x0 << 4) // (ADC12B) No effect. 01629 #define AT91C_ADC12B_CHER_CH4_ENABLE (0x1 << 4) // (ADC12B) Enables the corresponding channel. 01630 #define AT91C_ADC12B_CHER_CH5 (0x1 << 5) // (ADC12B) Channel 5 Enable 01631 #define AT91C_ADC12B_CHER_CH5_NO_EFFECT (0x0 << 5) // (ADC12B) No effect. 01632 #define AT91C_ADC12B_CHER_CH5_ENABLE (0x1 << 5) // (ADC12B) Enables the corresponding channel. 01633 #define AT91C_ADC12B_CHER_CH6 (0x1 << 6) // (ADC12B) Channel 6 Enable 01634 #define AT91C_ADC12B_CHER_CH6_NO_EFFECT (0x0 << 6) // (ADC12B) No effect. 01635 #define AT91C_ADC12B_CHER_CH6_ENABLE (0x1 << 6) // (ADC12B) Enables the corresponding channel. 01636 #define AT91C_ADC12B_CHER_CH7 (0x1 << 7) // (ADC12B) Channel 7 Enable 01637 #define AT91C_ADC12B_CHER_CH7_NO_EFFECT (0x0 << 7) // (ADC12B) No effect. 01638 #define AT91C_ADC12B_CHER_CH7_ENABLE (0x1 << 7) // (ADC12B) Enables the corresponding channel. 01639 // -------- ADC12B_CHDR : (ADC12B Offset: 0x14) Channel Disable Register -------- 01640 #define AT91C_ADC12B_CHDR_CH0 (0x1 << 0) // (ADC12B) Channel 0 Disable 01641 #define AT91C_ADC12B_CHDR_CH0_NO_EFFECT (0x0 << 0) // (ADC12B) No effect. 01642 #define AT91C_ADC12B_CHDR_CH0_DISABLE (0x1 << 0) // (ADC12B) Disables the corresponding channel. 01643 #define AT91C_ADC12B_CHDR_CH1 (0x1 << 1) // (ADC12B) Channel 1 Disable 01644 #define AT91C_ADC12B_CHDR_CH1_NO_EFFECT (0x0 << 1) // (ADC12B) No effect. 01645 #define AT91C_ADC12B_CHDR_CH1_DISABLE (0x1 << 1) // (ADC12B) Disables the corresponding channel. 01646 #define AT91C_ADC12B_CHDR_CH2 (0x1 << 2) // (ADC12B) Channel 2 Disable 01647 #define AT91C_ADC12B_CHDR_CH2_NO_EFFECT (0x0 << 2) // (ADC12B) No effect. 01648 #define AT91C_ADC12B_CHDR_CH2_DISABLE (0x1 << 2) // (ADC12B) Disables the corresponding channel. 01649 #define AT91C_ADC12B_CHDR_CH3 (0x1 << 3) // (ADC12B) Channel 3 Disable 01650 #define AT91C_ADC12B_CHDR_CH3_NO_EFFECT (0x0 << 3) // (ADC12B) No effect. 01651 #define AT91C_ADC12B_CHDR_CH3_DISABLE (0x1 << 3) // (ADC12B) Disables the corresponding channel. 01652 #define AT91C_ADC12B_CHDR_CH4 (0x1 << 4) // (ADC12B) Channel 4 Disable 01653 #define AT91C_ADC12B_CHDR_CH4_NO_EFFECT (0x0 << 4) // (ADC12B) No effect. 01654 #define AT91C_ADC12B_CHDR_CH4_DISABLE (0x1 << 4) // (ADC12B) Disables the corresponding channel. 01655 #define AT91C_ADC12B_CHDR_CH5 (0x1 << 5) // (ADC12B) Channel 5 Disable 01656 #define AT91C_ADC12B_CHDR_CH5_NO_EFFECT (0x0 << 5) // (ADC12B) No effect. 01657 #define AT91C_ADC12B_CHDR_CH5_DISABLE (0x1 << 5) // (ADC12B) Disables the corresponding channel. 01658 #define AT91C_ADC12B_CHDR_CH6 (0x1 << 6) // (ADC12B) Channel 6 Disable 01659 #define AT91C_ADC12B_CHDR_CH6_NO_EFFECT (0x0 << 6) // (ADC12B) No effect. 01660 #define AT91C_ADC12B_CHDR_CH6_DISABLE (0x1 << 6) // (ADC12B) Disables the corresponding channel. 01661 #define AT91C_ADC12B_CHDR_CH7 (0x1 << 7) // (ADC12B) Channel 7 Disable 01662 #define AT91C_ADC12B_CHDR_CH7_NO_EFFECT (0x0 << 7) // (ADC12B) No effect. 01663 #define AT91C_ADC12B_CHDR_CH7_DISABLE (0x1 << 7) // (ADC12B) Disables the corresponding channel. 01664 // -------- ADC12B_CHSR : (ADC12B Offset: 0x18) Channel Status Register -------- 01665 #define AT91C_ADC12B_CHSR_CH0 (0x1 << 0) // (ADC12B) Channel 0 Status 01666 #define AT91C_ADC12B_CHSR_CH0_DISABLED (0x0 << 0) // (ADC12B) Corresponding channel is disabled. 01667 #define AT91C_ADC12B_CHSR_CH0_ENABLED (0x1 << 0) // (ADC12B) Corresponding channel is enabled. 01668 #define AT91C_ADC12B_CHSR_CH1 (0x1 << 1) // (ADC12B) Channel 1 Status 01669 #define AT91C_ADC12B_CHSR_CH1_DISABLED (0x0 << 1) // (ADC12B) Corresponding channel is disabled. 01670 #define AT91C_ADC12B_CHSR_CH1_ENABLED (0x1 << 1) // (ADC12B) Corresponding channel is enabled. 01671 #define AT91C_ADC12B_CHSR_CH2 (0x1 << 2) // (ADC12B) Channel 2 Status 01672 #define AT91C_ADC12B_CHSR_CH2_DISABLED (0x0 << 2) // (ADC12B) Corresponding channel is disabled. 01673 #define AT91C_ADC12B_CHSR_CH2_ENABLED (0x1 << 2) // (ADC12B) Corresponding channel is enabled. 01674 #define AT91C_ADC12B_CHSR_CH3 (0x1 << 3) // (ADC12B) Channel 3 Status 01675 #define AT91C_ADC12B_CHSR_CH3_DISABLED (0x0 << 3) // (ADC12B) Corresponding channel is disabled. 01676 #define AT91C_ADC12B_CHSR_CH3_ENABLED (0x1 << 3) // (ADC12B) Corresponding channel is enabled. 01677 #define AT91C_ADC12B_CHSR_CH4 (0x1 << 4) // (ADC12B) Channel 4 Status 01678 #define AT91C_ADC12B_CHSR_CH4_DISABLED (0x0 << 4) // (ADC12B) Corresponding channel is disabled. 01679 #define AT91C_ADC12B_CHSR_CH4_ENABLED (0x1 << 4) // (ADC12B) Corresponding channel is enabled. 01680 #define AT91C_ADC12B_CHSR_CH5 (0x1 << 5) // (ADC12B) Channel 5 Status 01681 #define AT91C_ADC12B_CHSR_CH5_DISABLED (0x0 << 5) // (ADC12B) Corresponding channel is disabled. 01682 #define AT91C_ADC12B_CHSR_CH5_ENABLED (0x1 << 5) // (ADC12B) Corresponding channel is enabled. 01683 #define AT91C_ADC12B_CHSR_CH6 (0x1 << 6) // (ADC12B) Channel 6 Status 01684 #define AT91C_ADC12B_CHSR_CH6_DISABLED (0x0 << 6) // (ADC12B) Corresponding channel is disabled. 01685 #define AT91C_ADC12B_CHSR_CH6_ENABLED (0x1 << 6) // (ADC12B) Corresponding channel is enabled. 01686 #define AT91C_ADC12B_CHSR_CH7 (0x1 << 7) // (ADC12B) Channel 7 Status 01687 #define AT91C_ADC12B_CHSR_CH7_DISABLED (0x0 << 7) // (ADC12B) Corresponding channel is disabled. 01688 #define AT91C_ADC12B_CHSR_CH7_ENABLED (0x1 << 7) // (ADC12B) Corresponding channel is enabled. 01689 // -------- ADC12B_SR : (ADC12B Offset: 0x1C) Status Register -------- 01690 #define AT91C_ADC12B_SR_EOC0 (0x1 << 0) // (ADC12B) End of Conversion 0 01691 #define AT91C_ADC12B_SR_EOC0_DISABLE (0x0 << 0) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01692 #define AT91C_ADC12B_SR_EOC0_ENABLE (0x1 << 0) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01693 #define AT91C_ADC12B_SR_EOC1 (0x1 << 1) // (ADC12B) End of Conversion 1 01694 #define AT91C_ADC12B_SR_EOC1_DISABLE (0x0 << 1) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01695 #define AT91C_ADC12B_SR_EOC1_ENABLE (0x1 << 1) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01696 #define AT91C_ADC12B_SR_EOC2 (0x1 << 2) // (ADC12B) End of Conversion 2 01697 #define AT91C_ADC12B_SR_EOC2_DISABLE (0x0 << 2) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01698 #define AT91C_ADC12B_SR_EOC2_ENABLE (0x1 << 2) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01699 #define AT91C_ADC12B_SR_EOC3 (0x1 << 3) // (ADC12B) End of Conversion 3 01700 #define AT91C_ADC12B_SR_EOC3_DISABLE (0x0 << 3) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01701 #define AT91C_ADC12B_SR_EOC3_ENABLE (0x1 << 3) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01702 #define AT91C_ADC12B_SR_EOC4 (0x1 << 4) // (ADC12B) End of Conversion 4 01703 #define AT91C_ADC12B_SR_EOC4_DISABLE (0x0 << 4) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01704 #define AT91C_ADC12B_SR_EOC4_ENABLE (0x1 << 4) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01705 #define AT91C_ADC12B_SR_EOC5 (0x1 << 5) // (ADC12B) End of Conversion 5 01706 #define AT91C_ADC12B_SR_EOC5_DISABLE (0x0 << 5) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01707 #define AT91C_ADC12B_SR_EOC5_ENABLE (0x1 << 5) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01708 #define AT91C_ADC12B_SR_EOC6 (0x1 << 6) // (ADC12B) End of Conversion 6 01709 #define AT91C_ADC12B_SR_EOC6_DISABLE (0x0 << 6) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01710 #define AT91C_ADC12B_SR_EOC6_ENABLE (0x1 << 6) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01711 #define AT91C_ADC12B_SR_EOC7 (0x1 << 7) // (ADC12B) End of Conversion 7 01712 #define AT91C_ADC12B_SR_EOC7_DISABLE (0x0 << 7) // (ADC12B) Corresponding analog channel is disabled, or the conversion is not finished. 01713 #define AT91C_ADC12B_SR_EOC7_ENABLE (0x1 << 7) // (ADC12B) Corresponding analog channel is enabled and conversion is complete. 01714 #define AT91C_ADC12B_SR_OVRE0 (0x1 << 8) // (ADC12B) Overrun Error 0 01715 #define AT91C_ADC12B_SR_OVRE0_NO_ERROR (0x0 << 8) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01716 #define AT91C_ADC12B_SR_OVRE0_ERROR (0x1 << 8) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01717 #define AT91C_ADC12B_SR_OVRE1 (0x1 << 9) // (ADC12B) Overrun Error 1 01718 #define AT91C_ADC12B_SR_OVRE1_NO_ERROR (0x0 << 9) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01719 #define AT91C_ADC12B_SR_OVRE1_ERROR (0x1 << 9) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01720 #define AT91C_ADC12B_SR_OVRE2 (0x1 << 10) // (ADC12B) Overrun Error 2 01721 #define AT91C_ADC12B_SR_OVRE2_NO_ERROR (0x0 << 10) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01722 #define AT91C_ADC12B_SR_OVRE2_ERROR (0x1 << 10) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01723 #define AT91C_ADC12B_SR_OVRE3 (0x1 << 11) // (ADC12B) Overrun Error 3 01724 #define AT91C_ADC12B_SR_OVRE3_NO_ERROR (0x0 << 11) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01725 #define AT91C_ADC12B_SR_OVRE3_ERROR (0x1 << 11) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01726 #define AT91C_ADC12B_SR_OVRE4 (0x1 << 12) // (ADC12B) Overrun Error 4 01727 #define AT91C_ADC12B_SR_OVRE4_NO_ERROR (0x0 << 12) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01728 #define AT91C_ADC12B_SR_OVRE4_ERROR (0x1 << 12) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01729 #define AT91C_ADC12B_SR_OVRE5 (0x1 << 13) // (ADC12B) Overrun Error 5 01730 #define AT91C_ADC12B_SR_OVRE5_NO_ERROR (0x0 << 13) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01731 #define AT91C_ADC12B_SR_OVRE5_ERROR (0x1 << 13) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01732 #define AT91C_ADC12B_SR_OVRE6 (0x1 << 14) // (ADC12B) Overrun Error 6 01733 #define AT91C_ADC12B_SR_OVRE6_NO_ERROR (0x0 << 14) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01734 #define AT91C_ADC12B_SR_OVRE6_ERROR (0x1 << 14) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01735 #define AT91C_ADC12B_SR_OVRE7 (0x1 << 15) // (ADC12B) Overrun Error 7 01736 #define AT91C_ADC12B_SR_OVRE7_NO_ERROR (0x0 << 15) // (ADC12B) No overrun error on the corresponding channel since the last read of ADC12B_SR. 01737 #define AT91C_ADC12B_SR_OVRE7_ERROR (0x1 << 15) // (ADC12B) There has been an overrun error on the corresponding channel since the last read of ADC12B_SR. 01738 #define AT91C_ADC12B_SR_DRDY (0x1 << 16) // (ADC12B) Data Ready 01739 #define AT91C_ADC12B_SR_DRDY_NO_CONV (0x0 << 16) // (ADC12B) No data has been converted since the last read of ADC12B_LCDR. 01740 #define AT91C_ADC12B_SR_DRDY_CONV (0x1 << 16) // (ADC12B) At least one data has been converted and is available in ADC12B_LCDR. 01741 #define AT91C_ADC12B_SR_GOVRE (0x1 << 17) // (ADC12B) General Overrun Error 01742 #define AT91C_ADC12B_SR_GOVRE_NO_ERROR (0x0 << 17) // (ADC12B) No General Overrun Error occurred since the last read of ADC12B_SR. 01743 #define AT91C_ADC12B_SR_GOVRE_ERROR (0x1 << 17) // (ADC12B) At least one General Overrun Error has occurred since the last read of ADC12B_SR. 01744 #define AT91C_ADC12B_SR_ENDRX (0x1 << 18) // (ADC12B) End of RX Buffer 01745 #define AT91C_ADC12B_SR_ENDRX_NOT_REACH (0x0 << 18) // (ADC12B) The Receive Counter Register has not reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR. 01746 #define AT91C_ADC12B_SR_ENDRX_REACH_0 (0x1 << 18) // (ADC12B) The Receive Counter Register has reached 0 since the last write in ADC12B_RCR or ADC12B_RNCR. 01747 #define AT91C_ADC12B_SR_RXBUFF (0x1 << 19) // (ADC12B) RX Buffer Full 01748 #define AT91C_ADC12B_SR_RXBUFF_NO_ZERO (0x0 << 19) // (ADC12B) ADC12B_RCR or ADC12B_RNCR have a value other than 0. 01749 #define AT91C_ADC12B_SR_RXBUFF_ZERO (0x1 << 19) // (ADC12B) Both ADC12B_RCR and ADC12B_RNCR have a value of 0. 01750 // -------- ADC12B_LCDR : (ADC12B Offset: 0x20) Last Converted Data Register -------- 01751 #define AT91C_ADC12B_LCDR_LDATA (0xfff << 0) // (ADC12B) Last Data Converted 01752 // -------- ADC12B_IER : (ADC12B Offset: 0x24) Interrupt Enable Register -------- 01753 #define AT91C_ADC12B_IER_EOC0 (0x1 << 0) // (ADC12B) End of Conversion Interrupt Enable 0 01754 #define AT91C_ADC12B_IER_EOC0_NO_EFFECT (0x0 << 0) // (ADC12B) No effect. 01755 #define AT91C_ADC12B_IER_EOC0_ENABLE (0x1 << 0) // (ADC12B) Enables the corresponding interrupt. 01756 #define AT91C_ADC12B_IER_EOC1 (0x1 << 1) // (ADC12B) End of Conversion Interrupt Enable 1 01757 #define AT91C_ADC12B_IER_EOC1_NO_EFFECT (0x0 << 1) // (ADC12B) No effect. 01758 #define AT91C_ADC12B_IER_EOC1_ENABLE (0x1 << 1) // (ADC12B) Enables the corresponding interrupt. 01759 #define AT91C_ADC12B_IER_EOC2 (0x1 << 2) // (ADC12B) End of Conversion Interrupt Enable 2 01760 #define AT91C_ADC12B_IER_EOC2_NO_EFFECT (0x0 << 2) // (ADC12B) No effect. 01761 #define AT91C_ADC12B_IER_EOC2_ENABLE (0x1 << 2) // (ADC12B) Enables the corresponding interrupt. 01762 #define AT91C_ADC12B_IER_EOC3 (0x1 << 3) // (ADC12B) End of Conversion Interrupt Enable 3 01763 #define AT91C_ADC12B_IER_EOC3_NO_EFFECT (0x0 << 3) // (ADC12B) No effect. 01764 #define AT91C_ADC12B_IER_EOC3_ENABLE (0x1 << 3) // (ADC12B) Enables the corresponding interrupt. 01765 #define AT91C_ADC12B_IER_EOC4 (0x1 << 4) // (ADC12B) End of Conversion Interrupt Enable 4 01766 #define AT91C_ADC12B_IER_EOC4_NO_EFFECT (0x0 << 4) // (ADC12B) No effect. 01767 #define AT91C_ADC12B_IER_EOC4_ENABLE (0x1 << 4) // (ADC12B) Enables the corresponding interrupt. 01768 #define AT91C_ADC12B_IER_EOC5 (0x1 << 5) // (ADC12B) End of Conversion Interrupt Enable 5 01769 #define AT91C_ADC12B_IER_EOC5_NO_EFFECT (0x0 << 5) // (ADC12B) No effect. 01770 #define AT91C_ADC12B_IER_EOC5_ENABLE (0x1 << 5) // (ADC12B) Enables the corresponding interrupt. 01771 #define AT91C_ADC12B_IER_EOC6 (0x1 << 6) // (ADC12B) End of Conversion Interrupt Enable 6 01772 #define AT91C_ADC12B_IER_EOC6_NO_EFFECT (0x0 << 6) // (ADC12B) No effect. 01773 #define AT91C_ADC12B_IER_EOC6_ENABLE (0x1 << 6) // (ADC12B) Enables the corresponding interrupt. 01774 #define AT91C_ADC12B_IER_EOC7 (0x1 << 7) // (ADC12B) End of Conversion Interrupt Enable 7 01775 #define AT91C_ADC12B_IER_EOC7_NO_EFFECT (0x0 << 7) // (ADC12B) No effect. 01776 #define AT91C_ADC12B_IER_EOC7_ENABLE (0x1 << 7) // (ADC12B) Enables the corresponding interrupt. 01777 #define AT91C_ADC12B_IER_OVRE0 (0x1 << 8) // (ADC12B) Overrun Error Interrupt Enable 0 01778 #define AT91C_ADC12B_IER_OVRE0_NO_EFFECT (0x0 << 8) // (ADC12B) No effect. 01779 #define AT91C_ADC12B_IER_OVRE0_ENABLE (0x1 << 8) // (ADC12B) Enables the corresponding interrupt. 01780 #define AT91C_ADC12B_IER_OVRE1 (0x1 << 9) // (ADC12B) Overrun Error Interrupt Enable 1 01781 #define AT91C_ADC12B_IER_OVRE1_NO_EFFECT (0x0 << 9) // (ADC12B) No effect. 01782 #define AT91C_ADC12B_IER_OVRE1_ENABLE (0x1 << 9) // (ADC12B) Enables the corresponding interrupt. 01783 #define AT91C_ADC12B_IER_OVRE2 (0x1 << 10) // (ADC12B) Overrun Error Interrupt Enable 2 01784 #define AT91C_ADC12B_IER_OVRE2_NO_EFFECT (0x0 << 10) // (ADC12B) No effect. 01785 #define AT91C_ADC12B_IER_OVRE2_ENABLE (0x1 << 10) // (ADC12B) Enables the corresponding interrupt. 01786 #define AT91C_ADC12B_IER_OVRE3 (0x1 << 11) // (ADC12B) Overrun Error Interrupt Enable 3 01787 #define AT91C_ADC12B_IER_OVRE3_NO_EFFECT (0x0 << 11) // (ADC12B) No effect. 01788 #define AT91C_ADC12B_IER_OVRE3_ENABLE (0x1 << 11) // (ADC12B) Enables the corresponding interrupt. 01789 #define AT91C_ADC12B_IER_OVRE4 (0x1 << 12) // (ADC12B) Overrun Error Interrupt Enable 4 01790 #define AT91C_ADC12B_IER_OVRE4_NO_EFFECT (0x0 << 12) // (ADC12B) No effect. 01791 #define AT91C_ADC12B_IER_OVRE4_ENABLE (0x1 << 12) // (ADC12B) Enables the corresponding interrupt. 01792 #define AT91C_ADC12B_IER_OVRE5 (0x1 << 13) // (ADC12B) Overrun Error Interrupt Enable 5 01793 #define AT91C_ADC12B_IER_OVRE5_NO_EFFECT (0x0 << 13) // (ADC12B) No effect. 01794 #define AT91C_ADC12B_IER_OVRE5_ENABLE (0x1 << 13) // (ADC12B) Enables the corresponding interrupt. 01795 #define AT91C_ADC12B_IER_OVRE6 (0x1 << 14) // (ADC12B) Overrun Error Interrupt Enable 6 01796 #define AT91C_ADC12B_IER_OVRE6_NO_EFFECT (0x0 << 14) // (ADC12B) No effect. 01797 #define AT91C_ADC12B_IER_OVRE6_ENABLE (0x1 << 14) // (ADC12B) Enables the corresponding interrupt. 01798 #define AT91C_ADC12B_IER_OVRE7 (0x1 << 15) // (ADC12B) Overrun Error Interrupt Enable 7 01799 #define AT91C_ADC12B_IER_OVRE7_NO_EFFECT (0x0 << 15) // (ADC12B) No effect. 01800 #define AT91C_ADC12B_IER_OVRE7_ENABLE (0x1 << 15) // (ADC12B) Enables the corresponding interrupt. 01801 #define AT91C_ADC12B_IER_DRDY (0x1 << 16) // (ADC12B) Data Ready Interrupt Enable 01802 #define AT91C_ADC12B_IER_DRDY_NO_EFFECT (0x0 << 16) // (ADC12B) No effect. 01803 #define AT91C_ADC12B_IER_DRDY_ENABLE (0x1 << 16) // (ADC12B) Enables the corresponding interrupt. 01804 #define AT91C_ADC12B_IER_GOVRE (0x1 << 17) // (ADC12B) General Overrun Error Interrupt Enable 01805 #define AT91C_ADC12B_IER_GOVRE_NO_EFFECT (0x0 << 17) // (ADC12B) No effect. 01806 #define AT91C_ADC12B_IER_GOVRE_ENABLE (0x1 << 17) // (ADC12B) Enables the corresponding interrupt. 01807 #define AT91C_ADC12B_IER_ENDRX (0x1 << 18) // (ADC12B) End of Receive Buffer Interrupt Enable 01808 #define AT91C_ADC12B_IER_ENDRX_NO_EFFECT (0x0 << 18) // (ADC12B) No effect. 01809 #define AT91C_ADC12B_IER_ENDRX_ENABLE (0x1 << 18) // (ADC12B) Enables the corresponding interrupt. 01810 #define AT91C_ADC12B_IER_RXBUFF (0x1 << 19) // (ADC12B) Receive Buffer Full Interrupt Enable 01811 #define AT91C_ADC12B_IER_RXBUFF_NO_EFFECT (0x0 << 19) // (ADC12B) No effect. 01812 #define AT91C_ADC12B_IER_RXBUFF_ENABLE (0x1 << 19) // (ADC12B) Enables the corresponding interrupt. 01813 // -------- ADC12B_IDR : (ADC12B Offset: 0x28) Interrupt Disable Register -------- 01814 #define AT91C_ADC12B_IDR_EOC0 (0x1 << 0) // (ADC12B) End of Conversion Interrupt Disable 0 01815 #define AT91C_ADC12B_IDR_EOC0_NO_EFFECT (0x0 << 0) // (ADC12B) No effect. 01816 #define AT91C_ADC12B_IDR_EOC0_DISABLE (0x1 << 0) // (ADC12B) Disables the corresponding interrupt. 01817 #define AT91C_ADC12B_IDR_EOC1 (0x1 << 1) // (ADC12B) End of Conversion Interrupt Disable 1 01818 #define AT91C_ADC12B_IDR_EOC1_NO_EFFECT (0x0 << 1) // (ADC12B) No effect. 01819 #define AT91C_ADC12B_IDR_EOC1_DISABLE (0x1 << 1) // (ADC12B) Disables the corresponding interrupt. 01820 #define AT91C_ADC12B_IDR_EOC2 (0x1 << 2) // (ADC12B) End of Conversion Interrupt Disable 2 01821 #define AT91C_ADC12B_IDR_EOC2_NO_EFFECT (0x0 << 2) // (ADC12B) No effect. 01822 #define AT91C_ADC12B_IDR_EOC2_DISABLE (0x1 << 2) // (ADC12B) Disables the corresponding interrupt. 01823 #define AT91C_ADC12B_IDR_EOC3 (0x1 << 3) // (ADC12B) End of Conversion Interrupt Disable 3 01824 #define AT91C_ADC12B_IDR_EOC3_NO_EFFECT (0x0 << 3) // (ADC12B) No effect. 01825 #define AT91C_ADC12B_IDR_EOC3_DISABLE (0x1 << 3) // (ADC12B) Disables the corresponding interrupt. 01826 #define AT91C_ADC12B_IDR_EOC4 (0x1 << 4) // (ADC12B) End of Conversion Interrupt Disable 4 01827 #define AT91C_ADC12B_IDR_EOC4_NO_EFFECT (0x0 << 4) // (ADC12B) No effect. 01828 #define AT91C_ADC12B_IDR_EOC4_DISABLE (0x1 << 4) // (ADC12B) Disables the corresponding interrupt. 01829 #define AT91C_ADC12B_IDR_EOC5 (0x1 << 5) // (ADC12B) End of Conversion Interrupt Disable 5 01830 #define AT91C_ADC12B_IDR_EOC5_NO_EFFECT (0x0 << 5) // (ADC12B) No effect. 01831 #define AT91C_ADC12B_IDR_EOC5_DISABLE (0x1 << 5) // (ADC12B) Disables the corresponding interrupt. 01832 #define AT91C_ADC12B_IDR_EOC6 (0x1 << 6) // (ADC12B) End of Conversion Interrupt Disable 6 01833 #define AT91C_ADC12B_IDR_EOC6_NO_EFFECT (0x0 << 6) // (ADC12B) No effect. 01834 #define AT91C_ADC12B_IDR_EOC6_DISABLE (0x1 << 6) // (ADC12B) Disables the corresponding interrupt. 01835 #define AT91C_ADC12B_IDR_EOC7 (0x1 << 7) // (ADC12B) End of Conversion Interrupt Disable 7 01836 #define AT91C_ADC12B_IDR_EOC7_NO_EFFECT (0x0 << 7) // (ADC12B) No effect. 01837 #define AT91C_ADC12B_IDR_EOC7_DISABLE (0x1 << 7) // (ADC12B) Disables the corresponding interrupt. 01838 #define AT91C_ADC12B_IDR_OVRE0 (0x1 << 8) // (ADC12B) Overrun Error Interrupt Disable 0 01839 #define AT91C_ADC12B_IDR_OVRE0_NO_EFFECT (0x0 << 8) // (ADC12B) No effect. 01840 #define AT91C_ADC12B_IDR_OVRE0_DISABLE (0x1 << 8) // (ADC12B) Disables the corresponding interrupt. 01841 #define AT91C_ADC12B_IDR_OVRE1 (0x1 << 9) // (ADC12B) Overrun Error Interrupt Disable 1 01842 #define AT91C_ADC12B_IDR_OVRE1_NO_EFFECT (0x0 << 9) // (ADC12B) No effect. 01843 #define AT91C_ADC12B_IDR_OVRE1_DISABLE (0x1 << 9) // (ADC12B) Disables the corresponding interrupt. 01844 #define AT91C_ADC12B_IDR_OVRE2 (0x1 << 10) // (ADC12B) Overrun Error Interrupt Disable 2 01845 #define AT91C_ADC12B_IDR_OVRE2_NO_EFFECT (0x0 << 10) // (ADC12B) No effect. 01846 #define AT91C_ADC12B_IDR_OVRE2_DISABLE (0x1 << 10) // (ADC12B) Disables the corresponding interrupt. 01847 #define AT91C_ADC12B_IDR_OVRE3 (0x1 << 11) // (ADC12B) Overrun Error Interrupt Disable 3 01848 #define AT91C_ADC12B_IDR_OVRE3_NO_EFFECT (0x0 << 11) // (ADC12B) No effect. 01849 #define AT91C_ADC12B_IDR_OVRE3_DISABLE (0x1 << 11) // (ADC12B) Disables the corresponding interrupt. 01850 #define AT91C_ADC12B_IDR_OVRE4 (0x1 << 12) // (ADC12B) Overrun Error Interrupt Disable 4 01851 #define AT91C_ADC12B_IDR_OVRE4_NO_EFFECT (0x0 << 12) // (ADC12B) No effect. 01852 #define AT91C_ADC12B_IDR_OVRE4_DISABLE (0x1 << 12) // (ADC12B) Disables the corresponding interrupt. 01853 #define AT91C_ADC12B_IDR_OVRE5 (0x1 << 13) // (ADC12B) Overrun Error Interrupt Disable 5 01854 #define AT91C_ADC12B_IDR_OVRE5_NO_EFFECT (0x0 << 13) // (ADC12B) No effect. 01855 #define AT91C_ADC12B_IDR_OVRE5_DISABLE (0x1 << 13) // (ADC12B) Disables the corresponding interrupt. 01856 #define AT91C_ADC12B_IDR_OVRE6 (0x1 << 14) // (ADC12B) Overrun Error Interrupt Disable 6 01857 #define AT91C_ADC12B_IDR_OVRE6_NO_EFFECT (0x0 << 14) // (ADC12B) No effect. 01858 #define AT91C_ADC12B_IDR_OVRE6_DISABLE (0x1 << 14) // (ADC12B) Disables the corresponding interrupt. 01859 #define AT91C_ADC12B_IDR_OVRE7 (0x1 << 15) // (ADC12B) Overrun Error Interrupt Disable 7 01860 #define AT91C_ADC12B_IDR_OVRE7_NO_EFFECT (0x0 << 15) // (ADC12B) No effect. 01861 #define AT91C_ADC12B_IDR_OVRE7_DISABLE (0x1 << 15) // (ADC12B) Disables the corresponding interrupt. 01862 #define AT91C_ADC12B_IDR_DRDY (0x1 << 16) // (ADC12B) Data Ready Interrupt Disable 01863 #define AT91C_ADC12B_IDR_DRDY_NO_EFFECT (0x0 << 16) // (ADC12B) No effect. 01864 #define AT91C_ADC12B_IDR_DRDY_DISABLE (0x1 << 16) // (ADC12B) Disables the corresponding interrupt. 01865 #define AT91C_ADC12B_IDR_GOVRE (0x1 << 17) // (ADC12B) General Overrun Error Interrupt Disable 01866 #define AT91C_ADC12B_IDR_GOVRE_NO_EFFECT (0x0 << 17) // (ADC12B) No effect. 01867 #define AT91C_ADC12B_IDR_GOVRE_DISABLE (0x1 << 17) // (ADC12B) Disables the corresponding interrupt. 01868 #define AT91C_ADC12B_IDR_ENDRX (0x1 << 18) // (ADC12B) End of Receive Buffer Interrupt Disable 01869 #define AT91C_ADC12B_IDR_ENDRX_NO_EFFECT (0x0 << 18) // (ADC12B) No effect. 01870 #define AT91C_ADC12B_IDR_ENDRX_DISABLE (0x1 << 18) // (ADC12B) Disables the corresponding interrupt. 01871 #define AT91C_ADC12B_IDR_RXBUFF (0x1 << 19) // (ADC12B) Receive Buffer Full Interrupt Disable 01872 #define AT91C_ADC12B_IDR_RXBUFF_NO_EFFECT (0x0 << 19) // (ADC12B) No effect. 01873 #define AT91C_ADC12B_IDR_RXBUFF_DISABLE (0x1 << 19) // (ADC12B) Disables the corresponding interrupt. 01874 // -------- ADC12B_IMR : (ADC12B Offset: 0x2C) Interrupt Mask Register -------- 01875 #define AT91C_ADC12B_IMR_EOC0 (0x1 << 0) // (ADC12B) End of Conversion Interrupt Mask 0 01876 #define AT91C_ADC12B_IMR_EOC0_DIS (0x0 << 0) // (ADC12B) The corresponding interrupt is disabled. 01877 #define AT91C_ADC12B_IMR_EOC0_EN (0x1 << 0) // (ADC12B) The corresponding interrupt is enabled. 01878 #define AT91C_ADC12B_IMR_EOC1 (0x1 << 1) // (ADC12B) End of Conversion Interrupt Mask 1 01879 #define AT91C_ADC12B_IMR_EOC1_DIS (0x0 << 1) // (ADC12B) The corresponding interrupt is disabled. 01880 #define AT91C_ADC12B_IMR_EOC1_EN (0x1 << 1) // (ADC12B) The corresponding interrupt is enabled. 01881 #define AT91C_ADC12B_IMR_EOC2 (0x1 << 2) // (ADC12B) End of Conversion Interrupt Mask 2 01882 #define AT91C_ADC12B_IMR_EOC2_DIS (0x0 << 2) // (ADC12B) The corresponding interrupt is disabled. 01883 #define AT91C_ADC12B_IMR_EOC2_EN (0x1 << 2) // (ADC12B) The corresponding interrupt is enabled. 01884 #define AT91C_ADC12B_IMR_EOC3 (0x1 << 3) // (ADC12B) End of Conversion Interrupt Mask 3 01885 #define AT91C_ADC12B_IMR_EOC3_DIS (0x0 << 3) // (ADC12B) The corresponding interrupt is disabled. 01886 #define AT91C_ADC12B_IMR_EOC3_EN (0x1 << 3) // (ADC12B) The corresponding interrupt is enabled. 01887 #define AT91C_ADC12B_IMR_EOC4 (0x1 << 4) // (ADC12B) End of Conversion Interrupt Mask 4 01888 #define AT91C_ADC12B_IMR_EOC4_DIS (0x0 << 4) // (ADC12B) The corresponding interrupt is disabled. 01889 #define AT91C_ADC12B_IMR_EOC4_EN (0x1 << 4) // (ADC12B) The corresponding interrupt is enabled. 01890 #define AT91C_ADC12B_IMR_EOC5 (0x1 << 5) // (ADC12B) End of Conversion Interrupt Mask 5 01891 #define AT91C_ADC12B_IMR_EOC5_DIS (0x0 << 5) // (ADC12B) The corresponding interrupt is disabled. 01892 #define AT91C_ADC12B_IMR_EOC5_EN (0x1 << 5) // (ADC12B) The corresponding interrupt is enabled. 01893 #define AT91C_ADC12B_IMR_EOC6 (0x1 << 6) // (ADC12B) End of Conversion Interrupt Mask 6 01894 #define AT91C_ADC12B_IMR_EOC6_DIS (0x0 << 6) // (ADC12B) The corresponding interrupt is disabled. 01895 #define AT91C_ADC12B_IMR_EOC6_EN (0x1 << 6) // (ADC12B) The corresponding interrupt is enabled. 01896 #define AT91C_ADC12B_IMR_EOC7 (0x1 << 7) // (ADC12B) End of Conversion Interrupt Mask 7 01897 #define AT91C_ADC12B_IMR_EOC7_DIS (0x0 << 7) // (ADC12B) The corresponding interrupt is disabled. 01898 #define AT91C_ADC12B_IMR_EOC7_EN (0x1 << 7) // (ADC12B) The corresponding interrupt is enabled. 01899 #define AT91C_ADC12B_IMR_OVRE0 (0x1 << 8) // (ADC12B) Overrun Error Interrupt Mask 0 01900 #define AT91C_ADC12B_IMR_OVRE0_DIS (0x0 << 8) // (ADC12B) The corresponding interrupt is disabled. 01901 #define AT91C_ADC12B_IMR_OVRE0_EN (0x1 << 8) // (ADC12B) The corresponding interrupt is enabled. 01902 #define AT91C_ADC12B_IMR_OVRE1 (0x1 << 9) // (ADC12B) Overrun Error Interrupt Mask 1 01903 #define AT91C_ADC12B_IMR_OVRE1_DIS (0x0 << 9) // (ADC12B) The corresponding interrupt is disabled. 01904 #define AT91C_ADC12B_IMR_OVRE1_EN (0x1 << 9) // (ADC12B) The corresponding interrupt is enabled. 01905 #define AT91C_ADC12B_IMR_OVRE2 (0x1 << 10) // (ADC12B) Overrun Error Interrupt Mask 2 01906 #define AT91C_ADC12B_IMR_OVRE2_DIS (0x0 << 10) // (ADC12B) The corresponding interrupt is disabled. 01907 #define AT91C_ADC12B_IMR_OVRE2_EN (0x1 << 10) // (ADC12B) The corresponding interrupt is enabled. 01908 #define AT91C_ADC12B_IMR_OVRE3 (0x1 << 11) // (ADC12B) Overrun Error Interrupt Mask 3 01909 #define AT91C_ADC12B_IMR_OVRE3_DIS (0x0 << 11) // (ADC12B) The corresponding interrupt is disabled. 01910 #define AT91C_ADC12B_IMR_OVRE3_EN (0x1 << 11) // (ADC12B) The corresponding interrupt is enabled. 01911 #define AT91C_ADC12B_IMR_OVRE4 (0x1 << 12) // (ADC12B) Overrun Error Interrupt Mask 4 01912 #define AT91C_ADC12B_IMR_OVRE4_DIS (0x0 << 12) // (ADC12B) The corresponding interrupt is disabled. 01913 #define AT91C_ADC12B_IMR_OVRE4_EN (0x1 << 12) // (ADC12B) The corresponding interrupt is enabled. 01914 #define AT91C_ADC12B_IMR_OVRE5 (0x1 << 13) // (ADC12B) Overrun Error Interrupt Mask 5 01915 #define AT91C_ADC12B_IMR_OVRE5_DIS (0x0 << 13) // (ADC12B) The corresponding interrupt is disabled. 01916 #define AT91C_ADC12B_IMR_OVRE5_EN (0x1 << 13) // (ADC12B) The corresponding interrupt is enabled. 01917 #define AT91C_ADC12B_IMR_OVRE6 (0x1 << 14) // (ADC12B) Overrun Error Interrupt Mask 6 01918 #define AT91C_ADC12B_IMR_OVRE6_DIS (0x0 << 14) // (ADC12B) The corresponding interrupt is disabled. 01919 #define AT91C_ADC12B_IMR_OVRE6_EN (0x1 << 14) // (ADC12B) The corresponding interrupt is enabled. 01920 #define AT91C_ADC12B_IMR_OVRE7 (0x1 << 15) // (ADC12B) Overrun Error Interrupt Mask 7 01921 #define AT91C_ADC12B_IMR_OVRE7_DIS (0x0 << 15) // (ADC12B) The corresponding interrupt is disabled. 01922 #define AT91C_ADC12B_IMR_OVRE7_EN (0x1 << 15) // (ADC12B) The corresponding interrupt is enabled. 01923 #define AT91C_ADC12B_IMR_DRDY (0x1 << 16) // (ADC12B) Data Ready Interrupt Mask 01924 #define AT91C_ADC12B_IMR_DRDY_DIS (0x0 << 16) // (ADC12B) The corresponding interrupt is disabled. 01925 #define AT91C_ADC12B_IMR_DRDY_EN (0x1 << 16) // (ADC12B) The corresponding interrupt is enabled. 01926 #define AT91C_ADC12B_IMR_GOVRE (0x1 << 17) // (ADC12B) General Overrun Error Interrupt Mask 01927 #define AT91C_ADC12B_IMR_GOVRE_DIS (0x0 << 17) // (ADC12B) The corresponding interrupt is disabled. 01928 #define AT91C_ADC12B_IMR_GOVRE_EN (0x1 << 17) // (ADC12B) The corresponding interrupt is enabled. 01929 #define AT91C_ADC12B_IMR_ENDRX (0x1 << 18) // (ADC12B) End of Receive Buffer Interrupt Mask 01930 #define AT91C_ADC12B_IMR_ENDRX_DIS (0x0 << 18) // (ADC12B) The corresponding interrupt is disabled. 01931 #define AT91C_ADC12B_IMR_ENDRX_EN (0x1 << 18) // (ADC12B) The corresponding interrupt is enabled. 01932 #define AT91C_ADC12B_IMR_RXBUFF (0x1 << 19) // (ADC12B) Receive Buffer Full Interrupt Mask 01933 #define AT91C_ADC12B_IMR_RXBUFF_DIS (0x0 << 19) // (ADC12B) The corresponding interrupt is disabled. 01934 #define AT91C_ADC12B_IMR_RXBUFF_EN (0x1 << 19) // (ADC12B) The corresponding interrupt is enabled. 01935 // -------- ADC12B_CDR[8] : (ADC12B Offset: 0x30) Channel Data Register -------- 01936 #define AT91C_ADC12B_CDR_DATA (0xfff << 0) // (ADC12B) Converted Data 01937 // -------- ADC12B_ACR : (ADC12B Offset: 0x64) Analog Control Register -------- 01938 #define AT91C_ADC12B_ACR_GAIN (0x3 << 0) // (ADC12B) Input Gain 01939 #define AT91C_ADC12B_ACR_IBCTL (0x3 << 6) // (ADC12B) Bias Current Control 01940 #define AT91C_ADC12B_ACR_IBCTL_MIN20 (0x0 << 6) // (ADC12B) typ - 20% 01941 #define AT91C_ADC12B_ACR_IBCTL_TYP (0x1 << 6) // (ADC12B) typ 01942 #define AT91C_ADC12B_ACR_IBCTL_PLUS20 (0x2 << 6) // (ADC12B) typ + 20% 01943 #define AT91C_ADC12B_ACR_IBCTL_PLUS40 (0x3 << 6) // (ADC12B) typ + 40% 01944 #define AT91C_ADC12B_ACR_DIFF (0x1 << 16) // (ADC12B) Differential Mode 01945 #define AT91C_ADC12B_ACR_DIFF_SINGLE (0x0 << 16) // (ADC12B) Single Ended Mode 01946 #define AT91C_ADC12B_ACR_DIFF_FULLY (0x1 << 16) // (ADC12B) Fully Differential Mode 01947 #define AT91C_ADC12B_ACR_OFFSET (0x1 << 17) // (ADC12B) Input OFFSET 01948 // -------- ADC12B_EMR : (ADC12B Offset: 0x68) Extended Mode Register -------- 01949 #define AT91C_ADC12B_EMR_OFFMODES (0x1 << 0) // (ADC12B) Off Mode if Sleep Bit (ADC12B_MR) = 1 01950 #define AT91C_ADC12B_EMR_OFFMODES_STBY (0x0 << 0) // (ADC12B) Standby Mode 01951 #define AT91C_ADC12B_EMR_OFFMODES_OFF (0x1 << 0) // (ADC12B) Off Mode 01952 #define AT91C_ADC12B_EMR_OFF_MODE_STARTUP_TIME (0xff << 16) // (ADC12B) Startup Time 01953 01954 // ***************************************************************************** 01955 // SOFTWARE API DEFINITION FOR Timer Counter Channel Interface 01956 // ***************************************************************************** 01957 #ifndef __ASSEMBLY__ 01958 #else 01959 #define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register 01960 #define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode) 01961 #define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value 01962 #define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A 01963 #define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B 01964 #define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C 01965 #define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register 01966 #define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register 01967 #define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register 01968 #define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register 01969 01970 #endif 01971 // -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 01972 #define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command 01973 #define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command 01974 #define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command 01975 // -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 01976 #define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection 01977 #define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK 01978 #define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK 01979 #define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK 01980 #define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK 01981 #define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK 01982 #define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 01983 #define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 01984 #define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 01985 #define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert 01986 #define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection 01987 #define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal 01988 #define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock 01989 #define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock 01990 #define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock 01991 #define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare 01992 #define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading 01993 #define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare 01994 #define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading 01995 #define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection 01996 #define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None 01997 #define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge 01998 #define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge 01999 #define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge 02000 #define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection 02001 #define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None 02002 #define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge 02003 #define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge 02004 #define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge 02005 #define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection 02006 #define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input 02007 #define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output 02008 #define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output 02009 #define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output 02010 #define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection 02011 #define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable 02012 #define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection 02013 #define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare 02014 #define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare 02015 #define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare 02016 #define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare 02017 #define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable 02018 #define AT91C_TC_WAVE (0x1 << 15) // (TC) 02019 #define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA 02020 #define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none 02021 #define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set 02022 #define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear 02023 #define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle 02024 #define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection 02025 #define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None 02026 #define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA 02027 #define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA 02028 #define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA 02029 #define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA 02030 #define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none 02031 #define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set 02032 #define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear 02033 #define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle 02034 #define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection 02035 #define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None 02036 #define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA 02037 #define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA 02038 #define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA 02039 #define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA 02040 #define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none 02041 #define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set 02042 #define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear 02043 #define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle 02044 #define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA 02045 #define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none 02046 #define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set 02047 #define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear 02048 #define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle 02049 #define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB 02050 #define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none 02051 #define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set 02052 #define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear 02053 #define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle 02054 #define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB 02055 #define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none 02056 #define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set 02057 #define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear 02058 #define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle 02059 #define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB 02060 #define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none 02061 #define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set 02062 #define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear 02063 #define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle 02064 #define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB 02065 #define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none 02066 #define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set 02067 #define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear 02068 #define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle 02069 // -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 02070 #define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow 02071 #define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun 02072 #define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare 02073 #define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare 02074 #define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare 02075 #define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading 02076 #define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading 02077 #define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger 02078 #define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling 02079 #define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror 02080 #define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror 02081 // -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 02082 // -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 02083 // -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 02084 02085 // ***************************************************************************** 02086 // SOFTWARE API DEFINITION FOR Timer Counter Interface 02087 // ***************************************************************************** 02088 #ifndef __ASSEMBLY__ 02089 #else 02090 #define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register 02091 #define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register 02092 #define TC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER 02093 #define TC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER 02094 #define TC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER 02095 #define TC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER 02096 #define TC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TC_VER) Version Register 02097 02098 #endif 02099 // -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 02100 #define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command 02101 // -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 02102 #define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection 02103 #define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 02104 #define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 02105 #define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 02106 #define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 02107 #define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection 02108 #define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 02109 #define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 02110 #define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 02111 #define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 02112 #define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection 02113 #define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 02114 #define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 02115 #define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 02116 #define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 02117 02118 // ***************************************************************************** 02119 // SOFTWARE API DEFINITION FOR Embedded Flash Controller 2.0 02120 // ***************************************************************************** 02121 #ifndef __ASSEMBLY__ 02122 #else 02123 #define EFC_FMR (AT91_CAST(AT91_REG *) 0x00000000) // (EFC_FMR) EFC Flash Mode Register 02124 #define EFC_FCR (AT91_CAST(AT91_REG *) 0x00000004) // (EFC_FCR) EFC Flash Command Register 02125 #define EFC_FSR (AT91_CAST(AT91_REG *) 0x00000008) // (EFC_FSR) EFC Flash Status Register 02126 #define EFC_FRR (AT91_CAST(AT91_REG *) 0x0000000C) // (EFC_FRR) EFC Flash Result Register 02127 #define EFC_FVR (AT91_CAST(AT91_REG *) 0x00000014) // (EFC_FVR) EFC Flash Version Register 02128 02129 #endif 02130 // -------- EFC_FMR : (EFC Offset: 0x0) EFC Flash Mode Register -------- 02131 #define AT91C_EFC_FRDY (0x1 << 0) // (EFC) Ready Interrupt Enable 02132 #define AT91C_EFC_FWS (0xF << 8) // (EFC) Flash Wait State. 02133 #define AT91C_EFC_FWS_0WS (0x0 << 8) // (EFC) 0 Wait State 02134 #define AT91C_EFC_FWS_1WS (0x1 << 8) // (EFC) 1 Wait State 02135 #define AT91C_EFC_FWS_2WS (0x2 << 8) // (EFC) 2 Wait States 02136 #define AT91C_EFC_FWS_3WS (0x3 << 8) // (EFC) 3 Wait States 02137 // -------- EFC_FCR : (EFC Offset: 0x4) EFC Flash Command Register -------- 02138 #define AT91C_EFC_FCMD (0xFF << 0) // (EFC) Flash Command 02139 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor 02140 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page 02141 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock 02142 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page 02143 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock 02144 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All 02145 #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase Plane 02146 #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase Pages 02147 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit 02148 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit 02149 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit 02150 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit 02151 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit 02152 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit 02153 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID 02154 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID 02155 #define AT91C_EFC_FARG (0xFFFF << 8) // (EFC) Flash Command Argument 02156 #define AT91C_EFC_FKEY (0xFF << 24) // (EFC) Flash Writing Protection Key 02157 // -------- EFC_FSR : (EFC Offset: 0x8) EFC Flash Status Register -------- 02158 #define AT91C_EFC_FRDY_S (0x1 << 0) // (EFC) Flash Ready Status 02159 #define AT91C_EFC_FCMDE (0x1 << 1) // (EFC) Flash Command Error Status 02160 #define AT91C_EFC_LOCKE (0x1 << 2) // (EFC) Flash Lock Error Status 02161 // -------- EFC_FRR : (EFC Offset: 0xc) EFC Flash Result Register -------- 02162 #define AT91C_EFC_FVALUE (0x0 << 0) // (EFC) Flash Result Value 02163 02164 // ***************************************************************************** 02165 // SOFTWARE API DEFINITION FOR Multimedia Card Interface 02166 // ***************************************************************************** 02167 #ifndef __ASSEMBLY__ 02168 #else 02169 #define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register 02170 #define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register 02171 #define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register 02172 #define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD/SDIO Card Register 02173 #define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register 02174 #define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register 02175 #define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register 02176 #define MCI_CSTOR (AT91_CAST(AT91_REG *) 0x0000001C) // (MCI_CSTOR) MCI Completion Signal Timeout Register 02177 #define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register 02178 #define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register 02179 #define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register 02180 #define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register 02181 #define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register 02182 #define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register 02183 #define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register 02184 #define MCI_DMA (AT91_CAST(AT91_REG *) 0x00000050) // (MCI_DMA) MCI DMA Configuration Register 02185 #define MCI_CFG (AT91_CAST(AT91_REG *) 0x00000054) // (MCI_CFG) MCI Configuration Register 02186 #define MCI_WPCR (AT91_CAST(AT91_REG *) 0x000000E4) // (MCI_WPCR) MCI Write Protection Control Register 02187 #define MCI_WPSR (AT91_CAST(AT91_REG *) 0x000000E8) // (MCI_WPSR) MCI Write Protection Status Register 02188 #define MCI_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (MCI_ADDRSIZE) MCI ADDRSIZE REGISTER 02189 #define MCI_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (MCI_IPNAME1) MCI IPNAME1 REGISTER 02190 #define MCI_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (MCI_IPNAME2) MCI IPNAME2 REGISTER 02191 #define MCI_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (MCI_FEATURES) MCI FEATURES REGISTER 02192 #define MCI_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VER) MCI VERSION REGISTER 02193 #define MCI_FIFO (AT91_CAST(AT91_REG *) 0x00000200) // (MCI_FIFO) MCI FIFO Aperture Register 02194 02195 #endif 02196 // -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register -------- 02197 #define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable 02198 #define AT91C_MCI_MCIEN_0 (0x0) // (MCI) No effect 02199 #define AT91C_MCI_MCIEN_1 (0x1) // (MCI) Enable the MultiMedia Interface if MCIDIS is 0 02200 #define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable 02201 #define AT91C_MCI_MCIDIS_0 (0x0 << 1) // (MCI) No effect 02202 #define AT91C_MCI_MCIDIS_1 (0x1 << 1) // (MCI) Disable the MultiMedia Interface 02203 #define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable 02204 #define AT91C_MCI_PWSEN_0 (0x0 << 2) // (MCI) No effect 02205 #define AT91C_MCI_PWSEN_1 (0x1 << 2) // (MCI) Enable the Power-saving mode if PWSDIS is 0. 02206 #define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable 02207 #define AT91C_MCI_PWSDIS_0 (0x0 << 3) // (MCI) No effect 02208 #define AT91C_MCI_PWSDIS_1 (0x1 << 3) // (MCI) Disable the Power-saving mode. 02209 #define AT91C_MCI_IOWAITEN (0x1 << 4) // (MCI) SDIO Read Wait Enable 02210 #define AT91C_MCI_IOWAITEN_0 (0x0 << 4) // (MCI) No effect 02211 #define AT91C_MCI_IOWAITEN_1 (0x1 << 4) // (MCI) Enables the SDIO Read Wait Operation. 02212 #define AT91C_MCI_IOWAITDIS (0x1 << 5) // (MCI) SDIO Read Wait Disable 02213 #define AT91C_MCI_IOWAITDIS_0 (0x0 << 5) // (MCI) No effect 02214 #define AT91C_MCI_IOWAITDIS_1 (0x1 << 5) // (MCI) Disables the SDIO Read Wait Operation. 02215 #define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset 02216 #define AT91C_MCI_SWRST_0 (0x0 << 7) // (MCI) No effect 02217 #define AT91C_MCI_SWRST_1 (0x1 << 7) // (MCI) Resets the MCI 02218 // -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register -------- 02219 #define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider 02220 #define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider 02221 #define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable 02222 #define AT91C_MCI_RDPROOF_DISABLE (0x0 << 11) // (MCI) Disables Read Proof 02223 #define AT91C_MCI_RDPROOF_ENABLE (0x1 << 11) // (MCI) Enables Read Proof 02224 #define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable 02225 #define AT91C_MCI_WRPROOF_DISABLE (0x0 << 12) // (MCI) Disables Write Proof 02226 #define AT91C_MCI_WRPROOF_ENABLE (0x1 << 12) // (MCI) Enables Write Proof 02227 #define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer 02228 #define AT91C_MCI_PDCFBYTE_DISABLE (0x0 << 13) // (MCI) Disables PDC Force Byte Transfer 02229 #define AT91C_MCI_PDCFBYTE_ENABLE (0x1 << 13) // (MCI) Enables PDC Force Byte Transfer 02230 #define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value 02231 #define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode 02232 #define AT91C_MCI_PDCMODE_DISABLE (0x0 << 15) // (MCI) Disables PDC Transfer 02233 #define AT91C_MCI_PDCMODE_ENABLE (0x1 << 15) // (MCI) Enables PDC Transfer 02234 #define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length 02235 // -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register -------- 02236 #define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number 02237 #define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier 02238 #define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1 02239 #define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16 02240 #define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128 02241 #define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256 02242 #define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024 02243 #define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096 02244 #define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536 02245 #define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576 02246 // -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register -------- 02247 #define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card/SDIO Selector 02248 #define AT91C_MCI_SCDSEL_SLOTA (0x0) // (MCI) Slot A selected 02249 #define AT91C_MCI_SCDSEL_SLOTB (0x1) // (MCI) Slot B selected 02250 #define AT91C_MCI_SCDSEL_SLOTC (0x2) // (MCI) Slot C selected 02251 #define AT91C_MCI_SCDSEL_SLOTD (0x3) // (MCI) Slot D selected 02252 #define AT91C_MCI_SCDBUS (0x3 << 6) // (MCI) SDCard/SDIO Bus Width 02253 #define AT91C_MCI_SCDBUS_1BIT (0x0 << 6) // (MCI) 1-bit data bus 02254 #define AT91C_MCI_SCDBUS_4BITS (0x2 << 6) // (MCI) 4-bits data bus 02255 #define AT91C_MCI_SCDBUS_8BITS (0x3 << 6) // (MCI) 8-bits data bus 02256 // -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register -------- 02257 #define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number 02258 #define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type 02259 #define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response 02260 #define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response 02261 #define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response 02262 #define AT91C_MCI_RSPTYP_R1B (0x3 << 6) // (MCI) R1b response 02263 #define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD 02264 #define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD 02265 #define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD 02266 #define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD 02267 #define AT91C_MCI_SPCMD_CE_ATA (0x3 << 8) // (MCI) CE-ATA Completion Signal disable CMD 02268 #define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command 02269 #define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response 02270 #define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command 02271 #define AT91C_MCI_OPDCMD_PUSHPULL (0x0 << 11) // (MCI) Push/pull command 02272 #define AT91C_MCI_OPDCMD_OPENDRAIN (0x1 << 11) // (MCI) Open drain command 02273 #define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond 02274 #define AT91C_MCI_MAXLAT_5 (0x0 << 12) // (MCI) 5 cycles maximum latency 02275 #define AT91C_MCI_MAXLAT_64 (0x1 << 12) // (MCI) 64 cycles maximum latency 02276 #define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD 02277 #define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer 02278 #define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer 02279 #define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer 02280 #define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction 02281 #define AT91C_MCI_TRDIR_WRITE (0x0 << 18) // (MCI) Write 02282 #define AT91C_MCI_TRDIR_READ (0x1 << 18) // (MCI) Read 02283 #define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type 02284 #define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type 02285 #define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type 02286 #define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type 02287 #define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type 02288 #define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type 02289 #define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command 02290 #define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command 02291 #define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command 02292 #define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command 02293 #define AT91C_MCI_ATACS (0x1 << 26) // (MCI) ATA with command completion signal 02294 #define AT91C_MCI_ATACS_NORMAL (0x0 << 26) // (MCI) normal operation mode 02295 #define AT91C_MCI_ATACS_COMPLETION (0x1 << 26) // (MCI) completion signal is expected within MCI_CSTOR 02296 // -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register -------- 02297 #define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count 02298 // -------- MCI_CSTOR : (MCI Offset: 0x1c) MCI Completion Signal Timeout Register -------- 02299 #define AT91C_MCI_CSTOCYC (0xF << 0) // (MCI) Completion Signal Timeout Cycle Number 02300 #define AT91C_MCI_CSTOMUL (0x7 << 4) // (MCI) Completion Signal Timeout Multiplier 02301 #define AT91C_MCI_CSTOMUL_1 (0x0 << 4) // (MCI) CSTOCYC x 1 02302 #define AT91C_MCI_CSTOMUL_16 (0x1 << 4) // (MCI) CSTOCYC x 16 02303 #define AT91C_MCI_CSTOMUL_128 (0x2 << 4) // (MCI) CSTOCYC x 128 02304 #define AT91C_MCI_CSTOMUL_256 (0x3 << 4) // (MCI) CSTOCYC x 256 02305 #define AT91C_MCI_CSTOMUL_1024 (0x4 << 4) // (MCI) CSTOCYC x 1024 02306 #define AT91C_MCI_CSTOMUL_4096 (0x5 << 4) // (MCI) CSTOCYC x 4096 02307 #define AT91C_MCI_CSTOMUL_65536 (0x6 << 4) // (MCI) CSTOCYC x 65536 02308 #define AT91C_MCI_CSTOMUL_1048576 (0x7 << 4) // (MCI) CSTOCYC x 1048576 02309 // -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register -------- 02310 #define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag 02311 #define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag 02312 #define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag 02313 #define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag 02314 #define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag 02315 #define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag 02316 #define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag 02317 #define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag 02318 #define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A 02319 #define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B 02320 #define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C 02321 #define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D 02322 #define AT91C_MCI_SDIOWAIT (0x1 << 12) // (MCI) SDIO Read Wait operation flag 02323 #define AT91C_MCI_CSRCV (0x1 << 13) // (MCI) CE-ATA Completion Signal flag 02324 #define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag 02325 #define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag 02326 #define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag 02327 #define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag 02328 #define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag 02329 #define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag 02330 #define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag 02331 #define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag 02332 #define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag 02333 #define AT91C_MCI_CSTOE (0x1 << 23) // (MCI) Completion Signal timeout Error flag 02334 #define AT91C_MCI_BLKOVRE (0x1 << 24) // (MCI) DMA Block Overrun Error flag 02335 #define AT91C_MCI_DMADONE (0x1 << 25) // (MCI) DMA Transfer Done flag 02336 #define AT91C_MCI_FIFOEMPTY (0x1 << 26) // (MCI) FIFO Empty flag 02337 #define AT91C_MCI_XFRDONE (0x1 << 27) // (MCI) Transfer Done flag 02338 #define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag 02339 #define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag 02340 // -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register -------- 02341 // -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register -------- 02342 // -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register -------- 02343 // -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Configuration Register -------- 02344 #define AT91C_MCI_OFFSET (0x3 << 0) // (MCI) DMA Write Buffer Offset 02345 #define AT91C_MCI_CHKSIZE (0x7 << 4) // (MCI) DMA Channel Read/Write Chunk Size 02346 #define AT91C_MCI_CHKSIZE_1 (0x0 << 4) // (MCI) Number of data transferred is 1 02347 #define AT91C_MCI_CHKSIZE_4 (0x1 << 4) // (MCI) Number of data transferred is 4 02348 #define AT91C_MCI_CHKSIZE_8 (0x2 << 4) // (MCI) Number of data transferred is 8 02349 #define AT91C_MCI_CHKSIZE_16 (0x3 << 4) // (MCI) Number of data transferred is 16 02350 #define AT91C_MCI_CHKSIZE_32 (0x4 << 4) // (MCI) Number of data transferred is 32 02351 #define AT91C_MCI_DMAEN (0x1 << 8) // (MCI) DMA Hardware Handshaking Enable 02352 #define AT91C_MCI_DMAEN_DISABLE (0x0 << 8) // (MCI) DMA interface is disabled 02353 #define AT91C_MCI_DMAEN_ENABLE (0x1 << 8) // (MCI) DMA interface is enabled 02354 // -------- MCI_CFG : (MCI Offset: 0x54) MCI Configuration Register -------- 02355 #define AT91C_MCI_FIFOMODE (0x1 << 0) // (MCI) MCI Internal FIFO Control Mode 02356 #define AT91C_MCI_FIFOMODE_AMOUNTDATA (0x0) // (MCI) A write transfer starts when a sufficient amount of datas is written into the FIFO 02357 #define AT91C_MCI_FIFOMODE_ONEDATA (0x1) // (MCI) A write transfer starts as soon as one data is written into the FIFO 02358 #define AT91C_MCI_FERRCTRL (0x1 << 4) // (MCI) Flow Error Flag Reset Control Mode 02359 #define AT91C_MCI_FERRCTRL_RWCMD (0x0 << 4) // (MCI) When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag 02360 #define AT91C_MCI_FERRCTRL_READSR (0x1 << 4) // (MCI) When an underflow/overflow condition flag is set, a read status resets the flag 02361 #define AT91C_MCI_HSMODE (0x1 << 8) // (MCI) High Speed Mode 02362 #define AT91C_MCI_HSMODE_DISABLE (0x0 << 8) // (MCI) Default Bus Timing Mode 02363 #define AT91C_MCI_HSMODE_ENABLE (0x1 << 8) // (MCI) High Speed Mode 02364 #define AT91C_MCI_LSYNC (0x1 << 12) // (MCI) Synchronize on last block 02365 #define AT91C_MCI_LSYNC_CURRENT (0x0 << 12) // (MCI) Pending command sent at end of current data block 02366 #define AT91C_MCI_LSYNC_INFINITE (0x1 << 12) // (MCI) Pending command sent at end of block transfer when transfer length is not infinite 02367 // -------- MCI_WPCR : (MCI Offset: 0xe4) Write Protection Control Register -------- 02368 #define AT91C_MCI_WP_EN (0x1 << 0) // (MCI) Write Protection Enable 02369 #define AT91C_MCI_WP_EN_DISABLE (0x0) // (MCI) Write Operation is disabled (if WP_KEY corresponds) 02370 #define AT91C_MCI_WP_EN_ENABLE (0x1) // (MCI) Write Operation is enabled (if WP_KEY corresponds) 02371 #define AT91C_MCI_WP_KEY (0xFFFFFF << 8) // (MCI) Write Protection Key 02372 // -------- MCI_WPSR : (MCI Offset: 0xe8) Write Protection Status Register -------- 02373 #define AT91C_MCI_WP_VS (0xF << 0) // (MCI) Write Protection Violation Status 02374 #define AT91C_MCI_WP_VS_NO_VIOLATION (0x0) // (MCI) No Write Protection Violation detected since last read 02375 #define AT91C_MCI_WP_VS_ON_WRITE (0x1) // (MCI) Write Protection Violation detected since last read 02376 #define AT91C_MCI_WP_VS_ON_RESET (0x2) // (MCI) Software Reset Violation detected since last read 02377 #define AT91C_MCI_WP_VS_ON_BOTH (0x3) // (MCI) Write Protection and Software Reset Violation detected since last read 02378 #define AT91C_MCI_WP_VSRC (0xF << 8) // (MCI) Write Protection Violation Source 02379 #define AT91C_MCI_WP_VSRC_NO_VIOLATION (0x0 << 8) // (MCI) No Write Protection Violation detected since last read 02380 #define AT91C_MCI_WP_VSRC_MCI_MR (0x1 << 8) // (MCI) Write Protection Violation detected on MCI_MR since last read 02381 #define AT91C_MCI_WP_VSRC_MCI_DTOR (0x2 << 8) // (MCI) Write Protection Violation detected on MCI_DTOR since last read 02382 #define AT91C_MCI_WP_VSRC_MCI_SDCR (0x3 << 8) // (MCI) Write Protection Violation detected on MCI_SDCR since last read 02383 #define AT91C_MCI_WP_VSRC_MCI_CSTOR (0x4 << 8) // (MCI) Write Protection Violation detected on MCI_CSTOR since last read 02384 #define AT91C_MCI_WP_VSRC_MCI_DMA (0x5 << 8) // (MCI) Write Protection Violation detected on MCI_DMA since last read 02385 #define AT91C_MCI_WP_VSRC_MCI_CFG (0x6 << 8) // (MCI) Write Protection Violation detected on MCI_CFG since last read 02386 #define AT91C_MCI_WP_VSRC_MCI_DEL (0x7 << 8) // (MCI) Write Protection Violation detected on MCI_DEL since last read 02387 // -------- MCI_VER : (MCI Offset: 0xfc) VERSION Register -------- 02388 #define AT91C_MCI_VER (0xF << 0) // (MCI) VERSION Register 02389 02390 // ***************************************************************************** 02391 // SOFTWARE API DEFINITION FOR Two-wire Interface 02392 // ***************************************************************************** 02393 #ifndef __ASSEMBLY__ 02394 #else 02395 #define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register 02396 #define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register 02397 #define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register 02398 #define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register 02399 #define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register 02400 #define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register 02401 #define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register 02402 #define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register 02403 #define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register 02404 #define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register 02405 #define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register 02406 #define TWI_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TWI_ADDRSIZE) TWI ADDRSIZE REGISTER 02407 #define TWI_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TWI_IPNAME1) TWI IPNAME1 REGISTER 02408 #define TWI_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TWI_IPNAME2) TWI IPNAME2 REGISTER 02409 #define TWI_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TWI_FEATURES) TWI FEATURES REGISTER 02410 #define TWI_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TWI_VER) Version Register 02411 02412 #endif 02413 // -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 02414 #define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition 02415 #define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition 02416 #define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled 02417 #define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled 02418 #define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled 02419 #define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled 02420 #define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset 02421 // -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 02422 #define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size 02423 #define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address 02424 #define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address 02425 #define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address 02426 #define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address 02427 #define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction 02428 #define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address 02429 // -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 02430 #define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address 02431 // -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 02432 #define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider 02433 #define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider 02434 #define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider 02435 // -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 02436 #define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed 02437 #define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed 02438 #define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY 02439 #define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY 02440 #define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY 02441 #define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode) 02442 #define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode) 02443 #define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode) 02444 #define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode) 02445 #define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged 02446 #define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged 02447 #define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode) 02448 #define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode) 02449 #define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode) 02450 #define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer 02451 #define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer 02452 #define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt 02453 #define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt 02454 // -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 02455 // -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 02456 // -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 02457 02458 // ***************************************************************************** 02459 // SOFTWARE API DEFINITION FOR Usart 02460 // ***************************************************************************** 02461 #define US_CR_OFF ( 0x00000000) // (US_CR) Control Register 02462 #define US_MR_OFF ( 0x00000004) // (US_MR) Mode Register 02463 #define US_IER_OFF ( 0x00000008) // (US_IER) Interrupt Enable Register 02464 #define US_IDR_OFF ( 0x0000000C) // (US_IDR) Interrupt Disable Register 02465 #define US_IMR_OFF ( 0x00000010) // (US_IMR) Interrupt Mask Register 02466 #define US_CSR_OFF ( 0x00000014) // (US_CSR) Channel Status Register 02467 #define US_RHR_OFF ( 0x00000018) // (US_RHR) Receiver Holding Register 02468 #define US_THR_OFF ( 0x0000001C) // (US_THR) Transmitter Holding Register 02469 #define US_BRGR_OFF ( 0x00000020) // (US_BRGR) Baud Rate Generator Register 02470 #define US_RTOR_OFF ( 0x00000024) // (US_RTOR) Receiver Time-out Register 02471 #define US_TTGR_OFF ( 0x00000028) // (US_TTGR) Transmitter Time-guard Register 02472 #define US_FIDI_OFF ( 0x00000040) // (US_FIDI) FI_DI_Ratio Register 02473 #define US_NER_OFF ( 0x00000044) // (US_NER) Nb Errors Register 02474 #define US_IF_OFF ( 0x0000004C) // (US_IF) IRDA_FILTER Register 02475 #define US_MAN_OFF ( 0x00000050) // (US_MAN) Manchester Encoder Decoder Register 02476 #define US_ADDRSIZE_OFF ( 0x000000EC) // (US_ADDRSIZE) US ADDRSIZE REGISTER 02477 #define US_IPNAME1_OFF ( 0x000000F0) // (US_IPNAME1) US IPNAME1 REGISTER 02478 #define US_IPNAME2_OFF ( 0x000000F4) // (US_IPNAME2) US IPNAME2 REGISTER 02479 #define US_FEATURES_OFF ( 0x000000F8) // (US_FEATURES) US FEATURES REGISTER 02480 #define US_VER_OFF ( 0x000000FC) // (US_VER) VERSION Register 02481 02482 // -------- US_CR : (USART Offset: 0x0) Control Register -------- 02483 #define US_RSTRX (0x1 << 2) // (USART) Reset Receiver 02484 #define US_RSTTX (0x1 << 3) // (USART) Reset Transmitter 02485 #define US_RXEN (0x1 << 4) // (USART) Receiver Enable 02486 #define US_RXDIS (0x1 << 5) // (USART) Receiver Disable 02487 #define US_TXEN (0x1 << 6) // (USART) Transmitter Enable 02488 #define US_TXDIS (0x1 << 7) // (USART) Transmitter Disable 02489 #define US_RSTSTA (0x1 << 8) // (USART) Reset Status Bits 02490 #define US_STTBRK (0x1 << 9) // (USART) Start Break 02491 #define US_STPBRK (0x1 << 10) // (USART) Stop Break 02492 #define US_STTTO (0x1 << 11) // (USART) Start Time-out 02493 #define US_SENDA (0x1 << 12) // (USART) Send Address 02494 #define US_RSTIT (0x1 << 13) // (USART) Reset Iterations 02495 #define US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge 02496 #define US_RETTO (0x1 << 15) // (USART) Rearm Time-out 02497 #define US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable 02498 #define US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable 02499 #define US_RTSEN (0x1 << 18) // (USART) Request to Send enable 02500 #define US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable 02501 // -------- US_MR : (USART Offset: 0x4) Mode Register -------- 02502 #define US_USMODE (0xF << 0) // (USART) Usart mode 02503 #define US_USMODE_NORMAL (0x0) // (USART) Normal 02504 #define US_USMODE_RS485 (0x1) // (USART) RS485 02505 #define US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking 02506 #define US_USMODE_MODEM (0x3) // (USART) Modem 02507 #define US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 02508 #define US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 02509 #define US_USMODE_IRDA (0x8) // (USART) IrDA 02510 #define US_USMODE_SWHSH (0xC) // (USART) Software Handshaking 02511 #define US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock 02512 #define US_CLKS_MCK (0x0 << 4) // (USART) Clock 02513 #define US_CLKS_MCK8 (0x1 << 4) // (USART) fdiv1 02514 #define US_CLKS_SLCK (0x2 << 4) // (USART) slow_clock (ARM) 02515 #define US_CLKS_SCK (0x3 << 4) // (USART) External (SCK) 02516 #define US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock 02517 #define US_CHRL_5 (0x0 << 6) // (USART) Character Length: 5 bits 02518 #define US_CHRL_6 (0x1 << 6) // (USART) Character Length: 6 bits 02519 #define US_CHRL_7 (0x2 << 6) // (USART) Character Length: 7 bits 02520 #define US_CHRL_8 (0x3 << 6) // (USART) Character Length: 8 bits 02521 #define US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select 02522 #define US_PAR (0x7 << 9) // (USART) Parity type 02523 #define US_PAR_EVEN (0x0 << 9) // (USART) Even Parity 02524 #define US_PAR_ODD (0x1 << 9) // (USART) Odd Parity 02525 #define US_PAR_SPACE (0x2 << 9) // (USART) Parity forced to 0 (Space) 02526 #define US_PAR_MARK (0x3 << 9) // (USART) Parity forced to 1 (Mark) 02527 #define US_PAR_NO (0x4 << 9) // (USART) No Parity 02528 #define US_PAR_MULTIDROP (0x6 << 9) // (USART) Multi-drop mode 02529 #define US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits 02530 #define US_NBSTOP_1 (0x0 << 12) // (USART) 1 stop bit 02531 #define US_NBSTOP_15 (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits 02532 #define US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits 02533 #define US_CHMODE (0x3 << 14) // (USART) Channel Mode 02534 #define US_CHMODE_NORMAL (0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART. 02535 #define US_CHMODE_AUTO (0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin. 02536 #define US_CHMODE_LOCAL (0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. 02537 #define US_CHMODE_REMOTE (0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin. 02538 #define US_MSBF (0x1 << 16) // (USART) Bit Order 02539 #define US_MODE9 (0x1 << 17) // (USART) 9-bit Character length 02540 #define US_CKLO (0x1 << 18) // (USART) Clock Output Select 02541 #define US_OVER (0x1 << 19) // (USART) Over Sampling Mode 02542 #define US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge 02543 #define US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK 02544 #define US_VAR_SYNC (0x1 << 22) // (USART) Variable synchronization of command/data sync Start Frame Delimiter 02545 #define US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions 02546 #define US_FILTER (0x1 << 28) // (USART) Receive Line Filter 02547 #define US_MANMODE (0x1 << 29) // (USART) Manchester Encoder/Decoder Enable 02548 #define US_MODSYNC (0x1 << 30) // (USART) Manchester Synchronization mode 02549 #define US_ONEBIT (0x1 << 31) // (USART) Start Frame Delimiter selector 02550 // -------- US_IER : (USART Offset: 0x8) Interrupt Enable Register -------- 02551 #define US_RXRDY (0x1 << 0) // (USART) RXRDY Interrupt 02552 #define US_TXRDY (0x1 << 1) // (USART) TXRDY Interrupt 02553 #define US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break 02554 #define US_ENDRX (0x1 << 3) // (USART) End of Receive Transfer Interrupt 02555 #define US_ENDTX (0x1 << 4) // (USART) End of Transmit Interrupt 02556 #define US_OVRE (0x1 << 5) // (USART) Overrun Interrupt 02557 #define US_FRAME (0x1 << 6) // (USART) Framing Error Interrupt 02558 #define US_PARE (0x1 << 7) // (USART) Parity Error Interrupt 02559 #define US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out 02560 #define US_TXEMPTY (0x1 << 9) // (USART) TXEMPTY Interrupt 02561 #define US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached 02562 #define US_TXBUFE (0x1 << 11) // (USART) TXBUFE Interrupt 02563 #define US_RXBUFF (0x1 << 12) // (USART) RXBUFF Interrupt 02564 #define US_NACK (0x1 << 13) // (USART) Non Acknowledge 02565 #define US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag 02566 #define US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag 02567 #define US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag 02568 #define US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag 02569 #define US_MANE (0x1 << 20) // (USART) Manchester Error Interrupt 02570 // -------- US_IDR : (USART Offset: 0xc) Interrupt Disable Register -------- 02571 // -------- US_IMR : (USART Offset: 0x10) Interrupt Mask Register -------- 02572 // -------- US_CSR : (USART Offset: 0x14) Channel Status Register -------- 02573 #define US_RI (0x1 << 20) // (USART) Image of RI Input 02574 #define US_DSR (0x1 << 21) // (USART) Image of DSR Input 02575 #define US_DCD (0x1 << 22) // (USART) Image of DCD Input 02576 #define US_CTS (0x1 << 23) // (USART) Image of CTS Input 02577 #define US_MANERR (0x1 << 24) // (USART) Manchester Error 02578 // -------- US_MAN : (USART Offset: 0x50) Manchester Encoder Decoder Register -------- 02579 #define US_TX_PL (0xF << 0) // (USART) Transmitter Preamble Length 02580 #define US_TX_PP (0x3 << 8) // (USART) Transmitter Preamble Pattern 02581 #define US_TX_PP_ALL_ONE (0x0 << 8) // (USART) ALL_ONE 02582 #define US_TX_PP_ALL_ZERO (0x1 << 8) // (USART) ALL_ZERO 02583 #define US_TX_PP_ZERO_ONE (0x2 << 8) // (USART) ZERO_ONE 02584 #define US_TX_PP_ONE_ZERO (0x3 << 8) // (USART) ONE_ZERO 02585 #define US_TX_MPOL (0x1 << 12) // (USART) Transmitter Manchester Polarity 02586 #define US_RX_PL (0xF << 16) // (USART) Receiver Preamble Length 02587 #define US_RX_PP (0x3 << 24) // (USART) Receiver Preamble Pattern detected 02588 #define US_RX_PP_ALL_ONE (0x0 << 24) // (USART) ALL_ONE 02589 #define US_RX_PP_ALL_ZERO (0x1 << 24) // (USART) ALL_ZERO 02590 #define US_RX_PP_ZERO_ONE (0x2 << 24) // (USART) ZERO_ONE 02591 #define US_RX_PP_ONE_ZERO (0x3 << 24) // (USART) ONE_ZERO 02592 #define US_RX_MPOL (0x1 << 28) // (USART) Receiver Manchester Polarity 02593 #define US_DRIFT (0x1 << 30) // (USART) Drift compensation 02594 02595 // ***************************************************************************** 02596 // SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface 02597 // ***************************************************************************** 02598 #ifndef __ASSEMBLY__ 02599 #else 02600 #define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register 02601 #define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register 02602 #define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister 02603 #define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register 02604 #define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register 02605 #define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register 02606 #define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register 02607 #define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register 02608 #define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register 02609 #define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register 02610 #define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register 02611 #define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register 02612 #define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register 02613 #define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register 02614 #define SSC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (SSC_ADDRSIZE) SSC ADDRSIZE REGISTER 02615 #define SSC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (SSC_IPNAME1) SSC IPNAME1 REGISTER 02616 #define SSC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (SSC_IPNAME2) SSC IPNAME2 REGISTER 02617 #define SSC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (SSC_FEATURES) SSC FEATURES REGISTER 02618 #define SSC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (SSC_VER) Version Register 02619 02620 #endif 02621 // -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 02622 #define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable 02623 #define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable 02624 #define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable 02625 #define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable 02626 #define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset 02627 // -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 02628 #define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection 02629 #define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock 02630 #define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal 02631 #define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin 02632 #define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection 02633 #define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only 02634 #define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output 02635 #define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output 02636 #define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion 02637 #define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection 02638 #define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock 02639 #define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low 02640 #define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High 02641 #define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection 02642 #define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 02643 #define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start 02644 #define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input 02645 #define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input 02646 #define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input 02647 #define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input 02648 #define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input 02649 #define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input 02650 #define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 02651 #define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection 02652 #define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay 02653 #define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection 02654 // -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 02655 #define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length 02656 #define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode 02657 #define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First 02658 #define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame 02659 #define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length 02660 #define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection 02661 #define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only 02662 #define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse 02663 #define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse 02664 #define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer 02665 #define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer 02666 #define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer 02667 #define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection 02668 // -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 02669 // -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 02670 #define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value 02671 #define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable 02672 // -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 02673 #define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready 02674 #define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty 02675 #define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission 02676 #define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty 02677 #define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready 02678 #define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun 02679 #define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception 02680 #define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full 02681 #define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0 02682 #define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1 02683 #define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync 02684 #define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync 02685 #define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable 02686 #define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable 02687 // -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 02688 // -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 02689 // -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 02690 02691 // ***************************************************************************** 02692 // SOFTWARE API DEFINITION FOR PWMC Channel Interface 02693 // ***************************************************************************** 02694 #ifndef __ASSEMBLY__ 02695 #else 02696 #define PWMC_CMR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_CMR) Channel Mode Register 02697 #define PWMC_CDTYR (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_CDTYR) Channel Duty Cycle Register 02698 #define PWMC_CDTYUPDR (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_CDTYUPDR) Channel Duty Cycle Update Register 02699 #define PWMC_CPRDR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_CPRDR) Channel Period Register 02700 #define PWMC_CPRDUPDR (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_CPRDUPDR) Channel Period Update Register 02701 #define PWMC_CCNTR (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_CCNTR) Channel Counter Register 02702 #define PWMC_DTR (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_DTR) Channel Dead Time Value Register 02703 #define PWMC_DTUPDR (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_DTUPDR) Channel Dead Time Update Value Register 02704 02705 #endif 02706 // -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 02707 #define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx 02708 #define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) 02709 #define AT91C_PWMC_CPRE_MCK_DIV_2 (0x1) // (PWMC_CH) 02710 #define AT91C_PWMC_CPRE_MCK_DIV_4 (0x2) // (PWMC_CH) 02711 #define AT91C_PWMC_CPRE_MCK_DIV_8 (0x3) // (PWMC_CH) 02712 #define AT91C_PWMC_CPRE_MCK_DIV_16 (0x4) // (PWMC_CH) 02713 #define AT91C_PWMC_CPRE_MCK_DIV_32 (0x5) // (PWMC_CH) 02714 #define AT91C_PWMC_CPRE_MCK_DIV_64 (0x6) // (PWMC_CH) 02715 #define AT91C_PWMC_CPRE_MCK_DIV_128 (0x7) // (PWMC_CH) 02716 #define AT91C_PWMC_CPRE_MCK_DIV_256 (0x8) // (PWMC_CH) 02717 #define AT91C_PWMC_CPRE_MCK_DIV_512 (0x9) // (PWMC_CH) 02718 #define AT91C_PWMC_CPRE_MCK_DIV_1024 (0xA) // (PWMC_CH) 02719 #define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) 02720 #define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) 02721 #define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment 02722 #define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity 02723 #define AT91C_PWMC_CES (0x1 << 10) // (PWMC_CH) Counter Event Selection 02724 #define AT91C_PWMC_DTE (0x1 << 16) // (PWMC_CH) Dead Time Genrator Enable 02725 #define AT91C_PWMC_DTHI (0x1 << 17) // (PWMC_CH) Dead Time PWMHx Output Inverted 02726 #define AT91C_PWMC_DTLI (0x1 << 18) // (PWMC_CH) Dead Time PWMLx Output Inverted 02727 // -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 02728 #define AT91C_PWMC_CDTY (0xFFFFFF << 0) // (PWMC_CH) Channel Duty Cycle 02729 // -------- PWMC_CDTYUPDR : (PWMC_CH Offset: 0x8) PWMC Channel Duty Cycle Update Register -------- 02730 #define AT91C_PWMC_CDTYUPD (0xFFFFFF << 0) // (PWMC_CH) Channel Duty Cycle Update 02731 // -------- PWMC_CPRDR : (PWMC_CH Offset: 0xc) PWMC Channel Period Register -------- 02732 #define AT91C_PWMC_CPRD (0xFFFFFF << 0) // (PWMC_CH) Channel Period 02733 // -------- PWMC_CPRDUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Period Update Register -------- 02734 #define AT91C_PWMC_CPRDUPD (0xFFFFFF << 0) // (PWMC_CH) Channel Period Update 02735 // -------- PWMC_CCNTR : (PWMC_CH Offset: 0x14) PWMC Channel Counter Register -------- 02736 #define AT91C_PWMC_CCNT (0xFFFFFF << 0) // (PWMC_CH) Channel Counter 02737 // -------- PWMC_DTR : (PWMC_CH Offset: 0x18) Channel Dead Time Value Register -------- 02738 #define AT91C_PWMC_DTL (0xFFFF << 0) // (PWMC_CH) Channel Dead Time for PWML 02739 #define AT91C_PWMC_DTH (0xFFFF << 16) // (PWMC_CH) Channel Dead Time for PWMH 02740 // -------- PWMC_DTUPDR : (PWMC_CH Offset: 0x1c) Channel Dead Time Value Register -------- 02741 #define AT91C_PWMC_DTLUPD (0xFFFF << 0) // (PWMC_CH) Channel Dead Time Update for PWML. 02742 #define AT91C_PWMC_DTHUPD (0xFFFF << 16) // (PWMC_CH) Channel Dead Time Update for PWMH. 02743 02744 // ***************************************************************************** 02745 // SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface 02746 // ***************************************************************************** 02747 #ifndef __ASSEMBLY__ 02748 #else 02749 #define PWMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (PWMC_MR) PWMC Mode Register 02750 #define PWMC_ENA (AT91_CAST(AT91_REG *) 0x00000004) // (PWMC_ENA) PWMC Enable Register 02751 #define PWMC_DIS (AT91_CAST(AT91_REG *) 0x00000008) // (PWMC_DIS) PWMC Disable Register 02752 #define PWMC_SR (AT91_CAST(AT91_REG *) 0x0000000C) // (PWMC_SR) PWMC Status Register 02753 #define PWMC_IER1 (AT91_CAST(AT91_REG *) 0x00000010) // (PWMC_IER1) PWMC Interrupt Enable Register 1 02754 #define PWMC_IDR1 (AT91_CAST(AT91_REG *) 0x00000014) // (PWMC_IDR1) PWMC Interrupt Disable Register 1 02755 #define PWMC_IMR1 (AT91_CAST(AT91_REG *) 0x00000018) // (PWMC_IMR1) PWMC Interrupt Mask Register 1 02756 #define PWMC_ISR1 (AT91_CAST(AT91_REG *) 0x0000001C) // (PWMC_ISR1) PWMC Interrupt Status Register 1 02757 #define PWMC_SYNC (AT91_CAST(AT91_REG *) 0x00000020) // (PWMC_SYNC) PWM Synchronized Channels Register 02758 #define PWMC_UPCR (AT91_CAST(AT91_REG *) 0x00000028) // (PWMC_UPCR) PWM Update Control Register 02759 #define PWMC_SCUP (AT91_CAST(AT91_REG *) 0x0000002C) // (PWMC_SCUP) PWM Update Period Register 02760 #define PWMC_SCUPUPD (AT91_CAST(AT91_REG *) 0x00000030) // (PWMC_SCUPUPD) PWM Update Period Update Register 02761 #define PWMC_IER2 (AT91_CAST(AT91_REG *) 0x00000034) // (PWMC_IER2) PWMC Interrupt Enable Register 2 02762 #define PWMC_IDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (PWMC_IDR2) PWMC Interrupt Disable Register 2 02763 #define PWMC_IMR2 (AT91_CAST(AT91_REG *) 0x0000003C) // (PWMC_IMR2) PWMC Interrupt Mask Register 2 02764 #define PWMC_ISR2 (AT91_CAST(AT91_REG *) 0x00000040) // (PWMC_ISR2) PWMC Interrupt Status Register 2 02765 #define PWMC_OOV (AT91_CAST(AT91_REG *) 0x00000044) // (PWMC_OOV) PWM Output Override Value Register 02766 #define PWMC_OS (AT91_CAST(AT91_REG *) 0x00000048) // (PWMC_OS) PWM Output Selection Register 02767 #define PWMC_OSS (AT91_CAST(AT91_REG *) 0x0000004C) // (PWMC_OSS) PWM Output Selection Set Register 02768 #define PWMC_OSC (AT91_CAST(AT91_REG *) 0x00000050) // (PWMC_OSC) PWM Output Selection Clear Register 02769 #define PWMC_OSSUPD (AT91_CAST(AT91_REG *) 0x00000054) // (PWMC_OSSUPD) PWM Output Selection Set Update Register 02770 #define PWMC_OSCUPD (AT91_CAST(AT91_REG *) 0x00000058) // (PWMC_OSCUPD) PWM Output Selection Clear Update Register 02771 #define PWMC_FMR (AT91_CAST(AT91_REG *) 0x0000005C) // (PWMC_FMR) PWM Fault Mode Register 02772 #define PWMC_FSR (AT91_CAST(AT91_REG *) 0x00000060) // (PWMC_FSR) PWM Fault Mode Status Register 02773 #define PWMC_FCR (AT91_CAST(AT91_REG *) 0x00000064) // (PWMC_FCR) PWM Fault Mode Clear Register 02774 #define PWMC_FPV (AT91_CAST(AT91_REG *) 0x00000068) // (PWMC_FPV) PWM Fault Protection Value Register 02775 #define PWMC_FPER1 (AT91_CAST(AT91_REG *) 0x0000006C) // (PWMC_FPER1) PWM Fault Protection Enable Register 1 02776 #define PWMC_FPER2 (AT91_CAST(AT91_REG *) 0x00000070) // (PWMC_FPER2) PWM Fault Protection Enable Register 2 02777 #define PWMC_FPER3 (AT91_CAST(AT91_REG *) 0x00000074) // (PWMC_FPER3) PWM Fault Protection Enable Register 3 02778 #define PWMC_FPER4 (AT91_CAST(AT91_REG *) 0x00000078) // (PWMC_FPER4) PWM Fault Protection Enable Register 4 02779 #define PWMC_EL0MR (AT91_CAST(AT91_REG *) 0x0000007C) // (PWMC_EL0MR) PWM Event Line 0 Mode Register 02780 #define PWMC_EL1MR (AT91_CAST(AT91_REG *) 0x00000080) // (PWMC_EL1MR) PWM Event Line 1 Mode Register 02781 #define PWMC_EL2MR (AT91_CAST(AT91_REG *) 0x00000084) // (PWMC_EL2MR) PWM Event Line 2 Mode Register 02782 #define PWMC_EL3MR (AT91_CAST(AT91_REG *) 0x00000088) // (PWMC_EL3MR) PWM Event Line 3 Mode Register 02783 #define PWMC_EL4MR (AT91_CAST(AT91_REG *) 0x0000008C) // (PWMC_EL4MR) PWM Event Line 4 Mode Register 02784 #define PWMC_EL5MR (AT91_CAST(AT91_REG *) 0x00000090) // (PWMC_EL5MR) PWM Event Line 5 Mode Register 02785 #define PWMC_EL6MR (AT91_CAST(AT91_REG *) 0x00000094) // (PWMC_EL6MR) PWM Event Line 6 Mode Register 02786 #define PWMC_EL7MR (AT91_CAST(AT91_REG *) 0x00000098) // (PWMC_EL7MR) PWM Event Line 7 Mode Register 02787 #define PWMC_WPCR (AT91_CAST(AT91_REG *) 0x000000E4) // (PWMC_WPCR) PWM Write Protection Enable Register 02788 #define PWMC_WPSR (AT91_CAST(AT91_REG *) 0x000000E8) // (PWMC_WPSR) PWM Write Protection Status Register 02789 #define PWMC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (PWMC_ADDRSIZE) PWMC ADDRSIZE REGISTER 02790 #define PWMC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (PWMC_IPNAME1) PWMC IPNAME1 REGISTER 02791 #define PWMC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (PWMC_IPNAME2) PWMC IPNAME2 REGISTER 02792 #define PWMC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (PWMC_FEATURES) PWMC FEATURES REGISTER 02793 #define PWMC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (PWMC_VER) PWMC Version Register 02794 #define PWMC_CMP0V (AT91_CAST(AT91_REG *) 0x00000130) // (PWMC_CMP0V) PWM Comparison Value 0 Register 02795 #define PWMC_CMP0VUPD (AT91_CAST(AT91_REG *) 0x00000134) // (PWMC_CMP0VUPD) PWM Comparison Value 0 Update Register 02796 #define PWMC_CMP0M (AT91_CAST(AT91_REG *) 0x00000138) // (PWMC_CMP0M) PWM Comparison Mode 0 Register 02797 #define PWMC_CMP0MUPD (AT91_CAST(AT91_REG *) 0x0000013C) // (PWMC_CMP0MUPD) PWM Comparison Mode 0 Update Register 02798 #define PWMC_CMP1V (AT91_CAST(AT91_REG *) 0x00000140) // (PWMC_CMP1V) PWM Comparison Value 1 Register 02799 #define PWMC_CMP1VUPD (AT91_CAST(AT91_REG *) 0x00000144) // (PWMC_CMP1VUPD) PWM Comparison Value 1 Update Register 02800 #define PWMC_CMP1M (AT91_CAST(AT91_REG *) 0x00000148) // (PWMC_CMP1M) PWM Comparison Mode 1 Register 02801 #define PWMC_CMP1MUPD (AT91_CAST(AT91_REG *) 0x0000014C) // (PWMC_CMP1MUPD) PWM Comparison Mode 1 Update Register 02802 #define PWMC_CMP2V (AT91_CAST(AT91_REG *) 0x00000150) // (PWMC_CMP2V) PWM Comparison Value 2 Register 02803 #define PWMC_CMP2VUPD (AT91_CAST(AT91_REG *) 0x00000154) // (PWMC_CMP2VUPD) PWM Comparison Value 2 Update Register 02804 #define PWMC_CMP2M (AT91_CAST(AT91_REG *) 0x00000158) // (PWMC_CMP2M) PWM Comparison Mode 2 Register 02805 #define PWMC_CMP2MUPD (AT91_CAST(AT91_REG *) 0x0000015C) // (PWMC_CMP2MUPD) PWM Comparison Mode 2 Update Register 02806 #define PWMC_CMP3V (AT91_CAST(AT91_REG *) 0x00000160) // (PWMC_CMP3V) PWM Comparison Value 3 Register 02807 #define PWMC_CMP3VUPD (AT91_CAST(AT91_REG *) 0x00000164) // (PWMC_CMP3VUPD) PWM Comparison Value 3 Update Register 02808 #define PWMC_CMP3M (AT91_CAST(AT91_REG *) 0x00000168) // (PWMC_CMP3M) PWM Comparison Mode 3 Register 02809 #define PWMC_CMP3MUPD (AT91_CAST(AT91_REG *) 0x0000016C) // (PWMC_CMP3MUPD) PWM Comparison Mode 3 Update Register 02810 #define PWMC_CMP4V (AT91_CAST(AT91_REG *) 0x00000170) // (PWMC_CMP4V) PWM Comparison Value 4 Register 02811 #define PWMC_CMP4VUPD (AT91_CAST(AT91_REG *) 0x00000174) // (PWMC_CMP4VUPD) PWM Comparison Value 4 Update Register 02812 #define PWMC_CMP4M (AT91_CAST(AT91_REG *) 0x00000178) // (PWMC_CMP4M) PWM Comparison Mode 4 Register 02813 #define PWMC_CMP4MUPD (AT91_CAST(AT91_REG *) 0x0000017C) // (PWMC_CMP4MUPD) PWM Comparison Mode 4 Update Register 02814 #define PWMC_CMP5V (AT91_CAST(AT91_REG *) 0x00000180) // (PWMC_CMP5V) PWM Comparison Value 5 Register 02815 #define PWMC_CMP5VUPD (AT91_CAST(AT91_REG *) 0x00000184) // (PWMC_CMP5VUPD) PWM Comparison Value 5 Update Register 02816 #define PWMC_CMP5M (AT91_CAST(AT91_REG *) 0x00000188) // (PWMC_CMP5M) PWM Comparison Mode 5 Register 02817 #define PWMC_CMP5MUPD (AT91_CAST(AT91_REG *) 0x0000018C) // (PWMC_CMP5MUPD) PWM Comparison Mode 5 Update Register 02818 #define PWMC_CMP6V (AT91_CAST(AT91_REG *) 0x00000190) // (PWMC_CMP6V) PWM Comparison Value 6 Register 02819 #define PWMC_CMP6VUPD (AT91_CAST(AT91_REG *) 0x00000194) // (PWMC_CMP6VUPD) PWM Comparison Value 6 Update Register 02820 #define PWMC_CMP6M (AT91_CAST(AT91_REG *) 0x00000198) // (PWMC_CMP6M) PWM Comparison Mode 6 Register 02821 #define PWMC_CMP6MUPD (AT91_CAST(AT91_REG *) 0x0000019C) // (PWMC_CMP6MUPD) PWM Comparison Mode 6 Update Register 02822 #define PWMC_CMP7V (AT91_CAST(AT91_REG *) 0x000001A0) // (PWMC_CMP7V) PWM Comparison Value 7 Register 02823 #define PWMC_CMP7VUPD (AT91_CAST(AT91_REG *) 0x000001A4) // (PWMC_CMP7VUPD) PWM Comparison Value 7 Update Register 02824 #define PWMC_CMP7M (AT91_CAST(AT91_REG *) 0x000001A8) // (PWMC_CMP7M) PWM Comparison Mode 7 Register 02825 #define PWMC_CMP7MUPD (AT91_CAST(AT91_REG *) 0x000001AC) // (PWMC_CMP7MUPD) PWM Comparison Mode 7 Update Register 02826 02827 #endif 02828 // -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 02829 #define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. 02830 #define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A 02831 #define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) 02832 #define AT91C_PWMC_PREA_MCK_DIV_2 (0x1 << 8) // (PWMC) 02833 #define AT91C_PWMC_PREA_MCK_DIV_4 (0x2 << 8) // (PWMC) 02834 #define AT91C_PWMC_PREA_MCK_DIV_8 (0x3 << 8) // (PWMC) 02835 #define AT91C_PWMC_PREA_MCK_DIV_16 (0x4 << 8) // (PWMC) 02836 #define AT91C_PWMC_PREA_MCK_DIV_32 (0x5 << 8) // (PWMC) 02837 #define AT91C_PWMC_PREA_MCK_DIV_64 (0x6 << 8) // (PWMC) 02838 #define AT91C_PWMC_PREA_MCK_DIV_128 (0x7 << 8) // (PWMC) 02839 #define AT91C_PWMC_PREA_MCK_DIV_256 (0x8 << 8) // (PWMC) 02840 #define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. 02841 #define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B 02842 #define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) 02843 #define AT91C_PWMC_PREB_MCK_DIV_2 (0x1 << 24) // (PWMC) 02844 #define AT91C_PWMC_PREB_MCK_DIV_4 (0x2 << 24) // (PWMC) 02845 #define AT91C_PWMC_PREB_MCK_DIV_8 (0x3 << 24) // (PWMC) 02846 #define AT91C_PWMC_PREB_MCK_DIV_16 (0x4 << 24) // (PWMC) 02847 #define AT91C_PWMC_PREB_MCK_DIV_32 (0x5 << 24) // (PWMC) 02848 #define AT91C_PWMC_PREB_MCK_DIV_64 (0x6 << 24) // (PWMC) 02849 #define AT91C_PWMC_PREB_MCK_DIV_128 (0x7 << 24) // (PWMC) 02850 #define AT91C_PWMC_PREB_MCK_DIV_256 (0x8 << 24) // (PWMC) 02851 #define AT91C_PWMC_CLKSEL (0x1 << 31) // (PWMC) CCK Source Clock Selection 02852 // -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 02853 #define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 02854 #define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 02855 #define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 02856 #define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 02857 #define AT91C_PWMC_CHID4 (0x1 << 4) // (PWMC) Channel ID 4 02858 #define AT91C_PWMC_CHID5 (0x1 << 5) // (PWMC) Channel ID 5 02859 #define AT91C_PWMC_CHID6 (0x1 << 6) // (PWMC) Channel ID 6 02860 #define AT91C_PWMC_CHID7 (0x1 << 7) // (PWMC) Channel ID 7 02861 #define AT91C_PWMC_CHID8 (0x1 << 8) // (PWMC) Channel ID 8 02862 #define AT91C_PWMC_CHID9 (0x1 << 9) // (PWMC) Channel ID 9 02863 #define AT91C_PWMC_CHID10 (0x1 << 10) // (PWMC) Channel ID 10 02864 #define AT91C_PWMC_CHID11 (0x1 << 11) // (PWMC) Channel ID 11 02865 #define AT91C_PWMC_CHID12 (0x1 << 12) // (PWMC) Channel ID 12 02866 #define AT91C_PWMC_CHID13 (0x1 << 13) // (PWMC) Channel ID 13 02867 #define AT91C_PWMC_CHID14 (0x1 << 14) // (PWMC) Channel ID 14 02868 #define AT91C_PWMC_CHID15 (0x1 << 15) // (PWMC) Channel ID 15 02869 // -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 02870 // -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 02871 // -------- PWMC_IER1 : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 02872 #define AT91C_PWMC_FCHID0 (0x1 << 16) // (PWMC) Fault Event Channel ID 0 02873 #define AT91C_PWMC_FCHID1 (0x1 << 17) // (PWMC) Fault Event Channel ID 1 02874 #define AT91C_PWMC_FCHID2 (0x1 << 18) // (PWMC) Fault Event Channel ID 2 02875 #define AT91C_PWMC_FCHID3 (0x1 << 19) // (PWMC) Fault Event Channel ID 3 02876 #define AT91C_PWMC_FCHID4 (0x1 << 20) // (PWMC) Fault Event Channel ID 4 02877 #define AT91C_PWMC_FCHID5 (0x1 << 21) // (PWMC) Fault Event Channel ID 5 02878 #define AT91C_PWMC_FCHID6 (0x1 << 22) // (PWMC) Fault Event Channel ID 6 02879 #define AT91C_PWMC_FCHID7 (0x1 << 23) // (PWMC) Fault Event Channel ID 7 02880 #define AT91C_PWMC_FCHID8 (0x1 << 24) // (PWMC) Fault Event Channel ID 8 02881 #define AT91C_PWMC_FCHID9 (0x1 << 25) // (PWMC) Fault Event Channel ID 9 02882 #define AT91C_PWMC_FCHID10 (0x1 << 26) // (PWMC) Fault Event Channel ID 10 02883 #define AT91C_PWMC_FCHID11 (0x1 << 27) // (PWMC) Fault Event Channel ID 11 02884 #define AT91C_PWMC_FCHID12 (0x1 << 28) // (PWMC) Fault Event Channel ID 12 02885 #define AT91C_PWMC_FCHID13 (0x1 << 29) // (PWMC) Fault Event Channel ID 13 02886 #define AT91C_PWMC_FCHID14 (0x1 << 30) // (PWMC) Fault Event Channel ID 14 02887 #define AT91C_PWMC_FCHID15 (0x1 << 31) // (PWMC) Fault Event Channel ID 15 02888 // -------- PWMC_IDR1 : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 02889 // -------- PWMC_IMR1 : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 02890 // -------- PWMC_ISR1 : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 02891 // -------- PWMC_SYNC : (PWMC Offset: 0x20) PWMC Synchronous Channels Register -------- 02892 #define AT91C_PWMC_SYNC0 (0x1 << 0) // (PWMC) Synchronous Channel ID 0 02893 #define AT91C_PWMC_SYNC1 (0x1 << 1) // (PWMC) Synchronous Channel ID 1 02894 #define AT91C_PWMC_SYNC2 (0x1 << 2) // (PWMC) Synchronous Channel ID 2 02895 #define AT91C_PWMC_SYNC3 (0x1 << 3) // (PWMC) Synchronous Channel ID 3 02896 #define AT91C_PWMC_SYNC4 (0x1 << 4) // (PWMC) Synchronous Channel ID 4 02897 #define AT91C_PWMC_SYNC5 (0x1 << 5) // (PWMC) Synchronous Channel ID 5 02898 #define AT91C_PWMC_SYNC6 (0x1 << 6) // (PWMC) Synchronous Channel ID 6 02899 #define AT91C_PWMC_SYNC7 (0x1 << 7) // (PWMC) Synchronous Channel ID 7 02900 #define AT91C_PWMC_SYNC8 (0x1 << 8) // (PWMC) Synchronous Channel ID 8 02901 #define AT91C_PWMC_SYNC9 (0x1 << 9) // (PWMC) Synchronous Channel ID 9 02902 #define AT91C_PWMC_SYNC10 (0x1 << 10) // (PWMC) Synchronous Channel ID 10 02903 #define AT91C_PWMC_SYNC11 (0x1 << 11) // (PWMC) Synchronous Channel ID 11 02904 #define AT91C_PWMC_SYNC12 (0x1 << 12) // (PWMC) Synchronous Channel ID 12 02905 #define AT91C_PWMC_SYNC13 (0x1 << 13) // (PWMC) Synchronous Channel ID 13 02906 #define AT91C_PWMC_SYNC14 (0x1 << 14) // (PWMC) Synchronous Channel ID 14 02907 #define AT91C_PWMC_SYNC15 (0x1 << 15) // (PWMC) Synchronous Channel ID 15 02908 #define AT91C_PWMC_UPDM (0x3 << 16) // (PWMC) Synchronous Channels Update mode 02909 #define AT91C_PWMC_UPDM_MODE0 (0x0 << 16) // (PWMC) Manual write of data and manual trigger of the update 02910 #define AT91C_PWMC_UPDM_MODE1 (0x1 << 16) // (PWMC) Manual write of data and automatic trigger of the update 02911 #define AT91C_PWMC_UPDM_MODE2 (0x2 << 16) // (PWMC) Automatic write of data and automatic trigger of the update 02912 // -------- PWMC_UPCR : (PWMC Offset: 0x28) PWMC Update Control Register -------- 02913 #define AT91C_PWMC_UPDULOCK (0x1 << 0) // (PWMC) Synchronized Channels Duty Cycle Update Unlock 02914 // -------- PWMC_SCUP : (PWMC Offset: 0x2c) PWM Update Period Register -------- 02915 #define AT91C_PWMC_UPR (0xF << 0) // (PWMC) PWM Update Period. 02916 #define AT91C_PWMC_UPRCNT (0xF << 4) // (PWMC) PWM Update Period Counter. 02917 // -------- PWMC_SCUPUPD : (PWMC Offset: 0x30) PWM Update Period Update Register -------- 02918 #define AT91C_PWMC_UPVUPDAL (0xF << 0) // (PWMC) PWM Update Period Update. 02919 // -------- PWMC_IER2 : (PWMC Offset: 0x34) PWMC Interrupt Enable Register -------- 02920 #define AT91C_PWMC_WRDY (0x1 << 0) // (PWMC) PDC Write Ready 02921 #define AT91C_PWMC_ENDTX (0x1 << 1) // (PWMC) PDC End of TX Buffer 02922 #define AT91C_PWMC_TXBUFE (0x1 << 2) // (PWMC) PDC End of TX Buffer 02923 #define AT91C_PWMC_UNRE (0x1 << 3) // (PWMC) PDC End of TX Buffer 02924 // -------- PWMC_IDR2 : (PWMC Offset: 0x38) PWMC Interrupt Disable Register -------- 02925 // -------- PWMC_IMR2 : (PWMC Offset: 0x3c) PWMC Interrupt Mask Register -------- 02926 // -------- PWMC_ISR2 : (PWMC Offset: 0x40) PWMC Interrupt Status Register -------- 02927 #define AT91C_PWMC_CMPM0 (0x1 << 8) // (PWMC) Comparison x Match 02928 #define AT91C_PWMC_CMPM1 (0x1 << 9) // (PWMC) Comparison x Match 02929 #define AT91C_PWMC_CMPM2 (0x1 << 10) // (PWMC) Comparison x Match 02930 #define AT91C_PWMC_CMPM3 (0x1 << 11) // (PWMC) Comparison x Match 02931 #define AT91C_PWMC_CMPM4 (0x1 << 12) // (PWMC) Comparison x Match 02932 #define AT91C_PWMC_CMPM5 (0x1 << 13) // (PWMC) Comparison x Match 02933 #define AT91C_PWMC_CMPM6 (0x1 << 14) // (PWMC) Comparison x Match 02934 #define AT91C_PWMC_CMPM7 (0x1 << 15) // (PWMC) Comparison x Match 02935 #define AT91C_PWMC_CMPU0 (0x1 << 16) // (PWMC) Comparison x Update 02936 #define AT91C_PWMC_CMPU1 (0x1 << 17) // (PWMC) Comparison x Update 02937 #define AT91C_PWMC_CMPU2 (0x1 << 18) // (PWMC) Comparison x Update 02938 #define AT91C_PWMC_CMPU3 (0x1 << 19) // (PWMC) Comparison x Update 02939 #define AT91C_PWMC_CMPU4 (0x1 << 20) // (PWMC) Comparison x Update 02940 #define AT91C_PWMC_CMPU5 (0x1 << 21) // (PWMC) Comparison x Update 02941 #define AT91C_PWMC_CMPU6 (0x1 << 22) // (PWMC) Comparison x Update 02942 #define AT91C_PWMC_CMPU7 (0x1 << 23) // (PWMC) Comparison x Update 02943 // -------- PWMC_OOV : (PWMC Offset: 0x44) PWM Output Override Value Register -------- 02944 #define AT91C_PWMC_OOVH0 (0x1 << 0) // (PWMC) Output Override Value for PWMH output of the channel 0 02945 #define AT91C_PWMC_OOVH1 (0x1 << 1) // (PWMC) Output Override Value for PWMH output of the channel 1 02946 #define AT91C_PWMC_OOVH2 (0x1 << 2) // (PWMC) Output Override Value for PWMH output of the channel 2 02947 #define AT91C_PWMC_OOVH3 (0x1 << 3) // (PWMC) Output Override Value for PWMH output of the channel 3 02948 #define AT91C_PWMC_OOVH4 (0x1 << 4) // (PWMC) Output Override Value for PWMH output of the channel 4 02949 #define AT91C_PWMC_OOVH5 (0x1 << 5) // (PWMC) Output Override Value for PWMH output of the channel 5 02950 #define AT91C_PWMC_OOVH6 (0x1 << 6) // (PWMC) Output Override Value for PWMH output of the channel 6 02951 #define AT91C_PWMC_OOVH7 (0x1 << 7) // (PWMC) Output Override Value for PWMH output of the channel 7 02952 #define AT91C_PWMC_OOVH8 (0x1 << 8) // (PWMC) Output Override Value for PWMH output of the channel 8 02953 #define AT91C_PWMC_OOVH9 (0x1 << 9) // (PWMC) Output Override Value for PWMH output of the channel 9 02954 #define AT91C_PWMC_OOVH10 (0x1 << 10) // (PWMC) Output Override Value for PWMH output of the channel 10 02955 #define AT91C_PWMC_OOVH11 (0x1 << 11) // (PWMC) Output Override Value for PWMH output of the channel 11 02956 #define AT91C_PWMC_OOVH12 (0x1 << 12) // (PWMC) Output Override Value for PWMH output of the channel 12 02957 #define AT91C_PWMC_OOVH13 (0x1 << 13) // (PWMC) Output Override Value for PWMH output of the channel 13 02958 #define AT91C_PWMC_OOVH14 (0x1 << 14) // (PWMC) Output Override Value for PWMH output of the channel 14 02959 #define AT91C_PWMC_OOVH15 (0x1 << 15) // (PWMC) Output Override Value for PWMH output of the channel 15 02960 #define AT91C_PWMC_OOVL0 (0x1 << 16) // (PWMC) Output Override Value for PWML output of the channel 0 02961 #define AT91C_PWMC_OOVL1 (0x1 << 17) // (PWMC) Output Override Value for PWML output of the channel 1 02962 #define AT91C_PWMC_OOVL2 (0x1 << 18) // (PWMC) Output Override Value for PWML output of the channel 2 02963 #define AT91C_PWMC_OOVL3 (0x1 << 19) // (PWMC) Output Override Value for PWML output of the channel 3 02964 #define AT91C_PWMC_OOVL4 (0x1 << 20) // (PWMC) Output Override Value for PWML output of the channel 4 02965 #define AT91C_PWMC_OOVL5 (0x1 << 21) // (PWMC) Output Override Value for PWML output of the channel 5 02966 #define AT91C_PWMC_OOVL6 (0x1 << 22) // (PWMC) Output Override Value for PWML output of the channel 6 02967 #define AT91C_PWMC_OOVL7 (0x1 << 23) // (PWMC) Output Override Value for PWML output of the channel 7 02968 #define AT91C_PWMC_OOVL8 (0x1 << 24) // (PWMC) Output Override Value for PWML output of the channel 8 02969 #define AT91C_PWMC_OOVL9 (0x1 << 25) // (PWMC) Output Override Value for PWML output of the channel 9 02970 #define AT91C_PWMC_OOVL10 (0x1 << 26) // (PWMC) Output Override Value for PWML output of the channel 10 02971 #define AT91C_PWMC_OOVL11 (0x1 << 27) // (PWMC) Output Override Value for PWML output of the channel 11 02972 #define AT91C_PWMC_OOVL12 (0x1 << 28) // (PWMC) Output Override Value for PWML output of the channel 12 02973 #define AT91C_PWMC_OOVL13 (0x1 << 29) // (PWMC) Output Override Value for PWML output of the channel 13 02974 #define AT91C_PWMC_OOVL14 (0x1 << 30) // (PWMC) Output Override Value for PWML output of the channel 14 02975 #define AT91C_PWMC_OOVL15 (0x1 << 31) // (PWMC) Output Override Value for PWML output of the channel 15 02976 // -------- PWMC_OS : (PWMC Offset: 0x48) PWM Output Selection Register -------- 02977 #define AT91C_PWMC_OSH0 (0x1 << 0) // (PWMC) Output Selection for PWMH output of the channel 0 02978 #define AT91C_PWMC_OSH1 (0x1 << 1) // (PWMC) Output Selection for PWMH output of the channel 1 02979 #define AT91C_PWMC_OSH2 (0x1 << 2) // (PWMC) Output Selection for PWMH output of the channel 2 02980 #define AT91C_PWMC_OSH3 (0x1 << 3) // (PWMC) Output Selection for PWMH output of the channel 3 02981 #define AT91C_PWMC_OSH4 (0x1 << 4) // (PWMC) Output Selection for PWMH output of the channel 4 02982 #define AT91C_PWMC_OSH5 (0x1 << 5) // (PWMC) Output Selection for PWMH output of the channel 5 02983 #define AT91C_PWMC_OSH6 (0x1 << 6) // (PWMC) Output Selection for PWMH output of the channel 6 02984 #define AT91C_PWMC_OSH7 (0x1 << 7) // (PWMC) Output Selection for PWMH output of the channel 7 02985 #define AT91C_PWMC_OSH8 (0x1 << 8) // (PWMC) Output Selection for PWMH output of the channel 8 02986 #define AT91C_PWMC_OSH9 (0x1 << 9) // (PWMC) Output Selection for PWMH output of the channel 9 02987 #define AT91C_PWMC_OSH10 (0x1 << 10) // (PWMC) Output Selection for PWMH output of the channel 10 02988 #define AT91C_PWMC_OSH11 (0x1 << 11) // (PWMC) Output Selection for PWMH output of the channel 11 02989 #define AT91C_PWMC_OSH12 (0x1 << 12) // (PWMC) Output Selection for PWMH output of the channel 12 02990 #define AT91C_PWMC_OSH13 (0x1 << 13) // (PWMC) Output Selection for PWMH output of the channel 13 02991 #define AT91C_PWMC_OSH14 (0x1 << 14) // (PWMC) Output Selection for PWMH output of the channel 14 02992 #define AT91C_PWMC_OSH15 (0x1 << 15) // (PWMC) Output Selection for PWMH output of the channel 15 02993 #define AT91C_PWMC_OSL0 (0x1 << 16) // (PWMC) Output Selection for PWML output of the channel 0 02994 #define AT91C_PWMC_OSL1 (0x1 << 17) // (PWMC) Output Selection for PWML output of the channel 1 02995 #define AT91C_PWMC_OSL2 (0x1 << 18) // (PWMC) Output Selection for PWML output of the channel 2 02996 #define AT91C_PWMC_OSL3 (0x1 << 19) // (PWMC) Output Selection for PWML output of the channel 3 02997 #define AT91C_PWMC_OSL4 (0x1 << 20) // (PWMC) Output Selection for PWML output of the channel 4 02998 #define AT91C_PWMC_OSL5 (0x1 << 21) // (PWMC) Output Selection for PWML output of the channel 5 02999 #define AT91C_PWMC_OSL6 (0x1 << 22) // (PWMC) Output Selection for PWML output of the channel 6 03000 #define AT91C_PWMC_OSL7 (0x1 << 23) // (PWMC) Output Selection for PWML output of the channel 7 03001 #define AT91C_PWMC_OSL8 (0x1 << 24) // (PWMC) Output Selection for PWML output of the channel 8 03002 #define AT91C_PWMC_OSL9 (0x1 << 25) // (PWMC) Output Selection for PWML output of the channel 9 03003 #define AT91C_PWMC_OSL10 (0x1 << 26) // (PWMC) Output Selection for PWML output of the channel 10 03004 #define AT91C_PWMC_OSL11 (0x1 << 27) // (PWMC) Output Selection for PWML output of the channel 11 03005 #define AT91C_PWMC_OSL12 (0x1 << 28) // (PWMC) Output Selection for PWML output of the channel 12 03006 #define AT91C_PWMC_OSL13 (0x1 << 29) // (PWMC) Output Selection for PWML output of the channel 13 03007 #define AT91C_PWMC_OSL14 (0x1 << 30) // (PWMC) Output Selection for PWML output of the channel 14 03008 #define AT91C_PWMC_OSL15 (0x1 << 31) // (PWMC) Output Selection for PWML output of the channel 15 03009 // -------- PWMC_OSS : (PWMC Offset: 0x4c) PWM Output Selection Set Register -------- 03010 #define AT91C_PWMC_OSSH0 (0x1 << 0) // (PWMC) Output Selection Set for PWMH output of the channel 0 03011 #define AT91C_PWMC_OSSH1 (0x1 << 1) // (PWMC) Output Selection Set for PWMH output of the channel 1 03012 #define AT91C_PWMC_OSSH2 (0x1 << 2) // (PWMC) Output Selection Set for PWMH output of the channel 2 03013 #define AT91C_PWMC_OSSH3 (0x1 << 3) // (PWMC) Output Selection Set for PWMH output of the channel 3 03014 #define AT91C_PWMC_OSSH4 (0x1 << 4) // (PWMC) Output Selection Set for PWMH output of the channel 4 03015 #define AT91C_PWMC_OSSH5 (0x1 << 5) // (PWMC) Output Selection Set for PWMH output of the channel 5 03016 #define AT91C_PWMC_OSSH6 (0x1 << 6) // (PWMC) Output Selection Set for PWMH output of the channel 6 03017 #define AT91C_PWMC_OSSH7 (0x1 << 7) // (PWMC) Output Selection Set for PWMH output of the channel 7 03018 #define AT91C_PWMC_OSSH8 (0x1 << 8) // (PWMC) Output Selection Set for PWMH output of the channel 8 03019 #define AT91C_PWMC_OSSH9 (0x1 << 9) // (PWMC) Output Selection Set for PWMH output of the channel 9 03020 #define AT91C_PWMC_OSSH10 (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10 03021 #define AT91C_PWMC_OSSH11 (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11 03022 #define AT91C_PWMC_OSSH12 (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12 03023 #define AT91C_PWMC_OSSH13 (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13 03024 #define AT91C_PWMC_OSSH14 (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14 03025 #define AT91C_PWMC_OSSH15 (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15 03026 #define AT91C_PWMC_OSSL0 (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0 03027 #define AT91C_PWMC_OSSL1 (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1 03028 #define AT91C_PWMC_OSSL2 (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2 03029 #define AT91C_PWMC_OSSL3 (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3 03030 #define AT91C_PWMC_OSSL4 (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4 03031 #define AT91C_PWMC_OSSL5 (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5 03032 #define AT91C_PWMC_OSSL6 (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6 03033 #define AT91C_PWMC_OSSL7 (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7 03034 #define AT91C_PWMC_OSSL8 (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8 03035 #define AT91C_PWMC_OSSL9 (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9 03036 #define AT91C_PWMC_OSSL10 (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10 03037 #define AT91C_PWMC_OSSL11 (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11 03038 #define AT91C_PWMC_OSSL12 (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12 03039 #define AT91C_PWMC_OSSL13 (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13 03040 #define AT91C_PWMC_OSSL14 (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14 03041 #define AT91C_PWMC_OSSL15 (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15 03042 // -------- PWMC_OSC : (PWMC Offset: 0x50) PWM Output Selection Clear Register -------- 03043 #define AT91C_PWMC_OSCH0 (0x1 << 0) // (PWMC) Output Selection Clear for PWMH output of the channel 0 03044 #define AT91C_PWMC_OSCH1 (0x1 << 1) // (PWMC) Output Selection Clear for PWMH output of the channel 1 03045 #define AT91C_PWMC_OSCH2 (0x1 << 2) // (PWMC) Output Selection Clear for PWMH output of the channel 2 03046 #define AT91C_PWMC_OSCH3 (0x1 << 3) // (PWMC) Output Selection Clear for PWMH output of the channel 3 03047 #define AT91C_PWMC_OSCH4 (0x1 << 4) // (PWMC) Output Selection Clear for PWMH output of the channel 4 03048 #define AT91C_PWMC_OSCH5 (0x1 << 5) // (PWMC) Output Selection Clear for PWMH output of the channel 5 03049 #define AT91C_PWMC_OSCH6 (0x1 << 6) // (PWMC) Output Selection Clear for PWMH output of the channel 6 03050 #define AT91C_PWMC_OSCH7 (0x1 << 7) // (PWMC) Output Selection Clear for PWMH output of the channel 7 03051 #define AT91C_PWMC_OSCH8 (0x1 << 8) // (PWMC) Output Selection Clear for PWMH output of the channel 8 03052 #define AT91C_PWMC_OSCH9 (0x1 << 9) // (PWMC) Output Selection Clear for PWMH output of the channel 9 03053 #define AT91C_PWMC_OSCH10 (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10 03054 #define AT91C_PWMC_OSCH11 (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11 03055 #define AT91C_PWMC_OSCH12 (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12 03056 #define AT91C_PWMC_OSCH13 (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13 03057 #define AT91C_PWMC_OSCH14 (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14 03058 #define AT91C_PWMC_OSCH15 (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15 03059 #define AT91C_PWMC_OSCL0 (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0 03060 #define AT91C_PWMC_OSCL1 (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1 03061 #define AT91C_PWMC_OSCL2 (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2 03062 #define AT91C_PWMC_OSCL3 (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3 03063 #define AT91C_PWMC_OSCL4 (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4 03064 #define AT91C_PWMC_OSCL5 (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5 03065 #define AT91C_PWMC_OSCL6 (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6 03066 #define AT91C_PWMC_OSCL7 (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7 03067 #define AT91C_PWMC_OSCL8 (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8 03068 #define AT91C_PWMC_OSCL9 (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9 03069 #define AT91C_PWMC_OSCL10 (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10 03070 #define AT91C_PWMC_OSCL11 (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11 03071 #define AT91C_PWMC_OSCL12 (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12 03072 #define AT91C_PWMC_OSCL13 (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13 03073 #define AT91C_PWMC_OSCL14 (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14 03074 #define AT91C_PWMC_OSCL15 (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15 03075 // -------- PWMC_OSSUPD : (PWMC Offset: 0x54) Output Selection Set for PWMH / PWML output of the channel x -------- 03076 #define AT91C_PWMC_OSSUPDH0 (0x1 << 0) // (PWMC) Output Selection Set for PWMH output of the channel 0 03077 #define AT91C_PWMC_OSSUPDH1 (0x1 << 1) // (PWMC) Output Selection Set for PWMH output of the channel 1 03078 #define AT91C_PWMC_OSSUPDH2 (0x1 << 2) // (PWMC) Output Selection Set for PWMH output of the channel 2 03079 #define AT91C_PWMC_OSSUPDH3 (0x1 << 3) // (PWMC) Output Selection Set for PWMH output of the channel 3 03080 #define AT91C_PWMC_OSSUPDH4 (0x1 << 4) // (PWMC) Output Selection Set for PWMH output of the channel 4 03081 #define AT91C_PWMC_OSSUPDH5 (0x1 << 5) // (PWMC) Output Selection Set for PWMH output of the channel 5 03082 #define AT91C_PWMC_OSSUPDH6 (0x1 << 6) // (PWMC) Output Selection Set for PWMH output of the channel 6 03083 #define AT91C_PWMC_OSSUPDH7 (0x1 << 7) // (PWMC) Output Selection Set for PWMH output of the channel 7 03084 #define AT91C_PWMC_OSSUPDH8 (0x1 << 8) // (PWMC) Output Selection Set for PWMH output of the channel 8 03085 #define AT91C_PWMC_OSSUPDH9 (0x1 << 9) // (PWMC) Output Selection Set for PWMH output of the channel 9 03086 #define AT91C_PWMC_OSSUPDH10 (0x1 << 10) // (PWMC) Output Selection Set for PWMH output of the channel 10 03087 #define AT91C_PWMC_OSSUPDH11 (0x1 << 11) // (PWMC) Output Selection Set for PWMH output of the channel 11 03088 #define AT91C_PWMC_OSSUPDH12 (0x1 << 12) // (PWMC) Output Selection Set for PWMH output of the channel 12 03089 #define AT91C_PWMC_OSSUPDH13 (0x1 << 13) // (PWMC) Output Selection Set for PWMH output of the channel 13 03090 #define AT91C_PWMC_OSSUPDH14 (0x1 << 14) // (PWMC) Output Selection Set for PWMH output of the channel 14 03091 #define AT91C_PWMC_OSSUPDH15 (0x1 << 15) // (PWMC) Output Selection Set for PWMH output of the channel 15 03092 #define AT91C_PWMC_OSSUPDL0 (0x1 << 16) // (PWMC) Output Selection Set for PWML output of the channel 0 03093 #define AT91C_PWMC_OSSUPDL1 (0x1 << 17) // (PWMC) Output Selection Set for PWML output of the channel 1 03094 #define AT91C_PWMC_OSSUPDL2 (0x1 << 18) // (PWMC) Output Selection Set for PWML output of the channel 2 03095 #define AT91C_PWMC_OSSUPDL3 (0x1 << 19) // (PWMC) Output Selection Set for PWML output of the channel 3 03096 #define AT91C_PWMC_OSSUPDL4 (0x1 << 20) // (PWMC) Output Selection Set for PWML output of the channel 4 03097 #define AT91C_PWMC_OSSUPDL5 (0x1 << 21) // (PWMC) Output Selection Set for PWML output of the channel 5 03098 #define AT91C_PWMC_OSSUPDL6 (0x1 << 22) // (PWMC) Output Selection Set for PWML output of the channel 6 03099 #define AT91C_PWMC_OSSUPDL7 (0x1 << 23) // (PWMC) Output Selection Set for PWML output of the channel 7 03100 #define AT91C_PWMC_OSSUPDL8 (0x1 << 24) // (PWMC) Output Selection Set for PWML output of the channel 8 03101 #define AT91C_PWMC_OSSUPDL9 (0x1 << 25) // (PWMC) Output Selection Set for PWML output of the channel 9 03102 #define AT91C_PWMC_OSSUPDL10 (0x1 << 26) // (PWMC) Output Selection Set for PWML output of the channel 10 03103 #define AT91C_PWMC_OSSUPDL11 (0x1 << 27) // (PWMC) Output Selection Set for PWML output of the channel 11 03104 #define AT91C_PWMC_OSSUPDL12 (0x1 << 28) // (PWMC) Output Selection Set for PWML output of the channel 12 03105 #define AT91C_PWMC_OSSUPDL13 (0x1 << 29) // (PWMC) Output Selection Set for PWML output of the channel 13 03106 #define AT91C_PWMC_OSSUPDL14 (0x1 << 30) // (PWMC) Output Selection Set for PWML output of the channel 14 03107 #define AT91C_PWMC_OSSUPDL15 (0x1 << 31) // (PWMC) Output Selection Set for PWML output of the channel 15 03108 // -------- PWMC_OSCUPD : (PWMC Offset: 0x58) Output Selection Clear for PWMH / PWML output of the channel x -------- 03109 #define AT91C_PWMC_OSCUPDH0 (0x1 << 0) // (PWMC) Output Selection Clear for PWMH output of the channel 0 03110 #define AT91C_PWMC_OSCUPDH1 (0x1 << 1) // (PWMC) Output Selection Clear for PWMH output of the channel 1 03111 #define AT91C_PWMC_OSCUPDH2 (0x1 << 2) // (PWMC) Output Selection Clear for PWMH output of the channel 2 03112 #define AT91C_PWMC_OSCUPDH3 (0x1 << 3) // (PWMC) Output Selection Clear for PWMH output of the channel 3 03113 #define AT91C_PWMC_OSCUPDH4 (0x1 << 4) // (PWMC) Output Selection Clear for PWMH output of the channel 4 03114 #define AT91C_PWMC_OSCUPDH5 (0x1 << 5) // (PWMC) Output Selection Clear for PWMH output of the channel 5 03115 #define AT91C_PWMC_OSCUPDH6 (0x1 << 6) // (PWMC) Output Selection Clear for PWMH output of the channel 6 03116 #define AT91C_PWMC_OSCUPDH7 (0x1 << 7) // (PWMC) Output Selection Clear for PWMH output of the channel 7 03117 #define AT91C_PWMC_OSCUPDH8 (0x1 << 8) // (PWMC) Output Selection Clear for PWMH output of the channel 8 03118 #define AT91C_PWMC_OSCUPDH9 (0x1 << 9) // (PWMC) Output Selection Clear for PWMH output of the channel 9 03119 #define AT91C_PWMC_OSCUPDH10 (0x1 << 10) // (PWMC) Output Selection Clear for PWMH output of the channel 10 03120 #define AT91C_PWMC_OSCUPDH11 (0x1 << 11) // (PWMC) Output Selection Clear for PWMH output of the channel 11 03121 #define AT91C_PWMC_OSCUPDH12 (0x1 << 12) // (PWMC) Output Selection Clear for PWMH output of the channel 12 03122 #define AT91C_PWMC_OSCUPDH13 (0x1 << 13) // (PWMC) Output Selection Clear for PWMH output of the channel 13 03123 #define AT91C_PWMC_OSCUPDH14 (0x1 << 14) // (PWMC) Output Selection Clear for PWMH output of the channel 14 03124 #define AT91C_PWMC_OSCUPDH15 (0x1 << 15) // (PWMC) Output Selection Clear for PWMH output of the channel 15 03125 #define AT91C_PWMC_OSCUPDL0 (0x1 << 16) // (PWMC) Output Selection Clear for PWML output of the channel 0 03126 #define AT91C_PWMC_OSCUPDL1 (0x1 << 17) // (PWMC) Output Selection Clear for PWML output of the channel 1 03127 #define AT91C_PWMC_OSCUPDL2 (0x1 << 18) // (PWMC) Output Selection Clear for PWML output of the channel 2 03128 #define AT91C_PWMC_OSCUPDL3 (0x1 << 19) // (PWMC) Output Selection Clear for PWML output of the channel 3 03129 #define AT91C_PWMC_OSCUPDL4 (0x1 << 20) // (PWMC) Output Selection Clear for PWML output of the channel 4 03130 #define AT91C_PWMC_OSCUPDL5 (0x1 << 21) // (PWMC) Output Selection Clear for PWML output of the channel 5 03131 #define AT91C_PWMC_OSCUPDL6 (0x1 << 22) // (PWMC) Output Selection Clear for PWML output of the channel 6 03132 #define AT91C_PWMC_OSCUPDL7 (0x1 << 23) // (PWMC) Output Selection Clear for PWML output of the channel 7 03133 #define AT91C_PWMC_OSCUPDL8 (0x1 << 24) // (PWMC) Output Selection Clear for PWML output of the channel 8 03134 #define AT91C_PWMC_OSCUPDL9 (0x1 << 25) // (PWMC) Output Selection Clear for PWML output of the channel 9 03135 #define AT91C_PWMC_OSCUPDL10 (0x1 << 26) // (PWMC) Output Selection Clear for PWML output of the channel 10 03136 #define AT91C_PWMC_OSCUPDL11 (0x1 << 27) // (PWMC) Output Selection Clear for PWML output of the channel 11 03137 #define AT91C_PWMC_OSCUPDL12 (0x1 << 28) // (PWMC) Output Selection Clear for PWML output of the channel 12 03138 #define AT91C_PWMC_OSCUPDL13 (0x1 << 29) // (PWMC) Output Selection Clear for PWML output of the channel 13 03139 #define AT91C_PWMC_OSCUPDL14 (0x1 << 30) // (PWMC) Output Selection Clear for PWML output of the channel 14 03140 #define AT91C_PWMC_OSCUPDL15 (0x1 << 31) // (PWMC) Output Selection Clear for PWML output of the channel 15 03141 // -------- PWMC_FMR : (PWMC Offset: 0x5c) PWM Fault Mode Register -------- 03142 #define AT91C_PWMC_FPOL0 (0x1 << 0) // (PWMC) Fault Polarity on fault input 0 03143 #define AT91C_PWMC_FPOL1 (0x1 << 1) // (PWMC) Fault Polarity on fault input 1 03144 #define AT91C_PWMC_FPOL2 (0x1 << 2) // (PWMC) Fault Polarity on fault input 2 03145 #define AT91C_PWMC_FPOL3 (0x1 << 3) // (PWMC) Fault Polarity on fault input 3 03146 #define AT91C_PWMC_FPOL4 (0x1 << 4) // (PWMC) Fault Polarity on fault input 4 03147 #define AT91C_PWMC_FPOL5 (0x1 << 5) // (PWMC) Fault Polarity on fault input 5 03148 #define AT91C_PWMC_FPOL6 (0x1 << 6) // (PWMC) Fault Polarity on fault input 6 03149 #define AT91C_PWMC_FPOL7 (0x1 << 7) // (PWMC) Fault Polarity on fault input 7 03150 #define AT91C_PWMC_FMOD0 (0x1 << 8) // (PWMC) Fault Activation Mode on fault input 0 03151 #define AT91C_PWMC_FMOD1 (0x1 << 9) // (PWMC) Fault Activation Mode on fault input 1 03152 #define AT91C_PWMC_FMOD2 (0x1 << 10) // (PWMC) Fault Activation Mode on fault input 2 03153 #define AT91C_PWMC_FMOD3 (0x1 << 11) // (PWMC) Fault Activation Mode on fault input 3 03154 #define AT91C_PWMC_FMOD4 (0x1 << 12) // (PWMC) Fault Activation Mode on fault input 4 03155 #define AT91C_PWMC_FMOD5 (0x1 << 13) // (PWMC) Fault Activation Mode on fault input 5 03156 #define AT91C_PWMC_FMOD6 (0x1 << 14) // (PWMC) Fault Activation Mode on fault input 6 03157 #define AT91C_PWMC_FMOD7 (0x1 << 15) // (PWMC) Fault Activation Mode on fault input 7 03158 #define AT91C_PWMC_FFIL00 (0x1 << 16) // (PWMC) Fault Filtering on fault input 0 03159 #define AT91C_PWMC_FFIL01 (0x1 << 17) // (PWMC) Fault Filtering on fault input 1 03160 #define AT91C_PWMC_FFIL02 (0x1 << 18) // (PWMC) Fault Filtering on fault input 2 03161 #define AT91C_PWMC_FFIL03 (0x1 << 19) // (PWMC) Fault Filtering on fault input 3 03162 #define AT91C_PWMC_FFIL04 (0x1 << 20) // (PWMC) Fault Filtering on fault input 4 03163 #define AT91C_PWMC_FFIL05 (0x1 << 21) // (PWMC) Fault Filtering on fault input 5 03164 #define AT91C_PWMC_FFIL06 (0x1 << 22) // (PWMC) Fault Filtering on fault input 6 03165 #define AT91C_PWMC_FFIL07 (0x1 << 23) // (PWMC) Fault Filtering on fault input 7 03166 // -------- PWMC_FSR : (PWMC Offset: 0x60) Fault Input x Value -------- 03167 #define AT91C_PWMC_FIV0 (0x1 << 0) // (PWMC) Fault Input 0 Value 03168 #define AT91C_PWMC_FIV1 (0x1 << 1) // (PWMC) Fault Input 1 Value 03169 #define AT91C_PWMC_FIV2 (0x1 << 2) // (PWMC) Fault Input 2 Value 03170 #define AT91C_PWMC_FIV3 (0x1 << 3) // (PWMC) Fault Input 3 Value 03171 #define AT91C_PWMC_FIV4 (0x1 << 4) // (PWMC) Fault Input 4 Value 03172 #define AT91C_PWMC_FIV5 (0x1 << 5) // (PWMC) Fault Input 5 Value 03173 #define AT91C_PWMC_FIV6 (0x1 << 6) // (PWMC) Fault Input 6 Value 03174 #define AT91C_PWMC_FIV7 (0x1 << 7) // (PWMC) Fault Input 7 Value 03175 #define AT91C_PWMC_FS0 (0x1 << 8) // (PWMC) Fault 0 Status 03176 #define AT91C_PWMC_FS1 (0x1 << 9) // (PWMC) Fault 1 Status 03177 #define AT91C_PWMC_FS2 (0x1 << 10) // (PWMC) Fault 2 Status 03178 #define AT91C_PWMC_FS3 (0x1 << 11) // (PWMC) Fault 3 Status 03179 #define AT91C_PWMC_FS4 (0x1 << 12) // (PWMC) Fault 4 Status 03180 #define AT91C_PWMC_FS5 (0x1 << 13) // (PWMC) Fault 5 Status 03181 #define AT91C_PWMC_FS6 (0x1 << 14) // (PWMC) Fault 6 Status 03182 #define AT91C_PWMC_FS7 (0x1 << 15) // (PWMC) Fault 7 Status 03183 // -------- PWMC_FCR : (PWMC Offset: 0x64) Fault y Clear -------- 03184 #define AT91C_PWMC_FCLR0 (0x1 << 0) // (PWMC) Fault 0 Clear 03185 #define AT91C_PWMC_FCLR1 (0x1 << 1) // (PWMC) Fault 1 Clear 03186 #define AT91C_PWMC_FCLR2 (0x1 << 2) // (PWMC) Fault 2 Clear 03187 #define AT91C_PWMC_FCLR3 (0x1 << 3) // (PWMC) Fault 3 Clear 03188 #define AT91C_PWMC_FCLR4 (0x1 << 4) // (PWMC) Fault 4 Clear 03189 #define AT91C_PWMC_FCLR5 (0x1 << 5) // (PWMC) Fault 5 Clear 03190 #define AT91C_PWMC_FCLR6 (0x1 << 6) // (PWMC) Fault 6 Clear 03191 #define AT91C_PWMC_FCLR7 (0x1 << 7) // (PWMC) Fault 7 Clear 03192 // -------- PWMC_FPV : (PWMC Offset: 0x68) PWM Fault Protection Value -------- 03193 #define AT91C_PWMC_FPVH0 (0x1 << 0) // (PWMC) Fault Protection Value for PWMH output on channel 0 03194 #define AT91C_PWMC_FPVH1 (0x1 << 1) // (PWMC) Fault Protection Value for PWMH output on channel 1 03195 #define AT91C_PWMC_FPVH2 (0x1 << 2) // (PWMC) Fault Protection Value for PWMH output on channel 2 03196 #define AT91C_PWMC_FPVH3 (0x1 << 3) // (PWMC) Fault Protection Value for PWMH output on channel 3 03197 #define AT91C_PWMC_FPVH4 (0x1 << 4) // (PWMC) Fault Protection Value for PWMH output on channel 4 03198 #define AT91C_PWMC_FPVH5 (0x1 << 5) // (PWMC) Fault Protection Value for PWMH output on channel 5 03199 #define AT91C_PWMC_FPVH6 (0x1 << 6) // (PWMC) Fault Protection Value for PWMH output on channel 6 03200 #define AT91C_PWMC_FPVH7 (0x1 << 7) // (PWMC) Fault Protection Value for PWMH output on channel 7 03201 #define AT91C_PWMC_FPVL0 (0x1 << 16) // (PWMC) Fault Protection Value for PWML output on channel 0 03202 #define AT91C_PWMC_FPVL1 (0x1 << 17) // (PWMC) Fault Protection Value for PWML output on channel 1 03203 #define AT91C_PWMC_FPVL2 (0x1 << 18) // (PWMC) Fault Protection Value for PWML output on channel 2 03204 #define AT91C_PWMC_FPVL3 (0x1 << 19) // (PWMC) Fault Protection Value for PWML output on channel 3 03205 #define AT91C_PWMC_FPVL4 (0x1 << 20) // (PWMC) Fault Protection Value for PWML output on channel 4 03206 #define AT91C_PWMC_FPVL5 (0x1 << 21) // (PWMC) Fault Protection Value for PWML output on channel 5 03207 #define AT91C_PWMC_FPVL6 (0x1 << 22) // (PWMC) Fault Protection Value for PWML output on channel 6 03208 #define AT91C_PWMC_FPVL7 (0x1 << 23) // (PWMC) Fault Protection Value for PWML output on channel 7 03209 // -------- PWMC_FPER1 : (PWMC Offset: 0x6c) PWM Fault Protection Enable Register 1 -------- 03210 #define AT91C_PWMC_FPE0 (0xFF << 0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 0 03211 #define AT91C_PWMC_FPE1 (0xFF << 8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 1 03212 #define AT91C_PWMC_FPE2 (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 2 03213 #define AT91C_PWMC_FPE3 (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 3 03214 // -------- PWMC_FPER2 : (PWMC Offset: 0x70) PWM Fault Protection Enable Register 2 -------- 03215 #define AT91C_PWMC_FPE4 (0xFF << 0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 4 03216 #define AT91C_PWMC_FPE5 (0xFF << 8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 5 03217 #define AT91C_PWMC_FPE6 (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 6 03218 #define AT91C_PWMC_FPE7 (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 7 03219 // -------- PWMC_FPER3 : (PWMC Offset: 0x74) PWM Fault Protection Enable Register 3 -------- 03220 #define AT91C_PWMC_FPE8 (0xFF << 0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 8 03221 #define AT91C_PWMC_FPE9 (0xFF << 8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 9 03222 #define AT91C_PWMC_FPE10 (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 10 03223 #define AT91C_PWMC_FPE11 (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 11 03224 // -------- PWMC_FPER4 : (PWMC Offset: 0x78) PWM Fault Protection Enable Register 4 -------- 03225 #define AT91C_PWMC_FPE12 (0xFF << 0) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 12 03226 #define AT91C_PWMC_FPE13 (0xFF << 8) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 13 03227 #define AT91C_PWMC_FPE14 (0xFF << 16) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 14 03228 #define AT91C_PWMC_FPE15 (0xFF << 24) // (PWMC) Fault Protection Enable with Fault Input y for PWM channel 15 03229 // -------- PWMC_EL0MR : (PWMC Offset: 0x7c) PWM Event Line 0 Mode Register -------- 03230 #define AT91C_PWMC_L0CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03231 #define AT91C_PWMC_L0CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03232 #define AT91C_PWMC_L0CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03233 #define AT91C_PWMC_L0CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03234 #define AT91C_PWMC_L0CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03235 #define AT91C_PWMC_L0CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03236 #define AT91C_PWMC_L0CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03237 #define AT91C_PWMC_L0CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03238 // -------- PWMC_EL1MR : (PWMC Offset: 0x80) PWM Event Line 1 Mode Register -------- 03239 #define AT91C_PWMC_L1CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03240 #define AT91C_PWMC_L1CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03241 #define AT91C_PWMC_L1CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03242 #define AT91C_PWMC_L1CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03243 #define AT91C_PWMC_L1CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03244 #define AT91C_PWMC_L1CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03245 #define AT91C_PWMC_L1CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03246 #define AT91C_PWMC_L1CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03247 // -------- PWMC_EL2MR : (PWMC Offset: 0x84) PWM Event line 2 Mode Register -------- 03248 #define AT91C_PWMC_L2CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03249 #define AT91C_PWMC_L2CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03250 #define AT91C_PWMC_L2CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03251 #define AT91C_PWMC_L2CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03252 #define AT91C_PWMC_L2CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03253 #define AT91C_PWMC_L2CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03254 #define AT91C_PWMC_L2CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03255 #define AT91C_PWMC_L2CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03256 // -------- PWMC_EL3MR : (PWMC Offset: 0x88) PWM Event line 3 Mode Register -------- 03257 #define AT91C_PWMC_L3CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03258 #define AT91C_PWMC_L3CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03259 #define AT91C_PWMC_L3CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03260 #define AT91C_PWMC_L3CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03261 #define AT91C_PWMC_L3CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03262 #define AT91C_PWMC_L3CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03263 #define AT91C_PWMC_L3CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03264 #define AT91C_PWMC_L3CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03265 // -------- PWMC_EL4MR : (PWMC Offset: 0x8c) PWM Event line 4 Mode Register -------- 03266 #define AT91C_PWMC_L4CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03267 #define AT91C_PWMC_L4CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03268 #define AT91C_PWMC_L4CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03269 #define AT91C_PWMC_L4CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03270 #define AT91C_PWMC_L4CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03271 #define AT91C_PWMC_L4CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03272 #define AT91C_PWMC_L4CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03273 #define AT91C_PWMC_L4CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03274 // -------- PWMC_EL5MR : (PWMC Offset: 0x90) PWM Event line 5 Mode Register -------- 03275 #define AT91C_PWMC_L5CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03276 #define AT91C_PWMC_L5CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03277 #define AT91C_PWMC_L5CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03278 #define AT91C_PWMC_L5CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03279 #define AT91C_PWMC_L5CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03280 #define AT91C_PWMC_L5CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03281 #define AT91C_PWMC_L5CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03282 #define AT91C_PWMC_L5CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03283 // -------- PWMC_EL6MR : (PWMC Offset: 0x94) PWM Event line 6 Mode Register -------- 03284 #define AT91C_PWMC_L6CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03285 #define AT91C_PWMC_L6CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03286 #define AT91C_PWMC_L6CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03287 #define AT91C_PWMC_L6CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03288 #define AT91C_PWMC_L6CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03289 #define AT91C_PWMC_L6CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03290 #define AT91C_PWMC_L6CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03291 #define AT91C_PWMC_L6CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03292 // -------- PWMC_EL7MR : (PWMC Offset: 0x98) PWM Event line 7 Mode Register -------- 03293 #define AT91C_PWMC_L7CSEL0 (0x1 << 0) // (PWMC) Comparison 0 Selection 03294 #define AT91C_PWMC_L7CSEL1 (0x1 << 1) // (PWMC) Comparison 1 Selection 03295 #define AT91C_PWMC_L7CSEL2 (0x1 << 2) // (PWMC) Comparison 2 Selection 03296 #define AT91C_PWMC_L7CSEL3 (0x1 << 3) // (PWMC) Comparison 3 Selection 03297 #define AT91C_PWMC_L7CSEL4 (0x1 << 4) // (PWMC) Comparison 4 Selection 03298 #define AT91C_PWMC_L7CSEL5 (0x1 << 5) // (PWMC) Comparison 5 Selection 03299 #define AT91C_PWMC_L7CSEL6 (0x1 << 6) // (PWMC) Comparison 6 Selection 03300 #define AT91C_PWMC_L7CSEL7 (0x1 << 7) // (PWMC) Comparison 7 Selection 03301 // -------- PWMC_WPCR : (PWMC Offset: 0xe4) PWM Write Protection Control Register -------- 03302 #define AT91C_PWMC_WPCMD (0x3 << 0) // (PWMC) Write Protection Command 03303 #define AT91C_PWMC_WPRG0 (0x1 << 2) // (PWMC) Write Protect Register Group 0 03304 #define AT91C_PWMC_WPRG1 (0x1 << 3) // (PWMC) Write Protect Register Group 1 03305 #define AT91C_PWMC_WPRG2 (0x1 << 4) // (PWMC) Write Protect Register Group 2 03306 #define AT91C_PWMC_WPRG3 (0x1 << 5) // (PWMC) Write Protect Register Group 3 03307 #define AT91C_PWMC_WPRG4 (0x1 << 6) // (PWMC) Write Protect Register Group 4 03308 #define AT91C_PWMC_WPRG5 (0x1 << 7) // (PWMC) Write Protect Register Group 5 03309 #define AT91C_PWMC_WPKEY (0xFFFFFF << 8) // (PWMC) Protection Password 03310 // -------- PWMC_WPVS : (PWMC Offset: 0xe8) Write Protection Status Register -------- 03311 #define AT91C_PWMC_WPSWS0 (0x1 << 0) // (PWMC) Write Protect SW Group 0 Status 03312 #define AT91C_PWMC_WPSWS1 (0x1 << 1) // (PWMC) Write Protect SW Group 1 Status 03313 #define AT91C_PWMC_WPSWS2 (0x1 << 2) // (PWMC) Write Protect SW Group 2 Status 03314 #define AT91C_PWMC_WPSWS3 (0x1 << 3) // (PWMC) Write Protect SW Group 3 Status 03315 #define AT91C_PWMC_WPSWS4 (0x1 << 4) // (PWMC) Write Protect SW Group 4 Status 03316 #define AT91C_PWMC_WPSWS5 (0x1 << 5) // (PWMC) Write Protect SW Group 5 Status 03317 #define AT91C_PWMC_WPVS (0x1 << 7) // (PWMC) Write Protection Enable 03318 #define AT91C_PWMC_WPHWS0 (0x1 << 8) // (PWMC) Write Protect HW Group 0 Status 03319 #define AT91C_PWMC_WPHWS1 (0x1 << 9) // (PWMC) Write Protect HW Group 1 Status 03320 #define AT91C_PWMC_WPHWS2 (0x1 << 10) // (PWMC) Write Protect HW Group 2 Status 03321 #define AT91C_PWMC_WPHWS3 (0x1 << 11) // (PWMC) Write Protect HW Group 3 Status 03322 #define AT91C_PWMC_WPHWS4 (0x1 << 12) // (PWMC) Write Protect HW Group 4 Status 03323 #define AT91C_PWMC_WPHWS5 (0x1 << 13) // (PWMC) Write Protect HW Group 5 Status 03324 #define AT91C_PWMC_WPVSRC (0xFFFF << 16) // (PWMC) Write Protection Violation Source 03325 // -------- PWMC_CMP0V : (PWMC Offset: 0x130) PWM Comparison Value 0 Register -------- 03326 #define AT91C_PWMC_CV (0xFFFFFF << 0) // (PWMC) PWM Comparison Value 0. 03327 #define AT91C_PWMC_CVM (0x1 << 24) // (PWMC) Comparison Value 0 Mode. 03328 // -------- PWMC_CMP0VUPD : (PWMC Offset: 0x134) PWM Comparison Value 0 Update Register -------- 03329 #define AT91C_PWMC_CVUPD (0xFFFFFF << 0) // (PWMC) PWM Comparison Value Update. 03330 #define AT91C_PWMC_CVMUPD (0x1 << 24) // (PWMC) Comparison Value Update Mode. 03331 // -------- PWMC_CMP0M : (PWMC Offset: 0x138) PWM Comparison 0 Mode Register -------- 03332 #define AT91C_PWMC_CEN (0x1 << 0) // (PWMC) Comparison Enable. 03333 #define AT91C_PWMC_CTR (0xF << 4) // (PWMC) PWM Comparison Trigger. 03334 #define AT91C_PWMC_CPR (0xF << 8) // (PWMC) PWM Comparison Period. 03335 #define AT91C_PWMC_CPRCNT (0xF << 12) // (PWMC) PWM Comparison Period Counter. 03336 #define AT91C_PWMC_CUPR (0xF << 16) // (PWMC) PWM Comparison Update Period. 03337 #define AT91C_PWMC_CUPRCNT (0xF << 20) // (PWMC) PWM Comparison Update Period Counter. 03338 // -------- PWMC_CMP0MUPD : (PWMC Offset: 0x13c) PWM Comparison 0 Mode Update Register -------- 03339 #define AT91C_PWMC_CENUPD (0x1 << 0) // (PWMC) Comparison Enable Update. 03340 #define AT91C_PWMC_CTRUPD (0xF << 4) // (PWMC) PWM Comparison Trigger Update. 03341 #define AT91C_PWMC_CPRUPD (0xF << 8) // (PWMC) PWM Comparison Period Update. 03342 #define AT91C_PWMC_CUPRUPD (0xF << 16) // (PWMC) PWM Comparison Update Period Update. 03343 // -------- PWMC_CMP1V : (PWMC Offset: 0x140) PWM Comparison Value 1 Register -------- 03344 // -------- PWMC_CMP1VUPD : (PWMC Offset: 0x144) PWM Comparison Value 1 Update Register -------- 03345 // -------- PWMC_CMP1M : (PWMC Offset: 0x148) PWM Comparison 1 Mode Register -------- 03346 // -------- PWMC_CMP1MUPD : (PWMC Offset: 0x14c) PWM Comparison 1 Mode Update Register -------- 03347 // -------- PWMC_CMP2V : (PWMC Offset: 0x150) PWM Comparison Value 2 Register -------- 03348 // -------- PWMC_CMP2VUPD : (PWMC Offset: 0x154) PWM Comparison Value 2 Update Register -------- 03349 // -------- PWMC_CMP2M : (PWMC Offset: 0x158) PWM Comparison 2 Mode Register -------- 03350 // -------- PWMC_CMP2MUPD : (PWMC Offset: 0x15c) PWM Comparison 2 Mode Update Register -------- 03351 // -------- PWMC_CMP3V : (PWMC Offset: 0x160) PWM Comparison Value 3 Register -------- 03352 // -------- PWMC_CMP3VUPD : (PWMC Offset: 0x164) PWM Comparison Value 3 Update Register -------- 03353 // -------- PWMC_CMP3M : (PWMC Offset: 0x168) PWM Comparison 3 Mode Register -------- 03354 // -------- PWMC_CMP3MUPD : (PWMC Offset: 0x16c) PWM Comparison 3 Mode Update Register -------- 03355 // -------- PWMC_CMP4V : (PWMC Offset: 0x170) PWM Comparison Value 4 Register -------- 03356 // -------- PWMC_CMP4VUPD : (PWMC Offset: 0x174) PWM Comparison Value 4 Update Register -------- 03357 // -------- PWMC_CMP4M : (PWMC Offset: 0x178) PWM Comparison 4 Mode Register -------- 03358 // -------- PWMC_CMP4MUPD : (PWMC Offset: 0x17c) PWM Comparison 4 Mode Update Register -------- 03359 // -------- PWMC_CMP5V : (PWMC Offset: 0x180) PWM Comparison Value 5 Register -------- 03360 // -------- PWMC_CMP5VUPD : (PWMC Offset: 0x184) PWM Comparison Value 5 Update Register -------- 03361 // -------- PWMC_CMP5M : (PWMC Offset: 0x188) PWM Comparison 5 Mode Register -------- 03362 // -------- PWMC_CMP5MUPD : (PWMC Offset: 0x18c) PWM Comparison 5 Mode Update Register -------- 03363 // -------- PWMC_CMP6V : (PWMC Offset: 0x190) PWM Comparison Value 6 Register -------- 03364 // -------- PWMC_CMP6VUPD : (PWMC Offset: 0x194) PWM Comparison Value 6 Update Register -------- 03365 // -------- PWMC_CMP6M : (PWMC Offset: 0x198) PWM Comparison 6 Mode Register -------- 03366 // -------- PWMC_CMP6MUPD : (PWMC Offset: 0x19c) PWM Comparison 6 Mode Update Register -------- 03367 // -------- PWMC_CMP7V : (PWMC Offset: 0x1a0) PWM Comparison Value 7 Register -------- 03368 // -------- PWMC_CMP7VUPD : (PWMC Offset: 0x1a4) PWM Comparison Value 7 Update Register -------- 03369 // -------- PWMC_CMP7M : (PWMC Offset: 0x1a8) PWM Comparison 7 Mode Register -------- 03370 // -------- PWMC_CMP7MUPD : (PWMC Offset: 0x1ac) PWM Comparison 7 Mode Update Register -------- 03371 03372 // ***************************************************************************** 03373 // SOFTWARE API DEFINITION FOR Serial Parallel Interface 03374 // ***************************************************************************** 03375 #ifndef __ASSEMBLY__ 03376 #else 03377 #define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register 03378 #define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register 03379 #define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register 03380 #define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register 03381 #define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register 03382 #define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register 03383 #define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register 03384 #define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register 03385 #define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register 03386 #define SPI_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (SPI_ADDRSIZE) SPI ADDRSIZE REGISTER 03387 #define SPI_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (SPI_IPNAME1) SPI IPNAME1 REGISTER 03388 #define SPI_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (SPI_IPNAME2) SPI IPNAME2 REGISTER 03389 #define SPI_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (SPI_FEATURES) SPI FEATURES REGISTER 03390 #define SPI_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (SPI_VER) Version Register 03391 03392 #endif 03393 // -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 03394 #define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable 03395 #define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable 03396 #define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset 03397 #define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer 03398 // -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 03399 #define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode 03400 #define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select 03401 #define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select 03402 #define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select 03403 #define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode 03404 #define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection 03405 #define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection 03406 #define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection 03407 #define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select 03408 #define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects 03409 // -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 03410 #define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data 03411 #define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status 03412 // -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 03413 #define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data 03414 #define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status 03415 // -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 03416 #define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full 03417 #define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty 03418 #define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error 03419 #define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status 03420 #define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer 03421 #define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer 03422 #define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt 03423 #define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt 03424 #define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt 03425 #define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt 03426 #define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status 03427 // -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 03428 // -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 03429 // -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 03430 // -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 03431 #define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity 03432 #define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase 03433 #define AT91C_SPI_CSNAAT (0x1 << 2) // (SPI) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 03434 #define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer 03435 #define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer 03436 #define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer 03437 #define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer 03438 #define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer 03439 #define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer 03440 #define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer 03441 #define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer 03442 #define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer 03443 #define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer 03444 #define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer 03445 #define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate 03446 #define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Serial Clock Baud Rate 03447 #define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers 03448 03449 // ***************************************************************************** 03450 // SOFTWARE API DEFINITION FOR UDPHS Enpoint FIFO data register 03451 // ***************************************************************************** 03452 #ifndef __ASSEMBLY__ 03453 typedef struct _AT91S_UDPHS_EPTFIFO { 03454 AT91_REG UDPHS_READEPT0[16384]; // FIFO Endpoint Data Register 0 03455 AT91_REG UDPHS_READEPT1[16384]; // FIFO Endpoint Data Register 1 03456 AT91_REG UDPHS_READEPT2[16384]; // FIFO Endpoint Data Register 2 03457 AT91_REG UDPHS_READEPT3[16384]; // FIFO Endpoint Data Register 3 03458 AT91_REG UDPHS_READEPT4[16384]; // FIFO Endpoint Data Register 4 03459 AT91_REG UDPHS_READEPT5[16384]; // FIFO Endpoint Data Register 5 03460 AT91_REG UDPHS_READEPT6[16384]; // FIFO Endpoint Data Register 6 03461 } AT91S_UDPHS_EPTFIFO, *AT91PS_UDPHS_EPTFIFO; 03462 #else 03463 #define UDPHS_READEPT0 (AT91_CAST(AT91_REG *) 0x00000000) // (UDPHS_READEPT0) FIFO Endpoint Data Register 0 03464 #define UDPHS_READEPT1 (AT91_CAST(AT91_REG *) 0x00010000) // (UDPHS_READEPT1) FIFO Endpoint Data Register 1 03465 #define UDPHS_READEPT2 (AT91_CAST(AT91_REG *) 0x00020000) // (UDPHS_READEPT2) FIFO Endpoint Data Register 2 03466 #define UDPHS_READEPT3 (AT91_CAST(AT91_REG *) 0x00030000) // (UDPHS_READEPT3) FIFO Endpoint Data Register 3 03467 #define UDPHS_READEPT4 (AT91_CAST(AT91_REG *) 0x00040000) // (UDPHS_READEPT4) FIFO Endpoint Data Register 4 03468 #define UDPHS_READEPT5 (AT91_CAST(AT91_REG *) 0x00050000) // (UDPHS_READEPT5) FIFO Endpoint Data Register 5 03469 #define UDPHS_READEPT6 (AT91_CAST(AT91_REG *) 0x00060000) // (UDPHS_READEPT6) FIFO Endpoint Data Register 6 03470 03471 #endif 03472 03473 // ***************************************************************************** 03474 // SOFTWARE API DEFINITION FOR UDPHS Endpoint struct 03475 // ***************************************************************************** 03476 #ifndef __ASSEMBLY__ 03477 typedef struct _AT91S_UDPHS_EPT { 03478 AT91_REG UDPHS_EPTCFG; // UDPHS Endpoint Config Register 03479 AT91_REG UDPHS_EPTCTLENB; // UDPHS Endpoint Control Enable Register 03480 AT91_REG UDPHS_EPTCTLDIS; // UDPHS Endpoint Control Disable Register 03481 AT91_REG UDPHS_EPTCTL; // UDPHS Endpoint Control Register 03482 AT91_REG Reserved0[1]; // 03483 AT91_REG UDPHS_EPTSETSTA; // UDPHS Endpoint Set Status Register 03484 AT91_REG UDPHS_EPTCLRSTA; // UDPHS Endpoint Clear Status Register 03485 AT91_REG UDPHS_EPTSTA; // UDPHS Endpoint Status Register 03486 } AT91S_UDPHS_EPT, *AT91PS_UDPHS_EPT; 03487 #else 03488 #define UDPHS_EPTCFG (AT91_CAST(AT91_REG *) 0x00000000) // (UDPHS_EPTCFG) UDPHS Endpoint Config Register 03489 #define UDPHS_EPTCTLENB (AT91_CAST(AT91_REG *) 0x00000004) // (UDPHS_EPTCTLENB) UDPHS Endpoint Control Enable Register 03490 #define UDPHS_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x00000008) // (UDPHS_EPTCTLDIS) UDPHS Endpoint Control Disable Register 03491 #define UDPHS_EPTCTL (AT91_CAST(AT91_REG *) 0x0000000C) // (UDPHS_EPTCTL) UDPHS Endpoint Control Register 03492 #define UDPHS_EPTSETSTA (AT91_CAST(AT91_REG *) 0x00000014) // (UDPHS_EPTSETSTA) UDPHS Endpoint Set Status Register 03493 #define UDPHS_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x00000018) // (UDPHS_EPTCLRSTA) UDPHS Endpoint Clear Status Register 03494 #define UDPHS_EPTSTA (AT91_CAST(AT91_REG *) 0x0000001C) // (UDPHS_EPTSTA) UDPHS Endpoint Status Register 03495 03496 #endif 03497 // -------- UDPHS_EPTCFG : (UDPHS_EPT Offset: 0x0) UDPHS Endpoint Config Register -------- 03498 #define AT91C_UDPHS_EPT_SIZE (0x7 << 0) // (UDPHS_EPT) Endpoint Size 03499 #define AT91C_UDPHS_EPT_SIZE_8 (0x0) // (UDPHS_EPT) 8 bytes 03500 #define AT91C_UDPHS_EPT_SIZE_16 (0x1) // (UDPHS_EPT) 16 bytes 03501 #define AT91C_UDPHS_EPT_SIZE_32 (0x2) // (UDPHS_EPT) 32 bytes 03502 #define AT91C_UDPHS_EPT_SIZE_64 (0x3) // (UDPHS_EPT) 64 bytes 03503 #define AT91C_UDPHS_EPT_SIZE_128 (0x4) // (UDPHS_EPT) 128 bytes 03504 #define AT91C_UDPHS_EPT_SIZE_256 (0x5) // (UDPHS_EPT) 256 bytes (if possible) 03505 #define AT91C_UDPHS_EPT_SIZE_512 (0x6) // (UDPHS_EPT) 512 bytes (if possible) 03506 #define AT91C_UDPHS_EPT_SIZE_1024 (0x7) // (UDPHS_EPT) 1024 bytes (if possible) 03507 #define AT91C_UDPHS_EPT_DIR (0x1 << 3) // (UDPHS_EPT) Endpoint Direction 0:OUT, 1:IN 03508 #define AT91C_UDPHS_EPT_DIR_OUT (0x0 << 3) // (UDPHS_EPT) Direction OUT 03509 #define AT91C_UDPHS_EPT_DIR_IN (0x1 << 3) // (UDPHS_EPT) Direction IN 03510 #define AT91C_UDPHS_EPT_TYPE (0x3 << 4) // (UDPHS_EPT) Endpoint Type 03511 #define AT91C_UDPHS_EPT_TYPE_CTL_EPT (0x0 << 4) // (UDPHS_EPT) Control endpoint 03512 #define AT91C_UDPHS_EPT_TYPE_ISO_EPT (0x1 << 4) // (UDPHS_EPT) Isochronous endpoint 03513 #define AT91C_UDPHS_EPT_TYPE_BUL_EPT (0x2 << 4) // (UDPHS_EPT) Bulk endpoint 03514 #define AT91C_UDPHS_EPT_TYPE_INT_EPT (0x3 << 4) // (UDPHS_EPT) Interrupt endpoint 03515 #define AT91C_UDPHS_BK_NUMBER (0x3 << 6) // (UDPHS_EPT) Number of Banks 03516 #define AT91C_UDPHS_BK_NUMBER_0 (0x0 << 6) // (UDPHS_EPT) Zero Bank, the EndPoint is not mapped in memory 03517 #define AT91C_UDPHS_BK_NUMBER_1 (0x1 << 6) // (UDPHS_EPT) One Bank (Bank0) 03518 #define AT91C_UDPHS_BK_NUMBER_2 (0x2 << 6) // (UDPHS_EPT) Double bank (Ping-Pong : Bank0 / Bank1) 03519 #define AT91C_UDPHS_BK_NUMBER_3 (0x3 << 6) // (UDPHS_EPT) Triple Bank (Bank0 / Bank1 / Bank2) (if possible) 03520 #define AT91C_UDPHS_NB_TRANS (0x3 << 8) // (UDPHS_EPT) Number Of Transaction per Micro-Frame (High-Bandwidth iso only) 03521 #define AT91C_UDPHS_EPT_MAPD (0x1 << 31) // (UDPHS_EPT) Endpoint Mapped (read only 03522 // -------- UDPHS_EPTCTLENB : (UDPHS_EPT Offset: 0x4) UDPHS Endpoint Control Enable Register -------- 03523 #define AT91C_UDPHS_EPT_ENABL (0x1 << 0) // (UDPHS_EPT) Endpoint Enable 03524 #define AT91C_UDPHS_AUTO_VALID (0x1 << 1) // (UDPHS_EPT) Packet Auto-Valid Enable/Disable 03525 #define AT91C_UDPHS_INTDIS_DMA (0x1 << 3) // (UDPHS_EPT) Endpoint Interrupts DMA Request Enable/Disable 03526 #define AT91C_UDPHS_NYET_DIS (0x1 << 4) // (UDPHS_EPT) NYET Enable/Disable 03527 #define AT91C_UDPHS_DATAX_RX (0x1 << 6) // (UDPHS_EPT) DATAx Interrupt Enable/Disable 03528 #define AT91C_UDPHS_MDATA_RX (0x1 << 7) // (UDPHS_EPT) MDATA Interrupt Enabled/Disable 03529 #define AT91C_UDPHS_ERR_OVFLW (0x1 << 8) // (UDPHS_EPT) OverFlow Error Interrupt Enable/Disable/Status 03530 #define AT91C_UDPHS_RX_BK_RDY (0x1 << 9) // (UDPHS_EPT) Received OUT Data 03531 #define AT91C_UDPHS_TX_COMPLT (0x1 << 10) // (UDPHS_EPT) Transmitted IN Data Complete Interrupt Enable/Disable or Transmitted IN Data Complete (clear) 03532 #define AT91C_UDPHS_ERR_TRANS (0x1 << 11) // (UDPHS_EPT) Transaction Error Interrupt Enable/Disable 03533 #define AT91C_UDPHS_TX_PK_RDY (0x1 << 11) // (UDPHS_EPT) TX Packet Ready Interrupt Enable/Disable 03534 #define AT91C_UDPHS_RX_SETUP (0x1 << 12) // (UDPHS_EPT) Received SETUP Interrupt Enable/Disable 03535 #define AT91C_UDPHS_ERR_FL_ISO (0x1 << 12) // (UDPHS_EPT) Error Flow Clear/Interrupt Enable/Disable 03536 #define AT91C_UDPHS_STALL_SNT (0x1 << 13) // (UDPHS_EPT) Stall Sent Clear 03537 #define AT91C_UDPHS_ERR_CRISO (0x1 << 13) // (UDPHS_EPT) CRC error / Error NB Trans / Interrupt Enable/Disable 03538 #define AT91C_UDPHS_NAK_IN (0x1 << 14) // (UDPHS_EPT) NAKIN ERROR FLUSH / Clear / Interrupt Enable/Disable 03539 #define AT91C_UDPHS_NAK_OUT (0x1 << 15) // (UDPHS_EPT) NAKOUT / Clear / Interrupt Enable/Disable 03540 #define AT91C_UDPHS_BUSY_BANK (0x1 << 18) // (UDPHS_EPT) Busy Bank Interrupt Enable/Disable 03541 #define AT91C_UDPHS_SHRT_PCKT (0x1 << 31) // (UDPHS_EPT) Short Packet / Interrupt Enable/Disable 03542 // -------- UDPHS_EPTCTLDIS : (UDPHS_EPT Offset: 0x8) UDPHS Endpoint Control Disable Register -------- 03543 #define AT91C_UDPHS_EPT_DISABL (0x1 << 0) // (UDPHS_EPT) Endpoint Disable 03544 // -------- UDPHS_EPTCTL : (UDPHS_EPT Offset: 0xc) UDPHS Endpoint Control Register -------- 03545 // -------- UDPHS_EPTSETSTA : (UDPHS_EPT Offset: 0x14) UDPHS Endpoint Set Status Register -------- 03546 #define AT91C_UDPHS_FRCESTALL (0x1 << 5) // (UDPHS_EPT) Stall Handshake Request Set/Clear/Status 03547 #define AT91C_UDPHS_KILL_BANK (0x1 << 9) // (UDPHS_EPT) KILL Bank 03548 // -------- UDPHS_EPTCLRSTA : (UDPHS_EPT Offset: 0x18) UDPHS Endpoint Clear Status Register -------- 03549 #define AT91C_UDPHS_TOGGLESQ (0x1 << 6) // (UDPHS_EPT) Data Toggle Clear 03550 // -------- UDPHS_EPTSTA : (UDPHS_EPT Offset: 0x1c) UDPHS Endpoint Status Register -------- 03551 #define AT91C_UDPHS_TOGGLESQ_STA (0x3 << 6) // (UDPHS_EPT) Toggle Sequencing 03552 #define AT91C_UDPHS_TOGGLESQ_STA_00 (0x0 << 6) // (UDPHS_EPT) Data0 03553 #define AT91C_UDPHS_TOGGLESQ_STA_01 (0x1 << 6) // (UDPHS_EPT) Data1 03554 #define AT91C_UDPHS_TOGGLESQ_STA_10 (0x2 << 6) // (UDPHS_EPT) Data2 (only for High-Bandwidth Isochronous EndPoint) 03555 #define AT91C_UDPHS_TOGGLESQ_STA_11 (0x3 << 6) // (UDPHS_EPT) MData (only for High-Bandwidth Isochronous EndPoint) 03556 #define AT91C_UDPHS_CONTROL_DIR (0x3 << 16) // (UDPHS_EPT) 03557 #define AT91C_UDPHS_CONTROL_DIR_00 (0x0 << 16) // (UDPHS_EPT) Bank 0 03558 #define AT91C_UDPHS_CONTROL_DIR_01 (0x1 << 16) // (UDPHS_EPT) Bank 1 03559 #define AT91C_UDPHS_CONTROL_DIR_10 (0x2 << 16) // (UDPHS_EPT) Bank 2 03560 #define AT91C_UDPHS_CONTROL_DIR_11 (0x3 << 16) // (UDPHS_EPT) Invalid 03561 #define AT91C_UDPHS_CURRENT_BANK (0x3 << 16) // (UDPHS_EPT) 03562 #define AT91C_UDPHS_CURRENT_BANK_00 (0x0 << 16) // (UDPHS_EPT) Bank 0 03563 #define AT91C_UDPHS_CURRENT_BANK_01 (0x1 << 16) // (UDPHS_EPT) Bank 1 03564 #define AT91C_UDPHS_CURRENT_BANK_10 (0x2 << 16) // (UDPHS_EPT) Bank 2 03565 #define AT91C_UDPHS_CURRENT_BANK_11 (0x3 << 16) // (UDPHS_EPT) Invalid 03566 #define AT91C_UDPHS_BUSY_BANK_STA (0x3 << 18) // (UDPHS_EPT) Busy Bank Number 03567 #define AT91C_UDPHS_BUSY_BANK_STA_00 (0x0 << 18) // (UDPHS_EPT) All banks are free 03568 #define AT91C_UDPHS_BUSY_BANK_STA_01 (0x1 << 18) // (UDPHS_EPT) 1 busy bank 03569 #define AT91C_UDPHS_BUSY_BANK_STA_10 (0x2 << 18) // (UDPHS_EPT) 2 busy banks 03570 #define AT91C_UDPHS_BUSY_BANK_STA_11 (0x3 << 18) // (UDPHS_EPT) 3 busy banks (if possible) 03571 #define AT91C_UDPHS_BYTE_COUNT (0x7FF << 20) // (UDPHS_EPT) UDPHS Byte Count 03572 03573 // ***************************************************************************** 03574 // SOFTWARE API DEFINITION FOR UDPHS DMA struct 03575 // ***************************************************************************** 03576 #ifndef __ASSEMBLY__ 03577 typedef struct _AT91S_UDPHS_DMA { 03578 AT91_REG UDPHS_DMANXTDSC; // UDPHS DMA Channel Next Descriptor Address 03579 AT91_REG UDPHS_DMAADDRESS; // UDPHS DMA Channel Address Register 03580 AT91_REG UDPHS_DMACONTROL; // UDPHS DMA Channel Control Register 03581 AT91_REG UDPHS_DMASTATUS; // UDPHS DMA Channel Status Register 03582 } AT91S_UDPHS_DMA, *AT91PS_UDPHS_DMA; 03583 #else 03584 #define UDPHS_DMANXTDSC (AT91_CAST(AT91_REG *) 0x00000000) // (UDPHS_DMANXTDSC) UDPHS DMA Channel Next Descriptor Address 03585 #define UDPHS_DMAADDRESS (AT91_CAST(AT91_REG *) 0x00000004) // (UDPHS_DMAADDRESS) UDPHS DMA Channel Address Register 03586 #define UDPHS_DMACONTROL (AT91_CAST(AT91_REG *) 0x00000008) // (UDPHS_DMACONTROL) UDPHS DMA Channel Control Register 03587 #define UDPHS_DMASTATUS (AT91_CAST(AT91_REG *) 0x0000000C) // (UDPHS_DMASTATUS) UDPHS DMA Channel Status Register 03588 03589 #endif 03590 // -------- UDPHS_DMANXTDSC : (UDPHS_DMA Offset: 0x0) UDPHS DMA Next Descriptor Address Register -------- 03591 #define AT91C_UDPHS_NXT_DSC_ADD (0xFFFFFFF << 4) // (UDPHS_DMA) next Channel Descriptor 03592 // -------- UDPHS_DMAADDRESS : (UDPHS_DMA Offset: 0x4) UDPHS DMA Channel Address Register -------- 03593 #define AT91C_UDPHS_BUFF_ADD (0x0 << 0) // (UDPHS_DMA) starting address of a DMA Channel transfer 03594 // -------- UDPHS_DMACONTROL : (UDPHS_DMA Offset: 0x8) UDPHS DMA Channel Control Register -------- 03595 #define AT91C_UDPHS_CHANN_ENB (0x1 << 0) // (UDPHS_DMA) Channel Enabled 03596 #define AT91C_UDPHS_LDNXT_DSC (0x1 << 1) // (UDPHS_DMA) Load Next Channel Transfer Descriptor Enable 03597 #define AT91C_UDPHS_END_TR_EN (0x1 << 2) // (UDPHS_DMA) Buffer Close Input Enable 03598 #define AT91C_UDPHS_END_B_EN (0x1 << 3) // (UDPHS_DMA) End of DMA Buffer Packet Validation 03599 #define AT91C_UDPHS_END_TR_IT (0x1 << 4) // (UDPHS_DMA) End Of Transfer Interrupt Enable 03600 #define AT91C_UDPHS_END_BUFFIT (0x1 << 5) // (UDPHS_DMA) End Of Channel Buffer Interrupt Enable 03601 #define AT91C_UDPHS_DESC_LD_IT (0x1 << 6) // (UDPHS_DMA) Descriptor Loaded Interrupt Enable 03602 #define AT91C_UDPHS_BURST_LCK (0x1 << 7) // (UDPHS_DMA) Burst Lock Enable 03603 #define AT91C_UDPHS_BUFF_LENGTH (0xFFFF << 16) // (UDPHS_DMA) Buffer Byte Length (write only) 03604 // -------- UDPHS_DMASTATUS : (UDPHS_DMA Offset: 0xc) UDPHS DMA Channelx Status Register -------- 03605 #define AT91C_UDPHS_CHANN_ACT (0x1 << 1) // (UDPHS_DMA) 03606 #define AT91C_UDPHS_END_TR_ST (0x1 << 4) // (UDPHS_DMA) 03607 #define AT91C_UDPHS_END_BF_ST (0x1 << 5) // (UDPHS_DMA) 03608 #define AT91C_UDPHS_DESC_LDST (0x1 << 6) // (UDPHS_DMA) 03609 #define AT91C_UDPHS_BUFF_COUNT (0xFFFF << 16) // (UDPHS_DMA) 03610 03611 // ***************************************************************************** 03612 // SOFTWARE API DEFINITION FOR UDPHS High Speed Device Interface 03613 // ***************************************************************************** 03614 #ifndef __ASSEMBLY__ 03615 typedef struct _AT91S_UDPHS { 03616 AT91_REG UDPHS_CTRL; // UDPHS Control Register 03617 AT91_REG UDPHS_FNUM; // UDPHS Frame Number Register 03618 AT91_REG Reserved0[2]; // 03619 AT91_REG UDPHS_IEN; // UDPHS Interrupt Enable Register 03620 AT91_REG UDPHS_INTSTA; // UDPHS Interrupt Status Register 03621 AT91_REG UDPHS_CLRINT; // UDPHS Clear Interrupt Register 03622 AT91_REG UDPHS_EPTRST; // UDPHS Endpoints Reset Register 03623 AT91_REG Reserved1[44]; // 03624 AT91_REG UDPHS_TSTSOFCNT; // UDPHS Test SOF Counter Register 03625 AT91_REG UDPHS_TSTCNTA; // UDPHS Test A Counter Register 03626 AT91_REG UDPHS_TSTCNTB; // UDPHS Test B Counter Register 03627 AT91_REG UDPHS_TSTMODREG; // UDPHS Test Mode Register 03628 AT91_REG UDPHS_TST; // UDPHS Test Register 03629 AT91_REG Reserved2[2]; // 03630 AT91_REG UDPHS_RIPPADDRSIZE; // UDPHS PADDRSIZE Register 03631 AT91_REG UDPHS_RIPNAME1; // UDPHS Name1 Register 03632 AT91_REG UDPHS_RIPNAME2; // UDPHS Name2 Register 03633 AT91_REG UDPHS_IPFEATURES; // UDPHS Features Register 03634 AT91_REG UDPHS_IPVERSION; // UDPHS Version Register 03635 AT91S_UDPHS_EPT UDPHS_EPT[7]; // UDPHS Endpoint struct 03636 AT91_REG Reserved3[72]; // 03637 AT91S_UDPHS_DMA UDPHS_DMA[6]; // UDPHS DMA channel struct (not use [0]) 03638 } AT91S_UDPHS, *AT91PS_UDPHS; 03639 #else 03640 #define UDPHS_CTRL (AT91_CAST(AT91_REG *) 0x00000000) // (UDPHS_CTRL) UDPHS Control Register 03641 #define UDPHS_FNUM (AT91_CAST(AT91_REG *) 0x00000004) // (UDPHS_FNUM) UDPHS Frame Number Register 03642 #define UDPHS_IEN (AT91_CAST(AT91_REG *) 0x00000010) // (UDPHS_IEN) UDPHS Interrupt Enable Register 03643 #define UDPHS_INTSTA (AT91_CAST(AT91_REG *) 0x00000014) // (UDPHS_INTSTA) UDPHS Interrupt Status Register 03644 #define UDPHS_CLRINT (AT91_CAST(AT91_REG *) 0x00000018) // (UDPHS_CLRINT) UDPHS Clear Interrupt Register 03645 #define UDPHS_EPTRST (AT91_CAST(AT91_REG *) 0x0000001C) // (UDPHS_EPTRST) UDPHS Endpoints Reset Register 03646 #define UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *) 0x000000D0) // (UDPHS_TSTSOFCNT) UDPHS Test SOF Counter Register 03647 #define UDPHS_TSTCNTA (AT91_CAST(AT91_REG *) 0x000000D4) // (UDPHS_TSTCNTA) UDPHS Test A Counter Register 03648 #define UDPHS_TSTCNTB (AT91_CAST(AT91_REG *) 0x000000D8) // (UDPHS_TSTCNTB) UDPHS Test B Counter Register 03649 #define UDPHS_TSTMODREG (AT91_CAST(AT91_REG *) 0x000000DC) // (UDPHS_TSTMODREG) UDPHS Test Mode Register 03650 #define UDPHS_TST (AT91_CAST(AT91_REG *) 0x000000E0) // (UDPHS_TST) UDPHS Test Register 03651 #define UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (UDPHS_RIPPADDRSIZE) UDPHS PADDRSIZE Register 03652 #define UDPHS_RIPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (UDPHS_RIPNAME1) UDPHS Name1 Register 03653 #define UDPHS_RIPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (UDPHS_RIPNAME2) UDPHS Name2 Register 03654 #define UDPHS_IPFEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (UDPHS_IPFEATURES) UDPHS Features Register 03655 #define UDPHS_IPVERSION (AT91_CAST(AT91_REG *) 0x000000FC) // (UDPHS_IPVERSION) UDPHS Version Register 03656 03657 #endif 03658 // -------- UDPHS_CTRL : (UDPHS Offset: 0x0) UDPHS Control Register -------- 03659 #define AT91C_UDPHS_DEV_ADDR (0x7F << 0) // (UDPHS) UDPHS Address 03660 #define AT91C_UDPHS_FADDR_EN (0x1 << 7) // (UDPHS) Function Address Enable 03661 #define AT91C_UDPHS_EN_UDPHS (0x1 << 8) // (UDPHS) UDPHS Enable 03662 #define AT91C_UDPHS_DETACH (0x1 << 9) // (UDPHS) Detach Command 03663 #define AT91C_UDPHS_REWAKEUP (0x1 << 10) // (UDPHS) Send Remote Wake Up 03664 #define AT91C_UDPHS_PULLD_DIS (0x1 << 11) // (UDPHS) PullDown Disable 03665 // -------- UDPHS_FNUM : (UDPHS Offset: 0x4) UDPHS Frame Number Register -------- 03666 #define AT91C_UDPHS_MICRO_FRAME_NUM (0x7 << 0) // (UDPHS) Micro Frame Number 03667 #define AT91C_UDPHS_FRAME_NUMBER (0x7FF << 3) // (UDPHS) Frame Number as defined in the Packet Field Formats 03668 #define AT91C_UDPHS_FNUM_ERR (0x1 << 31) // (UDPHS) Frame Number CRC Error 03669 // -------- UDPHS_IEN : (UDPHS Offset: 0x10) UDPHS Interrupt Enable Register -------- 03670 #define AT91C_UDPHS_DET_SUSPD (0x1 << 1) // (UDPHS) Suspend Interrupt Enable/Clear/Status 03671 #define AT91C_UDPHS_MICRO_SOF (0x1 << 2) // (UDPHS) Micro-SOF Interrupt Enable/Clear/Status 03672 #define AT91C_UDPHS_IEN_SOF (0x1 << 3) // (UDPHS) SOF Interrupt Enable/Clear/Status 03673 #define AT91C_UDPHS_ENDRESET (0x1 << 4) // (UDPHS) End Of Reset Interrupt Enable/Clear/Status 03674 #define AT91C_UDPHS_WAKE_UP (0x1 << 5) // (UDPHS) Wake Up CPU Interrupt Enable/Clear/Status 03675 #define AT91C_UDPHS_ENDOFRSM (0x1 << 6) // (UDPHS) End Of Resume Interrupt Enable/Clear/Status 03676 #define AT91C_UDPHS_UPSTR_RES (0x1 << 7) // (UDPHS) Upstream Resume Interrupt Enable/Clear/Status 03677 #define AT91C_UDPHS_EPT_INT_0 (0x1 << 8) // (UDPHS) Endpoint 0 Interrupt Enable/Status 03678 #define AT91C_UDPHS_EPT_INT_1 (0x1 << 9) // (UDPHS) Endpoint 1 Interrupt Enable/Status 03679 #define AT91C_UDPHS_EPT_INT_2 (0x1 << 10) // (UDPHS) Endpoint 2 Interrupt Enable/Status 03680 #define AT91C_UDPHS_EPT_INT_3 (0x1 << 11) // (UDPHS) Endpoint 3 Interrupt Enable/Status 03681 #define AT91C_UDPHS_EPT_INT_4 (0x1 << 12) // (UDPHS) Endpoint 4 Interrupt Enable/Status 03682 #define AT91C_UDPHS_EPT_INT_5 (0x1 << 13) // (UDPHS) Endpoint 5 Interrupt Enable/Status 03683 #define AT91C_UDPHS_EPT_INT_6 (0x1 << 14) // (UDPHS) Endpoint 6 Interrupt Enable/Status 03684 #define AT91C_UDPHS_DMA_INT_1 (0x1 << 25) // (UDPHS) DMA Channel 1 Interrupt Enable/Status 03685 #define AT91C_UDPHS_DMA_INT_2 (0x1 << 26) // (UDPHS) DMA Channel 2 Interrupt Enable/Status 03686 #define AT91C_UDPHS_DMA_INT_3 (0x1 << 27) // (UDPHS) DMA Channel 3 Interrupt Enable/Status 03687 #define AT91C_UDPHS_DMA_INT_4 (0x1 << 28) // (UDPHS) DMA Channel 4 Interrupt Enable/Status 03688 #define AT91C_UDPHS_DMA_INT_5 (0x1 << 29) // (UDPHS) DMA Channel 5 Interrupt Enable/Status 03689 #define AT91C_UDPHS_DMA_INT_6 (0x1 << 30) // (UDPHS) DMA Channel 6 Interrupt Enable/Status 03690 // -------- UDPHS_INTSTA : (UDPHS Offset: 0x14) UDPHS Interrupt Status Register -------- 03691 #define AT91C_UDPHS_SPEED (0x1 << 0) // (UDPHS) Speed Status 03692 // -------- UDPHS_CLRINT : (UDPHS Offset: 0x18) UDPHS Clear Interrupt Register -------- 03693 // -------- UDPHS_EPTRST : (UDPHS Offset: 0x1c) UDPHS Endpoints Reset Register -------- 03694 #define AT91C_UDPHS_RST_EPT_0 (0x1 << 0) // (UDPHS) Endpoint Reset 0 03695 #define AT91C_UDPHS_RST_EPT_1 (0x1 << 1) // (UDPHS) Endpoint Reset 1 03696 #define AT91C_UDPHS_RST_EPT_2 (0x1 << 2) // (UDPHS) Endpoint Reset 2 03697 #define AT91C_UDPHS_RST_EPT_3 (0x1 << 3) // (UDPHS) Endpoint Reset 3 03698 #define AT91C_UDPHS_RST_EPT_4 (0x1 << 4) // (UDPHS) Endpoint Reset 4 03699 #define AT91C_UDPHS_RST_EPT_5 (0x1 << 5) // (UDPHS) Endpoint Reset 5 03700 #define AT91C_UDPHS_RST_EPT_6 (0x1 << 6) // (UDPHS) Endpoint Reset 6 03701 // -------- UDPHS_TSTSOFCNT : (UDPHS Offset: 0xd0) UDPHS Test SOF Counter Register -------- 03702 #define AT91C_UDPHS_SOFCNTMAX (0x3 << 0) // (UDPHS) SOF Counter Max Value 03703 #define AT91C_UDPHS_SOFCTLOAD (0x1 << 7) // (UDPHS) SOF Counter Load 03704 // -------- UDPHS_TSTCNTA : (UDPHS Offset: 0xd4) UDPHS Test A Counter Register -------- 03705 #define AT91C_UDPHS_CNTAMAX (0x7FFF << 0) // (UDPHS) A Counter Max Value 03706 #define AT91C_UDPHS_CNTALOAD (0x1 << 15) // (UDPHS) A Counter Load 03707 // -------- UDPHS_TSTCNTB : (UDPHS Offset: 0xd8) UDPHS Test B Counter Register -------- 03708 #define AT91C_UDPHS_CNTBMAX (0x7FFF << 0) // (UDPHS) B Counter Max Value 03709 #define AT91C_UDPHS_CNTBLOAD (0x1 << 15) // (UDPHS) B Counter Load 03710 // -------- UDPHS_TSTMODREG : (UDPHS Offset: 0xdc) UDPHS Test Mode Register -------- 03711 #define AT91C_UDPHS_TSTMODE (0x1F << 1) // (UDPHS) UDPHS Core TestModeReg 03712 // -------- UDPHS_TST : (UDPHS Offset: 0xe0) UDPHS Test Register -------- 03713 #define AT91C_UDPHS_SPEED_CFG (0x3 << 0) // (UDPHS) Speed Configuration 03714 #define AT91C_UDPHS_SPEED_CFG_NM (0x0) // (UDPHS) Normal Mode 03715 #define AT91C_UDPHS_SPEED_CFG_RS (0x1) // (UDPHS) Reserved 03716 #define AT91C_UDPHS_SPEED_CFG_HS (0x2) // (UDPHS) Force High Speed 03717 #define AT91C_UDPHS_SPEED_CFG_FS (0x3) // (UDPHS) Force Full-Speed 03718 #define AT91C_UDPHS_TST_J (0x1 << 2) // (UDPHS) TestJMode 03719 #define AT91C_UDPHS_TST_K (0x1 << 3) // (UDPHS) TestKMode 03720 #define AT91C_UDPHS_TST_PKT (0x1 << 4) // (UDPHS) TestPacketMode 03721 #define AT91C_UDPHS_OPMODE2 (0x1 << 5) // (UDPHS) OpMode2 03722 // -------- UDPHS_RIPPADDRSIZE : (UDPHS Offset: 0xec) UDPHS PADDRSIZE Register -------- 03723 #define AT91C_UDPHS_IPPADDRSIZE (0x0 << 0) // (UDPHS) 2^UDPHSDEV_PADDR_SIZE 03724 // -------- UDPHS_RIPNAME1 : (UDPHS Offset: 0xf0) UDPHS Name Register -------- 03725 #define AT91C_UDPHS_IPNAME1 (0x0 << 0) // (UDPHS) ASCII string HUSB 03726 // -------- UDPHS_RIPNAME2 : (UDPHS Offset: 0xf4) UDPHS Name Register -------- 03727 #define AT91C_UDPHS_IPNAME2 (0x0 << 0) // (UDPHS) ASCII string 2DEV 03728 // -------- UDPHS_IPFEATURES : (UDPHS Offset: 0xf8) UDPHS Features Register -------- 03729 #define AT91C_UDPHS_EPT_NBR_MAX (0xF << 0) // (UDPHS) Max Number of Endpoints 03730 #define AT91C_UDPHS_DMA_CHANNEL_NBR (0x7 << 4) // (UDPHS) Number of DMA Channels 03731 #define AT91C_UDPHS_DMA_B_SIZ (0x1 << 7) // (UDPHS) DMA Buffer Size 03732 #define AT91C_UDPHS_DMA_FIFO_WORD_DEPTH (0xF << 8) // (UDPHS) DMA FIFO Depth in words 03733 #define AT91C_UDPHS_FIFO_MAX_SIZE (0x7 << 12) // (UDPHS) DPRAM size 03734 #define AT91C_UDPHS_BW_DPRAM (0x1 << 15) // (UDPHS) DPRAM byte write capability 03735 #define AT91C_UDPHS_DATAB16_8 (0x1 << 16) // (UDPHS) UTMI DataBus16_8 03736 #define AT91C_UDPHS_ISO_EPT_1 (0x1 << 17) // (UDPHS) Endpoint 1 High Bandwidth Isochronous Capability 03737 #define AT91C_UDPHS_ISO_EPT_2 (0x1 << 18) // (UDPHS) Endpoint 2 High Bandwidth Isochronous Capability 03738 #define AT91C_UDPHS_ISO_EPT_5 (0x1 << 21) // (UDPHS) Endpoint 5 High Bandwidth Isochronous Capability 03739 #define AT91C_UDPHS_ISO_EPT_6 (0x1 << 22) // (UDPHS) Endpoint 6 High Bandwidth Isochronous Capability 03740 // -------- UDPHS_IPVERSION : (UDPHS Offset: 0xfc) UDPHS Version Register -------- 03741 #define AT91C_UDPHS_VERSION_NUM (0xFFFF << 0) // (UDPHS) Give the IP version 03742 #define AT91C_UDPHS_METAL_FIX_NUM (0x7 << 16) // (UDPHS) Give the number of metal fixes 03743 03744 // ***************************************************************************** 03745 // SOFTWARE API DEFINITION FOR HDMA Channel structure 03746 // ***************************************************************************** 03747 #ifndef __ASSEMBLY__ 03748 #else 03749 #define HDMA_SADDR (AT91_CAST(AT91_REG *) 0x00000000) // (HDMA_SADDR) HDMA Channel Source Address Register 03750 #define HDMA_DADDR (AT91_CAST(AT91_REG *) 0x00000004) // (HDMA_DADDR) HDMA Channel Destination Address Register 03751 #define HDMA_DSCR (AT91_CAST(AT91_REG *) 0x00000008) // (HDMA_DSCR) HDMA Channel Descriptor Address Register 03752 #define HDMA_CTRLA (AT91_CAST(AT91_REG *) 0x0000000C) // (HDMA_CTRLA) HDMA Channel Control A Register 03753 #define HDMA_CTRLB (AT91_CAST(AT91_REG *) 0x00000010) // (HDMA_CTRLB) HDMA Channel Control B Register 03754 #define HDMA_CFG (AT91_CAST(AT91_REG *) 0x00000014) // (HDMA_CFG) HDMA Channel Configuration Register 03755 #define HDMA_SPIP (AT91_CAST(AT91_REG *) 0x00000018) // (HDMA_SPIP) HDMA Channel Source Picture in Picture Configuration Register 03756 #define HDMA_DPIP (AT91_CAST(AT91_REG *) 0x0000001C) // (HDMA_DPIP) HDMA Channel Destination Picture in Picture Configuration Register 03757 #define HDMA_BDSCR (AT91_CAST(AT91_REG *) 0x00000020) // (HDMA_BDSCR) HDMA Reserved 03758 #define HDMA_CADDR (AT91_CAST(AT91_REG *) 0x00000024) // (HDMA_CADDR) HDMA Reserved 03759 03760 #endif 03761 // -------- HDMA_SADDR : (HDMA_CH Offset: 0x0) -------- 03762 #define AT91C_SADDR (0x0 << 0) // (HDMA_CH) 03763 // -------- HDMA_DADDR : (HDMA_CH Offset: 0x4) -------- 03764 #define AT91C_DADDR (0x0 << 0) // (HDMA_CH) 03765 // -------- HDMA_DSCR : (HDMA_CH Offset: 0x8) -------- 03766 #define AT91C_HDMA_DSCR_IF (0x3 << 0) // (HDMA_CH) Select AHB-Lite Interface for current channel 03767 #define AT91C_HDMA_DSCR_IF_0 (0x0) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0. 03768 #define AT91C_HDMA_DSCR_IF_1 (0x1) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 1. 03769 #define AT91C_HDMA_DSCR_IF_2 (0x2) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 2. 03770 #define AT91C_HDMA_DSCR_IF_3 (0x3) // (HDMA_CH) The Buffer Transfer descriptor is fetched via AHB-Lite Interface 3. 03771 #define AT91C_HDMA_DSCR (0x3FFFFFFF << 2) // (HDMA_CH) Buffer Transfer descriptor address. This address is word aligned. 03772 // -------- HDMA_CTRLA : (HDMA_CH Offset: 0xc) -------- 03773 #define AT91C_HDMA_BTSIZE (0xFFFF << 0) // (HDMA_CH) Buffer Transfer Size. 03774 #define AT91C_HDMA_SCSIZE (0x7 << 16) // (HDMA_CH) Source Chunk Transfer Size. 03775 #define AT91C_HDMA_SCSIZE_1 (0x0 << 16) // (HDMA_CH) 1. 03776 #define AT91C_HDMA_SCSIZE_4 (0x1 << 16) // (HDMA_CH) 4. 03777 #define AT91C_HDMA_SCSIZE_8 (0x2 << 16) // (HDMA_CH) 8. 03778 #define AT91C_HDMA_SCSIZE_16 (0x3 << 16) // (HDMA_CH) 16. 03779 #define AT91C_HDMA_SCSIZE_32 (0x4 << 16) // (HDMA_CH) 32. 03780 #define AT91C_HDMA_SCSIZE_64 (0x5 << 16) // (HDMA_CH) 64. 03781 #define AT91C_HDMA_SCSIZE_128 (0x6 << 16) // (HDMA_CH) 128. 03782 #define AT91C_HDMA_SCSIZE_256 (0x7 << 16) // (HDMA_CH) 256. 03783 #define AT91C_HDMA_DCSIZE (0x7 << 20) // (HDMA_CH) Destination Chunk Transfer Size 03784 #define AT91C_HDMA_DCSIZE_1 (0x0 << 20) // (HDMA_CH) 1. 03785 #define AT91C_HDMA_DCSIZE_4 (0x1 << 20) // (HDMA_CH) 4. 03786 #define AT91C_HDMA_DCSIZE_8 (0x2 << 20) // (HDMA_CH) 8. 03787 #define AT91C_HDMA_DCSIZE_16 (0x3 << 20) // (HDMA_CH) 16. 03788 #define AT91C_HDMA_DCSIZE_32 (0x4 << 20) // (HDMA_CH) 32. 03789 #define AT91C_HDMA_DCSIZE_64 (0x5 << 20) // (HDMA_CH) 64. 03790 #define AT91C_HDMA_DCSIZE_128 (0x6 << 20) // (HDMA_CH) 128. 03791 #define AT91C_HDMA_DCSIZE_256 (0x7 << 20) // (HDMA_CH) 256. 03792 #define AT91C_HDMA_SRC_WIDTH (0x3 << 24) // (HDMA_CH) Source Single Transfer Size 03793 #define AT91C_HDMA_SRC_WIDTH_BYTE (0x0 << 24) // (HDMA_CH) BYTE. 03794 #define AT91C_HDMA_SRC_WIDTH_HALFWORD (0x1 << 24) // (HDMA_CH) HALF-WORD. 03795 #define AT91C_HDMA_SRC_WIDTH_WORD (0x2 << 24) // (HDMA_CH) WORD. 03796 #define AT91C_HDMA_DST_WIDTH (0x3 << 28) // (HDMA_CH) Destination Single Transfer Size 03797 #define AT91C_HDMA_DST_WIDTH_BYTE (0x0 << 28) // (HDMA_CH) BYTE. 03798 #define AT91C_HDMA_DST_WIDTH_HALFWORD (0x1 << 28) // (HDMA_CH) HALF-WORD. 03799 #define AT91C_HDMA_DST_WIDTH_WORD (0x2 << 28) // (HDMA_CH) WORD. 03800 #define AT91C_HDMA_DONE (0x1 << 31) // (HDMA_CH) 03801 // -------- HDMA_CTRLB : (HDMA_CH Offset: 0x10) -------- 03802 #define AT91C_HDMA_SIF (0x3 << 0) // (HDMA_CH) Source Interface Selection Field. 03803 #define AT91C_HDMA_SIF_0 (0x0) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 0. 03804 #define AT91C_HDMA_SIF_1 (0x1) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 1. 03805 #define AT91C_HDMA_SIF_2 (0x2) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 2. 03806 #define AT91C_HDMA_SIF_3 (0x3) // (HDMA_CH) The Source Transfer is done via AHB-Lite Interface 3. 03807 #define AT91C_HDMA_DIF (0x3 << 4) // (HDMA_CH) Destination Interface Selection Field. 03808 #define AT91C_HDMA_DIF_0 (0x0 << 4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 0. 03809 #define AT91C_HDMA_DIF_1 (0x1 << 4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 1. 03810 #define AT91C_HDMA_DIF_2 (0x2 << 4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 2. 03811 #define AT91C_HDMA_DIF_3 (0x3 << 4) // (HDMA_CH) The Destination Transfer is done via AHB-Lite Interface 3. 03812 #define AT91C_HDMA_SRC_PIP (0x1 << 8) // (HDMA_CH) Source Picture-in-Picture Mode 03813 #define AT91C_HDMA_SRC_PIP_DISABLE (0x0 << 8) // (HDMA_CH) Source Picture-in-Picture mode is disabled. 03814 #define AT91C_HDMA_SRC_PIP_ENABLE (0x1 << 8) // (HDMA_CH) Source Picture-in-Picture mode is enabled. 03815 #define AT91C_HDMA_DST_PIP (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture Mode 03816 #define AT91C_HDMA_DST_PIP_DISABLE (0x0 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is disabled. 03817 #define AT91C_HDMA_DST_PIP_ENABLE (0x1 << 12) // (HDMA_CH) Destination Picture-in-Picture mode is enabled. 03818 #define AT91C_HDMA_SRC_DSCR (0x1 << 16) // (HDMA_CH) Source Buffer Descriptor Fetch operation 03819 #define AT91C_HDMA_SRC_DSCR_FETCH_FROM_MEM (0x0 << 16) // (HDMA_CH) Source address is updated when the descriptor is fetched from the memory. 03820 #define AT91C_HDMA_SRC_DSCR_FETCH_DISABLE (0x1 << 16) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the Source. 03821 #define AT91C_HDMA_DST_DSCR (0x1 << 20) // (HDMA_CH) Destination Buffer Descriptor operation 03822 #define AT91C_HDMA_DST_DSCR_FETCH_FROM_MEM (0x0 << 20) // (HDMA_CH) Destination address is updated when the descriptor is fetched from the memory. 03823 #define AT91C_HDMA_DST_DSCR_FETCH_DISABLE (0x1 << 20) // (HDMA_CH) Buffer Descriptor Fetch operation is disabled for the destination. 03824 #define AT91C_HDMA_FC (0x7 << 21) // (HDMA_CH) This field defines which devices controls the size of the buffer transfer, also referred as to the Flow Controller. 03825 #define AT91C_HDMA_FC_MEM2MEM (0x0 << 21) // (HDMA_CH) Memory-to-Memory (DMA Controller). 03826 #define AT91C_HDMA_FC_MEM2PER (0x1 << 21) // (HDMA_CH) Memory-to-Peripheral (DMA Controller). 03827 #define AT91C_HDMA_FC_PER2MEM (0x2 << 21) // (HDMA_CH) Peripheral-to-Memory (DMA Controller). 03828 #define AT91C_HDMA_FC_PER2PER (0x3 << 21) // (HDMA_CH) Peripheral-to-Peripheral (DMA Controller). 03829 #define AT91C_HDMA_FC_PER2MEM_PER (0x4 << 21) // (HDMA_CH) Peripheral-to-Memory (Peripheral). 03830 #define AT91C_HDMA_FC_MEM2PER_PER (0x5 << 21) // (HDMA_CH) Memory-to-Peripheral (Peripheral). 03831 #define AT91C_HDMA_FC_PER2PER_PER (0x6 << 21) // (HDMA_CH) Peripheral-to-Peripheral (Source Peripheral). 03832 #define AT91C_HDMA_SRC_ADDRESS_MODE (0x3 << 24) // (HDMA_CH) Type of addressing mode 03833 #define AT91C_HDMA_SRC_ADDRESS_MODE_INCR (0x0 << 24) // (HDMA_CH) Incrementing Mode. 03834 #define AT91C_HDMA_SRC_ADDRESS_MODE_DECR (0x1 << 24) // (HDMA_CH) Decrementing Mode. 03835 #define AT91C_HDMA_SRC_ADDRESS_MODE_FIXED (0x2 << 24) // (HDMA_CH) Fixed Mode. 03836 #define AT91C_HDMA_DST_ADDRESS_MODE (0x3 << 28) // (HDMA_CH) Type of addressing mode 03837 #define AT91C_HDMA_DST_ADDRESS_MODE_INCR (0x0 << 28) // (HDMA_CH) Incrementing Mode. 03838 #define AT91C_HDMA_DST_ADDRESS_MODE_DECR (0x1 << 28) // (HDMA_CH) Decrementing Mode. 03839 #define AT91C_HDMA_DST_ADDRESS_MODE_FIXED (0x2 << 28) // (HDMA_CH) Fixed Mode. 03840 #define AT91C_HDMA_AUTO (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer enable 03841 #define AT91C_HDMA_AUTO_DISABLE (0x0 << 31) // (HDMA_CH) Automatic multiple buffer transfer is disabled. 03842 #define AT91C_HDMA_AUTO_ENABLE (0x1 << 31) // (HDMA_CH) Automatic multiple buffer transfer is enabled. This enables replay mode or contiguous mode when several buffers are transferred. 03843 // -------- HDMA_CFG : (HDMA_CH Offset: 0x14) -------- 03844 #define AT91C_HDMA_SRC_PER (0xF << 0) // (HDMA_CH) Channel Source Request is associated with peripheral identifier coded SRC_PER handshaking interface. 03845 #define AT91C_HDMA_SRC_PER_0 (0x0) // (HDMA_CH) HW Handshaking Interface number 0. 03846 #define AT91C_HDMA_SRC_PER_1 (0x1) // (HDMA_CH) HW Handshaking Interface number 1. 03847 #define AT91C_HDMA_SRC_PER_2 (0x2) // (HDMA_CH) HW Handshaking Interface number 2. 03848 #define AT91C_HDMA_SRC_PER_3 (0x3) // (HDMA_CH) HW Handshaking Interface number 3. 03849 #define AT91C_HDMA_SRC_PER_4 (0x4) // (HDMA_CH) HW Handshaking Interface number 4. 03850 #define AT91C_HDMA_SRC_PER_5 (0x5) // (HDMA_CH) HW Handshaking Interface number 5. 03851 #define AT91C_HDMA_SRC_PER_6 (0x6) // (HDMA_CH) HW Handshaking Interface number 6. 03852 #define AT91C_HDMA_SRC_PER_7 (0x7) // (HDMA_CH) HW Handshaking Interface number 7. 03853 #define AT91C_HDMA_SRC_PER_8 (0x8) // (HDMA_CH) HW Handshaking Interface number 8. 03854 #define AT91C_HDMA_SRC_PER_9 (0x9) // (HDMA_CH) HW Handshaking Interface number 9. 03855 #define AT91C_HDMA_SRC_PER_10 (0xA) // (HDMA_CH) HW Handshaking Interface number 10. 03856 #define AT91C_HDMA_SRC_PER_11 (0xB) // (HDMA_CH) HW Handshaking Interface number 11. 03857 #define AT91C_HDMA_SRC_PER_12 (0xC) // (HDMA_CH) HW Handshaking Interface number 12. 03858 #define AT91C_HDMA_SRC_PER_13 (0xD) // (HDMA_CH) HW Handshaking Interface number 13. 03859 #define AT91C_HDMA_SRC_PER_14 (0xE) // (HDMA_CH) HW Handshaking Interface number 14. 03860 #define AT91C_HDMA_SRC_PER_15 (0xF) // (HDMA_CH) HW Handshaking Interface number 15. 03861 #define AT91C_HDMA_DST_PER (0xF << 4) // (HDMA_CH) Channel Destination Request is associated with peripheral identifier coded DST_PER handshaking interface. 03862 #define AT91C_HDMA_DST_PER_0 (0x0 << 4) // (HDMA_CH) HW Handshaking Interface number 0. 03863 #define AT91C_HDMA_DST_PER_1 (0x1 << 4) // (HDMA_CH) HW Handshaking Interface number 1. 03864 #define AT91C_HDMA_DST_PER_2 (0x2 << 4) // (HDMA_CH) HW Handshaking Interface number 2. 03865 #define AT91C_HDMA_DST_PER_3 (0x3 << 4) // (HDMA_CH) HW Handshaking Interface number 3. 03866 #define AT91C_HDMA_DST_PER_4 (0x4 << 4) // (HDMA_CH) HW Handshaking Interface number 4. 03867 #define AT91C_HDMA_DST_PER_5 (0x5 << 4) // (HDMA_CH) HW Handshaking Interface number 5. 03868 #define AT91C_HDMA_DST_PER_6 (0x6 << 4) // (HDMA_CH) HW Handshaking Interface number 6. 03869 #define AT91C_HDMA_DST_PER_7 (0x7 << 4) // (HDMA_CH) HW Handshaking Interface number 7. 03870 #define AT91C_HDMA_DST_PER_8 (0x8 << 4) // (HDMA_CH) HW Handshaking Interface number 8. 03871 #define AT91C_HDMA_DST_PER_9 (0x9 << 4) // (HDMA_CH) HW Handshaking Interface number 9. 03872 #define AT91C_HDMA_DST_PER_10 (0xA << 4) // (HDMA_CH) HW Handshaking Interface number 10. 03873 #define AT91C_HDMA_DST_PER_11 (0xB << 4) // (HDMA_CH) HW Handshaking Interface number 11. 03874 #define AT91C_HDMA_DST_PER_12 (0xC << 4) // (HDMA_CH) HW Handshaking Interface number 12. 03875 #define AT91C_HDMA_DST_PER_13 (0xD << 4) // (HDMA_CH) HW Handshaking Interface number 13. 03876 #define AT91C_HDMA_DST_PER_14 (0xE << 4) // (HDMA_CH) HW Handshaking Interface number 14. 03877 #define AT91C_HDMA_DST_PER_15 (0xF << 4) // (HDMA_CH) HW Handshaking Interface number 15. 03878 #define AT91C_HDMA_SRC_REP (0x1 << 8) // (HDMA_CH) Source Replay Mode 03879 #define AT91C_HDMA_SRC_REP_CONTIGUOUS_ADDR (0x0 << 8) // (HDMA_CH) When automatic mode is activated, source address is contiguous between two buffers. 03880 #define AT91C_HDMA_SRC_REP_RELOAD_ADDR (0x1 << 8) // (HDMA_CH) When automatic mode is activated, the source address and the control register are reloaded from previous transfer.. 03881 #define AT91C_HDMA_SRC_H2SEL (0x1 << 9) // (HDMA_CH) Source Handshaking Mode 03882 #define AT91C_HDMA_SRC_H2SEL_SW (0x0 << 9) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request. 03883 #define AT91C_HDMA_SRC_H2SEL_HW (0x1 << 9) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request. 03884 #define AT91C_HDMA_DST_REP (0x1 << 12) // (HDMA_CH) Destination Replay Mode 03885 #define AT91C_HDMA_DST_REP_CONTIGUOUS_ADDR (0x0 << 12) // (HDMA_CH) When automatic mode is activated, destination address is contiguous between two buffers. 03886 #define AT91C_HDMA_DST_REP_RELOAD_ADDR (0x1 << 12) // (HDMA_CH) When automatic mode is activated, the destination address and the control register are reloaded from previous transfer.. 03887 #define AT91C_HDMA_DST_H2SEL (0x1 << 13) // (HDMA_CH) Destination Handshaking Mode 03888 #define AT91C_HDMA_DST_H2SEL_SW (0x0 << 13) // (HDMA_CH) Software handshaking interface is used to trigger a transfer request. 03889 #define AT91C_HDMA_DST_H2SEL_HW (0x1 << 13) // (HDMA_CH) Hardware handshaking interface is used to trigger a transfer request. 03890 #define AT91C_HDMA_SOD (0x1 << 16) // (HDMA_CH) STOP ON DONE 03891 #define AT91C_HDMA_SOD_DISABLE (0x0 << 16) // (HDMA_CH) STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 03892 #define AT91C_HDMA_SOD_ENABLE (0x1 << 16) // (HDMA_CH) STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 03893 #define AT91C_HDMA_LOCK_IF (0x1 << 20) // (HDMA_CH) Interface Lock 03894 #define AT91C_HDMA_LOCK_IF_DISABLE (0x0 << 20) // (HDMA_CH) Interface Lock capability is disabled. 03895 #define AT91C_HDMA_LOCK_IF_ENABLE (0x1 << 20) // (HDMA_CH) Interface Lock capability is enabled. 03896 #define AT91C_HDMA_LOCK_B (0x1 << 21) // (HDMA_CH) AHB Bus Lock 03897 #define AT91C_HDMA_LOCK_B_DISABLE (0x0 << 21) // (HDMA_CH) AHB Bus Locking capability is disabled. 03898 #define AT91C_HDMA_LOCK_B_ENABLE (0x1 << 21) // (HDMA_CH) AHB Bus Locking capability is enabled. 03899 #define AT91C_HDMA_LOCK_IF_L (0x1 << 22) // (HDMA_CH) Master Interface Arbiter Lock 03900 #define AT91C_HDMA_LOCK_IF_L_CHUNK (0x0 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a chunk transfer. 03901 #define AT91C_HDMA_LOCK_IF_L_BUFFER (0x1 << 22) // (HDMA_CH) The Master Interface Arbiter is locked by the channel x for a buffer transfer. 03902 #define AT91C_HDMA_AHB_PROT (0x7 << 24) // (HDMA_CH) AHB Prot 03903 #define AT91C_HDMA_FIFOCFG (0x3 << 28) // (HDMA_CH) FIFO Request Configuration 03904 #define AT91C_HDMA_FIFOCFG_LARGESTBURST (0x0 << 28) // (HDMA_CH) The largest defined length AHB burst is performed on the destination AHB interface. 03905 #define AT91C_HDMA_FIFOCFG_HALFFIFO (0x1 << 28) // (HDMA_CH) When half fifo size is available/filled a source/destination request is serviced. 03906 #define AT91C_HDMA_FIFOCFG_ENOUGHSPACE (0x2 << 28) // (HDMA_CH) When there is enough space/data available to perfom a single AHB access then the request is serviced. 03907 // -------- HDMA_SPIP : (HDMA_CH Offset: 0x18) -------- 03908 #define AT91C_SPIP_HOLE (0xFFFF << 0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached. 03909 #define AT91C_SPIP_BOUNDARY (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation. 03910 // -------- HDMA_DPIP : (HDMA_CH Offset: 0x1c) -------- 03911 #define AT91C_DPIP_HOLE (0xFFFF << 0) // (HDMA_CH) This field indicates the value to add to the address when the programmable boundary has been reached. 03912 #define AT91C_DPIP_BOUNDARY (0x3FF << 16) // (HDMA_CH) This field indicates the number of source transfers to perform before the automatic address increment operation. 03913 // -------- HDMA_BDSCR : (HDMA_CH Offset: 0x20) -------- 03914 // -------- HDMA_CADDR : (HDMA_CH Offset: 0x24) -------- 03915 03916 // ***************************************************************************** 03917 // SOFTWARE API DEFINITION FOR HDMA controller 03918 // ***************************************************************************** 03919 #ifndef __ASSEMBLY__ 03920 #else 03921 #define HDMA_GCFG (AT91_CAST(AT91_REG *) 0x00000000) // (HDMA_GCFG) HDMA Global Configuration Register 03922 #define HDMA_EN (AT91_CAST(AT91_REG *) 0x00000004) // (HDMA_EN) HDMA Controller Enable Register 03923 #define HDMA_SREQ (AT91_CAST(AT91_REG *) 0x00000008) // (HDMA_SREQ) HDMA Software Single Request Register 03924 #define HDMA_CREQ (AT91_CAST(AT91_REG *) 0x0000000C) // (HDMA_CREQ) HDMA Software Chunk Transfer Request Register 03925 #define HDMA_LAST (AT91_CAST(AT91_REG *) 0x00000010) // (HDMA_LAST) HDMA Software Last Transfer Flag Register 03926 #define HDMA_SYNC (AT91_CAST(AT91_REG *) 0x00000014) // (HDMA_SYNC) HDMA Request Synchronization Register 03927 #define HDMA_EBCIER (AT91_CAST(AT91_REG *) 0x00000018) // (HDMA_EBCIER) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register 03928 #define HDMA_EBCIDR (AT91_CAST(AT91_REG *) 0x0000001C) // (HDMA_EBCIDR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register 03929 #define HDMA_EBCIMR (AT91_CAST(AT91_REG *) 0x00000020) // (HDMA_EBCIMR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register 03930 #define HDMA_EBCISR (AT91_CAST(AT91_REG *) 0x00000024) // (HDMA_EBCISR) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register 03931 #define HDMA_CHER (AT91_CAST(AT91_REG *) 0x00000028) // (HDMA_CHER) HDMA Channel Handler Enable Register 03932 #define HDMA_CHDR (AT91_CAST(AT91_REG *) 0x0000002C) // (HDMA_CHDR) HDMA Channel Handler Disable Register 03933 #define HDMA_CHSR (AT91_CAST(AT91_REG *) 0x00000030) // (HDMA_CHSR) HDMA Channel Handler Status Register 03934 #define HDMA_RSVD0 (AT91_CAST(AT91_REG *) 0x00000034) // (HDMA_RSVD0) HDMA Reserved 03935 #define HDMA_RSVD1 (AT91_CAST(AT91_REG *) 0x00000038) // (HDMA_RSVD1) HDMA Reserved 03936 #define HDMA_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000001EC) // (HDMA_ADDRSIZE) HDMA ADDRSIZE REGISTER 03937 #define HDMA_IPNAME1 (AT91_CAST(AT91_REG *) 0x000001F0) // (HDMA_IPNAME1) HDMA IPNAME1 REGISTER 03938 #define HDMA_IPNAME2 (AT91_CAST(AT91_REG *) 0x000001F4) // (HDMA_IPNAME2) HDMA IPNAME2 REGISTER 03939 #define HDMA_FEATURES (AT91_CAST(AT91_REG *) 0x000001F8) // (HDMA_FEATURES) HDMA FEATURES REGISTER 03940 #define HDMA_VER (AT91_CAST(AT91_REG *) 0x000001FC) // (HDMA_VER) HDMA VERSION REGISTER 03941 03942 #endif 03943 // -------- HDMA_GCFG : (HDMA Offset: 0x0) -------- 03944 #define AT91C_HDMA_IF0_BIGEND (0x1 << 0) // (HDMA) AHB-Lite Interface 0 endian mode. 03945 #define AT91C_HDMA_IF0_BIGEND_IS_LITTLE_ENDIAN (0x0) // (HDMA) AHB-Lite Interface 0 is little endian. 03946 #define AT91C_HDMA_IF0_BIGEND_IS_BIG_ENDIAN (0x1) // (HDMA) AHB-Lite Interface 0 is big endian. 03947 #define AT91C_HDMA_IF1_BIGEND (0x1 << 1) // (HDMA) AHB-Lite Interface 1 endian mode. 03948 #define AT91C_HDMA_IF1_BIGEND_IS_LITTLE_ENDIAN (0x0 << 1) // (HDMA) AHB-Lite Interface 1 is little endian. 03949 #define AT91C_HDMA_IF1_BIGEND_IS_BIG_ENDIAN (0x1 << 1) // (HDMA) AHB-Lite Interface 1 is big endian. 03950 #define AT91C_HDMA_IF2_BIGEND (0x1 << 2) // (HDMA) AHB-Lite Interface 2 endian mode. 03951 #define AT91C_HDMA_IF2_BIGEND_IS_LITTLE_ENDIAN (0x0 << 2) // (HDMA) AHB-Lite Interface 2 is little endian. 03952 #define AT91C_HDMA_IF2_BIGEND_IS_BIG_ENDIAN (0x1 << 2) // (HDMA) AHB-Lite Interface 2 is big endian. 03953 #define AT91C_HDMA_IF3_BIGEND (0x1 << 3) // (HDMA) AHB-Lite Interface 3 endian mode. 03954 #define AT91C_HDMA_IF3_BIGEND_IS_LITTLE_ENDIAN (0x0 << 3) // (HDMA) AHB-Lite Interface 3 is little endian. 03955 #define AT91C_HDMA_IF3_BIGEND_IS_BIG_ENDIAN (0x1 << 3) // (HDMA) AHB-Lite Interface 3 is big endian. 03956 #define AT91C_HDMA_ARB_CFG (0x1 << 4) // (HDMA) Arbiter mode. 03957 #define AT91C_HDMA_ARB_CFG_FIXED (0x0 << 4) // (HDMA) Fixed priority arbiter. 03958 #define AT91C_HDMA_ARB_CFG_ROUND_ROBIN (0x1 << 4) // (HDMA) Modified round robin arbiter. 03959 // -------- HDMA_EN : (HDMA Offset: 0x4) -------- 03960 #define AT91C_HDMA_ENABLE (0x1 << 0) // (HDMA) 03961 #define AT91C_HDMA_ENABLE_DISABLE (0x0) // (HDMA) Disables HDMA. 03962 #define AT91C_HDMA_ENABLE_ENABLE (0x1) // (HDMA) Enables HDMA. 03963 // -------- HDMA_SREQ : (HDMA Offset: 0x8) -------- 03964 #define AT91C_HDMA_SSREQ0 (0x1 << 0) // (HDMA) Request a source single transfer on channel 0 03965 #define AT91C_HDMA_SSREQ0_0 (0x0) // (HDMA) No effect. 03966 #define AT91C_HDMA_SSREQ0_1 (0x1) // (HDMA) Request a source single transfer on channel 0. 03967 #define AT91C_HDMA_DSREQ0 (0x1 << 1) // (HDMA) Request a destination single transfer on channel 0 03968 #define AT91C_HDMA_DSREQ0_0 (0x0 << 1) // (HDMA) No effect. 03969 #define AT91C_HDMA_DSREQ0_1 (0x1 << 1) // (HDMA) Request a destination single transfer on channel 0. 03970 #define AT91C_HDMA_SSREQ1 (0x1 << 2) // (HDMA) Request a source single transfer on channel 1 03971 #define AT91C_HDMA_SSREQ1_0 (0x0 << 2) // (HDMA) No effect. 03972 #define AT91C_HDMA_SSREQ1_1 (0x1 << 2) // (HDMA) Request a source single transfer on channel 1. 03973 #define AT91C_HDMA_DSREQ1 (0x1 << 3) // (HDMA) Request a destination single transfer on channel 1 03974 #define AT91C_HDMA_DSREQ1_0 (0x0 << 3) // (HDMA) No effect. 03975 #define AT91C_HDMA_DSREQ1_1 (0x1 << 3) // (HDMA) Request a destination single transfer on channel 1. 03976 #define AT91C_HDMA_SSREQ2 (0x1 << 4) // (HDMA) Request a source single transfer on channel 2 03977 #define AT91C_HDMA_SSREQ2_0 (0x0 << 4) // (HDMA) No effect. 03978 #define AT91C_HDMA_SSREQ2_1 (0x1 << 4) // (HDMA) Request a source single transfer on channel 2. 03979 #define AT91C_HDMA_DSREQ2 (0x1 << 5) // (HDMA) Request a destination single transfer on channel 2 03980 #define AT91C_HDMA_DSREQ2_0 (0x0 << 5) // (HDMA) No effect. 03981 #define AT91C_HDMA_DSREQ2_1 (0x1 << 5) // (HDMA) Request a destination single transfer on channel 2. 03982 #define AT91C_HDMA_SSREQ3 (0x1 << 6) // (HDMA) Request a source single transfer on channel 3 03983 #define AT91C_HDMA_SSREQ3_0 (0x0 << 6) // (HDMA) No effect. 03984 #define AT91C_HDMA_SSREQ3_1 (0x1 << 6) // (HDMA) Request a source single transfer on channel 3. 03985 #define AT91C_HDMA_DSREQ3 (0x1 << 7) // (HDMA) Request a destination single transfer on channel 3 03986 #define AT91C_HDMA_DSREQ3_0 (0x0 << 7) // (HDMA) No effect. 03987 #define AT91C_HDMA_DSREQ3_1 (0x1 << 7) // (HDMA) Request a destination single transfer on channel 3. 03988 #define AT91C_HDMA_SSREQ4 (0x1 << 8) // (HDMA) Request a source single transfer on channel 4 03989 #define AT91C_HDMA_SSREQ4_0 (0x0 << 8) // (HDMA) No effect. 03990 #define AT91C_HDMA_SSREQ4_1 (0x1 << 8) // (HDMA) Request a source single transfer on channel 4. 03991 #define AT91C_HDMA_DSREQ4 (0x1 << 9) // (HDMA) Request a destination single transfer on channel 4 03992 #define AT91C_HDMA_DSREQ4_0 (0x0 << 9) // (HDMA) No effect. 03993 #define AT91C_HDMA_DSREQ4_1 (0x1 << 9) // (HDMA) Request a destination single transfer on channel 4. 03994 #define AT91C_HDMA_SSREQ5 (0x1 << 10) // (HDMA) Request a source single transfer on channel 5 03995 #define AT91C_HDMA_SSREQ5_0 (0x0 << 10) // (HDMA) No effect. 03996 #define AT91C_HDMA_SSREQ5_1 (0x1 << 10) // (HDMA) Request a source single transfer on channel 5. 03997 #define AT91C_HDMA_DSREQ6 (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5 03998 #define AT91C_HDMA_DSREQ6_0 (0x0 << 11) // (HDMA) No effect. 03999 #define AT91C_HDMA_DSREQ6_1 (0x1 << 11) // (HDMA) Request a destination single transfer on channel 5. 04000 #define AT91C_HDMA_SSREQ6 (0x1 << 12) // (HDMA) Request a source single transfer on channel 6 04001 #define AT91C_HDMA_SSREQ6_0 (0x0 << 12) // (HDMA) No effect. 04002 #define AT91C_HDMA_SSREQ6_1 (0x1 << 12) // (HDMA) Request a source single transfer on channel 6. 04003 #define AT91C_HDMA_SSREQ7 (0x1 << 14) // (HDMA) Request a source single transfer on channel 7 04004 #define AT91C_HDMA_SSREQ7_0 (0x0 << 14) // (HDMA) No effect. 04005 #define AT91C_HDMA_SSREQ7_1 (0x1 << 14) // (HDMA) Request a source single transfer on channel 7. 04006 #define AT91C_HDMA_DSREQ7 (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7 04007 #define AT91C_HDMA_DSREQ7_0 (0x0 << 15) // (HDMA) No effect. 04008 #define AT91C_HDMA_DSREQ7_1 (0x1 << 15) // (HDMA) Request a destination single transfer on channel 7. 04009 // -------- HDMA_CREQ : (HDMA Offset: 0xc) -------- 04010 #define AT91C_HDMA_SCREQ0 (0x1 << 0) // (HDMA) Request a source chunk transfer on channel 0 04011 #define AT91C_HDMA_SCREQ0_0 (0x0) // (HDMA) No effect. 04012 #define AT91C_HDMA_SCREQ0_1 (0x1) // (HDMA) Request a source chunk transfer on channel 0. 04013 #define AT91C_HDMA_DCREQ0 (0x1 << 1) // (HDMA) Request a destination chunk transfer on channel 0 04014 #define AT91C_HDMA_DCREQ0_0 (0x0 << 1) // (HDMA) No effect. 04015 #define AT91C_HDMA_DCREQ0_1 (0x1 << 1) // (HDMA) Request a destination chunk transfer on channel 0. 04016 #define AT91C_HDMA_SCREQ1 (0x1 << 2) // (HDMA) Request a source chunk transfer on channel 1 04017 #define AT91C_HDMA_SCREQ1_0 (0x0 << 2) // (HDMA) No effect. 04018 #define AT91C_HDMA_SCREQ1_1 (0x1 << 2) // (HDMA) Request a source chunk transfer on channel 1. 04019 #define AT91C_HDMA_DCREQ1 (0x1 << 3) // (HDMA) Request a destination chunk transfer on channel 1 04020 #define AT91C_HDMA_DCREQ1_0 (0x0 << 3) // (HDMA) No effect. 04021 #define AT91C_HDMA_DCREQ1_1 (0x1 << 3) // (HDMA) Request a destination chunk transfer on channel 1. 04022 #define AT91C_HDMA_SCREQ2 (0x1 << 4) // (HDMA) Request a source chunk transfer on channel 2 04023 #define AT91C_HDMA_SCREQ2_0 (0x0 << 4) // (HDMA) No effect. 04024 #define AT91C_HDMA_SCREQ2_1 (0x1 << 4) // (HDMA) Request a source chunk transfer on channel 2. 04025 #define AT91C_HDMA_DCREQ2 (0x1 << 5) // (HDMA) Request a destination chunk transfer on channel 2 04026 #define AT91C_HDMA_DCREQ2_0 (0x0 << 5) // (HDMA) No effect. 04027 #define AT91C_HDMA_DCREQ2_1 (0x1 << 5) // (HDMA) Request a destination chunk transfer on channel 2. 04028 #define AT91C_HDMA_SCREQ3 (0x1 << 6) // (HDMA) Request a source chunk transfer on channel 3 04029 #define AT91C_HDMA_SCREQ3_0 (0x0 << 6) // (HDMA) No effect. 04030 #define AT91C_HDMA_SCREQ3_1 (0x1 << 6) // (HDMA) Request a source chunk transfer on channel 3. 04031 #define AT91C_HDMA_DCREQ3 (0x1 << 7) // (HDMA) Request a destination chunk transfer on channel 3 04032 #define AT91C_HDMA_DCREQ3_0 (0x0 << 7) // (HDMA) No effect. 04033 #define AT91C_HDMA_DCREQ3_1 (0x1 << 7) // (HDMA) Request a destination chunk transfer on channel 3. 04034 #define AT91C_HDMA_SCREQ4 (0x1 << 8) // (HDMA) Request a source chunk transfer on channel 4 04035 #define AT91C_HDMA_SCREQ4_0 (0x0 << 8) // (HDMA) No effect. 04036 #define AT91C_HDMA_SCREQ4_1 (0x1 << 8) // (HDMA) Request a source chunk transfer on channel 4. 04037 #define AT91C_HDMA_DCREQ4 (0x1 << 9) // (HDMA) Request a destination chunk transfer on channel 4 04038 #define AT91C_HDMA_DCREQ4_0 (0x0 << 9) // (HDMA) No effect. 04039 #define AT91C_HDMA_DCREQ4_1 (0x1 << 9) // (HDMA) Request a destination chunk transfer on channel 4. 04040 #define AT91C_HDMA_SCREQ5 (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5 04041 #define AT91C_HDMA_SCREQ5_0 (0x0 << 10) // (HDMA) No effect. 04042 #define AT91C_HDMA_SCREQ5_1 (0x1 << 10) // (HDMA) Request a source chunk transfer on channel 5. 04043 #define AT91C_HDMA_DCREQ6 (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5 04044 #define AT91C_HDMA_DCREQ6_0 (0x0 << 11) // (HDMA) No effect. 04045 #define AT91C_HDMA_DCREQ6_1 (0x1 << 11) // (HDMA) Request a destination chunk transfer on channel 5. 04046 #define AT91C_HDMA_SCREQ6 (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6 04047 #define AT91C_HDMA_SCREQ6_0 (0x0 << 12) // (HDMA) No effect. 04048 #define AT91C_HDMA_SCREQ6_1 (0x1 << 12) // (HDMA) Request a source chunk transfer on channel 6. 04049 #define AT91C_HDMA_SCREQ7 (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7 04050 #define AT91C_HDMA_SCREQ7_0 (0x0 << 14) // (HDMA) No effect. 04051 #define AT91C_HDMA_SCREQ7_1 (0x1 << 14) // (HDMA) Request a source chunk transfer on channel 7. 04052 #define AT91C_HDMA_DCREQ7 (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7 04053 #define AT91C_HDMA_DCREQ7_0 (0x0 << 15) // (HDMA) No effect. 04054 #define AT91C_HDMA_DCREQ7_1 (0x1 << 15) // (HDMA) Request a destination chunk transfer on channel 7. 04055 // -------- HDMA_LAST : (HDMA Offset: 0x10) -------- 04056 #define AT91C_HDMA_SLAST0 (0x1 << 0) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 0 04057 #define AT91C_HDMA_SLAST0_0 (0x0) // (HDMA) No effect. 04058 #define AT91C_HDMA_SLAST0_1 (0x1) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 0. 04059 #define AT91C_HDMA_DLAST0 (0x1 << 1) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 0 04060 #define AT91C_HDMA_DLAST0_0 (0x0 << 1) // (HDMA) No effect. 04061 #define AT91C_HDMA_DLAST0_1 (0x1 << 1) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 0. 04062 #define AT91C_HDMA_SLAST1 (0x1 << 2) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 1 04063 #define AT91C_HDMA_SLAST1_0 (0x0 << 2) // (HDMA) No effect. 04064 #define AT91C_HDMA_SLAST1_1 (0x1 << 2) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 1. 04065 #define AT91C_HDMA_DLAST1 (0x1 << 3) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 1 04066 #define AT91C_HDMA_DLAST1_0 (0x0 << 3) // (HDMA) No effect. 04067 #define AT91C_HDMA_DLAST1_1 (0x1 << 3) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 1. 04068 #define AT91C_HDMA_SLAST2 (0x1 << 4) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 2 04069 #define AT91C_HDMA_SLAST2_0 (0x0 << 4) // (HDMA) No effect. 04070 #define AT91C_HDMA_SLAST2_1 (0x1 << 4) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 2. 04071 #define AT91C_HDMA_DLAST2 (0x1 << 5) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 2 04072 #define AT91C_HDMA_DLAST2_0 (0x0 << 5) // (HDMA) No effect. 04073 #define AT91C_HDMA_DLAST2_1 (0x1 << 5) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 2. 04074 #define AT91C_HDMA_SLAST3 (0x1 << 6) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 3 04075 #define AT91C_HDMA_SLAST3_0 (0x0 << 6) // (HDMA) No effect. 04076 #define AT91C_HDMA_SLAST3_1 (0x1 << 6) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 3. 04077 #define AT91C_HDMA_DLAST3 (0x1 << 7) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 3 04078 #define AT91C_HDMA_DLAST3_0 (0x0 << 7) // (HDMA) No effect. 04079 #define AT91C_HDMA_DLAST3_1 (0x1 << 7) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 3. 04080 #define AT91C_HDMA_SLAST4 (0x1 << 8) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 4 04081 #define AT91C_HDMA_SLAST4_0 (0x0 << 8) // (HDMA) No effect. 04082 #define AT91C_HDMA_SLAST4_1 (0x1 << 8) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 4. 04083 #define AT91C_HDMA_DLAST4 (0x1 << 9) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 4 04084 #define AT91C_HDMA_DLAST4_0 (0x0 << 9) // (HDMA) No effect. 04085 #define AT91C_HDMA_DLAST4_1 (0x1 << 9) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 4. 04086 #define AT91C_HDMA_SLAST5 (0x1 << 10) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 5 04087 #define AT91C_HDMA_SLAST5_0 (0x0 << 10) // (HDMA) No effect. 04088 #define AT91C_HDMA_SLAST5_1 (0x1 << 10) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 5. 04089 #define AT91C_HDMA_DLAST6 (0x1 << 11) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 5 04090 #define AT91C_HDMA_DLAST6_0 (0x0 << 11) // (HDMA) No effect. 04091 #define AT91C_HDMA_DLAST6_1 (0x1 << 11) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 5. 04092 #define AT91C_HDMA_SLAST6 (0x1 << 12) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 6 04093 #define AT91C_HDMA_SLAST6_0 (0x0 << 12) // (HDMA) No effect. 04094 #define AT91C_HDMA_SLAST6_1 (0x1 << 12) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 6. 04095 #define AT91C_HDMA_SLAST7 (0x1 << 14) // (HDMA) Indicates that this source request is the last transfer of the buffer on channel 7 04096 #define AT91C_HDMA_SLAST7_0 (0x0 << 14) // (HDMA) No effect. 04097 #define AT91C_HDMA_SLAST7_1 (0x1 << 14) // (HDMA) Writing one to SLASTx prior to writing one to SSREQx or SCREQx indicates that this source request is the last transfer of the buffer on channel 7. 04098 #define AT91C_HDMA_DLAST7 (0x1 << 15) // (HDMA) Indicates that this destination request is the last transfer of the buffer on channel 7 04099 #define AT91C_HDMA_DLAST7_0 (0x0 << 15) // (HDMA) No effect. 04100 #define AT91C_HDMA_DLAST7_1 (0x1 << 15) // (HDMA) Writing one to DLASTx prior to writing one to DSREQx or DCREQx indicates that this destination request is the last transfer of the buffer on channel 7. 04101 // -------- HDMA_SYNC : (HDMA Offset: 0x14) -------- 04102 #define AT91C_SYNC_REQ (0xFFFF << 0) // (HDMA) 04103 // -------- HDMA_EBCIER : (HDMA Offset: 0x18) Buffer Transfer Completed/Chained Buffer Transfer Completed/Access Error Interrupt Enable Register -------- 04104 #define AT91C_HDMA_BTC0 (0x1 << 0) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04105 #define AT91C_HDMA_BTC1 (0x1 << 1) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04106 #define AT91C_HDMA_BTC2 (0x1 << 2) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04107 #define AT91C_HDMA_BTC3 (0x1 << 3) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04108 #define AT91C_HDMA_BTC4 (0x1 << 4) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04109 #define AT91C_HDMA_BTC5 (0x1 << 5) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04110 #define AT91C_HDMA_BTC6 (0x1 << 6) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04111 #define AT91C_HDMA_BTC7 (0x1 << 7) // (HDMA) Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04112 #define AT91C_HDMA_CBTC0 (0x1 << 8) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04113 #define AT91C_HDMA_CBTC1 (0x1 << 9) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04114 #define AT91C_HDMA_CBTC2 (0x1 << 10) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04115 #define AT91C_HDMA_CBTC3 (0x1 << 11) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04116 #define AT91C_HDMA_CBTC4 (0x1 << 12) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04117 #define AT91C_HDMA_CBTC5 (0x1 << 13) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04118 #define AT91C_HDMA_CBTC6 (0x1 << 14) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04119 #define AT91C_HDMA_CBTC7 (0x1 << 15) // (HDMA) Chained Buffer Transfer Completed Interrupt Enable/Disable/Status Register 04120 #define AT91C_HDMA_ERR0 (0x1 << 16) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04121 #define AT91C_HDMA_ERR1 (0x1 << 17) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04122 #define AT91C_HDMA_ERR2 (0x1 << 18) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04123 #define AT91C_HDMA_ERR3 (0x1 << 19) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04124 #define AT91C_HDMA_ERR4 (0x1 << 20) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04125 #define AT91C_HDMA_ERR5 (0x1 << 21) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04126 #define AT91C_HDMA_ERR6 (0x1 << 22) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04127 #define AT91C_HDMA_ERR7 (0x1 << 23) // (HDMA) Access HDMA_Error Interrupt Enable/Disable/Status Register 04128 // -------- HDMA_EBCIDR : (HDMA Offset: 0x1c) -------- 04129 // -------- HDMA_EBCIMR : (HDMA Offset: 0x20) -------- 04130 // -------- HDMA_EBCISR : (HDMA Offset: 0x24) -------- 04131 // -------- HDMA_CHER : (HDMA Offset: 0x28) -------- 04132 #define AT91C_HDMA_ENA0 (0x1 << 0) // (HDMA) When set, channel 0 enabled. 04133 #define AT91C_HDMA_ENA0_0 (0x0) // (HDMA) No effect. 04134 #define AT91C_HDMA_ENA0_1 (0x1) // (HDMA) Channel 0 enabled. 04135 #define AT91C_HDMA_ENA1 (0x1 << 1) // (HDMA) When set, channel 1 enabled. 04136 #define AT91C_HDMA_ENA1_0 (0x0 << 1) // (HDMA) No effect. 04137 #define AT91C_HDMA_ENA1_1 (0x1 << 1) // (HDMA) Channel 1 enabled. 04138 #define AT91C_HDMA_ENA2 (0x1 << 2) // (HDMA) When set, channel 2 enabled. 04139 #define AT91C_HDMA_ENA2_0 (0x0 << 2) // (HDMA) No effect. 04140 #define AT91C_HDMA_ENA2_1 (0x1 << 2) // (HDMA) Channel 2 enabled. 04141 #define AT91C_HDMA_ENA3 (0x1 << 3) // (HDMA) When set, channel 3 enabled. 04142 #define AT91C_HDMA_ENA3_0 (0x0 << 3) // (HDMA) No effect. 04143 #define AT91C_HDMA_ENA3_1 (0x1 << 3) // (HDMA) Channel 3 enabled. 04144 #define AT91C_HDMA_ENA4 (0x1 << 4) // (HDMA) When set, channel 4 enabled. 04145 #define AT91C_HDMA_ENA4_0 (0x0 << 4) // (HDMA) No effect. 04146 #define AT91C_HDMA_ENA4_1 (0x1 << 4) // (HDMA) Channel 4 enabled. 04147 #define AT91C_HDMA_ENA5 (0x1 << 5) // (HDMA) When set, channel 5 enabled. 04148 #define AT91C_HDMA_ENA5_0 (0x0 << 5) // (HDMA) No effect. 04149 #define AT91C_HDMA_ENA5_1 (0x1 << 5) // (HDMA) Channel 5 enabled. 04150 #define AT91C_HDMA_ENA6 (0x1 << 6) // (HDMA) When set, channel 6 enabled. 04151 #define AT91C_HDMA_ENA6_0 (0x0 << 6) // (HDMA) No effect. 04152 #define AT91C_HDMA_ENA6_1 (0x1 << 6) // (HDMA) Channel 6 enabled. 04153 #define AT91C_HDMA_ENA7 (0x1 << 7) // (HDMA) When set, channel 7 enabled. 04154 #define AT91C_HDMA_ENA7_0 (0x0 << 7) // (HDMA) No effect. 04155 #define AT91C_HDMA_ENA7_1 (0x1 << 7) // (HDMA) Channel 7 enabled. 04156 #define AT91C_HDMA_SUSP0 (0x1 << 8) // (HDMA) When set, channel 0 freezed and its current context. 04157 #define AT91C_HDMA_SUSP0_0 (0x0 << 8) // (HDMA) No effect. 04158 #define AT91C_HDMA_SUSP0_1 (0x1 << 8) // (HDMA) Channel 0 freezed. 04159 #define AT91C_HDMA_SUSP1 (0x1 << 9) // (HDMA) When set, channel 1 freezed and its current context. 04160 #define AT91C_HDMA_SUSP1_0 (0x0 << 9) // (HDMA) No effect. 04161 #define AT91C_HDMA_SUSP1_1 (0x1 << 9) // (HDMA) Channel 1 freezed. 04162 #define AT91C_HDMA_SUSP2 (0x1 << 10) // (HDMA) When set, channel 2 freezed and its current context. 04163 #define AT91C_HDMA_SUSP2_0 (0x0 << 10) // (HDMA) No effect. 04164 #define AT91C_HDMA_SUSP2_1 (0x1 << 10) // (HDMA) Channel 2 freezed. 04165 #define AT91C_HDMA_SUSP3 (0x1 << 11) // (HDMA) When set, channel 3 freezed and its current context. 04166 #define AT91C_HDMA_SUSP3_0 (0x0 << 11) // (HDMA) No effect. 04167 #define AT91C_HDMA_SUSP3_1 (0x1 << 11) // (HDMA) Channel 3 freezed. 04168 #define AT91C_HDMA_SUSP4 (0x1 << 12) // (HDMA) When set, channel 4 freezed and its current context. 04169 #define AT91C_HDMA_SUSP4_0 (0x0 << 12) // (HDMA) No effect. 04170 #define AT91C_HDMA_SUSP4_1 (0x1 << 12) // (HDMA) Channel 4 freezed. 04171 #define AT91C_HDMA_SUSP5 (0x1 << 13) // (HDMA) When set, channel 5 freezed and its current context. 04172 #define AT91C_HDMA_SUSP5_0 (0x0 << 13) // (HDMA) No effect. 04173 #define AT91C_HDMA_SUSP5_1 (0x1 << 13) // (HDMA) Channel 5 freezed. 04174 #define AT91C_HDMA_SUSP6 (0x1 << 14) // (HDMA) When set, channel 6 freezed and its current context. 04175 #define AT91C_HDMA_SUSP6_0 (0x0 << 14) // (HDMA) No effect. 04176 #define AT91C_HDMA_SUSP6_1 (0x1 << 14) // (HDMA) Channel 6 freezed. 04177 #define AT91C_HDMA_SUSP7 (0x1 << 15) // (HDMA) When set, channel 7 freezed and its current context. 04178 #define AT91C_HDMA_SUSP7_0 (0x0 << 15) // (HDMA) No effect. 04179 #define AT91C_HDMA_SUSP7_1 (0x1 << 15) // (HDMA) Channel 7 freezed. 04180 #define AT91C_HDMA_KEEP0 (0x1 << 24) // (HDMA) When set, it resumes the channel 0 from an automatic stall state. 04181 #define AT91C_HDMA_KEEP0_0 (0x0 << 24) // (HDMA) No effect. 04182 #define AT91C_HDMA_KEEP0_1 (0x1 << 24) // (HDMA) Resumes the channel 0. 04183 #define AT91C_HDMA_KEEP1 (0x1 << 25) // (HDMA) When set, it resumes the channel 1 from an automatic stall state. 04184 #define AT91C_HDMA_KEEP1_0 (0x0 << 25) // (HDMA) No effect. 04185 #define AT91C_HDMA_KEEP1_1 (0x1 << 25) // (HDMA) Resumes the channel 1. 04186 #define AT91C_HDMA_KEEP2 (0x1 << 26) // (HDMA) When set, it resumes the channel 2 from an automatic stall state. 04187 #define AT91C_HDMA_KEEP2_0 (0x0 << 26) // (HDMA) No effect. 04188 #define AT91C_HDMA_KEEP2_1 (0x1 << 26) // (HDMA) Resumes the channel 2. 04189 #define AT91C_HDMA_KEEP3 (0x1 << 27) // (HDMA) When set, it resumes the channel 3 from an automatic stall state. 04190 #define AT91C_HDMA_KEEP3_0 (0x0 << 27) // (HDMA) No effect. 04191 #define AT91C_HDMA_KEEP3_1 (0x1 << 27) // (HDMA) Resumes the channel 3. 04192 #define AT91C_HDMA_KEEP4 (0x1 << 28) // (HDMA) When set, it resumes the channel 4 from an automatic stall state. 04193 #define AT91C_HDMA_KEEP4_0 (0x0 << 28) // (HDMA) No effect. 04194 #define AT91C_HDMA_KEEP4_1 (0x1 << 28) // (HDMA) Resumes the channel 4. 04195 #define AT91C_HDMA_KEEP5 (0x1 << 29) // (HDMA) When set, it resumes the channel 5 from an automatic stall state. 04196 #define AT91C_HDMA_KEEP5_0 (0x0 << 29) // (HDMA) No effect. 04197 #define AT91C_HDMA_KEEP5_1 (0x1 << 29) // (HDMA) Resumes the channel 5. 04198 #define AT91C_HDMA_KEEP6 (0x1 << 30) // (HDMA) When set, it resumes the channel 6 from an automatic stall state. 04199 #define AT91C_HDMA_KEEP6_0 (0x0 << 30) // (HDMA) No effect. 04200 #define AT91C_HDMA_KEEP6_1 (0x1 << 30) // (HDMA) Resumes the channel 6. 04201 #define AT91C_HDMA_KEEP7 (0x1 << 31) // (HDMA) When set, it resumes the channel 7 from an automatic stall state. 04202 #define AT91C_HDMA_KEEP7_0 (0x0 << 31) // (HDMA) No effect. 04203 #define AT91C_HDMA_KEEP7_1 (0x1 << 31) // (HDMA) Resumes the channel 7. 04204 // -------- HDMA_CHDR : (HDMA Offset: 0x2c) -------- 04205 #define AT91C_HDMA_DIS0 (0x1 << 0) // (HDMA) Write one to this field to disable the channel 0. 04206 #define AT91C_HDMA_DIS0_0 (0x0) // (HDMA) No effect. 04207 #define AT91C_HDMA_DIS0_1 (0x1) // (HDMA) Disables the channel 0. 04208 #define AT91C_HDMA_DIS1 (0x1 << 1) // (HDMA) Write one to this field to disable the channel 1. 04209 #define AT91C_HDMA_DIS1_0 (0x0 << 1) // (HDMA) No effect. 04210 #define AT91C_HDMA_DIS1_1 (0x1 << 1) // (HDMA) Disables the channel 1. 04211 #define AT91C_HDMA_DIS2 (0x1 << 2) // (HDMA) Write one to this field to disable the channel 2. 04212 #define AT91C_HDMA_DIS2_0 (0x0 << 2) // (HDMA) No effect. 04213 #define AT91C_HDMA_DIS2_1 (0x1 << 2) // (HDMA) Disables the channel 2. 04214 #define AT91C_HDMA_DIS3 (0x1 << 3) // (HDMA) Write one to this field to disable the channel 3. 04215 #define AT91C_HDMA_DIS3_0 (0x0 << 3) // (HDMA) No effect. 04216 #define AT91C_HDMA_DIS3_1 (0x1 << 3) // (HDMA) Disables the channel 3. 04217 #define AT91C_HDMA_DIS4 (0x1 << 4) // (HDMA) Write one to this field to disable the channel 4. 04218 #define AT91C_HDMA_DIS4_0 (0x0 << 4) // (HDMA) No effect. 04219 #define AT91C_HDMA_DIS4_1 (0x1 << 4) // (HDMA) Disables the channel 4. 04220 #define AT91C_HDMA_DIS5 (0x1 << 5) // (HDMA) Write one to this field to disable the channel 5. 04221 #define AT91C_HDMA_DIS5_0 (0x0 << 5) // (HDMA) No effect. 04222 #define AT91C_HDMA_DIS5_1 (0x1 << 5) // (HDMA) Disables the channel 5. 04223 #define AT91C_HDMA_DIS6 (0x1 << 6) // (HDMA) Write one to this field to disable the channel 6. 04224 #define AT91C_HDMA_DIS6_0 (0x0 << 6) // (HDMA) No effect. 04225 #define AT91C_HDMA_DIS6_1 (0x1 << 6) // (HDMA) Disables the channel 6. 04226 #define AT91C_HDMA_DIS7 (0x1 << 7) // (HDMA) Write one to this field to disable the channel 7. 04227 #define AT91C_HDMA_DIS7_0 (0x0 << 7) // (HDMA) No effect. 04228 #define AT91C_HDMA_DIS7_1 (0x1 << 7) // (HDMA) Disables the channel 7. 04229 #define AT91C_HDMA_RES0 (0x1 << 8) // (HDMA) Write one to this field to resume the channel 0 transfer restoring its context. 04230 #define AT91C_HDMA_RES0_0 (0x0 << 8) // (HDMA) No effect. 04231 #define AT91C_HDMA_RES0_1 (0x1 << 8) // (HDMA) Resumes the channel 0. 04232 #define AT91C_HDMA_RES1 (0x1 << 9) // (HDMA) Write one to this field to resume the channel 1 transfer restoring its context. 04233 #define AT91C_HDMA_RES1_0 (0x0 << 9) // (HDMA) No effect. 04234 #define AT91C_HDMA_RES1_1 (0x1 << 9) // (HDMA) Resumes the channel 1. 04235 #define AT91C_HDMA_RES2 (0x1 << 10) // (HDMA) Write one to this field to resume the channel 2 transfer restoring its context. 04236 #define AT91C_HDMA_RES2_0 (0x0 << 10) // (HDMA) No effect. 04237 #define AT91C_HDMA_RES2_1 (0x1 << 10) // (HDMA) Resumes the channel 2. 04238 #define AT91C_HDMA_RES3 (0x1 << 11) // (HDMA) Write one to this field to resume the channel 3 transfer restoring its context. 04239 #define AT91C_HDMA_RES3_0 (0x0 << 11) // (HDMA) No effect. 04240 #define AT91C_HDMA_RES3_1 (0x1 << 11) // (HDMA) Resumes the channel 3. 04241 #define AT91C_HDMA_RES4 (0x1 << 12) // (HDMA) Write one to this field to resume the channel 4 transfer restoring its context. 04242 #define AT91C_HDMA_RES4_0 (0x0 << 12) // (HDMA) No effect. 04243 #define AT91C_HDMA_RES4_1 (0x1 << 12) // (HDMA) Resumes the channel 4. 04244 #define AT91C_HDMA_RES5 (0x1 << 13) // (HDMA) Write one to this field to resume the channel 5 transfer restoring its context. 04245 #define AT91C_HDMA_RES5_0 (0x0 << 13) // (HDMA) No effect. 04246 #define AT91C_HDMA_RES5_1 (0x1 << 13) // (HDMA) Resumes the channel 5. 04247 #define AT91C_HDMA_RES6 (0x1 << 14) // (HDMA) Write one to this field to resume the channel 6 transfer restoring its context. 04248 #define AT91C_HDMA_RES6_0 (0x0 << 14) // (HDMA) No effect. 04249 #define AT91C_HDMA_RES6_1 (0x1 << 14) // (HDMA) Resumes the channel 6. 04250 #define AT91C_HDMA_RES7 (0x1 << 15) // (HDMA) Write one to this field to resume the channel 7 transfer restoring its context. 04251 #define AT91C_HDMA_RES7_0 (0x0 << 15) // (HDMA) No effect. 04252 #define AT91C_HDMA_RES7_1 (0x1 << 15) // (HDMA) Resumes the channel 7. 04253 // -------- HDMA_CHSR : (HDMA Offset: 0x30) -------- 04254 #define AT91C_HDMA_EMPT0 (0x1 << 16) // (HDMA) When set, channel 0 is empty. 04255 #define AT91C_HDMA_EMPT0_0 (0x0 << 16) // (HDMA) No effect. 04256 #define AT91C_HDMA_EMPT0_1 (0x1 << 16) // (HDMA) Channel 0 empty. 04257 #define AT91C_HDMA_EMPT1 (0x1 << 17) // (HDMA) When set, channel 1 is empty. 04258 #define AT91C_HDMA_EMPT1_0 (0x0 << 17) // (HDMA) No effect. 04259 #define AT91C_HDMA_EMPT1_1 (0x1 << 17) // (HDMA) Channel 1 empty. 04260 #define AT91C_HDMA_EMPT2 (0x1 << 18) // (HDMA) When set, channel 2 is empty. 04261 #define AT91C_HDMA_EMPT2_0 (0x0 << 18) // (HDMA) No effect. 04262 #define AT91C_HDMA_EMPT2_1 (0x1 << 18) // (HDMA) Channel 2 empty. 04263 #define AT91C_HDMA_EMPT3 (0x1 << 19) // (HDMA) When set, channel 3 is empty. 04264 #define AT91C_HDMA_EMPT3_0 (0x0 << 19) // (HDMA) No effect. 04265 #define AT91C_HDMA_EMPT3_1 (0x1 << 19) // (HDMA) Channel 3 empty. 04266 #define AT91C_HDMA_EMPT4 (0x1 << 20) // (HDMA) When set, channel 4 is empty. 04267 #define AT91C_HDMA_EMPT4_0 (0x0 << 20) // (HDMA) No effect. 04268 #define AT91C_HDMA_EMPT4_1 (0x1 << 20) // (HDMA) Channel 4 empty. 04269 #define AT91C_HDMA_EMPT5 (0x1 << 21) // (HDMA) When set, channel 5 is empty. 04270 #define AT91C_HDMA_EMPT5_0 (0x0 << 21) // (HDMA) No effect. 04271 #define AT91C_HDMA_EMPT5_1 (0x1 << 21) // (HDMA) Channel 5 empty. 04272 #define AT91C_HDMA_EMPT6 (0x1 << 22) // (HDMA) When set, channel 6 is empty. 04273 #define AT91C_HDMA_EMPT6_0 (0x0 << 22) // (HDMA) No effect. 04274 #define AT91C_HDMA_EMPT6_1 (0x1 << 22) // (HDMA) Channel 6 empty. 04275 #define AT91C_HDMA_EMPT7 (0x1 << 23) // (HDMA) When set, channel 7 is empty. 04276 #define AT91C_HDMA_EMPT7_0 (0x0 << 23) // (HDMA) No effect. 04277 #define AT91C_HDMA_EMPT7_1 (0x1 << 23) // (HDMA) Channel 7 empty. 04278 #define AT91C_HDMA_STAL0 (0x1 << 24) // (HDMA) When set, channel 0 is stalled. 04279 #define AT91C_HDMA_STAL0_0 (0x0 << 24) // (HDMA) No effect. 04280 #define AT91C_HDMA_STAL0_1 (0x1 << 24) // (HDMA) Channel 0 stalled. 04281 #define AT91C_HDMA_STAL1 (0x1 << 25) // (HDMA) When set, channel 1 is stalled. 04282 #define AT91C_HDMA_STAL1_0 (0x0 << 25) // (HDMA) No effect. 04283 #define AT91C_HDMA_STAL1_1 (0x1 << 25) // (HDMA) Channel 1 stalled. 04284 #define AT91C_HDMA_STAL2 (0x1 << 26) // (HDMA) When set, channel 2 is stalled. 04285 #define AT91C_HDMA_STAL2_0 (0x0 << 26) // (HDMA) No effect. 04286 #define AT91C_HDMA_STAL2_1 (0x1 << 26) // (HDMA) Channel 2 stalled. 04287 #define AT91C_HDMA_STAL3 (0x1 << 27) // (HDMA) When set, channel 3 is stalled. 04288 #define AT91C_HDMA_STAL3_0 (0x0 << 27) // (HDMA) No effect. 04289 #define AT91C_HDMA_STAL3_1 (0x1 << 27) // (HDMA) Channel 3 stalled. 04290 #define AT91C_HDMA_STAL4 (0x1 << 28) // (HDMA) When set, channel 4 is stalled. 04291 #define AT91C_HDMA_STAL4_0 (0x0 << 28) // (HDMA) No effect. 04292 #define AT91C_HDMA_STAL4_1 (0x1 << 28) // (HDMA) Channel 4 stalled. 04293 #define AT91C_HDMA_STAL5 (0x1 << 29) // (HDMA) When set, channel 5 is stalled. 04294 #define AT91C_HDMA_STAL5_0 (0x0 << 29) // (HDMA) No effect. 04295 #define AT91C_HDMA_STAL5_1 (0x1 << 29) // (HDMA) Channel 5 stalled. 04296 #define AT91C_HDMA_STAL6 (0x1 << 30) // (HDMA) When set, channel 6 is stalled. 04297 #define AT91C_HDMA_STAL6_0 (0x0 << 30) // (HDMA) No effect. 04298 #define AT91C_HDMA_STAL6_1 (0x1 << 30) // (HDMA) Channel 6 stalled. 04299 #define AT91C_HDMA_STAL7 (0x1 << 31) // (HDMA) When set, channel 7 is stalled. 04300 #define AT91C_HDMA_STAL7_0 (0x0 << 31) // (HDMA) No effect. 04301 #define AT91C_HDMA_STAL7_1 (0x1 << 31) // (HDMA) Channel 7 stalled. 04302 // -------- HDMA_RSVD : (HDMA Offset: 0x34) -------- 04303 // -------- HDMA_RSVD : (HDMA Offset: 0x38) -------- 04304 // -------- HDMA_VER : (HDMA Offset: 0x1fc) -------- 04305 04306 // ***************************************************************************** 04307 // REGISTER ADDRESS DEFINITION FOR AT91SAM3U4 04308 // ***************************************************************************** 04309 // ========== Register definition for SYS peripheral ========== 04310 #define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0x400E1290) // (SYS) General Purpose Register 04311 // ========== Register definition for HSMC4_CS0 peripheral ========== 04312 #define AT91C_CS0_MODE (AT91_CAST(AT91_REG *) 0x400E0080) // (HSMC4_CS0) Mode Register 04313 #define AT91C_CS0_PULSE (AT91_CAST(AT91_REG *) 0x400E0074) // (HSMC4_CS0) Pulse Register 04314 #define AT91C_CS0_CYCLE (AT91_CAST(AT91_REG *) 0x400E0078) // (HSMC4_CS0) Cycle Register 04315 #define AT91C_CS0_TIMINGS (AT91_CAST(AT91_REG *) 0x400E007C) // (HSMC4_CS0) Timmings Register 04316 #define AT91C_CS0_SETUP (AT91_CAST(AT91_REG *) 0x400E0070) // (HSMC4_CS0) Setup Register 04317 // ========== Register definition for HSMC4_CS1 peripheral ========== 04318 #define AT91C_CS1_CYCLE (AT91_CAST(AT91_REG *) 0x400E008C) // (HSMC4_CS1) Cycle Register 04319 #define AT91C_CS1_PULSE (AT91_CAST(AT91_REG *) 0x400E0088) // (HSMC4_CS1) Pulse Register 04320 #define AT91C_CS1_MODE (AT91_CAST(AT91_REG *) 0x400E0094) // (HSMC4_CS1) Mode Register 04321 #define AT91C_CS1_SETUP (AT91_CAST(AT91_REG *) 0x400E0084) // (HSMC4_CS1) Setup Register 04322 #define AT91C_CS1_TIMINGS (AT91_CAST(AT91_REG *) 0x400E0090) // (HSMC4_CS1) Timmings Register 04323 // ========== Register definition for HSMC4_CS2 peripheral ========== 04324 #define AT91C_CS2_PULSE (AT91_CAST(AT91_REG *) 0x400E009C) // (HSMC4_CS2) Pulse Register 04325 #define AT91C_CS2_TIMINGS (AT91_CAST(AT91_REG *) 0x400E00A4) // (HSMC4_CS2) Timmings Register 04326 #define AT91C_CS2_CYCLE (AT91_CAST(AT91_REG *) 0x400E00A0) // (HSMC4_CS2) Cycle Register 04327 #define AT91C_CS2_MODE (AT91_CAST(AT91_REG *) 0x400E00A8) // (HSMC4_CS2) Mode Register 04328 #define AT91C_CS2_SETUP (AT91_CAST(AT91_REG *) 0x400E0098) // (HSMC4_CS2) Setup Register 04329 // ========== Register definition for HSMC4_CS3 peripheral ========== 04330 #define AT91C_CS3_MODE (AT91_CAST(AT91_REG *) 0x400E00BC) // (HSMC4_CS3) Mode Register 04331 #define AT91C_CS3_TIMINGS (AT91_CAST(AT91_REG *) 0x400E00B8) // (HSMC4_CS3) Timmings Register 04332 #define AT91C_CS3_SETUP (AT91_CAST(AT91_REG *) 0x400E00AC) // (HSMC4_CS3) Setup Register 04333 #define AT91C_CS3_CYCLE (AT91_CAST(AT91_REG *) 0x400E00B4) // (HSMC4_CS3) Cycle Register 04334 #define AT91C_CS3_PULSE (AT91_CAST(AT91_REG *) 0x400E00B0) // (HSMC4_CS3) Pulse Register 04335 // ========== Register definition for HSMC4_NFC peripheral ========== 04336 #define AT91C_NFC_MODE (AT91_CAST(AT91_REG *) 0x400E010C) // (HSMC4_NFC) Mode Register 04337 #define AT91C_NFC_CYCLE (AT91_CAST(AT91_REG *) 0x400E0104) // (HSMC4_NFC) Cycle Register 04338 #define AT91C_NFC_PULSE (AT91_CAST(AT91_REG *) 0x400E0100) // (HSMC4_NFC) Pulse Register 04339 #define AT91C_NFC_SETUP (AT91_CAST(AT91_REG *) 0x400E00FC) // (HSMC4_NFC) Setup Register 04340 #define AT91C_NFC_TIMINGS (AT91_CAST(AT91_REG *) 0x400E0108) // (HSMC4_NFC) Timmings Register 04341 // ========== Register definition for HSMC4 peripheral ========== 04342 #define AT91C_HSMC4_IPNAME1 (AT91_CAST(AT91_REG *) 0x400E01F0) // (HSMC4) Write Protection Status Register 04343 #define AT91C_HSMC4_ECCPR6 (AT91_CAST(AT91_REG *) 0x400E0048) // (HSMC4) ECC Parity register 6 04344 #define AT91C_HSMC4_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400E01EC) // (HSMC4) Write Protection Status Register 04345 #define AT91C_HSMC4_ECCPR11 (AT91_CAST(AT91_REG *) 0x400E005C) // (HSMC4) ECC Parity register 11 04346 #define AT91C_HSMC4_SR (AT91_CAST(AT91_REG *) 0x400E0008) // (HSMC4) Status Register 04347 #define AT91C_HSMC4_IMR (AT91_CAST(AT91_REG *) 0x400E0014) // (HSMC4) Interrupt Mask Register 04348 #define AT91C_HSMC4_WPSR (AT91_CAST(AT91_REG *) 0x400E01E8) // (HSMC4) Write Protection Status Register 04349 #define AT91C_HSMC4_BANK (AT91_CAST(AT91_REG *) 0x400E001C) // (HSMC4) Bank Register 04350 #define AT91C_HSMC4_ECCPR8 (AT91_CAST(AT91_REG *) 0x400E0050) // (HSMC4) ECC Parity register 8 04351 #define AT91C_HSMC4_WPCR (AT91_CAST(AT91_REG *) 0x400E01E4) // (HSMC4) Write Protection Control register 04352 #define AT91C_HSMC4_ECCPR2 (AT91_CAST(AT91_REG *) 0x400E0038) // (HSMC4) ECC Parity register 2 04353 #define AT91C_HSMC4_ECCPR1 (AT91_CAST(AT91_REG *) 0x400E0030) // (HSMC4) ECC Parity register 1 04354 #define AT91C_HSMC4_ECCSR2 (AT91_CAST(AT91_REG *) 0x400E0034) // (HSMC4) ECC Status register 2 04355 #define AT91C_HSMC4_OCMS (AT91_CAST(AT91_REG *) 0x400E0110) // (HSMC4) OCMS MODE register 04356 #define AT91C_HSMC4_ECCPR9 (AT91_CAST(AT91_REG *) 0x400E0054) // (HSMC4) ECC Parity register 9 04357 #define AT91C_HSMC4_DUMMY (AT91_CAST(AT91_REG *) 0x400E0200) // (HSMC4) This rtegister was created only ti have AHB constants 04358 #define AT91C_HSMC4_ECCPR5 (AT91_CAST(AT91_REG *) 0x400E0044) // (HSMC4) ECC Parity register 5 04359 #define AT91C_HSMC4_ECCCR (AT91_CAST(AT91_REG *) 0x400E0020) // (HSMC4) ECC reset register 04360 #define AT91C_HSMC4_KEY2 (AT91_CAST(AT91_REG *) 0x400E0118) // (HSMC4) KEY2 Register 04361 #define AT91C_HSMC4_IER (AT91_CAST(AT91_REG *) 0x400E000C) // (HSMC4) Interrupt Enable Register 04362 #define AT91C_HSMC4_ECCSR1 (AT91_CAST(AT91_REG *) 0x400E0028) // (HSMC4) ECC Status register 1 04363 #define AT91C_HSMC4_IDR (AT91_CAST(AT91_REG *) 0x400E0010) // (HSMC4) Interrupt Disable Register 04364 #define AT91C_HSMC4_ECCPR0 (AT91_CAST(AT91_REG *) 0x400E002C) // (HSMC4) ECC Parity register 0 04365 #define AT91C_HSMC4_FEATURES (AT91_CAST(AT91_REG *) 0x400E01F8) // (HSMC4) Write Protection Status Register 04366 #define AT91C_HSMC4_ECCPR7 (AT91_CAST(AT91_REG *) 0x400E004C) // (HSMC4) ECC Parity register 7 04367 #define AT91C_HSMC4_ECCPR12 (AT91_CAST(AT91_REG *) 0x400E0060) // (HSMC4) ECC Parity register 12 04368 #define AT91C_HSMC4_ECCPR10 (AT91_CAST(AT91_REG *) 0x400E0058) // (HSMC4) ECC Parity register 10 04369 #define AT91C_HSMC4_KEY1 (AT91_CAST(AT91_REG *) 0x400E0114) // (HSMC4) KEY1 Register 04370 #define AT91C_HSMC4_VER (AT91_CAST(AT91_REG *) 0x400E01FC) // (HSMC4) HSMC4 Version Register 04371 #define AT91C_HSMC4_Eccpr15 (AT91_CAST(AT91_REG *) 0x400E006C) // (HSMC4) ECC Parity register 15 04372 #define AT91C_HSMC4_ECCPR4 (AT91_CAST(AT91_REG *) 0x400E0040) // (HSMC4) ECC Parity register 4 04373 #define AT91C_HSMC4_IPNAME2 (AT91_CAST(AT91_REG *) 0x400E01F4) // (HSMC4) Write Protection Status Register 04374 #define AT91C_HSMC4_ECCCMD (AT91_CAST(AT91_REG *) 0x400E0024) // (HSMC4) ECC Page size register 04375 #define AT91C_HSMC4_ADDR (AT91_CAST(AT91_REG *) 0x400E0018) // (HSMC4) Address Cycle Zero Register 04376 #define AT91C_HSMC4_ECCPR3 (AT91_CAST(AT91_REG *) 0x400E003C) // (HSMC4) ECC Parity register 3 04377 #define AT91C_HSMC4_CFG (AT91_CAST(AT91_REG *) 0x400E0000) // (HSMC4) Configuration Register 04378 #define AT91C_HSMC4_CTRL (AT91_CAST(AT91_REG *) 0x400E0004) // (HSMC4) Control Register 04379 #define AT91C_HSMC4_ECCPR13 (AT91_CAST(AT91_REG *) 0x400E0064) // (HSMC4) ECC Parity register 13 04380 #define AT91C_HSMC4_ECCPR14 (AT91_CAST(AT91_REG *) 0x400E0068) // (HSMC4) ECC Parity register 14 04381 // ========== Register definition for MATRIX peripheral ========== 04382 #define AT91C_MATRIX_SFR2 (AT91_CAST(AT91_REG *) 0x400E0318) // (MATRIX) Special Function Register 2 04383 #define AT91C_MATRIX_SFR3 (AT91_CAST(AT91_REG *) 0x400E031C) // (MATRIX) Special Function Register 3 04384 #define AT91C_MATRIX_SCFG8 (AT91_CAST(AT91_REG *) 0x400E0260) // (MATRIX) Slave Configuration Register 8 04385 #define AT91C_MATRIX_MCFG2 (AT91_CAST(AT91_REG *) 0x400E0208) // (MATRIX) Master Configuration Register 2 04386 #define AT91C_MATRIX_MCFG7 (AT91_CAST(AT91_REG *) 0x400E021C) // (MATRIX) Master Configuration Register 7 04387 #define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x400E024C) // (MATRIX) Slave Configuration Register 3 04388 #define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x400E0240) // (MATRIX) Slave Configuration Register 0 04389 #define AT91C_MATRIX_SFR12 (AT91_CAST(AT91_REG *) 0x400E0340) // (MATRIX) Special Function Register 12 04390 #define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x400E0244) // (MATRIX) Slave Configuration Register 1 04391 #define AT91C_MATRIX_SFR8 (AT91_CAST(AT91_REG *) 0x400E0330) // (MATRIX) Special Function Register 8 04392 #define AT91C_MATRIX_VER (AT91_CAST(AT91_REG *) 0x400E03FC) // (MATRIX) HMATRIX2 VERSION REGISTER 04393 #define AT91C_MATRIX_SFR13 (AT91_CAST(AT91_REG *) 0x400E0344) // (MATRIX) Special Function Register 13 04394 #define AT91C_MATRIX_SFR5 (AT91_CAST(AT91_REG *) 0x400E0324) // (MATRIX) Special Function Register 5 04395 #define AT91C_MATRIX_MCFG0 (AT91_CAST(AT91_REG *) 0x400E0200) // (MATRIX) Master Configuration Register 0 : ARM I and D 04396 #define AT91C_MATRIX_SCFG6 (AT91_CAST(AT91_REG *) 0x400E0258) // (MATRIX) Slave Configuration Register 6 04397 #define AT91C_MATRIX_SFR14 (AT91_CAST(AT91_REG *) 0x400E0348) // (MATRIX) Special Function Register 14 04398 #define AT91C_MATRIX_SFR1 (AT91_CAST(AT91_REG *) 0x400E0314) // (MATRIX) Special Function Register 1 04399 #define AT91C_MATRIX_SFR15 (AT91_CAST(AT91_REG *) 0x400E034C) // (MATRIX) Special Function Register 15 04400 #define AT91C_MATRIX_SFR6 (AT91_CAST(AT91_REG *) 0x400E0328) // (MATRIX) Special Function Register 6 04401 #define AT91C_MATRIX_SFR11 (AT91_CAST(AT91_REG *) 0x400E033C) // (MATRIX) Special Function Register 11 04402 #define AT91C_MATRIX_IPNAME2 (AT91_CAST(AT91_REG *) 0x400E03F4) // (MATRIX) HMATRIX2 IPNAME2 REGISTER 04403 #define AT91C_MATRIX_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400E03EC) // (MATRIX) HMATRIX2 ADDRSIZE REGISTER 04404 #define AT91C_MATRIX_MCFG5 (AT91_CAST(AT91_REG *) 0x400E0214) // (MATRIX) Master Configuration Register 5 04405 #define AT91C_MATRIX_SFR9 (AT91_CAST(AT91_REG *) 0x400E0334) // (MATRIX) Special Function Register 9 04406 #define AT91C_MATRIX_MCFG3 (AT91_CAST(AT91_REG *) 0x400E020C) // (MATRIX) Master Configuration Register 3 04407 #define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x400E0250) // (MATRIX) Slave Configuration Register 4 04408 #define AT91C_MATRIX_MCFG1 (AT91_CAST(AT91_REG *) 0x400E0204) // (MATRIX) Master Configuration Register 1 : ARM S 04409 #define AT91C_MATRIX_SCFG7 (AT91_CAST(AT91_REG *) 0x400E025C) // (MATRIX) Slave Configuration Register 5 04410 #define AT91C_MATRIX_SFR10 (AT91_CAST(AT91_REG *) 0x400E0338) // (MATRIX) Special Function Register 10 04411 #define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x400E0248) // (MATRIX) Slave Configuration Register 2 04412 #define AT91C_MATRIX_SFR7 (AT91_CAST(AT91_REG *) 0x400E032C) // (MATRIX) Special Function Register 7 04413 #define AT91C_MATRIX_IPNAME1 (AT91_CAST(AT91_REG *) 0x400E03F0) // (MATRIX) HMATRIX2 IPNAME1 REGISTER 04414 #define AT91C_MATRIX_MCFG4 (AT91_CAST(AT91_REG *) 0x400E0210) // (MATRIX) Master Configuration Register 4 04415 #define AT91C_MATRIX_SFR0 (AT91_CAST(AT91_REG *) 0x400E0310) // (MATRIX) Special Function Register 0 04416 #define AT91C_MATRIX_FEATURES (AT91_CAST(AT91_REG *) 0x400E03F8) // (MATRIX) HMATRIX2 FEATURES REGISTER 04417 #define AT91C_MATRIX_SCFG5 (AT91_CAST(AT91_REG *) 0x400E0254) // (MATRIX) Slave Configuration Register 5 04418 #define AT91C_MATRIX_MCFG6 (AT91_CAST(AT91_REG *) 0x400E0218) // (MATRIX) Master Configuration Register 6 04419 #define AT91C_MATRIX_SCFG9 (AT91_CAST(AT91_REG *) 0x400E0264) // (MATRIX) Slave Configuration Register 9 04420 #define AT91C_MATRIX_SFR4 (AT91_CAST(AT91_REG *) 0x400E0320) // (MATRIX) Special Function Register 4 04421 // ========== Register definition for NVIC peripheral ========== 04422 #define AT91C_NVIC_MMAR (AT91_CAST(AT91_REG *) 0xE000ED34) // (NVIC) Mem Manage Address Register 04423 #define AT91C_NVIC_STIR (AT91_CAST(AT91_REG *) 0xE000EF00) // (NVIC) Software Trigger Interrupt Register 04424 #define AT91C_NVIC_MMFR2 (AT91_CAST(AT91_REG *) 0xE000ED58) // (NVIC) Memory Model Feature register2 04425 #define AT91C_NVIC_CPUID (AT91_CAST(AT91_REG *) 0xE000ED00) // (NVIC) CPUID Base Register 04426 #define AT91C_NVIC_DFSR (AT91_CAST(AT91_REG *) 0xE000ED30) // (NVIC) Debug Fault Status Register 04427 #define AT91C_NVIC_HAND4PR (AT91_CAST(AT91_REG *) 0xE000ED18) // (NVIC) System Handlers 4-7 Priority Register 04428 #define AT91C_NVIC_HFSR (AT91_CAST(AT91_REG *) 0xE000ED2C) // (NVIC) Hard Fault Status Register 04429 #define AT91C_NVIC_PID6 (AT91_CAST(AT91_REG *) 0xE000EFD8) // (NVIC) Peripheral identification register 04430 #define AT91C_NVIC_PFR0 (AT91_CAST(AT91_REG *) 0xE000ED40) // (NVIC) Processor Feature register0 04431 #define AT91C_NVIC_VTOFFR (AT91_CAST(AT91_REG *) 0xE000ED08) // (NVIC) Vector Table Offset Register 04432 #define AT91C_NVIC_ISPR (AT91_CAST(AT91_REG *) 0xE000E200) // (NVIC) Set Pending Register 04433 #define AT91C_NVIC_PID0 (AT91_CAST(AT91_REG *) 0xE000EFE0) // (NVIC) Peripheral identification register b7:0 04434 #define AT91C_NVIC_PID7 (AT91_CAST(AT91_REG *) 0xE000EFDC) // (NVIC) Peripheral identification register 04435 #define AT91C_NVIC_STICKRVR (AT91_CAST(AT91_REG *) 0xE000E014) // (NVIC) SysTick Reload Value Register 04436 #define AT91C_NVIC_PID2 (AT91_CAST(AT91_REG *) 0xE000EFE8) // (NVIC) Peripheral identification register b23:16 04437 #define AT91C_NVIC_ISAR0 (AT91_CAST(AT91_REG *) 0xE000ED60) // (NVIC) ISA Feature register0 04438 #define AT91C_NVIC_SCR (AT91_CAST(AT91_REG *) 0xE000ED10) // (NVIC) System Control Register 04439 #define AT91C_NVIC_PID4 (AT91_CAST(AT91_REG *) 0xE000EFD0) // (NVIC) Peripheral identification register 04440 #define AT91C_NVIC_ISAR2 (AT91_CAST(AT91_REG *) 0xE000ED68) // (NVIC) ISA Feature register2 04441 #define AT91C_NVIC_ISER (AT91_CAST(AT91_REG *) 0xE000E100) // (NVIC) Set Enable Register 04442 #define AT91C_NVIC_IPR (AT91_CAST(AT91_REG *) 0xE000E400) // (NVIC) Interrupt Mask Register 04443 #define AT91C_NVIC_AIRCR (AT91_CAST(AT91_REG *) 0xE000ED0C) // (NVIC) Application Interrupt/Reset Control Reg 04444 #define AT91C_NVIC_CID2 (AT91_CAST(AT91_REG *) 0xE000EFF8) // (NVIC) Component identification register b23:16 04445 #define AT91C_NVIC_ICPR (AT91_CAST(AT91_REG *) 0xE000E280) // (NVIC) Clear Pending Register 04446 #define AT91C_NVIC_CID3 (AT91_CAST(AT91_REG *) 0xE000EFFC) // (NVIC) Component identification register b31:24 04447 #define AT91C_NVIC_CFSR (AT91_CAST(AT91_REG *) 0xE000ED28) // (NVIC) Configurable Fault Status Register 04448 #define AT91C_NVIC_AFR0 (AT91_CAST(AT91_REG *) 0xE000ED4C) // (NVIC) Auxiliary Feature register0 04449 #define AT91C_NVIC_ICSR (AT91_CAST(AT91_REG *) 0xE000ED04) // (NVIC) Interrupt Control State Register 04450 #define AT91C_NVIC_CCR (AT91_CAST(AT91_REG *) 0xE000ED14) // (NVIC) Configuration Control Register 04451 #define AT91C_NVIC_CID0 (AT91_CAST(AT91_REG *) 0xE000EFF0) // (NVIC) Component identification register b7:0 04452 #define AT91C_NVIC_ISAR1 (AT91_CAST(AT91_REG *) 0xE000ED64) // (NVIC) ISA Feature register1 04453 #define AT91C_NVIC_STICKCVR (AT91_CAST(AT91_REG *) 0xE000E018) // (NVIC) SysTick Current Value Register 04454 #define AT91C_NVIC_STICKCSR (AT91_CAST(AT91_REG *) 0xE000E010) // (NVIC) SysTick Control and Status Register 04455 #define AT91C_NVIC_CID1 (AT91_CAST(AT91_REG *) 0xE000EFF4) // (NVIC) Component identification register b15:8 04456 #define AT91C_NVIC_DFR0 (AT91_CAST(AT91_REG *) 0xE000ED48) // (NVIC) Debug Feature register0 04457 #define AT91C_NVIC_MMFR3 (AT91_CAST(AT91_REG *) 0xE000ED5C) // (NVIC) Memory Model Feature register3 04458 #define AT91C_NVIC_MMFR0 (AT91_CAST(AT91_REG *) 0xE000ED50) // (NVIC) Memory Model Feature register0 04459 #define AT91C_NVIC_STICKCALVR (AT91_CAST(AT91_REG *) 0xE000E01C) // (NVIC) SysTick Calibration Value Register 04460 #define AT91C_NVIC_PID1 (AT91_CAST(AT91_REG *) 0xE000EFE4) // (NVIC) Peripheral identification register b15:8 04461 #define AT91C_NVIC_HAND12PR (AT91_CAST(AT91_REG *) 0xE000ED20) // (NVIC) System Handlers 12-15 Priority Register 04462 #define AT91C_NVIC_MMFR1 (AT91_CAST(AT91_REG *) 0xE000ED54) // (NVIC) Memory Model Feature register1 04463 #define AT91C_NVIC_AFSR (AT91_CAST(AT91_REG *) 0xE000ED3C) // (NVIC) Auxiliary Fault Status Register 04464 #define AT91C_NVIC_HANDCSR (AT91_CAST(AT91_REG *) 0xE000ED24) // (NVIC) System Handler Control and State Register 04465 #define AT91C_NVIC_ISAR4 (AT91_CAST(AT91_REG *) 0xE000ED70) // (NVIC) ISA Feature register4 04466 #define AT91C_NVIC_ABR (AT91_CAST(AT91_REG *) 0xE000E300) // (NVIC) Active Bit Register 04467 #define AT91C_NVIC_PFR1 (AT91_CAST(AT91_REG *) 0xE000ED44) // (NVIC) Processor Feature register1 04468 #define AT91C_NVIC_PID5 (AT91_CAST(AT91_REG *) 0xE000EFD4) // (NVIC) Peripheral identification register 04469 #define AT91C_NVIC_ICTR (AT91_CAST(AT91_REG *) 0xE000E004) // (NVIC) Interrupt Control Type Register 04470 #define AT91C_NVIC_ICER (AT91_CAST(AT91_REG *) 0xE000E180) // (NVIC) Clear enable Register 04471 #define AT91C_NVIC_PID3 (AT91_CAST(AT91_REG *) 0xE000EFEC) // (NVIC) Peripheral identification register b31:24 04472 #define AT91C_NVIC_ISAR3 (AT91_CAST(AT91_REG *) 0xE000ED6C) // (NVIC) ISA Feature register3 04473 #define AT91C_NVIC_HAND8PR (AT91_CAST(AT91_REG *) 0xE000ED1C) // (NVIC) System Handlers 8-11 Priority Register 04474 #define AT91C_NVIC_BFAR (AT91_CAST(AT91_REG *) 0xE000ED38) // (NVIC) Bus Fault Address Register 04475 // ========== Register definition for MPU peripheral ========== 04476 #define AT91C_MPU_REG_BASE_ADDR3 (AT91_CAST(AT91_REG *) 0xE000EDB4) // (MPU) MPU Region Base Address Register alias 3 04477 #define AT91C_MPU_REG_NB (AT91_CAST(AT91_REG *) 0xE000ED98) // (MPU) MPU Region Number Register 04478 #define AT91C_MPU_ATTR_SIZE1 (AT91_CAST(AT91_REG *) 0xE000EDA8) // (MPU) MPU Attribute and Size Register alias 1 04479 #define AT91C_MPU_REG_BASE_ADDR1 (AT91_CAST(AT91_REG *) 0xE000EDA4) // (MPU) MPU Region Base Address Register alias 1 04480 #define AT91C_MPU_ATTR_SIZE3 (AT91_CAST(AT91_REG *) 0xE000EDB8) // (MPU) MPU Attribute and Size Register alias 3 04481 #define AT91C_MPU_CTRL (AT91_CAST(AT91_REG *) 0xE000ED94) // (MPU) MPU Control Register 04482 #define AT91C_MPU_ATTR_SIZE2 (AT91_CAST(AT91_REG *) 0xE000EDB0) // (MPU) MPU Attribute and Size Register alias 2 04483 #define AT91C_MPU_REG_BASE_ADDR (AT91_CAST(AT91_REG *) 0xE000ED9C) // (MPU) MPU Region Base Address Register 04484 #define AT91C_MPU_REG_BASE_ADDR2 (AT91_CAST(AT91_REG *) 0xE000EDAC) // (MPU) MPU Region Base Address Register alias 2 04485 #define AT91C_MPU_ATTR_SIZE (AT91_CAST(AT91_REG *) 0xE000EDA0) // (MPU) MPU Attribute and Size Register 04486 #define AT91C_MPU_TYPE (AT91_CAST(AT91_REG *) 0xE000ED90) // (MPU) MPU Type Register 04487 // ========== Register definition for CM3 peripheral ========== 04488 #define AT91C_CM3_SHCSR (AT91_CAST(AT91_REG *) 0xE000ED24) // (CM3) System Handler Control and State Register 04489 #define AT91C_CM3_CCR (AT91_CAST(AT91_REG *) 0xE000ED14) // (CM3) Configuration Control Register 04490 #define AT91C_CM3_ICSR (AT91_CAST(AT91_REG *) 0xE000ED04) // (CM3) Interrupt Control State Register 04491 #define AT91C_CM3_CPUID (AT91_CAST(AT91_REG *) 0xE000ED00) // (CM3) CPU ID Base Register 04492 #define AT91C_CM3_SCR (AT91_CAST(AT91_REG *) 0xE000ED10) // (CM3) System Controller Register 04493 #define AT91C_CM3_AIRCR (AT91_CAST(AT91_REG *) 0xE000ED0C) // (CM3) Application Interrupt and Reset Control Register 04494 #define AT91C_CM3_SHPR (AT91_CAST(AT91_REG *) 0xE000ED18) // (CM3) System Handler Priority Register 04495 #define AT91C_CM3_VTOR (AT91_CAST(AT91_REG *) 0xE000ED08) // (CM3) Vector Table Offset Register 04496 // ========== Register definition for PDC_DBGU peripheral ========== 04497 #define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0x400E0708) // (PDC_DBGU) Transmit Pointer Register 04498 #define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0x400E0720) // (PDC_DBGU) PDC Transfer Control Register 04499 #define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0x400E071C) // (PDC_DBGU) Transmit Next Counter Register 04500 #define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0x400E0724) // (PDC_DBGU) PDC Transfer Status Register 04501 #define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0x400E0714) // (PDC_DBGU) Receive Next Counter Register 04502 #define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0x400E0700) // (PDC_DBGU) Receive Pointer Register 04503 #define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0x400E070C) // (PDC_DBGU) Transmit Counter Register 04504 #define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0x400E0710) // (PDC_DBGU) Receive Next Pointer Register 04505 #define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0x400E0718) // (PDC_DBGU) Transmit Next Pointer Register 04506 #define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0x400E0704) // (PDC_DBGU) Receive Counter Register 04507 // ========== Register definition for DBGU peripheral ========== 04508 #define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0x400E0600) // (DBGU) Control Register 04509 #define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0x400E060C) // (DBGU) Interrupt Disable Register 04510 #define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0x400E0740) // (DBGU) Chip ID Register 04511 #define AT91C_DBGU_IPNAME2 (AT91_CAST(AT91_REG *) 0x400E06F4) // (DBGU) DBGU IPNAME2 REGISTER 04512 #define AT91C_DBGU_FEATURES (AT91_CAST(AT91_REG *) 0x400E06F8) // (DBGU) DBGU FEATURES REGISTER 04513 #define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0x400E0648) // (DBGU) Force NTRST Register 04514 #define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0x400E0618) // (DBGU) Receiver Holding Register 04515 #define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0x400E061C) // (DBGU) Transmitter Holding Register 04516 #define AT91C_DBGU_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400E06EC) // (DBGU) DBGU ADDRSIZE REGISTER 04517 #define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0x400E0604) // (DBGU) Mode Register 04518 #define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0x400E0608) // (DBGU) Interrupt Enable Register 04519 #define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0x400E0620) // (DBGU) Baud Rate Generator Register 04520 #define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0x400E0614) // (DBGU) Channel Status Register 04521 #define AT91C_DBGU_VER (AT91_CAST(AT91_REG *) 0x400E06FC) // (DBGU) DBGU VERSION REGISTER 04522 #define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0x400E0610) // (DBGU) Interrupt Mask Register 04523 #define AT91C_DBGU_IPNAME1 (AT91_CAST(AT91_REG *) 0x400E06F0) // (DBGU) DBGU IPNAME1 REGISTER 04524 #define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0x400E0744) // (DBGU) Chip ID Extension Register 04525 // ========== Register definition for PIOA peripheral ========== 04526 #define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0x400E0C04) // (PIOA) PIO Disable Register 04527 #define AT91C_PIOA_FRLHSR (AT91_CAST(AT91_REG *) 0x400E0CD8) // (PIOA) Fall/Rise - Low/High Status Register 04528 #define AT91C_PIOA_KIMR (AT91_CAST(AT91_REG *) 0x400E0D38) // (PIOA) Keypad Controller Interrupt Mask Register 04529 #define AT91C_PIOA_LSR (AT91_CAST(AT91_REG *) 0x400E0CC4) // (PIOA) Level Select Register 04530 #define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0x400E0C28) // (PIOA) Input Filter Status Register 04531 #define AT91C_PIOA_KKRR (AT91_CAST(AT91_REG *) 0x400E0D44) // (PIOA) Keypad Controller Key Release Register 04532 #define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0x400E0C14) // (PIOA) Output Disable Registerr 04533 #define AT91C_PIOA_SCIFSR (AT91_CAST(AT91_REG *) 0x400E0C80) // (PIOA) System Clock Glitch Input Filter Select Register 04534 #define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0x400E0C00) // (PIOA) PIO Enable Register 04535 #define AT91C_PIOA_VER (AT91_CAST(AT91_REG *) 0x400E0CFC) // (PIOA) PIO VERSION REGISTER 04536 #define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0x400E0CA8) // (PIOA) Output Write Status Register 04537 #define AT91C_PIOA_KSR (AT91_CAST(AT91_REG *) 0x400E0D3C) // (PIOA) Keypad Controller Status Register 04538 #define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0x400E0C48) // (PIOA) Interrupt Mask Register 04539 #define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0x400E0CA4) // (PIOA) Output Write Disable Register 04540 #define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0x400E0C58) // (PIOA) Multi-driver Status Register 04541 #define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0x400E0C24) // (PIOA) Input Filter Disable Register 04542 #define AT91C_PIOA_AIMDR (AT91_CAST(AT91_REG *) 0x400E0CB4) // (PIOA) Additional Interrupt Modes Disables Register 04543 #define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0x400E0C34) // (PIOA) Clear Output Data Register 04544 #define AT91C_PIOA_SCDR (AT91_CAST(AT91_REG *) 0x400E0C8C) // (PIOA) Slow Clock Divider Debouncing Register 04545 #define AT91C_PIOA_KIER (AT91_CAST(AT91_REG *) 0x400E0D30) // (PIOA) Keypad Controller Interrupt Enable Register 04546 #define AT91C_PIOA_REHLSR (AT91_CAST(AT91_REG *) 0x400E0CD4) // (PIOA) Rising Edge/ High Level Select Register 04547 #define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0x400E0C4C) // (PIOA) Interrupt Status Register 04548 #define PIOA_ISR (AT91_CAST(AT91_REG *) 0x400E0C4C) // (PIOA) Interrupt Status Register 04549 #define AT91C_PIOA_ESR (AT91_CAST(AT91_REG *) 0x400E0CC0) // (PIOA) Edge Select Register 04550 #define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0x400E0C60) // (PIOA) Pull-up Disable Register 04551 #define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0x400E0C54) // (PIOA) Multi-driver Disable Register 04552 #define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0x400E0C08) // (PIOA) PIO Status Register 04553 #define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0x400E0C3C) // (PIOA) Pin Data Status Register 04554 #define AT91C_PIOA_IFDGSR (AT91_CAST(AT91_REG *) 0x400E0C88) // (PIOA) Glitch or Debouncing Input Filter Clock Selection Status Register 04555 #define AT91C_PIOA_FELLSR (AT91_CAST(AT91_REG *) 0x400E0CD0) // (PIOA) Falling Edge/Low Level Select Register 04556 #define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0x400E0C68) // (PIOA) Pull-up Status Register 04557 #define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0x400E0C10) // (PIOA) Output Enable Register 04558 #define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0x400E0C18) // (PIOA) Output Status Register 04559 #define AT91C_PIOA_KKPR (AT91_CAST(AT91_REG *) 0x400E0D40) // (PIOA) Keypad Controller Key Press Register 04560 #define AT91C_PIOA_AIMMR (AT91_CAST(AT91_REG *) 0x400E0CB8) // (PIOA) Additional Interrupt Modes Mask Register 04561 #define AT91C_PIOA_KRCR (AT91_CAST(AT91_REG *) 0x400E0D24) // (PIOA) Keypad Controller Row Column Register 04562 #define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0x400E0C40) // (PIOA) Interrupt Enable Register 04563 #define AT91C_PIOA_KER (AT91_CAST(AT91_REG *) 0x400E0D20) // (PIOA) Keypad Controller Enable Register 04564 #define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0x400E0C64) // (PIOA) Pull-up Enable Register 04565 #define AT91C_PIOA_KIDR (AT91_CAST(AT91_REG *) 0x400E0D34) // (PIOA) Keypad Controller Interrupt Disable Register 04566 #define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0x400E0C70) // (PIOA) Peripheral AB Select Register 04567 #define AT91C_PIOA_LOCKSR (AT91_CAST(AT91_REG *) 0x400E0CE0) // (PIOA) Lock Status Register 04568 #define AT91C_PIOA_DIFSR (AT91_CAST(AT91_REG *) 0x400E0C84) // (PIOA) Debouncing Input Filter Select Register 04569 #define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0x400E0C50) // (PIOA) Multi-driver Enable Register 04570 #define AT91C_PIOA_AIMER (AT91_CAST(AT91_REG *) 0x400E0CB0) // (PIOA) Additional Interrupt Modes Enable Register 04571 #define AT91C_PIOA_ELSR (AT91_CAST(AT91_REG *) 0x400E0CC8) // (PIOA) Edge/Level Status Register 04572 #define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0x400E0C20) // (PIOA) Input Filter Enable Register 04573 #define AT91C_PIOA_KDR (AT91_CAST(AT91_REG *) 0x400E0D28) // (PIOA) Keypad Controller Debouncing Register 04574 #define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0x400E0C44) // (PIOA) Interrupt Disable Register 04575 #define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0x400E0CA0) // (PIOA) Output Write Enable Register 04576 #define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0x400E0C38) // (PIOA) Output Data Status Register 04577 #define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0x400E0C30) // (PIOA) Set Output Data Register 04578 // ========== Register definition for PIOB peripheral ========== 04579 #define AT91C_PIOB_KIDR (AT91_CAST(AT91_REG *) 0x400E0F34) // (PIOB) Keypad Controller Interrupt Disable Register 04580 #define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0x400E0EA8) // (PIOB) Output Write Status Register 04581 #define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0x400E0E08) // (PIOB) PIO Status Register 04582 #define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0x400E0E50) // (PIOB) Multi-driver Enable Register 04583 #define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0x400E0E14) // (PIOB) Output Disable Registerr 04584 #define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0x400E0E44) // (PIOB) Interrupt Disable Register 04585 #define AT91C_PIOB_AIMER (AT91_CAST(AT91_REG *) 0x400E0EB0) // (PIOB) Additional Interrupt Modes Enable Register 04586 #define AT91C_PIOB_DIFSR (AT91_CAST(AT91_REG *) 0x400E0E84) // (PIOB) Debouncing Input Filter Select Register 04587 #define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0x400E0E04) // (PIOB) PIO Disable Register 04588 #define AT91C_PIOB_REHLSR (AT91_CAST(AT91_REG *) 0x400E0ED4) // (PIOB) Rising Edge/ High Level Select Register 04589 #define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0x400E0E3C) // (PIOB) Pin Data Status Register 04590 #define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0x400E0E60) // (PIOB) Pull-up Disable Register 04591 #define AT91C_PIOB_LSR (AT91_CAST(AT91_REG *) 0x400E0EC4) // (PIOB) Level Select Register 04592 #define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0x400E0EA4) // (PIOB) Output Write Disable Register 04593 #define AT91C_PIOB_FELLSR (AT91_CAST(AT91_REG *) 0x400E0ED0) // (PIOB) Falling Edge/Low Level Select Register 04594 #define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0x400E0E20) // (PIOB) Input Filter Enable Register 04595 #define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0x400E0E70) // (PIOB) Peripheral AB Select Register 04596 #define AT91C_PIOB_KIMR (AT91_CAST(AT91_REG *) 0x400E0F38) // (PIOB) Keypad Controller Interrupt Mask Register 04597 #define AT91C_PIOB_KKPR (AT91_CAST(AT91_REG *) 0x400E0F40) // (PIOB) Keypad Controller Key Press Register 04598 #define AT91C_PIOB_FRLHSR (AT91_CAST(AT91_REG *) 0x400E0ED8) // (PIOB) Fall/Rise - Low/High Status Register 04599 #define AT91C_PIOB_AIMDR (AT91_CAST(AT91_REG *) 0x400E0EB4) // (PIOB) Additional Interrupt Modes Disables Register 04600 #define AT91C_PIOB_SCIFSR (AT91_CAST(AT91_REG *) 0x400E0E80) // (PIOB) System Clock Glitch Input Filter Select Register 04601 #define AT91C_PIOB_VER (AT91_CAST(AT91_REG *) 0x400E0EFC) // (PIOB) PIO VERSION REGISTER 04602 #define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0x400E0E00) // (PIOB) PIO Enable Register 04603 #define AT91C_PIOB_ELSR (AT91_CAST(AT91_REG *) 0x400E0EC8) // (PIOB) Edge/Level Status Register 04604 #define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0x400E0E48) // (PIOB) Interrupt Mask Register 04605 #define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0x400E0E68) // (PIOB) Pull-up Status Register 04606 #define AT91C_PIOB_SCDR (AT91_CAST(AT91_REG *) 0x400E0E8C) // (PIOB) Slow Clock Divider Debouncing Register 04607 #define AT91C_PIOB_KSR (AT91_CAST(AT91_REG *) 0x400E0F3C) // (PIOB) Keypad Controller Status Register 04608 #define AT91C_PIOB_IFDGSR (AT91_CAST(AT91_REG *) 0x400E0E88) // (PIOB) Glitch or Debouncing Input Filter Clock Selection Status Register 04609 #define AT91C_PIOB_ESR (AT91_CAST(AT91_REG *) 0x400E0EC0) // (PIOB) Edge Select Register 04610 #define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0x400E0E38) // (PIOB) Output Data Status Register 04611 #define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0x400E0E24) // (PIOB) Input Filter Disable Register 04612 #define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0x400E0E30) // (PIOB) Set Output Data Register 04613 #define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0x400E0E40) // (PIOB) Interrupt Enable Register 04614 #define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0x400E0E58) // (PIOB) Multi-driver Status Register 04615 #define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0x400E0E4C) // (PIOB) Interrupt Status Register 04616 #define PIOB_ISR (AT91_CAST(AT91_REG *) 0x400E0E4C) // (PIOB) Interrupt Status Register 04617 #define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0x400E0E28) // (PIOB) Input Filter Status Register 04618 #define AT91C_PIOB_KER (AT91_CAST(AT91_REG *) 0x400E0F20) // (PIOB) Keypad Controller Enable Register 04619 #define AT91C_PIOB_KKRR (AT91_CAST(AT91_REG *) 0x400E0F44) // (PIOB) Keypad Controller Key Release Register 04620 #define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0x400E0E64) // (PIOB) Pull-up Enable Register 04621 #define AT91C_PIOB_LOCKSR (AT91_CAST(AT91_REG *) 0x400E0EE0) // (PIOB) Lock Status Register 04622 #define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0x400E0EA0) // (PIOB) Output Write Enable Register 04623 #define AT91C_PIOB_KIER (AT91_CAST(AT91_REG *) 0x400E0F30) // (PIOB) Keypad Controller Interrupt Enable Register 04624 #define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0x400E0E54) // (PIOB) Multi-driver Disable Register 04625 #define AT91C_PIOB_KRCR (AT91_CAST(AT91_REG *) 0x400E0F24) // (PIOB) Keypad Controller Row Column Register 04626 #define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0x400E0E34) // (PIOB) Clear Output Data Register 04627 #define AT91C_PIOB_KDR (AT91_CAST(AT91_REG *) 0x400E0F28) // (PIOB) Keypad Controller Debouncing Register 04628 #define AT91C_PIOB_AIMMR (AT91_CAST(AT91_REG *) 0x400E0EB8) // (PIOB) Additional Interrupt Modes Mask Register 04629 #define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0x400E0E10) // (PIOB) Output Enable Register 04630 #define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0x400E0E18) // (PIOB) Output Status Register 04631 // ========== Register definition for PIOC peripheral ========== 04632 #define AT91C_PIOC_FELLSR (AT91_CAST(AT91_REG *) 0x400E10D0) // (PIOC) Falling Edge/Low Level Select Register 04633 #define AT91C_PIOC_FRLHSR (AT91_CAST(AT91_REG *) 0x400E10D8) // (PIOC) Fall/Rise - Low/High Status Register 04634 #define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0x400E1054) // (PIOC) Multi-driver Disable Register 04635 #define AT91C_PIOC_IFDGSR (AT91_CAST(AT91_REG *) 0x400E1088) // (PIOC) Glitch or Debouncing Input Filter Clock Selection Status Register 04636 #define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0x400E1070) // (PIOC) Peripheral AB Select Register 04637 #define AT91C_PIOC_KIMR (AT91_CAST(AT91_REG *) 0x400E1138) // (PIOC) Keypad Controller Interrupt Mask Register 04638 #define AT91C_PIOC_KRCR (AT91_CAST(AT91_REG *) 0x400E1124) // (PIOC) Keypad Controller Row Column Register 04639 #define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0x400E1038) // (PIOC) Output Data Status Register 04640 #define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0x400E1018) // (PIOC) Output Status Register 04641 #define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0x400E1020) // (PIOC) Input Filter Enable Register 04642 #define AT91C_PIOC_KKPR (AT91_CAST(AT91_REG *) 0x400E1140) // (PIOC) Keypad Controller Key Press Register 04643 #define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0x400E1058) // (PIOC) Multi-driver Status Register 04644 #define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0x400E1024) // (PIOC) Input Filter Disable Register 04645 #define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0x400E1050) // (PIOC) Multi-driver Enable Register 04646 #define AT91C_PIOC_SCDR (AT91_CAST(AT91_REG *) 0x400E108C) // (PIOC) Slow Clock Divider Debouncing Register 04647 #define AT91C_PIOC_SCIFSR (AT91_CAST(AT91_REG *) 0x400E1080) // (PIOC) System Clock Glitch Input Filter Select Register 04648 #define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0x400E1040) // (PIOC) Interrupt Enable Register 04649 #define AT91C_PIOC_KDR (AT91_CAST(AT91_REG *) 0x400E1128) // (PIOC) Keypad Controller Debouncing Register 04650 #define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0x400E10A4) // (PIOC) Output Write Disable Register 04651 #define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0x400E1028) // (PIOC) Input Filter Status Register 04652 #define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0x400E104C) // (PIOC) Interrupt Status Register 04653 #define PIOC_ISR (AT91_CAST(AT91_REG *) 0x400E104C) // (PIOC) Interrupt Status Register 04654 #define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0x400E1060) // (PIOC) Pull-up Disable Register 04655 #define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0x400E103C) // (PIOC) Pin Data Status Register 04656 #define AT91C_PIOC_KKRR (AT91_CAST(AT91_REG *) 0x400E1144) // (PIOC) Keypad Controller Key Release Register 04657 #define AT91C_PIOC_AIMDR (AT91_CAST(AT91_REG *) 0x400E10B4) // (PIOC) Additional Interrupt Modes Disables Register 04658 #define AT91C_PIOC_LSR (AT91_CAST(AT91_REG *) 0x400E10C4) // (PIOC) Level Select Register 04659 #define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0x400E1064) // (PIOC) Pull-up Enable Register 04660 #define AT91C_PIOC_AIMER (AT91_CAST(AT91_REG *) 0x400E10B0) // (PIOC) Additional Interrupt Modes Enable Register 04661 #define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0x400E1010) // (PIOC) Output Enable Register 04662 #define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0x400E1034) // (PIOC) Clear Output Data Register 04663 #define AT91C_PIOC_AIMMR (AT91_CAST(AT91_REG *) 0x400E10B8) // (PIOC) Additional Interrupt Modes Mask Register 04664 #define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0x400E10A0) // (PIOC) Output Write Enable Register 04665 #define AT91C_PIOC_VER (AT91_CAST(AT91_REG *) 0x400E10FC) // (PIOC) PIO VERSION REGISTER 04666 #define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0x400E1048) // (PIOC) Interrupt Mask Register 04667 #define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0x400E1068) // (PIOC) Pull-up Status Register 04668 #define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0x400E1044) // (PIOC) Interrupt Disable Register 04669 #define AT91C_PIOC_DIFSR (AT91_CAST(AT91_REG *) 0x400E1084) // (PIOC) Debouncing Input Filter Select Register 04670 #define AT91C_PIOC_KIDR (AT91_CAST(AT91_REG *) 0x400E1134) // (PIOC) Keypad Controller Interrupt Disable Register 04671 #define AT91C_PIOC_KSR (AT91_CAST(AT91_REG *) 0x400E113C) // (PIOC) Keypad Controller Status Register 04672 #define AT91C_PIOC_REHLSR (AT91_CAST(AT91_REG *) 0x400E10D4) // (PIOC) Rising Edge/ High Level Select Register 04673 #define AT91C_PIOC_ESR (AT91_CAST(AT91_REG *) 0x400E10C0) // (PIOC) Edge Select Register 04674 #define AT91C_PIOC_KIER (AT91_CAST(AT91_REG *) 0x400E1130) // (PIOC) Keypad Controller Interrupt Enable Register 04675 #define AT91C_PIOC_ELSR (AT91_CAST(AT91_REG *) 0x400E10C8) // (PIOC) Edge/Level Status Register 04676 #define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0x400E1030) // (PIOC) Set Output Data Register 04677 #define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0x400E1008) // (PIOC) PIO Status Register 04678 #define AT91C_PIOC_KER (AT91_CAST(AT91_REG *) 0x400E1120) // (PIOC) Keypad Controller Enable Register 04679 #define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0x400E1014) // (PIOC) Output Disable Registerr 04680 #define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0x400E10A8) // (PIOC) Output Write Status Register 04681 #define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0x400E1004) // (PIOC) PIO Disable Register 04682 #define AT91C_PIOC_LOCKSR (AT91_CAST(AT91_REG *) 0x400E10E0) // (PIOC) Lock Status Register 04683 #define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0x400E1000) // (PIOC) PIO Enable Register 04684 // ========== Register definition for PMC peripheral ========== 04685 #define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0x400E0428) // (PMC) PLL Register 04686 #define AT91C_PMC_UCKR (AT91_CAST(AT91_REG *) 0x400E041C) // (PMC) UTMI Clock Configuration Register 04687 #define AT91C_PMC_FSMR (AT91_CAST(AT91_REG *) 0x400E0470) // (PMC) Fast Startup Mode Register 04688 #define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0x400E0430) // (PMC) Master Clock Register 04689 #define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0x400E0400) // (PMC) System Clock Enable Register 04690 #define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0x400E0418) // (PMC) Peripheral Clock Status Register 04691 #define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0x400E0424) // (PMC) Main Clock Frequency Register 04692 #define AT91C_PMC_FOCR (AT91_CAST(AT91_REG *) 0x400E0478) // (PMC) Fault Output Clear Register 04693 #define AT91C_PMC_FSPR (AT91_CAST(AT91_REG *) 0x400E0474) // (PMC) Fast Startup Polarity Register 04694 #define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0x400E0408) // (PMC) System Clock Status Register 04695 #define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0x400E0464) // (PMC) Interrupt Disable Register 04696 #define AT91C_PMC_VER (AT91_CAST(AT91_REG *) 0x400E04FC) // (PMC) APMC VERSION REGISTER 04697 #define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0x400E046C) // (PMC) Interrupt Mask Register 04698 #define AT91C_PMC_IPNAME2 (AT91_CAST(AT91_REG *) 0x400E04F4) // (PMC) PMC IPNAME2 REGISTER 04699 #define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0x400E0404) // (PMC) System Clock Disable Register 04700 #define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0x400E0440) // (PMC) Programmable Clock Register 04701 #define AT91C_PMC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400E04EC) // (PMC) PMC ADDRSIZE REGISTER 04702 #define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0x400E0414) // (PMC) Peripheral Clock Disable Register 04703 #define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0x400E0420) // (PMC) Main Oscillator Register 04704 #define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0x400E0468) // (PMC) Status Register 04705 #define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0x400E0460) // (PMC) Interrupt Enable Register 04706 #define AT91C_PMC_IPNAME1 (AT91_CAST(AT91_REG *) 0x400E04F0) // (PMC) PMC IPNAME1 REGISTER 04707 #define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0x400E0410) // (PMC) Peripheral Clock Enable Register 04708 #define AT91C_PMC_FEATURES (AT91_CAST(AT91_REG *) 0x400E04F8) // (PMC) PMC FEATURES REGISTER 04709 // ========== Register definition for CKGR peripheral ========== 04710 #define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x400E0428) // (CKGR) PLL Register 04711 #define AT91C_CKGR_UCKR (AT91_CAST(AT91_REG *) 0x400E041C) // (CKGR) UTMI Clock Configuration Register 04712 #define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0x400E0420) // (CKGR) Main Oscillator Register 04713 #define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0x400E0424) // (CKGR) Main Clock Frequency Register 04714 // ========== Register definition for RSTC peripheral ========== 04715 #define AT91C_RSTC_VER (AT91_CAST(AT91_REG *) 0x400E12FC) // (RSTC) Version Register 04716 #define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0x400E1200) // (RSTC) Reset Control Register 04717 #define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0x400E1208) // (RSTC) Reset Mode Register 04718 #define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0x400E1204) // (RSTC) Reset Status Register 04719 // ========== Register definition for SUPC peripheral ========== 04720 #define AT91C_SUPC_CR (AT91_CAST(AT91_REG *) 0x400E1210) // (SUPC) Supply Controller Control Register 04721 #define AT91C_SUPC_SMMR (AT91_CAST(AT91_REG *) 0x400E1214) // (SUPC) Supply Controller Supply Monitor Mode Register 04722 #define AT91C_SUPC_MR (AT91_CAST(AT91_REG *) 0x400E1218) // (SUPC) Supply Controller Mode Register 04723 #define AT91C_SUPC_WUMR (AT91_CAST(AT91_REG *) 0x400E121C) // (SUPC) Supply Controller Wake Up Mode Register 04724 #define AT91C_SUPC_WUIR (AT91_CAST(AT91_REG *) 0x400E1220) // (SUPC) Supply Controller Wake Up Inputs Register 04725 #define AT91C_SUPC_SR (AT91_CAST(AT91_REG *) 0x400E1224) // (SUPC) Supply Controller Status Register 04726 // ========== Register definition for RTTC peripheral ========== 04727 #define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0x400E1238) // (RTTC) Real-time Value Register 04728 #define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0x400E1234) // (RTTC) Real-time Alarm Register 04729 #define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0x400E1230) // (RTTC) Real-time Mode Register 04730 #define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0x400E123C) // (RTTC) Real-time Status Register 04731 // ========== Register definition for WDTC peripheral ========== 04732 #define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0x400E1258) // (WDTC) Watchdog Status Register 04733 #define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0x400E1254) // (WDTC) Watchdog Mode Register 04734 #define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0x400E1250) // (WDTC) Watchdog Control Register 04735 // ========== Register definition for RTC peripheral ========== 04736 #define AT91C_RTC_IMR (AT91_CAST(AT91_REG *) 0x400E1288) // (RTC) Interrupt Mask Register 04737 #define AT91C_RTC_SCCR (AT91_CAST(AT91_REG *) 0x400E127C) // (RTC) Status Clear Command Register 04738 #define AT91C_RTC_CALR (AT91_CAST(AT91_REG *) 0x400E126C) // (RTC) Calendar Register 04739 #define AT91C_RTC_MR (AT91_CAST(AT91_REG *) 0x400E1264) // (RTC) Mode Register 04740 #define AT91C_RTC_TIMR (AT91_CAST(AT91_REG *) 0x400E1268) // (RTC) Time Register 04741 #define AT91C_RTC_CALALR (AT91_CAST(AT91_REG *) 0x400E1274) // (RTC) Calendar Alarm Register 04742 #define AT91C_RTC_VER (AT91_CAST(AT91_REG *) 0x400E128C) // (RTC) Valid Entry Register 04743 #define AT91C_RTC_CR (AT91_CAST(AT91_REG *) 0x400E1260) // (RTC) Control Register 04744 #define AT91C_RTC_IDR (AT91_CAST(AT91_REG *) 0x400E1284) // (RTC) Interrupt Disable Register 04745 #define AT91C_RTC_TIMALR (AT91_CAST(AT91_REG *) 0x400E1270) // (RTC) Time Alarm Register 04746 #define AT91C_RTC_IER (AT91_CAST(AT91_REG *) 0x400E1280) // (RTC) Interrupt Enable Register 04747 #define AT91C_RTC_SR (AT91_CAST(AT91_REG *) 0x400E1278) // (RTC) Status Register 04748 // ========== Register definition for ADC0 peripheral ========== 04749 #define AT91C_ADC0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400AC0F4) // (ADC0) ADC IPNAME2 REGISTER 04750 #define AT91C_ADC0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400AC0EC) // (ADC0) ADC ADDRSIZE REGISTER 04751 #define AT91C_ADC0_IDR (AT91_CAST(AT91_REG *) 0x400AC028) // (ADC0) ADC Interrupt Disable Register 04752 #define AT91C_ADC0_CHSR (AT91_CAST(AT91_REG *) 0x400AC018) // (ADC0) ADC Channel Status Register 04753 #define AT91C_ADC0_FEATURES (AT91_CAST(AT91_REG *) 0x400AC0F8) // (ADC0) ADC FEATURES REGISTER 04754 #define AT91C_ADC0_CDR0 (AT91_CAST(AT91_REG *) 0x400AC030) // (ADC0) ADC Channel Data Register 0 04755 #define AT91C_ADC0_LCDR (AT91_CAST(AT91_REG *) 0x400AC020) // (ADC0) ADC Last Converted Data Register 04756 #define AT91C_ADC0_EMR (AT91_CAST(AT91_REG *) 0x400AC068) // (ADC0) Extended Mode Register 04757 #define AT91C_ADC0_CDR3 (AT91_CAST(AT91_REG *) 0x400AC03C) // (ADC0) ADC Channel Data Register 3 04758 #define AT91C_ADC0_CDR7 (AT91_CAST(AT91_REG *) 0x400AC04C) // (ADC0) ADC Channel Data Register 7 04759 #define AT91C_ADC0_SR (AT91_CAST(AT91_REG *) 0x400AC01C) // (ADC0) ADC Status Register 04760 #define AT91C_ADC0_ACR (AT91_CAST(AT91_REG *) 0x400AC064) // (ADC0) Analog Control Register 04761 #define AT91C_ADC0_CDR5 (AT91_CAST(AT91_REG *) 0x400AC044) // (ADC0) ADC Channel Data Register 5 04762 #define AT91C_ADC0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400AC0F0) // (ADC0) ADC IPNAME1 REGISTER 04763 #define AT91C_ADC0_CDR6 (AT91_CAST(AT91_REG *) 0x400AC048) // (ADC0) ADC Channel Data Register 6 04764 #define AT91C_ADC0_MR (AT91_CAST(AT91_REG *) 0x400AC004) // (ADC0) ADC Mode Register 04765 #define AT91C_ADC0_CDR1 (AT91_CAST(AT91_REG *) 0x400AC034) // (ADC0) ADC Channel Data Register 1 04766 #define AT91C_ADC0_CDR2 (AT91_CAST(AT91_REG *) 0x400AC038) // (ADC0) ADC Channel Data Register 2 04767 #define AT91C_ADC0_CDR4 (AT91_CAST(AT91_REG *) 0x400AC040) // (ADC0) ADC Channel Data Register 4 04768 #define AT91C_ADC0_CHER (AT91_CAST(AT91_REG *) 0x400AC010) // (ADC0) ADC Channel Enable Register 04769 #define AT91C_ADC0_VER (AT91_CAST(AT91_REG *) 0x400AC0FC) // (ADC0) ADC VERSION REGISTER 04770 #define AT91C_ADC0_CHDR (AT91_CAST(AT91_REG *) 0x400AC014) // (ADC0) ADC Channel Disable Register 04771 #define AT91C_ADC0_CR (AT91_CAST(AT91_REG *) 0x400AC000) // (ADC0) ADC Control Register 04772 #define AT91C_ADC0_IMR (AT91_CAST(AT91_REG *) 0x400AC02C) // (ADC0) ADC Interrupt Mask Register 04773 #define AT91C_ADC0_IER (AT91_CAST(AT91_REG *) 0x400AC024) // (ADC0) ADC Interrupt Enable Register 04774 // ========== Register definition for ADC12B peripheral ========== 04775 #define AT91C_ADC12B_CR (AT91_CAST(AT91_REG *) 0x400A8000) // (ADC12B) Control Register 04776 #define AT91C_ADC12B_MR (AT91_CAST(AT91_REG *) 0x400A8004) // (ADC12B) Mode Register 04777 #define AT91C_ADC12B_CHER (AT91_CAST(AT91_REG *) 0x400A8010) // (ADC12B) Channel Enable Register 04778 #define AT91C_ADC12B_CHDR (AT91_CAST(AT91_REG *) 0x400A8014) // (ADC12B) Channel Disable Register 04779 #define AT91C_ADC12B_CHSR (AT91_CAST(AT91_REG *) 0x400A8018) // (ADC12B) Channel Status Register 04780 #define AT91C_ADC12B_SR (AT91_CAST(AT91_REG *) 0x400A801C) // (ADC12B) Status Register 04781 #define AT91C_ADC12B_LCDR (AT91_CAST(AT91_REG *) 0x400A8020) // (ADC12B) Last Converted Data Register 04782 #define AT91C_ADC12B_IER (AT91_CAST(AT91_REG *) 0x400A8024) // (ADC12B) Interrupt Enable Register 04783 #define AT91C_ADC12B_IDR (AT91_CAST(AT91_REG *) 0x400A8028) // (ADC12B) Interrupt Disable Register 04784 #define AT91C_ADC12B_IMR (AT91_CAST(AT91_REG *) 0x400A802C) // (ADC12B) Interrupt Mask Register 04785 #define AT91C_ADC12B_CDR (AT91_CAST(AT91_REG *) 0x400A8030) // (ADC12B) Channel Data Register 04786 #define AT91C_ADC12B_ACR (AT91_CAST(AT91_REG *) 0x400A8064) // (ADC12B) Analog Control Register 04787 #define AT91C_ADC12B_EMR (AT91_CAST(AT91_REG *) 0x400A8068) // (ADC12B) Extended Mode Register 04788 // ========== Register definition for TC0 peripheral ========== 04789 #define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0x40080024) // (TC0) Interrupt Enable Register 04790 #define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0x40080010) // (TC0) Counter Value 04791 #define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0x40080014) // (TC0) Register A 04792 #define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0x40080018) // (TC0) Register B 04793 #define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0x40080028) // (TC0) Interrupt Disable Register 04794 #define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0x40080020) // (TC0) Status Register 04795 #define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0x4008002C) // (TC0) Interrupt Mask Register 04796 #define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0x40080004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) 04797 #define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0x4008001C) // (TC0) Register C 04798 #define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0x40080000) // (TC0) Channel Control Register 04799 // ========== Register definition for TC1 peripheral ========== 04800 #define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0x40080060) // (TC1) Status Register 04801 #define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0x40080054) // (TC1) Register A 04802 #define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0x40080064) // (TC1) Interrupt Enable Register 04803 #define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0x40080058) // (TC1) Register B 04804 #define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0x40080068) // (TC1) Interrupt Disable Register 04805 #define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0x40080040) // (TC1) Channel Control Register 04806 #define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0x4008006C) // (TC1) Interrupt Mask Register 04807 #define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0x4008005C) // (TC1) Register C 04808 #define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0x40080044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) 04809 #define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0x40080050) // (TC1) Counter Value 04810 // ========== Register definition for TC2 peripheral ========== 04811 #define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0x40080094) // (TC2) Register A 04812 #define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0x40080098) // (TC2) Register B 04813 #define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0x40080084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) 04814 #define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0x400800A0) // (TC2) Status Register 04815 #define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0x40080080) // (TC2) Channel Control Register 04816 #define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0x400800AC) // (TC2) Interrupt Mask Register 04817 #define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0x40080090) // (TC2) Counter Value 04818 #define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0x4008009C) // (TC2) Register C 04819 #define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0x400800A4) // (TC2) Interrupt Enable Register 04820 #define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0x400800A8) // (TC2) Interrupt Disable Register 04821 // ========== Register definition for TCB0 peripheral ========== 04822 #define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0x400800C0) // (TCB0) TC Block Control Register 04823 #define AT91C_TCB0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400800F4) // (TCB0) TC IPNAME2 REGISTER 04824 #define AT91C_TCB0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400800F0) // (TCB0) TC IPNAME1 REGISTER 04825 #define AT91C_TCB0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400800EC) // (TCB0) TC ADDRSIZE REGISTER 04826 #define AT91C_TCB0_FEATURES (AT91_CAST(AT91_REG *) 0x400800F8) // (TCB0) TC FEATURES REGISTER 04827 #define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0x400800C4) // (TCB0) TC Block Mode Register 04828 #define AT91C_TCB0_VER (AT91_CAST(AT91_REG *) 0x400800FC) // (TCB0) Version Register 04829 // ========== Register definition for TCB1 peripheral ========== 04830 #define AT91C_TCB1_BCR (AT91_CAST(AT91_REG *) 0x40080100) // (TCB1) TC Block Control Register 04831 #define AT91C_TCB1_VER (AT91_CAST(AT91_REG *) 0x4008013C) // (TCB1) Version Register 04832 #define AT91C_TCB1_FEATURES (AT91_CAST(AT91_REG *) 0x40080138) // (TCB1) TC FEATURES REGISTER 04833 #define AT91C_TCB1_IPNAME2 (AT91_CAST(AT91_REG *) 0x40080134) // (TCB1) TC IPNAME2 REGISTER 04834 #define AT91C_TCB1_BMR (AT91_CAST(AT91_REG *) 0x40080104) // (TCB1) TC Block Mode Register 04835 #define AT91C_TCB1_ADDRSIZE (AT91_CAST(AT91_REG *) 0x4008012C) // (TCB1) TC ADDRSIZE REGISTER 04836 #define AT91C_TCB1_IPNAME1 (AT91_CAST(AT91_REG *) 0x40080130) // (TCB1) TC IPNAME1 REGISTER 04837 // ========== Register definition for TCB2 peripheral ========== 04838 #define AT91C_TCB2_FEATURES (AT91_CAST(AT91_REG *) 0x40080178) // (TCB2) TC FEATURES REGISTER 04839 #define AT91C_TCB2_VER (AT91_CAST(AT91_REG *) 0x4008017C) // (TCB2) Version Register 04840 #define AT91C_TCB2_ADDRSIZE (AT91_CAST(AT91_REG *) 0x4008016C) // (TCB2) TC ADDRSIZE REGISTER 04841 #define AT91C_TCB2_IPNAME1 (AT91_CAST(AT91_REG *) 0x40080170) // (TCB2) TC IPNAME1 REGISTER 04842 #define AT91C_TCB2_IPNAME2 (AT91_CAST(AT91_REG *) 0x40080174) // (TCB2) TC IPNAME2 REGISTER 04843 #define AT91C_TCB2_BMR (AT91_CAST(AT91_REG *) 0x40080144) // (TCB2) TC Block Mode Register 04844 #define AT91C_TCB2_BCR (AT91_CAST(AT91_REG *) 0x40080140) // (TCB2) TC Block Control Register 04845 // ========== Register definition for EFC0 peripheral ========== 04846 #define AT91C_EFC0_FCR (AT91_CAST(AT91_REG *) 0x400E0804) // (EFC0) EFC Flash Command Register 04847 #define AT91C_EFC0_FRR (AT91_CAST(AT91_REG *) 0x400E080C) // (EFC0) EFC Flash Result Register 04848 #define AT91C_EFC0_FMR (AT91_CAST(AT91_REG *) 0x400E0800) // (EFC0) EFC Flash Mode Register 04849 #define AT91C_EFC0_FSR (AT91_CAST(AT91_REG *) 0x400E0808) // (EFC0) EFC Flash Status Register 04850 #define AT91C_EFC0_FVR (AT91_CAST(AT91_REG *) 0x400E0814) // (EFC0) EFC Flash Version Register 04851 // ========== Register definition for EFC1 peripheral ========== 04852 #define AT91C_EFC1_FMR (AT91_CAST(AT91_REG *) 0x400E0A00) // (EFC1) EFC Flash Mode Register 04853 #define AT91C_EFC1_FVR (AT91_CAST(AT91_REG *) 0x400E0A14) // (EFC1) EFC Flash Version Register 04854 #define AT91C_EFC1_FSR (AT91_CAST(AT91_REG *) 0x400E0A08) // (EFC1) EFC Flash Status Register 04855 #define AT91C_EFC1_FCR (AT91_CAST(AT91_REG *) 0x400E0A04) // (EFC1) EFC Flash Command Register 04856 #define AT91C_EFC1_FRR (AT91_CAST(AT91_REG *) 0x400E0A0C) // (EFC1) EFC Flash Result Register 04857 // ========== Register definition for MCI0 peripheral ========== 04858 #define AT91C_MCI0_DMA (AT91_CAST(AT91_REG *) 0x40000050) // (MCI0) MCI DMA Configuration Register 04859 #define AT91C_MCI0_SDCR (AT91_CAST(AT91_REG *) 0x4000000C) // (MCI0) MCI SD/SDIO Card Register 04860 #define AT91C_MCI0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400000F0) // (MCI0) MCI IPNAME1 REGISTER 04861 #define AT91C_MCI0_CSTOR (AT91_CAST(AT91_REG *) 0x4000001C) // (MCI0) MCI Completion Signal Timeout Register 04862 #define AT91C_MCI0_RDR (AT91_CAST(AT91_REG *) 0x40000030) // (MCI0) MCI Receive Data Register 04863 #define AT91C_MCI0_CMDR (AT91_CAST(AT91_REG *) 0x40000014) // (MCI0) MCI Command Register 04864 #define AT91C_MCI0_IDR (AT91_CAST(AT91_REG *) 0x40000048) // (MCI0) MCI Interrupt Disable Register 04865 #define AT91C_MCI0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400000EC) // (MCI0) MCI ADDRSIZE REGISTER 04866 #define AT91C_MCI0_WPCR (AT91_CAST(AT91_REG *) 0x400000E4) // (MCI0) MCI Write Protection Control Register 04867 #define AT91C_MCI0_RSPR (AT91_CAST(AT91_REG *) 0x40000020) // (MCI0) MCI Response Register 04868 #define AT91C_MCI0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400000F4) // (MCI0) MCI IPNAME2 REGISTER 04869 #define AT91C_MCI0_CR (AT91_CAST(AT91_REG *) 0x40000000) // (MCI0) MCI Control Register 04870 #define AT91C_MCI0_IMR (AT91_CAST(AT91_REG *) 0x4000004C) // (MCI0) MCI Interrupt Mask Register 04871 #define AT91C_MCI0_WPSR (AT91_CAST(AT91_REG *) 0x400000E8) // (MCI0) MCI Write Protection Status Register 04872 #define AT91C_MCI0_DTOR (AT91_CAST(AT91_REG *) 0x40000008) // (MCI0) MCI Data Timeout Register 04873 #define AT91C_MCI0_MR (AT91_CAST(AT91_REG *) 0x40000004) // (MCI0) MCI Mode Register 04874 #define AT91C_MCI0_SR (AT91_CAST(AT91_REG *) 0x40000040) // (MCI0) MCI Status Register 04875 #define AT91C_MCI0_IER (AT91_CAST(AT91_REG *) 0x40000044) // (MCI0) MCI Interrupt Enable Register 04876 #define AT91C_MCI0_VER (AT91_CAST(AT91_REG *) 0x400000FC) // (MCI0) MCI VERSION REGISTER 04877 #define AT91C_MCI0_FEATURES (AT91_CAST(AT91_REG *) 0x400000F8) // (MCI0) MCI FEATURES REGISTER 04878 #define AT91C_MCI0_BLKR (AT91_CAST(AT91_REG *) 0x40000018) // (MCI0) MCI Block Register 04879 #define AT91C_MCI0_ARGR (AT91_CAST(AT91_REG *) 0x40000010) // (MCI0) MCI Argument Register 04880 #define AT91C_MCI0_FIFO (AT91_CAST(AT91_REG *) 0x40000200) // (MCI0) MCI FIFO Aperture Register 04881 #define AT91C_MCI0_TDR (AT91_CAST(AT91_REG *) 0x40000034) // (MCI0) MCI Transmit Data Register 04882 #define AT91C_MCI0_CFG (AT91_CAST(AT91_REG *) 0x40000054) // (MCI0) MCI Configuration Register 04883 // ========== Register definition for PDC_TWI0 peripheral ========== 04884 #define AT91C_TWI0_TNCR (AT91_CAST(AT91_REG *) 0x4008411C) // (PDC_TWI0) Transmit Next Counter Register 04885 #define AT91C_TWI0_PTCR (AT91_CAST(AT91_REG *) 0x40084120) // (PDC_TWI0) PDC Transfer Control Register 04886 #define AT91C_TWI0_PTSR (AT91_CAST(AT91_REG *) 0x40084124) // (PDC_TWI0) PDC Transfer Status Register 04887 #define AT91C_TWI0_RCR (AT91_CAST(AT91_REG *) 0x40084104) // (PDC_TWI0) Receive Counter Register 04888 #define AT91C_TWI0_TNPR (AT91_CAST(AT91_REG *) 0x40084118) // (PDC_TWI0) Transmit Next Pointer Register 04889 #define AT91C_TWI0_RNPR (AT91_CAST(AT91_REG *) 0x40084110) // (PDC_TWI0) Receive Next Pointer Register 04890 #define AT91C_TWI0_RPR (AT91_CAST(AT91_REG *) 0x40084100) // (PDC_TWI0) Receive Pointer Register 04891 #define AT91C_TWI0_RNCR (AT91_CAST(AT91_REG *) 0x40084114) // (PDC_TWI0) Receive Next Counter Register 04892 #define AT91C_TWI0_TPR (AT91_CAST(AT91_REG *) 0x40084108) // (PDC_TWI0) Transmit Pointer Register 04893 #define AT91C_TWI0_TCR (AT91_CAST(AT91_REG *) 0x4008410C) // (PDC_TWI0) Transmit Counter Register 04894 // ========== Register definition for PDC_TWI1 peripheral ========== 04895 #define AT91C_TWI1_TNCR (AT91_CAST(AT91_REG *) 0x4008811C) // (PDC_TWI1) Transmit Next Counter Register 04896 #define AT91C_TWI1_PTCR (AT91_CAST(AT91_REG *) 0x40088120) // (PDC_TWI1) PDC Transfer Control Register 04897 #define AT91C_TWI1_RNCR (AT91_CAST(AT91_REG *) 0x40088114) // (PDC_TWI1) Receive Next Counter Register 04898 #define AT91C_TWI1_RCR (AT91_CAST(AT91_REG *) 0x40088104) // (PDC_TWI1) Receive Counter Register 04899 #define AT91C_TWI1_RPR (AT91_CAST(AT91_REG *) 0x40088100) // (PDC_TWI1) Receive Pointer Register 04900 #define AT91C_TWI1_TNPR (AT91_CAST(AT91_REG *) 0x40088118) // (PDC_TWI1) Transmit Next Pointer Register 04901 #define AT91C_TWI1_RNPR (AT91_CAST(AT91_REG *) 0x40088110) // (PDC_TWI1) Receive Next Pointer Register 04902 #define AT91C_TWI1_TCR (AT91_CAST(AT91_REG *) 0x4008810C) // (PDC_TWI1) Transmit Counter Register 04903 #define AT91C_TWI1_TPR (AT91_CAST(AT91_REG *) 0x40088108) // (PDC_TWI1) Transmit Pointer Register 04904 #define AT91C_TWI1_PTSR (AT91_CAST(AT91_REG *) 0x40088124) // (PDC_TWI1) PDC Transfer Status Register 04905 // ========== Register definition for TWI0 peripheral ========== 04906 #define AT91C_TWI0_FEATURES (AT91_CAST(AT91_REG *) 0x400840F8) // (TWI0) TWI FEATURES REGISTER 04907 #define AT91C_TWI0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400840F0) // (TWI0) TWI IPNAME1 REGISTER 04908 #define AT91C_TWI0_SMR (AT91_CAST(AT91_REG *) 0x40084008) // (TWI0) Slave Mode Register 04909 #define AT91C_TWI0_MMR (AT91_CAST(AT91_REG *) 0x40084004) // (TWI0) Master Mode Register 04910 #define AT91C_TWI0_SR (AT91_CAST(AT91_REG *) 0x40084020) // (TWI0) Status Register 04911 #define AT91C_TWI0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400840F4) // (TWI0) TWI IPNAME2 REGISTER 04912 #define AT91C_TWI0_CR (AT91_CAST(AT91_REG *) 0x40084000) // (TWI0) Control Register 04913 #define AT91C_TWI0_IER (AT91_CAST(AT91_REG *) 0x40084024) // (TWI0) Interrupt Enable Register 04914 #define AT91C_TWI0_RHR (AT91_CAST(AT91_REG *) 0x40084030) // (TWI0) Receive Holding Register 04915 #define AT91C_TWI0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400840EC) // (TWI0) TWI ADDRSIZE REGISTER 04916 #define AT91C_TWI0_THR (AT91_CAST(AT91_REG *) 0x40084034) // (TWI0) Transmit Holding Register 04917 #define AT91C_TWI0_VER (AT91_CAST(AT91_REG *) 0x400840FC) // (TWI0) Version Register 04918 #define AT91C_TWI0_IADR (AT91_CAST(AT91_REG *) 0x4008400C) // (TWI0) Internal Address Register 04919 #define AT91C_TWI0_IMR (AT91_CAST(AT91_REG *) 0x4008402C) // (TWI0) Interrupt Mask Register 04920 #define AT91C_TWI0_CWGR (AT91_CAST(AT91_REG *) 0x40084010) // (TWI0) Clock Waveform Generator Register 04921 #define AT91C_TWI0_IDR (AT91_CAST(AT91_REG *) 0x40084028) // (TWI0) Interrupt Disable Register 04922 // ========== Register definition for TWI1 peripheral ========== 04923 #define AT91C_TWI1_VER (AT91_CAST(AT91_REG *) 0x400880FC) // (TWI1) Version Register 04924 #define AT91C_TWI1_IDR (AT91_CAST(AT91_REG *) 0x40088028) // (TWI1) Interrupt Disable Register 04925 #define AT91C_TWI1_IPNAME2 (AT91_CAST(AT91_REG *) 0x400880F4) // (TWI1) TWI IPNAME2 REGISTER 04926 #define AT91C_TWI1_CWGR (AT91_CAST(AT91_REG *) 0x40088010) // (TWI1) Clock Waveform Generator Register 04927 #define AT91C_TWI1_CR (AT91_CAST(AT91_REG *) 0x40088000) // (TWI1) Control Register 04928 #define AT91C_TWI1_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400880EC) // (TWI1) TWI ADDRSIZE REGISTER 04929 #define AT91C_TWI1_IADR (AT91_CAST(AT91_REG *) 0x4008800C) // (TWI1) Internal Address Register 04930 #define AT91C_TWI1_IER (AT91_CAST(AT91_REG *) 0x40088024) // (TWI1) Interrupt Enable Register 04931 #define AT91C_TWI1_SMR (AT91_CAST(AT91_REG *) 0x40088008) // (TWI1) Slave Mode Register 04932 #define AT91C_TWI1_RHR (AT91_CAST(AT91_REG *) 0x40088030) // (TWI1) Receive Holding Register 04933 #define AT91C_TWI1_FEATURES (AT91_CAST(AT91_REG *) 0x400880F8) // (TWI1) TWI FEATURES REGISTER 04934 #define AT91C_TWI1_IMR (AT91_CAST(AT91_REG *) 0x4008802C) // (TWI1) Interrupt Mask Register 04935 #define AT91C_TWI1_SR (AT91_CAST(AT91_REG *) 0x40088020) // (TWI1) Status Register 04936 #define AT91C_TWI1_THR (AT91_CAST(AT91_REG *) 0x40088034) // (TWI1) Transmit Holding Register 04937 #define AT91C_TWI1_MMR (AT91_CAST(AT91_REG *) 0x40088004) // (TWI1) Master Mode Register 04938 #define AT91C_TWI1_IPNAME1 (AT91_CAST(AT91_REG *) 0x400880F0) // (TWI1) TWI IPNAME1 REGISTER 04939 // ========== Register definition for PDC_US0 peripheral ========== 04940 #define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0x40090114) // (PDC_US0) Receive Next Counter Register 04941 #define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0x40090118) // (PDC_US0) Transmit Next Pointer Register 04942 #define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0x40090108) // (PDC_US0) Transmit Pointer Register 04943 #define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0x40090104) // (PDC_US0) Receive Counter Register 04944 #define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0x40090110) // (PDC_US0) Receive Next Pointer Register 04945 #define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0x4009011C) // (PDC_US0) Transmit Next Counter Register 04946 #define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0x40090124) // (PDC_US0) PDC Transfer Status Register 04947 #define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0x40090100) // (PDC_US0) Receive Pointer Register 04948 #define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0x40090120) // (PDC_US0) PDC Transfer Control Register 04949 #define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0x4009010C) // (PDC_US0) Transmit Counter Register 04950 // ========== Register definition for US0 peripheral ========== 04951 #define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0x40090044) // (US0) Nb Errors Register 04952 #define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0x40090018) // (US0) Receiver Holding Register 04953 #define AT91C_US0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400900F0) // (US0) US IPNAME1 REGISTER 04954 #define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0x40090004) // (US0) Mode Register 04955 #define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0x40090024) // (US0) Receiver Time-out Register 04956 #define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0x4009004C) // (US0) IRDA_FILTER Register 04957 #define AT91C_US0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400900EC) // (US0) US ADDRSIZE REGISTER 04958 #define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0x4009000C) // (US0) Interrupt Disable Register 04959 #define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0x40090010) // (US0) Interrupt Mask Register 04960 #define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0x40090008) // (US0) Interrupt Enable Register 04961 #define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0x40090028) // (US0) Transmitter Time-guard Register 04962 #define AT91C_US0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400900F4) // (US0) US IPNAME2 REGISTER 04963 #define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0x40090040) // (US0) FI_DI_Ratio Register 04964 #define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0x40090000) // (US0) Control Register 04965 #define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0x40090020) // (US0) Baud Rate Generator Register 04966 #define AT91C_US0_MAN (AT91_CAST(AT91_REG *) 0x40090050) // (US0) Manchester Encoder Decoder Register 04967 #define AT91C_US0_VER (AT91_CAST(AT91_REG *) 0x400900FC) // (US0) VERSION Register 04968 #define AT91C_US0_FEATURES (AT91_CAST(AT91_REG *) 0x400900F8) // (US0) US FEATURES REGISTER 04969 #define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0x40090014) // (US0) Channel Status Register 04970 #define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0x4009001C) // (US0) Transmitter Holding Register 04971 // ========== Register definition for PDC_US1 peripheral ========== 04972 #define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0x40094118) // (PDC_US1) Transmit Next Pointer Register 04973 #define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0x40094108) // (PDC_US1) Transmit Pointer Register 04974 #define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0x40094114) // (PDC_US1) Receive Next Counter Register 04975 #define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0x4009411C) // (PDC_US1) Transmit Next Counter Register 04976 #define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0x40094110) // (PDC_US1) Receive Next Pointer Register 04977 #define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0x4009410C) // (PDC_US1) Transmit Counter Register 04978 #define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0x40094124) // (PDC_US1) PDC Transfer Status Register 04979 #define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0x40094104) // (PDC_US1) Receive Counter Register 04980 #define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0x40094100) // (PDC_US1) Receive Pointer Register 04981 #define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0x40094120) // (PDC_US1) PDC Transfer Control Register 04982 // ========== Register definition for US1 peripheral ========== 04983 #define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0x40094010) // (US1) Interrupt Mask Register 04984 #define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0x40094024) // (US1) Receiver Time-out Register 04985 #define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0x40094018) // (US1) Receiver Holding Register 04986 #define AT91C_US1_IPNAME1 (AT91_CAST(AT91_REG *) 0x400940F0) // (US1) US IPNAME1 REGISTER 04987 #define AT91C_US1_VER (AT91_CAST(AT91_REG *) 0x400940FC) // (US1) VERSION Register 04988 #define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0x40094004) // (US1) Mode Register 04989 #define AT91C_US1_FEATURES (AT91_CAST(AT91_REG *) 0x400940F8) // (US1) US FEATURES REGISTER 04990 #define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0x40094044) // (US1) Nb Errors Register 04991 #define AT91C_US1_IPNAME2 (AT91_CAST(AT91_REG *) 0x400940F4) // (US1) US IPNAME2 REGISTER 04992 #define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0x40094000) // (US1) Control Register 04993 #define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0x40094020) // (US1) Baud Rate Generator Register 04994 #define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0x4009404C) // (US1) IRDA_FILTER Register 04995 #define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0x40094008) // (US1) Interrupt Enable Register 04996 #define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0x40094028) // (US1) Transmitter Time-guard Register 04997 #define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0x40094040) // (US1) FI_DI_Ratio Register 04998 #define AT91C_US1_MAN (AT91_CAST(AT91_REG *) 0x40094050) // (US1) Manchester Encoder Decoder Register 04999 #define AT91C_US1_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400940EC) // (US1) US ADDRSIZE REGISTER 05000 #define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0x40094014) // (US1) Channel Status Register 05001 #define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0x4009401C) // (US1) Transmitter Holding Register 05002 #define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0x4009400C) // (US1) Interrupt Disable Register 05003 // ========== Register definition for PDC_US2 peripheral ========== 05004 #define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0x40098100) // (PDC_US2) Receive Pointer Register 05005 #define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0x40098108) // (PDC_US2) Transmit Pointer Register 05006 #define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0x4009810C) // (PDC_US2) Transmit Counter Register 05007 #define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0x40098124) // (PDC_US2) PDC Transfer Status Register 05008 #define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0x40098120) // (PDC_US2) PDC Transfer Control Register 05009 #define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0x40098110) // (PDC_US2) Receive Next Pointer Register 05010 #define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0x4009811C) // (PDC_US2) Transmit Next Counter Register 05011 #define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0x40098114) // (PDC_US2) Receive Next Counter Register 05012 #define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0x40098118) // (PDC_US2) Transmit Next Pointer Register 05013 #define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0x40098104) // (PDC_US2) Receive Counter Register 05014 // ========== Register definition for US2 peripheral ========== 05015 #define AT91C_US2_MAN (AT91_CAST(AT91_REG *) 0x40098050) // (US2) Manchester Encoder Decoder Register 05016 #define AT91C_US2_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400980EC) // (US2) US ADDRSIZE REGISTER 05017 #define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0x40098004) // (US2) Mode Register 05018 #define AT91C_US2_IPNAME1 (AT91_CAST(AT91_REG *) 0x400980F0) // (US2) US IPNAME1 REGISTER 05019 #define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0x4009804C) // (US2) IRDA_FILTER Register 05020 #define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0x40098020) // (US2) Baud Rate Generator Register 05021 #define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0x40098040) // (US2) FI_DI_Ratio Register 05022 #define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0x40098008) // (US2) Interrupt Enable Register 05023 #define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0x40098024) // (US2) Receiver Time-out Register 05024 #define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0x40098000) // (US2) Control Register 05025 #define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0x4009801C) // (US2) Transmitter Holding Register 05026 #define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0x40098014) // (US2) Channel Status Register 05027 #define AT91C_US2_VER (AT91_CAST(AT91_REG *) 0x400980FC) // (US2) VERSION Register 05028 #define AT91C_US2_FEATURES (AT91_CAST(AT91_REG *) 0x400980F8) // (US2) US FEATURES REGISTER 05029 #define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0x4009800C) // (US2) Interrupt Disable Register 05030 #define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0x40098028) // (US2) Transmitter Time-guard Register 05031 #define AT91C_US2_IPNAME2 (AT91_CAST(AT91_REG *) 0x400980F4) // (US2) US IPNAME2 REGISTER 05032 #define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0x40098018) // (US2) Receiver Holding Register 05033 #define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0x40098044) // (US2) Nb Errors Register 05034 #define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0x40098010) // (US2) Interrupt Mask Register 05035 // ========== Register definition for PDC_US3 peripheral ========== 05036 #define AT91C_US3_TPR (AT91_CAST(AT91_REG *) 0x4009C108) // (PDC_US3) Transmit Pointer Register 05037 #define AT91C_US3_PTCR (AT91_CAST(AT91_REG *) 0x4009C120) // (PDC_US3) PDC Transfer Control Register 05038 #define AT91C_US3_TCR (AT91_CAST(AT91_REG *) 0x4009C10C) // (PDC_US3) Transmit Counter Register 05039 #define AT91C_US3_RCR (AT91_CAST(AT91_REG *) 0x4009C104) // (PDC_US3) Receive Counter Register 05040 #define AT91C_US3_RNCR (AT91_CAST(AT91_REG *) 0x4009C114) // (PDC_US3) Receive Next Counter Register 05041 #define AT91C_US3_RNPR (AT91_CAST(AT91_REG *) 0x4009C110) // (PDC_US3) Receive Next Pointer Register 05042 #define AT91C_US3_RPR (AT91_CAST(AT91_REG *) 0x4009C100) // (PDC_US3) Receive Pointer Register 05043 #define AT91C_US3_PTSR (AT91_CAST(AT91_REG *) 0x4009C124) // (PDC_US3) PDC Transfer Status Register 05044 #define AT91C_US3_TNCR (AT91_CAST(AT91_REG *) 0x4009C11C) // (PDC_US3) Transmit Next Counter Register 05045 #define AT91C_US3_TNPR (AT91_CAST(AT91_REG *) 0x4009C118) // (PDC_US3) Transmit Next Pointer Register 05046 // ========== Register definition for US3 peripheral ========== 05047 #define AT91C_US3_MAN (AT91_CAST(AT91_REG *) 0x4009C050) // (US3) Manchester Encoder Decoder Register 05048 #define AT91C_US3_CSR (AT91_CAST(AT91_REG *) 0x4009C014) // (US3) Channel Status Register 05049 #define AT91C_US3_BRGR (AT91_CAST(AT91_REG *) 0x4009C020) // (US3) Baud Rate Generator Register 05050 #define AT91C_US3_IPNAME2 (AT91_CAST(AT91_REG *) 0x4009C0F4) // (US3) US IPNAME2 REGISTER 05051 #define AT91C_US3_RTOR (AT91_CAST(AT91_REG *) 0x4009C024) // (US3) Receiver Time-out Register 05052 #define AT91C_US3_ADDRSIZE (AT91_CAST(AT91_REG *) 0x4009C0EC) // (US3) US ADDRSIZE REGISTER 05053 #define AT91C_US3_CR (AT91_CAST(AT91_REG *) 0x4009C000) // (US3) Control Register 05054 #define AT91C_US3_IF (AT91_CAST(AT91_REG *) 0x4009C04C) // (US3) IRDA_FILTER Register 05055 #define AT91C_US3_FEATURES (AT91_CAST(AT91_REG *) 0x4009C0F8) // (US3) US FEATURES REGISTER 05056 #define AT91C_US3_VER (AT91_CAST(AT91_REG *) 0x4009C0FC) // (US3) VERSION Register 05057 #define AT91C_US3_RHR (AT91_CAST(AT91_REG *) 0x4009C018) // (US3) Receiver Holding Register 05058 #define AT91C_US3_TTGR (AT91_CAST(AT91_REG *) 0x4009C028) // (US3) Transmitter Time-guard Register 05059 #define AT91C_US3_NER (AT91_CAST(AT91_REG *) 0x4009C044) // (US3) Nb Errors Register 05060 #define AT91C_US3_IMR (AT91_CAST(AT91_REG *) 0x4009C010) // (US3) Interrupt Mask Register 05061 #define AT91C_US3_THR (AT91_CAST(AT91_REG *) 0x4009C01C) // (US3) Transmitter Holding Register 05062 #define AT91C_US3_IDR (AT91_CAST(AT91_REG *) 0x4009C00C) // (US3) Interrupt Disable Register 05063 #define AT91C_US3_MR (AT91_CAST(AT91_REG *) 0x4009C004) // (US3) Mode Register 05064 #define AT91C_US3_IER (AT91_CAST(AT91_REG *) 0x4009C008) // (US3) Interrupt Enable Register 05065 #define AT91C_US3_FIDI (AT91_CAST(AT91_REG *) 0x4009C040) // (US3) FI_DI_Ratio Register 05066 #define AT91C_US3_IPNAME1 (AT91_CAST(AT91_REG *) 0x4009C0F0) // (US3) US IPNAME1 REGISTER 05067 // ========== Register definition for PDC_SSC0 peripheral ========== 05068 #define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0x40004114) // (PDC_SSC0) Receive Next Counter Register 05069 #define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0x40004108) // (PDC_SSC0) Transmit Pointer Register 05070 #define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0x4000410C) // (PDC_SSC0) Transmit Counter Register 05071 #define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0x40004120) // (PDC_SSC0) PDC Transfer Control Register 05072 #define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0x40004118) // (PDC_SSC0) Transmit Next Pointer Register 05073 #define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0x40004100) // (PDC_SSC0) Receive Pointer Register 05074 #define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0x4000411C) // (PDC_SSC0) Transmit Next Counter Register 05075 #define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0x40004110) // (PDC_SSC0) Receive Next Pointer Register 05076 #define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0x40004104) // (PDC_SSC0) Receive Counter Register 05077 #define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0x40004124) // (PDC_SSC0) PDC Transfer Status Register 05078 // ========== Register definition for SSC0 peripheral ========== 05079 #define AT91C_SSC0_FEATURES (AT91_CAST(AT91_REG *) 0x400040F8) // (SSC0) SSC FEATURES REGISTER 05080 #define AT91C_SSC0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400040F0) // (SSC0) SSC IPNAME1 REGISTER 05081 #define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0x40004000) // (SSC0) Control Register 05082 #define AT91C_SSC0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400040EC) // (SSC0) SSC ADDRSIZE REGISTER 05083 #define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0x40004020) // (SSC0) Receive Holding Register 05084 #define AT91C_SSC0_VER (AT91_CAST(AT91_REG *) 0x400040FC) // (SSC0) Version Register 05085 #define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0x40004034) // (SSC0) Transmit Sync Holding Register 05086 #define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0x40004014) // (SSC0) Receive Frame Mode Register 05087 #define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0x40004048) // (SSC0) Interrupt Disable Register 05088 #define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0x4000401C) // (SSC0) Transmit Frame Mode Register 05089 #define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0x40004030) // (SSC0) Receive Sync Holding Register 05090 #define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0x40004018) // (SSC0) Transmit Clock Mode Register 05091 #define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0x40004010) // (SSC0) Receive Clock ModeRegister 05092 #define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0x40004040) // (SSC0) Status Register 05093 #define AT91C_SSC0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400040F4) // (SSC0) SSC IPNAME2 REGISTER 05094 #define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0x40004024) // (SSC0) Transmit Holding Register 05095 #define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0x40004004) // (SSC0) Clock Mode Register 05096 #define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0x40004044) // (SSC0) Interrupt Enable Register 05097 #define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0x4000404C) // (SSC0) Interrupt Mask Register 05098 // ========== Register definition for PDC_PWMC peripheral ========== 05099 #define AT91C_PWMC_TNCR (AT91_CAST(AT91_REG *) 0x4008C11C) // (PDC_PWMC) Transmit Next Counter Register 05100 #define AT91C_PWMC_TPR (AT91_CAST(AT91_REG *) 0x4008C108) // (PDC_PWMC) Transmit Pointer Register 05101 #define AT91C_PWMC_RPR (AT91_CAST(AT91_REG *) 0x4008C100) // (PDC_PWMC) Receive Pointer Register 05102 #define AT91C_PWMC_TCR (AT91_CAST(AT91_REG *) 0x4008C10C) // (PDC_PWMC) Transmit Counter Register 05103 #define AT91C_PWMC_PTSR (AT91_CAST(AT91_REG *) 0x4008C124) // (PDC_PWMC) PDC Transfer Status Register 05104 #define AT91C_PWMC_RNPR (AT91_CAST(AT91_REG *) 0x4008C110) // (PDC_PWMC) Receive Next Pointer Register 05105 #define AT91C_PWMC_RCR (AT91_CAST(AT91_REG *) 0x4008C104) // (PDC_PWMC) Receive Counter Register 05106 #define AT91C_PWMC_RNCR (AT91_CAST(AT91_REG *) 0x4008C114) // (PDC_PWMC) Receive Next Counter Register 05107 #define AT91C_PWMC_PTCR (AT91_CAST(AT91_REG *) 0x4008C120) // (PDC_PWMC) PDC Transfer Control Register 05108 #define AT91C_PWMC_TNPR (AT91_CAST(AT91_REG *) 0x4008C118) // (PDC_PWMC) Transmit Next Pointer Register 05109 // ========== Register definition for PWMC_CH0 peripheral ========== 05110 #define AT91C_PWMC_CH0_DTR (AT91_CAST(AT91_REG *) 0x4008C218) // (PWMC_CH0) Channel Dead Time Value Register 05111 #define AT91C_PWMC_CH0_CMR (AT91_CAST(AT91_REG *) 0x4008C200) // (PWMC_CH0) Channel Mode Register 05112 #define AT91C_PWMC_CH0_CCNTR (AT91_CAST(AT91_REG *) 0x4008C214) // (PWMC_CH0) Channel Counter Register 05113 #define AT91C_PWMC_CH0_CPRDR (AT91_CAST(AT91_REG *) 0x4008C20C) // (PWMC_CH0) Channel Period Register 05114 #define AT91C_PWMC_CH0_DTUPDR (AT91_CAST(AT91_REG *) 0x4008C21C) // (PWMC_CH0) Channel Dead Time Update Value Register 05115 #define AT91C_PWMC_CH0_CPRDUPDR (AT91_CAST(AT91_REG *) 0x4008C210) // (PWMC_CH0) Channel Period Update Register 05116 #define AT91C_PWMC_CH0_CDTYUPDR (AT91_CAST(AT91_REG *) 0x4008C208) // (PWMC_CH0) Channel Duty Cycle Update Register 05117 #define AT91C_PWMC_CH0_CDTYR (AT91_CAST(AT91_REG *) 0x4008C204) // (PWMC_CH0) Channel Duty Cycle Register 05118 // ========== Register definition for PWMC_CH1 peripheral ========== 05119 #define AT91C_PWMC_CH1_CCNTR (AT91_CAST(AT91_REG *) 0x4008C234) // (PWMC_CH1) Channel Counter Register 05120 #define AT91C_PWMC_CH1_DTR (AT91_CAST(AT91_REG *) 0x4008C238) // (PWMC_CH1) Channel Dead Time Value Register 05121 #define AT91C_PWMC_CH1_CDTYUPDR (AT91_CAST(AT91_REG *) 0x4008C228) // (PWMC_CH1) Channel Duty Cycle Update Register 05122 #define AT91C_PWMC_CH1_DTUPDR (AT91_CAST(AT91_REG *) 0x4008C23C) // (PWMC_CH1) Channel Dead Time Update Value Register 05123 #define AT91C_PWMC_CH1_CDTYR (AT91_CAST(AT91_REG *) 0x4008C224) // (PWMC_CH1) Channel Duty Cycle Register 05124 #define AT91C_PWMC_CH1_CPRDR (AT91_CAST(AT91_REG *) 0x4008C22C) // (PWMC_CH1) Channel Period Register 05125 #define AT91C_PWMC_CH1_CPRDUPDR (AT91_CAST(AT91_REG *) 0x4008C230) // (PWMC_CH1) Channel Period Update Register 05126 #define AT91C_PWMC_CH1_CMR (AT91_CAST(AT91_REG *) 0x4008C220) // (PWMC_CH1) Channel Mode Register 05127 // ========== Register definition for PWMC_CH2 peripheral ========== 05128 #define AT91C_PWMC_CH2_CDTYR (AT91_CAST(AT91_REG *) 0x4008C244) // (PWMC_CH2) Channel Duty Cycle Register 05129 #define AT91C_PWMC_CH2_DTUPDR (AT91_CAST(AT91_REG *) 0x4008C25C) // (PWMC_CH2) Channel Dead Time Update Value Register 05130 #define AT91C_PWMC_CH2_CCNTR (AT91_CAST(AT91_REG *) 0x4008C254) // (PWMC_CH2) Channel Counter Register 05131 #define AT91C_PWMC_CH2_CMR (AT91_CAST(AT91_REG *) 0x4008C240) // (PWMC_CH2) Channel Mode Register 05132 #define AT91C_PWMC_CH2_CPRDR (AT91_CAST(AT91_REG *) 0x4008C24C) // (PWMC_CH2) Channel Period Register 05133 #define AT91C_PWMC_CH2_CPRDUPDR (AT91_CAST(AT91_REG *) 0x4008C250) // (PWMC_CH2) Channel Period Update Register 05134 #define AT91C_PWMC_CH2_CDTYUPDR (AT91_CAST(AT91_REG *) 0x4008C248) // (PWMC_CH2) Channel Duty Cycle Update Register 05135 #define AT91C_PWMC_CH2_DTR (AT91_CAST(AT91_REG *) 0x4008C258) // (PWMC_CH2) Channel Dead Time Value Register 05136 // ========== Register definition for PWMC_CH3 peripheral ========== 05137 #define AT91C_PWMC_CH3_CPRDUPDR (AT91_CAST(AT91_REG *) 0x4008C270) // (PWMC_CH3) Channel Period Update Register 05138 #define AT91C_PWMC_CH3_DTR (AT91_CAST(AT91_REG *) 0x4008C278) // (PWMC_CH3) Channel Dead Time Value Register 05139 #define AT91C_PWMC_CH3_CDTYR (AT91_CAST(AT91_REG *) 0x4008C264) // (PWMC_CH3) Channel Duty Cycle Register 05140 #define AT91C_PWMC_CH3_DTUPDR (AT91_CAST(AT91_REG *) 0x4008C27C) // (PWMC_CH3) Channel Dead Time Update Value Register 05141 #define AT91C_PWMC_CH3_CDTYUPDR (AT91_CAST(AT91_REG *) 0x4008C268) // (PWMC_CH3) Channel Duty Cycle Update Register 05142 #define AT91C_PWMC_CH3_CCNTR (AT91_CAST(AT91_REG *) 0x4008C274) // (PWMC_CH3) Channel Counter Register 05143 #define AT91C_PWMC_CH3_CMR (AT91_CAST(AT91_REG *) 0x4008C260) // (PWMC_CH3) Channel Mode Register 05144 #define AT91C_PWMC_CH3_CPRDR (AT91_CAST(AT91_REG *) 0x4008C26C) // (PWMC_CH3) Channel Period Register 05145 // ========== Register definition for PWMC peripheral ========== 05146 #define AT91C_PWMC_CMP6MUPD (AT91_CAST(AT91_REG *) 0x4008C19C) // (PWMC) PWM Comparison Mode 6 Update Register 05147 #define AT91C_PWMC_ISR1 (AT91_CAST(AT91_REG *) 0x4008C01C) // (PWMC) PWMC Interrupt Status Register 1 05148 #define AT91C_PWMC_CMP5V (AT91_CAST(AT91_REG *) 0x4008C180) // (PWMC) PWM Comparison Value 5 Register 05149 #define AT91C_PWMC_CMP4MUPD (AT91_CAST(AT91_REG *) 0x4008C17C) // (PWMC) PWM Comparison Mode 4 Update Register 05150 #define AT91C_PWMC_FMR (AT91_CAST(AT91_REG *) 0x4008C05C) // (PWMC) PWM Fault Mode Register 05151 #define AT91C_PWMC_CMP6V (AT91_CAST(AT91_REG *) 0x4008C190) // (PWMC) PWM Comparison Value 6 Register 05152 #define AT91C_PWMC_EL4MR (AT91_CAST(AT91_REG *) 0x4008C08C) // (PWMC) PWM Event Line 4 Mode Register 05153 #define AT91C_PWMC_UPCR (AT91_CAST(AT91_REG *) 0x4008C028) // (PWMC) PWM Update Control Register 05154 #define AT91C_PWMC_CMP1VUPD (AT91_CAST(AT91_REG *) 0x4008C144) // (PWMC) PWM Comparison Value 1 Update Register 05155 #define AT91C_PWMC_CMP0M (AT91_CAST(AT91_REG *) 0x4008C138) // (PWMC) PWM Comparison Mode 0 Register 05156 #define AT91C_PWMC_CMP5VUPD (AT91_CAST(AT91_REG *) 0x4008C184) // (PWMC) PWM Comparison Value 5 Update Register 05157 #define AT91C_PWMC_FPER3 (AT91_CAST(AT91_REG *) 0x4008C074) // (PWMC) PWM Fault Protection Enable Register 3 05158 #define AT91C_PWMC_OSCUPD (AT91_CAST(AT91_REG *) 0x4008C058) // (PWMC) PWM Output Selection Clear Update Register 05159 #define AT91C_PWMC_FPER1 (AT91_CAST(AT91_REG *) 0x4008C06C) // (PWMC) PWM Fault Protection Enable Register 1 05160 #define AT91C_PWMC_SCUPUPD (AT91_CAST(AT91_REG *) 0x4008C030) // (PWMC) PWM Update Period Update Register 05161 #define AT91C_PWMC_DIS (AT91_CAST(AT91_REG *) 0x4008C008) // (PWMC) PWMC Disable Register 05162 #define AT91C_PWMC_IER1 (AT91_CAST(AT91_REG *) 0x4008C010) // (PWMC) PWMC Interrupt Enable Register 1 05163 #define AT91C_PWMC_IMR2 (AT91_CAST(AT91_REG *) 0x4008C03C) // (PWMC) PWMC Interrupt Mask Register 2 05164 #define AT91C_PWMC_CMP0V (AT91_CAST(AT91_REG *) 0x4008C130) // (PWMC) PWM Comparison Value 0 Register 05165 #define AT91C_PWMC_SR (AT91_CAST(AT91_REG *) 0x4008C00C) // (PWMC) PWMC Status Register 05166 #define AT91C_PWMC_CMP4M (AT91_CAST(AT91_REG *) 0x4008C178) // (PWMC) PWM Comparison Mode 4 Register 05167 #define AT91C_PWMC_CMP3M (AT91_CAST(AT91_REG *) 0x4008C168) // (PWMC) PWM Comparison Mode 3 Register 05168 #define AT91C_PWMC_IER2 (AT91_CAST(AT91_REG *) 0x4008C034) // (PWMC) PWMC Interrupt Enable Register 2 05169 #define AT91C_PWMC_CMP3VUPD (AT91_CAST(AT91_REG *) 0x4008C164) // (PWMC) PWM Comparison Value 3 Update Register 05170 #define AT91C_PWMC_CMP2M (AT91_CAST(AT91_REG *) 0x4008C158) // (PWMC) PWM Comparison Mode 2 Register 05171 #define AT91C_PWMC_IDR2 (AT91_CAST(AT91_REG *) 0x4008C038) // (PWMC) PWMC Interrupt Disable Register 2 05172 #define AT91C_PWMC_EL2MR (AT91_CAST(AT91_REG *) 0x4008C084) // (PWMC) PWM Event Line 2 Mode Register 05173 #define AT91C_PWMC_CMP7V (AT91_CAST(AT91_REG *) 0x4008C1A0) // (PWMC) PWM Comparison Value 7 Register 05174 #define AT91C_PWMC_CMP1M (AT91_CAST(AT91_REG *) 0x4008C148) // (PWMC) PWM Comparison Mode 1 Register 05175 #define AT91C_PWMC_CMP0VUPD (AT91_CAST(AT91_REG *) 0x4008C134) // (PWMC) PWM Comparison Value 0 Update Register 05176 #define AT91C_PWMC_WPSR (AT91_CAST(AT91_REG *) 0x4008C0E8) // (PWMC) PWM Write Protection Status Register 05177 #define AT91C_PWMC_CMP6VUPD (AT91_CAST(AT91_REG *) 0x4008C194) // (PWMC) PWM Comparison Value 6 Update Register 05178 #define AT91C_PWMC_CMP1MUPD (AT91_CAST(AT91_REG *) 0x4008C14C) // (PWMC) PWM Comparison Mode 1 Update Register 05179 #define AT91C_PWMC_CMP1V (AT91_CAST(AT91_REG *) 0x4008C140) // (PWMC) PWM Comparison Value 1 Register 05180 #define AT91C_PWMC_FCR (AT91_CAST(AT91_REG *) 0x4008C064) // (PWMC) PWM Fault Mode Clear Register 05181 #define AT91C_PWMC_VER (AT91_CAST(AT91_REG *) 0x4008C0FC) // (PWMC) PWMC Version Register 05182 #define AT91C_PWMC_EL1MR (AT91_CAST(AT91_REG *) 0x4008C080) // (PWMC) PWM Event Line 1 Mode Register 05183 #define AT91C_PWMC_EL6MR (AT91_CAST(AT91_REG *) 0x4008C094) // (PWMC) PWM Event Line 6 Mode Register 05184 #define AT91C_PWMC_ISR2 (AT91_CAST(AT91_REG *) 0x4008C040) // (PWMC) PWMC Interrupt Status Register 2 05185 #define AT91C_PWMC_CMP4VUPD (AT91_CAST(AT91_REG *) 0x4008C174) // (PWMC) PWM Comparison Value 4 Update Register 05186 #define AT91C_PWMC_CMP5MUPD (AT91_CAST(AT91_REG *) 0x4008C18C) // (PWMC) PWM Comparison Mode 5 Update Register 05187 #define AT91C_PWMC_OS (AT91_CAST(AT91_REG *) 0x4008C048) // (PWMC) PWM Output Selection Register 05188 #define AT91C_PWMC_FPV (AT91_CAST(AT91_REG *) 0x4008C068) // (PWMC) PWM Fault Protection Value Register 05189 #define AT91C_PWMC_FPER2 (AT91_CAST(AT91_REG *) 0x4008C070) // (PWMC) PWM Fault Protection Enable Register 2 05190 #define AT91C_PWMC_EL7MR (AT91_CAST(AT91_REG *) 0x4008C098) // (PWMC) PWM Event Line 7 Mode Register 05191 #define AT91C_PWMC_OSSUPD (AT91_CAST(AT91_REG *) 0x4008C054) // (PWMC) PWM Output Selection Set Update Register 05192 #define AT91C_PWMC_FEATURES (AT91_CAST(AT91_REG *) 0x4008C0F8) // (PWMC) PWMC FEATURES REGISTER 05193 #define AT91C_PWMC_CMP2V (AT91_CAST(AT91_REG *) 0x4008C150) // (PWMC) PWM Comparison Value 2 Register 05194 #define AT91C_PWMC_FSR (AT91_CAST(AT91_REG *) 0x4008C060) // (PWMC) PWM Fault Mode Status Register 05195 #define AT91C_PWMC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x4008C0EC) // (PWMC) PWMC ADDRSIZE REGISTER 05196 #define AT91C_PWMC_OSC (AT91_CAST(AT91_REG *) 0x4008C050) // (PWMC) PWM Output Selection Clear Register 05197 #define AT91C_PWMC_SCUP (AT91_CAST(AT91_REG *) 0x4008C02C) // (PWMC) PWM Update Period Register 05198 #define AT91C_PWMC_CMP7MUPD (AT91_CAST(AT91_REG *) 0x4008C1AC) // (PWMC) PWM Comparison Mode 7 Update Register 05199 #define AT91C_PWMC_CMP2VUPD (AT91_CAST(AT91_REG *) 0x4008C154) // (PWMC) PWM Comparison Value 2 Update Register 05200 #define AT91C_PWMC_FPER4 (AT91_CAST(AT91_REG *) 0x4008C078) // (PWMC) PWM Fault Protection Enable Register 4 05201 #define AT91C_PWMC_IMR1 (AT91_CAST(AT91_REG *) 0x4008C018) // (PWMC) PWMC Interrupt Mask Register 1 05202 #define AT91C_PWMC_EL3MR (AT91_CAST(AT91_REG *) 0x4008C088) // (PWMC) PWM Event Line 3 Mode Register 05203 #define AT91C_PWMC_CMP3V (AT91_CAST(AT91_REG *) 0x4008C160) // (PWMC) PWM Comparison Value 3 Register 05204 #define AT91C_PWMC_IPNAME1 (AT91_CAST(AT91_REG *) 0x4008C0F0) // (PWMC) PWMC IPNAME1 REGISTER 05205 #define AT91C_PWMC_OSS (AT91_CAST(AT91_REG *) 0x4008C04C) // (PWMC) PWM Output Selection Set Register 05206 #define AT91C_PWMC_CMP0MUPD (AT91_CAST(AT91_REG *) 0x4008C13C) // (PWMC) PWM Comparison Mode 0 Update Register 05207 #define AT91C_PWMC_CMP2MUPD (AT91_CAST(AT91_REG *) 0x4008C15C) // (PWMC) PWM Comparison Mode 2 Update Register 05208 #define AT91C_PWMC_CMP4V (AT91_CAST(AT91_REG *) 0x4008C170) // (PWMC) PWM Comparison Value 4 Register 05209 #define AT91C_PWMC_ENA (AT91_CAST(AT91_REG *) 0x4008C004) // (PWMC) PWMC Enable Register 05210 #define AT91C_PWMC_CMP3MUPD (AT91_CAST(AT91_REG *) 0x4008C16C) // (PWMC) PWM Comparison Mode 3 Update Register 05211 #define AT91C_PWMC_EL0MR (AT91_CAST(AT91_REG *) 0x4008C07C) // (PWMC) PWM Event Line 0 Mode Register 05212 #define AT91C_PWMC_OOV (AT91_CAST(AT91_REG *) 0x4008C044) // (PWMC) PWM Output Override Value Register 05213 #define AT91C_PWMC_WPCR (AT91_CAST(AT91_REG *) 0x4008C0E4) // (PWMC) PWM Write Protection Enable Register 05214 #define AT91C_PWMC_CMP7M (AT91_CAST(AT91_REG *) 0x4008C1A8) // (PWMC) PWM Comparison Mode 7 Register 05215 #define AT91C_PWMC_CMP6M (AT91_CAST(AT91_REG *) 0x4008C198) // (PWMC) PWM Comparison Mode 6 Register 05216 #define AT91C_PWMC_CMP5M (AT91_CAST(AT91_REG *) 0x4008C188) // (PWMC) PWM Comparison Mode 5 Register 05217 #define AT91C_PWMC_IPNAME2 (AT91_CAST(AT91_REG *) 0x4008C0F4) // (PWMC) PWMC IPNAME2 REGISTER 05218 #define AT91C_PWMC_CMP7VUPD (AT91_CAST(AT91_REG *) 0x4008C1A4) // (PWMC) PWM Comparison Value 7 Update Register 05219 #define AT91C_PWMC_SYNC (AT91_CAST(AT91_REG *) 0x4008C020) // (PWMC) PWM Synchronized Channels Register 05220 #define AT91C_PWMC_MR (AT91_CAST(AT91_REG *) 0x4008C000) // (PWMC) PWMC Mode Register 05221 #define AT91C_PWMC_IDR1 (AT91_CAST(AT91_REG *) 0x4008C014) // (PWMC) PWMC Interrupt Disable Register 1 05222 #define AT91C_PWMC_EL5MR (AT91_CAST(AT91_REG *) 0x4008C090) // (PWMC) PWM Event Line 5 Mode Register 05223 // ========== Register definition for SPI0 peripheral ========== 05224 #define AT91C_SPI0_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400080EC) // (SPI0) SPI ADDRSIZE REGISTER 05225 #define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0x40008008) // (SPI0) Receive Data Register 05226 #define AT91C_SPI0_FEATURES (AT91_CAST(AT91_REG *) 0x400080F8) // (SPI0) SPI FEATURES REGISTER 05227 #define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0x40008000) // (SPI0) Control Register 05228 #define AT91C_SPI0_IPNAME1 (AT91_CAST(AT91_REG *) 0x400080F0) // (SPI0) SPI IPNAME1 REGISTER 05229 #define AT91C_SPI0_VER (AT91_CAST(AT91_REG *) 0x400080FC) // (SPI0) Version Register 05230 #define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0x40008018) // (SPI0) Interrupt Disable Register 05231 #define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0x4000800C) // (SPI0) Transmit Data Register 05232 #define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0x40008004) // (SPI0) Mode Register 05233 #define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0x40008014) // (SPI0) Interrupt Enable Register 05234 #define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0x4000801C) // (SPI0) Interrupt Mask Register 05235 #define AT91C_SPI0_IPNAME2 (AT91_CAST(AT91_REG *) 0x400080F4) // (SPI0) SPI IPNAME2 REGISTER 05236 #define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0x40008030) // (SPI0) Chip Select Register 05237 #define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0x40008010) // (SPI0) Status Register 05238 // ========== Register definition for UDPHS_EPTFIFO peripheral ========== 05239 #define AT91C_UDPHS_EPTFIFO_READEPT6 (AT91_CAST(AT91_REG *) 0x201E0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6 05240 #define AT91C_UDPHS_EPTFIFO_READEPT2 (AT91_CAST(AT91_REG *) 0x201A0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2 05241 #define AT91C_UDPHS_EPTFIFO_READEPT1 (AT91_CAST(AT91_REG *) 0x20190000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1 05242 #define AT91C_UDPHS_EPTFIFO_READEPT0 (AT91_CAST(AT91_REG *) 0x20180000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0 05243 #define AT91C_UDPHS_EPTFIFO_READEPT5 (AT91_CAST(AT91_REG *) 0x201D0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5 05244 #define AT91C_UDPHS_EPTFIFO_READEPT4 (AT91_CAST(AT91_REG *) 0x201C0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4 05245 #define AT91C_UDPHS_EPTFIFO_READEPT3 (AT91_CAST(AT91_REG *) 0x201B0000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3 05246 // ========== Register definition for UDPHS_EPT_0 peripheral ========== 05247 #define AT91C_UDPHS_EPT_0_EPTCTL (AT91_CAST(AT91_REG *) 0x400A410C) // (UDPHS_EPT_0) UDPHS Endpoint Control Register 05248 #define AT91C_UDPHS_EPT_0_EPTSTA (AT91_CAST(AT91_REG *) 0x400A411C) // (UDPHS_EPT_0) UDPHS Endpoint Status Register 05249 #define AT91C_UDPHS_EPT_0_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A4118) // (UDPHS_EPT_0) UDPHS Endpoint Clear Status Register 05250 #define AT91C_UDPHS_EPT_0_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A4108) // (UDPHS_EPT_0) UDPHS Endpoint Control Disable Register 05251 #define AT91C_UDPHS_EPT_0_EPTCFG (AT91_CAST(AT91_REG *) 0x400A4100) // (UDPHS_EPT_0) UDPHS Endpoint Config Register 05252 #define AT91C_UDPHS_EPT_0_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A4114) // (UDPHS_EPT_0) UDPHS Endpoint Set Status Register 05253 #define AT91C_UDPHS_EPT_0_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A4104) // (UDPHS_EPT_0) UDPHS Endpoint Control Enable Register 05254 // ========== Register definition for UDPHS_EPT_1 peripheral ========== 05255 #define AT91C_UDPHS_EPT_1_EPTSTA (AT91_CAST(AT91_REG *) 0x400A413C) // (UDPHS_EPT_1) UDPHS Endpoint Status Register 05256 #define AT91C_UDPHS_EPT_1_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A4134) // (UDPHS_EPT_1) UDPHS Endpoint Set Status Register 05257 #define AT91C_UDPHS_EPT_1_EPTCTL (AT91_CAST(AT91_REG *) 0x400A412C) // (UDPHS_EPT_1) UDPHS Endpoint Control Register 05258 #define AT91C_UDPHS_EPT_1_EPTCFG (AT91_CAST(AT91_REG *) 0x400A4120) // (UDPHS_EPT_1) UDPHS Endpoint Config Register 05259 #define AT91C_UDPHS_EPT_1_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A4128) // (UDPHS_EPT_1) UDPHS Endpoint Control Disable Register 05260 #define AT91C_UDPHS_EPT_1_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A4138) // (UDPHS_EPT_1) UDPHS Endpoint Clear Status Register 05261 #define AT91C_UDPHS_EPT_1_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A4124) // (UDPHS_EPT_1) UDPHS Endpoint Control Enable Register 05262 // ========== Register definition for UDPHS_EPT_2 peripheral ========== 05263 #define AT91C_UDPHS_EPT_2_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A4144) // (UDPHS_EPT_2) UDPHS Endpoint Control Enable Register 05264 #define AT91C_UDPHS_EPT_2_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A4158) // (UDPHS_EPT_2) UDPHS Endpoint Clear Status Register 05265 #define AT91C_UDPHS_EPT_2_EPTCFG (AT91_CAST(AT91_REG *) 0x400A4140) // (UDPHS_EPT_2) UDPHS Endpoint Config Register 05266 #define AT91C_UDPHS_EPT_2_EPTCTL (AT91_CAST(AT91_REG *) 0x400A414C) // (UDPHS_EPT_2) UDPHS Endpoint Control Register 05267 #define AT91C_UDPHS_EPT_2_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A4154) // (UDPHS_EPT_2) UDPHS Endpoint Set Status Register 05268 #define AT91C_UDPHS_EPT_2_EPTSTA (AT91_CAST(AT91_REG *) 0x400A415C) // (UDPHS_EPT_2) UDPHS Endpoint Status Register 05269 #define AT91C_UDPHS_EPT_2_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A4148) // (UDPHS_EPT_2) UDPHS Endpoint Control Disable Register 05270 // ========== Register definition for UDPHS_EPT_3 peripheral ========== 05271 #define AT91C_UDPHS_EPT_3_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A4168) // (UDPHS_EPT_3) UDPHS Endpoint Control Disable Register 05272 #define AT91C_UDPHS_EPT_3_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A4164) // (UDPHS_EPT_3) UDPHS Endpoint Control Enable Register 05273 #define AT91C_UDPHS_EPT_3_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A4174) // (UDPHS_EPT_3) UDPHS Endpoint Set Status Register 05274 #define AT91C_UDPHS_EPT_3_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A4178) // (UDPHS_EPT_3) UDPHS Endpoint Clear Status Register 05275 #define AT91C_UDPHS_EPT_3_EPTCFG (AT91_CAST(AT91_REG *) 0x400A4160) // (UDPHS_EPT_3) UDPHS Endpoint Config Register 05276 #define AT91C_UDPHS_EPT_3_EPTSTA (AT91_CAST(AT91_REG *) 0x400A417C) // (UDPHS_EPT_3) UDPHS Endpoint Status Register 05277 #define AT91C_UDPHS_EPT_3_EPTCTL (AT91_CAST(AT91_REG *) 0x400A416C) // (UDPHS_EPT_3) UDPHS Endpoint Control Register 05278 // ========== Register definition for UDPHS_EPT_4 peripheral ========== 05279 #define AT91C_UDPHS_EPT_4_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A4194) // (UDPHS_EPT_4) UDPHS Endpoint Set Status Register 05280 #define AT91C_UDPHS_EPT_4_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A4188) // (UDPHS_EPT_4) UDPHS Endpoint Control Disable Register 05281 #define AT91C_UDPHS_EPT_4_EPTCTL (AT91_CAST(AT91_REG *) 0x400A418C) // (UDPHS_EPT_4) UDPHS Endpoint Control Register 05282 #define AT91C_UDPHS_EPT_4_EPTCFG (AT91_CAST(AT91_REG *) 0x400A4180) // (UDPHS_EPT_4) UDPHS Endpoint Config Register 05283 #define AT91C_UDPHS_EPT_4_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A4184) // (UDPHS_EPT_4) UDPHS Endpoint Control Enable Register 05284 #define AT91C_UDPHS_EPT_4_EPTSTA (AT91_CAST(AT91_REG *) 0x400A419C) // (UDPHS_EPT_4) UDPHS Endpoint Status Register 05285 #define AT91C_UDPHS_EPT_4_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A4198) // (UDPHS_EPT_4) UDPHS Endpoint Clear Status Register 05286 // ========== Register definition for UDPHS_EPT_5 peripheral ========== 05287 #define AT91C_UDPHS_EPT_5_EPTCFG (AT91_CAST(AT91_REG *) 0x400A41A0) // (UDPHS_EPT_5) UDPHS Endpoint Config Register 05288 #define AT91C_UDPHS_EPT_5_EPTCTL (AT91_CAST(AT91_REG *) 0x400A41AC) // (UDPHS_EPT_5) UDPHS Endpoint Control Register 05289 #define AT91C_UDPHS_EPT_5_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A41A4) // (UDPHS_EPT_5) UDPHS Endpoint Control Enable Register 05290 #define AT91C_UDPHS_EPT_5_EPTSTA (AT91_CAST(AT91_REG *) 0x400A41BC) // (UDPHS_EPT_5) UDPHS Endpoint Status Register 05291 #define AT91C_UDPHS_EPT_5_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A41B4) // (UDPHS_EPT_5) UDPHS Endpoint Set Status Register 05292 #define AT91C_UDPHS_EPT_5_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A41A8) // (UDPHS_EPT_5) UDPHS Endpoint Control Disable Register 05293 #define AT91C_UDPHS_EPT_5_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A41B8) // (UDPHS_EPT_5) UDPHS Endpoint Clear Status Register 05294 // ========== Register definition for UDPHS_EPT_6 peripheral ========== 05295 #define AT91C_UDPHS_EPT_6_EPTCLRSTA (AT91_CAST(AT91_REG *) 0x400A41D8) // (UDPHS_EPT_6) UDPHS Endpoint Clear Status Register 05296 #define AT91C_UDPHS_EPT_6_EPTCTL (AT91_CAST(AT91_REG *) 0x400A41CC) // (UDPHS_EPT_6) UDPHS Endpoint Control Register 05297 #define AT91C_UDPHS_EPT_6_EPTCFG (AT91_CAST(AT91_REG *) 0x400A41C0) // (UDPHS_EPT_6) UDPHS Endpoint Config Register 05298 #define AT91C_UDPHS_EPT_6_EPTCTLDIS (AT91_CAST(AT91_REG *) 0x400A41C8) // (UDPHS_EPT_6) UDPHS Endpoint Control Disable Register 05299 #define AT91C_UDPHS_EPT_6_EPTSTA (AT91_CAST(AT91_REG *) 0x400A41DC) // (UDPHS_EPT_6) UDPHS Endpoint Status Register 05300 #define AT91C_UDPHS_EPT_6_EPTCTLENB (AT91_CAST(AT91_REG *) 0x400A41C4) // (UDPHS_EPT_6) UDPHS Endpoint Control Enable Register 05301 #define AT91C_UDPHS_EPT_6_EPTSETSTA (AT91_CAST(AT91_REG *) 0x400A41D4) // (UDPHS_EPT_6) UDPHS Endpoint Set Status Register 05302 // ========== Register definition for UDPHS_DMA_1 peripheral ========== 05303 #define AT91C_UDPHS_DMA_1_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A431C) // (UDPHS_DMA_1) UDPHS DMA Channel Status Register 05304 #define AT91C_UDPHS_DMA_1_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4318) // (UDPHS_DMA_1) UDPHS DMA Channel Control Register 05305 #define AT91C_UDPHS_DMA_1_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4310) // (UDPHS_DMA_1) UDPHS DMA Channel Next Descriptor Address 05306 #define AT91C_UDPHS_DMA_1_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4314) // (UDPHS_DMA_1) UDPHS DMA Channel Address Register 05307 // ========== Register definition for UDPHS_DMA_2 peripheral ========== 05308 #define AT91C_UDPHS_DMA_2_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A432C) // (UDPHS_DMA_2) UDPHS DMA Channel Status Register 05309 #define AT91C_UDPHS_DMA_2_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4320) // (UDPHS_DMA_2) UDPHS DMA Channel Next Descriptor Address 05310 #define AT91C_UDPHS_DMA_2_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4328) // (UDPHS_DMA_2) UDPHS DMA Channel Control Register 05311 #define AT91C_UDPHS_DMA_2_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4324) // (UDPHS_DMA_2) UDPHS DMA Channel Address Register 05312 // ========== Register definition for UDPHS_DMA_3 peripheral ========== 05313 #define AT91C_UDPHS_DMA_3_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4338) // (UDPHS_DMA_3) UDPHS DMA Channel Control Register 05314 #define AT91C_UDPHS_DMA_3_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4330) // (UDPHS_DMA_3) UDPHS DMA Channel Next Descriptor Address 05315 #define AT91C_UDPHS_DMA_3_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A433C) // (UDPHS_DMA_3) UDPHS DMA Channel Status Register 05316 #define AT91C_UDPHS_DMA_3_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4334) // (UDPHS_DMA_3) UDPHS DMA Channel Address Register 05317 // ========== Register definition for UDPHS_DMA_4 peripheral ========== 05318 #define AT91C_UDPHS_DMA_4_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4344) // (UDPHS_DMA_4) UDPHS DMA Channel Address Register 05319 #define AT91C_UDPHS_DMA_4_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4340) // (UDPHS_DMA_4) UDPHS DMA Channel Next Descriptor Address 05320 #define AT91C_UDPHS_DMA_4_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A434C) // (UDPHS_DMA_4) UDPHS DMA Channel Status Register 05321 #define AT91C_UDPHS_DMA_4_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4348) // (UDPHS_DMA_4) UDPHS DMA Channel Control Register 05322 // ========== Register definition for UDPHS_DMA_5 peripheral ========== 05323 #define AT91C_UDPHS_DMA_5_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4358) // (UDPHS_DMA_5) UDPHS DMA Channel Control Register 05324 #define AT91C_UDPHS_DMA_5_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4354) // (UDPHS_DMA_5) UDPHS DMA Channel Address Register 05325 #define AT91C_UDPHS_DMA_5_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4350) // (UDPHS_DMA_5) UDPHS DMA Channel Next Descriptor Address 05326 #define AT91C_UDPHS_DMA_5_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A435C) // (UDPHS_DMA_5) UDPHS DMA Channel Status Register 05327 // ========== Register definition for UDPHS_DMA_6 peripheral ========== 05328 #define AT91C_UDPHS_DMA_6_DMASTATUS (AT91_CAST(AT91_REG *) 0x400A436C) // (UDPHS_DMA_6) UDPHS DMA Channel Status Register 05329 #define AT91C_UDPHS_DMA_6_DMACONTROL (AT91_CAST(AT91_REG *) 0x400A4368) // (UDPHS_DMA_6) UDPHS DMA Channel Control Register 05330 #define AT91C_UDPHS_DMA_6_DMANXTDSC (AT91_CAST(AT91_REG *) 0x400A4360) // (UDPHS_DMA_6) UDPHS DMA Channel Next Descriptor Address 05331 #define AT91C_UDPHS_DMA_6_DMAADDRESS (AT91_CAST(AT91_REG *) 0x400A4364) // (UDPHS_DMA_6) UDPHS DMA Channel Address Register 05332 // ========== Register definition for UDPHS peripheral ========== 05333 #define AT91C_UDPHS_EPTRST (AT91_CAST(AT91_REG *) 0x400A401C) // (UDPHS) UDPHS Endpoints Reset Register 05334 #define AT91C_UDPHS_IEN (AT91_CAST(AT91_REG *) 0x400A4010) // (UDPHS) UDPHS Interrupt Enable Register 05335 #define AT91C_UDPHS_TSTCNTB (AT91_CAST(AT91_REG *) 0x400A40D8) // (UDPHS) UDPHS Test B Counter Register 05336 #define AT91C_UDPHS_RIPNAME2 (AT91_CAST(AT91_REG *) 0x400A40F4) // (UDPHS) UDPHS Name2 Register 05337 #define AT91C_UDPHS_RIPPADDRSIZE (AT91_CAST(AT91_REG *) 0x400A40EC) // (UDPHS) UDPHS PADDRSIZE Register 05338 #define AT91C_UDPHS_TSTMODREG (AT91_CAST(AT91_REG *) 0x400A40DC) // (UDPHS) UDPHS Test Mode Register 05339 #define AT91C_UDPHS_TST (AT91_CAST(AT91_REG *) 0x400A40E0) // (UDPHS) UDPHS Test Register 05340 #define AT91C_UDPHS_TSTSOFCNT (AT91_CAST(AT91_REG *) 0x400A40D0) // (UDPHS) UDPHS Test SOF Counter Register 05341 #define AT91C_UDPHS_FNUM (AT91_CAST(AT91_REG *) 0x400A4004) // (UDPHS) UDPHS Frame Number Register 05342 #define AT91C_UDPHS_TSTCNTA (AT91_CAST(AT91_REG *) 0x400A40D4) // (UDPHS) UDPHS Test A Counter Register 05343 #define AT91C_UDPHS_INTSTA (AT91_CAST(AT91_REG *) 0x400A4014) // (UDPHS) UDPHS Interrupt Status Register 05344 #define AT91C_UDPHS_IPFEATURES (AT91_CAST(AT91_REG *) 0x400A40F8) // (UDPHS) UDPHS Features Register 05345 #define AT91C_UDPHS_CLRINT (AT91_CAST(AT91_REG *) 0x400A4018) // (UDPHS) UDPHS Clear Interrupt Register 05346 #define AT91C_UDPHS_RIPNAME1 (AT91_CAST(AT91_REG *) 0x400A40F0) // (UDPHS) UDPHS Name1 Register 05347 #define AT91C_UDPHS_CTRL (AT91_CAST(AT91_REG *) 0x400A4000) // (UDPHS) UDPHS Control Register 05348 #define AT91C_UDPHS_IPVERSION (AT91_CAST(AT91_REG *) 0x400A40FC) // (UDPHS) UDPHS Version Register 05349 // ========== Register definition for HDMA_CH_0 peripheral ========== 05350 #define AT91C_HDMA_CH_0_CADDR (AT91_CAST(AT91_REG *) 0x400B0060) // (HDMA_CH_0) HDMA Reserved 05351 #define AT91C_HDMA_CH_0_DADDR (AT91_CAST(AT91_REG *) 0x400B0040) // (HDMA_CH_0) HDMA Channel Destination Address Register 05352 #define AT91C_HDMA_CH_0_BDSCR (AT91_CAST(AT91_REG *) 0x400B005C) // (HDMA_CH_0) HDMA Reserved 05353 #define AT91C_HDMA_CH_0_CFG (AT91_CAST(AT91_REG *) 0x400B0050) // (HDMA_CH_0) HDMA Channel Configuration Register 05354 #define AT91C_HDMA_CH_0_CTRLB (AT91_CAST(AT91_REG *) 0x400B004C) // (HDMA_CH_0) HDMA Channel Control B Register 05355 #define AT91C_HDMA_CH_0_CTRLA (AT91_CAST(AT91_REG *) 0x400B0048) // (HDMA_CH_0) HDMA Channel Control A Register 05356 #define AT91C_HDMA_CH_0_DSCR (AT91_CAST(AT91_REG *) 0x400B0044) // (HDMA_CH_0) HDMA Channel Descriptor Address Register 05357 #define AT91C_HDMA_CH_0_SADDR (AT91_CAST(AT91_REG *) 0x400B003C) // (HDMA_CH_0) HDMA Channel Source Address Register 05358 #define AT91C_HDMA_CH_0_DPIP (AT91_CAST(AT91_REG *) 0x400B0058) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register 05359 #define AT91C_HDMA_CH_0_SPIP (AT91_CAST(AT91_REG *) 0x400B0054) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register 05360 // ========== Register definition for HDMA_CH_1 peripheral ========== 05361 #define AT91C_HDMA_CH_1_DSCR (AT91_CAST(AT91_REG *) 0x400B006C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register 05362 #define AT91C_HDMA_CH_1_BDSCR (AT91_CAST(AT91_REG *) 0x400B0084) // (HDMA_CH_1) HDMA Reserved 05363 #define AT91C_HDMA_CH_1_CTRLB (AT91_CAST(AT91_REG *) 0x400B0074) // (HDMA_CH_1) HDMA Channel Control B Register 05364 #define AT91C_HDMA_CH_1_SPIP (AT91_CAST(AT91_REG *) 0x400B007C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register 05365 #define AT91C_HDMA_CH_1_SADDR (AT91_CAST(AT91_REG *) 0x400B0064) // (HDMA_CH_1) HDMA Channel Source Address Register 05366 #define AT91C_HDMA_CH_1_DPIP (AT91_CAST(AT91_REG *) 0x400B0080) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register 05367 #define AT91C_HDMA_CH_1_CFG (AT91_CAST(AT91_REG *) 0x400B0078) // (HDMA_CH_1) HDMA Channel Configuration Register 05368 #define AT91C_HDMA_CH_1_DADDR (AT91_CAST(AT91_REG *) 0x400B0068) // (HDMA_CH_1) HDMA Channel Destination Address Register 05369 #define AT91C_HDMA_CH_1_CADDR (AT91_CAST(AT91_REG *) 0x400B0088) // (HDMA_CH_1) HDMA Reserved 05370 #define AT91C_HDMA_CH_1_CTRLA (AT91_CAST(AT91_REG *) 0x400B0070) // (HDMA_CH_1) HDMA Channel Control A Register 05371 // ========== Register definition for HDMA_CH_2 peripheral ========== 05372 #define AT91C_HDMA_CH_2_BDSCR (AT91_CAST(AT91_REG *) 0x400B00AC) // (HDMA_CH_2) HDMA Reserved 05373 #define AT91C_HDMA_CH_2_CTRLB (AT91_CAST(AT91_REG *) 0x400B009C) // (HDMA_CH_2) HDMA Channel Control B Register 05374 #define AT91C_HDMA_CH_2_CADDR (AT91_CAST(AT91_REG *) 0x400B00B0) // (HDMA_CH_2) HDMA Reserved 05375 #define AT91C_HDMA_CH_2_CFG (AT91_CAST(AT91_REG *) 0x400B00A0) // (HDMA_CH_2) HDMA Channel Configuration Register 05376 #define AT91C_HDMA_CH_2_CTRLA (AT91_CAST(AT91_REG *) 0x400B0098) // (HDMA_CH_2) HDMA Channel Control A Register 05377 #define AT91C_HDMA_CH_2_SADDR (AT91_CAST(AT91_REG *) 0x400B008C) // (HDMA_CH_2) HDMA Channel Source Address Register 05378 #define AT91C_HDMA_CH_2_DPIP (AT91_CAST(AT91_REG *) 0x400B00A8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register 05379 #define AT91C_HDMA_CH_2_DADDR (AT91_CAST(AT91_REG *) 0x400B0090) // (HDMA_CH_2) HDMA Channel Destination Address Register 05380 #define AT91C_HDMA_CH_2_SPIP (AT91_CAST(AT91_REG *) 0x400B00A4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register 05381 #define AT91C_HDMA_CH_2_DSCR (AT91_CAST(AT91_REG *) 0x400B0094) // (HDMA_CH_2) HDMA Channel Descriptor Address Register 05382 // ========== Register definition for HDMA_CH_3 peripheral ========== 05383 #define AT91C_HDMA_CH_3_DSCR (AT91_CAST(AT91_REG *) 0x400B00BC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register 05384 #define AT91C_HDMA_CH_3_SADDR (AT91_CAST(AT91_REG *) 0x400B00B4) // (HDMA_CH_3) HDMA Channel Source Address Register 05385 #define AT91C_HDMA_CH_3_BDSCR (AT91_CAST(AT91_REG *) 0x400B00D4) // (HDMA_CH_3) HDMA Reserved 05386 #define AT91C_HDMA_CH_3_CTRLA (AT91_CAST(AT91_REG *) 0x400B00C0) // (HDMA_CH_3) HDMA Channel Control A Register 05387 #define AT91C_HDMA_CH_3_DPIP (AT91_CAST(AT91_REG *) 0x400B00D0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register 05388 #define AT91C_HDMA_CH_3_CTRLB (AT91_CAST(AT91_REG *) 0x400B00C4) // (HDMA_CH_3) HDMA Channel Control B Register 05389 #define AT91C_HDMA_CH_3_SPIP (AT91_CAST(AT91_REG *) 0x400B00CC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register 05390 #define AT91C_HDMA_CH_3_CFG (AT91_CAST(AT91_REG *) 0x400B00C8) // (HDMA_CH_3) HDMA Channel Configuration Register 05391 #define AT91C_HDMA_CH_3_CADDR (AT91_CAST(AT91_REG *) 0x400B00D8) // (HDMA_CH_3) HDMA Reserved 05392 #define AT91C_HDMA_CH_3_DADDR (AT91_CAST(AT91_REG *) 0x400B00B8) // (HDMA_CH_3) HDMA Channel Destination Address Register 05393 // ========== Register definition for HDMA peripheral ========== 05394 #define AT91C_HDMA_SYNC (AT91_CAST(AT91_REG *) 0x400B0014) // (HDMA) HDMA Request Synchronization Register 05395 #define AT91C_HDMA_VER (AT91_CAST(AT91_REG *) 0x400B01FC) // (HDMA) HDMA VERSION REGISTER 05396 #define AT91C_HDMA_RSVD0 (AT91_CAST(AT91_REG *) 0x400B0034) // (HDMA) HDMA Reserved 05397 #define AT91C_HDMA_CHSR (AT91_CAST(AT91_REG *) 0x400B0030) // (HDMA) HDMA Channel Handler Status Register 05398 #define AT91C_HDMA_IPNAME2 (AT91_CAST(AT91_REG *) 0x400B01F4) // (HDMA) HDMA IPNAME2 REGISTER 05399 #define AT91C_HDMA_EBCIMR (AT91_CAST(AT91_REG *) 0x400B0020) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register 05400 #define AT91C_HDMA_CHDR (AT91_CAST(AT91_REG *) 0x400B002C) // (HDMA) HDMA Channel Handler Disable Register 05401 #define AT91C_HDMA_EN (AT91_CAST(AT91_REG *) 0x400B0004) // (HDMA) HDMA Controller Enable Register 05402 #define AT91C_HDMA_GCFG (AT91_CAST(AT91_REG *) 0x400B0000) // (HDMA) HDMA Global Configuration Register 05403 #define AT91C_HDMA_IPNAME1 (AT91_CAST(AT91_REG *) 0x400B01F0) // (HDMA) HDMA IPNAME1 REGISTER 05404 #define AT91C_HDMA_LAST (AT91_CAST(AT91_REG *) 0x400B0010) // (HDMA) HDMA Software Last Transfer Flag Register 05405 #define AT91C_HDMA_FEATURES (AT91_CAST(AT91_REG *) 0x400B01F8) // (HDMA) HDMA FEATURES REGISTER 05406 #define AT91C_HDMA_CREQ (AT91_CAST(AT91_REG *) 0x400B000C) // (HDMA) HDMA Software Chunk Transfer Request Register 05407 #define AT91C_HDMA_EBCIER (AT91_CAST(AT91_REG *) 0x400B0018) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register 05408 #define AT91C_HDMA_CHER (AT91_CAST(AT91_REG *) 0x400B0028) // (HDMA) HDMA Channel Handler Enable Register 05409 #define AT91C_HDMA_ADDRSIZE (AT91_CAST(AT91_REG *) 0x400B01EC) // (HDMA) HDMA ADDRSIZE REGISTER 05410 #define AT91C_HDMA_EBCISR (AT91_CAST(AT91_REG *) 0x400B0024) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register 05411 #define AT91C_HDMA_SREQ (AT91_CAST(AT91_REG *) 0x400B0008) // (HDMA) HDMA Software Single Request Register 05412 #define AT91C_HDMA_EBCIDR (AT91_CAST(AT91_REG *) 0x400B001C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register 05413 #define AT91C_HDMA_RSVD1 (AT91_CAST(AT91_REG *) 0x400B0038) // (HDMA) HDMA Reserved 05414 05415 // ***************************************************************************** 05416 // PIO DEFINITIONS FOR AT91SAM3U4 05417 // ***************************************************************************** 05418 #define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 05419 #define AT91C_PA0_TIOB0 (AT91C_PIO_PA0) // 05420 #define AT91C_PA0_SPI0_NPCS1 (AT91C_PIO_PA0) // 05421 #define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 05422 #define AT91C_PA1_TIOA0 (AT91C_PIO_PA1) // 05423 #define AT91C_PA1_SPI0_NPCS2 (AT91C_PIO_PA1) // 05424 #define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 05425 #define AT91C_PA10_TWCK0 (AT91C_PIO_PA10) // 05426 #define AT91C_PA10_PWML3 (AT91C_PIO_PA10) // 05427 #define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 05428 #define AT91C_PA11_DRXD (AT91C_PIO_PA11) // 05429 #define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 05430 #define AT91C_PA12_DTXD (AT91C_PIO_PA12) // 05431 #define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 05432 #define AT91C_PA13_SPI0_MISO (AT91C_PIO_PA13) // 05433 #define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 05434 #define AT91C_PA14_SPI0_MOSI (AT91C_PIO_PA14) // 05435 #define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 05436 #define AT91C_PA15_SPI0_SPCK (AT91C_PIO_PA15) // 05437 #define AT91C_PA15_PWMH2 (AT91C_PIO_PA15) // 05438 #define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 05439 #define AT91C_PA16_SPI0_NPCS0 (AT91C_PIO_PA16) // 05440 #define AT91C_PA16_NCS1 (AT91C_PIO_PA16) // 05441 #define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 05442 #define AT91C_PA17_SCK0 (AT91C_PIO_PA17) // 05443 #define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 05444 #define AT91C_PA18_TXD0 (AT91C_PIO_PA18) // 05445 #define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 05446 #define AT91C_PA19_RXD0 (AT91C_PIO_PA19) // 05447 #define AT91C_PA19_SPI0_NPCS3 (AT91C_PIO_PA19) // 05448 #define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 05449 #define AT91C_PA2_TCLK0 (AT91C_PIO_PA2) // 05450 #define AT91C_PA2_ADTRG1 (AT91C_PIO_PA2) // 05451 #define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 05452 #define AT91C_PA20_TXD1 (AT91C_PIO_PA20) // 05453 #define AT91C_PA20_PWMH3 (AT91C_PIO_PA20) // 05454 #define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 05455 #define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // 05456 #define AT91C_PA21_PCK0 (AT91C_PIO_PA21) // 05457 #define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 05458 #define AT91C_PA22_TXD2 (AT91C_PIO_PA22) // 05459 #define AT91C_PA22_RTS1 (AT91C_PIO_PA22) // 05460 #define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 05461 #define AT91C_PA23_RXD2 (AT91C_PIO_PA23) // 05462 #define AT91C_PA23_CTS1 (AT91C_PIO_PA23) // 05463 #define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 05464 #define AT91C_PA24_TWD1 (AT91C_PIO_PA24) // 05465 #define AT91C_PA24_SCK1 (AT91C_PIO_PA24) // 05466 #define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 05467 #define AT91C_PA25_TWCK1 (AT91C_PIO_PA25) // 05468 #define AT91C_PA25_SCK2 (AT91C_PIO_PA25) // 05469 #define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 05470 #define AT91C_PA26_TD0 (AT91C_PIO_PA26) // 05471 #define AT91C_PA26_TCLK2 (AT91C_PIO_PA26) // 05472 #define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 05473 #define AT91C_PA27_RD0 (AT91C_PIO_PA27) // 05474 #define AT91C_PA27_PCK0 (AT91C_PIO_PA27) // 05475 #define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 05476 #define AT91C_PA28_TK0 (AT91C_PIO_PA28) // 05477 #define AT91C_PA28_PWMH0 (AT91C_PIO_PA28) // 05478 #define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 05479 #define AT91C_PA29_RK0 (AT91C_PIO_PA29) // 05480 #define AT91C_PA29_PWMH1 (AT91C_PIO_PA29) // 05481 #define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 05482 #define AT91C_PA3_MCI0_CK (AT91C_PIO_PA3) // 05483 #define AT91C_PA3_PCK1 (AT91C_PIO_PA3) // 05484 #define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 05485 #define AT91C_PA30_TF0 (AT91C_PIO_PA30) // 05486 #define AT91C_PA30_TIOA2 (AT91C_PIO_PA30) // 05487 #define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 05488 #define AT91C_PA31_RF0 (AT91C_PIO_PA31) // 05489 #define AT91C_PA31_TIOB2 (AT91C_PIO_PA31) // 05490 #define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 05491 #define AT91C_PA4_MCI0_CDA (AT91C_PIO_PA4) // 05492 #define AT91C_PA4_PWMH0 (AT91C_PIO_PA4) // 05493 #define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 05494 #define AT91C_PA5_MCI0_DA0 (AT91C_PIO_PA5) // 05495 #define AT91C_PA5_PWMH1 (AT91C_PIO_PA5) // 05496 #define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 05497 #define AT91C_PA6_MCI0_DA1 (AT91C_PIO_PA6) // 05498 #define AT91C_PA6_PWMH2 (AT91C_PIO_PA6) // 05499 #define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 05500 #define AT91C_PA7_MCI0_DA2 (AT91C_PIO_PA7) // 05501 #define AT91C_PA7_PWML0 (AT91C_PIO_PA7) // 05502 #define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 05503 #define AT91C_PA8_MCI0_DA3 (AT91C_PIO_PA8) // 05504 #define AT91C_PA8_PWML1 (AT91C_PIO_PA8) // 05505 #define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 05506 #define AT91C_PA9_TWD0 (AT91C_PIO_PA9) // 05507 #define AT91C_PA9_PWML2 (AT91C_PIO_PA9) // 05508 #define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 05509 #define AT91C_PB0_PWMH0 (AT91C_PIO_PB0) // 05510 #define AT91C_PB0_A2 (AT91C_PIO_PB0) // 05511 #define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 05512 #define AT91C_PB1_PWMH1 (AT91C_PIO_PB1) // 05513 #define AT91C_PB1_A3 (AT91C_PIO_PB1) // 05514 #define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 05515 #define AT91C_PB10_D1 (AT91C_PIO_PB10) // 05516 #define AT91C_PB10_DSR0 (AT91C_PIO_PB10) // 05517 #define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 05518 #define AT91C_PB11_D2 (AT91C_PIO_PB11) // 05519 #define AT91C_PB11_DCD0 (AT91C_PIO_PB11) // 05520 #define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 05521 #define AT91C_PB12_D3 (AT91C_PIO_PB12) // 05522 #define AT91C_PB12_RI0 (AT91C_PIO_PB12) // 05523 #define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 05524 #define AT91C_PB13_D4 (AT91C_PIO_PB13) // 05525 #define AT91C_PB13_PWMH0 (AT91C_PIO_PB13) // 05526 #define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 05527 #define AT91C_PB14_D5 (AT91C_PIO_PB14) // 05528 #define AT91C_PB14_PWMH1 (AT91C_PIO_PB14) // 05529 #define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 05530 #define AT91C_PB15_D6 (AT91C_PIO_PB15) // 05531 #define AT91C_PB15_PWMH2 (AT91C_PIO_PB15) // 05532 #define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 05533 #define AT91C_PB16_D7 (AT91C_PIO_PB16) // 05534 #define AT91C_PB16_PWMH3 (AT91C_PIO_PB16) // 05535 #define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 05536 #define AT91C_PB17_NANDOE (AT91C_PIO_PB17) // 05537 #define AT91C_PB17_PWML0 (AT91C_PIO_PB17) // 05538 #define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 05539 #define AT91C_PB18_NANDWE (AT91C_PIO_PB18) // 05540 #define AT91C_PB18_PWML1 (AT91C_PIO_PB18) // 05541 #define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 05542 #define AT91C_PB19_NRD (AT91C_PIO_PB19) // 05543 #define AT91C_PB19_PWML2 (AT91C_PIO_PB19) // 05544 #define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 05545 #define AT91C_PB2_PWMH2 (AT91C_PIO_PB2) // 05546 #define AT91C_PB2_A4 (AT91C_PIO_PB2) // 05547 #define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 05548 #define AT91C_PB20_NCS0 (AT91C_PIO_PB20) // 05549 #define AT91C_PB20_PWML3 (AT91C_PIO_PB20) // 05550 #define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 05551 #define AT91C_PB21_A21_NANDALE (AT91C_PIO_PB21) // 05552 #define AT91C_PB21_RTS2 (AT91C_PIO_PB21) // 05553 #define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 05554 #define AT91C_PB22_A22_NANDCLE (AT91C_PIO_PB22) // 05555 #define AT91C_PB22_CTS2 (AT91C_PIO_PB22) // 05556 #define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 05557 #define AT91C_PB23_NWR0_NWE (AT91C_PIO_PB23) // 05558 #define AT91C_PB23_PCK2 (AT91C_PIO_PB23) // 05559 #define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 05560 #define AT91C_PB24_NANDRDY (AT91C_PIO_PB24) // 05561 #define AT91C_PB24_PCK1 (AT91C_PIO_PB24) // 05562 #define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 05563 #define AT91C_PB25_D8 (AT91C_PIO_PB25) // 05564 #define AT91C_PB25_PWML0 (AT91C_PIO_PB25) // 05565 #define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 05566 #define AT91C_PB26_D9 (AT91C_PIO_PB26) // 05567 #define AT91C_PB26_PWML1 (AT91C_PIO_PB26) // 05568 #define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 05569 #define AT91C_PB27_D10 (AT91C_PIO_PB27) // 05570 #define AT91C_PB27_PWML2 (AT91C_PIO_PB27) // 05571 #define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 05572 #define AT91C_PB28_D11 (AT91C_PIO_PB28) // 05573 #define AT91C_PB28_PWML3 (AT91C_PIO_PB28) // 05574 #define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 05575 #define AT91C_PB29_D12 (AT91C_PIO_PB29) // 05576 #define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 05577 #define AT91C_PB3_PWMH3 (AT91C_PIO_PB3) // 05578 #define AT91C_PB3_A5 (AT91C_PIO_PB3) // 05579 #define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 05580 #define AT91C_PB30_D13 (AT91C_PIO_PB30) // 05581 #define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 05582 #define AT91C_PB31_D14 (AT91C_PIO_PB31) // 05583 #define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 05584 #define AT91C_PB4_TCLK1 (AT91C_PIO_PB4) // 05585 #define AT91C_PB4_A6 (AT91C_PIO_PB4) // 05586 #define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 05587 #define AT91C_PB5_TIOA1 (AT91C_PIO_PB5) // 05588 #define AT91C_PB5_A7 (AT91C_PIO_PB5) // 05589 #define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 05590 #define AT91C_PB6_TIOB1 (AT91C_PIO_PB6) // 05591 #define AT91C_PB6_D15 (AT91C_PIO_PB6) // 05592 #define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 05593 #define AT91C_PB7_RTS0 (AT91C_PIO_PB7) // 05594 #define AT91C_PB7_A0_NBS0 (AT91C_PIO_PB7) // 05595 #define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 05596 #define AT91C_PB8_CTS0 (AT91C_PIO_PB8) // 05597 #define AT91C_PB8_A1 (AT91C_PIO_PB8) // 05598 #define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 05599 #define AT91C_PB9_D0 (AT91C_PIO_PB9) // 05600 #define AT91C_PB9_DTR0 (AT91C_PIO_PB9) // 05601 #define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 05602 #define AT91C_PC0_A2 (AT91C_PIO_PC0) // 05603 #define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 05604 #define AT91C_PC1_A3 (AT91C_PIO_PC1) // 05605 #define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 05606 #define AT91C_PC10_A12 (AT91C_PIO_PC10) // 05607 #define AT91C_PC10_CTS3 (AT91C_PIO_PC10) // 05608 #define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 05609 #define AT91C_PC11_A13 (AT91C_PIO_PC11) // 05610 #define AT91C_PC11_RTS3 (AT91C_PIO_PC11) // 05611 #define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 05612 #define AT91C_PC12_NCS1 (AT91C_PIO_PC12) // 05613 #define AT91C_PC12_TXD3 (AT91C_PIO_PC12) // 05614 #define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 05615 #define AT91C_PC13_A2 (AT91C_PIO_PC13) // 05616 #define AT91C_PC13_RXD3 (AT91C_PIO_PC13) // 05617 #define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 05618 #define AT91C_PC14_A3 (AT91C_PIO_PC14) // 05619 #define AT91C_PC14_SPI0_NPCS2 (AT91C_PIO_PC14) // 05620 #define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 05621 #define AT91C_PC15_NWR1_NBS1 (AT91C_PIO_PC15) // 05622 #define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 05623 #define AT91C_PC16_NCS2 (AT91C_PIO_PC16) // 05624 #define AT91C_PC16_PWML3 (AT91C_PIO_PC16) // 05625 #define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 05626 #define AT91C_PC17_NCS3 (AT91C_PIO_PC17) // 05627 #define AT91C_PC17_A24 (AT91C_PIO_PC17) // 05628 #define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 05629 #define AT91C_PC18_NWAIT (AT91C_PIO_PC18) // 05630 #define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 05631 #define AT91C_PC19_SCK3 (AT91C_PIO_PC19) // 05632 #define AT91C_PC19_NPCS1 (AT91C_PIO_PC19) // 05633 #define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 05634 #define AT91C_PC2_A4 (AT91C_PIO_PC2) // 05635 #define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 05636 #define AT91C_PC20_A14 (AT91C_PIO_PC20) // 05637 #define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 05638 #define AT91C_PC21_A15 (AT91C_PIO_PC21) // 05639 #define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 05640 #define AT91C_PC22_A16 (AT91C_PIO_PC22) // 05641 #define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 05642 #define AT91C_PC23_A17 (AT91C_PIO_PC23) // 05643 #define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 05644 #define AT91C_PC24_A18 (AT91C_PIO_PC24) // 05645 #define AT91C_PC24_PWMH0 (AT91C_PIO_PC24) // 05646 #define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 05647 #define AT91C_PC25_A19 (AT91C_PIO_PC25) // 05648 #define AT91C_PC25_PWMH1 (AT91C_PIO_PC25) // 05649 #define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 05650 #define AT91C_PC26_A20 (AT91C_PIO_PC26) // 05651 #define AT91C_PC26_PWMH2 (AT91C_PIO_PC26) // 05652 #define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 05653 #define AT91C_PC27_A23 (AT91C_PIO_PC27) // 05654 #define AT91C_PC27_PWMH3 (AT91C_PIO_PC27) // 05655 #define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 05656 #define AT91C_PC28_A24 (AT91C_PIO_PC28) // 05657 #define AT91C_PC28_MCI0_DA4 (AT91C_PIO_PC28) // 05658 #define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 05659 #define AT91C_PC29_PWML0 (AT91C_PIO_PC29) // 05660 #define AT91C_PC29_MCI0_DA5 (AT91C_PIO_PC29) // 05661 #define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 05662 #define AT91C_PC3_A5 (AT91C_PIO_PC3) // 05663 #define AT91C_PC3_SPI0_NPCS1 (AT91C_PIO_PC3) // 05664 #define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 05665 #define AT91C_PC30_PWML1 (AT91C_PIO_PC30) // 05666 #define AT91C_PC30_MCI0_DA6 (AT91C_PIO_PC30) // 05667 #define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 05668 #define AT91C_PC31_PWML2 (AT91C_PIO_PC31) // 05669 #define AT91C_PC31_MCI0_DA7 (AT91C_PIO_PC31) // 05670 #define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 05671 #define AT91C_PC4_A6 (AT91C_PIO_PC4) // 05672 #define AT91C_PC4_SPI0_NPCS2 (AT91C_PIO_PC4) // 05673 #define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 05674 #define AT91C_PC5_A7 (AT91C_PIO_PC5) // 05675 #define AT91C_PC5_SPI0_NPCS3 (AT91C_PIO_PC5) // 05676 #define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 05677 #define AT91C_PC6_A8 (AT91C_PIO_PC6) // 05678 #define AT91C_PC6_PWML0 (AT91C_PIO_PC6) // 05679 #define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 05680 #define AT91C_PC7_A9 (AT91C_PIO_PC7) // 05681 #define AT91C_PC7_PWML1 (AT91C_PIO_PC7) // 05682 #define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 05683 #define AT91C_PC8_A10 (AT91C_PIO_PC8) // 05684 #define AT91C_PC8_PWML2 (AT91C_PIO_PC8) // 05685 #define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 05686 #define AT91C_PC9_A11 (AT91C_PIO_PC9) // 05687 #define AT91C_PC9_PWML3 (AT91C_PIO_PC9) // 05688 05689 // ***************************************************************************** 05690 // PERIPHERAL ID DEFINITIONS FOR AT91SAM3U4 05691 // ***************************************************************************** 05692 #define AT91C_ID_SUPC ( 0) // SUPPLY CONTROLLER 05693 #define AT91C_ID_RSTC ( 1) // RESET CONTROLLER 05694 #define AT91C_ID_RTC ( 2) // REAL TIME CLOCK 05695 #define AT91C_ID_RTT ( 3) // REAL TIME TIMER 05696 #define AT91C_ID_WDG ( 4) // WATCHDOG TIMER 05697 #define AT91C_ID_PMC ( 5) // PMC 05698 #define AT91C_ID_EFC0 ( 6) // EFC0 05699 #define AT91C_ID_EFC1 ( 7) // EFC1 05700 #define AT91C_ID_DBGU ( 8) // DBGU 05701 #define AT91C_ID_HSMC4 ( 9) // HSMC4 05702 #define AT91C_ID_PIOA (10) // Parallel IO Controller A 05703 #define AT91C_ID_PIOB (11) // Parallel IO Controller B 05704 #define AT91C_ID_PIOC (12) // Parallel IO Controller C 05705 #define AT91C_ID_US0 (13) // USART 0 05706 #define AT91C_ID_US1 (14) // USART 1 05707 #define AT91C_ID_US2 (15) // USART 2 05708 #define AT91C_ID_US3 (16) // USART 3 05709 #define AT91C_ID_MCI0 (17) // Multimedia Card Interface 05710 #define AT91C_ID_TWI0 (18) // TWI 0 05711 #define AT91C_ID_TWI1 (19) // TWI 1 05712 #define AT91C_ID_SPI0 (20) // Serial Peripheral Interface 05713 #define AT91C_ID_SSC0 (21) // Serial Synchronous Controller 0 05714 #define AT91C_ID_TC0 (22) // Timer Counter 0 05715 #define AT91C_ID_TC1 (23) // Timer Counter 1 05716 #define AT91C_ID_TC2 (24) // Timer Counter 2 05717 #define AT91C_ID_PWMC (25) // Pulse Width Modulation Controller 05718 #define AT91C_ID_ADC12B (26) // 12-bit ADC Controller (ADC12B) 05719 #define AT91C_ID_ADC (27) // 10-bit ADC Controller (ADC) 05720 #define AT91C_ID_HDMA (28) // HDMA 05721 #define AT91C_ID_UDPHS (29) // USB Device High Speed 05722 #define AT91C_ALL_INT (0x3FFFFFFF) // ALL VALID INTERRUPTS 05723 05724 // ***************************************************************************** 05725 // BASE ADDRESS DEFINITIONS FOR AT91SAM3U4 05726 // ***************************************************************************** 05727 #define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0x400E0000) // (SYS) Base Address 05728 #define AT91C_BASE_HSMC4_CS0 (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0070) // (HSMC4_CS0) Base Address 05729 #define AT91C_BASE_HSMC4_CS1 (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0084) // (HSMC4_CS1) Base Address 05730 #define AT91C_BASE_HSMC4_CS2 (AT91_CAST(AT91PS_HSMC4_CS) 0x400E0098) // (HSMC4_CS2) Base Address 05731 #define AT91C_BASE_HSMC4_CS3 (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00AC) // (HSMC4_CS3) Base Address 05732 #define AT91C_BASE_HSMC4_NFC (AT91_CAST(AT91PS_HSMC4_CS) 0x400E00FC) // (HSMC4_NFC) Base Address 05733 #define AT91C_BASE_HSMC4 (AT91_CAST(AT91PS_HSMC4) 0x400E0000) // (HSMC4) Base Address 05734 #define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_HMATRIX2) 0x400E0200) // (MATRIX) Base Address 05735 #define AT91C_BASE_NVIC (AT91_CAST(AT91PS_NVIC) 0xE000E000) // (NVIC) Base Address 05736 #define AT91C_BASE_MPU (AT91_CAST(AT91PS_MPU) 0xE000ED90) // (MPU) Base Address 05737 #define AT91C_BASE_CM3 (AT91_CAST(AT91PS_CM3) 0xE000ED00) // (CM3) Base Address 05738 #define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0x400E0700) // (PDC_DBGU) Base Address 05739 #define AT91C_BASE_DBGU ( 0x400E0600) // (DBGU) Base Address 05740 #define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0x400E0C00) // (PIOA) Base Address 05741 #define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0x400E0E00) // (PIOB) Base Address 05742 #define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0x400E1000) // (PIOC) Base Address 05743 #define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0x400E0400) // (PMC) Base Address 05744 #define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0x400E041C) // (CKGR) Base Address 05745 #define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0x400E1200) // (RSTC) Base Address 05746 #define AT91C_BASE_SUPC (AT91_CAST(AT91PS_SUPC) 0x400E1210) // (SUPC) Base Address 05747 #define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0x400E1230) // (RTTC) Base Address 05748 #define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0x400E1250) // (WDTC) Base Address 05749 #define AT91C_BASE_RTC (AT91_CAST(AT91PS_RTC) 0x400E1260) // (RTC) Base Address 05750 #define AT91C_BASE_ADC0 (AT91_CAST(AT91PS_ADC) 0x400AC000) // (ADC0) Base Address 05751 #define AT91C_BASE_ADC12B (AT91_CAST(AT91PS_ADC12B ) 0x400A8000) // (ADC12B ) Base Address 05752 #define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0x40080000) // (TC0) Base Address 05753 #define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0x40080040) // (TC1) Base Address 05754 #define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0x40080080) // (TC2) Base Address 05755 #define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0x40080000) // (TCB0) Base Address 05756 #define AT91C_BASE_TCB1 (AT91_CAST(AT91PS_TCB) 0x40080040) // (TCB1) Base Address 05757 #define AT91C_BASE_TCB2 (AT91_CAST(AT91PS_TCB) 0x40080080) // (TCB2) Base Address 05758 #define AT91C_BASE_EFC0 (AT91_CAST(AT91PS_EFC) 0x400E0800) // (EFC0) Base Address 05759 #define AT91C_BASE_EFC1 (AT91_CAST(AT91PS_EFC) 0x400E0A00) // (EFC1) Base Address 05760 #define AT91C_BASE_MCI0 (AT91_CAST(AT91PS_MCI) 0x40000000) // (MCI0) Base Address 05761 #define AT91C_BASE_PDC_TWI0 (AT91_CAST(AT91PS_PDC) 0x40084100) // (PDC_TWI0) Base Address 05762 #define AT91C_BASE_PDC_TWI1 (AT91_CAST(AT91PS_PDC) 0x40088100) // (PDC_TWI1) Base Address 05763 #define AT91C_BASE_TWI0 (AT91_CAST(AT91PS_TWI) 0x40084000) // (TWI0) Base Address 05764 #define AT91C_BASE_TWI1 (AT91_CAST(AT91PS_TWI) 0x40088000) // (TWI1) Base Address 05765 #define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0x40090100) // (PDC_US0) Base Address 05766 #define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0x40090000) // (US0) Base Address 05767 #define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0x40094100) // (PDC_US1) Base Address 05768 #define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0x40094000) // (US1) Base Address 05769 #define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0x40098100) // (PDC_US2) Base Address 05770 #define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0x40098000) // (US2) Base Address 05771 #define AT91C_BASE_PDC_US3 (AT91_CAST(AT91PS_PDC) 0x4009C100) // (PDC_US3) Base Address 05772 #define AT91C_BASE_US3 (AT91_CAST(AT91PS_USART) 0x4009C000) // (US3) Base Address 05773 #define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0x40004100) // (PDC_SSC0) Base Address 05774 #define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0x40004000) // (SSC0) Base Address 05775 #define AT91C_BASE_PDC_PWMC (AT91_CAST(AT91PS_PDC) 0x4008C100) // (PDC_PWMC) Base Address 05776 #define AT91C_BASE_PWMC_CH0 (AT91_CAST(AT91PS_PWMC_CH) 0x4008C200) // (PWMC_CH0) Base Address 05777 #define AT91C_BASE_PWMC_CH1 (AT91_CAST(AT91PS_PWMC_CH) 0x4008C220) // (PWMC_CH1) Base Address 05778 #define AT91C_BASE_PWMC_CH2 (AT91_CAST(AT91PS_PWMC_CH) 0x4008C240) // (PWMC_CH2) Base Address 05779 #define AT91C_BASE_PWMC_CH3 (AT91_CAST(AT91PS_PWMC_CH) 0x4008C260) // (PWMC_CH3) Base Address 05780 #define AT91C_BASE_PWMC (AT91_CAST(AT91PS_PWMC) 0x4008C000) // (PWMC) Base Address 05781 #define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0x40008000) // (SPI0) Base Address 05782 #define AT91C_BASE_UDPHS_EPTFIFO (AT91_CAST(AT91PS_UDPHS_EPTFIFO) 0x20180000) // (UDPHS_EPTFIFO) Base Address 05783 #define AT91C_BASE_UDPHS_EPT_0 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4100) // (UDPHS_EPT_0) Base Address 05784 #define AT91C_BASE_UDPHS_EPT_1 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4120) // (UDPHS_EPT_1) Base Address 05785 #define AT91C_BASE_UDPHS_EPT_2 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4140) // (UDPHS_EPT_2) Base Address 05786 #define AT91C_BASE_UDPHS_EPT_3 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4160) // (UDPHS_EPT_3) Base Address 05787 #define AT91C_BASE_UDPHS_EPT_4 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A4180) // (UDPHS_EPT_4) Base Address 05788 #define AT91C_BASE_UDPHS_EPT_5 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41A0) // (UDPHS_EPT_5) Base Address 05789 #define AT91C_BASE_UDPHS_EPT_6 (AT91_CAST(AT91PS_UDPHS_EPT) 0x400A41C0) // (UDPHS_EPT_6) Base Address 05790 #define AT91C_BASE_UDPHS_DMA_1 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4310) // (UDPHS_DMA_1) Base Address 05791 #define AT91C_BASE_UDPHS_DMA_2 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4320) // (UDPHS_DMA_2) Base Address 05792 #define AT91C_BASE_UDPHS_DMA_3 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4330) // (UDPHS_DMA_3) Base Address 05793 #define AT91C_BASE_UDPHS_DMA_4 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4340) // (UDPHS_DMA_4) Base Address 05794 #define AT91C_BASE_UDPHS_DMA_5 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4350) // (UDPHS_DMA_5) Base Address 05795 #define AT91C_BASE_UDPHS_DMA_6 (AT91_CAST(AT91PS_UDPHS_DMA) 0x400A4360) // (UDPHS_DMA_6) Base Address 05796 #define AT91C_BASE_UDPHS (AT91_CAST(AT91PS_UDPHS) 0x400A4000) // (UDPHS) Base Address 05797 #define AT91C_BASE_HDMA_CH_0 (AT91_CAST(AT91PS_HDMA_CH) 0x400B003C) // (HDMA_CH_0) Base Address 05798 #define AT91C_BASE_HDMA_CH_1 (AT91_CAST(AT91PS_HDMA_CH) 0x400B0064) // (HDMA_CH_1) Base Address 05799 #define AT91C_BASE_HDMA_CH_2 (AT91_CAST(AT91PS_HDMA_CH) 0x400B008C) // (HDMA_CH_2) Base Address 05800 #define AT91C_BASE_HDMA_CH_3 (AT91_CAST(AT91PS_HDMA_CH) 0x400B00B4) // (HDMA_CH_3) Base Address 05801 #define AT91C_BASE_HDMA (AT91_CAST(AT91PS_HDMA) 0x400B0000) // (HDMA) Base Address 05802 05803 // ***************************************************************************** 05804 // MEMORY MAPPING DEFINITIONS FOR AT91SAM3U4 05805 // ***************************************************************************** 05806 // ITCM 05807 #define AT91C_ITCM (0x00100000) // Maximum ITCM Area base address 05808 #define AT91C_ITCM_SIZE (0x00010000) // Maximum ITCM Area size in byte (64 Kbytes) 05809 // DTCM 05810 #define AT91C_DTCM (0x00200000) // Maximum DTCM Area base address 05811 #define AT91C_DTCM_SIZE (0x00010000) // Maximum DTCM Area size in byte (64 Kbytes) 05812 // IRAM 05813 #define AT91C_IRAM (0x20000000) // Maximum Internal SRAM base address 05814 #define AT91C_IRAM_SIZE (0x00008000) // Maximum Internal SRAM size in byte (32 Kbytes) 05815 // IRAM_MIN 05816 #define AT91C_IRAM_MIN (0x00300000) // Minimum Internal RAM base address 05817 #define AT91C_IRAM_MIN_SIZE (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes) 05818 // IROM 05819 #define AT91C_IROM (0x00180000) // Internal ROM base address 05820 #define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes) 05821 // IFLASH0 05822 #define AT91C_IFLASH0 (0x00080000) // Maximum IFLASH Area : 128Kbyte base address 05823 #define AT91C_IFLASH0_SIZE (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes) 05824 #define AT91C_IFLASH0_PAGE_SIZE (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes 05825 #define AT91C_IFLASH0_LOCK_REGION_SIZE (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes 05826 #define AT91C_IFLASH0_NB_OF_PAGES (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes 05827 #define AT91C_IFLASH0_NB_OF_LOCK_BITS (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 16 bytes 05828 // IFLASH1 05829 #define AT91C_IFLASH1 (0x00100000) // Maximum IFLASH Area : 128Kbyte base address 05830 #define AT91C_IFLASH1_SIZE (0x00020000) // Maximum IFLASH Area : 128Kbyte size in byte (128 Kbytes) 05831 #define AT91C_IFLASH1_PAGE_SIZE (256) // Maximum IFLASH Area : 128Kbyte Page Size: 256 bytes 05832 #define AT91C_IFLASH1_LOCK_REGION_SIZE (8192) // Maximum IFLASH Area : 128Kbyte Lock Region Size: 8 Kbytes 05833 #define AT91C_IFLASH1_NB_OF_PAGES (512) // Maximum IFLASH Area : 128Kbyte Number of Pages: 512 bytes 05834 #define AT91C_IFLASH1_NB_OF_LOCK_BITS (16) // Maximum IFLASH Area : 128Kbyte Number of Lock Bits: 16 bytes 05835 // EBI_CS0 05836 #define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address 05837 #define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes) 05838 // EBI_CS1 05839 #define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address 05840 #define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes) 05841 // EBI_SDRAM 05842 #define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address 05843 #define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes) 05844 // EBI_SDRAM_16BIT 05845 #define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address 05846 #define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes) 05847 // EBI_SDRAM_32BIT 05848 #define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address 05849 #define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes) 05850 // EBI_CS2 05851 #define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address 05852 #define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes) 05853 // EBI_CS3 05854 #define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address 05855 #define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes) 05856 // EBI_SM 05857 #define AT91C_EBI_SM (0x40000000) // NANDFLASH on EBI Chip Select 3 base address 05858 #define AT91C_EBI_SM_SIZE (0x10000000) // NANDFLASH on EBI Chip Select 3 size in byte (262144 Kbytes) 05859 // EBI_CS4 05860 #define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address 05861 #define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes) 05862 // EBI_CF0 05863 #define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address 05864 #define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes) 05865 // EBI_CS5 05866 #define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address 05867 #define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes) 05868 // EBI_CF1 05869 #define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on EBIChip Select 5 base address 05870 #define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on EBIChip Select 5 size in byte (262144 Kbytes) 05871 05873 typedef enum IRQn 05874 { 05875 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 05876 NonMaskableInt_IRQn = -14, 05877 MemoryManagement_IRQn = -12, 05878 BusFault_IRQn = -11, 05879 UsageFault_IRQn = -10, 05880 SVCall_IRQn = -5, 05881 DebugMonitor_IRQn = -4, 05882 PendSV_IRQn = -2, 05883 SysTick_IRQn = -1, 05885 /****** AT91SAM3U4 specific Interrupt Numbers *********************************************************/ 05886 IROn_SUPC = AT91C_ID_SUPC , // SUPPLY CONTROLLER 05887 IROn_RSTC = AT91C_ID_RSTC , // RESET CONTROLLER 05888 IROn_RTC = AT91C_ID_RTC , // REAL TIME CLOCK 05889 IROn_RTT = AT91C_ID_RTT , // REAL TIME TIMER 05890 IROn_WDG = AT91C_ID_WDG , // WATCHDOG TIMER 05891 IROn_PMC = AT91C_ID_PMC , // PMC 05892 IROn_EFC0 = AT91C_ID_EFC0 , // EFC0 05893 IROn_EFC1 = AT91C_ID_EFC1 , // EFC1 05894 IROn_DBGU = AT91C_ID_DBGU , // DBGU 05895 IROn_HSMC4 = AT91C_ID_HSMC4, // HSMC4 05896 IROn_PIOA = AT91C_ID_PIOA , // Parallel IO Controller A 05897 IROn_PIOB = AT91C_ID_PIOB , // Parallel IO Controller B 05898 IROn_PIOC = AT91C_ID_PIOC , // Parallel IO Controller C 05899 IROn_US0 = AT91C_ID_US0 , // USART 0 05900 IROn_US1 = AT91C_ID_US1 , // USART 1 05901 IROn_US2 = AT91C_ID_US2 , // USART 2 05902 IROn_US3 = AT91C_ID_US3 , // USART 3 05903 IROn_MCI0 = AT91C_ID_MCI0 , // Multimedia Card Interface 05904 IROn_TWI0 = AT91C_ID_TWI0 , // TWI 0 05905 IROn_TWI1 = AT91C_ID_TWI1 , // TWI 1 05906 IROn_SPI0 = AT91C_ID_SPI0 , // Serial Peripheral Interface 05907 IROn_SSC0 = AT91C_ID_SSC0 , // Serial Synchronous Controller 0 05908 IROn_TC0 = AT91C_ID_TC0 , // Timer Counter 0 05909 IROn_TC1 = AT91C_ID_TC1 , // Timer Counter 1 05910 IROn_TC2 = AT91C_ID_TC2 , // Timer Counter 2 05911 IROn_PWMC = AT91C_ID_PWMC , // Pulse Width Modulation Controller 05912 IROn_ADCC0 = AT91C_ID_ADCC0, // ADC controller0 05913 IROn_ADCC1 = AT91C_ID_ADCC1, // ADC controller1 05914 IROn_HDMA = AT91C_ID_HDMA , // HDMA 05915 IROn_UDPHS = AT91C_ID_UDPHS // USB Device High Speed 05916 } IRQn_Type; 05917 05918 05919 #endif