ITM_Type Struct Reference

Structure type to access the Instrumentation Trace Macrocell Register (ITM). More...

#include <core_cm3.h>

Collaboration diagram for ITM_Type:

Data Fields
union {
__O uint8_t   u8
__O uint16_t   u16
__O uint32_t   u32
}	PORT [32]
uint32_t	RESERVED0 [864]
__IO uint32_t	TER
uint32_t	RESERVED1 [15]
__IO uint32_t	TPR
uint32_t	RESERVED2 [15]
__IO uint32_t	TCR
union {
__O uint8_t   u8
__O uint16_t   u16
__O uint32_t   u32
}	PORT [32]
uint32_t	RESERVED3 [29]
__O uint32_t	IWR
__I uint32_t	IRR
__IO uint32_t	IMCR
uint32_t	RESERVED4 [43]
__O uint32_t	LAR
__I uint32_t	LSR
uint32_t	RESERVED5 [6]
__I uint32_t	PID4
__I uint32_t	PID5
__I uint32_t	PID6
__I uint32_t	PID7
__I uint32_t	PID0
__I uint32_t	PID1
__I uint32_t	PID2
__I uint32_t	PID3
__I uint32_t	CID0
__I uint32_t	CID1
__I uint32_t	CID2
__I uint32_t	CID3

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Detailed Description

Structure type to access the Instrumentation Trace Macrocell Register (ITM).

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Field Documentation

__O uint8_t ITM_Type::u8

Offset: 0x000 ( /W) ITM Stimulus Port 8-bit

__O uint16_t ITM_Type::u16

Offset: 0x000 ( /W) ITM Stimulus Port 16-bit

__O uint32_t ITM_Type::u32

Offset: 0x000 ( /W) ITM Stimulus Port 32-bit

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

uint32_t ITM_Type::RESERVED0

__IO uint32_t ITM_Type::TER

Offset: 0xE00 (R/W) ITM Trace Enable Register

uint32_t ITM_Type::RESERVED1

__IO uint32_t ITM_Type::TPR

Offset: 0xE40 (R/W) ITM Trace Privilege Register

uint32_t ITM_Type::RESERVED2

__IO uint32_t ITM_Type::TCR

Offset: 0xE80 (R/W) ITM Trace Control Register

__O { ... } ITM_Type::PORT[32]

Offset: 0x000 ( /W) ITM Stimulus Port Registers

uint32_t ITM_Type::RESERVED3[29]

__O uint32_t ITM_Type::IWR

Offset: 0xEF8 ( /W) ITM Integration Write Register

__I uint32_t ITM_Type::IRR

Offset: 0xEFC (R/ ) ITM Integration Read Register

__IO uint32_t ITM_Type::IMCR

Offset: 0xF00 (R/W) ITM Integration Mode Control Register

uint32_t ITM_Type::RESERVED4[43]

__O uint32_t ITM_Type::LAR

Offset: 0xFB0 ( /W) ITM Lock Access Register

__I uint32_t ITM_Type::LSR

Offset: 0xFB4 (R/ ) ITM Lock Status Register

uint32_t ITM_Type::RESERVED5[6]

__I uint32_t ITM_Type::PID4

Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

__I uint32_t ITM_Type::PID5

Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

__I uint32_t ITM_Type::PID6

Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

__I uint32_t ITM_Type::PID7

Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

__I uint32_t ITM_Type::PID0

Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

__I uint32_t ITM_Type::PID1

Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

__I uint32_t ITM_Type::PID2

Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

__I uint32_t ITM_Type::PID3

Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

__I uint32_t ITM_Type::CID0

Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

__I uint32_t ITM_Type::CID1

Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

__I uint32_t ITM_Type::CID2

Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

__I uint32_t ITM_Type::CID3

Offset: 0xFFC (R/ ) ITM Component Identification Register #3

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The documentation for this struct was generated from the following files:

• include/arch/cm3/core_cm3.h
• include/arch/cm3/core_cm4.h