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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 /**************************************************************************/ 00023 #if defined ( __ICCARM__ ) 00024 #pragma system_include /* treat file as system include file for MISRA check */ 00025 #endif 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 #ifndef __CORE_CM4_H_GENERIC 00032 #define __CORE_CM4_H_GENERIC 00033 00048 /******************************************************************************* 00049 * CMSIS definitions 00050 ******************************************************************************/ 00055 /* CMSIS CM4 definitions */ 00056 #define __CM4_CMSIS_VERSION_MAIN (0x03) 00057 #define __CM4_CMSIS_VERSION_SUB (0x01) 00058 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ 00059 __CM4_CMSIS_VERSION_SUB ) 00061 #define __CORTEX_M (0x04) 00064 #if defined ( __CC_ARM ) 00065 #define __ASM __asm 00066 #define __INLINE __inline 00067 #define __STATIC_INLINE static __inline 00068 00069 #elif defined ( __ICCARM__ ) 00070 #define __ASM __asm 00071 #define __INLINE inline 00072 #define __STATIC_INLINE static inline 00073 00074 #elif defined ( __TMS470__ ) 00075 #define __ASM __asm 00076 #define __STATIC_INLINE static inline 00077 00078 #elif defined ( __GNUC__ ) 00079 #define __ASM __asm 00080 #define __INLINE inline 00081 #define __STATIC_INLINE static inline 00082 00083 #elif defined ( __TASKING__ ) 00084 #define __ASM __asm 00085 #define __INLINE inline 00086 #define __STATIC_INLINE static inline 00087 00088 #endif 00089 00092 #if defined ( __CC_ARM ) 00093 #if defined __TARGET_FPU_VFP 00094 #if (__FPU_PRESENT == 1) 00095 #define __FPU_USED 1 00096 #else 00097 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00098 #define __FPU_USED 0 00099 #endif 00100 #else 00101 #define __FPU_USED 0 00102 #endif 00103 00104 #elif defined ( __ICCARM__ ) 00105 #if defined __ARMVFP__ 00106 #if (__FPU_PRESENT == 1) 00107 #define __FPU_USED 1 00108 #else 00109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00110 #define __FPU_USED 0 00111 #endif 00112 #else 00113 #define __FPU_USED 0 00114 #endif 00115 00116 #elif defined ( __TMS470__ ) 00117 #if defined __TI_VFP_SUPPORT__ 00118 #if (__FPU_PRESENT == 1) 00119 #define __FPU_USED 1 00120 #else 00121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00122 #define __FPU_USED 0 00123 #endif 00124 #else 00125 #define __FPU_USED 0 00126 #endif 00127 00128 #elif defined ( __GNUC__ ) 00129 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00130 #if (__FPU_PRESENT == 1) 00131 #define __FPU_USED 1 00132 #else 00133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00134 #define __FPU_USED 0 00135 #endif 00136 #else 00137 #define __FPU_USED 0 00138 #endif 00139 00140 #elif defined ( __TASKING__ ) 00141 #if defined __FPU_VFP__ 00142 #if (__FPU_PRESENT == 1) 00143 #define __FPU_USED 1 00144 #else 00145 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00146 #define __FPU_USED 0 00147 #endif 00148 #else 00149 #define __FPU_USED 0 00150 #endif 00151 #endif 00152 00153 #include <stdint.h> /* standard types definitions */ 00154 #include <arch/cm3/core_cmInstr.h> /* Core Instruction Access */ 00155 #include <arch/cm3/core_cmFunc.h> /* Core Function Access */ 00156 #include <arch/cm3/core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */ 00157 00158 #endif /* __CORE_CM4_H_GENERIC */ 00159 00160 #ifndef __CMSIS_GENERIC 00161 00162 #ifndef __CORE_CM4_H_DEPENDANT 00163 #define __CORE_CM4_H_DEPENDANT 00164 00165 /* check device defines and use defaults */ 00166 #if defined __CHECK_DEVICE_DEFINES 00167 #ifndef __CM4_REV 00168 #define __CM4_REV 0x0000 00169 #warning "__CM4_REV not defined in device header file; using default!" 00170 #endif 00171 00172 #ifndef __FPU_PRESENT 00173 #define __FPU_PRESENT 0 00174 #warning "__FPU_PRESENT not defined in device header file; using default!" 00175 #endif 00176 00177 #ifndef __MPU_PRESENT 00178 #define __MPU_PRESENT 0 00179 #warning "__MPU_PRESENT not defined in device header file; using default!" 00180 #endif 00181 00182 #ifndef __NVIC_PRIO_BITS 00183 #define __NVIC_PRIO_BITS 4 00184 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00185 #endif 00186 00187 #ifndef __Vendor_SysTickConfig 00188 #define __Vendor_SysTickConfig 0 00189 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00190 #endif 00191 #endif 00192 00193 /* IO definitions (access restrictions to peripheral registers) */ 00201 #ifdef __cplusplus 00202 #define __I volatile 00203 #else 00204 #define __I volatile const 00205 #endif 00206 #define __O volatile 00207 #define __IO volatile 00209 00213 /******************************************************************************* 00214 * Register Abstraction 00215 Core Register contain: 00216 - Core Register 00217 - Core NVIC Register 00218 - Core SCB Register 00219 - Core SysTick Register 00220 - Core Debug Register 00221 - Core MPU Register 00222 - Core FPU Register 00223 ******************************************************************************/ 00224 00236 typedef union 00237 { 00238 struct 00239 { 00240 #if (__CORTEX_M != 0x04) 00241 uint32_t _reserved0:27; 00242 #else 00243 uint32_t _reserved0:16; 00244 uint32_t GE:4; 00245 uint32_t _reserved1:7; 00246 #endif 00247 uint32_t Q:1; 00248 uint32_t V:1; 00249 uint32_t C:1; 00250 uint32_t Z:1; 00251 uint32_t N:1; 00252 } b; 00253 uint32_t w; 00254 } APSR_Type; 00255 00256 00259 typedef union 00260 { 00261 struct 00262 { 00263 uint32_t ISR:9; 00264 uint32_t _reserved0:23; 00265 } b; 00266 uint32_t w; 00267 } IPSR_Type; 00268 00269 00272 typedef union 00273 { 00274 struct 00275 { 00276 uint32_t ISR:9; 00277 #if (__CORTEX_M != 0x04) 00278 uint32_t _reserved0:15; 00279 #else 00280 uint32_t _reserved0:7; 00281 uint32_t GE:4; 00282 uint32_t _reserved1:4; 00283 #endif 00284 uint32_t T:1; 00285 uint32_t IT:2; 00286 uint32_t Q:1; 00287 uint32_t V:1; 00288 uint32_t C:1; 00289 uint32_t Z:1; 00290 uint32_t N:1; 00291 } b; 00292 uint32_t w; 00293 } xPSR_Type; 00294 00295 00298 typedef union 00299 { 00300 struct 00301 { 00302 uint32_t nPRIV:1; 00303 uint32_t SPSEL:1; 00304 uint32_t FPCA:1; 00305 uint32_t _reserved0:29; 00306 } b; 00307 uint32_t w; 00308 } CONTROL_Type; 00309 00321 typedef struct 00322 { 00323 __IO uint32_t ISER[8]; 00324 uint32_t RESERVED0[24]; 00325 __IO uint32_t ICER[8]; 00326 uint32_t RSERVED1[24]; 00327 __IO uint32_t ISPR[8]; 00328 uint32_t RESERVED2[24]; 00329 __IO uint32_t ICPR[8]; 00330 uint32_t RESERVED3[24]; 00331 __IO uint32_t IABR[8]; 00332 uint32_t RESERVED4[56]; 00333 __IO uint8_t IP[240]; 00334 uint32_t RESERVED5[644]; 00335 __O uint32_t STIR; 00336 } NVIC_Type; 00337 00338 /* Software Triggered Interrupt Register Definitions */ 00339 #define NVIC_STIR_INTID_Pos 0 00340 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) 00342 00353 typedef struct 00354 { 00355 __I uint32_t CPUID; 00356 __IO uint32_t ICSR; 00357 __IO uint32_t VTOR; 00358 __IO uint32_t AIRCR; 00359 __IO uint32_t SCR; 00360 __IO uint32_t CCR; 00361 __IO uint8_t SHP[12]; 00362 __IO uint32_t SHCSR; 00363 __IO uint32_t CFSR; 00364 __IO uint32_t HFSR; 00365 __IO uint32_t DFSR; 00366 __IO uint32_t MMFAR; 00367 __IO uint32_t BFAR; 00368 __IO uint32_t AFSR; 00369 __I uint32_t PFR[2]; 00370 __I uint32_t DFR; 00371 __I uint32_t ADR; 00372 __I uint32_t MMFR[4]; 00373 __I uint32_t ISAR[5]; 00374 uint32_t RESERVED0[5]; 00375 __IO uint32_t CPACR; 00376 } SCB_Type; 00377 00378 /* SCB CPUID Register Definitions */ 00379 #define SCB_CPUID_IMPLEMENTER_Pos 24 00380 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 00382 #define SCB_CPUID_VARIANT_Pos 20 00383 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 00385 #define SCB_CPUID_ARCHITECTURE_Pos 16 00386 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 00388 #define SCB_CPUID_PARTNO_Pos 4 00389 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 00391 #define SCB_CPUID_REVISION_Pos 0 00392 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) 00394 /* SCB Interrupt Control State Register Definitions */ 00395 #define SCB_ICSR_NMIPENDSET_Pos 31 00396 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 00398 #define SCB_ICSR_PENDSVSET_Pos 28 00399 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 00401 #define SCB_ICSR_PENDSVCLR_Pos 27 00402 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 00404 #define SCB_ICSR_PENDSTSET_Pos 26 00405 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 00407 #define SCB_ICSR_PENDSTCLR_Pos 25 00408 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 00410 #define SCB_ICSR_ISRPREEMPT_Pos 23 00411 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 00413 #define SCB_ICSR_ISRPENDING_Pos 22 00414 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 00416 #define SCB_ICSR_VECTPENDING_Pos 12 00417 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 00419 #define SCB_ICSR_RETTOBASE_Pos 11 00420 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 00422 #define SCB_ICSR_VECTACTIVE_Pos 0 00423 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) 00425 /* SCB Vector Table Offset Register Definitions */ 00426 #define SCB_VTOR_TBLOFF_Pos 7 00427 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 00429 /* SCB Application Interrupt and Reset Control Register Definitions */ 00430 #define SCB_AIRCR_VECTKEY_Pos 16 00431 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 00433 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 00434 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 00436 #define SCB_AIRCR_ENDIANESS_Pos 15 00437 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 00439 #define SCB_AIRCR_PRIGROUP_Pos 8 00440 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 00442 #define SCB_AIRCR_SYSRESETREQ_Pos 2 00443 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 00445 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 00446 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 00448 #define SCB_AIRCR_VECTRESET_Pos 0 00449 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) 00451 /* SCB System Control Register Definitions */ 00452 #define SCB_SCR_SEVONPEND_Pos 4 00453 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 00455 #define SCB_SCR_SLEEPDEEP_Pos 2 00456 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 00458 #define SCB_SCR_SLEEPONEXIT_Pos 1 00459 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 00461 /* SCB Configuration Control Register Definitions */ 00462 #define SCB_CCR_STKALIGN_Pos 9 00463 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 00465 #define SCB_CCR_BFHFNMIGN_Pos 8 00466 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 00468 #define SCB_CCR_DIV_0_TRP_Pos 4 00469 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 00471 #define SCB_CCR_UNALIGN_TRP_Pos 3 00472 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 00474 #define SCB_CCR_USERSETMPEND_Pos 1 00475 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 00477 #define SCB_CCR_NONBASETHRDENA_Pos 0 00478 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) 00480 /* SCB System Handler Control and State Register Definitions */ 00481 #define SCB_SHCSR_USGFAULTENA_Pos 18 00482 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 00484 #define SCB_SHCSR_BUSFAULTENA_Pos 17 00485 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 00487 #define SCB_SHCSR_MEMFAULTENA_Pos 16 00488 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 00490 #define SCB_SHCSR_SVCALLPENDED_Pos 15 00491 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 00493 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 00494 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 00496 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 00497 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 00499 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 00500 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 00502 #define SCB_SHCSR_SYSTICKACT_Pos 11 00503 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 00505 #define SCB_SHCSR_PENDSVACT_Pos 10 00506 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 00508 #define SCB_SHCSR_MONITORACT_Pos 8 00509 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 00511 #define SCB_SHCSR_SVCALLACT_Pos 7 00512 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 00514 #define SCB_SHCSR_USGFAULTACT_Pos 3 00515 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 00517 #define SCB_SHCSR_BUSFAULTACT_Pos 1 00518 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 00520 #define SCB_SHCSR_MEMFAULTACT_Pos 0 00521 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) 00523 /* SCB Configurable Fault Status Registers Definitions */ 00524 #define SCB_CFSR_USGFAULTSR_Pos 16 00525 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 00527 #define SCB_CFSR_BUSFAULTSR_Pos 8 00528 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 00530 #define SCB_CFSR_MEMFAULTSR_Pos 0 00531 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) 00533 /* SCB Hard Fault Status Registers Definitions */ 00534 #define SCB_HFSR_DEBUGEVT_Pos 31 00535 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 00537 #define SCB_HFSR_FORCED_Pos 30 00538 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 00540 #define SCB_HFSR_VECTTBL_Pos 1 00541 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 00543 /* SCB Debug Fault Status Register Definitions */ 00544 #define SCB_DFSR_EXTERNAL_Pos 4 00545 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 00547 #define SCB_DFSR_VCATCH_Pos 3 00548 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 00550 #define SCB_DFSR_DWTTRAP_Pos 2 00551 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 00553 #define SCB_DFSR_BKPT_Pos 1 00554 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 00556 #define SCB_DFSR_HALTED_Pos 0 00557 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) 00559 00570 typedef struct 00571 { 00572 uint32_t RESERVED0[1]; 00573 __I uint32_t ICTR; 00574 __IO uint32_t ACTLR; 00575 } SCnSCB_Type; 00576 00577 /* Interrupt Controller Type Register Definitions */ 00578 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 00579 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) 00581 /* Auxiliary Control Register Definitions */ 00582 #define SCnSCB_ACTLR_DISOOFP_Pos 9 00583 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) 00585 #define SCnSCB_ACTLR_DISFPCA_Pos 8 00586 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) 00588 #define SCnSCB_ACTLR_DISFOLD_Pos 2 00589 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 00591 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 00592 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) 00594 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 00595 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) 00597 00608 typedef struct 00609 { 00610 __IO uint32_t CTRL; 00611 __IO uint32_t LOAD; 00612 __IO uint32_t VAL; 00613 __I uint32_t CALIB; 00614 } SysTick_Type; 00615 00616 /* SysTick Control / Status Register Definitions */ 00617 #define SysTick_CTRL_COUNTFLAG_Pos 16 00618 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 00620 #define SysTick_CTRL_CLKSOURCE_Pos 2 00621 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 00623 #define SysTick_CTRL_TICKINT_Pos 1 00624 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 00626 #define SysTick_CTRL_ENABLE_Pos 0 00627 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) 00629 /* SysTick Reload Register Definitions */ 00630 #define SysTick_LOAD_RELOAD_Pos 0 00631 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) 00633 /* SysTick Current Register Definitions */ 00634 #define SysTick_VAL_CURRENT_Pos 0 00635 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) 00637 /* SysTick Calibration Register Definitions */ 00638 #define SysTick_CALIB_NOREF_Pos 31 00639 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 00641 #define SysTick_CALIB_SKEW_Pos 30 00642 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 00644 #define SysTick_CALIB_TENMS_Pos 0 00645 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) 00647 00658 typedef struct 00659 { 00660 __O union 00661 { 00662 __O uint8_t u8; 00663 __O uint16_t u16; 00664 __O uint32_t u32; 00665 } PORT [32]; 00666 uint32_t RESERVED0[864]; 00667 __IO uint32_t TER; 00668 uint32_t RESERVED1[15]; 00669 __IO uint32_t TPR; 00670 uint32_t RESERVED2[15]; 00671 __IO uint32_t TCR; 00672 uint32_t RESERVED3[29]; 00673 __O uint32_t IWR; 00674 __I uint32_t IRR; 00675 __IO uint32_t IMCR; 00676 uint32_t RESERVED4[43]; 00677 __O uint32_t LAR; 00678 __I uint32_t LSR; 00679 uint32_t RESERVED5[6]; 00680 __I uint32_t PID4; 00681 __I uint32_t PID5; 00682 __I uint32_t PID6; 00683 __I uint32_t PID7; 00684 __I uint32_t PID0; 00685 __I uint32_t PID1; 00686 __I uint32_t PID2; 00687 __I uint32_t PID3; 00688 __I uint32_t CID0; 00689 __I uint32_t CID1; 00690 __I uint32_t CID2; 00691 __I uint32_t CID3; 00692 } ITM_Type; 00693 00694 /* ITM Trace Privilege Register Definitions */ 00695 #define ITM_TPR_PRIVMASK_Pos 0 00696 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) 00698 /* ITM Trace Control Register Definitions */ 00699 #define ITM_TCR_BUSY_Pos 23 00700 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 00702 #define ITM_TCR_TraceBusID_Pos 16 00703 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 00705 #define ITM_TCR_GTSFREQ_Pos 10 00706 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 00708 #define ITM_TCR_TSPrescale_Pos 8 00709 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 00711 #define ITM_TCR_SWOENA_Pos 4 00712 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 00714 #define ITM_TCR_DWTENA_Pos 3 00715 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) 00717 #define ITM_TCR_SYNCENA_Pos 2 00718 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 00720 #define ITM_TCR_TSENA_Pos 1 00721 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 00723 #define ITM_TCR_ITMENA_Pos 0 00724 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) 00726 /* ITM Integration Write Register Definitions */ 00727 #define ITM_IWR_ATVALIDM_Pos 0 00728 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) 00730 /* ITM Integration Read Register Definitions */ 00731 #define ITM_IRR_ATREADYM_Pos 0 00732 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) 00734 /* ITM Integration Mode Control Register Definitions */ 00735 #define ITM_IMCR_INTEGRATION_Pos 0 00736 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) 00738 /* ITM Lock Status Register Definitions */ 00739 #define ITM_LSR_ByteAcc_Pos 2 00740 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) 00742 #define ITM_LSR_Access_Pos 1 00743 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) 00745 #define ITM_LSR_Present_Pos 0 00746 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) 00748 /* end of group CMSIS_ITM */ 00749 00750 00759 typedef struct 00760 { 00761 __IO uint32_t CTRL; 00762 __IO uint32_t CYCCNT; 00763 __IO uint32_t CPICNT; 00764 __IO uint32_t EXCCNT; 00765 __IO uint32_t SLEEPCNT; 00766 __IO uint32_t LSUCNT; 00767 __IO uint32_t FOLDCNT; 00768 __I uint32_t PCSR; 00769 __IO uint32_t COMP0; 00770 __IO uint32_t MASK0; 00771 __IO uint32_t FUNCTION0; 00772 uint32_t RESERVED0[1]; 00773 __IO uint32_t COMP1; 00774 __IO uint32_t MASK1; 00775 __IO uint32_t FUNCTION1; 00776 uint32_t RESERVED1[1]; 00777 __IO uint32_t COMP2; 00778 __IO uint32_t MASK2; 00779 __IO uint32_t FUNCTION2; 00780 uint32_t RESERVED2[1]; 00781 __IO uint32_t COMP3; 00782 __IO uint32_t MASK3; 00783 __IO uint32_t FUNCTION3; 00784 } DWT_Type; 00785 00786 /* DWT Control Register Definitions */ 00787 #define DWT_CTRL_NUMCOMP_Pos 28 00788 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 00790 #define DWT_CTRL_NOTRCPKT_Pos 27 00791 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 00793 #define DWT_CTRL_NOEXTTRIG_Pos 26 00794 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 00796 #define DWT_CTRL_NOCYCCNT_Pos 25 00797 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 00799 #define DWT_CTRL_NOPRFCNT_Pos 24 00800 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 00802 #define DWT_CTRL_CYCEVTENA_Pos 22 00803 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 00805 #define DWT_CTRL_FOLDEVTENA_Pos 21 00806 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 00808 #define DWT_CTRL_LSUEVTENA_Pos 20 00809 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 00811 #define DWT_CTRL_SLEEPEVTENA_Pos 19 00812 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 00814 #define DWT_CTRL_EXCEVTENA_Pos 18 00815 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 00817 #define DWT_CTRL_CPIEVTENA_Pos 17 00818 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 00820 #define DWT_CTRL_EXCTRCENA_Pos 16 00821 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 00823 #define DWT_CTRL_PCSAMPLENA_Pos 12 00824 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 00826 #define DWT_CTRL_SYNCTAP_Pos 10 00827 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 00829 #define DWT_CTRL_CYCTAP_Pos 9 00830 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 00832 #define DWT_CTRL_POSTINIT_Pos 5 00833 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 00835 #define DWT_CTRL_POSTPRESET_Pos 1 00836 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 00838 #define DWT_CTRL_CYCCNTENA_Pos 0 00839 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) 00841 /* DWT CPI Count Register Definitions */ 00842 #define DWT_CPICNT_CPICNT_Pos 0 00843 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) 00845 /* DWT Exception Overhead Count Register Definitions */ 00846 #define DWT_EXCCNT_EXCCNT_Pos 0 00847 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) 00849 /* DWT Sleep Count Register Definitions */ 00850 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 00851 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) 00853 /* DWT LSU Count Register Definitions */ 00854 #define DWT_LSUCNT_LSUCNT_Pos 0 00855 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) 00857 /* DWT Folded-instruction Count Register Definitions */ 00858 #define DWT_FOLDCNT_FOLDCNT_Pos 0 00859 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) 00861 /* DWT Comparator Mask Register Definitions */ 00862 #define DWT_MASK_MASK_Pos 0 00863 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) 00865 /* DWT Comparator Function Register Definitions */ 00866 #define DWT_FUNCTION_MATCHED_Pos 24 00867 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 00869 #define DWT_FUNCTION_DATAVADDR1_Pos 16 00870 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 00872 #define DWT_FUNCTION_DATAVADDR0_Pos 12 00873 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 00875 #define DWT_FUNCTION_DATAVSIZE_Pos 10 00876 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 00878 #define DWT_FUNCTION_LNK1ENA_Pos 9 00879 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 00881 #define DWT_FUNCTION_DATAVMATCH_Pos 8 00882 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 00884 #define DWT_FUNCTION_CYCMATCH_Pos 7 00885 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 00887 #define DWT_FUNCTION_EMITRANGE_Pos 5 00888 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 00890 #define DWT_FUNCTION_FUNCTION_Pos 0 00891 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) 00893 /* end of group CMSIS_DWT */ 00894 00895 00904 typedef struct 00905 { 00906 __IO uint32_t SSPSR; 00907 __IO uint32_t CSPSR; 00908 uint32_t RESERVED0[2]; 00909 __IO uint32_t ACPR; 00910 uint32_t RESERVED1[55]; 00911 __IO uint32_t SPPR; 00912 uint32_t RESERVED2[131]; 00913 __I uint32_t FFSR; 00914 __IO uint32_t FFCR; 00915 __I uint32_t FSCR; 00916 uint32_t RESERVED3[759]; 00917 __I uint32_t TRIGGER; 00918 __I uint32_t FIFO0; 00919 __I uint32_t ITATBCTR2; 00920 uint32_t RESERVED4[1]; 00921 __I uint32_t ITATBCTR0; 00922 __I uint32_t FIFO1; 00923 __IO uint32_t ITCTRL; 00924 uint32_t RESERVED5[39]; 00925 __IO uint32_t CLAIMSET; 00926 __IO uint32_t CLAIMCLR; 00927 uint32_t RESERVED7[8]; 00928 __I uint32_t DEVID; 00929 __I uint32_t DEVTYPE; 00930 } TPI_Type; 00931 00932 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00933 #define TPI_ACPR_PRESCALER_Pos 0 00934 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) 00936 /* TPI Selected Pin Protocol Register Definitions */ 00937 #define TPI_SPPR_TXMODE_Pos 0 00938 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) 00940 /* TPI Formatter and Flush Status Register Definitions */ 00941 #define TPI_FFSR_FtNonStop_Pos 3 00942 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 00944 #define TPI_FFSR_TCPresent_Pos 2 00945 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 00947 #define TPI_FFSR_FtStopped_Pos 1 00948 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 00950 #define TPI_FFSR_FlInProg_Pos 0 00951 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) 00953 /* TPI Formatter and Flush Control Register Definitions */ 00954 #define TPI_FFCR_TrigIn_Pos 8 00955 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 00957 #define TPI_FFCR_EnFCont_Pos 1 00958 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 00960 /* TPI TRIGGER Register Definitions */ 00961 #define TPI_TRIGGER_TRIGGER_Pos 0 00962 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) 00964 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00965 #define TPI_FIFO0_ITM_ATVALID_Pos 29 00966 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 00968 #define TPI_FIFO0_ITM_bytecount_Pos 27 00969 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 00971 #define TPI_FIFO0_ETM_ATVALID_Pos 26 00972 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 00974 #define TPI_FIFO0_ETM_bytecount_Pos 24 00975 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 00977 #define TPI_FIFO0_ETM2_Pos 16 00978 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 00980 #define TPI_FIFO0_ETM1_Pos 8 00981 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 00983 #define TPI_FIFO0_ETM0_Pos 0 00984 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) 00986 /* TPI ITATBCTR2 Register Definitions */ 00987 #define TPI_ITATBCTR2_ATREADY_Pos 0 00988 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) 00990 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00991 #define TPI_FIFO1_ITM_ATVALID_Pos 29 00992 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 00994 #define TPI_FIFO1_ITM_bytecount_Pos 27 00995 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 00997 #define TPI_FIFO1_ETM_ATVALID_Pos 26 00998 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 01000 #define TPI_FIFO1_ETM_bytecount_Pos 24 01001 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 01003 #define TPI_FIFO1_ITM2_Pos 16 01004 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 01006 #define TPI_FIFO1_ITM1_Pos 8 01007 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 01009 #define TPI_FIFO1_ITM0_Pos 0 01010 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) 01012 /* TPI ITATBCTR0 Register Definitions */ 01013 #define TPI_ITATBCTR0_ATREADY_Pos 0 01014 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) 01016 /* TPI Integration Mode Control Register Definitions */ 01017 #define TPI_ITCTRL_Mode_Pos 0 01018 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) 01020 /* TPI DEVID Register Definitions */ 01021 #define TPI_DEVID_NRZVALID_Pos 11 01022 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 01024 #define TPI_DEVID_MANCVALID_Pos 10 01025 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 01027 #define TPI_DEVID_PTINVALID_Pos 9 01028 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 01030 #define TPI_DEVID_MinBufSz_Pos 6 01031 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 01033 #define TPI_DEVID_AsynClkIn_Pos 5 01034 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 01036 #define TPI_DEVID_NrTraceInput_Pos 0 01037 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) 01039 /* TPI DEVTYPE Register Definitions */ 01040 #define TPI_DEVTYPE_SubType_Pos 0 01041 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) 01043 #define TPI_DEVTYPE_MajorType_Pos 4 01044 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 01046 /* end of group CMSIS_TPI */ 01047 01048 01049 #if (__MPU_PRESENT == 1) 01050 01058 typedef struct 01059 { 01060 __I uint32_t TYPE; 01061 __IO uint32_t CTRL; 01062 __IO uint32_t RNR; 01063 __IO uint32_t RBAR; 01064 __IO uint32_t RASR; 01065 __IO uint32_t RBAR_A1; 01066 __IO uint32_t RASR_A1; 01067 __IO uint32_t RBAR_A2; 01068 __IO uint32_t RASR_A2; 01069 __IO uint32_t RBAR_A3; 01070 __IO uint32_t RASR_A3; 01071 } MPU_Type; 01072 01073 /* MPU Type Register */ 01074 #define MPU_TYPE_IREGION_Pos 16 01075 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 01077 #define MPU_TYPE_DREGION_Pos 8 01078 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 01080 #define MPU_TYPE_SEPARATE_Pos 0 01081 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) 01083 /* MPU Control Register */ 01084 #define MPU_CTRL_PRIVDEFENA_Pos 2 01085 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 01087 #define MPU_CTRL_HFNMIENA_Pos 1 01088 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 01090 #define MPU_CTRL_ENABLE_Pos 0 01091 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) 01093 /* MPU Region Number Register */ 01094 #define MPU_RNR_REGION_Pos 0 01095 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) 01097 /* MPU Region Base Address Register */ 01098 #define MPU_RBAR_ADDR_Pos 5 01099 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 01101 #define MPU_RBAR_VALID_Pos 4 01102 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 01104 #define MPU_RBAR_REGION_Pos 0 01105 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) 01107 /* MPU Region Attribute and Size Register */ 01108 #define MPU_RASR_ATTRS_Pos 16 01109 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 01111 #define MPU_RASR_XN_Pos 28 01112 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) 01114 #define MPU_RASR_AP_Pos 24 01115 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) 01117 #define MPU_RASR_TEX_Pos 19 01118 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) 01120 #define MPU_RASR_S_Pos 18 01121 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) 01123 #define MPU_RASR_C_Pos 17 01124 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) 01126 #define MPU_RASR_B_Pos 16 01127 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) 01129 #define MPU_RASR_SRD_Pos 8 01130 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 01132 #define MPU_RASR_SIZE_Pos 1 01133 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 01135 #define MPU_RASR_ENABLE_Pos 0 01136 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) 01138 01139 #endif 01140 01141 01142 #if (__FPU_PRESENT == 1) 01143 01151 typedef struct 01152 { 01153 uint32_t RESERVED0[1]; 01154 __IO uint32_t FPCCR; 01155 __IO uint32_t FPCAR; 01156 __IO uint32_t FPDSCR; 01157 __I uint32_t MVFR0; 01158 __I uint32_t MVFR1; 01159 } FPU_Type; 01160 01161 /* Floating-Point Context Control Register */ 01162 #define FPU_FPCCR_ASPEN_Pos 31 01163 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) 01165 #define FPU_FPCCR_LSPEN_Pos 30 01166 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) 01168 #define FPU_FPCCR_MONRDY_Pos 8 01169 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) 01171 #define FPU_FPCCR_BFRDY_Pos 6 01172 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) 01174 #define FPU_FPCCR_MMRDY_Pos 5 01175 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) 01177 #define FPU_FPCCR_HFRDY_Pos 4 01178 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) 01180 #define FPU_FPCCR_THREAD_Pos 3 01181 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) 01183 #define FPU_FPCCR_USER_Pos 1 01184 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) 01186 #define FPU_FPCCR_LSPACT_Pos 0 01187 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) 01189 /* Floating-Point Context Address Register */ 01190 #define FPU_FPCAR_ADDRESS_Pos 3 01191 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) 01193 /* Floating-Point Default Status Control Register */ 01194 #define FPU_FPDSCR_AHP_Pos 26 01195 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) 01197 #define FPU_FPDSCR_DN_Pos 25 01198 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) 01200 #define FPU_FPDSCR_FZ_Pos 24 01201 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) 01203 #define FPU_FPDSCR_RMode_Pos 22 01204 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) 01206 /* Media and FP Feature Register 0 */ 01207 #define FPU_MVFR0_FP_rounding_modes_Pos 28 01208 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) 01210 #define FPU_MVFR0_Short_vectors_Pos 24 01211 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) 01213 #define FPU_MVFR0_Square_root_Pos 20 01214 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) 01216 #define FPU_MVFR0_Divide_Pos 16 01217 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) 01219 #define FPU_MVFR0_FP_excep_trapping_Pos 12 01220 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) 01222 #define FPU_MVFR0_Double_precision_Pos 8 01223 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) 01225 #define FPU_MVFR0_Single_precision_Pos 4 01226 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) 01228 #define FPU_MVFR0_A_SIMD_registers_Pos 0 01229 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) 01231 /* Media and FP Feature Register 1 */ 01232 #define FPU_MVFR1_FP_fused_MAC_Pos 28 01233 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) 01235 #define FPU_MVFR1_FP_HPFP_Pos 24 01236 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) 01238 #define FPU_MVFR1_D_NaN_mode_Pos 4 01239 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) 01241 #define FPU_MVFR1_FtZ_mode_Pos 0 01242 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) 01244 01245 #endif 01246 01247 01256 typedef struct 01257 { 01258 __IO uint32_t DHCSR; 01259 __O uint32_t DCRSR; 01260 __IO uint32_t DCRDR; 01261 __IO uint32_t DEMCR; 01262 } CoreDebug_Type; 01263 01264 /* Debug Halting Control and Status Register */ 01265 #define CoreDebug_DHCSR_DBGKEY_Pos 16 01266 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 01268 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 01269 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 01271 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 01272 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 01274 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 01275 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 01277 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 01278 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 01280 #define CoreDebug_DHCSR_S_HALT_Pos 17 01281 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 01283 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 01284 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 01286 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 01287 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 01289 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 01290 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 01292 #define CoreDebug_DHCSR_C_STEP_Pos 2 01293 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 01295 #define CoreDebug_DHCSR_C_HALT_Pos 1 01296 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 01298 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 01299 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) 01301 /* Debug Core Register Selector Register */ 01302 #define CoreDebug_DCRSR_REGWnR_Pos 16 01303 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 01305 #define CoreDebug_DCRSR_REGSEL_Pos 0 01306 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) 01308 /* Debug Exception and Monitor Control Register */ 01309 #define CoreDebug_DEMCR_TRCENA_Pos 24 01310 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 01312 #define CoreDebug_DEMCR_MON_REQ_Pos 19 01313 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 01315 #define CoreDebug_DEMCR_MON_STEP_Pos 18 01316 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 01318 #define CoreDebug_DEMCR_MON_PEND_Pos 17 01319 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 01321 #define CoreDebug_DEMCR_MON_EN_Pos 16 01322 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 01324 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 01325 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 01327 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 01328 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 01330 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 01331 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 01333 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 01334 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 01336 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 01337 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 01339 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 01340 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 01342 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 01343 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 01345 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 01346 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) 01348 01357 /* Memory mapping of Cortex-M4 Hardware */ 01358 #define SCS_BASE (0xE000E000UL) 01359 #define ITM_BASE (0xE0000000UL) 01360 #define DWT_BASE (0xE0001000UL) 01361 #define TPI_BASE (0xE0040000UL) 01362 #define CoreDebug_BASE (0xE000EDF0UL) 01363 #define SysTick_BASE (SCS_BASE + 0x0010UL) 01364 #define NVIC_BASE (SCS_BASE + 0x0100UL) 01365 #define SCB_BASE (SCS_BASE + 0x0D00UL) 01367 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 01368 #define SCB ((SCB_Type *) SCB_BASE ) 01369 #define SysTick ((SysTick_Type *) SysTick_BASE ) 01370 #define NVIC ((NVIC_Type *) NVIC_BASE ) 01371 #define ITM ((ITM_Type *) ITM_BASE ) 01372 #define DWT ((DWT_Type *) DWT_BASE ) 01373 #define TPI ((TPI_Type *) TPI_BASE ) 01374 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 01376 #if (__MPU_PRESENT == 1) 01377 #define MPU_BASE (SCS_BASE + 0x0D90UL) 01378 #define MPU ((MPU_Type *) MPU_BASE ) 01379 #endif 01380 01381 #if (__FPU_PRESENT == 1) 01382 #define FPU_BASE (SCS_BASE + 0x0F30UL) 01383 #define FPU ((FPU_Type *) FPU_BASE ) 01384 #endif 01385 01390 /******************************************************************************* 01391 * Hardware Abstraction Layer 01392 Core Function Interface contains: 01393 - Core NVIC Functions 01394 - Core SysTick Functions 01395 - Core Debug Functions 01396 - Core Register Access Functions 01397 ******************************************************************************/ 01403 /* ########################## NVIC functions #################################### */ 01420 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01421 { 01422 uint32_t reg_value; 01423 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 01424 01425 reg_value = SCB->AIRCR; /* read old register configuration */ 01426 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 01427 reg_value = (reg_value | 01428 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01429 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 01430 SCB->AIRCR = reg_value; 01431 } 01432 01433 01440 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01441 { 01442 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 01443 } 01444 01445 01452 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01453 { 01454 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ 01455 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ 01456 } 01457 01458 01465 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01466 { 01467 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 01468 } 01469 01470 01481 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01482 { 01483 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01484 } 01485 01486 01493 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01494 { 01495 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 01496 } 01497 01498 01505 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01506 { 01507 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 01508 } 01509 01510 01520 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01521 { 01522 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01523 } 01524 #define NVIC_GetEnableIRQ NVIC_GetActive 01525 01526 01536 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01537 { 01538 if(IRQn < 0) { 01539 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 01540 else { 01541 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01542 } 01543 01544 01556 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01557 { 01558 01559 if(IRQn < 0) { 01560 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 01561 else { 01562 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01563 } 01564 01565 01578 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01579 { 01580 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01581 uint32_t PreemptPriorityBits; 01582 uint32_t SubPriorityBits; 01583 01584 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01585 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01586 01587 return ( 01588 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01589 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01590 ); 01591 } 01592 01593 01606 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01607 { 01608 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01609 uint32_t PreemptPriorityBits; 01610 uint32_t SubPriorityBits; 01611 01612 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01613 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01614 01615 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01616 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01617 } 01618 01619 01624 __STATIC_INLINE void NVIC_SystemReset(void) 01625 { 01626 __DSB(); /* Ensure all outstanding memory accesses included 01627 buffered write are completed before reset */ 01628 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01629 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01630 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 01631 __DSB(); /* Ensure completion of memory access */ 01632 while(1); /* wait until reset */ 01633 } 01634 01639 /* ################################## SysTick function ############################################ */ 01646 #if (__Vendor_SysTickConfig == 0) 01647 01663 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01664 { 01665 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 01666 01667 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 01668 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 01669 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 01670 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01671 SysTick_CTRL_TICKINT_Msk | 01672 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01673 return (0); /* Function successful */ 01674 } 01675 01676 #endif 01677 01682 /* ##################################### Debug In/Output function ########################################### */ 01689 extern volatile int32_t ITM_RxBuffer; 01690 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 01703 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01704 { 01705 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 01706 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 01707 { 01708 while (ITM->PORT[0].u32 == 0); 01709 ITM->PORT[0].u8 = (uint8_t) ch; 01710 } 01711 return (ch); 01712 } 01713 01714 01722 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 01723 int32_t ch = -1; /* no character available */ 01724 01725 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 01726 ch = ITM_RxBuffer; 01727 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01728 } 01729 01730 return (ch); 01731 } 01732 01733 01741 __STATIC_INLINE int32_t ITM_CheckChar (void) { 01742 01743 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 01744 return (0); /* no character available */ 01745 } else { 01746 return (1); /* character available */ 01747 } 01748 } 01749 01752 #endif /* __CORE_CM4_H_DEPENDANT */ 01753 01754 #endif /* __CMSIS_GENERIC */ 01755 01756 #ifdef __cplusplus 01757 } 01758 #endif