Structure type to access the Data Watchpoint and Trace Register (DWT). More...
#include <core_cm3.h>
Data Fields | |
__IO uint32_t | CTRL |
__IO uint32_t | CYCCNT |
__IO uint32_t | CPICNT |
__IO uint32_t | EXCCNT |
__IO uint32_t | SLEEPCNT |
__IO uint32_t | LSUCNT |
__IO uint32_t | FOLDCNT |
__I uint32_t | PCSR |
__IO uint32_t | COMP0 |
__IO uint32_t | MASK0 |
__IO uint32_t | FUNCTION0 |
uint32_t | RESERVED0 [1] |
__IO uint32_t | COMP1 |
__IO uint32_t | MASK1 |
__IO uint32_t | FUNCTION1 |
uint32_t | RESERVED1 [1] |
__IO uint32_t | COMP2 |
__IO uint32_t | MASK2 |
__IO uint32_t | FUNCTION2 |
uint32_t | RESERVED2 [1] |
__IO uint32_t | COMP3 |
__IO uint32_t | MASK3 |
__IO uint32_t | FUNCTION3 |
Structure type to access the Data Watchpoint and Trace Register (DWT).
__IO uint32_t DWT_Type::CTRL |
Offset: 0x000 (R/W) Control Register
__IO uint32_t DWT_Type::CYCCNT |
Offset: 0x004 (R/W) Cycle Count Register
__IO uint32_t DWT_Type::CPICNT |
Offset: 0x008 (R/W) CPI Count Register
__IO uint32_t DWT_Type::EXCCNT |
Offset: 0x00C (R/W) Exception Overhead Count Register
Offset: 0x010 (R/W) Sleep Count Register
__IO uint32_t DWT_Type::LSUCNT |
Offset: 0x014 (R/W) LSU Count Register
Offset: 0x018 (R/W) Folded-instruction Count Register
Offset: 0x01C (R/ ) Program Counter Sample Register
__IO uint32_t DWT_Type::COMP0 |
Offset: 0x020 (R/W) Comparator Register 0
__IO uint32_t DWT_Type::MASK0 |
Offset: 0x024 (R/W) Mask Register 0
Offset: 0x028 (R/W) Function Register 0
__IO uint32_t DWT_Type::COMP1 |
Offset: 0x030 (R/W) Comparator Register 1
__IO uint32_t DWT_Type::MASK1 |
Offset: 0x034 (R/W) Mask Register 1
Offset: 0x038 (R/W) Function Register 1
__IO uint32_t DWT_Type::COMP2 |
Offset: 0x040 (R/W) Comparator Register 2
__IO uint32_t DWT_Type::MASK2 |
Offset: 0x044 (R/W) Mask Register 2
Offset: 0x048 (R/W) Function Register 2
__IO uint32_t DWT_Type::COMP3 |
Offset: 0x050 (R/W) Comparator Register 3
__IO uint32_t DWT_Type::MASK3 |
Offset: 0x054 (R/W) Mask Register 3
Offset: 0x058 (R/W) Function Register 3