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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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TIM. More...
#include <stm32f10x.h>
Data Fields | |
| __IO uint16_t | CR1 |
| uint16_t | RESERVED0 |
| __IO uint16_t | CR2 |
| uint16_t | RESERVED1 |
| __IO uint16_t | SMCR |
| uint16_t | RESERVED2 |
| __IO uint16_t | DIER |
| uint16_t | RESERVED3 |
| __IO uint16_t | SR |
| uint16_t | RESERVED4 |
| __IO uint16_t | EGR |
| uint16_t | RESERVED5 |
| __IO uint16_t | CCMR1 |
| uint16_t | RESERVED6 |
| __IO uint16_t | CCMR2 |
| uint16_t | RESERVED7 |
| __IO uint16_t | CCER |
| uint16_t | RESERVED8 |
| __IO uint16_t | CNT |
| uint16_t | RESERVED9 |
| __IO uint16_t | PSC |
| uint16_t | RESERVED10 |
| __IO uint16_t | ARR |
| uint16_t | RESERVED11 |
| __IO uint16_t | RCR |
| uint16_t | RESERVED12 |
| __IO uint16_t | CCR1 |
| uint16_t | RESERVED13 |
| __IO uint16_t | CCR2 |
| uint16_t | RESERVED14 |
| __IO uint16_t | CCR3 |
| uint16_t | RESERVED15 |
| __IO uint16_t | CCR4 |
| uint16_t | RESERVED16 |
| __IO uint16_t | BDTR |
| uint16_t | RESERVED17 |
| __IO uint16_t | DCR |
| uint16_t | RESERVED18 |
| __IO uint16_t | DMAR |
| uint16_t | RESERVED19 |
| __IO uint32_t | CNT |
| __IO uint32_t | ARR |
| __IO uint32_t | CCR1 |
| __IO uint32_t | CCR2 |
| __IO uint32_t | CCR3 |
| __IO uint32_t | CCR4 |
| __IO uint16_t | OR |
| uint32_t | RESERVED12 |
| uint32_t | RESERVED17 |
| uint16_t | RESERVED20 |
TIM.
| __IO uint16_t TIM_TypeDef::CR1 |
TIM control register 1, Address offset: 0x00
Referenced by TIM_ARRPreloadConfig(), TIM_Cmd(), TIM_CounterModeConfig(), TIM_SelectOnePulseMode(), TIM_SetClockDivision(), TIM_TimeBaseInit(), TIM_UpdateDisableConfig(), and TIM_UpdateRequestConfig().
Reserved, 0x02
| __IO uint16_t TIM_TypeDef::CR2 |
TIM control register 2, Address offset: 0x04
Referenced by TIM_CCPreloadControl(), TIM_OC1Init(), TIM_OC2Init(), TIM_OC3Init(), TIM_OC4Init(), TIM_SelectCCDMA(), TIM_SelectCOM(), TIM_SelectHallSensor(), and TIM_SelectOutputTrigger().
Reserved, 0x06
TIM slave mode control register, Address offset: 0x08
Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_ETRClockMode2Config(), TIM_ETRConfig(), TIM_InternalClockConfig(), TIM_ITRxExternalClockConfig(), TIM_SelectInputTrigger(), TIM_SelectMasterSlaveMode(), TIM_SelectSlaveMode(), and TIM_TIxExternalClockConfig().
Reserved, 0x0A
TIM DMA/interrupt enable register, Address offset: 0x0C
Referenced by TIM_DMACmd(), TIM_GetITStatus(), and TIM_ITConfig().
Reserved, 0x0E
| __IO uint16_t TIM_TypeDef::SR |
TIM status register, Address offset: 0x10
Referenced by TIM_ClearFlag(), TIM_ClearITPendingBit(), TIM_GetFlagStatus(), and TIM_GetITStatus().
Reserved, 0x12
| __IO uint16_t TIM_TypeDef::EGR |
TIM event generation register, Address offset: 0x14
Referenced by TIM_GenerateEvent(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().
Reserved, 0x16
TIM capture/compare mode register 1, Address offset: 0x18
Referenced by TIM_ClearOC1Ref(), TIM_ClearOC2Ref(), TIM_EncoderInterfaceConfig(), TIM_ForcedOC1Config(), TIM_ForcedOC2Config(), TIM_OC1FastConfig(), TIM_OC1Init(), TIM_OC1PreloadConfig(), TIM_OC2FastConfig(), TIM_OC2Init(), TIM_OC2PreloadConfig(), TIM_SetIC1Prescaler(), and TIM_SetIC2Prescaler().
Reserved, 0x1A
TIM capture/compare mode register 2, Address offset: 0x1C
Referenced by TIM_ClearOC3Ref(), TIM_ClearOC4Ref(), TIM_ForcedOC3Config(), TIM_ForcedOC4Config(), TIM_OC3FastConfig(), TIM_OC3Init(), TIM_OC3PreloadConfig(), TIM_OC4FastConfig(), TIM_OC4Init(), TIM_OC4PreloadConfig(), TIM_SetIC3Prescaler(), and TIM_SetIC4Prescaler().
Reserved, 0x1E
TIM capture/compare enable register, Address offset: 0x20
Referenced by TIM_CCxCmd(), TIM_CCxNCmd(), TIM_EncoderInterfaceConfig(), TIM_OC1Init(), TIM_OC1NPolarityConfig(), TIM_OC1PolarityConfig(), TIM_OC2Init(), TIM_OC2NPolarityConfig(), TIM_OC2PolarityConfig(), TIM_OC3Init(), TIM_OC3NPolarityConfig(), TIM_OC3PolarityConfig(), TIM_OC4Init(), TIM_OC4PolarityConfig(), and TIM_SelectOCxM().
Reserved, 0x22
| __IO uint32_t TIM_TypeDef::CNT |
TIM counter register, Address offset: 0x24
Referenced by TIM_GetCounter(), and TIM_SetCounter().
Reserved, 0x2A
| __IO uint16_t TIM_TypeDef::PSC |
TIM prescaler, Address offset: 0x28
Referenced by TIM_GetPrescaler(), TIM_PrescalerConfig(), and TIM_TimeBaseInit().
Reserved, 0x32
Reserved, 0x2A
| __IO uint32_t TIM_TypeDef::ARR |
TIM auto-reload register, Address offset: 0x2C
Referenced by TIM_SetAutoreload(), and TIM_TimeBaseInit().
Reserved, 0x46
| __IO uint16_t TIM_TypeDef::RCR |
TIM repetition counter register, Address offset: 0x30
Referenced by TIM_TimeBaseInit().
Reserved, 0x4A
TIM capture/compare register 1, Address offset: 0x34
Referenced by TIM_GetCapture1(), TIM_OC1Init(), and TIM_SetCompare1().
Reserved, 0x4E
TIM capture/compare register 2, Address offset: 0x38
Referenced by TIM_GetCapture2(), TIM_OC2Init(), and TIM_SetCompare2().
Reserved, 0x52
TIM capture/compare register 3, Address offset: 0x3C
Referenced by TIM_GetCapture3(), TIM_OC3Init(), and TIM_SetCompare3().
TIM capture/compare register 4, Address offset: 0x40
Referenced by TIM_GetCapture4(), TIM_OC4Init(), and TIM_SetCompare4().
TIM break and dead-time register, Address offset: 0x44
Referenced by TIM_BDTRConfig(), and TIM_CtrlPWMOutputs().
| __IO uint16_t TIM_TypeDef::DCR |
TIM DMA control register, Address offset: 0x48
Referenced by TIM_DMAConfig().
Reserved, 0x4A
TIM DMA address for full transfer, Address offset: 0x4C
Reserved, 0x4E
| __IO uint32_t TIM_TypeDef::CNT |
TIM counter register, Address offset: 0x24
| __IO uint32_t TIM_TypeDef::ARR |
TIM auto-reload register, Address offset: 0x2C
TIM capture/compare register 1, Address offset: 0x34
TIM capture/compare register 2, Address offset: 0x38
TIM capture/compare register 3, Address offset: 0x3C
TIM capture/compare register 4, Address offset: 0x40
| __IO uint16_t TIM_TypeDef::OR |
TIM option register, Address offset: 0x50
Reserved, 0x30
Reserved, 0x44
Reserved, 0x52