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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 00047 #include <cfg/arch.h> 00048 #include <cfg/clock.h> 00049 00050 #ifndef __STM32F4xx_H 00051 #define __STM32F4xx_H 00052 00053 #ifdef __cplusplus 00054 extern "C" { 00055 #endif /* __cplusplus */ 00056 00061 /* Uncomment the line below according to the target STM32 device used in your 00062 application 00063 */ 00064 00065 #if !defined (STM32F4XX) 00066 #define STM32F4XX 00067 #endif 00068 00069 /* Tip: To avoid modifying this file each time you need to switch between these 00070 devices, you can define the device in your toolchain compiler preprocessor. 00071 */ 00072 00073 #if !defined (STM32F4XX) 00074 #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)" 00075 #endif 00076 00077 #if !defined (USE_STDPERIPH_DRIVER) 00078 00083 /*#define USE_STDPERIPH_DRIVER*/ 00084 #endif /* USE_STDPERIPH_DRIVER */ 00085 00094 #if !defined (HSE_VALUE) 00095 #define HSE_VALUE ((uint32_t)25000000) 00096 #endif /* HSE_VALUE */ 00097 00102 #if !defined (HSE_STARTUP_TIMEOUT) 00103 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 00104 #endif /* HSE_STARTUP_TIMEOUT */ 00105 00106 #if !defined (HSI_VALUE) 00107 #define HSI_VALUE ((uint32_t)16000000) 00108 #endif /* HSI_VALUE */ 00109 00113 #define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) 00114 #define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x00) 00115 #define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) 00116 #define __STM32F4XX_STDPERIPH_VERSION_RC (0x00) 00117 #define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\ 00118 |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ 00119 |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ 00120 |(__STM32F4XX_STDPERIPH_VERSION_RC)) 00121 00133 #define __CM4_REV 0x0001 00134 #define __MPU_PRESENT 1 00135 #define __NVIC_PRIO_BITS 4 00136 #define __Vendor_SysTickConfig 0 00137 #define __FPU_PRESENT 1 00143 typedef enum IRQn 00144 { 00145 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 00146 NonMaskableInt_IRQn = -14, 00147 MemoryManagement_IRQn = -12, 00148 BusFault_IRQn = -11, 00149 UsageFault_IRQn = -10, 00150 SVCall_IRQn = -5, 00151 DebugMonitor_IRQn = -4, 00152 PendSV_IRQn = -2, 00153 SysTick_IRQn = -1, 00154 /****** STM32 specific Interrupt Numbers **********************************************************************/ 00155 WWDG_IRQn = 0, 00156 PVD_IRQn = 1, 00157 TAMP_STAMP_IRQn = 2, 00158 RTC_WKUP_IRQn = 3, 00159 FLASH_IRQn = 4, 00160 RCC_IRQn = 5, 00161 EXTI0_IRQn = 6, 00162 EXTI1_IRQn = 7, 00163 EXTI2_IRQn = 8, 00164 EXTI3_IRQn = 9, 00165 EXTI4_IRQn = 10, 00166 DMA1_Stream0_IRQn = 11, 00167 DMA1_Stream1_IRQn = 12, 00168 DMA1_Stream2_IRQn = 13, 00169 DMA1_Stream3_IRQn = 14, 00170 DMA1_Stream4_IRQn = 15, 00171 DMA1_Stream5_IRQn = 16, 00172 DMA1_Stream6_IRQn = 17, 00173 ADC_IRQn = 18, 00174 CAN1_TX_IRQn = 19, 00175 CAN1_RX0_IRQn = 20, 00176 CAN1_RX1_IRQn = 21, 00177 CAN1_SCE_IRQn = 22, 00178 EXTI9_5_IRQn = 23, 00179 TIM1_BRK_TIM9_IRQn = 24, 00180 TIM1_UP_TIM10_IRQn = 25, 00181 TIM1_TRG_COM_TIM11_IRQn = 26, 00182 TIM1_CC_IRQn = 27, 00183 TIM2_IRQn = 28, 00184 TIM3_IRQn = 29, 00185 TIM4_IRQn = 30, 00186 I2C1_EV_IRQn = 31, 00187 I2C1_ER_IRQn = 32, 00188 I2C2_EV_IRQn = 33, 00189 I2C2_ER_IRQn = 34, 00190 SPI1_IRQn = 35, 00191 SPI2_IRQn = 36, 00192 USART1_IRQn = 37, 00193 USART2_IRQn = 38, 00194 USART3_IRQn = 39, 00195 EXTI15_10_IRQn = 40, 00196 RTC_Alarm_IRQn = 41, 00197 OTG_FS_WKUP_IRQn = 42, 00198 TIM8_BRK_TIM12_IRQn = 43, 00199 TIM8_UP_TIM13_IRQn = 44, 00200 TIM8_TRG_COM_TIM14_IRQn = 45, 00201 TIM8_CC_IRQn = 46, 00202 DMA1_Stream7_IRQn = 47, 00203 FSMC_IRQn = 48, 00204 SDIO_IRQn = 49, 00205 TIM5_IRQn = 50, 00206 SPI3_IRQn = 51, 00207 UART4_IRQn = 52, 00208 UART5_IRQn = 53, 00209 TIM6_DAC_IRQn = 54, 00210 TIM7_IRQn = 55, 00211 DMA2_Stream0_IRQn = 56, 00212 DMA2_Stream1_IRQn = 57, 00213 DMA2_Stream2_IRQn = 58, 00214 DMA2_Stream3_IRQn = 59, 00215 DMA2_Stream4_IRQn = 60, 00216 ETH_IRQn = 61, 00217 ETH_WKUP_IRQn = 62, 00218 CAN2_TX_IRQn = 63, 00219 CAN2_RX0_IRQn = 64, 00220 CAN2_RX1_IRQn = 65, 00221 CAN2_SCE_IRQn = 66, 00222 OTG_FS_IRQn = 67, 00223 DMA2_Stream5_IRQn = 68, 00224 DMA2_Stream6_IRQn = 69, 00225 DMA2_Stream7_IRQn = 70, 00226 USART6_IRQn = 71, 00227 I2C3_EV_IRQn = 72, 00228 I2C3_ER_IRQn = 73, 00229 OTG_HS_EP1_OUT_IRQn = 74, 00230 OTG_HS_EP1_IN_IRQn = 75, 00231 OTG_HS_WKUP_IRQn = 76, 00232 OTG_HS_IRQn = 77, 00233 DCMI_IRQn = 78, 00234 CRYP_IRQn = 79, 00235 HASH_RNG_IRQn = 80, 00236 FPU_IRQn = 81 00237 } IRQn_Type; 00238 00243 #include <arch/cm3/core_cm4.h> /* Cortex-M4 processor and core peripherals */ 00244 #include <arch/cm3/stm/system_stm32f4xx.h> 00245 #include <stdint.h> 00246 00251 typedef int32_t s32; 00252 typedef int16_t s16; 00253 typedef int8_t s8; 00254 00255 typedef const int32_t sc32; 00256 typedef const int16_t sc16; 00257 typedef const int8_t sc8; 00259 typedef __IO int32_t vs32; 00260 typedef __IO int16_t vs16; 00261 typedef __IO int8_t vs8; 00262 00263 typedef __I int32_t vsc32; 00264 typedef __I int16_t vsc16; 00265 typedef __I int8_t vsc8; 00267 typedef uint32_t u32; 00268 typedef uint16_t u16; 00269 typedef uint8_t u8; 00270 00271 typedef const uint32_t uc32; 00272 typedef const uint16_t uc16; 00273 typedef const uint8_t uc8; 00275 typedef __IO uint32_t vu32; 00276 typedef __IO uint16_t vu16; 00277 typedef __IO uint8_t vu8; 00278 00279 typedef __I uint32_t vuc32; 00280 typedef __I uint16_t vuc16; 00281 typedef __I uint8_t vuc8; 00283 #ifndef __cplusplus 00284 typedef enum 00285 { 00286 FALSE = 0, TRUE = !FALSE 00287 } 00288 bool; 00289 #endif 00290 00291 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 00292 00293 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00294 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00295 00296 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00297 00310 typedef struct 00311 { 00312 __IO uint32_t SR; 00313 __IO uint32_t CR1; 00314 __IO uint32_t CR2; 00315 __IO uint32_t SMPR1; 00316 __IO uint32_t SMPR2; 00317 __IO uint32_t JOFR1; 00318 __IO uint32_t JOFR2; 00319 __IO uint32_t JOFR3; 00320 __IO uint32_t JOFR4; 00321 __IO uint32_t HTR; 00322 __IO uint32_t LTR; 00323 __IO uint32_t SQR1; 00324 __IO uint32_t SQR2; 00325 __IO uint32_t SQR3; 00326 __IO uint32_t JSQR; 00327 __IO uint32_t JDR1; 00328 __IO uint32_t JDR2; 00329 __IO uint32_t JDR3; 00330 __IO uint32_t JDR4; 00331 __IO uint32_t DR; 00332 } ADC_TypeDef; 00333 00334 typedef struct 00335 { 00336 __IO uint32_t CSR; 00337 __IO uint32_t CCR; 00338 __IO uint32_t CDR; 00340 } ADC_Common_TypeDef; 00341 00342 00347 typedef struct 00348 { 00349 __IO uint32_t TIR; 00350 __IO uint32_t TDTR; 00351 __IO uint32_t TDLR; 00352 __IO uint32_t TDHR; 00353 } CAN_TxMailBox_TypeDef; 00354 00359 typedef struct 00360 { 00361 __IO uint32_t RIR; 00362 __IO uint32_t RDTR; 00363 __IO uint32_t RDLR; 00364 __IO uint32_t RDHR; 00365 } CAN_FIFOMailBox_TypeDef; 00366 00371 typedef struct 00372 { 00373 __IO uint32_t FR1; 00374 __IO uint32_t FR2; 00375 } CAN_FilterRegister_TypeDef; 00376 00381 typedef struct 00382 { 00383 __IO uint32_t MCR; 00384 __IO uint32_t MSR; 00385 __IO uint32_t TSR; 00386 __IO uint32_t RF0R; 00387 __IO uint32_t RF1R; 00388 __IO uint32_t IER; 00389 __IO uint32_t ESR; 00390 __IO uint32_t BTR; 00391 uint32_t RESERVED0[88]; 00392 CAN_TxMailBox_TypeDef sTxMailBox[3]; 00393 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 00394 uint32_t RESERVED1[12]; 00395 __IO uint32_t FMR; 00396 __IO uint32_t FM1R; 00397 uint32_t RESERVED2; 00398 __IO uint32_t FS1R; 00399 uint32_t RESERVED3; 00400 __IO uint32_t FFA1R; 00401 uint32_t RESERVED4; 00402 __IO uint32_t FA1R; 00403 uint32_t RESERVED5[8]; 00404 CAN_FilterRegister_TypeDef sFilterRegister[28]; 00405 } CAN_TypeDef; 00406 00411 typedef struct 00412 { 00413 __IO uint32_t DR; 00414 __IO uint8_t IDR; 00415 uint8_t RESERVED0; 00416 uint16_t RESERVED1; 00417 __IO uint32_t CR; 00418 } CRC_TypeDef; 00419 00424 typedef struct 00425 { 00426 __IO uint32_t CR; 00427 __IO uint32_t SWTRIGR; 00428 __IO uint32_t DHR12R1; 00429 __IO uint32_t DHR12L1; 00430 __IO uint32_t DHR8R1; 00431 __IO uint32_t DHR12R2; 00432 __IO uint32_t DHR12L2; 00433 __IO uint32_t DHR8R2; 00434 __IO uint32_t DHR12RD; 00435 __IO uint32_t DHR12LD; 00436 __IO uint32_t DHR8RD; 00437 __IO uint32_t DOR1; 00438 __IO uint32_t DOR2; 00439 __IO uint32_t SR; 00440 } DAC_TypeDef; 00441 00446 typedef struct 00447 { 00448 __IO uint32_t IDCODE; 00449 __IO uint32_t CR; 00450 __IO uint32_t APB1FZ; 00451 __IO uint32_t APB2FZ; 00452 }DBGMCU_TypeDef; 00453 00458 typedef struct 00459 { 00460 __IO uint32_t CR; 00461 __IO uint32_t SR; 00462 __IO uint32_t RISR; 00463 __IO uint32_t IER; 00464 __IO uint32_t MISR; 00465 __IO uint32_t ICR; 00466 __IO uint32_t ESCR; 00467 __IO uint32_t ESUR; 00468 __IO uint32_t CWSTRTR; 00469 __IO uint32_t CWSIZER; 00470 __IO uint32_t DR; 00471 } DCMI_TypeDef; 00472 00477 typedef struct 00478 { 00479 __IO uint32_t CR; 00480 __IO uint32_t NDTR; 00481 __IO uint32_t PAR; 00482 __IO uint32_t M0AR; 00483 __IO uint32_t M1AR; 00484 __IO uint32_t FCR; 00485 } DMA_Stream_TypeDef; 00486 00487 typedef struct 00488 { 00489 __IO uint32_t LISR; 00490 __IO uint32_t HISR; 00491 __IO uint32_t LIFCR; 00492 __IO uint32_t HIFCR; 00493 } DMA_TypeDef; 00494 00499 typedef struct 00500 { 00501 __IO uint32_t MACCR; 00502 __IO uint32_t MACFFR; 00503 __IO uint32_t MACHTHR; 00504 __IO uint32_t MACHTLR; 00505 __IO uint32_t MACMIIAR; 00506 __IO uint32_t MACMIIDR; 00507 __IO uint32_t MACFCR; 00508 __IO uint32_t MACVLANTR; /* 8 */ 00509 uint32_t RESERVED0[2]; 00510 __IO uint32_t MACRWUFFR; /* 11 */ 00511 __IO uint32_t MACPMTCSR; 00512 uint32_t RESERVED1[2]; 00513 __IO uint32_t MACSR; /* 15 */ 00514 __IO uint32_t MACIMR; 00515 __IO uint32_t MACA0HR; 00516 __IO uint32_t MACA0LR; 00517 __IO uint32_t MACA1HR; 00518 __IO uint32_t MACA1LR; 00519 __IO uint32_t MACA2HR; 00520 __IO uint32_t MACA2LR; 00521 __IO uint32_t MACA3HR; 00522 __IO uint32_t MACA3LR; /* 24 */ 00523 uint32_t RESERVED2[40]; 00524 __IO uint32_t MMCCR; /* 65 */ 00525 __IO uint32_t MMCRIR; 00526 __IO uint32_t MMCTIR; 00527 __IO uint32_t MMCRIMR; 00528 __IO uint32_t MMCTIMR; /* 69 */ 00529 uint32_t RESERVED3[14]; 00530 __IO uint32_t MMCTGFSCCR; /* 84 */ 00531 __IO uint32_t MMCTGFMSCCR; 00532 uint32_t RESERVED4[5]; 00533 __IO uint32_t MMCTGFCR; 00534 uint32_t RESERVED5[10]; 00535 __IO uint32_t MMCRFCECR; 00536 __IO uint32_t MMCRFAECR; 00537 uint32_t RESERVED6[10]; 00538 __IO uint32_t MMCRGUFCR; 00539 uint32_t RESERVED7[334]; 00540 __IO uint32_t PTPTSCR; 00541 __IO uint32_t PTPSSIR; 00542 __IO uint32_t PTPTSHR; 00543 __IO uint32_t PTPTSLR; 00544 __IO uint32_t PTPTSHUR; 00545 __IO uint32_t PTPTSLUR; 00546 __IO uint32_t PTPTSAR; 00547 __IO uint32_t PTPTTHR; 00548 __IO uint32_t PTPTTLR; 00549 __IO uint32_t RESERVED8; 00550 __IO uint32_t PTPTSSR; 00551 uint32_t RESERVED9[565]; 00552 __IO uint32_t DMABMR; 00553 __IO uint32_t DMATPDR; 00554 __IO uint32_t DMARPDR; 00555 __IO uint32_t DMARDLAR; 00556 __IO uint32_t DMATDLAR; 00557 __IO uint32_t DMASR; 00558 __IO uint32_t DMAOMR; 00559 __IO uint32_t DMAIER; 00560 __IO uint32_t DMAMFBOCR; 00561 __IO uint32_t DMARSWTR; 00562 uint32_t RESERVED10[8]; 00563 __IO uint32_t DMACHTDR; 00564 __IO uint32_t DMACHRDR; 00565 __IO uint32_t DMACHTBAR; 00566 __IO uint32_t DMACHRBAR; 00567 } ETH_TypeDef; 00568 00573 typedef struct 00574 { 00575 __IO uint32_t IMR; 00576 __IO uint32_t EMR; 00577 __IO uint32_t RTSR; 00578 __IO uint32_t FTSR; 00579 __IO uint32_t SWIER; 00580 __IO uint32_t PR; 00581 } EXTI_TypeDef; 00582 00587 typedef struct 00588 { 00589 __IO uint32_t ACR; 00590 __IO uint32_t KEYR; 00591 __IO uint32_t OPTKEYR; 00592 __IO uint32_t SR; 00593 __IO uint32_t CR; 00594 __IO uint32_t OPTCR; 00595 } FLASH_TypeDef; 00596 00601 typedef struct 00602 { 00603 __IO uint32_t BTCR[8]; 00604 } FSMC_Bank1_TypeDef; 00605 00610 typedef struct 00611 { 00612 __IO uint32_t BWTR[7]; 00613 } FSMC_Bank1E_TypeDef; 00614 00619 typedef struct 00620 { 00621 __IO uint32_t PCR2; 00622 __IO uint32_t SR2; 00623 __IO uint32_t PMEM2; 00624 __IO uint32_t PATT2; 00625 uint32_t RESERVED0; 00626 __IO uint32_t ECCR2; 00627 } FSMC_Bank2_TypeDef; 00628 00633 typedef struct 00634 { 00635 __IO uint32_t PCR3; 00636 __IO uint32_t SR3; 00637 __IO uint32_t PMEM3; 00638 __IO uint32_t PATT3; 00639 uint32_t RESERVED0; 00640 __IO uint32_t ECCR3; 00641 } FSMC_Bank3_TypeDef; 00642 00647 typedef struct 00648 { 00649 __IO uint32_t PCR4; 00650 __IO uint32_t SR4; 00651 __IO uint32_t PMEM4; 00652 __IO uint32_t PATT4; 00653 __IO uint32_t PIO4; 00654 } FSMC_Bank4_TypeDef; 00655 00660 typedef struct 00661 { 00662 __IO uint32_t MODER; 00663 __IO uint32_t OTYPER; 00664 __IO uint32_t OSPEEDR; 00665 __IO uint32_t PUPDR; 00666 __IO uint32_t IDR; 00667 __IO uint32_t ODR; 00668 __IO uint16_t BSRRL; 00669 __IO uint16_t BSRRH; 00670 __IO uint32_t LCKR; 00671 __IO uint32_t AFR[2]; 00672 } GPIO_TypeDef; 00673 00678 typedef struct 00679 { 00680 __IO uint32_t MEMRMP; 00681 __IO uint32_t PMC; 00682 __IO uint32_t EXTICR[4]; 00683 uint32_t RESERVED[2]; 00684 __IO uint32_t CMPCR; 00685 } SYSCFG_TypeDef; 00686 00691 typedef struct 00692 { 00693 __IO uint16_t CR1; 00694 uint16_t RESERVED0; 00695 __IO uint16_t CR2; 00696 uint16_t RESERVED1; 00697 __IO uint16_t OAR1; 00698 uint16_t RESERVED2; 00699 __IO uint16_t OAR2; 00700 uint16_t RESERVED3; 00701 __IO uint16_t DR; 00702 uint16_t RESERVED4; 00703 __IO uint16_t SR1; 00704 uint16_t RESERVED5; 00705 __IO uint16_t SR2; 00706 uint16_t RESERVED6; 00707 __IO uint16_t CCR; 00708 uint16_t RESERVED7; 00709 __IO uint16_t TRISE; 00710 uint16_t RESERVED8; 00711 } I2C_TypeDef; 00712 00717 typedef struct 00718 { 00719 __IO uint32_t KR; 00720 __IO uint32_t PR; 00721 __IO uint32_t RLR; 00722 __IO uint32_t SR; 00723 } IWDG_TypeDef; 00724 00729 typedef struct 00730 { 00731 __IO uint32_t CR; 00732 __IO uint32_t CSR; 00733 } PWR_TypeDef; 00734 00739 typedef struct 00740 { 00741 __IO uint32_t CR; 00742 __IO uint32_t PLLCFGR; 00743 __IO uint32_t CFGR; 00744 __IO uint32_t CIR; 00745 __IO uint32_t AHB1RSTR; 00746 __IO uint32_t AHB2RSTR; 00747 __IO uint32_t AHB3RSTR; 00748 uint32_t RESERVED0; 00749 __IO uint32_t APB1RSTR; 00750 __IO uint32_t APB2RSTR; 00751 uint32_t RESERVED1[2]; 00752 __IO uint32_t AHB1ENR; 00753 __IO uint32_t AHB2ENR; 00754 __IO uint32_t AHB3ENR; 00755 uint32_t RESERVED2; 00756 __IO uint32_t APB1ENR; 00757 __IO uint32_t APB2ENR; 00758 uint32_t RESERVED3[2]; 00759 __IO uint32_t AHB1LPENR; 00760 __IO uint32_t AHB2LPENR; 00761 __IO uint32_t AHB3LPENR; 00762 uint32_t RESERVED4; 00763 __IO uint32_t APB1LPENR; 00764 __IO uint32_t APB2LPENR; 00765 uint32_t RESERVED5[2]; 00766 __IO uint32_t BDCR; 00767 __IO uint32_t CSR; 00768 uint32_t RESERVED6[2]; 00769 __IO uint32_t SSCGR; 00770 __IO uint32_t PLLI2SCFGR; 00771 } RCC_TypeDef; 00772 00777 typedef struct 00778 { 00779 __IO uint32_t TR; 00780 __IO uint32_t DR; 00781 __IO uint32_t CR; 00782 __IO uint32_t ISR; 00783 __IO uint32_t PRER; 00784 __IO uint32_t WUTR; 00785 __IO uint32_t CALIBR; 00786 __IO uint32_t ALRMAR; 00787 __IO uint32_t ALRMBR; 00788 __IO uint32_t WPR; 00789 __IO uint32_t SSR; 00790 __IO uint32_t SHIFTR; 00791 __IO uint32_t TSTR; 00792 __IO uint32_t TSDR; 00793 __IO uint32_t TSSSR; 00794 __IO uint32_t CALR; 00795 __IO uint32_t TAFCR; 00796 __IO uint32_t ALRMASSR; 00797 __IO uint32_t ALRMBSSR; 00798 uint32_t RESERVED7; 00799 __IO uint32_t BKP0R; 00800 __IO uint32_t BKP1R; 00801 __IO uint32_t BKP2R; 00802 __IO uint32_t BKP3R; 00803 __IO uint32_t BKP4R; 00804 __IO uint32_t BKP5R; 00805 __IO uint32_t BKP6R; 00806 __IO uint32_t BKP7R; 00807 __IO uint32_t BKP8R; 00808 __IO uint32_t BKP9R; 00809 __IO uint32_t BKP10R; 00810 __IO uint32_t BKP11R; 00811 __IO uint32_t BKP12R; 00812 __IO uint32_t BKP13R; 00813 __IO uint32_t BKP14R; 00814 __IO uint32_t BKP15R; 00815 __IO uint32_t BKP16R; 00816 __IO uint32_t BKP17R; 00817 __IO uint32_t BKP18R; 00818 __IO uint32_t BKP19R; 00819 } RTC_TypeDef; 00820 00825 typedef struct 00826 { 00827 __IO uint32_t POWER; 00828 __IO uint32_t CLKCR; 00829 __IO uint32_t ARG; 00830 __IO uint32_t CMD; 00831 __I uint32_t RESPCMD; 00832 __I uint32_t RESP1; 00833 __I uint32_t RESP2; 00834 __I uint32_t RESP3; 00835 __I uint32_t RESP4; 00836 __IO uint32_t DTIMER; 00837 __IO uint32_t DLEN; 00838 __IO uint32_t DCTRL; 00839 __I uint32_t DCOUNT; 00840 __I uint32_t STA; 00841 __IO uint32_t ICR; 00842 __IO uint32_t MASK; 00843 uint32_t RESERVED0[2]; 00844 __I uint32_t FIFOCNT; 00845 uint32_t RESERVED1[13]; 00846 __IO uint32_t FIFO; 00847 } SDIO_TypeDef; 00848 00853 typedef struct 00854 { 00855 __IO uint16_t CR1; 00856 uint16_t RESERVED0; 00857 __IO uint16_t CR2; 00858 uint16_t RESERVED1; 00859 __IO uint16_t SR; 00860 uint16_t RESERVED2; 00861 __IO uint16_t DR; 00862 uint16_t RESERVED3; 00863 __IO uint16_t CRCPR; 00864 uint16_t RESERVED4; 00865 __IO uint16_t RXCRCR; 00866 uint16_t RESERVED5; 00867 __IO uint16_t TXCRCR; 00868 uint16_t RESERVED6; 00869 __IO uint16_t I2SCFGR; 00870 uint16_t RESERVED7; 00871 __IO uint16_t I2SPR; 00872 uint16_t RESERVED8; 00873 } SPI_TypeDef; 00874 00879 typedef struct 00880 { 00881 __IO uint16_t CR1; 00882 uint16_t RESERVED0; 00883 __IO uint16_t CR2; 00884 uint16_t RESERVED1; 00885 __IO uint16_t SMCR; 00886 uint16_t RESERVED2; 00887 __IO uint16_t DIER; 00888 uint16_t RESERVED3; 00889 __IO uint16_t SR; 00890 uint16_t RESERVED4; 00891 __IO uint16_t EGR; 00892 uint16_t RESERVED5; 00893 __IO uint16_t CCMR1; 00894 uint16_t RESERVED6; 00895 __IO uint16_t CCMR2; 00896 uint16_t RESERVED7; 00897 __IO uint16_t CCER; 00898 uint16_t RESERVED8; 00899 __IO uint32_t CNT; 00900 __IO uint16_t PSC; 00901 uint16_t RESERVED9; 00902 __IO uint32_t ARR; 00903 __IO uint16_t RCR; 00904 uint16_t RESERVED10; 00905 __IO uint32_t CCR1; 00906 __IO uint32_t CCR2; 00907 __IO uint32_t CCR3; 00908 __IO uint32_t CCR4; 00909 __IO uint16_t BDTR; 00910 uint16_t RESERVED11; 00911 __IO uint16_t DCR; 00912 uint16_t RESERVED12; 00913 __IO uint16_t DMAR; 00914 uint16_t RESERVED13; 00915 __IO uint16_t OR; 00916 uint16_t RESERVED14; 00917 } TIM_TypeDef; 00918 00923 typedef struct 00924 { 00925 __IO uint16_t SR; 00926 uint16_t RESERVED0; 00927 __IO uint16_t DR; 00928 uint16_t RESERVED1; 00929 __IO uint16_t BRR; 00930 uint16_t RESERVED2; 00931 __IO uint16_t CR1; 00932 uint16_t RESERVED3; 00933 __IO uint16_t CR2; 00934 uint16_t RESERVED4; 00935 __IO uint16_t CR3; 00936 uint16_t RESERVED5; 00937 __IO uint16_t GTPR; 00938 uint16_t RESERVED6; 00939 } USART_TypeDef; 00940 00945 typedef struct 00946 { 00947 __IO uint32_t CR; 00948 __IO uint32_t CFR; 00949 __IO uint32_t SR; 00950 } WWDG_TypeDef; 00951 00956 typedef struct 00957 { 00958 __IO uint32_t CR; 00959 __IO uint32_t SR; 00960 __IO uint32_t DR; 00961 __IO uint32_t DOUT; 00962 __IO uint32_t DMACR; 00963 __IO uint32_t IMSCR; 00964 __IO uint32_t RISR; 00965 __IO uint32_t MISR; 00966 __IO uint32_t K0LR; 00967 __IO uint32_t K0RR; 00968 __IO uint32_t K1LR; 00969 __IO uint32_t K1RR; 00970 __IO uint32_t K2LR; 00971 __IO uint32_t K2RR; 00972 __IO uint32_t K3LR; 00973 __IO uint32_t K3RR; 00974 __IO uint32_t IV0LR; 00975 __IO uint32_t IV0RR; 00976 __IO uint32_t IV1LR; 00977 __IO uint32_t IV1RR; 00978 } CRYP_TypeDef; 00979 00984 typedef struct 00985 { 00986 __IO uint32_t CR; 00987 __IO uint32_t DIN; 00988 __IO uint32_t STR; 00989 __IO uint32_t HR[5]; 00990 __IO uint32_t IMR; 00991 __IO uint32_t SR; 00992 uint32_t RESERVED[52]; 00993 __IO uint32_t CSR[51]; 00994 } HASH_TypeDef; 00995 01000 typedef struct 01001 { 01002 __IO uint32_t CR; 01003 __IO uint32_t SR; 01004 __IO uint32_t DR; 01005 } RNG_TypeDef; 01006 01014 #define FLASH_BASE ((uint32_t)0x08000000) 01015 #define CCMDATARAM_BASE ((uint32_t)0x10000000) 01016 #define SRAM1_BASE ((uint32_t)0x20000000) 01017 #define SRAM2_BASE ((uint32_t)0x2001C000) 01018 #define PERIPH_BASE ((uint32_t)0x40000000) 01019 #define BKPSRAM_BASE ((uint32_t)0x40024000) 01020 #define FSMC_R_BASE ((uint32_t)0xA0000000) 01022 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) 01023 #define SRAM1_BB_BASE ((uint32_t)0x22000000) 01024 #define SRAM2_BB_BASE ((uint32_t)0x2201C000) 01025 #define PERIPH_BB_BASE ((uint32_t)0x42000000) 01026 #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) 01028 /* Legacy defines */ 01029 #define SRAM_BASE SRAM1_BASE 01030 #define SRAM_BB_BASE SRAM1_BB_BASE 01031 01032 01034 #define APB1PERIPH_BASE PERIPH_BASE 01035 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) 01036 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) 01037 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) 01038 01040 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 01041 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 01042 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 01043 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 01044 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 01045 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 01046 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) 01047 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) 01048 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) 01049 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 01050 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 01051 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 01052 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) 01053 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 01054 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 01055 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) 01056 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 01057 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 01058 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 01059 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 01060 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 01061 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 01062 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) 01063 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 01064 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) 01065 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 01066 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 01067 01069 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) 01070 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) 01071 #define USART1_BASE (APB2PERIPH_BASE + 0x1000) 01072 #define USART6_BASE (APB2PERIPH_BASE + 0x1400) 01073 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) 01074 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) 01075 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) 01076 #define ADC_BASE (APB2PERIPH_BASE + 0x2300) 01077 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) 01078 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 01079 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) 01080 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) 01081 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) 01082 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) 01083 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) 01084 01086 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) 01087 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) 01088 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) 01089 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) 01090 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) 01091 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) 01092 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) 01093 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) 01094 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) 01095 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) 01096 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) 01097 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) 01098 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) 01099 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) 01100 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) 01101 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) 01102 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) 01103 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) 01104 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) 01105 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) 01106 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) 01107 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) 01108 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) 01109 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) 01110 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) 01111 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) 01112 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) 01113 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) 01114 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) 01115 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) 01116 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) 01117 #define ETH_MAC_BASE (ETH_BASE) 01118 #define ETH_MMC_BASE (ETH_BASE + 0x0100) 01119 #define ETH_PTP_BASE (ETH_BASE + 0x0700) 01120 #define ETH_DMA_BASE (ETH_BASE + 0x1000) 01121 01123 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) 01124 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) 01125 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) 01126 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) 01127 01129 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) 01130 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) 01131 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) 01132 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) 01133 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) 01134 01135 /* Debug MCU registers base address */ 01136 #define DBGMCU_BASE ((uint32_t )0xE0042000) 01137 01145 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 01146 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 01147 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 01148 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 01149 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 01150 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 01151 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 01152 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 01153 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 01154 #define RTC ((RTC_TypeDef *) RTC_BASE) 01155 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 01156 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 01157 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE) 01158 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 01159 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 01160 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE) 01161 #define USART2 ((USART_TypeDef *) USART2_BASE) 01162 #define USART3 ((USART_TypeDef *) USART3_BASE) 01163 #define UART4 ((USART_TypeDef *) UART4_BASE) 01164 #define UART5 ((USART_TypeDef *) UART5_BASE) 01165 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 01166 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 01167 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 01168 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 01169 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 01170 #define PWR ((PWR_TypeDef *) PWR_BASE) 01171 #define DAC ((DAC_TypeDef *) DAC_BASE) 01172 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 01173 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 01174 #define USART1 ((USART_TypeDef *) USART1_BASE) 01175 #define USART6 ((USART_TypeDef *) USART6_BASE) 01176 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) 01177 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 01178 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 01179 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 01180 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 01181 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01182 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 01183 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 01184 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 01185 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 01186 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 01187 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01188 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01189 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01190 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01191 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01192 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01193 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01194 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 01195 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 01196 #define CRC ((CRC_TypeDef *) CRC_BASE) 01197 #define RCC ((RCC_TypeDef *) RCC_BASE) 01198 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01199 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01200 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) 01201 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) 01202 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) 01203 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) 01204 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) 01205 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) 01206 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) 01207 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) 01208 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01209 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) 01210 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) 01211 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) 01212 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) 01213 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) 01214 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) 01215 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) 01216 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) 01217 #define ETH ((ETH_TypeDef *) ETH_BASE) 01218 #define DCMI ((DCMI_TypeDef *) DCMI_BASE) 01219 #define CRYP ((CRYP_TypeDef *) CRYP_BASE) 01220 #define HASH ((HASH_TypeDef *) HASH_BASE) 01221 #define RNG ((RNG_TypeDef *) RNG_BASE) 01222 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 01223 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 01224 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) 01225 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) 01226 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) 01227 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01228 01241 /******************************************************************************/ 01242 /* Peripheral Registers_Bits_Definition */ 01243 /******************************************************************************/ 01244 01245 /******************************************************************************/ 01246 /* */ 01247 /* Analog to Digital Converter */ 01248 /* */ 01249 /******************************************************************************/ 01250 /******************** Bit definition for ADC_SR register ********************/ 01251 #define ADC_SR_AWD ((uint8_t)0x01) 01252 #define ADC_SR_EOC ((uint8_t)0x02) 01253 #define ADC_SR_JEOC ((uint8_t)0x04) 01254 #define ADC_SR_JSTRT ((uint8_t)0x08) 01255 #define ADC_SR_STRT ((uint8_t)0x10) 01256 #define ADC_SR_OVR ((uint8_t)0x20) 01258 /******************* Bit definition for ADC_CR1 register ********************/ 01259 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) 01260 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) 01261 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) 01262 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) 01263 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) 01264 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) 01265 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) 01266 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) 01267 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) 01268 #define ADC_CR1_SCAN ((uint32_t)0x00000100) 01269 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) 01270 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) 01271 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) 01272 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) 01273 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) 01274 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) 01275 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) 01276 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) 01277 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) 01278 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) 01279 #define ADC_CR1_RES ((uint32_t)0x03000000) 01280 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) 01281 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) 01282 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) 01284 /******************* Bit definition for ADC_CR2 register ********************/ 01285 #define ADC_CR2_ADON ((uint32_t)0x00000001) 01286 #define ADC_CR2_CONT ((uint32_t)0x00000002) 01287 #define ADC_CR2_DMA ((uint32_t)0x00000100) 01288 #define ADC_CR2_DDS ((uint32_t)0x00000200) 01289 #define ADC_CR2_EOCS ((uint32_t)0x00000400) 01290 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) 01291 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) 01292 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) 01293 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) 01294 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) 01295 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) 01296 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) 01297 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) 01298 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) 01299 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) 01300 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) 01301 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) 01302 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) 01303 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) 01304 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) 01305 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) 01306 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) 01307 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) 01308 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) 01310 /****************** Bit definition for ADC_SMPR1 register *******************/ 01311 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) 01312 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) 01313 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) 01314 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) 01315 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) 01316 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) 01317 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) 01318 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) 01319 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) 01320 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) 01321 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) 01322 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) 01323 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) 01324 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) 01325 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) 01326 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) 01327 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) 01328 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) 01329 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) 01330 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) 01331 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) 01332 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) 01333 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) 01334 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) 01335 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) 01336 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) 01337 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) 01338 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) 01339 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) 01340 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) 01341 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) 01342 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) 01343 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) 01344 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) 01345 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) 01346 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) 01348 /****************** Bit definition for ADC_SMPR2 register *******************/ 01349 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) 01350 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) 01351 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) 01352 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) 01353 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) 01354 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) 01355 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) 01356 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) 01357 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) 01358 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) 01359 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) 01360 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) 01361 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) 01362 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) 01363 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) 01364 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) 01365 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) 01366 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) 01367 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) 01368 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) 01369 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) 01370 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) 01371 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) 01372 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) 01373 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) 01374 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) 01375 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) 01376 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) 01377 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) 01378 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) 01379 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) 01380 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) 01381 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) 01382 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) 01383 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) 01384 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) 01385 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) 01386 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) 01387 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) 01388 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) 01390 /****************** Bit definition for ADC_JOFR1 register *******************/ 01391 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) 01393 /****************** Bit definition for ADC_JOFR2 register *******************/ 01394 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) 01396 /****************** Bit definition for ADC_JOFR3 register *******************/ 01397 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) 01399 /****************** Bit definition for ADC_JOFR4 register *******************/ 01400 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) 01402 /******************* Bit definition for ADC_HTR register ********************/ 01403 #define ADC_HTR_HT ((uint16_t)0x0FFF) 01405 /******************* Bit definition for ADC_LTR register ********************/ 01406 #define ADC_LTR_LT ((uint16_t)0x0FFF) 01408 /******************* Bit definition for ADC_SQR1 register *******************/ 01409 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) 01410 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) 01411 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) 01412 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) 01413 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) 01414 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) 01415 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) 01416 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) 01417 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) 01418 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) 01419 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) 01420 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) 01421 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) 01422 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) 01423 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) 01424 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) 01425 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) 01426 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) 01427 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) 01428 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) 01429 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) 01430 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) 01431 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) 01432 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) 01433 #define ADC_SQR1_L ((uint32_t)0x00F00000) 01434 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) 01435 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) 01436 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) 01437 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) 01439 /******************* Bit definition for ADC_SQR2 register *******************/ 01440 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) 01441 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) 01442 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) 01443 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) 01444 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) 01445 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) 01446 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) 01447 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) 01448 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) 01449 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) 01450 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) 01451 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) 01452 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) 01453 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) 01454 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) 01455 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) 01456 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) 01457 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) 01458 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) 01459 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) 01460 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) 01461 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) 01462 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) 01463 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) 01464 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) 01465 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) 01466 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) 01467 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) 01468 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) 01469 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) 01470 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) 01471 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) 01472 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) 01473 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) 01474 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) 01475 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) 01477 /******************* Bit definition for ADC_SQR3 register *******************/ 01478 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) 01479 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) 01480 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) 01481 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) 01482 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) 01483 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) 01484 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) 01485 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) 01486 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) 01487 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) 01488 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) 01489 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) 01490 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) 01491 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) 01492 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) 01493 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) 01494 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) 01495 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) 01496 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) 01497 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) 01498 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) 01499 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) 01500 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) 01501 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) 01502 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) 01503 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) 01504 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) 01505 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) 01506 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) 01507 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) 01508 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) 01509 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) 01510 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) 01511 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) 01512 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) 01513 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) 01515 /******************* Bit definition for ADC_JSQR register *******************/ 01516 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) 01517 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) 01518 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) 01519 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) 01520 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) 01521 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) 01522 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) 01523 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) 01524 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) 01525 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) 01526 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) 01527 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) 01528 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) 01529 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) 01530 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) 01531 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) 01532 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) 01533 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) 01534 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) 01535 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) 01536 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) 01537 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) 01538 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) 01539 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) 01540 #define ADC_JSQR_JL ((uint32_t)0x00300000) 01541 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) 01542 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) 01544 /******************* Bit definition for ADC_JDR1 register *******************/ 01545 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) 01547 /******************* Bit definition for ADC_JDR2 register *******************/ 01548 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) 01550 /******************* Bit definition for ADC_JDR3 register *******************/ 01551 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) 01553 /******************* Bit definition for ADC_JDR4 register *******************/ 01554 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) 01556 /******************** Bit definition for ADC_DR register ********************/ 01557 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) 01558 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) 01560 /******************* Bit definition for ADC_CSR register ********************/ 01561 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) 01562 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) 01563 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) 01564 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) 01565 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) 01566 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) 01567 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) 01568 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) 01569 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) 01570 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) 01571 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) 01572 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) 01573 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) 01574 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) 01575 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) 01576 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) 01577 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) 01578 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) 01580 /******************* Bit definition for ADC_CCR register ********************/ 01581 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) 01582 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) 01583 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) 01584 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) 01585 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) 01586 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) 01587 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) 01588 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) 01589 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) 01590 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) 01591 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) 01592 #define ADC_CCR_DDS ((uint32_t)0x00002000) 01593 #define ADC_CCR_DMA ((uint32_t)0x0000C000) 01594 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) 01595 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) 01596 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) 01597 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) 01598 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) 01599 #define ADC_CCR_VBATE ((uint32_t)0x00400000) 01600 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) 01602 /******************* Bit definition for ADC_CDR register ********************/ 01603 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) 01604 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) 01606 /******************************************************************************/ 01607 /* */ 01608 /* Controller Area Network */ 01609 /* */ 01610 /******************************************************************************/ 01612 /******************* Bit definition for CAN_MCR register ********************/ 01613 #define CAN_MCR_INRQ ((uint16_t)0x0001) 01614 #define CAN_MCR_SLEEP ((uint16_t)0x0002) 01615 #define CAN_MCR_TXFP ((uint16_t)0x0004) 01616 #define CAN_MCR_RFLM ((uint16_t)0x0008) 01617 #define CAN_MCR_NART ((uint16_t)0x0010) 01618 #define CAN_MCR_AWUM ((uint16_t)0x0020) 01619 #define CAN_MCR_ABOM ((uint16_t)0x0040) 01620 #define CAN_MCR_TTCM ((uint16_t)0x0080) 01621 #define CAN_MCR_RESET ((uint16_t)0x8000) 01623 /******************* Bit definition for CAN_MSR register ********************/ 01624 #define CAN_MSR_INAK ((uint16_t)0x0001) 01625 #define CAN_MSR_SLAK ((uint16_t)0x0002) 01626 #define CAN_MSR_ERRI ((uint16_t)0x0004) 01627 #define CAN_MSR_WKUI ((uint16_t)0x0008) 01628 #define CAN_MSR_SLAKI ((uint16_t)0x0010) 01629 #define CAN_MSR_TXM ((uint16_t)0x0100) 01630 #define CAN_MSR_RXM ((uint16_t)0x0200) 01631 #define CAN_MSR_SAMP ((uint16_t)0x0400) 01632 #define CAN_MSR_RX ((uint16_t)0x0800) 01634 /******************* Bit definition for CAN_TSR register ********************/ 01635 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) 01636 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) 01637 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) 01638 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) 01639 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) 01640 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) 01641 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) 01642 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) 01643 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) 01644 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) 01645 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) 01646 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) 01647 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) 01648 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) 01649 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) 01650 #define CAN_TSR_CODE ((uint32_t)0x03000000) 01652 #define CAN_TSR_TME ((uint32_t)0x1C000000) 01653 #define CAN_TSR_TME0 ((uint32_t)0x04000000) 01654 #define CAN_TSR_TME1 ((uint32_t)0x08000000) 01655 #define CAN_TSR_TME2 ((uint32_t)0x10000000) 01657 #define CAN_TSR_LOW ((uint32_t)0xE0000000) 01658 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) 01659 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) 01660 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) 01662 /******************* Bit definition for CAN_RF0R register *******************/ 01663 #define CAN_RF0R_FMP0 ((uint8_t)0x03) 01664 #define CAN_RF0R_FULL0 ((uint8_t)0x08) 01665 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) 01666 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) 01668 /******************* Bit definition for CAN_RF1R register *******************/ 01669 #define CAN_RF1R_FMP1 ((uint8_t)0x03) 01670 #define CAN_RF1R_FULL1 ((uint8_t)0x08) 01671 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) 01672 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) 01674 /******************** Bit definition for CAN_IER register *******************/ 01675 #define CAN_IER_TMEIE ((uint32_t)0x00000001) 01676 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) 01677 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) 01678 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) 01679 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) 01680 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) 01681 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) 01682 #define CAN_IER_EWGIE ((uint32_t)0x00000100) 01683 #define CAN_IER_EPVIE ((uint32_t)0x00000200) 01684 #define CAN_IER_BOFIE ((uint32_t)0x00000400) 01685 #define CAN_IER_LECIE ((uint32_t)0x00000800) 01686 #define CAN_IER_ERRIE ((uint32_t)0x00008000) 01687 #define CAN_IER_WKUIE ((uint32_t)0x00010000) 01688 #define CAN_IER_SLKIE ((uint32_t)0x00020000) 01690 /******************** Bit definition for CAN_ESR register *******************/ 01691 #define CAN_ESR_EWGF ((uint32_t)0x00000001) 01692 #define CAN_ESR_EPVF ((uint32_t)0x00000002) 01693 #define CAN_ESR_BOFF ((uint32_t)0x00000004) 01695 #define CAN_ESR_LEC ((uint32_t)0x00000070) 01696 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) 01697 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) 01698 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) 01700 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) 01701 #define CAN_ESR_REC ((uint32_t)0xFF000000) 01703 /******************* Bit definition for CAN_BTR register ********************/ 01704 #define CAN_BTR_BRP ((uint32_t)0x000003FF) 01705 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) 01706 #define CAN_BTR_TS2 ((uint32_t)0x00700000) 01707 #define CAN_BTR_SJW ((uint32_t)0x03000000) 01708 #define CAN_BTR_LBKM ((uint32_t)0x40000000) 01709 #define CAN_BTR_SILM ((uint32_t)0x80000000) 01712 /****************** Bit definition for CAN_TI0R register ********************/ 01713 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) 01714 #define CAN_TI0R_RTR ((uint32_t)0x00000002) 01715 #define CAN_TI0R_IDE ((uint32_t)0x00000004) 01716 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) 01717 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) 01719 /****************** Bit definition for CAN_TDT0R register *******************/ 01720 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) 01721 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) 01722 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) 01724 /****************** Bit definition for CAN_TDL0R register *******************/ 01725 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) 01726 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) 01727 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) 01728 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) 01730 /****************** Bit definition for CAN_TDH0R register *******************/ 01731 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) 01732 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) 01733 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) 01734 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) 01736 /******************* Bit definition for CAN_TI1R register *******************/ 01737 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) 01738 #define CAN_TI1R_RTR ((uint32_t)0x00000002) 01739 #define CAN_TI1R_IDE ((uint32_t)0x00000004) 01740 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) 01741 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) 01743 /******************* Bit definition for CAN_TDT1R register ******************/ 01744 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) 01745 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) 01746 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) 01748 /******************* Bit definition for CAN_TDL1R register ******************/ 01749 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) 01750 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) 01751 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) 01752 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) 01754 /******************* Bit definition for CAN_TDH1R register ******************/ 01755 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) 01756 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) 01757 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) 01758 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) 01760 /******************* Bit definition for CAN_TI2R register *******************/ 01761 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) 01762 #define CAN_TI2R_RTR ((uint32_t)0x00000002) 01763 #define CAN_TI2R_IDE ((uint32_t)0x00000004) 01764 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) 01765 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) 01767 /******************* Bit definition for CAN_TDT2R register ******************/ 01768 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) 01769 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) 01770 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) 01772 /******************* Bit definition for CAN_TDL2R register ******************/ 01773 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) 01774 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) 01775 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) 01776 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) 01778 /******************* Bit definition for CAN_TDH2R register ******************/ 01779 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) 01780 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) 01781 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) 01782 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) 01784 /******************* Bit definition for CAN_RI0R register *******************/ 01785 #define CAN_RI0R_RTR ((uint32_t)0x00000002) 01786 #define CAN_RI0R_IDE ((uint32_t)0x00000004) 01787 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) 01788 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) 01790 /******************* Bit definition for CAN_RDT0R register ******************/ 01791 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) 01792 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) 01793 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 01795 /******************* Bit definition for CAN_RDL0R register ******************/ 01796 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 01797 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 01798 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) 01799 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 01801 /******************* Bit definition for CAN_RDH0R register ******************/ 01802 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 01803 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 01804 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 01805 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) 01807 /******************* Bit definition for CAN_RI1R register *******************/ 01808 #define CAN_RI1R_RTR ((uint32_t)0x00000002) 01809 #define CAN_RI1R_IDE ((uint32_t)0x00000004) 01810 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) 01811 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) 01813 /******************* Bit definition for CAN_RDT1R register ******************/ 01814 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) 01815 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) 01816 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) 01818 /******************* Bit definition for CAN_RDL1R register ******************/ 01819 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) 01820 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) 01821 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) 01822 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) 01824 /******************* Bit definition for CAN_RDH1R register ******************/ 01825 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) 01826 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) 01827 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) 01828 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) 01831 /******************* Bit definition for CAN_FMR register ********************/ 01832 #define CAN_FMR_FINIT ((uint8_t)0x01) 01834 /******************* Bit definition for CAN_FM1R register *******************/ 01835 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) 01836 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) 01837 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) 01838 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) 01839 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) 01840 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) 01841 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) 01842 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) 01843 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) 01844 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) 01845 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) 01846 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) 01847 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) 01848 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) 01849 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) 01851 /******************* Bit definition for CAN_FS1R register *******************/ 01852 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) 01853 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) 01854 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) 01855 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) 01856 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) 01857 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) 01858 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) 01859 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) 01860 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) 01861 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) 01862 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) 01863 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) 01864 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) 01865 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) 01866 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) 01868 /****************** Bit definition for CAN_FFA1R register *******************/ 01869 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) 01870 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) 01871 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) 01872 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) 01873 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) 01874 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) 01875 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) 01876 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) 01877 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) 01878 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) 01879 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) 01880 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) 01881 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) 01882 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) 01883 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) 01885 /******************* Bit definition for CAN_FA1R register *******************/ 01886 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) 01887 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) 01888 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) 01889 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) 01890 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) 01891 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) 01892 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) 01893 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) 01894 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) 01895 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) 01896 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) 01897 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) 01898 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) 01899 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) 01900 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) 01902 /******************* Bit definition for CAN_F0R1 register *******************/ 01903 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) 01904 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) 01905 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) 01906 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) 01907 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) 01908 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) 01909 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) 01910 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) 01911 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) 01912 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) 01913 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) 01914 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) 01915 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) 01916 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) 01917 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) 01918 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) 01919 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) 01920 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) 01921 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) 01922 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) 01923 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) 01924 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) 01925 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) 01926 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) 01927 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) 01928 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) 01929 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) 01930 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) 01931 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) 01932 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) 01933 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) 01934 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) 01936 /******************* Bit definition for CAN_F1R1 register *******************/ 01937 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) 01938 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) 01939 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) 01940 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) 01941 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) 01942 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) 01943 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) 01944 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) 01945 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) 01946 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) 01947 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) 01948 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) 01949 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) 01950 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) 01951 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) 01952 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) 01953 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) 01954 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) 01955 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) 01956 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) 01957 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) 01958 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) 01959 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) 01960 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) 01961 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) 01962 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) 01963 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) 01964 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) 01965 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) 01966 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) 01967 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) 01968 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) 01970 /******************* Bit definition for CAN_F2R1 register *******************/ 01971 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) 01972 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) 01973 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) 01974 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) 01975 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) 01976 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) 01977 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) 01978 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) 01979 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) 01980 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) 01981 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) 01982 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) 01983 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) 01984 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) 01985 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) 01986 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) 01987 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) 01988 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) 01989 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) 01990 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) 01991 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) 01992 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) 01993 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) 01994 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) 01995 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) 01996 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) 01997 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) 01998 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) 01999 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) 02000 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) 02001 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) 02002 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) 02004 /******************* Bit definition for CAN_F3R1 register *******************/ 02005 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) 02006 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) 02007 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) 02008 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) 02009 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) 02010 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) 02011 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) 02012 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) 02013 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) 02014 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) 02015 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) 02016 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) 02017 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) 02018 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) 02019 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) 02020 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) 02021 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) 02022 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) 02023 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) 02024 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) 02025 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) 02026 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) 02027 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) 02028 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) 02029 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) 02030 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) 02031 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) 02032 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) 02033 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) 02034 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) 02035 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) 02036 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) 02038 /******************* Bit definition for CAN_F4R1 register *******************/ 02039 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) 02040 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) 02041 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) 02042 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) 02043 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) 02044 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) 02045 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) 02046 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) 02047 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) 02048 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) 02049 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) 02050 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) 02051 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) 02052 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) 02053 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) 02054 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) 02055 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) 02056 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) 02057 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) 02058 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) 02059 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) 02060 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) 02061 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) 02062 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) 02063 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) 02064 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) 02065 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) 02066 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) 02067 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) 02068 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) 02069 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) 02070 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) 02072 /******************* Bit definition for CAN_F5R1 register *******************/ 02073 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) 02074 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) 02075 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) 02076 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) 02077 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) 02078 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) 02079 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) 02080 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) 02081 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) 02082 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) 02083 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) 02084 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) 02085 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) 02086 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) 02087 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) 02088 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) 02089 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) 02090 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) 02091 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) 02092 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) 02093 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) 02094 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) 02095 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) 02096 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) 02097 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) 02098 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) 02099 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) 02100 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) 02101 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) 02102 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) 02103 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) 02104 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) 02106 /******************* Bit definition for CAN_F6R1 register *******************/ 02107 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) 02108 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) 02109 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) 02110 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) 02111 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) 02112 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) 02113 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) 02114 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) 02115 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) 02116 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) 02117 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) 02118 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) 02119 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) 02120 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) 02121 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) 02122 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) 02123 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) 02124 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) 02125 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) 02126 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) 02127 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) 02128 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) 02129 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) 02130 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) 02131 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) 02132 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) 02133 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) 02134 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) 02135 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) 02136 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) 02137 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) 02138 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) 02140 /******************* Bit definition for CAN_F7R1 register *******************/ 02141 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) 02142 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) 02143 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) 02144 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) 02145 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) 02146 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) 02147 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) 02148 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) 02149 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) 02150 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) 02151 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) 02152 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) 02153 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) 02154 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) 02155 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) 02156 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) 02157 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) 02158 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) 02159 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) 02160 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) 02161 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) 02162 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) 02163 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) 02164 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) 02165 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) 02166 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) 02167 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) 02168 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) 02169 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) 02170 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) 02171 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) 02172 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) 02174 /******************* Bit definition for CAN_F8R1 register *******************/ 02175 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) 02176 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) 02177 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) 02178 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) 02179 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) 02180 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) 02181 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) 02182 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) 02183 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) 02184 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) 02185 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) 02186 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) 02187 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) 02188 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) 02189 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) 02190 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) 02191 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) 02192 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) 02193 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) 02194 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) 02195 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) 02196 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) 02197 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) 02198 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) 02199 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) 02200 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) 02201 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) 02202 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) 02203 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) 02204 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) 02205 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) 02206 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) 02208 /******************* Bit definition for CAN_F9R1 register *******************/ 02209 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) 02210 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) 02211 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) 02212 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) 02213 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) 02214 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) 02215 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) 02216 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) 02217 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) 02218 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) 02219 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) 02220 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) 02221 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) 02222 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) 02223 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) 02224 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) 02225 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) 02226 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) 02227 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) 02228 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) 02229 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) 02230 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) 02231 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) 02232 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) 02233 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) 02234 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) 02235 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) 02236 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) 02237 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) 02238 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) 02239 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) 02240 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) 02242 /******************* Bit definition for CAN_F10R1 register ******************/ 02243 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) 02244 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) 02245 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) 02246 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) 02247 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) 02248 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) 02249 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) 02250 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) 02251 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) 02252 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) 02253 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) 02254 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) 02255 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) 02256 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) 02257 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) 02258 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) 02259 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) 02260 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) 02261 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) 02262 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) 02263 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) 02264 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) 02265 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) 02266 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) 02267 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) 02268 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) 02269 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) 02270 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) 02271 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) 02272 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) 02273 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) 02274 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) 02276 /******************* Bit definition for CAN_F11R1 register ******************/ 02277 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) 02278 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) 02279 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) 02280 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) 02281 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) 02282 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) 02283 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) 02284 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) 02285 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) 02286 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) 02287 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) 02288 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) 02289 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) 02290 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) 02291 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) 02292 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) 02293 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) 02294 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) 02295 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) 02296 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) 02297 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) 02298 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) 02299 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) 02300 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) 02301 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) 02302 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) 02303 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) 02304 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) 02305 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) 02306 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) 02307 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) 02308 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) 02310 /******************* Bit definition for CAN_F12R1 register ******************/ 02311 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) 02312 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) 02313 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) 02314 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) 02315 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) 02316 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) 02317 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) 02318 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) 02319 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) 02320 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) 02321 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) 02322 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) 02323 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) 02324 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) 02325 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) 02326 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) 02327 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) 02328 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) 02329 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) 02330 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) 02331 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) 02332 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) 02333 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) 02334 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) 02335 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) 02336 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) 02337 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) 02338 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) 02339 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) 02340 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) 02341 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) 02342 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) 02344 /******************* Bit definition for CAN_F13R1 register ******************/ 02345 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) 02346 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) 02347 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) 02348 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) 02349 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) 02350 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) 02351 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) 02352 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) 02353 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) 02354 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) 02355 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) 02356 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) 02357 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) 02358 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) 02359 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) 02360 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) 02361 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) 02362 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) 02363 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) 02364 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) 02365 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) 02366 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) 02367 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) 02368 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) 02369 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) 02370 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) 02371 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) 02372 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) 02373 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) 02374 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) 02375 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) 02376 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) 02378 /******************* Bit definition for CAN_F0R2 register *******************/ 02379 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) 02380 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) 02381 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) 02382 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) 02383 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) 02384 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) 02385 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) 02386 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) 02387 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) 02388 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) 02389 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) 02390 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) 02391 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) 02392 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) 02393 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) 02394 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) 02395 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) 02396 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) 02397 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) 02398 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) 02399 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) 02400 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) 02401 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) 02402 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) 02403 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) 02404 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) 02405 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) 02406 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) 02407 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) 02408 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) 02409 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) 02410 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) 02412 /******************* Bit definition for CAN_F1R2 register *******************/ 02413 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) 02414 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) 02415 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) 02416 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) 02417 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) 02418 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) 02419 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) 02420 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) 02421 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) 02422 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) 02423 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) 02424 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) 02425 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) 02426 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) 02427 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) 02428 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) 02429 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) 02430 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) 02431 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) 02432 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) 02433 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) 02434 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) 02435 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) 02436 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) 02437 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) 02438 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) 02439 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) 02440 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) 02441 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) 02442 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) 02443 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) 02444 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) 02446 /******************* Bit definition for CAN_F2R2 register *******************/ 02447 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) 02448 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) 02449 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) 02450 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) 02451 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) 02452 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) 02453 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) 02454 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) 02455 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) 02456 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) 02457 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) 02458 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) 02459 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) 02460 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) 02461 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) 02462 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) 02463 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) 02464 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) 02465 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) 02466 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) 02467 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) 02468 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) 02469 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) 02470 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) 02471 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) 02472 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) 02473 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) 02474 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) 02475 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) 02476 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) 02477 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) 02478 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) 02480 /******************* Bit definition for CAN_F3R2 register *******************/ 02481 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) 02482 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) 02483 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) 02484 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) 02485 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) 02486 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) 02487 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) 02488 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) 02489 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) 02490 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) 02491 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) 02492 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) 02493 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) 02494 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) 02495 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) 02496 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) 02497 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) 02498 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) 02499 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) 02500 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) 02501 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) 02502 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) 02503 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) 02504 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) 02505 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) 02506 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) 02507 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) 02508 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) 02509 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) 02510 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) 02511 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) 02512 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) 02514 /******************* Bit definition for CAN_F4R2 register *******************/ 02515 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) 02516 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) 02517 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) 02518 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) 02519 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) 02520 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) 02521 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) 02522 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) 02523 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) 02524 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) 02525 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) 02526 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) 02527 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) 02528 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) 02529 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) 02530 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) 02531 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) 02532 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) 02533 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) 02534 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) 02535 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) 02536 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) 02537 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) 02538 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) 02539 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) 02540 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) 02541 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) 02542 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) 02543 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) 02544 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) 02545 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) 02546 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) 02548 /******************* Bit definition for CAN_F5R2 register *******************/ 02549 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) 02550 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) 02551 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) 02552 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) 02553 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) 02554 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) 02555 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) 02556 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) 02557 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) 02558 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) 02559 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) 02560 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) 02561 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) 02562 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) 02563 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) 02564 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) 02565 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) 02566 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) 02567 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) 02568 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) 02569 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) 02570 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) 02571 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) 02572 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) 02573 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) 02574 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) 02575 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) 02576 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) 02577 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) 02578 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) 02579 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) 02580 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) 02582 /******************* Bit definition for CAN_F6R2 register *******************/ 02583 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) 02584 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) 02585 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) 02586 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) 02587 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) 02588 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) 02589 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) 02590 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) 02591 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) 02592 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) 02593 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) 02594 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) 02595 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) 02596 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) 02597 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) 02598 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) 02599 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) 02600 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) 02601 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) 02602 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) 02603 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) 02604 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) 02605 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) 02606 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) 02607 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) 02608 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) 02609 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) 02610 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) 02611 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) 02612 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) 02613 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) 02614 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) 02616 /******************* Bit definition for CAN_F7R2 register *******************/ 02617 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) 02618 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) 02619 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) 02620 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) 02621 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) 02622 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) 02623 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) 02624 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) 02625 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) 02626 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) 02627 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) 02628 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) 02629 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) 02630 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) 02631 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) 02632 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) 02633 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) 02634 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) 02635 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) 02636 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) 02637 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) 02638 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) 02639 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) 02640 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) 02641 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) 02642 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) 02643 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) 02644 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) 02645 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) 02646 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) 02647 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) 02648 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) 02650 /******************* Bit definition for CAN_F8R2 register *******************/ 02651 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) 02652 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) 02653 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) 02654 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) 02655 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) 02656 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) 02657 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) 02658 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) 02659 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) 02660 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) 02661 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) 02662 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) 02663 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) 02664 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) 02665 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) 02666 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) 02667 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) 02668 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) 02669 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) 02670 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) 02671 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) 02672 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) 02673 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) 02674 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) 02675 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) 02676 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) 02677 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) 02678 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) 02679 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) 02680 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) 02681 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) 02682 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) 02684 /******************* Bit definition for CAN_F9R2 register *******************/ 02685 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) 02686 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) 02687 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) 02688 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) 02689 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) 02690 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) 02691 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) 02692 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) 02693 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) 02694 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) 02695 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) 02696 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) 02697 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) 02698 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) 02699 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) 02700 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) 02701 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) 02702 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) 02703 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) 02704 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) 02705 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) 02706 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) 02707 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) 02708 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) 02709 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) 02710 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) 02711 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) 02712 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) 02713 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) 02714 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) 02715 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) 02716 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) 02718 /******************* Bit definition for CAN_F10R2 register ******************/ 02719 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) 02720 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) 02721 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) 02722 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) 02723 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) 02724 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) 02725 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) 02726 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) 02727 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) 02728 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) 02729 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) 02730 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) 02731 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) 02732 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) 02733 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) 02734 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) 02735 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) 02736 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) 02737 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) 02738 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) 02739 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) 02740 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) 02741 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) 02742 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) 02743 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) 02744 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) 02745 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) 02746 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) 02747 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) 02748 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) 02749 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) 02750 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) 02752 /******************* Bit definition for CAN_F11R2 register ******************/ 02753 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) 02754 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) 02755 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) 02756 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) 02757 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) 02758 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) 02759 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) 02760 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) 02761 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) 02762 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) 02763 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) 02764 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) 02765 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) 02766 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) 02767 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) 02768 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) 02769 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) 02770 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) 02771 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) 02772 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) 02773 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) 02774 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) 02775 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) 02776 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) 02777 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) 02778 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) 02779 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) 02780 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) 02781 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) 02782 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) 02783 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) 02784 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) 02786 /******************* Bit definition for CAN_F12R2 register ******************/ 02787 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) 02788 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) 02789 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) 02790 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) 02791 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) 02792 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) 02793 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) 02794 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) 02795 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) 02796 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) 02797 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) 02798 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) 02799 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) 02800 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) 02801 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) 02802 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) 02803 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) 02804 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) 02805 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) 02806 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) 02807 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) 02808 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) 02809 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) 02810 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) 02811 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) 02812 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) 02813 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) 02814 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) 02815 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) 02816 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) 02817 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) 02818 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) 02820 /******************* Bit definition for CAN_F13R2 register ******************/ 02821 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) 02822 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) 02823 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) 02824 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) 02825 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) 02826 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) 02827 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) 02828 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) 02829 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) 02830 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) 02831 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) 02832 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) 02833 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) 02834 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) 02835 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) 02836 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) 02837 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) 02838 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) 02839 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) 02840 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) 02841 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) 02842 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) 02843 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) 02844 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) 02845 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) 02846 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) 02847 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) 02848 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) 02849 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) 02850 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) 02851 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) 02852 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) 02854 /******************************************************************************/ 02855 /* */ 02856 /* CRC calculation unit */ 02857 /* */ 02858 /******************************************************************************/ 02859 /******************* Bit definition for CRC_DR register *********************/ 02860 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) 02863 /******************* Bit definition for CRC_IDR register ********************/ 02864 #define CRC_IDR_IDR ((uint8_t)0xFF) 02867 /******************** Bit definition for CRC_CR register ********************/ 02868 #define CRC_CR_RESET ((uint8_t)0x01) 02870 /******************************************************************************/ 02871 /* */ 02872 /* Crypto Processor */ 02873 /* */ 02874 /******************************************************************************/ 02875 /******************* Bits definition for CRYP_CR register ********************/ 02876 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004) 02877 02878 #define CRYP_CR_ALGOMODE ((uint32_t)0x00000038) 02879 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) 02880 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) 02881 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) 02882 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) 02883 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) 02884 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) 02885 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) 02886 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) 02887 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) 02888 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) 02889 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) 02890 02891 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0) 02892 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) 02893 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) 02894 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300) 02895 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) 02896 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) 02897 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000) 02898 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000) 02899 /****************** Bits definition for CRYP_SR register *********************/ 02900 #define CRYP_SR_IFEM ((uint32_t)0x00000001) 02901 #define CRYP_SR_IFNF ((uint32_t)0x00000002) 02902 #define CRYP_SR_OFNE ((uint32_t)0x00000004) 02903 #define CRYP_SR_OFFU ((uint32_t)0x00000008) 02904 #define CRYP_SR_BUSY ((uint32_t)0x00000010) 02905 /****************** Bits definition for CRYP_DMACR register ******************/ 02906 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001) 02907 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002) 02908 /***************** Bits definition for CRYP_IMSCR register ******************/ 02909 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001) 02910 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) 02911 /****************** Bits definition for CRYP_RISR register *******************/ 02912 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001) 02913 #define CRYP_RISR_INRIS ((uint32_t)0x00000002) 02914 /****************** Bits definition for CRYP_MISR register *******************/ 02915 #define CRYP_MISR_INMIS ((uint32_t)0x00000001) 02916 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002) 02917 02918 /******************************************************************************/ 02919 /* */ 02920 /* Digital to Analog Converter */ 02921 /* */ 02922 /******************************************************************************/ 02923 /******************** Bit definition for DAC_CR register ********************/ 02924 #define DAC_CR_EN1 ((uint32_t)0x00000001) 02925 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) 02926 #define DAC_CR_TEN1 ((uint32_t)0x00000004) 02928 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) 02929 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) 02930 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) 02931 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) 02933 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) 02934 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) 02935 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) 02937 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) 02938 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) 02939 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) 02940 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) 02941 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) 02943 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) 02944 #define DAC_CR_EN2 ((uint32_t)0x00010000) 02945 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) 02946 #define DAC_CR_TEN2 ((uint32_t)0x00040000) 02948 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) 02949 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) 02950 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) 02951 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) 02953 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) 02954 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) 02955 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) 02957 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) 02958 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) 02959 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) 02960 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) 02961 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) 02963 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) 02965 /***************** Bit definition for DAC_SWTRIGR register ******************/ 02966 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) 02967 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) 02969 /***************** Bit definition for DAC_DHR12R1 register ******************/ 02970 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) 02972 /***************** Bit definition for DAC_DHR12L1 register ******************/ 02973 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) 02975 /****************** Bit definition for DAC_DHR8R1 register ******************/ 02976 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) 02978 /***************** Bit definition for DAC_DHR12R2 register ******************/ 02979 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) 02981 /***************** Bit definition for DAC_DHR12L2 register ******************/ 02982 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) 02984 /****************** Bit definition for DAC_DHR8R2 register ******************/ 02985 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) 02987 /***************** Bit definition for DAC_DHR12RD register ******************/ 02988 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) 02989 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) 02991 /***************** Bit definition for DAC_DHR12LD register ******************/ 02992 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) 02993 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) 02995 /****************** Bit definition for DAC_DHR8RD register ******************/ 02996 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) 02997 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) 02999 /******************* Bit definition for DAC_DOR1 register *******************/ 03000 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) 03002 /******************* Bit definition for DAC_DOR2 register *******************/ 03003 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) 03005 /******************** Bit definition for DAC_SR register ********************/ 03006 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) 03007 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) 03009 /******************************************************************************/ 03010 /* */ 03011 /* Debug MCU */ 03012 /* */ 03013 /******************************************************************************/ 03014 03015 /******************************************************************************/ 03016 /* */ 03017 /* DCMI */ 03018 /* */ 03019 /******************************************************************************/ 03020 /******************** Bits definition for DCMI_CR register ******************/ 03021 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) 03022 #define DCMI_CR_CM ((uint32_t)0x00000002) 03023 #define DCMI_CR_CROP ((uint32_t)0x00000004) 03024 #define DCMI_CR_JPEG ((uint32_t)0x00000008) 03025 #define DCMI_CR_ESS ((uint32_t)0x00000010) 03026 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) 03027 #define DCMI_CR_HSPOL ((uint32_t)0x00000040) 03028 #define DCMI_CR_VSPOL ((uint32_t)0x00000080) 03029 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) 03030 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) 03031 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) 03032 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) 03033 #define DCMI_CR_CRE ((uint32_t)0x00001000) 03034 #define DCMI_CR_ENABLE ((uint32_t)0x00004000) 03035 03036 /******************** Bits definition for DCMI_SR register ******************/ 03037 #define DCMI_SR_HSYNC ((uint32_t)0x00000001) 03038 #define DCMI_SR_VSYNC ((uint32_t)0x00000002) 03039 #define DCMI_SR_FNE ((uint32_t)0x00000004) 03040 03041 /******************** Bits definition for DCMI_RISR register ****************/ 03042 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) 03043 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) 03044 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) 03045 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) 03046 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) 03047 03048 /******************** Bits definition for DCMI_IER register *****************/ 03049 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) 03050 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002) 03051 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) 03052 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) 03053 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) 03054 03055 /******************** Bits definition for DCMI_MISR register ****************/ 03056 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) 03057 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) 03058 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) 03059 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) 03060 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) 03061 03062 /******************** Bits definition for DCMI_ICR register *****************/ 03063 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) 03064 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) 03065 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) 03066 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) 03067 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) 03068 03069 /******************************************************************************/ 03070 /* */ 03071 /* DMA Controller */ 03072 /* */ 03073 /******************************************************************************/ 03074 /******************** Bits definition for DMA_SxCR register *****************/ 03075 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) 03076 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) 03077 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) 03078 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) 03079 #define DMA_SxCR_MBURST ((uint32_t)0x01800000) 03080 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) 03081 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) 03082 #define DMA_SxCR_PBURST ((uint32_t)0x00600000) 03083 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) 03084 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) 03085 #define DMA_SxCR_ACK ((uint32_t)0x00100000) 03086 #define DMA_SxCR_CT ((uint32_t)0x00080000) 03087 #define DMA_SxCR_DBM ((uint32_t)0x00040000) 03088 #define DMA_SxCR_PL ((uint32_t)0x00030000) 03089 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000) 03090 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000) 03091 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000) 03092 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000) 03093 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) 03094 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) 03095 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800) 03096 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) 03097 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) 03098 #define DMA_SxCR_MINC ((uint32_t)0x00000400) 03099 #define DMA_SxCR_PINC ((uint32_t)0x00000200) 03100 #define DMA_SxCR_CIRC ((uint32_t)0x00000100) 03101 #define DMA_SxCR_DIR ((uint32_t)0x000000C0) 03102 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) 03103 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) 03104 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) 03105 #define DMA_SxCR_TCIE ((uint32_t)0x00000010) 03106 #define DMA_SxCR_HTIE ((uint32_t)0x00000008) 03107 #define DMA_SxCR_TEIE ((uint32_t)0x00000004) 03108 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002) 03109 #define DMA_SxCR_EN ((uint32_t)0x00000001) 03110 03111 /******************** Bits definition for DMA_SxCNDTR register **************/ 03112 #define DMA_SxNDT ((uint32_t)0x0000FFFF) 03113 #define DMA_SxNDT_0 ((uint32_t)0x00000001) 03114 #define DMA_SxNDT_1 ((uint32_t)0x00000002) 03115 #define DMA_SxNDT_2 ((uint32_t)0x00000004) 03116 #define DMA_SxNDT_3 ((uint32_t)0x00000008) 03117 #define DMA_SxNDT_4 ((uint32_t)0x00000010) 03118 #define DMA_SxNDT_5 ((uint32_t)0x00000020) 03119 #define DMA_SxNDT_6 ((uint32_t)0x00000040) 03120 #define DMA_SxNDT_7 ((uint32_t)0x00000080) 03121 #define DMA_SxNDT_8 ((uint32_t)0x00000100) 03122 #define DMA_SxNDT_9 ((uint32_t)0x00000200) 03123 #define DMA_SxNDT_10 ((uint32_t)0x00000400) 03124 #define DMA_SxNDT_11 ((uint32_t)0x00000800) 03125 #define DMA_SxNDT_12 ((uint32_t)0x00001000) 03126 #define DMA_SxNDT_13 ((uint32_t)0x00002000) 03127 #define DMA_SxNDT_14 ((uint32_t)0x00004000) 03128 #define DMA_SxNDT_15 ((uint32_t)0x00008000) 03129 03130 /******************** Bits definition for DMA_SxFCR register ****************/ 03131 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080) 03132 #define DMA_SxFCR_FS ((uint32_t)0x00000038) 03133 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) 03134 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) 03135 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) 03136 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) 03137 #define DMA_SxFCR_FTH ((uint32_t)0x00000003) 03138 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) 03139 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) 03140 03141 /******************** Bits definition for DMA_LISR register *****************/ 03142 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000) 03143 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000) 03144 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000) 03145 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) 03146 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000) 03147 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000) 03148 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000) 03149 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000) 03150 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) 03151 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000) 03152 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800) 03153 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400) 03154 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200) 03155 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) 03156 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040) 03157 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020) 03158 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010) 03159 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008) 03160 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) 03161 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001) 03162 03163 /******************** Bits definition for DMA_HISR register *****************/ 03164 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000) 03165 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000) 03166 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000) 03167 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) 03168 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000) 03169 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000) 03170 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000) 03171 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000) 03172 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) 03173 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000) 03174 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800) 03175 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400) 03176 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200) 03177 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) 03178 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040) 03179 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020) 03180 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010) 03181 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008) 03182 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) 03183 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001) 03184 03185 /******************** Bits definition for DMA_LIFCR register ****************/ 03186 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) 03187 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) 03188 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) 03189 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) 03190 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) 03191 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) 03192 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) 03193 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) 03194 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) 03195 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) 03196 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) 03197 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) 03198 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) 03199 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) 03200 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) 03201 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) 03202 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) 03203 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) 03204 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) 03205 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) 03206 03207 /******************** Bits definition for DMA_HIFCR register ****************/ 03208 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) 03209 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) 03210 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) 03211 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) 03212 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) 03213 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) 03214 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) 03215 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) 03216 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) 03217 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) 03218 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) 03219 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) 03220 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) 03221 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) 03222 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) 03223 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) 03224 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) 03225 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) 03226 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) 03227 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) 03228 03229 /******************************************************************************/ 03230 /* */ 03231 /* External Interrupt/Event Controller */ 03232 /* */ 03233 /******************************************************************************/ 03234 /******************* Bit definition for EXTI_IMR register *******************/ 03235 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) 03236 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) 03237 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) 03238 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) 03239 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) 03240 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) 03241 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) 03242 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) 03243 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) 03244 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) 03245 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) 03246 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) 03247 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) 03248 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) 03249 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) 03250 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) 03251 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) 03252 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) 03253 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) 03254 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) 03256 /******************* Bit definition for EXTI_EMR register *******************/ 03257 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) 03258 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) 03259 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) 03260 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) 03261 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) 03262 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) 03263 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) 03264 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) 03265 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) 03266 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) 03267 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) 03268 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) 03269 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) 03270 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) 03271 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) 03272 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) 03273 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) 03274 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) 03275 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) 03276 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) 03278 /****************** Bit definition for EXTI_RTSR register *******************/ 03279 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) 03280 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) 03281 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) 03282 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) 03283 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) 03284 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) 03285 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) 03286 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) 03287 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) 03288 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) 03289 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) 03290 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) 03291 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) 03292 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) 03293 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) 03294 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) 03295 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) 03296 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) 03297 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) 03298 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) 03300 /****************** Bit definition for EXTI_FTSR register *******************/ 03301 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) 03302 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) 03303 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) 03304 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) 03305 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) 03306 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) 03307 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) 03308 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) 03309 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) 03310 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) 03311 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) 03312 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) 03313 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) 03314 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) 03315 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) 03316 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) 03317 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) 03318 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) 03319 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) 03320 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) 03322 /****************** Bit definition for EXTI_SWIER register ******************/ 03323 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) 03324 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) 03325 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) 03326 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) 03327 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) 03328 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) 03329 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) 03330 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) 03331 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) 03332 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) 03333 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) 03334 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) 03335 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) 03336 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) 03337 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) 03338 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) 03339 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) 03340 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) 03341 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) 03342 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) 03344 /******************* Bit definition for EXTI_PR register ********************/ 03345 #define EXTI_PR_PR0 ((uint32_t)0x00000001) 03346 #define EXTI_PR_PR1 ((uint32_t)0x00000002) 03347 #define EXTI_PR_PR2 ((uint32_t)0x00000004) 03348 #define EXTI_PR_PR3 ((uint32_t)0x00000008) 03349 #define EXTI_PR_PR4 ((uint32_t)0x00000010) 03350 #define EXTI_PR_PR5 ((uint32_t)0x00000020) 03351 #define EXTI_PR_PR6 ((uint32_t)0x00000040) 03352 #define EXTI_PR_PR7 ((uint32_t)0x00000080) 03353 #define EXTI_PR_PR8 ((uint32_t)0x00000100) 03354 #define EXTI_PR_PR9 ((uint32_t)0x00000200) 03355 #define EXTI_PR_PR10 ((uint32_t)0x00000400) 03356 #define EXTI_PR_PR11 ((uint32_t)0x00000800) 03357 #define EXTI_PR_PR12 ((uint32_t)0x00001000) 03358 #define EXTI_PR_PR13 ((uint32_t)0x00002000) 03359 #define EXTI_PR_PR14 ((uint32_t)0x00004000) 03360 #define EXTI_PR_PR15 ((uint32_t)0x00008000) 03361 #define EXTI_PR_PR16 ((uint32_t)0x00010000) 03362 #define EXTI_PR_PR17 ((uint32_t)0x00020000) 03363 #define EXTI_PR_PR18 ((uint32_t)0x00040000) 03364 #define EXTI_PR_PR19 ((uint32_t)0x00080000) 03366 /******************************************************************************/ 03367 /* */ 03368 /* FLASH */ 03369 /* */ 03370 /******************************************************************************/ 03371 /******************* Bits definition for FLASH_ACR register *****************/ 03372 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) 03373 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) 03374 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) 03375 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) 03376 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) 03377 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) 03378 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) 03379 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) 03380 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) 03381 03382 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) 03383 #define FLASH_ACR_ICEN ((uint32_t)0x00000200) 03384 #define FLASH_ACR_DCEN ((uint32_t)0x00000400) 03385 #define FLASH_ACR_ICRST ((uint32_t)0x00000800) 03386 #define FLASH_ACR_DCRST ((uint32_t)0x00001000) 03387 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) 03388 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) 03389 03390 /******************* Bits definition for FLASH_SR register ******************/ 03391 #define FLASH_SR_EOP ((uint32_t)0x00000001) 03392 #define FLASH_SR_SOP ((uint32_t)0x00000002) 03393 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) 03394 #define FLASH_SR_PGAERR ((uint32_t)0x00000020) 03395 #define FLASH_SR_PGPERR ((uint32_t)0x00000040) 03396 #define FLASH_SR_PGSERR ((uint32_t)0x00000080) 03397 #define FLASH_SR_BSY ((uint32_t)0x00010000) 03398 03399 /******************* Bits definition for FLASH_CR register ******************/ 03400 #define FLASH_CR_PG ((uint32_t)0x00000001) 03401 #define FLASH_CR_SER ((uint32_t)0x00000002) 03402 #define FLASH_CR_MER ((uint32_t)0x00000004) 03403 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008) 03404 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010) 03405 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020) 03406 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040) 03407 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) 03408 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) 03409 #define FLASH_CR_STRT ((uint32_t)0x00010000) 03410 #define FLASH_CR_EOPIE ((uint32_t)0x01000000) 03411 #define FLASH_CR_LOCK ((uint32_t)0x80000000) 03412 03413 /******************* Bits definition for FLASH_OPTCR register ***************/ 03414 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) 03415 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) 03416 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) 03417 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) 03418 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) 03419 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) 03420 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) 03421 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) 03422 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) 03423 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) 03424 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) 03425 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) 03426 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) 03427 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) 03428 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) 03429 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) 03430 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) 03431 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) 03432 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) 03433 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) 03434 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) 03435 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) 03436 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) 03437 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) 03438 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) 03439 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) 03440 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) 03441 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) 03442 03443 /******************************************************************************/ 03444 /* */ 03445 /* Flexible Static Memory Controller */ 03446 /* */ 03447 /******************************************************************************/ 03448 /****************** Bit definition for FSMC_BCR1 register *******************/ 03449 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) 03450 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) 03452 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) 03453 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) 03454 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) 03456 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) 03457 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) 03458 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) 03460 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) 03461 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) 03462 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) 03463 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) 03464 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) 03465 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) 03466 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) 03467 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) 03468 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) 03469 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) 03471 /****************** Bit definition for FSMC_BCR2 register *******************/ 03472 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) 03473 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) 03475 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) 03476 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) 03477 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) 03479 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) 03480 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) 03481 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) 03483 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) 03484 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) 03485 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) 03486 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) 03487 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) 03488 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) 03489 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) 03490 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) 03491 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) 03492 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) 03494 /****************** Bit definition for FSMC_BCR3 register *******************/ 03495 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) 03496 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) 03498 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) 03499 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) 03500 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) 03502 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) 03503 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) 03504 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) 03506 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) 03507 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) 03508 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) 03509 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) 03510 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) 03511 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) 03512 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) 03513 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) 03514 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) 03515 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) 03517 /****************** Bit definition for FSMC_BCR4 register *******************/ 03518 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) 03519 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) 03521 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) 03522 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) 03523 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) 03525 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) 03526 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) 03527 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) 03529 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) 03530 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) 03531 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) 03532 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) 03533 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) 03534 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) 03535 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) 03536 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) 03537 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) 03538 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) 03540 /****************** Bit definition for FSMC_BTR1 register ******************/ 03541 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) 03542 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) 03543 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) 03544 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) 03545 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) 03547 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) 03548 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) 03549 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) 03550 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) 03551 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) 03553 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) 03554 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) 03555 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) 03556 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) 03557 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) 03559 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) 03560 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) 03561 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) 03562 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) 03563 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) 03565 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) 03566 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) 03567 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) 03568 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) 03569 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) 03571 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) 03572 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) 03573 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) 03574 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) 03575 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) 03577 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) 03578 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) 03579 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) 03581 /****************** Bit definition for FSMC_BTR2 register *******************/ 03582 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) 03583 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) 03584 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) 03585 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) 03586 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) 03588 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) 03589 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) 03590 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) 03591 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) 03592 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) 03594 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) 03595 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) 03596 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) 03597 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) 03598 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) 03600 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) 03601 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) 03602 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) 03603 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) 03604 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) 03606 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) 03607 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) 03608 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) 03609 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) 03610 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) 03612 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) 03613 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) 03614 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) 03615 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) 03616 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) 03618 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) 03619 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) 03620 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) 03622 /******************* Bit definition for FSMC_BTR3 register *******************/ 03623 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) 03624 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) 03625 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) 03626 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) 03627 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) 03629 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) 03630 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) 03631 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) 03632 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) 03633 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) 03635 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) 03636 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) 03637 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) 03638 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) 03639 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) 03641 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) 03642 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) 03643 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) 03644 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) 03645 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) 03647 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) 03648 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) 03649 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) 03650 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) 03651 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) 03653 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) 03654 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) 03655 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) 03656 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) 03657 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) 03659 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) 03660 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) 03661 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) 03663 /****************** Bit definition for FSMC_BTR4 register *******************/ 03664 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) 03665 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) 03666 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) 03667 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) 03668 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) 03670 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) 03671 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) 03672 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) 03673 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) 03674 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) 03676 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) 03677 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) 03678 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) 03679 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) 03680 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) 03682 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) 03683 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) 03684 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) 03685 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) 03686 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) 03688 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) 03689 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) 03690 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) 03691 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) 03692 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) 03694 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) 03695 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) 03696 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) 03697 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) 03698 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) 03700 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) 03701 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) 03702 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) 03704 /****************** Bit definition for FSMC_BWTR1 register ******************/ 03705 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) 03706 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) 03707 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) 03708 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) 03709 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) 03711 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) 03712 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) 03713 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) 03714 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) 03715 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) 03717 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) 03718 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) 03719 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) 03720 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) 03721 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) 03723 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) 03724 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) 03725 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) 03726 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) 03727 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) 03729 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) 03730 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) 03731 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) 03732 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) 03733 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) 03735 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) 03736 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) 03737 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) 03739 /****************** Bit definition for FSMC_BWTR2 register ******************/ 03740 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) 03741 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) 03742 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) 03743 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) 03744 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) 03746 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) 03747 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) 03748 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) 03749 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) 03750 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) 03752 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) 03753 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) 03754 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) 03755 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) 03756 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) 03758 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) 03759 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) 03760 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) 03761 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) 03762 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) 03764 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) 03765 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) 03766 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) 03767 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) 03768 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) 03770 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) 03771 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) 03772 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) 03774 /****************** Bit definition for FSMC_BWTR3 register ******************/ 03775 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) 03776 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) 03777 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) 03778 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) 03779 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) 03781 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) 03782 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) 03783 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) 03784 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) 03785 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) 03787 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) 03788 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) 03789 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) 03790 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) 03791 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) 03793 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) 03794 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) 03795 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) 03796 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) 03797 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) 03799 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) 03800 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) 03801 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) 03802 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) 03803 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) 03805 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) 03806 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) 03807 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) 03809 /****************** Bit definition for FSMC_BWTR4 register ******************/ 03810 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) 03811 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) 03812 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) 03813 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) 03814 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) 03816 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) 03817 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) 03818 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) 03819 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) 03820 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) 03822 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) 03823 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) 03824 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) 03825 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) 03826 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) 03828 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) 03829 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) 03830 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) 03831 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) 03832 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) 03834 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 03835 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 03836 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 03837 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 03838 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) 03840 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 03841 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 03842 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 03844 /****************** Bit definition for FSMC_PCR2 register *******************/ 03845 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) 03846 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) 03847 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) 03849 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) 03850 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) 03851 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) 03853 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) 03855 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 03856 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 03857 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 03858 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 03859 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) 03861 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) 03862 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 03863 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 03864 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 03865 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 03867 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) 03868 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) 03869 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) 03870 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) 03872 /****************** Bit definition for FSMC_PCR3 register *******************/ 03873 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) 03874 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) 03875 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) 03877 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) 03878 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) 03879 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) 03881 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) 03883 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) 03884 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) 03885 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) 03886 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) 03887 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) 03889 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) 03890 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) 03891 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) 03892 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) 03893 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) 03895 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) 03896 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) 03897 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) 03898 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) 03900 /****************** Bit definition for FSMC_PCR4 register *******************/ 03901 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) 03902 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) 03903 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) 03905 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) 03906 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) 03907 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) 03909 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) 03911 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) 03912 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) 03913 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) 03914 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) 03915 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) 03917 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) 03918 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) 03919 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) 03920 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) 03921 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) 03923 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) 03924 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) 03925 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) 03926 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) 03928 /******************* Bit definition for FSMC_SR2 register *******************/ 03929 #define FSMC_SR2_IRS ((uint8_t)0x01) 03930 #define FSMC_SR2_ILS ((uint8_t)0x02) 03931 #define FSMC_SR2_IFS ((uint8_t)0x04) 03932 #define FSMC_SR2_IREN ((uint8_t)0x08) 03933 #define FSMC_SR2_ILEN ((uint8_t)0x10) 03934 #define FSMC_SR2_IFEN ((uint8_t)0x20) 03935 #define FSMC_SR2_FEMPT ((uint8_t)0x40) 03937 /******************* Bit definition for FSMC_SR3 register *******************/ 03938 #define FSMC_SR3_IRS ((uint8_t)0x01) 03939 #define FSMC_SR3_ILS ((uint8_t)0x02) 03940 #define FSMC_SR3_IFS ((uint8_t)0x04) 03941 #define FSMC_SR3_IREN ((uint8_t)0x08) 03942 #define FSMC_SR3_ILEN ((uint8_t)0x10) 03943 #define FSMC_SR3_IFEN ((uint8_t)0x20) 03944 #define FSMC_SR3_FEMPT ((uint8_t)0x40) 03946 /******************* Bit definition for FSMC_SR4 register *******************/ 03947 #define FSMC_SR4_IRS ((uint8_t)0x01) 03948 #define FSMC_SR4_ILS ((uint8_t)0x02) 03949 #define FSMC_SR4_IFS ((uint8_t)0x04) 03950 #define FSMC_SR4_IREN ((uint8_t)0x08) 03951 #define FSMC_SR4_ILEN ((uint8_t)0x10) 03952 #define FSMC_SR4_IFEN ((uint8_t)0x20) 03953 #define FSMC_SR4_FEMPT ((uint8_t)0x40) 03955 /****************** Bit definition for FSMC_PMEM2 register ******************/ 03956 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) 03957 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) 03958 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) 03959 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) 03960 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) 03961 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) 03962 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) 03963 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) 03964 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) 03966 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) 03967 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) 03968 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) 03969 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) 03970 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) 03971 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) 03972 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) 03973 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) 03974 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) 03976 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) 03977 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) 03978 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) 03979 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) 03980 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) 03981 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) 03982 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) 03983 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) 03984 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) 03986 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) 03987 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) 03988 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) 03989 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) 03990 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) 03991 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) 03992 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) 03993 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) 03994 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) 03996 /****************** Bit definition for FSMC_PMEM3 register ******************/ 03997 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) 03998 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) 03999 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) 04000 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) 04001 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) 04002 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) 04003 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) 04004 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) 04005 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) 04007 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) 04008 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) 04009 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) 04010 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) 04011 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) 04012 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) 04013 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) 04014 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) 04015 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) 04017 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) 04018 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) 04019 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) 04020 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) 04021 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) 04022 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) 04023 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) 04024 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) 04025 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) 04027 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) 04028 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) 04029 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) 04030 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) 04031 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) 04032 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) 04033 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) 04034 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) 04035 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) 04037 /****************** Bit definition for FSMC_PMEM4 register ******************/ 04038 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) 04039 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) 04040 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) 04041 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) 04042 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) 04043 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) 04044 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) 04045 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) 04046 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) 04048 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) 04049 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) 04050 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) 04051 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) 04052 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) 04053 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) 04054 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) 04055 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) 04056 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) 04058 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) 04059 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) 04060 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) 04061 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) 04062 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) 04063 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) 04064 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) 04065 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) 04066 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) 04068 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) 04069 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) 04070 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) 04071 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) 04072 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) 04073 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) 04074 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) 04075 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) 04076 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) 04078 /****************** Bit definition for FSMC_PATT2 register ******************/ 04079 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) 04080 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) 04081 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) 04082 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) 04083 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) 04084 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) 04085 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) 04086 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) 04087 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) 04089 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) 04090 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) 04091 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) 04092 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) 04093 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) 04094 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) 04095 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) 04096 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) 04097 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) 04099 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) 04100 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) 04101 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) 04102 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) 04103 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) 04104 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) 04105 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) 04106 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) 04107 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) 04109 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) 04110 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) 04111 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) 04112 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) 04113 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) 04114 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) 04115 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) 04116 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) 04117 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) 04119 /****************** Bit definition for FSMC_PATT3 register ******************/ 04120 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) 04121 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) 04122 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) 04123 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) 04124 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) 04125 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) 04126 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) 04127 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) 04128 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) 04130 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) 04131 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) 04132 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) 04133 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) 04134 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) 04135 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) 04136 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) 04137 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) 04138 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) 04140 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) 04141 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) 04142 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) 04143 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) 04144 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) 04145 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) 04146 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) 04147 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) 04148 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) 04150 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) 04151 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) 04152 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) 04153 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) 04154 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) 04155 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) 04156 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) 04157 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) 04158 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) 04160 /****************** Bit definition for FSMC_PATT4 register ******************/ 04161 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) 04162 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) 04163 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) 04164 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) 04165 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) 04166 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) 04167 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) 04168 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) 04169 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) 04171 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) 04172 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) 04173 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) 04174 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) 04175 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) 04176 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) 04177 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) 04178 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) 04179 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) 04181 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) 04182 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) 04183 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) 04184 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) 04185 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) 04186 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) 04187 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) 04188 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) 04189 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) 04191 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) 04192 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) 04193 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) 04194 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) 04195 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) 04196 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) 04197 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) 04198 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) 04199 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) 04201 /****************** Bit definition for FSMC_PIO4 register *******************/ 04202 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) 04203 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) 04204 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) 04205 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) 04206 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) 04207 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) 04208 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) 04209 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) 04210 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) 04212 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) 04213 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) 04214 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) 04215 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) 04216 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) 04217 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) 04218 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) 04219 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) 04220 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) 04222 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) 04223 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) 04224 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) 04225 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) 04226 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) 04227 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) 04228 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) 04229 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) 04230 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) 04232 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) 04233 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) 04234 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) 04235 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) 04236 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) 04237 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) 04238 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) 04239 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) 04240 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) 04242 /****************** Bit definition for FSMC_ECCR2 register ******************/ 04243 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) 04245 /****************** Bit definition for FSMC_ECCR3 register ******************/ 04246 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) 04248 /******************************************************************************/ 04249 /* */ 04250 /* General Purpose I/O */ 04251 /* */ 04252 /******************************************************************************/ 04253 /****************** Bits definition for GPIO_MODER register *****************/ 04254 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) 04255 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) 04256 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) 04257 04258 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) 04259 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) 04260 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) 04261 04262 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) 04263 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) 04264 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) 04265 04266 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) 04267 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) 04268 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) 04269 04270 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) 04271 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) 04272 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) 04273 04274 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) 04275 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) 04276 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) 04277 04278 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) 04279 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) 04280 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) 04281 04282 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) 04283 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) 04284 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) 04285 04286 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) 04287 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) 04288 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) 04289 04290 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) 04291 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) 04292 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) 04293 04294 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) 04295 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) 04296 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) 04297 04298 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) 04299 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) 04300 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) 04301 04302 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) 04303 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) 04304 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) 04305 04306 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) 04307 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) 04308 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) 04309 04310 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) 04311 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) 04312 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) 04313 04314 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) 04315 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) 04316 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) 04317 04318 /****************** Bits definition for GPIO_OTYPER register ****************/ 04319 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) 04320 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) 04321 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) 04322 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) 04323 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) 04324 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) 04325 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) 04326 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) 04327 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) 04328 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) 04329 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) 04330 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) 04331 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) 04332 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) 04333 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) 04334 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) 04335 04336 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 04337 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) 04338 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) 04339 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) 04340 04341 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) 04342 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) 04343 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) 04344 04345 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) 04346 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) 04347 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) 04348 04349 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) 04350 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) 04351 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) 04352 04353 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) 04354 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) 04355 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) 04356 04357 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) 04358 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) 04359 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) 04360 04361 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) 04362 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) 04363 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) 04364 04365 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) 04366 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) 04367 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) 04368 04369 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) 04370 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) 04371 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) 04372 04373 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) 04374 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) 04375 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) 04376 04377 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) 04378 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) 04379 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) 04380 04381 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) 04382 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) 04383 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) 04384 04385 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) 04386 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) 04387 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) 04388 04389 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) 04390 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) 04391 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) 04392 04393 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) 04394 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) 04395 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) 04396 04397 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) 04398 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) 04399 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) 04400 04401 /****************** Bits definition for GPIO_PUPDR register *****************/ 04402 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) 04403 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) 04404 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) 04405 04406 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) 04407 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) 04408 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) 04409 04410 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) 04411 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) 04412 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) 04413 04414 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) 04415 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) 04416 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) 04417 04418 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) 04419 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) 04420 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) 04421 04422 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) 04423 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) 04424 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) 04425 04426 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) 04427 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) 04428 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) 04429 04430 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) 04431 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) 04432 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) 04433 04434 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) 04435 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) 04436 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) 04437 04438 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) 04439 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) 04440 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) 04441 04442 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) 04443 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) 04444 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) 04445 04446 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) 04447 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) 04448 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) 04449 04450 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) 04451 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) 04452 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) 04453 04454 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) 04455 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) 04456 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) 04457 04458 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) 04459 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) 04460 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) 04461 04462 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) 04463 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) 04464 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) 04465 04466 /****************** Bits definition for GPIO_IDR register *******************/ 04467 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001) 04468 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002) 04469 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004) 04470 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008) 04471 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010) 04472 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020) 04473 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040) 04474 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080) 04475 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100) 04476 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200) 04477 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400) 04478 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800) 04479 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000) 04480 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000) 04481 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000) 04482 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000) 04483 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */ 04484 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0 04485 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1 04486 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2 04487 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3 04488 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4 04489 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5 04490 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6 04491 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7 04492 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8 04493 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9 04494 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10 04495 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11 04496 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12 04497 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13 04498 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14 04499 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15 04500 04501 /****************** Bits definition for GPIO_ODR register *******************/ 04502 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001) 04503 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002) 04504 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004) 04505 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008) 04506 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010) 04507 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020) 04508 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040) 04509 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080) 04510 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100) 04511 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200) 04512 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400) 04513 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800) 04514 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000) 04515 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000) 04516 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000) 04517 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000) 04518 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */ 04519 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0 04520 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1 04521 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2 04522 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3 04523 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4 04524 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5 04525 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6 04526 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7 04527 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8 04528 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9 04529 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10 04530 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11 04531 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12 04532 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13 04533 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14 04534 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15 04535 04536 /****************** Bits definition for GPIO_BSRR register ******************/ 04537 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) 04538 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) 04539 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) 04540 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) 04541 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) 04542 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) 04543 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) 04544 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) 04545 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) 04546 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) 04547 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) 04548 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) 04549 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) 04550 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) 04551 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) 04552 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) 04553 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) 04554 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) 04555 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) 04556 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) 04557 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) 04558 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) 04559 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) 04560 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) 04561 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) 04562 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) 04563 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) 04564 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) 04565 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) 04566 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) 04567 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) 04568 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) 04569 04570 /******************************************************************************/ 04571 /* */ 04572 /* HASH */ 04573 /* */ 04574 /******************************************************************************/ 04575 /****************** Bits definition for HASH_CR register ********************/ 04576 #define HASH_CR_INIT ((uint32_t)0x00000004) 04577 #define HASH_CR_DMAE ((uint32_t)0x00000008) 04578 #define HASH_CR_DATATYPE ((uint32_t)0x00000030) 04579 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) 04580 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) 04581 #define HASH_CR_MODE ((uint32_t)0x00000040) 04582 #define HASH_CR_ALGO ((uint32_t)0x00000080) 04583 #define HASH_CR_NBW ((uint32_t)0x00000F00) 04584 #define HASH_CR_NBW_0 ((uint32_t)0x00000100) 04585 #define HASH_CR_NBW_1 ((uint32_t)0x00000200) 04586 #define HASH_CR_NBW_2 ((uint32_t)0x00000400) 04587 #define HASH_CR_NBW_3 ((uint32_t)0x00000800) 04588 #define HASH_CR_DINNE ((uint32_t)0x00001000) 04589 #define HASH_CR_LKEY ((uint32_t)0x00010000) 04590 04591 /****************** Bits definition for HASH_STR register *******************/ 04592 #define HASH_STR_NBW ((uint32_t)0x0000001F) 04593 #define HASH_STR_NBW_0 ((uint32_t)0x00000001) 04594 #define HASH_STR_NBW_1 ((uint32_t)0x00000002) 04595 #define HASH_STR_NBW_2 ((uint32_t)0x00000004) 04596 #define HASH_STR_NBW_3 ((uint32_t)0x00000008) 04597 #define HASH_STR_NBW_4 ((uint32_t)0x00000010) 04598 #define HASH_STR_DCAL ((uint32_t)0x00000100) 04599 04600 /****************** Bits definition for HASH_IMR register *******************/ 04601 #define HASH_IMR_DINIM ((uint32_t)0x00000001) 04602 #define HASH_IMR_DCIM ((uint32_t)0x00000002) 04603 04604 /****************** Bits definition for HASH_SR register ********************/ 04605 #define HASH_SR_DINIS ((uint32_t)0x00000001) 04606 #define HASH_SR_DCIS ((uint32_t)0x00000002) 04607 #define HASH_SR_DMAS ((uint32_t)0x00000004) 04608 #define HASH_SR_BUSY ((uint32_t)0x00000008) 04609 04610 /******************************************************************************/ 04611 /* */ 04612 /* Inter-integrated Circuit Interface */ 04613 /* */ 04614 /******************************************************************************/ 04615 /******************* Bit definition for I2C_CR1 register ********************/ 04616 #define I2C_CR1_PE ((uint16_t)0x0001) 04617 #define I2C_CR1_SMBUS ((uint16_t)0x0002) 04618 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) 04619 #define I2C_CR1_ENARP ((uint16_t)0x0010) 04620 #define I2C_CR1_ENPEC ((uint16_t)0x0020) 04621 #define I2C_CR1_ENGC ((uint16_t)0x0040) 04622 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) 04623 #define I2C_CR1_START ((uint16_t)0x0100) 04624 #define I2C_CR1_STOP ((uint16_t)0x0200) 04625 #define I2C_CR1_ACK ((uint16_t)0x0400) 04626 #define I2C_CR1_POS ((uint16_t)0x0800) 04627 #define I2C_CR1_PEC ((uint16_t)0x1000) 04628 #define I2C_CR1_ALERT ((uint16_t)0x2000) 04629 #define I2C_CR1_SWRST ((uint16_t)0x8000) 04631 /******************* Bit definition for I2C_CR2 register ********************/ 04632 #define I2C_CR2_FREQ ((uint16_t)0x003F) 04633 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) 04634 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) 04635 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) 04636 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) 04637 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) 04638 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) 04640 #define I2C_CR2_ITERREN ((uint16_t)0x0100) 04641 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) 04642 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) 04643 #define I2C_CR2_DMAEN ((uint16_t)0x0800) 04644 #define I2C_CR2_LAST ((uint16_t)0x1000) 04646 /******************* Bit definition for I2C_OAR1 register *******************/ 04647 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) 04648 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) 04650 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) 04651 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) 04652 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) 04653 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) 04654 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) 04655 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) 04656 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) 04657 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) 04658 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) 04659 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) 04661 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) 04663 /******************* Bit definition for I2C_OAR2 register *******************/ 04664 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) 04665 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) 04667 /******************** Bit definition for I2C_DR register ********************/ 04668 #define I2C_DR_DR ((uint8_t)0xFF) 04670 /******************* Bit definition for I2C_SR1 register ********************/ 04671 #define I2C_SR1_SB ((uint16_t)0x0001) 04672 #define I2C_SR1_ADDR ((uint16_t)0x0002) 04673 #define I2C_SR1_BTF ((uint16_t)0x0004) 04674 #define I2C_SR1_ADD10 ((uint16_t)0x0008) 04675 #define I2C_SR1_STOPF ((uint16_t)0x0010) 04676 #define I2C_SR1_RXNE ((uint16_t)0x0040) 04677 #define I2C_SR1_TXE ((uint16_t)0x0080) 04678 #define I2C_SR1_BERR ((uint16_t)0x0100) 04679 #define I2C_SR1_ARLO ((uint16_t)0x0200) 04680 #define I2C_SR1_AF ((uint16_t)0x0400) 04681 #define I2C_SR1_OVR ((uint16_t)0x0800) 04682 #define I2C_SR1_PECERR ((uint16_t)0x1000) 04683 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) 04684 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) 04686 /******************* Bit definition for I2C_SR2 register ********************/ 04687 #define I2C_SR2_MSL ((uint16_t)0x0001) 04688 #define I2C_SR2_BUSY ((uint16_t)0x0002) 04689 #define I2C_SR2_TRA ((uint16_t)0x0004) 04690 #define I2C_SR2_GENCALL ((uint16_t)0x0010) 04691 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) 04692 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) 04693 #define I2C_SR2_DUALF ((uint16_t)0x0080) 04694 #define I2C_SR2_PEC ((uint16_t)0xFF00) 04696 /******************* Bit definition for I2C_CCR register ********************/ 04697 #define I2C_CCR_CCR ((uint16_t)0x0FFF) 04698 #define I2C_CCR_DUTY ((uint16_t)0x4000) 04699 #define I2C_CCR_FS ((uint16_t)0x8000) 04701 /****************** Bit definition for I2C_TRISE register *******************/ 04702 #define I2C_TRISE_TRISE ((uint8_t)0x3F) 04704 /******************************************************************************/ 04705 /* */ 04706 /* Independent WATCHDOG */ 04707 /* */ 04708 /******************************************************************************/ 04709 /******************* Bit definition for IWDG_KR register ********************/ 04710 #define IWDG_KR_KEY ((uint16_t)0xFFFF) 04712 /******************* Bit definition for IWDG_PR register ********************/ 04713 #define IWDG_PR_PR ((uint8_t)0x07) 04714 #define IWDG_PR_PR_0 ((uint8_t)0x01) 04715 #define IWDG_PR_PR_1 ((uint8_t)0x02) 04716 #define IWDG_PR_PR_2 ((uint8_t)0x04) 04718 /******************* Bit definition for IWDG_RLR register *******************/ 04719 #define IWDG_RLR_RL ((uint16_t)0x0FFF) 04721 /******************* Bit definition for IWDG_SR register ********************/ 04722 #define IWDG_SR_PVU ((uint8_t)0x01) 04723 #define IWDG_SR_RVU ((uint8_t)0x02) 04725 /******************************************************************************/ 04726 /* */ 04727 /* Power Control */ 04728 /* */ 04729 /******************************************************************************/ 04730 /******************** Bit definition for PWR_CR register ********************/ 04731 #define PWR_CR_LPDS ((uint16_t)0x0001) 04732 #define PWR_CR_PDDS ((uint16_t)0x0002) 04733 #define PWR_CR_CWUF ((uint16_t)0x0004) 04734 #define PWR_CR_CSBF ((uint16_t)0x0008) 04735 #define PWR_CR_PVDE ((uint16_t)0x0010) 04737 #define PWR_CR_PLS ((uint16_t)0x00E0) 04738 #define PWR_CR_PLS_0 ((uint16_t)0x0020) 04739 #define PWR_CR_PLS_1 ((uint16_t)0x0040) 04740 #define PWR_CR_PLS_2 ((uint16_t)0x0080) 04744 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) 04745 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) 04746 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) 04747 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) 04748 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) 04749 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) 04750 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) 04751 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) 04753 #define PWR_CR_DBP ((uint16_t)0x0100) 04754 #define PWR_CR_FPDS ((uint16_t)0x0200) 04755 #define PWR_CR_VOS ((uint16_t)0x4000) 04756 /* Legacy define */ 04757 #define PWR_CR_PMODE PWR_CR_VOS 04758 04759 /******************* Bit definition for PWR_CSR register ********************/ 04760 #define PWR_CSR_WUF ((uint16_t)0x0001) 04761 #define PWR_CSR_SBF ((uint16_t)0x0002) 04762 #define PWR_CSR_PVDO ((uint16_t)0x0004) 04763 #define PWR_CSR_BRR ((uint16_t)0x0008) 04764 #define PWR_CSR_EWUP ((uint16_t)0x0100) 04765 #define PWR_CSR_BRE ((uint16_t)0x0200) 04766 #define PWR_CSR_VOSRDY ((uint16_t)0x4000) 04767 /* Legacy define */ 04768 #define PWR_CSR_REGRDY PWR_CSR_VOSRDY 04769 04770 /******************************************************************************/ 04771 /* */ 04772 /* Reset and Clock Control */ 04773 /* */ 04774 /******************************************************************************/ 04775 /******************** Bit definition for RCC_CR register ********************/ 04776 #define RCC_CR_HSION ((uint32_t)0x00000001) 04777 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 04778 04779 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 04780 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) 04781 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) 04782 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) 04783 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) 04784 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) 04786 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) 04787 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) 04788 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) 04789 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) 04790 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) 04791 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) 04792 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) 04793 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) 04794 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) 04796 #define RCC_CR_HSEON ((uint32_t)0x00010000) 04797 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 04798 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 04799 #define RCC_CR_CSSON ((uint32_t)0x00080000) 04800 #define RCC_CR_PLLON ((uint32_t)0x01000000) 04801 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 04802 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) 04803 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) 04804 04805 /******************** Bit definition for RCC_PLLCFGR register ***************/ 04806 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) 04807 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) 04808 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) 04809 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) 04810 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) 04811 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) 04812 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) 04813 04814 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) 04815 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) 04816 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) 04817 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) 04818 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) 04819 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) 04820 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) 04821 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) 04822 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) 04823 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) 04824 04825 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) 04826 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) 04827 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) 04828 04829 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) 04830 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) 04831 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) 04832 04833 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) 04834 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) 04835 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) 04836 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) 04837 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) 04838 04839 /******************** Bit definition for RCC_CFGR register ******************/ 04841 #define RCC_CFGR_SW ((uint32_t)0x00000003) 04842 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) 04843 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) 04845 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) 04846 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) 04847 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) 04850 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) 04851 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) 04852 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) 04854 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) 04855 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) 04856 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) 04859 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) 04860 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) 04861 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) 04862 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) 04863 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) 04865 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) 04866 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) 04867 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) 04868 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) 04869 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) 04870 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) 04871 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) 04872 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) 04873 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) 04876 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) 04877 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) 04878 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) 04879 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) 04881 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) 04882 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) 04883 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) 04884 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) 04885 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) 04888 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) 04889 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) 04890 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) 04891 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) 04893 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) 04894 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) 04895 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) 04896 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) 04897 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) 04900 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) 04901 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) 04902 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) 04903 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) 04904 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) 04905 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) 04906 04908 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000) 04909 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) 04910 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) 04911 04912 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) 04913 04914 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) 04915 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) 04916 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) 04917 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) 04918 04919 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) 04920 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) 04921 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) 04922 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) 04923 04924 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) 04925 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) 04926 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) 04927 04928 /******************** Bit definition for RCC_CIR register *******************/ 04929 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 04930 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) 04931 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 04932 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) 04933 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 04934 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) 04935 #define RCC_CIR_CSSF ((uint32_t)0x00000080) 04936 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) 04937 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) 04938 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) 04939 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) 04940 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) 04941 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) 04942 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) 04943 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 04944 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 04945 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 04946 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) 04947 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) 04948 #define RCC_CIR_CSSC ((uint32_t)0x00800000) 04949 04950 /******************** Bit definition for RCC_AHB1RSTR register **************/ 04951 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) 04952 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) 04953 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) 04954 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) 04955 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) 04956 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) 04957 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) 04958 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) 04959 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) 04960 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) 04961 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) 04962 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) 04963 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) 04964 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) 04965 04966 /******************** Bit definition for RCC_AHB2RSTR register **************/ 04967 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) 04968 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) 04969 #define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020) 04970 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) 04971 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) 04972 04973 /******************** Bit definition for RCC_AHB3RSTR register **************/ 04974 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) 04975 04976 /******************** Bit definition for RCC_APB1RSTR register **************/ 04977 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) 04978 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 04979 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) 04980 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 04981 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 04982 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 04983 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) 04984 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) 04985 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) 04986 #define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) 04987 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000) 04988 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000) 04989 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 04990 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) 04991 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 04992 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 04993 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) 04994 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 04995 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) 04996 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) 04997 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) 04998 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 04999 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 05000 05001 /******************** Bit definition for RCC_APB2RSTR register **************/ 05002 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) 05003 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) 05004 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) 05005 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) 05006 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) 05007 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) 05008 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) 05009 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) 05010 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) 05011 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) 05012 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) 05013 /* Old SPI1RST bit definition, maintained for legacy purpose */ 05014 #define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST 05015 05016 /******************** Bit definition for RCC_AHB1ENR register ***************/ 05017 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) 05018 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) 05019 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) 05020 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) 05021 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) 05022 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) 05023 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) 05024 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) 05025 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) 05026 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) 05027 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) 05028 #define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000) 05029 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) 05030 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) 05031 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) 05032 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) 05033 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) 05034 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) 05035 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) 05036 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) 05037 05038 /******************** Bit definition for RCC_AHB2ENR register ***************/ 05039 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) 05040 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) 05041 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) 05042 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) 05043 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) 05044 05045 /******************** Bit definition for RCC_AHB3ENR register ***************/ 05046 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) 05047 05048 /******************** Bit definition for RCC_APB1ENR register ***************/ 05049 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 05050 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) 05051 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) 05052 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 05053 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 05054 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 05055 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) 05056 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) 05057 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) 05058 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 05059 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) 05060 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 05061 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 05062 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) 05063 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 05064 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 05065 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) 05066 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 05067 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) 05068 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 05069 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) 05070 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) 05071 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 05072 05073 /******************** Bit definition for RCC_APB2ENR register ***************/ 05074 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) 05075 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) 05076 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) 05077 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) 05078 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) 05079 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) 05080 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) 05081 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) 05082 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) 05083 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) 05084 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) 05085 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) 05086 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) 05087 05088 /******************** Bit definition for RCC_AHB1LPENR register *************/ 05089 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) 05090 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) 05091 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) 05092 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) 05093 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) 05094 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) 05095 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) 05096 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) 05097 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) 05098 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) 05099 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) 05100 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) 05101 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) 05102 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) 05103 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) 05104 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) 05105 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) 05106 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) 05107 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) 05108 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) 05109 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) 05110 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) 05111 05112 /******************** Bit definition for RCC_AHB2LPENR register *************/ 05113 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) 05114 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) 05115 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) 05116 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) 05117 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) 05118 05119 /******************** Bit definition for RCC_AHB3LPENR register *************/ 05120 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) 05121 05122 /******************** Bit definition for RCC_APB1LPENR register *************/ 05123 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) 05124 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) 05125 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) 05126 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) 05127 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) 05128 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) 05129 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) 05130 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) 05131 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) 05132 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) 05133 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) 05134 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) 05135 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) 05136 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) 05137 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) 05138 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) 05139 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) 05140 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) 05141 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) 05142 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) 05143 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) 05144 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) 05145 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) 05146 05147 /******************** Bit definition for RCC_APB2LPENR register *************/ 05148 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) 05149 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) 05150 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) 05151 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) 05152 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) 05153 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) 05154 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) 05155 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) 05156 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) 05157 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) 05158 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) 05159 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) 05160 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) 05161 05162 /******************** Bit definition for RCC_BDCR register ******************/ 05163 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) 05164 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) 05165 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) 05166 05167 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) 05168 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) 05169 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) 05170 05171 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) 05172 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) 05173 05174 /******************** Bit definition for RCC_CSR register *******************/ 05175 #define RCC_CSR_LSION ((uint32_t)0x00000001) 05176 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) 05177 #define RCC_CSR_RMVF ((uint32_t)0x01000000) 05178 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) 05179 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000) 05180 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) 05181 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 05182 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) 05183 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) 05184 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) 05185 05186 /******************** Bit definition for RCC_SSCGR register *****************/ 05187 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) 05188 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) 05189 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) 05190 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) 05191 05192 /******************** Bit definition for RCC_PLLI2SCFGR register ************/ 05193 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) 05194 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) 05195 05196 /******************************************************************************/ 05197 /* */ 05198 /* RNG */ 05199 /* */ 05200 /******************************************************************************/ 05201 /******************** Bits definition for RNG_CR register *******************/ 05202 #define RNG_CR_RNGEN ((uint32_t)0x00000004) 05203 #define RNG_CR_IE ((uint32_t)0x00000008) 05204 05205 /******************** Bits definition for RNG_SR register *******************/ 05206 #define RNG_SR_DRDY ((uint32_t)0x00000001) 05207 #define RNG_SR_CECS ((uint32_t)0x00000002) 05208 #define RNG_SR_SECS ((uint32_t)0x00000004) 05209 #define RNG_SR_CEIS ((uint32_t)0x00000020) 05210 #define RNG_SR_SEIS ((uint32_t)0x00000040) 05211 05212 /******************************************************************************/ 05213 /* */ 05214 /* Real-Time Clock (RTC) */ 05215 /* */ 05216 /******************************************************************************/ 05217 /******************** Bits definition for RTC_TR register *******************/ 05218 #define RTC_TR_PM ((uint32_t)0x00400000) 05219 #define RTC_TR_HT ((uint32_t)0x00300000) 05220 #define RTC_TR_HT_0 ((uint32_t)0x00100000) 05221 #define RTC_TR_HT_1 ((uint32_t)0x00200000) 05222 #define RTC_TR_HU ((uint32_t)0x000F0000) 05223 #define RTC_TR_HU_0 ((uint32_t)0x00010000) 05224 #define RTC_TR_HU_1 ((uint32_t)0x00020000) 05225 #define RTC_TR_HU_2 ((uint32_t)0x00040000) 05226 #define RTC_TR_HU_3 ((uint32_t)0x00080000) 05227 #define RTC_TR_MNT ((uint32_t)0x00007000) 05228 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) 05229 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) 05230 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) 05231 #define RTC_TR_MNU ((uint32_t)0x00000F00) 05232 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) 05233 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) 05234 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) 05235 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) 05236 #define RTC_TR_ST ((uint32_t)0x00000070) 05237 #define RTC_TR_ST_0 ((uint32_t)0x00000010) 05238 #define RTC_TR_ST_1 ((uint32_t)0x00000020) 05239 #define RTC_TR_ST_2 ((uint32_t)0x00000040) 05240 #define RTC_TR_SU ((uint32_t)0x0000000F) 05241 #define RTC_TR_SU_0 ((uint32_t)0x00000001) 05242 #define RTC_TR_SU_1 ((uint32_t)0x00000002) 05243 #define RTC_TR_SU_2 ((uint32_t)0x00000004) 05244 #define RTC_TR_SU_3 ((uint32_t)0x00000008) 05245 05246 /******************** Bits definition for RTC_DR register *******************/ 05247 #define RTC_DR_YT ((uint32_t)0x00F00000) 05248 #define RTC_DR_YT_0 ((uint32_t)0x00100000) 05249 #define RTC_DR_YT_1 ((uint32_t)0x00200000) 05250 #define RTC_DR_YT_2 ((uint32_t)0x00400000) 05251 #define RTC_DR_YT_3 ((uint32_t)0x00800000) 05252 #define RTC_DR_YU ((uint32_t)0x000F0000) 05253 #define RTC_DR_YU_0 ((uint32_t)0x00010000) 05254 #define RTC_DR_YU_1 ((uint32_t)0x00020000) 05255 #define RTC_DR_YU_2 ((uint32_t)0x00040000) 05256 #define RTC_DR_YU_3 ((uint32_t)0x00080000) 05257 #define RTC_DR_WDU ((uint32_t)0x0000E000) 05258 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) 05259 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) 05260 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) 05261 #define RTC_DR_MT ((uint32_t)0x00001000) 05262 #define RTC_DR_MU ((uint32_t)0x00000F00) 05263 #define RTC_DR_MU_0 ((uint32_t)0x00000100) 05264 #define RTC_DR_MU_1 ((uint32_t)0x00000200) 05265 #define RTC_DR_MU_2 ((uint32_t)0x00000400) 05266 #define RTC_DR_MU_3 ((uint32_t)0x00000800) 05267 #define RTC_DR_DT ((uint32_t)0x00000030) 05268 #define RTC_DR_DT_0 ((uint32_t)0x00000010) 05269 #define RTC_DR_DT_1 ((uint32_t)0x00000020) 05270 #define RTC_DR_DU ((uint32_t)0x0000000F) 05271 #define RTC_DR_DU_0 ((uint32_t)0x00000001) 05272 #define RTC_DR_DU_1 ((uint32_t)0x00000002) 05273 #define RTC_DR_DU_2 ((uint32_t)0x00000004) 05274 #define RTC_DR_DU_3 ((uint32_t)0x00000008) 05275 05276 /******************** Bits definition for RTC_CR register *******************/ 05277 #define RTC_CR_COE ((uint32_t)0x00800000) 05278 #define RTC_CR_OSEL ((uint32_t)0x00600000) 05279 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) 05280 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) 05281 #define RTC_CR_POL ((uint32_t)0x00100000) 05282 #define RTC_CR_COSEL ((uint32_t)0x00080000) 05283 #define RTC_CR_BCK ((uint32_t)0x00040000) 05284 #define RTC_CR_SUB1H ((uint32_t)0x00020000) 05285 #define RTC_CR_ADD1H ((uint32_t)0x00010000) 05286 #define RTC_CR_TSIE ((uint32_t)0x00008000) 05287 #define RTC_CR_WUTIE ((uint32_t)0x00004000) 05288 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) 05289 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) 05290 #define RTC_CR_TSE ((uint32_t)0x00000800) 05291 #define RTC_CR_WUTE ((uint32_t)0x00000400) 05292 #define RTC_CR_ALRBE ((uint32_t)0x00000200) 05293 #define RTC_CR_ALRAE ((uint32_t)0x00000100) 05294 #define RTC_CR_DCE ((uint32_t)0x00000080) 05295 #define RTC_CR_FMT ((uint32_t)0x00000040) 05296 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020) 05297 #define RTC_CR_REFCKON ((uint32_t)0x00000010) 05298 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) 05299 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) 05300 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) 05301 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) 05302 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) 05303 05304 /******************** Bits definition for RTC_ISR register ******************/ 05305 #define RTC_ISR_RECALPF ((uint32_t)0x00010000) 05306 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) 05307 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) 05308 #define RTC_ISR_TSF ((uint32_t)0x00000800) 05309 #define RTC_ISR_WUTF ((uint32_t)0x00000400) 05310 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) 05311 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) 05312 #define RTC_ISR_INIT ((uint32_t)0x00000080) 05313 #define RTC_ISR_INITF ((uint32_t)0x00000040) 05314 #define RTC_ISR_RSF ((uint32_t)0x00000020) 05315 #define RTC_ISR_INITS ((uint32_t)0x00000010) 05316 #define RTC_ISR_SHPF ((uint32_t)0x00000008) 05317 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) 05318 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) 05319 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) 05320 05321 /******************** Bits definition for RTC_PRER register *****************/ 05322 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) 05323 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) 05324 05325 /******************** Bits definition for RTC_WUTR register *****************/ 05326 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) 05327 05328 /******************** Bits definition for RTC_CALIBR register ***************/ 05329 #define RTC_CALIBR_DCS ((uint32_t)0x00000080) 05330 #define RTC_CALIBR_DC ((uint32_t)0x0000001F) 05331 05332 /******************** Bits definition for RTC_ALRMAR register ***************/ 05333 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) 05334 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) 05335 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) 05336 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) 05337 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) 05338 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) 05339 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) 05340 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) 05341 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) 05342 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) 05343 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) 05344 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) 05345 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) 05346 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) 05347 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) 05348 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) 05349 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) 05350 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) 05351 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) 05352 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) 05353 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) 05354 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) 05355 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) 05356 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) 05357 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) 05358 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) 05359 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) 05360 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) 05361 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) 05362 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) 05363 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) 05364 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) 05365 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) 05366 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) 05367 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) 05368 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) 05369 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) 05370 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) 05371 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) 05372 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) 05373 05374 /******************** Bits definition for RTC_ALRMBR register ***************/ 05375 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) 05376 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) 05377 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) 05378 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) 05379 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) 05380 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) 05381 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) 05382 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) 05383 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) 05384 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) 05385 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) 05386 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) 05387 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) 05388 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) 05389 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) 05390 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) 05391 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) 05392 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) 05393 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) 05394 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) 05395 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) 05396 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) 05397 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) 05398 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) 05399 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) 05400 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) 05401 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) 05402 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) 05403 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) 05404 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) 05405 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) 05406 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) 05407 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) 05408 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) 05409 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) 05410 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) 05411 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) 05412 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) 05413 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) 05414 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) 05415 05416 /******************** Bits definition for RTC_WPR register ******************/ 05417 #define RTC_WPR_KEY ((uint32_t)0x000000FF) 05418 05419 /******************** Bits definition for RTC_SSR register ******************/ 05420 #define RTC_SSR_SS ((uint32_t)0x0000FFFF) 05421 05422 /******************** Bits definition for RTC_SHIFTR register ***************/ 05423 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF) 05424 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000) 05425 05426 /******************** Bits definition for RTC_TSTR register *****************/ 05427 #define RTC_TSTR_PM ((uint32_t)0x00400000) 05428 #define RTC_TSTR_HT ((uint32_t)0x00300000) 05429 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) 05430 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) 05431 #define RTC_TSTR_HU ((uint32_t)0x000F0000) 05432 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) 05433 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) 05434 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) 05435 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) 05436 #define RTC_TSTR_MNT ((uint32_t)0x00007000) 05437 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) 05438 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) 05439 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) 05440 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) 05441 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) 05442 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) 05443 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) 05444 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) 05445 #define RTC_TSTR_ST ((uint32_t)0x00000070) 05446 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) 05447 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) 05448 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) 05449 #define RTC_TSTR_SU ((uint32_t)0x0000000F) 05450 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) 05451 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) 05452 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) 05453 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) 05454 05455 /******************** Bits definition for RTC_TSDR register *****************/ 05456 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) 05457 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) 05458 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) 05459 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) 05460 #define RTC_TSDR_MT ((uint32_t)0x00001000) 05461 #define RTC_TSDR_MU ((uint32_t)0x00000F00) 05462 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) 05463 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) 05464 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) 05465 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) 05466 #define RTC_TSDR_DT ((uint32_t)0x00000030) 05467 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) 05468 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) 05469 #define RTC_TSDR_DU ((uint32_t)0x0000000F) 05470 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) 05471 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) 05472 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) 05473 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) 05474 05475 /******************** Bits definition for RTC_TSSSR register ****************/ 05476 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF) 05477 05478 /******************** Bits definition for RTC_CAL register *****************/ 05479 #define RTC_CALR_CALP ((uint32_t)0x00008000) 05480 #define RTC_CALR_CALW8 ((uint32_t)0x00004000) 05481 #define RTC_CALR_CALW16 ((uint32_t)0x00002000) 05482 #define RTC_CALR_CALM ((uint32_t)0x000001FF) 05483 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001) 05484 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002) 05485 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004) 05486 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008) 05487 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010) 05488 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020) 05489 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040) 05490 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080) 05491 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100) 05492 05493 /******************** Bits definition for RTC_TAFCR register ****************/ 05494 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) 05495 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) 05496 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) 05497 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000) 05498 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000) 05499 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000) 05500 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000) 05501 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800) 05502 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800) 05503 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000) 05504 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700) 05505 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100) 05506 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200) 05507 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400) 05508 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080) 05509 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) 05510 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) 05511 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) 05512 05513 /******************** Bits definition for RTC_ALRMASSR register *************/ 05514 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000) 05515 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000) 05516 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000) 05517 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000) 05518 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000) 05519 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF) 05520 05521 /******************** Bits definition for RTC_ALRMBSSR register *************/ 05522 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000) 05523 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000) 05524 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000) 05525 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000) 05526 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000) 05527 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF) 05528 05529 /******************** Bits definition for RTC_BKP0R register ****************/ 05530 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) 05531 05532 /******************** Bits definition for RTC_BKP1R register ****************/ 05533 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) 05534 05535 /******************** Bits definition for RTC_BKP2R register ****************/ 05536 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) 05537 05538 /******************** Bits definition for RTC_BKP3R register ****************/ 05539 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) 05540 05541 /******************** Bits definition for RTC_BKP4R register ****************/ 05542 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) 05543 05544 /******************** Bits definition for RTC_BKP5R register ****************/ 05545 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) 05546 05547 /******************** Bits definition for RTC_BKP6R register ****************/ 05548 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) 05549 05550 /******************** Bits definition for RTC_BKP7R register ****************/ 05551 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) 05552 05553 /******************** Bits definition for RTC_BKP8R register ****************/ 05554 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) 05555 05556 /******************** Bits definition for RTC_BKP9R register ****************/ 05557 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) 05558 05559 /******************** Bits definition for RTC_BKP10R register ***************/ 05560 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) 05561 05562 /******************** Bits definition for RTC_BKP11R register ***************/ 05563 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) 05564 05565 /******************** Bits definition for RTC_BKP12R register ***************/ 05566 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) 05567 05568 /******************** Bits definition for RTC_BKP13R register ***************/ 05569 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) 05570 05571 /******************** Bits definition for RTC_BKP14R register ***************/ 05572 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) 05573 05574 /******************** Bits definition for RTC_BKP15R register ***************/ 05575 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) 05576 05577 /******************** Bits definition for RTC_BKP16R register ***************/ 05578 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) 05579 05580 /******************** Bits definition for RTC_BKP17R register ***************/ 05581 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) 05582 05583 /******************** Bits definition for RTC_BKP18R register ***************/ 05584 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) 05585 05586 /******************** Bits definition for RTC_BKP19R register ***************/ 05587 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) 05588 05589 /******************************************************************************/ 05590 /* */ 05591 /* SD host Interface */ 05592 /* */ 05593 /******************************************************************************/ 05594 /****************** Bit definition for SDIO_POWER register ******************/ 05595 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) 05596 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) 05597 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) 05599 /****************** Bit definition for SDIO_CLKCR register ******************/ 05600 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) 05601 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) 05602 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) 05603 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) 05605 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) 05606 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) 05607 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) 05609 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) 05610 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) 05612 /******************* Bit definition for SDIO_ARG register *******************/ 05613 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) 05615 /******************* Bit definition for SDIO_CMD register *******************/ 05616 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) 05618 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) 05619 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) 05620 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) 05622 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) 05623 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) 05624 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) 05625 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) 05626 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) 05627 #define SDIO_CMD_NIEN ((uint16_t)0x2000) 05628 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) 05630 /***************** Bit definition for SDIO_RESPCMD register *****************/ 05631 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) 05633 /****************** Bit definition for SDIO_RESP0 register ******************/ 05634 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) 05636 /****************** Bit definition for SDIO_RESP1 register ******************/ 05637 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) 05639 /****************** Bit definition for SDIO_RESP2 register ******************/ 05640 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) 05642 /****************** Bit definition for SDIO_RESP3 register ******************/ 05643 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) 05645 /****************** Bit definition for SDIO_RESP4 register ******************/ 05646 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) 05648 /****************** Bit definition for SDIO_DTIMER register *****************/ 05649 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) 05651 /****************** Bit definition for SDIO_DLEN register *******************/ 05652 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) 05654 /****************** Bit definition for SDIO_DCTRL register ******************/ 05655 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) 05656 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) 05657 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) 05658 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) 05660 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) 05661 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) 05662 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) 05663 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) 05664 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) 05666 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) 05667 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) 05668 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) 05669 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) 05671 /****************** Bit definition for SDIO_DCOUNT register *****************/ 05672 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) 05674 /****************** Bit definition for SDIO_STA register ********************/ 05675 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) 05676 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) 05677 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) 05678 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) 05679 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) 05680 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) 05681 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) 05682 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) 05683 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) 05684 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) 05685 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) 05686 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) 05687 #define SDIO_STA_TXACT ((uint32_t)0x00001000) 05688 #define SDIO_STA_RXACT ((uint32_t)0x00002000) 05689 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) 05690 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) 05691 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) 05692 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) 05693 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) 05694 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) 05695 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) 05696 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) 05697 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) 05698 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) 05700 /******************* Bit definition for SDIO_ICR register *******************/ 05701 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) 05702 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) 05703 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) 05704 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) 05705 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) 05706 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) 05707 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) 05708 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) 05709 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) 05710 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) 05711 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) 05712 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) 05713 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) 05715 /****************** Bit definition for SDIO_MASK register *******************/ 05716 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) 05717 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) 05718 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) 05719 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) 05720 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) 05721 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) 05722 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) 05723 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) 05724 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) 05725 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) 05726 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) 05727 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) 05728 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) 05729 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) 05730 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) 05731 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) 05732 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) 05733 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) 05734 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) 05735 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) 05736 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) 05737 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) 05738 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) 05739 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) 05741 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 05742 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) 05744 /****************** Bit definition for SDIO_FIFO register *******************/ 05745 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) 05747 /******************************************************************************/ 05748 /* */ 05749 /* Serial Peripheral Interface */ 05750 /* */ 05751 /******************************************************************************/ 05752 /******************* Bit definition for SPI_CR1 register ********************/ 05753 #define SPI_CR1_CPHA ((uint16_t)0x0001) 05754 #define SPI_CR1_CPOL ((uint16_t)0x0002) 05755 #define SPI_CR1_MSTR ((uint16_t)0x0004) 05757 #define SPI_CR1_BR ((uint16_t)0x0038) 05758 #define SPI_CR1_BR_0 ((uint16_t)0x0008) 05759 #define SPI_CR1_BR_1 ((uint16_t)0x0010) 05760 #define SPI_CR1_BR_2 ((uint16_t)0x0020) 05762 #define SPI_CR1_SPE ((uint16_t)0x0040) 05763 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) 05764 #define SPI_CR1_SSI ((uint16_t)0x0100) 05765 #define SPI_CR1_SSM ((uint16_t)0x0200) 05766 #define SPI_CR1_RXONLY ((uint16_t)0x0400) 05767 #define SPI_CR1_DFF ((uint16_t)0x0800) 05768 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) 05769 #define SPI_CR1_CRCEN ((uint16_t)0x2000) 05770 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) 05771 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) 05773 /******************* Bit definition for SPI_CR2 register ********************/ 05774 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) 05775 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) 05776 #define SPI_CR2_SSOE ((uint8_t)0x04) 05777 #define SPI_CR2_ERRIE ((uint8_t)0x20) 05778 #define SPI_CR2_RXNEIE ((uint8_t)0x40) 05779 #define SPI_CR2_TXEIE ((uint8_t)0x80) 05781 /******************** Bit definition for SPI_SR register ********************/ 05782 #define SPI_SR_RXNE ((uint8_t)0x01) 05783 #define SPI_SR_TXE ((uint8_t)0x02) 05784 #define SPI_SR_CHSIDE ((uint8_t)0x04) 05785 #define SPI_SR_UDR ((uint8_t)0x08) 05786 #define SPI_SR_CRCERR ((uint8_t)0x10) 05787 #define SPI_SR_MODF ((uint8_t)0x20) 05788 #define SPI_SR_OVR ((uint8_t)0x40) 05789 #define SPI_SR_BSY ((uint8_t)0x80) 05791 /******************** Bit definition for SPI_DR register ********************/ 05792 #define SPI_DR_DR ((uint16_t)0xFFFF) 05794 /******************* Bit definition for SPI_CRCPR register ******************/ 05795 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) 05797 /****************** Bit definition for SPI_RXCRCR register ******************/ 05798 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) 05800 /****************** Bit definition for SPI_TXCRCR register ******************/ 05801 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) 05803 /****************** Bit definition for SPI_I2SCFGR register *****************/ 05804 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) 05806 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) 05807 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) 05808 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) 05810 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) 05812 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) 05813 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) 05814 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) 05816 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) 05818 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) 05819 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) 05820 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) 05822 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) 05823 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) 05825 /****************** Bit definition for SPI_I2SPR register *******************/ 05826 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) 05827 #define SPI_I2SPR_ODD ((uint16_t)0x0100) 05828 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) 05830 /******************************************************************************/ 05831 /* */ 05832 /* SYSCFG */ 05833 /* */ 05834 /******************************************************************************/ 05835 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 05836 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) 05837 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) 05838 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) 05839 05840 /****************** Bit definition for SYSCFG_PMC register ******************/ 05841 #define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) 05842 /* Old MII_RMII_SEL bit definition, maintained for legacy purpose */ 05843 #define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL 05844 05845 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 05846 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) 05847 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) 05848 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) 05849 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) 05853 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) 05854 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) 05855 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) 05856 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) 05857 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) 05858 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) 05859 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) 05860 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) 05861 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) 05865 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) 05866 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) 05867 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) 05868 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) 05869 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) 05870 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) 05871 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) 05872 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) 05873 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) 05877 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) 05878 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) 05879 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) 05880 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) 05881 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) 05882 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) 05883 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) 05884 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) 05885 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) 05889 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) 05890 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) 05891 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) 05892 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) 05893 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) 05894 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) 05895 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) 05896 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) 05897 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) 05899 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 05900 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) 05901 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) 05902 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) 05903 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) 05907 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) 05908 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) 05909 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) 05910 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) 05911 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) 05912 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) 05913 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) 05914 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) 05915 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) 05919 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) 05920 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) 05921 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) 05922 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) 05923 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) 05924 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) 05925 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) 05926 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) 05927 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) 05931 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) 05932 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) 05933 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) 05934 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) 05935 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) 05936 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) 05937 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) 05938 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) 05939 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) 05943 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) 05944 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) 05945 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) 05946 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) 05947 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) 05948 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) 05949 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) 05950 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) 05951 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) 05953 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 05954 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) 05955 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) 05956 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) 05957 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) 05962 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) 05963 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) 05964 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) 05965 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) 05966 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) 05967 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) 05968 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) 05969 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) 05970 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) 05974 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) 05975 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) 05976 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) 05977 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) 05978 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) 05979 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) 05980 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) 05981 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) 05982 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) 05986 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) 05987 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) 05988 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) 05989 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) 05990 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) 05991 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) 05992 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) 05993 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) 05994 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) 05998 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) 05999 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) 06000 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) 06001 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) 06002 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) 06003 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) 06004 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) 06005 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) 06006 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) 06008 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 06009 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) 06010 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) 06011 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) 06012 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) 06016 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) 06017 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) 06018 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) 06019 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) 06020 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) 06021 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) 06022 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) 06023 #define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) 06027 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) 06028 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) 06029 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) 06030 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) 06031 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) 06032 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) 06033 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) 06034 #define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) 06038 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) 06039 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) 06040 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) 06041 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) 06042 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) 06043 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) 06044 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) 06045 #define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) 06049 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) 06050 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) 06051 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) 06052 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) 06053 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) 06054 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) 06055 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) 06056 #define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) 06058 /****************** Bit definition for SYSCFG_CMPCR register ****************/ 06059 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) 06060 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) 06062 /******************************************************************************/ 06063 /* */ 06064 /* TIM */ 06065 /* */ 06066 /******************************************************************************/ 06067 /******************* Bit definition for TIM_CR1 register ********************/ 06068 #define TIM_CR1_CEN ((uint16_t)0x0001) 06069 #define TIM_CR1_UDIS ((uint16_t)0x0002) 06070 #define TIM_CR1_URS ((uint16_t)0x0004) 06071 #define TIM_CR1_OPM ((uint16_t)0x0008) 06072 #define TIM_CR1_DIR ((uint16_t)0x0010) 06074 #define TIM_CR1_CMS ((uint16_t)0x0060) 06075 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) 06076 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) 06078 #define TIM_CR1_ARPE ((uint16_t)0x0080) 06080 #define TIM_CR1_CKD ((uint16_t)0x0300) 06081 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) 06082 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) 06084 /******************* Bit definition for TIM_CR2 register ********************/ 06085 #define TIM_CR2_CCPC ((uint16_t)0x0001) 06086 #define TIM_CR2_CCUS ((uint16_t)0x0004) 06087 #define TIM_CR2_CCDS ((uint16_t)0x0008) 06089 #define TIM_CR2_MMS ((uint16_t)0x0070) 06090 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) 06091 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) 06092 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) 06094 #define TIM_CR2_TI1S ((uint16_t)0x0080) 06095 #define TIM_CR2_OIS1 ((uint16_t)0x0100) 06096 #define TIM_CR2_OIS1N ((uint16_t)0x0200) 06097 #define TIM_CR2_OIS2 ((uint16_t)0x0400) 06098 #define TIM_CR2_OIS2N ((uint16_t)0x0800) 06099 #define TIM_CR2_OIS3 ((uint16_t)0x1000) 06100 #define TIM_CR2_OIS3N ((uint16_t)0x2000) 06101 #define TIM_CR2_OIS4 ((uint16_t)0x4000) 06103 /******************* Bit definition for TIM_SMCR register *******************/ 06104 #define TIM_SMCR_SMS ((uint16_t)0x0007) 06105 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) 06106 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) 06107 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) 06109 #define TIM_SMCR_TS ((uint16_t)0x0070) 06110 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) 06111 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) 06112 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) 06114 #define TIM_SMCR_MSM ((uint16_t)0x0080) 06116 #define TIM_SMCR_ETF ((uint16_t)0x0F00) 06117 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) 06118 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) 06119 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) 06120 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) 06122 #define TIM_SMCR_ETPS ((uint16_t)0x3000) 06123 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) 06124 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) 06126 #define TIM_SMCR_ECE ((uint16_t)0x4000) 06127 #define TIM_SMCR_ETP ((uint16_t)0x8000) 06129 /******************* Bit definition for TIM_DIER register *******************/ 06130 #define TIM_DIER_UIE ((uint16_t)0x0001) 06131 #define TIM_DIER_CC1IE ((uint16_t)0x0002) 06132 #define TIM_DIER_CC2IE ((uint16_t)0x0004) 06133 #define TIM_DIER_CC3IE ((uint16_t)0x0008) 06134 #define TIM_DIER_CC4IE ((uint16_t)0x0010) 06135 #define TIM_DIER_COMIE ((uint16_t)0x0020) 06136 #define TIM_DIER_TIE ((uint16_t)0x0040) 06137 #define TIM_DIER_BIE ((uint16_t)0x0080) 06138 #define TIM_DIER_UDE ((uint16_t)0x0100) 06139 #define TIM_DIER_CC1DE ((uint16_t)0x0200) 06140 #define TIM_DIER_CC2DE ((uint16_t)0x0400) 06141 #define TIM_DIER_CC3DE ((uint16_t)0x0800) 06142 #define TIM_DIER_CC4DE ((uint16_t)0x1000) 06143 #define TIM_DIER_COMDE ((uint16_t)0x2000) 06144 #define TIM_DIER_TDE ((uint16_t)0x4000) 06146 /******************** Bit definition for TIM_SR register ********************/ 06147 #define TIM_SR_UIF ((uint16_t)0x0001) 06148 #define TIM_SR_CC1IF ((uint16_t)0x0002) 06149 #define TIM_SR_CC2IF ((uint16_t)0x0004) 06150 #define TIM_SR_CC3IF ((uint16_t)0x0008) 06151 #define TIM_SR_CC4IF ((uint16_t)0x0010) 06152 #define TIM_SR_COMIF ((uint16_t)0x0020) 06153 #define TIM_SR_TIF ((uint16_t)0x0040) 06154 #define TIM_SR_BIF ((uint16_t)0x0080) 06155 #define TIM_SR_CC1OF ((uint16_t)0x0200) 06156 #define TIM_SR_CC2OF ((uint16_t)0x0400) 06157 #define TIM_SR_CC3OF ((uint16_t)0x0800) 06158 #define TIM_SR_CC4OF ((uint16_t)0x1000) 06160 /******************* Bit definition for TIM_EGR register ********************/ 06161 #define TIM_EGR_UG ((uint8_t)0x01) 06162 #define TIM_EGR_CC1G ((uint8_t)0x02) 06163 #define TIM_EGR_CC2G ((uint8_t)0x04) 06164 #define TIM_EGR_CC3G ((uint8_t)0x08) 06165 #define TIM_EGR_CC4G ((uint8_t)0x10) 06166 #define TIM_EGR_COMG ((uint8_t)0x20) 06167 #define TIM_EGR_TG ((uint8_t)0x40) 06168 #define TIM_EGR_BG ((uint8_t)0x80) 06170 /****************** Bit definition for TIM_CCMR1 register *******************/ 06171 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) 06172 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) 06173 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) 06175 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) 06176 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) 06178 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) 06179 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 06180 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 06181 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 06183 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) 06185 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) 06186 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 06187 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 06189 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) 06190 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) 06192 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) 06193 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 06194 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 06195 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 06197 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) 06199 /*----------------------------------------------------------------------------*/ 06200 06201 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 06202 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 06203 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 06205 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) 06206 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 06207 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 06208 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 06209 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 06211 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 06212 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) 06213 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) 06215 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) 06216 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) 06217 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) 06218 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) 06219 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) 06221 /****************** Bit definition for TIM_CCMR2 register *******************/ 06222 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) 06223 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) 06224 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) 06226 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) 06227 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) 06229 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) 06230 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) 06231 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) 06232 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) 06234 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) 06236 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) 06237 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) 06238 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) 06240 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) 06241 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) 06243 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) 06244 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) 06245 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) 06246 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) 06248 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) 06250 /*----------------------------------------------------------------------------*/ 06251 06252 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) 06253 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) 06254 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) 06256 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) 06257 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) 06258 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) 06259 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) 06260 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) 06262 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) 06263 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) 06264 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) 06266 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) 06267 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) 06268 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) 06269 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) 06270 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) 06272 /******************* Bit definition for TIM_CCER register *******************/ 06273 #define TIM_CCER_CC1E ((uint16_t)0x0001) 06274 #define TIM_CCER_CC1P ((uint16_t)0x0002) 06275 #define TIM_CCER_CC1NE ((uint16_t)0x0004) 06276 #define TIM_CCER_CC1NP ((uint16_t)0x0008) 06277 #define TIM_CCER_CC2E ((uint16_t)0x0010) 06278 #define TIM_CCER_CC2P ((uint16_t)0x0020) 06279 #define TIM_CCER_CC2NE ((uint16_t)0x0040) 06280 #define TIM_CCER_CC2NP ((uint16_t)0x0080) 06281 #define TIM_CCER_CC3E ((uint16_t)0x0100) 06282 #define TIM_CCER_CC3P ((uint16_t)0x0200) 06283 #define TIM_CCER_CC3NE ((uint16_t)0x0400) 06284 #define TIM_CCER_CC3NP ((uint16_t)0x0800) 06285 #define TIM_CCER_CC4E ((uint16_t)0x1000) 06286 #define TIM_CCER_CC4P ((uint16_t)0x2000) 06287 #define TIM_CCER_CC4NP ((uint16_t)0x8000) 06289 /******************* Bit definition for TIM_CNT register ********************/ 06290 #define TIM_CNT_CNT ((uint16_t)0xFFFF) 06292 /******************* Bit definition for TIM_PSC register ********************/ 06293 #define TIM_PSC_PSC ((uint16_t)0xFFFF) 06295 /******************* Bit definition for TIM_ARR register ********************/ 06296 #define TIM_ARR_ARR ((uint16_t)0xFFFF) 06298 /******************* Bit definition for TIM_RCR register ********************/ 06299 #define TIM_RCR_REP ((uint8_t)0xFF) 06301 /******************* Bit definition for TIM_CCR1 register *******************/ 06302 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) 06304 /******************* Bit definition for TIM_CCR2 register *******************/ 06305 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) 06307 /******************* Bit definition for TIM_CCR3 register *******************/ 06308 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) 06310 /******************* Bit definition for TIM_CCR4 register *******************/ 06311 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) 06313 /******************* Bit definition for TIM_BDTR register *******************/ 06314 #define TIM_BDTR_DTG ((uint16_t)0x00FF) 06315 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) 06316 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) 06317 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) 06318 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) 06319 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) 06320 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) 06321 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) 06322 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) 06324 #define TIM_BDTR_LOCK ((uint16_t)0x0300) 06325 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) 06326 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) 06328 #define TIM_BDTR_OSSI ((uint16_t)0x0400) 06329 #define TIM_BDTR_OSSR ((uint16_t)0x0800) 06330 #define TIM_BDTR_BKE ((uint16_t)0x1000) 06331 #define TIM_BDTR_BKP ((uint16_t)0x2000) 06332 #define TIM_BDTR_AOE ((uint16_t)0x4000) 06333 #define TIM_BDTR_MOE ((uint16_t)0x8000) 06335 /******************* Bit definition for TIM_DCR register ********************/ 06336 #define TIM_DCR_DBA ((uint16_t)0x001F) 06337 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) 06338 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) 06339 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) 06340 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) 06341 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) 06343 #define TIM_DCR_DBL ((uint16_t)0x1F00) 06344 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) 06345 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) 06346 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) 06347 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) 06348 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) 06350 /******************* Bit definition for TIM_DMAR register *******************/ 06351 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) 06353 /******************* Bit definition for TIM_OR register *********************/ 06354 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) 06355 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) 06356 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) 06357 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) 06358 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) 06359 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) 06362 /******************************************************************************/ 06363 /* */ 06364 /* Universal Synchronous Asynchronous Receiver Transmitter */ 06365 /* */ 06366 /******************************************************************************/ 06367 /******************* Bit definition for USART_SR register *******************/ 06368 #define USART_SR_PE ((uint16_t)0x0001) 06369 #define USART_SR_FE ((uint16_t)0x0002) 06370 #define USART_SR_NE ((uint16_t)0x0004) 06371 #define USART_SR_ORE ((uint16_t)0x0008) 06372 #define USART_SR_IDLE ((uint16_t)0x0010) 06373 #define USART_SR_RXNE ((uint16_t)0x0020) 06374 #define USART_SR_TC ((uint16_t)0x0040) 06375 #define USART_SR_TXE ((uint16_t)0x0080) 06376 #define USART_SR_LBD ((uint16_t)0x0100) 06377 #define USART_SR_CTS ((uint16_t)0x0200) 06379 /******************* Bit definition for USART_DR register *******************/ 06380 #define USART_DR_DR ((uint16_t)0x01FF) 06382 /****************** Bit definition for USART_BRR register *******************/ 06383 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) 06384 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) 06386 /****************** Bit definition for USART_CR1 register *******************/ 06387 #define USART_CR1_SBK ((uint16_t)0x0001) 06388 #define USART_CR1_RWU ((uint16_t)0x0002) 06389 #define USART_CR1_RE ((uint16_t)0x0004) 06390 #define USART_CR1_TE ((uint16_t)0x0008) 06391 #define USART_CR1_IDLEIE ((uint16_t)0x0010) 06392 #define USART_CR1_RXNEIE ((uint16_t)0x0020) 06393 #define USART_CR1_TCIE ((uint16_t)0x0040) 06394 #define USART_CR1_TXEIE ((uint16_t)0x0080) 06395 #define USART_CR1_PEIE ((uint16_t)0x0100) 06396 #define USART_CR1_PS ((uint16_t)0x0200) 06397 #define USART_CR1_PCE ((uint16_t)0x0400) 06398 #define USART_CR1_WAKE ((uint16_t)0x0800) 06399 #define USART_CR1_M ((uint16_t)0x1000) 06400 #define USART_CR1_UE ((uint16_t)0x2000) 06401 #define USART_CR1_OVER8 ((uint16_t)0x8000) 06403 /****************** Bit definition for USART_CR2 register *******************/ 06404 #define USART_CR2_ADD ((uint16_t)0x000F) 06405 #define USART_CR2_LBDL ((uint16_t)0x0020) 06406 #define USART_CR2_LBDIE ((uint16_t)0x0040) 06407 #define USART_CR2_LBCL ((uint16_t)0x0100) 06408 #define USART_CR2_CPHA ((uint16_t)0x0200) 06409 #define USART_CR2_CPOL ((uint16_t)0x0400) 06410 #define USART_CR2_CLKEN ((uint16_t)0x0800) 06412 #define USART_CR2_STOP ((uint16_t)0x3000) 06413 #define USART_CR2_STOP_0 ((uint16_t)0x1000) 06414 #define USART_CR2_STOP_1 ((uint16_t)0x2000) 06416 #define USART_CR2_LINEN ((uint16_t)0x4000) 06418 /****************** Bit definition for USART_CR3 register *******************/ 06419 #define USART_CR3_EIE ((uint16_t)0x0001) 06420 #define USART_CR3_IREN ((uint16_t)0x0002) 06421 #define USART_CR3_IRLP ((uint16_t)0x0004) 06422 #define USART_CR3_HDSEL ((uint16_t)0x0008) 06423 #define USART_CR3_NACK ((uint16_t)0x0010) 06424 #define USART_CR3_SCEN ((uint16_t)0x0020) 06425 #define USART_CR3_DMAR ((uint16_t)0x0040) 06426 #define USART_CR3_DMAT ((uint16_t)0x0080) 06427 #define USART_CR3_RTSE ((uint16_t)0x0100) 06428 #define USART_CR3_CTSE ((uint16_t)0x0200) 06429 #define USART_CR3_CTSIE ((uint16_t)0x0400) 06430 #define USART_CR3_ONEBIT ((uint16_t)0x0800) 06432 /****************** Bit definition for USART_GTPR register ******************/ 06433 #define USART_GTPR_PSC ((uint16_t)0x00FF) 06434 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) 06435 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) 06436 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) 06437 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) 06438 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) 06439 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) 06440 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) 06441 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) 06443 #define USART_GTPR_GT ((uint16_t)0xFF00) 06445 /******************************************************************************/ 06446 /* */ 06447 /* Window WATCHDOG */ 06448 /* */ 06449 /******************************************************************************/ 06450 /******************* Bit definition for WWDG_CR register ********************/ 06451 #define WWDG_CR_T ((uint8_t)0x7F) 06452 #define WWDG_CR_T0 ((uint8_t)0x01) 06453 #define WWDG_CR_T1 ((uint8_t)0x02) 06454 #define WWDG_CR_T2 ((uint8_t)0x04) 06455 #define WWDG_CR_T3 ((uint8_t)0x08) 06456 #define WWDG_CR_T4 ((uint8_t)0x10) 06457 #define WWDG_CR_T5 ((uint8_t)0x20) 06458 #define WWDG_CR_T6 ((uint8_t)0x40) 06460 #define WWDG_CR_WDGA ((uint8_t)0x80) 06462 /******************* Bit definition for WWDG_CFR register *******************/ 06463 #define WWDG_CFR_W ((uint16_t)0x007F) 06464 #define WWDG_CFR_W0 ((uint16_t)0x0001) 06465 #define WWDG_CFR_W1 ((uint16_t)0x0002) 06466 #define WWDG_CFR_W2 ((uint16_t)0x0004) 06467 #define WWDG_CFR_W3 ((uint16_t)0x0008) 06468 #define WWDG_CFR_W4 ((uint16_t)0x0010) 06469 #define WWDG_CFR_W5 ((uint16_t)0x0020) 06470 #define WWDG_CFR_W6 ((uint16_t)0x0040) 06472 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) 06473 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) 06474 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) 06476 #define WWDG_CFR_EWI ((uint16_t)0x0200) 06478 /******************* Bit definition for WWDG_SR register ********************/ 06479 #define WWDG_SR_EWIF ((uint8_t)0x01) 06482 /******************************************************************************/ 06483 /* */ 06484 /* DBG */ 06485 /* */ 06486 /******************************************************************************/ 06487 /******************** Bit definition for DBGMCU_IDCODE register *************/ 06488 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 06489 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 06490 06491 /******************** Bit definition for DBGMCU_CR register *****************/ 06492 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 06493 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 06494 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 06495 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 06496 06497 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 06498 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) 06499 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) 06501 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 06502 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) 06503 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) 06504 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) 06505 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) 06506 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) 06507 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) 06508 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) 06509 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) 06510 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) 06511 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) 06512 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) 06513 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) 06514 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) 06515 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) 06516 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) 06517 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) 06518 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) 06519 /* Old IWDGSTOP bit definition, maintained for legacy purpose */ 06520 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP 06521 06522 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 06523 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) 06524 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) 06525 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) 06526 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) 06527 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) 06528 06529 /******************************************************************************/ 06530 /* */ 06531 /* Ethernet MAC Registers bits definitions */ 06532 /* */ 06533 /******************************************************************************/ 06534 /* Bit definition for Ethernet MAC Control Register register */ 06535 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ 06536 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ 06537 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ 06538 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ 06539 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ 06540 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ 06541 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ 06542 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ 06543 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ 06544 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ 06545 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ 06546 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ 06547 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ 06548 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ 06549 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ 06550 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ 06551 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ 06552 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ 06553 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ 06554 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling 06555 a transmission attempt during retries after a collision: 0 =< r <2^k */ 06556 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ 06557 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ 06558 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ 06559 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ 06560 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ 06561 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ 06562 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ 06563 06564 /* Bit definition for Ethernet MAC Frame Filter Register */ 06565 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ 06566 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ 06567 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ 06568 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ 06569 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ 06570 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ 06571 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ 06572 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ 06573 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ 06574 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ 06575 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ 06576 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ 06577 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ 06578 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ 06579 06580 /* Bit definition for Ethernet MAC Hash Table High Register */ 06581 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ 06582 06583 /* Bit definition for Ethernet MAC Hash Table Low Register */ 06584 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ 06585 06586 /* Bit definition for Ethernet MAC MII Address Register */ 06587 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ 06588 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ 06589 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ 06590 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ 06591 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */ 06592 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ 06593 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ 06594 #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ 06595 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ 06596 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ 06597 06598 /* Bit definition for Ethernet MAC MII Data Register */ 06599 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ 06600 06601 /* Bit definition for Ethernet MAC Flow Control Register */ 06602 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ 06603 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ 06604 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ 06605 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ 06606 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ 06607 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ 06608 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ 06609 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ 06610 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ 06611 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ 06612 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ 06613 06614 /* Bit definition for Ethernet MAC VLAN Tag Register */ 06615 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ 06616 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ 06617 06618 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 06619 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ 06620 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. 06621 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ 06622 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask 06623 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask 06624 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask 06625 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask 06626 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 06627 RSVD - Filter1 Command - RSVD - Filter0 Command 06628 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset 06629 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 06630 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ 06631 06632 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 06633 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ 06634 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ 06635 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ 06636 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ 06637 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ 06638 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ 06639 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ 06640 06641 /* Bit definition for Ethernet MAC Status Register */ 06642 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ 06643 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ 06644 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ 06645 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ 06646 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ 06647 06648 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 06649 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ 06650 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ 06651 06652 /* Bit definition for Ethernet MAC Address0 High Register */ 06653 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ 06654 06655 /* Bit definition for Ethernet MAC Address0 Low Register */ 06656 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ 06657 06658 /* Bit definition for Ethernet MAC Address1 High Register */ 06659 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ 06660 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ 06661 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ 06662 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06663 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06664 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06665 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06666 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06667 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ 06668 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 06669 06670 /* Bit definition for Ethernet MAC Address1 Low Register */ 06671 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ 06672 06673 /* Bit definition for Ethernet MAC Address2 High Register */ 06674 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ 06675 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ 06676 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 06677 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06678 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06679 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06680 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06681 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06682 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 06683 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 06684 06685 /* Bit definition for Ethernet MAC Address2 Low Register */ 06686 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ 06687 06688 /* Bit definition for Ethernet MAC Address3 High Register */ 06689 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ 06690 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ 06691 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 06692 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06693 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06694 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06695 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06696 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06697 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 06698 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ 06699 06700 /* Bit definition for Ethernet MAC Address3 Low Register */ 06701 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ 06702 06703 /******************************************************************************/ 06704 /* Ethernet MMC Registers bits definition */ 06705 /******************************************************************************/ 06706 06707 /* Bit definition for Ethernet MMC Contol Register */ 06708 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */ 06709 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */ 06710 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ 06711 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ 06712 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ 06713 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ 06714 06715 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 06716 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ 06717 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ 06718 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ 06719 06720 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 06721 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ 06722 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ 06723 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ 06724 06725 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 06726 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ 06727 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ 06728 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ 06729 06730 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 06731 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ 06732 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ 06733 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ 06734 06735 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ 06736 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ 06737 06738 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ 06739 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ 06740 06741 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ 06742 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ 06743 06744 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ 06745 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ 06746 06747 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ 06748 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ 06749 06750 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ 06751 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ 06752 06753 /******************************************************************************/ 06754 /* Ethernet PTP Registers bits definition */ 06755 /******************************************************************************/ 06756 06757 /* Bit definition for Ethernet PTP Time Stamp Contol Register */ 06758 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ 06759 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ 06760 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ 06761 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ 06762 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ 06763 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ 06764 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ 06765 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ 06766 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ 06767 06768 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ 06769 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ 06770 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ 06771 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ 06772 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ 06773 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ 06774 06775 /* Bit definition for Ethernet PTP Sub-Second Increment Register */ 06776 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ 06777 06778 /* Bit definition for Ethernet PTP Time Stamp High Register */ 06779 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ 06780 06781 /* Bit definition for Ethernet PTP Time Stamp Low Register */ 06782 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ 06783 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ 06784 06785 /* Bit definition for Ethernet PTP Time Stamp High Update Register */ 06786 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ 06787 06788 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ 06789 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ 06790 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ 06791 06792 /* Bit definition for Ethernet PTP Time Stamp Addend Register */ 06793 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ 06794 06795 /* Bit definition for Ethernet PTP Target Time High Register */ 06796 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ 06797 06798 /* Bit definition for Ethernet PTP Target Time Low Register */ 06799 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ 06800 06801 /* Bit definition for Ethernet PTP Time Stamp Status Register */ 06802 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ 06803 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ 06804 06805 /******************************************************************************/ 06806 /* Ethernet DMA Registers bits definition */ 06807 /******************************************************************************/ 06808 06809 /* Bit definition for Ethernet DMA Bus Mode Register */ 06810 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ 06811 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ 06812 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ 06813 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ 06814 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ 06815 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ 06816 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 06817 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 06818 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 06819 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 06820 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 06821 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 06822 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 06823 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 06824 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ 06825 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ 06826 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ 06827 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 06828 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ 06829 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ 06830 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ 06831 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 06832 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ 06833 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 06834 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 06835 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 06836 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 06837 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 06838 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 06839 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 06840 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 06841 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 06842 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 06843 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 06844 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 06845 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ 06846 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ 06847 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ 06848 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ 06849 06850 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ 06851 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ 06852 06853 /* Bit definition for Ethernet DMA Receive Poll Demand Register */ 06854 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ 06855 06856 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ 06857 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ 06858 06859 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ 06860 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ 06861 06862 /* Bit definition for Ethernet DMA Status Register */ 06863 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ 06864 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ 06865 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ 06866 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ 06867 /* combination with EBS[2:0] for GetFlagStatus function */ 06868 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ 06869 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ 06870 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ 06871 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ 06872 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ 06873 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ 06874 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ 06875 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ 06876 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ 06877 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ 06878 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ 06879 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ 06880 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ 06881 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ 06882 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ 06883 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ 06884 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ 06885 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ 06886 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ 06887 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ 06888 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ 06889 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ 06890 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ 06891 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ 06892 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ 06893 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ 06894 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ 06895 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ 06896 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ 06897 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ 06898 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ 06899 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ 06900 06901 /* Bit definition for Ethernet DMA Operation Mode Register */ 06902 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ 06903 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ 06904 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ 06905 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ 06906 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ 06907 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ 06908 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ 06909 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ 06910 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ 06911 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ 06912 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ 06913 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ 06914 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ 06915 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ 06916 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ 06917 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ 06918 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ 06919 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ 06920 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ 06921 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ 06922 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ 06923 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ 06924 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ 06925 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ 06926 06927 /* Bit definition for Ethernet DMA Interrupt Enable Register */ 06928 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ 06929 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ 06930 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ 06931 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ 06932 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ 06933 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ 06934 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ 06935 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ 06936 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ 06937 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ 06938 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ 06939 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ 06940 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ 06941 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ 06942 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ 06943 06944 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ 06945 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ 06946 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ 06947 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ 06948 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ 06949 06950 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ 06951 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ 06952 06953 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ 06954 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ 06955 06956 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ 06957 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ 06958 06959 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ 06960 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ 06961 06970 #ifdef USE_STDPERIPH_DRIVER 06971 #include "stm32f4xx_conf.h" 06972 #endif /* USE_STDPERIPH_DRIVER */ 06973 06978 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 06979 06980 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 06981 06982 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 06983 06984 #define CLEAR_REG(REG) ((REG) = (0x0)) 06985 06986 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 06987 06988 #define READ_REG(REG) ((REG)) 06989 06990 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 06991 06996 #ifdef __cplusplus 06997 } 06998 #endif /* __cplusplus */ 06999 07000 #endif /* __STM32F4xx_H */ 07001 07010 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/