Peripheral_Registers_Bits_Definition

Collaboration diagram for Peripheral_Registers_Bits_Definition:

Defines
#define	CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
#define	CRC_IDR_IDR   ((uint8_t)0xFF)
#define	CRC_CR_RESET   ((uint8_t)0x01)
#define	PWR_CR_LPDS   ((uint16_t)0x0001)
#define	PWR_CR_PDDS   ((uint16_t)0x0002)
#define	PWR_CR_CWUF   ((uint16_t)0x0004)
#define	PWR_CR_CSBF   ((uint16_t)0x0008)
#define	PWR_CR_PVDE   ((uint16_t)0x0010)
#define	PWR_CR_PLS   ((uint16_t)0x00E0)
#define	PWR_CR_PLS_0   ((uint16_t)0x0020)
#define	PWR_CR_PLS_1   ((uint16_t)0x0040)
#define	PWR_CR_PLS_2   ((uint16_t)0x0080)
#define	PWR_CR_PLS_2V2   ((uint16_t)0x0000)
#define	PWR_CR_PLS_2V3   ((uint16_t)0x0020)
#define	PWR_CR_PLS_2V4   ((uint16_t)0x0040)
#define	PWR_CR_PLS_2V5   ((uint16_t)0x0060)
#define	PWR_CR_PLS_2V6   ((uint16_t)0x0080)
#define	PWR_CR_PLS_2V7   ((uint16_t)0x00A0)
#define	PWR_CR_PLS_2V8   ((uint16_t)0x00C0)
#define	PWR_CR_PLS_2V9   ((uint16_t)0x00E0)
#define	PWR_CR_DBP   ((uint16_t)0x0100)
#define	PWR_CSR_WUF   ((uint16_t)0x0001)
#define	PWR_CSR_SBF   ((uint16_t)0x0002)
#define	PWR_CSR_PVDO   ((uint16_t)0x0004)
#define	PWR_CSR_EWUP   ((uint16_t)0x0100)
#define	BKP_DR1_D   ((uint16_t)0xFFFF)
#define	BKP_DR2_D   ((uint16_t)0xFFFF)
#define	BKP_DR3_D   ((uint16_t)0xFFFF)
#define	BKP_DR4_D   ((uint16_t)0xFFFF)
#define	BKP_DR5_D   ((uint16_t)0xFFFF)
#define	BKP_DR6_D   ((uint16_t)0xFFFF)
#define	BKP_DR7_D   ((uint16_t)0xFFFF)
#define	BKP_DR8_D   ((uint16_t)0xFFFF)
#define	BKP_DR9_D   ((uint16_t)0xFFFF)
#define	BKP_DR10_D   ((uint16_t)0xFFFF)
#define	BKP_DR11_D   ((uint16_t)0xFFFF)
#define	BKP_DR12_D   ((uint16_t)0xFFFF)
#define	BKP_DR13_D   ((uint16_t)0xFFFF)
#define	BKP_DR14_D   ((uint16_t)0xFFFF)
#define	BKP_DR15_D   ((uint16_t)0xFFFF)
#define	BKP_DR16_D   ((uint16_t)0xFFFF)
#define	BKP_DR17_D   ((uint16_t)0xFFFF)
#define	BKP_DR18_D   ((uint16_t)0xFFFF)
#define	BKP_DR19_D   ((uint16_t)0xFFFF)
#define	BKP_DR20_D   ((uint16_t)0xFFFF)
#define	BKP_DR21_D   ((uint16_t)0xFFFF)
#define	BKP_DR22_D   ((uint16_t)0xFFFF)
#define	BKP_DR23_D   ((uint16_t)0xFFFF)
#define	BKP_DR24_D   ((uint16_t)0xFFFF)
#define	BKP_DR25_D   ((uint16_t)0xFFFF)
#define	BKP_DR26_D   ((uint16_t)0xFFFF)
#define	BKP_DR27_D   ((uint16_t)0xFFFF)
#define	BKP_DR28_D   ((uint16_t)0xFFFF)
#define	BKP_DR29_D   ((uint16_t)0xFFFF)
#define	BKP_DR30_D   ((uint16_t)0xFFFF)
#define	BKP_DR31_D   ((uint16_t)0xFFFF)
#define	BKP_DR32_D   ((uint16_t)0xFFFF)
#define	BKP_DR33_D   ((uint16_t)0xFFFF)
#define	BKP_DR34_D   ((uint16_t)0xFFFF)
#define	BKP_DR35_D   ((uint16_t)0xFFFF)
#define	BKP_DR36_D   ((uint16_t)0xFFFF)
#define	BKP_DR37_D   ((uint16_t)0xFFFF)
#define	BKP_DR38_D   ((uint16_t)0xFFFF)
#define	BKP_DR39_D   ((uint16_t)0xFFFF)
#define	BKP_DR40_D   ((uint16_t)0xFFFF)
#define	BKP_DR41_D   ((uint16_t)0xFFFF)
#define	BKP_DR42_D   ((uint16_t)0xFFFF)
#define	BKP_RTCCR_CAL   ((uint16_t)0x007F)
#define	BKP_RTCCR_CCO   ((uint16_t)0x0080)
#define	BKP_RTCCR_ASOE   ((uint16_t)0x0100)
#define	BKP_RTCCR_ASOS   ((uint16_t)0x0200)
#define	BKP_CR_TPE   ((uint8_t)0x01)
#define	BKP_CR_TPAL   ((uint8_t)0x02)
#define	BKP_CSR_CTE   ((uint16_t)0x0001)
#define	BKP_CSR_CTI   ((uint16_t)0x0002)
#define	BKP_CSR_TPIE   ((uint16_t)0x0004)
#define	BKP_CSR_TEF   ((uint16_t)0x0100)
#define	BKP_CSR_TIF   ((uint16_t)0x0200)
#define	RCC_CR_HSION   ((uint32_t)0x00000001)
#define	RCC_CR_HSIRDY   ((uint32_t)0x00000002)
#define	RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
#define	RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
#define	RCC_CR_HSEON   ((uint32_t)0x00010000)
#define	RCC_CR_HSERDY   ((uint32_t)0x00020000)
#define	RCC_CR_HSEBYP   ((uint32_t)0x00040000)
#define	RCC_CR_CSSON   ((uint32_t)0x00080000)
#define	RCC_CR_PLLON   ((uint32_t)0x01000000)
#define	RCC_CR_PLLRDY   ((uint32_t)0x02000000)
#define	RCC_CFGR_SW   ((uint32_t)0x00000003)
#define	RCC_CFGR_SW_0   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_1   ((uint32_t)0x00000002)
#define	RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
#define	RCC_CFGR_SWS   ((uint32_t)0x0000000C)
#define	RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
#define	RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
#define	RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
#define	RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
#define	RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
#define	RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
#define	RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
#define	RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
#define	RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
#define	RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
#define	RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
#define	RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
#define	RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
#define	RCC_CFGR_PPRE1   ((uint32_t)0x00000700)
#define	RCC_CFGR_PPRE1_0   ((uint32_t)0x00000100)
#define	RCC_CFGR_PPRE1_1   ((uint32_t)0x00000200)
#define	RCC_CFGR_PPRE1_2   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00000500)
#define	RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00000600)
#define	RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00000700)
#define	RCC_CFGR_PPRE2   ((uint32_t)0x00003800)
#define	RCC_CFGR_PPRE2_0   ((uint32_t)0x00000800)
#define	RCC_CFGR_PPRE2_1   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE2_2   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x00002800)
#define	RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x00003000)
#define	RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x00003800)
#define	RCC_CFGR_ADCPRE   ((uint32_t)0x0000C000)
#define	RCC_CFGR_ADCPRE_0   ((uint32_t)0x00004000)
#define	RCC_CFGR_ADCPRE_1   ((uint32_t)0x00008000)
#define	RCC_CFGR_ADCPRE_DIV2   ((uint32_t)0x00000000)
#define	RCC_CFGR_ADCPRE_DIV4   ((uint32_t)0x00004000)
#define	RCC_CFGR_ADCPRE_DIV6   ((uint32_t)0x00008000)
#define	RCC_CFGR_ADCPRE_DIV8   ((uint32_t)0x0000C000)
#define	RCC_CFGR_PLLSRC   ((uint32_t)0x00010000)
#define	RCC_CFGR_PLLXTPRE   ((uint32_t)0x00020000)
#define	RCC_CFGR_PLLMULL   ((uint32_t)0x003C0000)
#define	RCC_CFGR_PLLMULL_0   ((uint32_t)0x00040000)
#define	RCC_CFGR_PLLMULL_1   ((uint32_t)0x00080000)
#define	RCC_CFGR_PLLMULL_2   ((uint32_t)0x00100000)
#define	RCC_CFGR_PLLMULL_3   ((uint32_t)0x00200000)
#define	RCC_CFGR_PLLSRC_HSI_Div2   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLSRC_HSE   ((uint32_t)0x00010000)
#define	RCC_CFGR_PLLXTPRE_HSE   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLXTPRE_HSE_Div2   ((uint32_t)0x00020000)
#define	RCC_CFGR_PLLMULL2   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLMULL3   ((uint32_t)0x00040000)
#define	RCC_CFGR_PLLMULL4   ((uint32_t)0x00080000)
#define	RCC_CFGR_PLLMULL5   ((uint32_t)0x000C0000)
#define	RCC_CFGR_PLLMULL6   ((uint32_t)0x00100000)
#define	RCC_CFGR_PLLMULL7   ((uint32_t)0x00140000)
#define	RCC_CFGR_PLLMULL8   ((uint32_t)0x00180000)
#define	RCC_CFGR_PLLMULL9   ((uint32_t)0x001C0000)
#define	RCC_CFGR_PLLMULL10   ((uint32_t)0x00200000)
#define	RCC_CFGR_PLLMULL11   ((uint32_t)0x00240000)
#define	RCC_CFGR_PLLMULL12   ((uint32_t)0x00280000)
#define	RCC_CFGR_PLLMULL13   ((uint32_t)0x002C0000)
#define	RCC_CFGR_PLLMULL14   ((uint32_t)0x00300000)
#define	RCC_CFGR_PLLMULL15   ((uint32_t)0x00340000)
#define	RCC_CFGR_PLLMULL16   ((uint32_t)0x00380000)
#define	RCC_CFGR_USBPRE   ((uint32_t)0x00400000)
#define	RCC_CFGR_MCO   ((uint32_t)0x07000000)
#define	RCC_CFGR_MCO_0   ((uint32_t)0x01000000)
#define	RCC_CFGR_MCO_1   ((uint32_t)0x02000000)
#define	RCC_CFGR_MCO_2   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO_NOCLOCK   ((uint32_t)0x00000000)
#define	RCC_CFGR_MCO_SYSCLK   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO_HSI   ((uint32_t)0x05000000)
#define	RCC_CFGR_MCO_HSE   ((uint32_t)0x06000000)
#define	RCC_CFGR_MCO_PLL   ((uint32_t)0x07000000)
#define	RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
#define	RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
#define	RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
#define	RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
#define	RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
#define	RCC_CIR_CSSF   ((uint32_t)0x00000080)
#define	RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
#define	RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
#define	RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
#define	RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
#define	RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
#define	RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
#define	RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
#define	RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
#define	RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
#define	RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
#define	RCC_CIR_CSSC   ((uint32_t)0x00800000)
#define	RCC_APB2RSTR_AFIORST   ((uint32_t)0x00000001)
#define	RCC_APB2RSTR_IOPARST   ((uint32_t)0x00000004)
#define	RCC_APB2RSTR_IOPBRST   ((uint32_t)0x00000008)
#define	RCC_APB2RSTR_IOPCRST   ((uint32_t)0x00000010)
#define	RCC_APB2RSTR_IOPDRST   ((uint32_t)0x00000020)
#define	RCC_APB2RSTR_ADC1RST   ((uint32_t)0x00000200)
#define	RCC_APB2RSTR_ADC2RST   ((uint32_t)0x00000400)
#define	RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000800)
#define	RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
#define	RCC_APB2RSTR_USART1RST   ((uint32_t)0x00004000)
#define	RCC_APB2RSTR_IOPERST   ((uint32_t)0x00000040)
#define	RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
#define	RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)
#define	RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
#define	RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
#define	RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
#define	RCC_APB1RSTR_BKPRST   ((uint32_t)0x08000000)
#define	RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
#define	RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
#define	RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)
#define	RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
#define	RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
#define	RCC_AHBENR_DMA1EN   ((uint16_t)0x0001)
#define	RCC_AHBENR_SRAMEN   ((uint16_t)0x0004)
#define	RCC_AHBENR_FLITFEN   ((uint16_t)0x0010)
#define	RCC_AHBENR_CRCEN   ((uint16_t)0x0040)
#define	RCC_APB2ENR_AFIOEN   ((uint32_t)0x00000001)
#define	RCC_APB2ENR_IOPAEN   ((uint32_t)0x00000004)
#define	RCC_APB2ENR_IOPBEN   ((uint32_t)0x00000008)
#define	RCC_APB2ENR_IOPCEN   ((uint32_t)0x00000010)
#define	RCC_APB2ENR_IOPDEN   ((uint32_t)0x00000020)
#define	RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000200)
#define	RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000400)
#define	RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000800)
#define	RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
#define	RCC_APB2ENR_USART1EN   ((uint32_t)0x00004000)
#define	RCC_APB2ENR_IOPEEN   ((uint32_t)0x00000040)
#define	RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
#define	RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
#define	RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
#define	RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
#define	RCC_APB1ENR_BKPEN   ((uint32_t)0x08000000)
#define	RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
#define	RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
#define	RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
#define	RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
#define	RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
#define	RCC_BDCR_LSEON   ((uint32_t)0x00000001)
#define	RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
#define	RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
#define	RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
#define	RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
#define	RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
#define	RCC_BDCR_RTCSEL_NOCLOCK   ((uint32_t)0x00000000)
#define	RCC_BDCR_RTCSEL_LSE   ((uint32_t)0x00000100)
#define	RCC_BDCR_RTCSEL_LSI   ((uint32_t)0x00000200)
#define	RCC_BDCR_RTCSEL_HSE   ((uint32_t)0x00000300)
#define	RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
#define	RCC_BDCR_BDRST   ((uint32_t)0x00010000)
#define	RCC_CSR_LSION   ((uint32_t)0x00000001)
#define	RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
#define	RCC_CSR_RMVF   ((uint32_t)0x01000000)
#define	RCC_CSR_PINRSTF   ((uint32_t)0x04000000)
#define	RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
#define	RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
#define	RCC_CSR_IWDGRSTF   ((uint32_t)0x20000000)
#define	RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
#define	RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
#define	GPIO_CRL_MODE   ((uint32_t)0x33333333)
#define	GPIO_CRL_MODE0   ((uint32_t)0x00000003)
#define	GPIO_CRL_MODE0_0   ((uint32_t)0x00000001)
#define	GPIO_CRL_MODE0_1   ((uint32_t)0x00000002)
#define	GPIO_CRL_MODE1   ((uint32_t)0x00000030)
#define	GPIO_CRL_MODE1_0   ((uint32_t)0x00000010)
#define	GPIO_CRL_MODE1_1   ((uint32_t)0x00000020)
#define	GPIO_CRL_MODE2   ((uint32_t)0x00000300)
#define	GPIO_CRL_MODE2_0   ((uint32_t)0x00000100)
#define	GPIO_CRL_MODE2_1   ((uint32_t)0x00000200)
#define	GPIO_CRL_MODE3   ((uint32_t)0x00003000)
#define	GPIO_CRL_MODE3_0   ((uint32_t)0x00001000)
#define	GPIO_CRL_MODE3_1   ((uint32_t)0x00002000)
#define	GPIO_CRL_MODE4   ((uint32_t)0x00030000)
#define	GPIO_CRL_MODE4_0   ((uint32_t)0x00010000)
#define	GPIO_CRL_MODE4_1   ((uint32_t)0x00020000)
#define	GPIO_CRL_MODE5   ((uint32_t)0x00300000)
#define	GPIO_CRL_MODE5_0   ((uint32_t)0x00100000)
#define	GPIO_CRL_MODE5_1   ((uint32_t)0x00200000)
#define	GPIO_CRL_MODE6   ((uint32_t)0x03000000)
#define	GPIO_CRL_MODE6_0   ((uint32_t)0x01000000)
#define	GPIO_CRL_MODE6_1   ((uint32_t)0x02000000)
#define	GPIO_CRL_MODE7   ((uint32_t)0x30000000)
#define	GPIO_CRL_MODE7_0   ((uint32_t)0x10000000)
#define	GPIO_CRL_MODE7_1   ((uint32_t)0x20000000)
#define	GPIO_CRL_CNF   ((uint32_t)0xCCCCCCCC)
#define	GPIO_CRL_CNF0   ((uint32_t)0x0000000C)
#define	GPIO_CRL_CNF0_0   ((uint32_t)0x00000004)
#define	GPIO_CRL_CNF0_1   ((uint32_t)0x00000008)
#define	GPIO_CRL_CNF1   ((uint32_t)0x000000C0)
#define	GPIO_CRL_CNF1_0   ((uint32_t)0x00000040)
#define	GPIO_CRL_CNF1_1   ((uint32_t)0x00000080)
#define	GPIO_CRL_CNF2   ((uint32_t)0x00000C00)
#define	GPIO_CRL_CNF2_0   ((uint32_t)0x00000400)
#define	GPIO_CRL_CNF2_1   ((uint32_t)0x00000800)
#define	GPIO_CRL_CNF3   ((uint32_t)0x0000C000)
#define	GPIO_CRL_CNF3_0   ((uint32_t)0x00004000)
#define	GPIO_CRL_CNF3_1   ((uint32_t)0x00008000)
#define	GPIO_CRL_CNF4   ((uint32_t)0x000C0000)
#define	GPIO_CRL_CNF4_0   ((uint32_t)0x00040000)
#define	GPIO_CRL_CNF4_1   ((uint32_t)0x00080000)
#define	GPIO_CRL_CNF5   ((uint32_t)0x00C00000)
#define	GPIO_CRL_CNF5_0   ((uint32_t)0x00400000)
#define	GPIO_CRL_CNF5_1   ((uint32_t)0x00800000)
#define	GPIO_CRL_CNF6   ((uint32_t)0x0C000000)
#define	GPIO_CRL_CNF6_0   ((uint32_t)0x04000000)
#define	GPIO_CRL_CNF6_1   ((uint32_t)0x08000000)
#define	GPIO_CRL_CNF7   ((uint32_t)0xC0000000)
#define	GPIO_CRL_CNF7_0   ((uint32_t)0x40000000)
#define	GPIO_CRL_CNF7_1   ((uint32_t)0x80000000)
#define	GPIO_CRH_MODE   ((uint32_t)0x33333333)
#define	GPIO_CRH_MODE8   ((uint32_t)0x00000003)
#define	GPIO_CRH_MODE8_0   ((uint32_t)0x00000001)
#define	GPIO_CRH_MODE8_1   ((uint32_t)0x00000002)
#define	GPIO_CRH_MODE9   ((uint32_t)0x00000030)
#define	GPIO_CRH_MODE9_0   ((uint32_t)0x00000010)
#define	GPIO_CRH_MODE9_1   ((uint32_t)0x00000020)
#define	GPIO_CRH_MODE10   ((uint32_t)0x00000300)
#define	GPIO_CRH_MODE10_0   ((uint32_t)0x00000100)
#define	GPIO_CRH_MODE10_1   ((uint32_t)0x00000200)
#define	GPIO_CRH_MODE11   ((uint32_t)0x00003000)
#define	GPIO_CRH_MODE11_0   ((uint32_t)0x00001000)
#define	GPIO_CRH_MODE11_1   ((uint32_t)0x00002000)
#define	GPIO_CRH_MODE12   ((uint32_t)0x00030000)
#define	GPIO_CRH_MODE12_0   ((uint32_t)0x00010000)
#define	GPIO_CRH_MODE12_1   ((uint32_t)0x00020000)
#define	GPIO_CRH_MODE13   ((uint32_t)0x00300000)
#define	GPIO_CRH_MODE13_0   ((uint32_t)0x00100000)
#define	GPIO_CRH_MODE13_1   ((uint32_t)0x00200000)
#define	GPIO_CRH_MODE14   ((uint32_t)0x03000000)
#define	GPIO_CRH_MODE14_0   ((uint32_t)0x01000000)
#define	GPIO_CRH_MODE14_1   ((uint32_t)0x02000000)
#define	GPIO_CRH_MODE15   ((uint32_t)0x30000000)
#define	GPIO_CRH_MODE15_0   ((uint32_t)0x10000000)
#define	GPIO_CRH_MODE15_1   ((uint32_t)0x20000000)
#define	GPIO_CRH_CNF   ((uint32_t)0xCCCCCCCC)
#define	GPIO_CRH_CNF8   ((uint32_t)0x0000000C)
#define	GPIO_CRH_CNF8_0   ((uint32_t)0x00000004)
#define	GPIO_CRH_CNF8_1   ((uint32_t)0x00000008)
#define	GPIO_CRH_CNF9   ((uint32_t)0x000000C0)
#define	GPIO_CRH_CNF9_0   ((uint32_t)0x00000040)
#define	GPIO_CRH_CNF9_1   ((uint32_t)0x00000080)
#define	GPIO_CRH_CNF10   ((uint32_t)0x00000C00)
#define	GPIO_CRH_CNF10_0   ((uint32_t)0x00000400)
#define	GPIO_CRH_CNF10_1   ((uint32_t)0x00000800)
#define	GPIO_CRH_CNF11   ((uint32_t)0x0000C000)
#define	GPIO_CRH_CNF11_0   ((uint32_t)0x00004000)
#define	GPIO_CRH_CNF11_1   ((uint32_t)0x00008000)
#define	GPIO_CRH_CNF12   ((uint32_t)0x000C0000)
#define	GPIO_CRH_CNF12_0   ((uint32_t)0x00040000)
#define	GPIO_CRH_CNF12_1   ((uint32_t)0x00080000)
#define	GPIO_CRH_CNF13   ((uint32_t)0x00C00000)
#define	GPIO_CRH_CNF13_0   ((uint32_t)0x00400000)
#define	GPIO_CRH_CNF13_1   ((uint32_t)0x00800000)
#define	GPIO_CRH_CNF14   ((uint32_t)0x0C000000)
#define	GPIO_CRH_CNF14_0   ((uint32_t)0x04000000)
#define	GPIO_CRH_CNF14_1   ((uint32_t)0x08000000)
#define	GPIO_CRH_CNF15   ((uint32_t)0xC0000000)
#define	GPIO_CRH_CNF15_0   ((uint32_t)0x40000000)
#define	GPIO_CRH_CNF15_1   ((uint32_t)0x80000000)
#define	GPIO_IDR_IDR0   ((uint16_t)0x0001)
#define	GPIO_IDR_IDR1   ((uint16_t)0x0002)
#define	GPIO_IDR_IDR2   ((uint16_t)0x0004)
#define	GPIO_IDR_IDR3   ((uint16_t)0x0008)
#define	GPIO_IDR_IDR4   ((uint16_t)0x0010)
#define	GPIO_IDR_IDR5   ((uint16_t)0x0020)
#define	GPIO_IDR_IDR6   ((uint16_t)0x0040)
#define	GPIO_IDR_IDR7   ((uint16_t)0x0080)
#define	GPIO_IDR_IDR8   ((uint16_t)0x0100)
#define	GPIO_IDR_IDR9   ((uint16_t)0x0200)
#define	GPIO_IDR_IDR10   ((uint16_t)0x0400)
#define	GPIO_IDR_IDR11   ((uint16_t)0x0800)
#define	GPIO_IDR_IDR12   ((uint16_t)0x1000)
#define	GPIO_IDR_IDR13   ((uint16_t)0x2000)
#define	GPIO_IDR_IDR14   ((uint16_t)0x4000)
#define	GPIO_IDR_IDR15   ((uint16_t)0x8000)
#define	GPIO_ODR_ODR0   ((uint16_t)0x0001)
#define	GPIO_ODR_ODR1   ((uint16_t)0x0002)
#define	GPIO_ODR_ODR2   ((uint16_t)0x0004)
#define	GPIO_ODR_ODR3   ((uint16_t)0x0008)
#define	GPIO_ODR_ODR4   ((uint16_t)0x0010)
#define	GPIO_ODR_ODR5   ((uint16_t)0x0020)
#define	GPIO_ODR_ODR6   ((uint16_t)0x0040)
#define	GPIO_ODR_ODR7   ((uint16_t)0x0080)
#define	GPIO_ODR_ODR8   ((uint16_t)0x0100)
#define	GPIO_ODR_ODR9   ((uint16_t)0x0200)
#define	GPIO_ODR_ODR10   ((uint16_t)0x0400)
#define	GPIO_ODR_ODR11   ((uint16_t)0x0800)
#define	GPIO_ODR_ODR12   ((uint16_t)0x1000)
#define	GPIO_ODR_ODR13   ((uint16_t)0x2000)
#define	GPIO_ODR_ODR14   ((uint16_t)0x4000)
#define	GPIO_ODR_ODR15   ((uint16_t)0x8000)
#define	GPIO_BSRR_BS0   ((uint32_t)0x00000001)
#define	GPIO_BSRR_BS1   ((uint32_t)0x00000002)
#define	GPIO_BSRR_BS2   ((uint32_t)0x00000004)
#define	GPIO_BSRR_BS3   ((uint32_t)0x00000008)
#define	GPIO_BSRR_BS4   ((uint32_t)0x00000010)
#define	GPIO_BSRR_BS5   ((uint32_t)0x00000020)
#define	GPIO_BSRR_BS6   ((uint32_t)0x00000040)
#define	GPIO_BSRR_BS7   ((uint32_t)0x00000080)
#define	GPIO_BSRR_BS8   ((uint32_t)0x00000100)
#define	GPIO_BSRR_BS9   ((uint32_t)0x00000200)
#define	GPIO_BSRR_BS10   ((uint32_t)0x00000400)
#define	GPIO_BSRR_BS11   ((uint32_t)0x00000800)
#define	GPIO_BSRR_BS12   ((uint32_t)0x00001000)
#define	GPIO_BSRR_BS13   ((uint32_t)0x00002000)
#define	GPIO_BSRR_BS14   ((uint32_t)0x00004000)
#define	GPIO_BSRR_BS15   ((uint32_t)0x00008000)
#define	GPIO_BSRR_BR0   ((uint32_t)0x00010000)
#define	GPIO_BSRR_BR1   ((uint32_t)0x00020000)
#define	GPIO_BSRR_BR2   ((uint32_t)0x00040000)
#define	GPIO_BSRR_BR3   ((uint32_t)0x00080000)
#define	GPIO_BSRR_BR4   ((uint32_t)0x00100000)
#define	GPIO_BSRR_BR5   ((uint32_t)0x00200000)
#define	GPIO_BSRR_BR6   ((uint32_t)0x00400000)
#define	GPIO_BSRR_BR7   ((uint32_t)0x00800000)
#define	GPIO_BSRR_BR8   ((uint32_t)0x01000000)
#define	GPIO_BSRR_BR9   ((uint32_t)0x02000000)
#define	GPIO_BSRR_BR10   ((uint32_t)0x04000000)
#define	GPIO_BSRR_BR11   ((uint32_t)0x08000000)
#define	GPIO_BSRR_BR12   ((uint32_t)0x10000000)
#define	GPIO_BSRR_BR13   ((uint32_t)0x20000000)
#define	GPIO_BSRR_BR14   ((uint32_t)0x40000000)
#define	GPIO_BSRR_BR15   ((uint32_t)0x80000000)
#define	GPIO_BRR_BR0   ((uint16_t)0x0001)
#define	GPIO_BRR_BR1   ((uint16_t)0x0002)
#define	GPIO_BRR_BR2   ((uint16_t)0x0004)
#define	GPIO_BRR_BR3   ((uint16_t)0x0008)
#define	GPIO_BRR_BR4   ((uint16_t)0x0010)
#define	GPIO_BRR_BR5   ((uint16_t)0x0020)
#define	GPIO_BRR_BR6   ((uint16_t)0x0040)
#define	GPIO_BRR_BR7   ((uint16_t)0x0080)
#define	GPIO_BRR_BR8   ((uint16_t)0x0100)
#define	GPIO_BRR_BR9   ((uint16_t)0x0200)
#define	GPIO_BRR_BR10   ((uint16_t)0x0400)
#define	GPIO_BRR_BR11   ((uint16_t)0x0800)
#define	GPIO_BRR_BR12   ((uint16_t)0x1000)
#define	GPIO_BRR_BR13   ((uint16_t)0x2000)
#define	GPIO_BRR_BR14   ((uint16_t)0x4000)
#define	GPIO_BRR_BR15   ((uint16_t)0x8000)
#define	GPIO_LCKR_LCK0   ((uint32_t)0x00000001)
#define	GPIO_LCKR_LCK1   ((uint32_t)0x00000002)
#define	GPIO_LCKR_LCK2   ((uint32_t)0x00000004)
#define	GPIO_LCKR_LCK3   ((uint32_t)0x00000008)
#define	GPIO_LCKR_LCK4   ((uint32_t)0x00000010)
#define	GPIO_LCKR_LCK5   ((uint32_t)0x00000020)
#define	GPIO_LCKR_LCK6   ((uint32_t)0x00000040)
#define	GPIO_LCKR_LCK7   ((uint32_t)0x00000080)
#define	GPIO_LCKR_LCK8   ((uint32_t)0x00000100)
#define	GPIO_LCKR_LCK9   ((uint32_t)0x00000200)
#define	GPIO_LCKR_LCK10   ((uint32_t)0x00000400)
#define	GPIO_LCKR_LCK11   ((uint32_t)0x00000800)
#define	GPIO_LCKR_LCK12   ((uint32_t)0x00001000)
#define	GPIO_LCKR_LCK13   ((uint32_t)0x00002000)
#define	GPIO_LCKR_LCK14   ((uint32_t)0x00004000)
#define	GPIO_LCKR_LCK15   ((uint32_t)0x00008000)
#define	GPIO_LCKR_LCKK   ((uint32_t)0x00010000)
#define	AFIO_EVCR_PIN   ((uint8_t)0x0F)
#define	AFIO_EVCR_PIN_0   ((uint8_t)0x01)
#define	AFIO_EVCR_PIN_1   ((uint8_t)0x02)
#define	AFIO_EVCR_PIN_2   ((uint8_t)0x04)
#define	AFIO_EVCR_PIN_3   ((uint8_t)0x08)
#define	AFIO_EVCR_PIN_PX0   ((uint8_t)0x00)
#define	AFIO_EVCR_PIN_PX1   ((uint8_t)0x01)
#define	AFIO_EVCR_PIN_PX2   ((uint8_t)0x02)
#define	AFIO_EVCR_PIN_PX3   ((uint8_t)0x03)
#define	AFIO_EVCR_PIN_PX4   ((uint8_t)0x04)
#define	AFIO_EVCR_PIN_PX5   ((uint8_t)0x05)
#define	AFIO_EVCR_PIN_PX6   ((uint8_t)0x06)
#define	AFIO_EVCR_PIN_PX7   ((uint8_t)0x07)
#define	AFIO_EVCR_PIN_PX8   ((uint8_t)0x08)
#define	AFIO_EVCR_PIN_PX9   ((uint8_t)0x09)
#define	AFIO_EVCR_PIN_PX10   ((uint8_t)0x0A)
#define	AFIO_EVCR_PIN_PX11   ((uint8_t)0x0B)
#define	AFIO_EVCR_PIN_PX12   ((uint8_t)0x0C)
#define	AFIO_EVCR_PIN_PX13   ((uint8_t)0x0D)
#define	AFIO_EVCR_PIN_PX14   ((uint8_t)0x0E)
#define	AFIO_EVCR_PIN_PX15   ((uint8_t)0x0F)
#define	AFIO_EVCR_PORT   ((uint8_t)0x70)
#define	AFIO_EVCR_PORT_0   ((uint8_t)0x10)
#define	AFIO_EVCR_PORT_1   ((uint8_t)0x20)
#define	AFIO_EVCR_PORT_2   ((uint8_t)0x40)
#define	AFIO_EVCR_PORT_PA   ((uint8_t)0x00)
#define	AFIO_EVCR_PORT_PB   ((uint8_t)0x10)
#define	AFIO_EVCR_PORT_PC   ((uint8_t)0x20)
#define	AFIO_EVCR_PORT_PD   ((uint8_t)0x30)
#define	AFIO_EVCR_PORT_PE   ((uint8_t)0x40)
#define	AFIO_EVCR_EVOE   ((uint8_t)0x80)
#define	AFIO_MAPR_SPI1_REMAP   ((uint32_t)0x00000001)
#define	AFIO_MAPR_I2C1_REMAP   ((uint32_t)0x00000002)
#define	AFIO_MAPR_USART1_REMAP   ((uint32_t)0x00000004)
#define	AFIO_MAPR_USART2_REMAP   ((uint32_t)0x00000008)
#define	AFIO_MAPR_USART3_REMAP   ((uint32_t)0x00000030)
#define	AFIO_MAPR_USART3_REMAP_0   ((uint32_t)0x00000010)
#define	AFIO_MAPR_USART3_REMAP_1   ((uint32_t)0x00000020)
#define	AFIO_MAPR_USART3_REMAP_NOREMAP   ((uint32_t)0x00000000)
#define	AFIO_MAPR_USART3_REMAP_PARTIALREMAP   ((uint32_t)0x00000010)
#define	AFIO_MAPR_USART3_REMAP_FULLREMAP   ((uint32_t)0x00000030)
#define	AFIO_MAPR_TIM1_REMAP   ((uint32_t)0x000000C0)
#define	AFIO_MAPR_TIM1_REMAP_0   ((uint32_t)0x00000040)
#define	AFIO_MAPR_TIM1_REMAP_1   ((uint32_t)0x00000080)
#define	AFIO_MAPR_TIM1_REMAP_NOREMAP   ((uint32_t)0x00000000)
#define	AFIO_MAPR_TIM1_REMAP_PARTIALREMAP   ((uint32_t)0x00000040)
#define	AFIO_MAPR_TIM1_REMAP_FULLREMAP   ((uint32_t)0x000000C0)
#define	AFIO_MAPR_TIM2_REMAP   ((uint32_t)0x00000300)
#define	AFIO_MAPR_TIM2_REMAP_0   ((uint32_t)0x00000100)
#define	AFIO_MAPR_TIM2_REMAP_1   ((uint32_t)0x00000200)
#define	AFIO_MAPR_TIM2_REMAP_NOREMAP   ((uint32_t)0x00000000)
#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)
#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)
#define	AFIO_MAPR_TIM2_REMAP_FULLREMAP   ((uint32_t)0x00000300)
#define	AFIO_MAPR_TIM3_REMAP   ((uint32_t)0x00000C00)
#define	AFIO_MAPR_TIM3_REMAP_0   ((uint32_t)0x00000400)
#define	AFIO_MAPR_TIM3_REMAP_1   ((uint32_t)0x00000800)
#define	AFIO_MAPR_TIM3_REMAP_NOREMAP   ((uint32_t)0x00000000)
#define	AFIO_MAPR_TIM3_REMAP_PARTIALREMAP   ((uint32_t)0x00000800)
#define	AFIO_MAPR_TIM3_REMAP_FULLREMAP   ((uint32_t)0x00000C00)
#define	AFIO_MAPR_TIM4_REMAP   ((uint32_t)0x00001000)
#define	AFIO_MAPR_CAN_REMAP   ((uint32_t)0x00006000)
#define	AFIO_MAPR_CAN_REMAP_0   ((uint32_t)0x00002000)
#define	AFIO_MAPR_CAN_REMAP_1   ((uint32_t)0x00004000)
#define	AFIO_MAPR_CAN_REMAP_REMAP1   ((uint32_t)0x00000000)
#define	AFIO_MAPR_CAN_REMAP_REMAP2   ((uint32_t)0x00004000)
#define	AFIO_MAPR_CAN_REMAP_REMAP3   ((uint32_t)0x00006000)
#define	AFIO_MAPR_PD01_REMAP   ((uint32_t)0x00008000)
#define	AFIO_MAPR_TIM5CH4_IREMAP   ((uint32_t)0x00010000)
#define	AFIO_MAPR_ADC1_ETRGINJ_REMAP   ((uint32_t)0x00020000)
#define	AFIO_MAPR_ADC1_ETRGREG_REMAP   ((uint32_t)0x00040000)
#define	AFIO_MAPR_ADC2_ETRGINJ_REMAP   ((uint32_t)0x00080000)
#define	AFIO_MAPR_ADC2_ETRGREG_REMAP   ((uint32_t)0x00100000)
#define	AFIO_MAPR_SWJ_CFG   ((uint32_t)0x07000000)
#define	AFIO_MAPR_SWJ_CFG_0   ((uint32_t)0x01000000)
#define	AFIO_MAPR_SWJ_CFG_1   ((uint32_t)0x02000000)
#define	AFIO_MAPR_SWJ_CFG_2   ((uint32_t)0x04000000)
#define	AFIO_MAPR_SWJ_CFG_RESET   ((uint32_t)0x00000000)
#define	AFIO_MAPR_SWJ_CFG_NOJNTRST   ((uint32_t)0x01000000)
#define	AFIO_MAPR_SWJ_CFG_JTAGDISABLE   ((uint32_t)0x02000000)
#define	AFIO_MAPR_SWJ_CFG_DISABLE   ((uint32_t)0x04000000)
#define	AFIO_EXTICR1_EXTI0   ((uint16_t)0x000F)
#define	AFIO_EXTICR1_EXTI1   ((uint16_t)0x00F0)
#define	AFIO_EXTICR1_EXTI2   ((uint16_t)0x0F00)
#define	AFIO_EXTICR1_EXTI3   ((uint16_t)0xF000)
#define	AFIO_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
#define	AFIO_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
#define	AFIO_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
#define	AFIO_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
#define	AFIO_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
#define	AFIO_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
#define	AFIO_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
#define	AFIO_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
#define	AFIO_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
#define	AFIO_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
#define	AFIO_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
#define	AFIO_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
#define	AFIO_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
#define	AFIO_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
#define	AFIO_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
#define	AFIO_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
#define	AFIO_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
#define	AFIO_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
#define	AFIO_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
#define	AFIO_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
#define	AFIO_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
#define	AFIO_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
#define	AFIO_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
#define	AFIO_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
#define	AFIO_EXTICR2_EXTI4   ((uint16_t)0x000F)
#define	AFIO_EXTICR2_EXTI5   ((uint16_t)0x00F0)
#define	AFIO_EXTICR2_EXTI6   ((uint16_t)0x0F00)
#define	AFIO_EXTICR2_EXTI7   ((uint16_t)0xF000)
#define	AFIO_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
#define	AFIO_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
#define	AFIO_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
#define	AFIO_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
#define	AFIO_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
#define	AFIO_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
#define	AFIO_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
#define	AFIO_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
#define	AFIO_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
#define	AFIO_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
#define	AFIO_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
#define	AFIO_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
#define	AFIO_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
#define	AFIO_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
#define	AFIO_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
#define	AFIO_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
#define	AFIO_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
#define	AFIO_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
#define	AFIO_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
#define	AFIO_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
#define	AFIO_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
#define	AFIO_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
#define	AFIO_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
#define	AFIO_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
#define	AFIO_EXTICR3_EXTI8   ((uint16_t)0x000F)
#define	AFIO_EXTICR3_EXTI9   ((uint16_t)0x00F0)
#define	AFIO_EXTICR3_EXTI10   ((uint16_t)0x0F00)
#define	AFIO_EXTICR3_EXTI11   ((uint16_t)0xF000)
#define	AFIO_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
#define	AFIO_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
#define	AFIO_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
#define	AFIO_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
#define	AFIO_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
#define	AFIO_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
#define	AFIO_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
#define	AFIO_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
#define	AFIO_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
#define	AFIO_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
#define	AFIO_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
#define	AFIO_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
#define	AFIO_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
#define	AFIO_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
#define	AFIO_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
#define	AFIO_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
#define	AFIO_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
#define	AFIO_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
#define	AFIO_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
#define	AFIO_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
#define	AFIO_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
#define	AFIO_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
#define	AFIO_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
#define	AFIO_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
#define	AFIO_EXTICR4_EXTI12   ((uint16_t)0x000F)
#define	AFIO_EXTICR4_EXTI13   ((uint16_t)0x00F0)
#define	AFIO_EXTICR4_EXTI14   ((uint16_t)0x0F00)
#define	AFIO_EXTICR4_EXTI15   ((uint16_t)0xF000)
#define	AFIO_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
#define	AFIO_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
#define	AFIO_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
#define	AFIO_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
#define	AFIO_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
#define	AFIO_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
#define	AFIO_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
#define	AFIO_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
#define	AFIO_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
#define	AFIO_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
#define	AFIO_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
#define	AFIO_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
#define	AFIO_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
#define	AFIO_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
#define	AFIO_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
#define	AFIO_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
#define	AFIO_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
#define	AFIO_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
#define	AFIO_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
#define	AFIO_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
#define	AFIO_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
#define	AFIO_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
#define	AFIO_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
#define	AFIO_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
#define	AFIO_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
#define	SysTick_CTRL_ENABLE   ((uint32_t)0x00000001)
#define	SysTick_CTRL_TICKINT   ((uint32_t)0x00000002)
#define	SysTick_CTRL_CLKSOURCE   ((uint32_t)0x00000004)
#define	SysTick_CTRL_COUNTFLAG   ((uint32_t)0x00010000)
#define	SysTick_LOAD_RELOAD   ((uint32_t)0x00FFFFFF)
#define	SysTick_VAL_CURRENT   ((uint32_t)0x00FFFFFF)
#define	SysTick_CALIB_TENMS   ((uint32_t)0x00FFFFFF)
#define	SysTick_CALIB_SKEW   ((uint32_t)0x40000000)
#define	SysTick_CALIB_NOREF   ((uint32_t)0x80000000)
#define	NVIC_ISER_SETENA   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ISER_SETENA_0   ((uint32_t)0x00000001)
#define	NVIC_ISER_SETENA_1   ((uint32_t)0x00000002)
#define	NVIC_ISER_SETENA_2   ((uint32_t)0x00000004)
#define	NVIC_ISER_SETENA_3   ((uint32_t)0x00000008)
#define	NVIC_ISER_SETENA_4   ((uint32_t)0x00000010)
#define	NVIC_ISER_SETENA_5   ((uint32_t)0x00000020)
#define	NVIC_ISER_SETENA_6   ((uint32_t)0x00000040)
#define	NVIC_ISER_SETENA_7   ((uint32_t)0x00000080)
#define	NVIC_ISER_SETENA_8   ((uint32_t)0x00000100)
#define	NVIC_ISER_SETENA_9   ((uint32_t)0x00000200)
#define	NVIC_ISER_SETENA_10   ((uint32_t)0x00000400)
#define	NVIC_ISER_SETENA_11   ((uint32_t)0x00000800)
#define	NVIC_ISER_SETENA_12   ((uint32_t)0x00001000)
#define	NVIC_ISER_SETENA_13   ((uint32_t)0x00002000)
#define	NVIC_ISER_SETENA_14   ((uint32_t)0x00004000)
#define	NVIC_ISER_SETENA_15   ((uint32_t)0x00008000)
#define	NVIC_ISER_SETENA_16   ((uint32_t)0x00010000)
#define	NVIC_ISER_SETENA_17   ((uint32_t)0x00020000)
#define	NVIC_ISER_SETENA_18   ((uint32_t)0x00040000)
#define	NVIC_ISER_SETENA_19   ((uint32_t)0x00080000)
#define	NVIC_ISER_SETENA_20   ((uint32_t)0x00100000)
#define	NVIC_ISER_SETENA_21   ((uint32_t)0x00200000)
#define	NVIC_ISER_SETENA_22   ((uint32_t)0x00400000)
#define	NVIC_ISER_SETENA_23   ((uint32_t)0x00800000)
#define	NVIC_ISER_SETENA_24   ((uint32_t)0x01000000)
#define	NVIC_ISER_SETENA_25   ((uint32_t)0x02000000)
#define	NVIC_ISER_SETENA_26   ((uint32_t)0x04000000)
#define	NVIC_ISER_SETENA_27   ((uint32_t)0x08000000)
#define	NVIC_ISER_SETENA_28   ((uint32_t)0x10000000)
#define	NVIC_ISER_SETENA_29   ((uint32_t)0x20000000)
#define	NVIC_ISER_SETENA_30   ((uint32_t)0x40000000)
#define	NVIC_ISER_SETENA_31   ((uint32_t)0x80000000)
#define	NVIC_ICER_CLRENA   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ICER_CLRENA_0   ((uint32_t)0x00000001)
#define	NVIC_ICER_CLRENA_1   ((uint32_t)0x00000002)
#define	NVIC_ICER_CLRENA_2   ((uint32_t)0x00000004)
#define	NVIC_ICER_CLRENA_3   ((uint32_t)0x00000008)
#define	NVIC_ICER_CLRENA_4   ((uint32_t)0x00000010)
#define	NVIC_ICER_CLRENA_5   ((uint32_t)0x00000020)
#define	NVIC_ICER_CLRENA_6   ((uint32_t)0x00000040)
#define	NVIC_ICER_CLRENA_7   ((uint32_t)0x00000080)
#define	NVIC_ICER_CLRENA_8   ((uint32_t)0x00000100)
#define	NVIC_ICER_CLRENA_9   ((uint32_t)0x00000200)
#define	NVIC_ICER_CLRENA_10   ((uint32_t)0x00000400)
#define	NVIC_ICER_CLRENA_11   ((uint32_t)0x00000800)
#define	NVIC_ICER_CLRENA_12   ((uint32_t)0x00001000)
#define	NVIC_ICER_CLRENA_13   ((uint32_t)0x00002000)
#define	NVIC_ICER_CLRENA_14   ((uint32_t)0x00004000)
#define	NVIC_ICER_CLRENA_15   ((uint32_t)0x00008000)
#define	NVIC_ICER_CLRENA_16   ((uint32_t)0x00010000)
#define	NVIC_ICER_CLRENA_17   ((uint32_t)0x00020000)
#define	NVIC_ICER_CLRENA_18   ((uint32_t)0x00040000)
#define	NVIC_ICER_CLRENA_19   ((uint32_t)0x00080000)
#define	NVIC_ICER_CLRENA_20   ((uint32_t)0x00100000)
#define	NVIC_ICER_CLRENA_21   ((uint32_t)0x00200000)
#define	NVIC_ICER_CLRENA_22   ((uint32_t)0x00400000)
#define	NVIC_ICER_CLRENA_23   ((uint32_t)0x00800000)
#define	NVIC_ICER_CLRENA_24   ((uint32_t)0x01000000)
#define	NVIC_ICER_CLRENA_25   ((uint32_t)0x02000000)
#define	NVIC_ICER_CLRENA_26   ((uint32_t)0x04000000)
#define	NVIC_ICER_CLRENA_27   ((uint32_t)0x08000000)
#define	NVIC_ICER_CLRENA_28   ((uint32_t)0x10000000)
#define	NVIC_ICER_CLRENA_29   ((uint32_t)0x20000000)
#define	NVIC_ICER_CLRENA_30   ((uint32_t)0x40000000)
#define	NVIC_ICER_CLRENA_31   ((uint32_t)0x80000000)
#define	NVIC_ISPR_SETPEND   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ISPR_SETPEND_0   ((uint32_t)0x00000001)
#define	NVIC_ISPR_SETPEND_1   ((uint32_t)0x00000002)
#define	NVIC_ISPR_SETPEND_2   ((uint32_t)0x00000004)
#define	NVIC_ISPR_SETPEND_3   ((uint32_t)0x00000008)
#define	NVIC_ISPR_SETPEND_4   ((uint32_t)0x00000010)
#define	NVIC_ISPR_SETPEND_5   ((uint32_t)0x00000020)
#define	NVIC_ISPR_SETPEND_6   ((uint32_t)0x00000040)
#define	NVIC_ISPR_SETPEND_7   ((uint32_t)0x00000080)
#define	NVIC_ISPR_SETPEND_8   ((uint32_t)0x00000100)
#define	NVIC_ISPR_SETPEND_9   ((uint32_t)0x00000200)
#define	NVIC_ISPR_SETPEND_10   ((uint32_t)0x00000400)
#define	NVIC_ISPR_SETPEND_11   ((uint32_t)0x00000800)
#define	NVIC_ISPR_SETPEND_12   ((uint32_t)0x00001000)
#define	NVIC_ISPR_SETPEND_13   ((uint32_t)0x00002000)
#define	NVIC_ISPR_SETPEND_14   ((uint32_t)0x00004000)
#define	NVIC_ISPR_SETPEND_15   ((uint32_t)0x00008000)
#define	NVIC_ISPR_SETPEND_16   ((uint32_t)0x00010000)
#define	NVIC_ISPR_SETPEND_17   ((uint32_t)0x00020000)
#define	NVIC_ISPR_SETPEND_18   ((uint32_t)0x00040000)
#define	NVIC_ISPR_SETPEND_19   ((uint32_t)0x00080000)
#define	NVIC_ISPR_SETPEND_20   ((uint32_t)0x00100000)
#define	NVIC_ISPR_SETPEND_21   ((uint32_t)0x00200000)
#define	NVIC_ISPR_SETPEND_22   ((uint32_t)0x00400000)
#define	NVIC_ISPR_SETPEND_23   ((uint32_t)0x00800000)
#define	NVIC_ISPR_SETPEND_24   ((uint32_t)0x01000000)
#define	NVIC_ISPR_SETPEND_25   ((uint32_t)0x02000000)
#define	NVIC_ISPR_SETPEND_26   ((uint32_t)0x04000000)
#define	NVIC_ISPR_SETPEND_27   ((uint32_t)0x08000000)
#define	NVIC_ISPR_SETPEND_28   ((uint32_t)0x10000000)
#define	NVIC_ISPR_SETPEND_29   ((uint32_t)0x20000000)
#define	NVIC_ISPR_SETPEND_30   ((uint32_t)0x40000000)
#define	NVIC_ISPR_SETPEND_31   ((uint32_t)0x80000000)
#define	NVIC_ICPR_CLRPEND   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ICPR_CLRPEND_0   ((uint32_t)0x00000001)
#define	NVIC_ICPR_CLRPEND_1   ((uint32_t)0x00000002)
#define	NVIC_ICPR_CLRPEND_2   ((uint32_t)0x00000004)
#define	NVIC_ICPR_CLRPEND_3   ((uint32_t)0x00000008)
#define	NVIC_ICPR_CLRPEND_4   ((uint32_t)0x00000010)
#define	NVIC_ICPR_CLRPEND_5   ((uint32_t)0x00000020)
#define	NVIC_ICPR_CLRPEND_6   ((uint32_t)0x00000040)
#define	NVIC_ICPR_CLRPEND_7   ((uint32_t)0x00000080)
#define	NVIC_ICPR_CLRPEND_8   ((uint32_t)0x00000100)
#define	NVIC_ICPR_CLRPEND_9   ((uint32_t)0x00000200)
#define	NVIC_ICPR_CLRPEND_10   ((uint32_t)0x00000400)
#define	NVIC_ICPR_CLRPEND_11   ((uint32_t)0x00000800)
#define	NVIC_ICPR_CLRPEND_12   ((uint32_t)0x00001000)
#define	NVIC_ICPR_CLRPEND_13   ((uint32_t)0x00002000)
#define	NVIC_ICPR_CLRPEND_14   ((uint32_t)0x00004000)
#define	NVIC_ICPR_CLRPEND_15   ((uint32_t)0x00008000)
#define	NVIC_ICPR_CLRPEND_16   ((uint32_t)0x00010000)
#define	NVIC_ICPR_CLRPEND_17   ((uint32_t)0x00020000)
#define	NVIC_ICPR_CLRPEND_18   ((uint32_t)0x00040000)
#define	NVIC_ICPR_CLRPEND_19   ((uint32_t)0x00080000)
#define	NVIC_ICPR_CLRPEND_20   ((uint32_t)0x00100000)
#define	NVIC_ICPR_CLRPEND_21   ((uint32_t)0x00200000)
#define	NVIC_ICPR_CLRPEND_22   ((uint32_t)0x00400000)
#define	NVIC_ICPR_CLRPEND_23   ((uint32_t)0x00800000)
#define	NVIC_ICPR_CLRPEND_24   ((uint32_t)0x01000000)
#define	NVIC_ICPR_CLRPEND_25   ((uint32_t)0x02000000)
#define	NVIC_ICPR_CLRPEND_26   ((uint32_t)0x04000000)
#define	NVIC_ICPR_CLRPEND_27   ((uint32_t)0x08000000)
#define	NVIC_ICPR_CLRPEND_28   ((uint32_t)0x10000000)
#define	NVIC_ICPR_CLRPEND_29   ((uint32_t)0x20000000)
#define	NVIC_ICPR_CLRPEND_30   ((uint32_t)0x40000000)
#define	NVIC_ICPR_CLRPEND_31   ((uint32_t)0x80000000)
#define	NVIC_IABR_ACTIVE   ((uint32_t)0xFFFFFFFF)
#define	NVIC_IABR_ACTIVE_0   ((uint32_t)0x00000001)
#define	NVIC_IABR_ACTIVE_1   ((uint32_t)0x00000002)
#define	NVIC_IABR_ACTIVE_2   ((uint32_t)0x00000004)
#define	NVIC_IABR_ACTIVE_3   ((uint32_t)0x00000008)
#define	NVIC_IABR_ACTIVE_4   ((uint32_t)0x00000010)
#define	NVIC_IABR_ACTIVE_5   ((uint32_t)0x00000020)
#define	NVIC_IABR_ACTIVE_6   ((uint32_t)0x00000040)
#define	NVIC_IABR_ACTIVE_7   ((uint32_t)0x00000080)
#define	NVIC_IABR_ACTIVE_8   ((uint32_t)0x00000100)
#define	NVIC_IABR_ACTIVE_9   ((uint32_t)0x00000200)
#define	NVIC_IABR_ACTIVE_10   ((uint32_t)0x00000400)
#define	NVIC_IABR_ACTIVE_11   ((uint32_t)0x00000800)
#define	NVIC_IABR_ACTIVE_12   ((uint32_t)0x00001000)
#define	NVIC_IABR_ACTIVE_13   ((uint32_t)0x00002000)
#define	NVIC_IABR_ACTIVE_14   ((uint32_t)0x00004000)
#define	NVIC_IABR_ACTIVE_15   ((uint32_t)0x00008000)
#define	NVIC_IABR_ACTIVE_16   ((uint32_t)0x00010000)
#define	NVIC_IABR_ACTIVE_17   ((uint32_t)0x00020000)
#define	NVIC_IABR_ACTIVE_18   ((uint32_t)0x00040000)
#define	NVIC_IABR_ACTIVE_19   ((uint32_t)0x00080000)
#define	NVIC_IABR_ACTIVE_20   ((uint32_t)0x00100000)
#define	NVIC_IABR_ACTIVE_21   ((uint32_t)0x00200000)
#define	NVIC_IABR_ACTIVE_22   ((uint32_t)0x00400000)
#define	NVIC_IABR_ACTIVE_23   ((uint32_t)0x00800000)
#define	NVIC_IABR_ACTIVE_24   ((uint32_t)0x01000000)
#define	NVIC_IABR_ACTIVE_25   ((uint32_t)0x02000000)
#define	NVIC_IABR_ACTIVE_26   ((uint32_t)0x04000000)
#define	NVIC_IABR_ACTIVE_27   ((uint32_t)0x08000000)
#define	NVIC_IABR_ACTIVE_28   ((uint32_t)0x10000000)
#define	NVIC_IABR_ACTIVE_29   ((uint32_t)0x20000000)
#define	NVIC_IABR_ACTIVE_30   ((uint32_t)0x40000000)
#define	NVIC_IABR_ACTIVE_31   ((uint32_t)0x80000000)
#define	NVIC_IPR0_PRI_0   ((uint32_t)0x000000FF)
#define	NVIC_IPR0_PRI_1   ((uint32_t)0x0000FF00)
#define	NVIC_IPR0_PRI_2   ((uint32_t)0x00FF0000)
#define	NVIC_IPR0_PRI_3   ((uint32_t)0xFF000000)
#define	NVIC_IPR1_PRI_4   ((uint32_t)0x000000FF)
#define	NVIC_IPR1_PRI_5   ((uint32_t)0x0000FF00)
#define	NVIC_IPR1_PRI_6   ((uint32_t)0x00FF0000)
#define	NVIC_IPR1_PRI_7   ((uint32_t)0xFF000000)
#define	NVIC_IPR2_PRI_8   ((uint32_t)0x000000FF)
#define	NVIC_IPR2_PRI_9   ((uint32_t)0x0000FF00)
#define	NVIC_IPR2_PRI_10   ((uint32_t)0x00FF0000)
#define	NVIC_IPR2_PRI_11   ((uint32_t)0xFF000000)
#define	NVIC_IPR3_PRI_12   ((uint32_t)0x000000FF)
#define	NVIC_IPR3_PRI_13   ((uint32_t)0x0000FF00)
#define	NVIC_IPR3_PRI_14   ((uint32_t)0x00FF0000)
#define	NVIC_IPR3_PRI_15   ((uint32_t)0xFF000000)
#define	NVIC_IPR4_PRI_16   ((uint32_t)0x000000FF)
#define	NVIC_IPR4_PRI_17   ((uint32_t)0x0000FF00)
#define	NVIC_IPR4_PRI_18   ((uint32_t)0x00FF0000)
#define	NVIC_IPR4_PRI_19   ((uint32_t)0xFF000000)
#define	NVIC_IPR5_PRI_20   ((uint32_t)0x000000FF)
#define	NVIC_IPR5_PRI_21   ((uint32_t)0x0000FF00)
#define	NVIC_IPR5_PRI_22   ((uint32_t)0x00FF0000)
#define	NVIC_IPR5_PRI_23   ((uint32_t)0xFF000000)
#define	NVIC_IPR6_PRI_24   ((uint32_t)0x000000FF)
#define	NVIC_IPR6_PRI_25   ((uint32_t)0x0000FF00)
#define	NVIC_IPR6_PRI_26   ((uint32_t)0x00FF0000)
#define	NVIC_IPR6_PRI_27   ((uint32_t)0xFF000000)
#define	NVIC_IPR7_PRI_28   ((uint32_t)0x000000FF)
#define	NVIC_IPR7_PRI_29   ((uint32_t)0x0000FF00)
#define	NVIC_IPR7_PRI_30   ((uint32_t)0x00FF0000)
#define	NVIC_IPR7_PRI_31   ((uint32_t)0xFF000000)
#define	SCB_CPUID_REVISION   ((uint32_t)0x0000000F)
#define	SCB_CPUID_PARTNO   ((uint32_t)0x0000FFF0)
#define	SCB_CPUID_Constant   ((uint32_t)0x000F0000)
#define	SCB_CPUID_VARIANT   ((uint32_t)0x00F00000)
#define	SCB_CPUID_IMPLEMENTER   ((uint32_t)0xFF000000)
#define	SCB_ICSR_VECTACTIVE   ((uint32_t)0x000001FF)
#define	SCB_ICSR_RETTOBASE   ((uint32_t)0x00000800)
#define	SCB_ICSR_VECTPENDING   ((uint32_t)0x003FF000)
#define	SCB_ICSR_ISRPENDING   ((uint32_t)0x00400000)
#define	SCB_ICSR_ISRPREEMPT   ((uint32_t)0x00800000)
#define	SCB_ICSR_PENDSTCLR   ((uint32_t)0x02000000)
#define	SCB_ICSR_PENDSTSET   ((uint32_t)0x04000000)
#define	SCB_ICSR_PENDSVCLR   ((uint32_t)0x08000000)
#define	SCB_ICSR_PENDSVSET   ((uint32_t)0x10000000)
#define	SCB_ICSR_NMIPENDSET   ((uint32_t)0x80000000)
#define	SCB_VTOR_TBLOFF   ((uint32_t)0x1FFFFF80)
#define	SCB_VTOR_TBLBASE   ((uint32_t)0x20000000)
#define	SCB_AIRCR_VECTRESET   ((uint32_t)0x00000001)
#define	SCB_AIRCR_VECTCLRACTIVE   ((uint32_t)0x00000002)
#define	SCB_AIRCR_SYSRESETREQ   ((uint32_t)0x00000004)
#define	SCB_AIRCR_PRIGROUP   ((uint32_t)0x00000700)
#define	SCB_AIRCR_PRIGROUP_0   ((uint32_t)0x00000100)
#define	SCB_AIRCR_PRIGROUP_1   ((uint32_t)0x00000200)
#define	SCB_AIRCR_PRIGROUP_2   ((uint32_t)0x00000400)
#define	SCB_AIRCR_PRIGROUP0   ((uint32_t)0x00000000)
#define	SCB_AIRCR_PRIGROUP1   ((uint32_t)0x00000100)
#define	SCB_AIRCR_PRIGROUP2   ((uint32_t)0x00000200)
#define	SCB_AIRCR_PRIGROUP3   ((uint32_t)0x00000300)
#define	SCB_AIRCR_PRIGROUP4   ((uint32_t)0x00000400)
#define	SCB_AIRCR_PRIGROUP5   ((uint32_t)0x00000500)
#define	SCB_AIRCR_PRIGROUP6   ((uint32_t)0x00000600)
#define	SCB_AIRCR_PRIGROUP7   ((uint32_t)0x00000700)
#define	SCB_AIRCR_ENDIANESS   ((uint32_t)0x00008000)
#define	SCB_AIRCR_VECTKEY   ((uint32_t)0xFFFF0000)
#define	SCB_SCR_SLEEPONEXIT   ((uint8_t)0x02)
#define	SCB_SCR_SLEEPDEEP   ((uint8_t)0x04)
#define	SCB_SCR_SEVONPEND   ((uint8_t)0x10)
#define	SCB_CCR_NONBASETHRDENA   ((uint16_t)0x0001)
#define	SCB_CCR_USERSETMPEND   ((uint16_t)0x0002)
#define	SCB_CCR_UNALIGN_TRP   ((uint16_t)0x0008)
#define	SCB_CCR_DIV_0_TRP   ((uint16_t)0x0010)
#define	SCB_CCR_BFHFNMIGN   ((uint16_t)0x0100)
#define	SCB_CCR_STKALIGN   ((uint16_t)0x0200)
#define	SCB_SHPR_PRI_N   ((uint32_t)0x000000FF)
#define	SCB_SHPR_PRI_N1   ((uint32_t)0x0000FF00)
#define	SCB_SHPR_PRI_N2   ((uint32_t)0x00FF0000)
#define	SCB_SHPR_PRI_N3   ((uint32_t)0xFF000000)
#define	SCB_SHCSR_MEMFAULTACT   ((uint32_t)0x00000001)
#define	SCB_SHCSR_BUSFAULTACT   ((uint32_t)0x00000002)
#define	SCB_SHCSR_USGFAULTACT   ((uint32_t)0x00000008)
#define	SCB_SHCSR_SVCALLACT   ((uint32_t)0x00000080)
#define	SCB_SHCSR_MONITORACT   ((uint32_t)0x00000100)
#define	SCB_SHCSR_PENDSVACT   ((uint32_t)0x00000400)
#define	SCB_SHCSR_SYSTICKACT   ((uint32_t)0x00000800)
#define	SCB_SHCSR_USGFAULTPENDED   ((uint32_t)0x00001000)
#define	SCB_SHCSR_MEMFAULTPENDED   ((uint32_t)0x00002000)
#define	SCB_SHCSR_BUSFAULTPENDED   ((uint32_t)0x00004000)
#define	SCB_SHCSR_SVCALLPENDED   ((uint32_t)0x00008000)
#define	SCB_SHCSR_MEMFAULTENA   ((uint32_t)0x00010000)
#define	SCB_SHCSR_BUSFAULTENA   ((uint32_t)0x00020000)
#define	SCB_SHCSR_USGFAULTENA   ((uint32_t)0x00040000)
#define	SCB_CFSR_IACCVIOL   ((uint32_t)0x00000001)
#define	SCB_CFSR_DACCVIOL   ((uint32_t)0x00000002)
#define	SCB_CFSR_MUNSTKERR   ((uint32_t)0x00000008)
#define	SCB_CFSR_MSTKERR   ((uint32_t)0x00000010)
#define	SCB_CFSR_MMARVALID   ((uint32_t)0x00000080)
#define	SCB_CFSR_IBUSERR   ((uint32_t)0x00000100)
#define	SCB_CFSR_PRECISERR   ((uint32_t)0x00000200)
#define	SCB_CFSR_IMPRECISERR   ((uint32_t)0x00000400)
#define	SCB_CFSR_UNSTKERR   ((uint32_t)0x00000800)
#define	SCB_CFSR_STKERR   ((uint32_t)0x00001000)
#define	SCB_CFSR_BFARVALID   ((uint32_t)0x00008000)
#define	SCB_CFSR_UNDEFINSTR   ((uint32_t)0x00010000)
#define	SCB_CFSR_INVSTATE   ((uint32_t)0x00020000)
#define	SCB_CFSR_INVPC   ((uint32_t)0x00040000)
#define	SCB_CFSR_NOCP   ((uint32_t)0x00080000)
#define	SCB_CFSR_UNALIGNED   ((uint32_t)0x01000000)
#define	SCB_CFSR_DIVBYZERO   ((uint32_t)0x02000000)
#define	SCB_HFSR_VECTTBL   ((uint32_t)0x00000002)
#define	SCB_HFSR_FORCED   ((uint32_t)0x40000000)
#define	SCB_HFSR_DEBUGEVT   ((uint32_t)0x80000000)
#define	SCB_DFSR_HALTED   ((uint8_t)0x01)
#define	SCB_DFSR_BKPT   ((uint8_t)0x02)
#define	SCB_DFSR_DWTTRAP   ((uint8_t)0x04)
#define	SCB_DFSR_VCATCH   ((uint8_t)0x08)
#define	SCB_DFSR_EXTERNAL   ((uint8_t)0x10)
#define	SCB_MMFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)
#define	SCB_BFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)
#define	SCB_AFSR_IMPDEF   ((uint32_t)0xFFFFFFFF)
#define	EXTI_IMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_IMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_IMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_IMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_IMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_IMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_IMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_IMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_IMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_IMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_IMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_IMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_IMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_IMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_IMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_IMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_IMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_IMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_IMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_EMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_EMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_EMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_EMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_EMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_EMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_EMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_EMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_EMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_EMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_EMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_EMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_EMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_EMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_EMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_EMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_EMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_EMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_EMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_EMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_RTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_RTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_RTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_RTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_RTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_RTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_RTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_RTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_RTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_RTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_RTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_RTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_RTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_RTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_RTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_RTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_RTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_RTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_RTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_RTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_FTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_FTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_FTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_FTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_FTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_FTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_FTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_FTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_FTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_FTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_FTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_FTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_FTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_FTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_FTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_FTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_FTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_FTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_FTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_FTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
#define	EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
#define	EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
#define	EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
#define	EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
#define	EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
#define	EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
#define	EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
#define	EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
#define	EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
#define	EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
#define	EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
#define	EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
#define	EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
#define	EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
#define	EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
#define	EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
#define	EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
#define	EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
#define	EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
#define	EXTI_PR_PR0   ((uint32_t)0x00000001)
#define	EXTI_PR_PR1   ((uint32_t)0x00000002)
#define	EXTI_PR_PR2   ((uint32_t)0x00000004)
#define	EXTI_PR_PR3   ((uint32_t)0x00000008)
#define	EXTI_PR_PR4   ((uint32_t)0x00000010)
#define	EXTI_PR_PR5   ((uint32_t)0x00000020)
#define	EXTI_PR_PR6   ((uint32_t)0x00000040)
#define	EXTI_PR_PR7   ((uint32_t)0x00000080)
#define	EXTI_PR_PR8   ((uint32_t)0x00000100)
#define	EXTI_PR_PR9   ((uint32_t)0x00000200)
#define	EXTI_PR_PR10   ((uint32_t)0x00000400)
#define	EXTI_PR_PR11   ((uint32_t)0x00000800)
#define	EXTI_PR_PR12   ((uint32_t)0x00001000)
#define	EXTI_PR_PR13   ((uint32_t)0x00002000)
#define	EXTI_PR_PR14   ((uint32_t)0x00004000)
#define	EXTI_PR_PR15   ((uint32_t)0x00008000)
#define	EXTI_PR_PR16   ((uint32_t)0x00010000)
#define	EXTI_PR_PR17   ((uint32_t)0x00020000)
#define	EXTI_PR_PR18   ((uint32_t)0x00040000)
#define	EXTI_PR_PR19   ((uint32_t)0x00080000)
#define	DMA_ISR_GIF1   ((uint32_t)0x00000001)
#define	DMA_ISR_TCIF1   ((uint32_t)0x00000002)
#define	DMA_ISR_HTIF1   ((uint32_t)0x00000004)
#define	DMA_ISR_TEIF1   ((uint32_t)0x00000008)
#define	DMA_ISR_GIF2   ((uint32_t)0x00000010)
#define	DMA_ISR_TCIF2   ((uint32_t)0x00000020)
#define	DMA_ISR_HTIF2   ((uint32_t)0x00000040)
#define	DMA_ISR_TEIF2   ((uint32_t)0x00000080)
#define	DMA_ISR_GIF3   ((uint32_t)0x00000100)
#define	DMA_ISR_TCIF3   ((uint32_t)0x00000200)
#define	DMA_ISR_HTIF3   ((uint32_t)0x00000400)
#define	DMA_ISR_TEIF3   ((uint32_t)0x00000800)
#define	DMA_ISR_GIF4   ((uint32_t)0x00001000)
#define	DMA_ISR_TCIF4   ((uint32_t)0x00002000)
#define	DMA_ISR_HTIF4   ((uint32_t)0x00004000)
#define	DMA_ISR_TEIF4   ((uint32_t)0x00008000)
#define	DMA_ISR_GIF5   ((uint32_t)0x00010000)
#define	DMA_ISR_TCIF5   ((uint32_t)0x00020000)
#define	DMA_ISR_HTIF5   ((uint32_t)0x00040000)
#define	DMA_ISR_TEIF5   ((uint32_t)0x00080000)
#define	DMA_ISR_GIF6   ((uint32_t)0x00100000)
#define	DMA_ISR_TCIF6   ((uint32_t)0x00200000)
#define	DMA_ISR_HTIF6   ((uint32_t)0x00400000)
#define	DMA_ISR_TEIF6   ((uint32_t)0x00800000)
#define	DMA_ISR_GIF7   ((uint32_t)0x01000000)
#define	DMA_ISR_TCIF7   ((uint32_t)0x02000000)
#define	DMA_ISR_HTIF7   ((uint32_t)0x04000000)
#define	DMA_ISR_TEIF7   ((uint32_t)0x08000000)
#define	DMA_IFCR_CGIF1   ((uint32_t)0x00000001)
#define	DMA_IFCR_CTCIF1   ((uint32_t)0x00000002)
#define	DMA_IFCR_CHTIF1   ((uint32_t)0x00000004)
#define	DMA_IFCR_CTEIF1   ((uint32_t)0x00000008)
#define	DMA_IFCR_CGIF2   ((uint32_t)0x00000010)
#define	DMA_IFCR_CTCIF2   ((uint32_t)0x00000020)
#define	DMA_IFCR_CHTIF2   ((uint32_t)0x00000040)
#define	DMA_IFCR_CTEIF2   ((uint32_t)0x00000080)
#define	DMA_IFCR_CGIF3   ((uint32_t)0x00000100)
#define	DMA_IFCR_CTCIF3   ((uint32_t)0x00000200)
#define	DMA_IFCR_CHTIF3   ((uint32_t)0x00000400)
#define	DMA_IFCR_CTEIF3   ((uint32_t)0x00000800)
#define	DMA_IFCR_CGIF4   ((uint32_t)0x00001000)
#define	DMA_IFCR_CTCIF4   ((uint32_t)0x00002000)
#define	DMA_IFCR_CHTIF4   ((uint32_t)0x00004000)
#define	DMA_IFCR_CTEIF4   ((uint32_t)0x00008000)
#define	DMA_IFCR_CGIF5   ((uint32_t)0x00010000)
#define	DMA_IFCR_CTCIF5   ((uint32_t)0x00020000)
#define	DMA_IFCR_CHTIF5   ((uint32_t)0x00040000)
#define	DMA_IFCR_CTEIF5   ((uint32_t)0x00080000)
#define	DMA_IFCR_CGIF6   ((uint32_t)0x00100000)
#define	DMA_IFCR_CTCIF6   ((uint32_t)0x00200000)
#define	DMA_IFCR_CHTIF6   ((uint32_t)0x00400000)
#define	DMA_IFCR_CTEIF6   ((uint32_t)0x00800000)
#define	DMA_IFCR_CGIF7   ((uint32_t)0x01000000)
#define	DMA_IFCR_CTCIF7   ((uint32_t)0x02000000)
#define	DMA_IFCR_CHTIF7   ((uint32_t)0x04000000)
#define	DMA_IFCR_CTEIF7   ((uint32_t)0x08000000)
#define	DMA_CCR1_EN   ((uint16_t)0x0001)
#define	DMA_CCR1_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR1_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR1_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR1_DIR   ((uint16_t)0x0010)
#define	DMA_CCR1_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR1_PINC   ((uint16_t)0x0040)
#define	DMA_CCR1_MINC   ((uint16_t)0x0080)
#define	DMA_CCR1_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR1_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR1_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR1_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR1_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR1_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR1_PL   ((uint16_t)0x3000)
#define	DMA_CCR1_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR1_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR1_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR2_EN   ((uint16_t)0x0001)
#define	DMA_CCR2_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR2_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR2_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR2_DIR   ((uint16_t)0x0010)
#define	DMA_CCR2_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR2_PINC   ((uint16_t)0x0040)
#define	DMA_CCR2_MINC   ((uint16_t)0x0080)
#define	DMA_CCR2_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR2_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR2_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR2_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR2_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR2_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR2_PL   ((uint16_t)0x3000)
#define	DMA_CCR2_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR2_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR2_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR3_EN   ((uint16_t)0x0001)
#define	DMA_CCR3_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR3_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR3_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR3_DIR   ((uint16_t)0x0010)
#define	DMA_CCR3_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR3_PINC   ((uint16_t)0x0040)
#define	DMA_CCR3_MINC   ((uint16_t)0x0080)
#define	DMA_CCR3_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR3_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR3_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR3_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR3_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR3_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR3_PL   ((uint16_t)0x3000)
#define	DMA_CCR3_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR3_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR3_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR4_EN   ((uint16_t)0x0001)
#define	DMA_CCR4_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR4_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR4_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR4_DIR   ((uint16_t)0x0010)
#define	DMA_CCR4_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR4_PINC   ((uint16_t)0x0040)
#define	DMA_CCR4_MINC   ((uint16_t)0x0080)
#define	DMA_CCR4_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR4_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR4_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR4_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR4_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR4_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR4_PL   ((uint16_t)0x3000)
#define	DMA_CCR4_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR4_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR4_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR5_EN   ((uint16_t)0x0001)
#define	DMA_CCR5_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR5_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR5_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR5_DIR   ((uint16_t)0x0010)
#define	DMA_CCR5_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR5_PINC   ((uint16_t)0x0040)
#define	DMA_CCR5_MINC   ((uint16_t)0x0080)
#define	DMA_CCR5_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR5_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR5_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR5_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR5_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR5_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR5_PL   ((uint16_t)0x3000)
#define	DMA_CCR5_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR5_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR5_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR6_EN   ((uint16_t)0x0001)
#define	DMA_CCR6_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR6_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR6_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR6_DIR   ((uint16_t)0x0010)
#define	DMA_CCR6_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR6_PINC   ((uint16_t)0x0040)
#define	DMA_CCR6_MINC   ((uint16_t)0x0080)
#define	DMA_CCR6_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR6_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR6_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR6_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR6_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR6_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR6_PL   ((uint16_t)0x3000)
#define	DMA_CCR6_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR6_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR6_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR7_EN   ((uint16_t)0x0001)
#define	DMA_CCR7_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR7_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR7_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR7_DIR   ((uint16_t)0x0010)
#define	DMA_CCR7_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR7_PINC   ((uint16_t)0x0040)
#define	DMA_CCR7_MINC   ((uint16_t)0x0080)
#define	DMA_CCR7_PSIZE   , ((uint16_t)0x0300)
#define	DMA_CCR7_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR7_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR7_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR7_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR7_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR7_PL   ((uint16_t)0x3000)
#define	DMA_CCR7_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR7_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR7_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CNDTR1_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR2_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR3_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR4_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR5_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR6_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR7_NDT   ((uint16_t)0xFFFF)
#define	DMA_CPAR1_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR2_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR3_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR4_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR5_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR6_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR7_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR1_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR2_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR3_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR4_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR5_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR6_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR7_MA   ((uint32_t)0xFFFFFFFF)
#define	ADC_SR_AWD   ((uint8_t)0x01)
#define	ADC_SR_EOC   ((uint8_t)0x02)
#define	ADC_SR_JEOC   ((uint8_t)0x04)
#define	ADC_SR_JSTRT   ((uint8_t)0x08)
#define	ADC_SR_STRT   ((uint8_t)0x10)
#define	ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
#define	ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
#define	ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
#define	ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
#define	ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
#define	ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
#define	ADC_CR1_EOCIE   ((uint32_t)0x00000020)
#define	ADC_CR1_AWDIE   ((uint32_t)0x00000040)
#define	ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
#define	ADC_CR1_SCAN   ((uint32_t)0x00000100)
#define	ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
#define	ADC_CR1_JAUTO   ((uint32_t)0x00000400)
#define	ADC_CR1_DISCEN   ((uint32_t)0x00000800)
#define	ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
#define	ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
#define	ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
#define	ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
#define	ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
#define	ADC_CR1_DUALMOD   ((uint32_t)0x000F0000)
#define	ADC_CR1_DUALMOD_0   ((uint32_t)0x00010000)
#define	ADC_CR1_DUALMOD_1   ((uint32_t)0x00020000)
#define	ADC_CR1_DUALMOD_2   ((uint32_t)0x00040000)
#define	ADC_CR1_DUALMOD_3   ((uint32_t)0x00080000)
#define	ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
#define	ADC_CR1_AWDEN   ((uint32_t)0x00800000)
#define	ADC_CR2_ADON   ((uint32_t)0x00000001)
#define	ADC_CR2_CONT   ((uint32_t)0x00000002)
#define	ADC_CR2_CAL   ((uint32_t)0x00000004)
#define	ADC_CR2_RSTCAL   ((uint32_t)0x00000008)
#define	ADC_CR2_DMA   ((uint32_t)0x00000100)
#define	ADC_CR2_ALIGN   ((uint32_t)0x00000800)
#define	ADC_CR2_JEXTSEL   ((uint32_t)0x00007000)
#define	ADC_CR2_JEXTSEL_0   ((uint32_t)0x00001000)
#define	ADC_CR2_JEXTSEL_1   ((uint32_t)0x00002000)
#define	ADC_CR2_JEXTSEL_2   ((uint32_t)0x00004000)
#define	ADC_CR2_JEXTTRIG   ((uint32_t)0x00008000)
#define	ADC_CR2_EXTSEL   ((uint32_t)0x000E0000)
#define	ADC_CR2_EXTSEL_0   ((uint32_t)0x00020000)
#define	ADC_CR2_EXTSEL_1   ((uint32_t)0x00040000)
#define	ADC_CR2_EXTSEL_2   ((uint32_t)0x00080000)
#define	ADC_CR2_EXTTRIG   ((uint32_t)0x00100000)
#define	ADC_CR2_JSWSTART   ((uint32_t)0x00200000)
#define	ADC_CR2_SWSTART   ((uint32_t)0x00400000)
#define	ADC_CR2_TSVREFE   ((uint32_t)0x00800000)
#define	ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
#define	ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
#define	ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
#define	ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
#define	ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
#define	ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
#define	ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
#define	ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
#define	ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
#define	ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
#define	ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
#define	ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
#define	ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
#define	ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
#define	ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
#define	ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
#define	ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
#define	ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
#define	ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
#define	ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
#define	ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
#define	ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
#define	ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
#define	ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
#define	ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
#define	ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
#define	ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
#define	ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
#define	ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
#define	ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
#define	ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
#define	ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
#define	ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
#define	ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
#define	ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
#define	ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
#define	ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
#define	ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
#define	ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
#define	ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
#define	ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
#define	ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
#define	ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
#define	ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
#define	ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
#define	ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
#define	ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
#define	ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
#define	ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
#define	ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
#define	ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
#define	ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
#define	ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
#define	ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
#define	ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
#define	ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
#define	ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
#define	ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
#define	ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
#define	ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
#define	ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
#define	ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
#define	ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
#define	ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
#define	ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
#define	ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
#define	ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
#define	ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
#define	ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
#define	ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
#define	ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
#define	ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
#define	ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
#define	ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
#define	ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
#define	ADC_HTR_HT   ((uint16_t)0x0FFF)
#define	ADC_LTR_LT   ((uint16_t)0x0FFF)
#define	ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
#define	ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
#define	ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
#define	ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
#define	ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
#define	ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
#define	ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
#define	ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
#define	ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
#define	ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
#define	ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
#define	ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
#define	ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
#define	ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
#define	ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
#define	ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
#define	ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
#define	ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
#define	ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
#define	ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
#define	ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
#define	ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
#define	ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
#define	ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
#define	ADC_SQR1_L   ((uint32_t)0x00F00000)
#define	ADC_SQR1_L_0   ((uint32_t)0x00100000)
#define	ADC_SQR1_L_1   ((uint32_t)0x00200000)
#define	ADC_SQR1_L_2   ((uint32_t)0x00400000)
#define	ADC_SQR1_L_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
#define	ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
#define	ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
#define	ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
#define	ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
#define	ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
#define	ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
#define	ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
#define	ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
#define	ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
#define	ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
#define	ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
#define	ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
#define	ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
#define	ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
#define	ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
#define	ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
#define	ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
#define	ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
#define	ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
#define	ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
#define	ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
#define	ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
#define	ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
#define	ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
#define	ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
#define	ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
#define	ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
#define	ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
#define	ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
#define	ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
#define	ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
#define	ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
#define	ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
#define	ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
#define	ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
#define	ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
#define	ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
#define	ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
#define	ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
#define	ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
#define	ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
#define	ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
#define	ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
#define	ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
#define	ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
#define	ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
#define	ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
#define	ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
#define	ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
#define	ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
#define	ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
#define	ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
#define	ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
#define	ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
#define	ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
#define	ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
#define	ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
#define	ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
#define	ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
#define	ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
#define	ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
#define	ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
#define	ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
#define	ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
#define	ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
#define	ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
#define	ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
#define	ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
#define	ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
#define	ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
#define	ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
#define	ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
#define	ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
#define	ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
#define	ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
#define	ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
#define	ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
#define	ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
#define	ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
#define	ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
#define	ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
#define	ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
#define	ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
#define	ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
#define	ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
#define	ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
#define	ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
#define	ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
#define	ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
#define	ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
#define	ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
#define	ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
#define	ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
#define	ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
#define	ADC_JSQR_JL   ((uint32_t)0x00300000)
#define	ADC_JSQR_JL_0   ((uint32_t)0x00100000)
#define	ADC_JSQR_JL_1   ((uint32_t)0x00200000)
#define	ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
#define	ADC_DR_DATA   ((uint32_t)0x0000FFFF)
#define	ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
#define	DAC_CR_EN1   ((uint32_t)0x00000001)
#define	DAC_CR_BOFF1   ((uint32_t)0x00000002)
#define	DAC_CR_TEN1   ((uint32_t)0x00000004)
#define	DAC_CR_TSEL1   ((uint32_t)0x00000038)
#define	DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
#define	DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
#define	DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
#define	DAC_CR_WAVE1   ((uint32_t)0x000000C0)
#define	DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
#define	DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
#define	DAC_CR_MAMP1   ((uint32_t)0x00000F00)
#define	DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
#define	DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
#define	DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
#define	DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
#define	DAC_CR_DMAEN1   ((uint32_t)0x00001000)
#define	DAC_CR_EN2   ((uint32_t)0x00010000)
#define	DAC_CR_BOFF2   ((uint32_t)0x00020000)
#define	DAC_CR_TEN2   ((uint32_t)0x00040000)
#define	DAC_CR_TSEL2   ((uint32_t)0x00380000)
#define	DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
#define	DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
#define	DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
#define	DAC_CR_WAVE2   ((uint32_t)0x00C00000)
#define	DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
#define	DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
#define	DAC_CR_MAMP2   ((uint32_t)0x0F000000)
#define	DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
#define	DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
#define	DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
#define	DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
#define	DAC_CR_DMAEN2   ((uint32_t)0x10000000)
#define	DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
#define	DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
#define	DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
#define	DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
#define	DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
#define	DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
#define	DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
#define	DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
#define	DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
#define	DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
#define	DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
#define	DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
#define	DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
#define	DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
#define	CEC_CFGR_PE   ((uint16_t)0x0001)
#define	CEC_CFGR_IE   ((uint16_t)0x0002)
#define	CEC_CFGR_BTEM   ((uint16_t)0x0004)
#define	CEC_CFGR_BPEM   ((uint16_t)0x0008)
#define	CEC_OAR_OA   ((uint16_t)0x000F)
#define	CEC_OAR_OA_0   ((uint16_t)0x0001)
#define	CEC_OAR_OA_1   ((uint16_t)0x0002)
#define	CEC_OAR_OA_2   ((uint16_t)0x0004)
#define	CEC_OAR_OA_3   ((uint16_t)0x0008)
#define	CEC_PRES_PRES   ((uint16_t)0x3FFF)
#define	CEC_ESR_BTE   ((uint16_t)0x0001)
#define	CEC_ESR_BPE   ((uint16_t)0x0002)
#define	CEC_ESR_RBTFE   ((uint16_t)0x0004)
#define	CEC_ESR_SBE   ((uint16_t)0x0008)
#define	CEC_ESR_ACKE   ((uint16_t)0x0010)
#define	CEC_ESR_LINE   ((uint16_t)0x0020)
#define	CEC_ESR_TBTFE   ((uint16_t)0x0040)
#define	CEC_CSR_TSOM   ((uint16_t)0x0001)
#define	CEC_CSR_TEOM   ((uint16_t)0x0002)
#define	CEC_CSR_TERR   ((uint16_t)0x0004)
#define	CEC_CSR_TBTRF   ((uint16_t)0x0008)
#define	CEC_CSR_RSOM   ((uint16_t)0x0010)
#define	CEC_CSR_REOM   ((uint16_t)0x0020)
#define	CEC_CSR_RERR   ((uint16_t)0x0040)
#define	CEC_CSR_RBTF   ((uint16_t)0x0080)
#define	CEC_TXD_TXD   ((uint16_t)0x00FF)
#define	CEC_RXD_RXD   ((uint16_t)0x00FF)
#define	TIM_CR1_CEN   ((uint16_t)0x0001)
#define	TIM_CR1_UDIS   ((uint16_t)0x0002)
#define	TIM_CR1_URS   ((uint16_t)0x0004)
#define	TIM_CR1_OPM   ((uint16_t)0x0008)
#define	TIM_CR1_DIR   ((uint16_t)0x0010)
#define	TIM_CR1_CMS   ((uint16_t)0x0060)
#define	TIM_CR1_CMS_0   ((uint16_t)0x0020)
#define	TIM_CR1_CMS_1   ((uint16_t)0x0040)
#define	TIM_CR1_ARPE   ((uint16_t)0x0080)
#define	TIM_CR1_CKD   ((uint16_t)0x0300)
#define	TIM_CR1_CKD_0   ((uint16_t)0x0100)
#define	TIM_CR1_CKD_1   ((uint16_t)0x0200)
#define	TIM_CR2_CCPC   ((uint16_t)0x0001)
#define	TIM_CR2_CCUS   ((uint16_t)0x0004)
#define	TIM_CR2_CCDS   ((uint16_t)0x0008)
#define	TIM_CR2_MMS   ((uint16_t)0x0070)
#define	TIM_CR2_MMS_0   ((uint16_t)0x0010)
#define	TIM_CR2_MMS_1   ((uint16_t)0x0020)
#define	TIM_CR2_MMS_2   ((uint16_t)0x0040)
#define	TIM_CR2_TI1S   ((uint16_t)0x0080)
#define	TIM_CR2_OIS1   ((uint16_t)0x0100)
#define	TIM_CR2_OIS1N   ((uint16_t)0x0200)
#define	TIM_CR2_OIS2   ((uint16_t)0x0400)
#define	TIM_CR2_OIS2N   ((uint16_t)0x0800)
#define	TIM_CR2_OIS3   ((uint16_t)0x1000)
#define	TIM_CR2_OIS3N   ((uint16_t)0x2000)
#define	TIM_CR2_OIS4   ((uint16_t)0x4000)
#define	TIM_SMCR_SMS   ((uint16_t)0x0007)
#define	TIM_SMCR_SMS_0   ((uint16_t)0x0001)
#define	TIM_SMCR_SMS_1   ((uint16_t)0x0002)
#define	TIM_SMCR_SMS_2   ((uint16_t)0x0004)
#define	TIM_SMCR_TS   ((uint16_t)0x0070)
#define	TIM_SMCR_TS_0   ((uint16_t)0x0010)
#define	TIM_SMCR_TS_1   ((uint16_t)0x0020)
#define	TIM_SMCR_TS_2   ((uint16_t)0x0040)
#define	TIM_SMCR_MSM   ((uint16_t)0x0080)
#define	TIM_SMCR_ETF   ((uint16_t)0x0F00)
#define	TIM_SMCR_ETF_0   ((uint16_t)0x0100)
#define	TIM_SMCR_ETF_1   ((uint16_t)0x0200)
#define	TIM_SMCR_ETF_2   ((uint16_t)0x0400)
#define	TIM_SMCR_ETF_3   ((uint16_t)0x0800)
#define	TIM_SMCR_ETPS   ((uint16_t)0x3000)
#define	TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
#define	TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
#define	TIM_SMCR_ECE   ((uint16_t)0x4000)
#define	TIM_SMCR_ETP   ((uint16_t)0x8000)
#define	TIM_DIER_UIE   ((uint16_t)0x0001)
#define	TIM_DIER_CC1IE   ((uint16_t)0x0002)
#define	TIM_DIER_CC2IE   ((uint16_t)0x0004)
#define	TIM_DIER_CC3IE   ((uint16_t)0x0008)
#define	TIM_DIER_CC4IE   ((uint16_t)0x0010)
#define	TIM_DIER_COMIE   ((uint16_t)0x0020)
#define	TIM_DIER_TIE   ((uint16_t)0x0040)
#define	TIM_DIER_BIE   ((uint16_t)0x0080)
#define	TIM_DIER_UDE   ((uint16_t)0x0100)
#define	TIM_DIER_CC1DE   ((uint16_t)0x0200)
#define	TIM_DIER_CC2DE   ((uint16_t)0x0400)
#define	TIM_DIER_CC3DE   ((uint16_t)0x0800)
#define	TIM_DIER_CC4DE   ((uint16_t)0x1000)
#define	TIM_DIER_COMDE   ((uint16_t)0x2000)
#define	TIM_DIER_TDE   ((uint16_t)0x4000)
#define	TIM_SR_UIF   ((uint16_t)0x0001)
#define	TIM_SR_CC1IF   ((uint16_t)0x0002)
#define	TIM_SR_CC2IF   ((uint16_t)0x0004)
#define	TIM_SR_CC3IF   ((uint16_t)0x0008)
#define	TIM_SR_CC4IF   ((uint16_t)0x0010)
#define	TIM_SR_COMIF   ((uint16_t)0x0020)
#define	TIM_SR_TIF   ((uint16_t)0x0040)
#define	TIM_SR_BIF   ((uint16_t)0x0080)
#define	TIM_SR_CC1OF   ((uint16_t)0x0200)
#define	TIM_SR_CC2OF   ((uint16_t)0x0400)
#define	TIM_SR_CC3OF   ((uint16_t)0x0800)
#define	TIM_SR_CC4OF   ((uint16_t)0x1000)
#define	TIM_EGR_UG   ((uint8_t)0x01)
#define	TIM_EGR_CC1G   ((uint8_t)0x02)
#define	TIM_EGR_CC2G   ((uint8_t)0x04)
#define	TIM_EGR_CC3G   ((uint8_t)0x08)
#define	TIM_EGR_CC4G   ((uint8_t)0x10)
#define	TIM_EGR_COMG   ((uint8_t)0x20)
#define	TIM_EGR_TG   ((uint8_t)0x40)
#define	TIM_EGR_BG   ((uint8_t)0x80)
#define	TIM_CCMR1_CC1S   ((uint16_t)0x0003)
#define	TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
#define	TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
#define	TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
#define	TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
#define	TIM_CCMR1_OC1M   ((uint16_t)0x0070)
#define	TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
#define	TIM_CCMR1_CC2S   ((uint16_t)0x0300)
#define	TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
#define	TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
#define	TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
#define	TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
#define	TIM_CCMR1_OC2M   ((uint16_t)0x7000)
#define	TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
#define	TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
#define	TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
#define	TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
#define	TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR1_IC2F   ((uint16_t)0xF000)
#define	TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
#define	TIM_CCMR2_CC3S   ((uint16_t)0x0003)
#define	TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
#define	TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
#define	TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
#define	TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
#define	TIM_CCMR2_OC3M   ((uint16_t)0x0070)
#define	TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
#define	TIM_CCMR2_CC4S   ((uint16_t)0x0300)
#define	TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
#define	TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
#define	TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
#define	TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
#define	TIM_CCMR2_OC4M   ((uint16_t)0x7000)
#define	TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
#define	TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
#define	TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
#define	TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
#define	TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR2_IC4F   ((uint16_t)0xF000)
#define	TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
#define	TIM_CCER_CC1E   ((uint16_t)0x0001)
#define	TIM_CCER_CC1P   ((uint16_t)0x0002)
#define	TIM_CCER_CC1NE   ((uint16_t)0x0004)
#define	TIM_CCER_CC1NP   ((uint16_t)0x0008)
#define	TIM_CCER_CC2E   ((uint16_t)0x0010)
#define	TIM_CCER_CC2P   ((uint16_t)0x0020)
#define	TIM_CCER_CC2NE   ((uint16_t)0x0040)
#define	TIM_CCER_CC2NP   ((uint16_t)0x0080)
#define	TIM_CCER_CC3E   ((uint16_t)0x0100)
#define	TIM_CCER_CC3P   ((uint16_t)0x0200)
#define	TIM_CCER_CC3NE   ((uint16_t)0x0400)
#define	TIM_CCER_CC3NP   ((uint16_t)0x0800)
#define	TIM_CCER_CC4E   ((uint16_t)0x1000)
#define	TIM_CCER_CC4P   ((uint16_t)0x2000)
#define	TIM_CNT_CNT   ((uint16_t)0xFFFF)
#define	TIM_PSC_PSC   ((uint16_t)0xFFFF)
#define	TIM_ARR_ARR   ((uint16_t)0xFFFF)
#define	TIM_RCR_REP   ((uint8_t)0xFF)
#define	TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
#define	TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
#define	TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
#define	TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
#define	TIM_BDTR_DTG   ((uint16_t)0x00FF)
#define	TIM_BDTR_DTG_0   ((uint16_t)0x0001)
#define	TIM_BDTR_DTG_1   ((uint16_t)0x0002)
#define	TIM_BDTR_DTG_2   ((uint16_t)0x0004)
#define	TIM_BDTR_DTG_3   ((uint16_t)0x0008)
#define	TIM_BDTR_DTG_4   ((uint16_t)0x0010)
#define	TIM_BDTR_DTG_5   ((uint16_t)0x0020)
#define	TIM_BDTR_DTG_6   ((uint16_t)0x0040)
#define	TIM_BDTR_DTG_7   ((uint16_t)0x0080)
#define	TIM_BDTR_LOCK   ((uint16_t)0x0300)
#define	TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
#define	TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
#define	TIM_BDTR_OSSI   ((uint16_t)0x0400)
#define	TIM_BDTR_OSSR   ((uint16_t)0x0800)
#define	TIM_BDTR_BKE   ((uint16_t)0x1000)
#define	TIM_BDTR_BKP   ((uint16_t)0x2000)
#define	TIM_BDTR_AOE   ((uint16_t)0x4000)
#define	TIM_BDTR_MOE   ((uint16_t)0x8000)
#define	TIM_DCR_DBA   ((uint16_t)0x001F)
#define	TIM_DCR_DBA_0   ((uint16_t)0x0001)
#define	TIM_DCR_DBA_1   ((uint16_t)0x0002)
#define	TIM_DCR_DBA_2   ((uint16_t)0x0004)
#define	TIM_DCR_DBA_3   ((uint16_t)0x0008)
#define	TIM_DCR_DBA_4   ((uint16_t)0x0010)
#define	TIM_DCR_DBL   ((uint16_t)0x1F00)
#define	TIM_DCR_DBL_0   ((uint16_t)0x0100)
#define	TIM_DCR_DBL_1   ((uint16_t)0x0200)
#define	TIM_DCR_DBL_2   ((uint16_t)0x0400)
#define	TIM_DCR_DBL_3   ((uint16_t)0x0800)
#define	TIM_DCR_DBL_4   ((uint16_t)0x1000)
#define	TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
#define	RTC_CRH_SECIE   ((uint8_t)0x01)
#define	RTC_CRH_ALRIE   ((uint8_t)0x02)
#define	RTC_CRH_OWIE   ((uint8_t)0x04)
#define	RTC_CRL_SECF   ((uint8_t)0x01)
#define	RTC_CRL_ALRF   ((uint8_t)0x02)
#define	RTC_CRL_OWF   ((uint8_t)0x04)
#define	RTC_CRL_RSF   ((uint8_t)0x08)
#define	RTC_CRL_CNF   ((uint8_t)0x10)
#define	RTC_CRL_RTOFF   ((uint8_t)0x20)
#define	RTC_PRLH_PRL   ((uint16_t)0x000F)
#define	RTC_PRLL_PRL   ((uint16_t)0xFFFF)
#define	RTC_DIVH_RTC_DIV   ((uint16_t)0x000F)
#define	RTC_DIVL_RTC_DIV   ((uint16_t)0xFFFF)
#define	RTC_CNTH_RTC_CNT   ((uint16_t)0xFFFF)
#define	RTC_CNTL_RTC_CNT   ((uint16_t)0xFFFF)
#define	RTC_ALRH_RTC_ALR   ((uint16_t)0xFFFF)
#define	RTC_ALRL_RTC_ALR   ((uint16_t)0xFFFF)
#define	IWDG_KR_KEY   ((uint16_t)0xFFFF)
#define	IWDG_PR_PR   ((uint8_t)0x07)
#define	IWDG_PR_PR_0   ((uint8_t)0x01)
#define	IWDG_PR_PR_1   ((uint8_t)0x02)
#define	IWDG_PR_PR_2   ((uint8_t)0x04)
#define	IWDG_RLR_RL   ((uint16_t)0x0FFF)
#define	IWDG_SR_PVU   ((uint8_t)0x01)
#define	IWDG_SR_RVU   ((uint8_t)0x02)
#define	WWDG_CR_T   ((uint8_t)0x7F)
#define	WWDG_CR_T0   ((uint8_t)0x01)
#define	WWDG_CR_T1   ((uint8_t)0x02)
#define	WWDG_CR_T2   ((uint8_t)0x04)
#define	WWDG_CR_T3   ((uint8_t)0x08)
#define	WWDG_CR_T4   ((uint8_t)0x10)
#define	WWDG_CR_T5   ((uint8_t)0x20)
#define	WWDG_CR_T6   ((uint8_t)0x40)
#define	WWDG_CR_WDGA   ((uint8_t)0x80)
#define	WWDG_CFR_W   ((uint16_t)0x007F)
#define	WWDG_CFR_W0   ((uint16_t)0x0001)
#define	WWDG_CFR_W1   ((uint16_t)0x0002)
#define	WWDG_CFR_W2   ((uint16_t)0x0004)
#define	WWDG_CFR_W3   ((uint16_t)0x0008)
#define	WWDG_CFR_W4   ((uint16_t)0x0010)
#define	WWDG_CFR_W5   ((uint16_t)0x0020)
#define	WWDG_CFR_W6   ((uint16_t)0x0040)
#define	WWDG_CFR_WDGTB   ((uint16_t)0x0180)
#define	WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
#define	WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
#define	WWDG_CFR_EWI   ((uint16_t)0x0200)
#define	WWDG_SR_EWIF   ((uint8_t)0x01)
#define	FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR1_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR1_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR2_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR2_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR3_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR3_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR4_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR4_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR2_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR3_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR4_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_SR2_IRS   ((uint8_t)0x01)
#define	FSMC_SR2_ILS   ((uint8_t)0x02)
#define	FSMC_SR2_IFS   ((uint8_t)0x04)
#define	FSMC_SR2_IREN   ((uint8_t)0x08)
#define	FSMC_SR2_ILEN   ((uint8_t)0x10)
#define	FSMC_SR2_IFEN   ((uint8_t)0x20)
#define	FSMC_SR2_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR3_IRS   ((uint8_t)0x01)
#define	FSMC_SR3_ILS   ((uint8_t)0x02)
#define	FSMC_SR3_IFS   ((uint8_t)0x04)
#define	FSMC_SR3_IREN   ((uint8_t)0x08)
#define	FSMC_SR3_ILEN   ((uint8_t)0x10)
#define	FSMC_SR3_IFEN   ((uint8_t)0x20)
#define	FSMC_SR3_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR4_IRS   ((uint8_t)0x01)
#define	FSMC_SR4_ILS   ((uint8_t)0x02)
#define	FSMC_SR4_IFS   ((uint8_t)0x04)
#define	FSMC_SR4_IREN   ((uint8_t)0x08)
#define	FSMC_SR4_ILEN   ((uint8_t)0x10)
#define	FSMC_SR4_IFEN   ((uint8_t)0x20)
#define	FSMC_SR4_FEMPT   ((uint8_t)0x40)
#define	FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
#define	FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
#define	FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
#define	FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
#define	FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
#define	FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
#define	FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
#define	FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
#define	FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
#define	SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
#define	SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
#define	SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
#define	SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
#define	SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
#define	SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
#define	SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
#define	SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
#define	SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
#define	SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
#define	SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
#define	SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
#define	SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
#define	SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
#define	SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
#define	SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
#define	SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
#define	SDIO_CMD_WAITINT   ((uint16_t)0x0100)
#define	SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
#define	SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
#define	SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
#define	SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
#define	SDIO_CMD_NIEN   ((uint16_t)0x2000)
#define	SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
#define	SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
#define	SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
#define	SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
#define	SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
#define	SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
#define	SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
#define	SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
#define	SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
#define	SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
#define	SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
#define	SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
#define	SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
#define	SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
#define	SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
#define	SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
#define	SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
#define	SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
#define	SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
#define	SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
#define	SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
#define	SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
#define	SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
#define	SDIO_STA_CMDREND   ((uint32_t)0x00000040)
#define	SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
#define	SDIO_STA_DATAEND   ((uint32_t)0x00000100)
#define	SDIO_STA_STBITERR   ((uint32_t)0x00000200)
#define	SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
#define	SDIO_STA_CMDACT   ((uint32_t)0x00000800)
#define	SDIO_STA_TXACT   ((uint32_t)0x00001000)
#define	SDIO_STA_RXACT   ((uint32_t)0x00002000)
#define	SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
#define	SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
#define	SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
#define	SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
#define	SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
#define	SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
#define	SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
#define	SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
#define	SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
#define	SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
#define	SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
#define	SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
#define	SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
#define	SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
#define	SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
#define	SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
#define	SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
#define	SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
#define	SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
#define	SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
#define	SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
#define	SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
#define	SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
#define	SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
#define	SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
#define	SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
#define	SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
#define	SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
#define	SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
#define	SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
#define	SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
#define	SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
#define	SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
#define	SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
#define	SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
#define	SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
#define	SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
#define	SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
#define	SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
#define	SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
#define	SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
#define	SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
#define	SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
#define	SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
#define	SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
#define	SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
#define	SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
#define	SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
#define	SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
#define	USB_EP0R_EA   ((uint16_t)0x000F)
#define	USB_EP0R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP0R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP0R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP0R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP0R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP0R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP0R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP0R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP0R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP0R_SETUP   ((uint16_t)0x0800)
#define	USB_EP0R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP0R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP0R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP0R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP0R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP1R_EA   ((uint16_t)0x000F)
#define	USB_EP1R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP1R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP1R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP1R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP1R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP1R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP1R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP1R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP1R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP1R_SETUP   ((uint16_t)0x0800)
#define	USB_EP1R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP1R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP1R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP1R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP1R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP2R_EA   ((uint16_t)0x000F)
#define	USB_EP2R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP2R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP2R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP2R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP2R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP2R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP2R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP2R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP2R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP2R_SETUP   ((uint16_t)0x0800)
#define	USB_EP2R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP2R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP2R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP2R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP2R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP3R_EA   ((uint16_t)0x000F)
#define	USB_EP3R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP3R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP3R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP3R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP3R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP3R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP3R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP3R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP3R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP3R_SETUP   ((uint16_t)0x0800)
#define	USB_EP3R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP3R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP3R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP3R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP3R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP4R_EA   ((uint16_t)0x000F)
#define	USB_EP4R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP4R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP4R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP4R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP4R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP4R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP4R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP4R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP4R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP4R_SETUP   ((uint16_t)0x0800)
#define	USB_EP4R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP4R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP4R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP4R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP4R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP5R_EA   ((uint16_t)0x000F)
#define	USB_EP5R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP5R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP5R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP5R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP5R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP5R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP5R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP5R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP5R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP5R_SETUP   ((uint16_t)0x0800)
#define	USB_EP5R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP5R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP5R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP5R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP5R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP6R_EA   ((uint16_t)0x000F)
#define	USB_EP6R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP6R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP6R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP6R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP6R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP6R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP6R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP6R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP6R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP6R_SETUP   ((uint16_t)0x0800)
#define	USB_EP6R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP6R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP6R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP6R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP6R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP7R_EA   ((uint16_t)0x000F)
#define	USB_EP7R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP7R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP7R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP7R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP7R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP7R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP7R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP7R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP7R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP7R_SETUP   ((uint16_t)0x0800)
#define	USB_EP7R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP7R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP7R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP7R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP7R_CTR_RX   ((uint16_t)0x8000)
#define	USB_CNTR_FRES   ((uint16_t)0x0001)
#define	USB_CNTR_PDWN   ((uint16_t)0x0002)
#define	USB_CNTR_LP_MODE   ((uint16_t)0x0004)
#define	USB_CNTR_FSUSP   ((uint16_t)0x0008)
#define	USB_CNTR_RESUME   ((uint16_t)0x0010)
#define	USB_CNTR_ESOFM   ((uint16_t)0x0100)
#define	USB_CNTR_SOFM   ((uint16_t)0x0200)
#define	USB_CNTR_RESETM   ((uint16_t)0x0400)
#define	USB_CNTR_SUSPM   ((uint16_t)0x0800)
#define	USB_CNTR_WKUPM   ((uint16_t)0x1000)
#define	USB_CNTR_ERRM   ((uint16_t)0x2000)
#define	USB_CNTR_PMAOVRM   ((uint16_t)0x4000)
#define	USB_CNTR_CTRM   ((uint16_t)0x8000)
#define	USB_ISTR_EP_ID   ((uint16_t)0x000F)
#define	USB_ISTR_DIR   ((uint16_t)0x0010)
#define	USB_ISTR_ESOF   ((uint16_t)0x0100)
#define	USB_ISTR_SOF   ((uint16_t)0x0200)
#define	USB_ISTR_RESET   ((uint16_t)0x0400)
#define	USB_ISTR_SUSP   ((uint16_t)0x0800)
#define	USB_ISTR_WKUP   ((uint16_t)0x1000)
#define	USB_ISTR_ERR   ((uint16_t)0x2000)
#define	USB_ISTR_PMAOVR   ((uint16_t)0x4000)
#define	USB_ISTR_CTR   ((uint16_t)0x8000)
#define	USB_FNR_FN   ((uint16_t)0x07FF)
#define	USB_FNR_LSOF   ((uint16_t)0x1800)
#define	USB_FNR_LCK   ((uint16_t)0x2000)
#define	USB_FNR_RXDM   ((uint16_t)0x4000)
#define	USB_FNR_RXDP   ((uint16_t)0x8000)
#define	USB_DADDR_ADD   ((uint8_t)0x7F)
#define	USB_DADDR_ADD0   ((uint8_t)0x01)
#define	USB_DADDR_ADD1   ((uint8_t)0x02)
#define	USB_DADDR_ADD2   ((uint8_t)0x04)
#define	USB_DADDR_ADD3   ((uint8_t)0x08)
#define	USB_DADDR_ADD4   ((uint8_t)0x10)
#define	USB_DADDR_ADD5   ((uint8_t)0x20)
#define	USB_DADDR_ADD6   ((uint8_t)0x40)
#define	USB_DADDR_EF   ((uint8_t)0x80)
#define	USB_BTABLE_BTABLE   ((uint16_t)0xFFF8)
#define	USB_ADDR0_TX_ADDR0_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR1_TX_ADDR1_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR2_TX_ADDR2_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR3_TX_ADDR3_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR4_TX_ADDR4_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR5_TX_ADDR5_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR6_TX_ADDR6_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR7_TX_ADDR7_TX   ((uint16_t)0xFFFE)
#define	USB_COUNT0_TX_COUNT0_TX   ((uint16_t)0x03FF)
#define	USB_COUNT1_TX_COUNT1_TX   ((uint16_t)0x03FF)
#define	USB_COUNT2_TX_COUNT2_TX   ((uint16_t)0x03FF)
#define	USB_COUNT3_TX_COUNT3_TX   ((uint16_t)0x03FF)
#define	USB_COUNT4_TX_COUNT4_TX   ((uint16_t)0x03FF)
#define	USB_COUNT5_TX_COUNT5_TX   ((uint16_t)0x03FF)
#define	USB_COUNT6_TX_COUNT6_TX   ((uint16_t)0x03FF)
#define	USB_COUNT7_TX_COUNT7_TX   ((uint16_t)0x03FF)
#define	USB_COUNT0_TX_0_COUNT0_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT0_TX_1_COUNT0_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT1_TX_0_COUNT1_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT1_TX_1_COUNT1_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT2_TX_0_COUNT2_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT2_TX_1_COUNT2_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT3_TX_0_COUNT3_TX_0   ((uint16_t)0x000003FF)
#define	USB_COUNT3_TX_1_COUNT3_TX_1   ((uint16_t)0x03FF0000)
#define	USB_COUNT4_TX_0_COUNT4_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT4_TX_1_COUNT4_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT5_TX_0_COUNT5_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT5_TX_1_COUNT5_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT6_TX_0_COUNT6_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT6_TX_1_COUNT6_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT7_TX_0_COUNT7_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT7_TX_1_COUNT7_TX_1   ((uint32_t)0x03FF0000)
#define	USB_ADDR0_RX_ADDR0_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR1_RX_ADDR1_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR2_RX_ADDR2_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR3_RX_ADDR3_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR4_RX_ADDR4_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR5_RX_ADDR5_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR6_RX_ADDR6_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR7_RX_ADDR7_RX   ((uint16_t)0xFFFE)
#define	USB_COUNT0_RX_COUNT0_RX   ((uint16_t)0x03FF)
#define	USB_COUNT0_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT0_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT0_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT0_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT0_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT0_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT0_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT1_RX_COUNT1_RX   ((uint16_t)0x03FF)
#define	USB_COUNT1_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT1_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT1_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT1_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT1_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT1_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT1_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT2_RX_COUNT2_RX   ((uint16_t)0x03FF)
#define	USB_COUNT2_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT2_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT2_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT2_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT2_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT2_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT2_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT3_RX_COUNT3_RX   ((uint16_t)0x03FF)
#define	USB_COUNT3_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT3_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT3_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT3_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT3_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT3_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT3_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT4_RX_COUNT4_RX   ((uint16_t)0x03FF)
#define	USB_COUNT4_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT4_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT4_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT4_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT4_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT4_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT4_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT5_RX_COUNT5_RX   ((uint16_t)0x03FF)
#define	USB_COUNT5_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT5_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT5_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT5_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT5_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT5_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT5_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT6_RX_COUNT6_RX   ((uint16_t)0x03FF)
#define	USB_COUNT6_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT6_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT6_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT6_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT6_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT6_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT6_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT7_RX_COUNT7_RX   ((uint16_t)0x03FF)
#define	USB_COUNT7_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT7_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT7_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT7_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT7_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT7_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT7_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT0_RX_0_COUNT0_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT0_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT0_RX_1_COUNT0_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT0_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT1_RX_0_COUNT1_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT1_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT1_RX_1_COUNT1_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT1_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT2_RX_0_COUNT2_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT2_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT2_RX_1_COUNT2_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT2_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT3_RX_0_COUNT3_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT3_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT3_RX_1_COUNT3_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT3_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT4_RX_0_COUNT4_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT4_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT4_RX_1_COUNT4_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT4_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT5_RX_0_COUNT5_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT5_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT5_RX_1_COUNT5_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT5_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT6_RX_0_COUNT6_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT6_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT6_RX_1_COUNT6_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT6_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT7_RX_0_COUNT7_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT7_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT7_RX_1_COUNT7_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT7_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	CAN_MCR_INRQ   ((uint16_t)0x0001)
#define	CAN_MCR_SLEEP   ((uint16_t)0x0002)
#define	CAN_MCR_TXFP   ((uint16_t)0x0004)
#define	CAN_MCR_RFLM   ((uint16_t)0x0008)
#define	CAN_MCR_NART   ((uint16_t)0x0010)
#define	CAN_MCR_AWUM   ((uint16_t)0x0020)
#define	CAN_MCR_ABOM   ((uint16_t)0x0040)
#define	CAN_MCR_TTCM   ((uint16_t)0x0080)
#define	CAN_MCR_RESET   ((uint16_t)0x8000)
#define	CAN_MSR_INAK   ((uint16_t)0x0001)
#define	CAN_MSR_SLAK   ((uint16_t)0x0002)
#define	CAN_MSR_ERRI   ((uint16_t)0x0004)
#define	CAN_MSR_WKUI   ((uint16_t)0x0008)
#define	CAN_MSR_SLAKI   ((uint16_t)0x0010)
#define	CAN_MSR_TXM   ((uint16_t)0x0100)
#define	CAN_MSR_RXM   ((uint16_t)0x0200)
#define	CAN_MSR_SAMP   ((uint16_t)0x0400)
#define	CAN_MSR_RX   ((uint16_t)0x0800)
#define	CAN_TSR_RQCP0   ((uint32_t)0x00000001)
#define	CAN_TSR_TXOK0   ((uint32_t)0x00000002)
#define	CAN_TSR_ALST0   ((uint32_t)0x00000004)
#define	CAN_TSR_TERR0   ((uint32_t)0x00000008)
#define	CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
#define	CAN_TSR_RQCP1   ((uint32_t)0x00000100)
#define	CAN_TSR_TXOK1   ((uint32_t)0x00000200)
#define	CAN_TSR_ALST1   ((uint32_t)0x00000400)
#define	CAN_TSR_TERR1   ((uint32_t)0x00000800)
#define	CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
#define	CAN_TSR_RQCP2   ((uint32_t)0x00010000)
#define	CAN_TSR_TXOK2   ((uint32_t)0x00020000)
#define	CAN_TSR_ALST2   ((uint32_t)0x00040000)
#define	CAN_TSR_TERR2   ((uint32_t)0x00080000)
#define	CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
#define	CAN_TSR_CODE   ((uint32_t)0x03000000)
#define	CAN_TSR_TME   ((uint32_t)0x1C000000)
#define	CAN_TSR_TME0   ((uint32_t)0x04000000)
#define	CAN_TSR_TME1   ((uint32_t)0x08000000)
#define	CAN_TSR_TME2   ((uint32_t)0x10000000)
#define	CAN_TSR_LOW   ((uint32_t)0xE0000000)
#define	CAN_TSR_LOW0   ((uint32_t)0x20000000)
#define	CAN_TSR_LOW1   ((uint32_t)0x40000000)
#define	CAN_TSR_LOW2   ((uint32_t)0x80000000)
#define	CAN_RF0R_FMP0   ((uint8_t)0x03)
#define	CAN_RF0R_FULL0   ((uint8_t)0x08)
#define	CAN_RF0R_FOVR0   ((uint8_t)0x10)
#define	CAN_RF0R_RFOM0   ((uint8_t)0x20)
#define	CAN_RF1R_FMP1   ((uint8_t)0x03)
#define	CAN_RF1R_FULL1   ((uint8_t)0x08)
#define	CAN_RF1R_FOVR1   ((uint8_t)0x10)
#define	CAN_RF1R_RFOM1   ((uint8_t)0x20)
#define	CAN_IER_TMEIE   ((uint32_t)0x00000001)
#define	CAN_IER_FMPIE0   ((uint32_t)0x00000002)
#define	CAN_IER_FFIE0   ((uint32_t)0x00000004)
#define	CAN_IER_FOVIE0   ((uint32_t)0x00000008)
#define	CAN_IER_FMPIE1   ((uint32_t)0x00000010)
#define	CAN_IER_FFIE1   ((uint32_t)0x00000020)
#define	CAN_IER_FOVIE1   ((uint32_t)0x00000040)
#define	CAN_IER_EWGIE   ((uint32_t)0x00000100)
#define	CAN_IER_EPVIE   ((uint32_t)0x00000200)
#define	CAN_IER_BOFIE   ((uint32_t)0x00000400)
#define	CAN_IER_LECIE   ((uint32_t)0x00000800)
#define	CAN_IER_ERRIE   ((uint32_t)0x00008000)
#define	CAN_IER_WKUIE   ((uint32_t)0x00010000)
#define	CAN_IER_SLKIE   ((uint32_t)0x00020000)
#define	CAN_ESR_EWGF   ((uint32_t)0x00000001)
#define	CAN_ESR_EPVF   ((uint32_t)0x00000002)
#define	CAN_ESR_BOFF   ((uint32_t)0x00000004)
#define	CAN_ESR_LEC   ((uint32_t)0x00000070)
#define	CAN_ESR_LEC_0   ((uint32_t)0x00000010)
#define	CAN_ESR_LEC_1   ((uint32_t)0x00000020)
#define	CAN_ESR_LEC_2   ((uint32_t)0x00000040)
#define	CAN_ESR_TEC   ((uint32_t)0x00FF0000)
#define	CAN_ESR_REC   ((uint32_t)0xFF000000)
#define	CAN_BTR_BRP   ((uint32_t)0x000003FF)
#define	CAN_BTR_TS1   ((uint32_t)0x000F0000)
#define	CAN_BTR_TS2   ((uint32_t)0x00700000)
#define	CAN_BTR_SJW   ((uint32_t)0x03000000)
#define	CAN_BTR_LBKM   ((uint32_t)0x40000000)
#define	CAN_BTR_SILM   ((uint32_t)0x80000000)
#define	CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT0R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT1R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI2R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI2R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI2R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT2R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_FMR_FINIT   ((uint8_t)0x01)
#define	CAN_FM1R_FBM   ((uint16_t)0x3FFF)
#define	CAN_FM1R_FBM0   ((uint16_t)0x0001)
#define	CAN_FM1R_FBM1   ((uint16_t)0x0002)
#define	CAN_FM1R_FBM2   ((uint16_t)0x0004)
#define	CAN_FM1R_FBM3   ((uint16_t)0x0008)
#define	CAN_FM1R_FBM4   ((uint16_t)0x0010)
#define	CAN_FM1R_FBM5   ((uint16_t)0x0020)
#define	CAN_FM1R_FBM6   ((uint16_t)0x0040)
#define	CAN_FM1R_FBM7   ((uint16_t)0x0080)
#define	CAN_FM1R_FBM8   ((uint16_t)0x0100)
#define	CAN_FM1R_FBM9   ((uint16_t)0x0200)
#define	CAN_FM1R_FBM10   ((uint16_t)0x0400)
#define	CAN_FM1R_FBM11   ((uint16_t)0x0800)
#define	CAN_FM1R_FBM12   ((uint16_t)0x1000)
#define	CAN_FM1R_FBM13   ((uint16_t)0x2000)
#define	CAN_FS1R_FSC   ((uint16_t)0x3FFF)
#define	CAN_FS1R_FSC0   ((uint16_t)0x0001)
#define	CAN_FS1R_FSC1   ((uint16_t)0x0002)
#define	CAN_FS1R_FSC2   ((uint16_t)0x0004)
#define	CAN_FS1R_FSC3   ((uint16_t)0x0008)
#define	CAN_FS1R_FSC4   ((uint16_t)0x0010)
#define	CAN_FS1R_FSC5   ((uint16_t)0x0020)
#define	CAN_FS1R_FSC6   ((uint16_t)0x0040)
#define	CAN_FS1R_FSC7   ((uint16_t)0x0080)
#define	CAN_FS1R_FSC8   ((uint16_t)0x0100)
#define	CAN_FS1R_FSC9   ((uint16_t)0x0200)
#define	CAN_FS1R_FSC10   ((uint16_t)0x0400)
#define	CAN_FS1R_FSC11   ((uint16_t)0x0800)
#define	CAN_FS1R_FSC12   ((uint16_t)0x1000)
#define	CAN_FS1R_FSC13   ((uint16_t)0x2000)
#define	CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
#define	CAN_FFA1R_FFA0   ((uint16_t)0x0001)
#define	CAN_FFA1R_FFA1   ((uint16_t)0x0002)
#define	CAN_FFA1R_FFA2   ((uint16_t)0x0004)
#define	CAN_FFA1R_FFA3   ((uint16_t)0x0008)
#define	CAN_FFA1R_FFA4   ((uint16_t)0x0010)
#define	CAN_FFA1R_FFA5   ((uint16_t)0x0020)
#define	CAN_FFA1R_FFA6   ((uint16_t)0x0040)
#define	CAN_FFA1R_FFA7   ((uint16_t)0x0080)
#define	CAN_FFA1R_FFA8   ((uint16_t)0x0100)
#define	CAN_FFA1R_FFA9   ((uint16_t)0x0200)
#define	CAN_FFA1R_FFA10   ((uint16_t)0x0400)
#define	CAN_FFA1R_FFA11   ((uint16_t)0x0800)
#define	CAN_FFA1R_FFA12   ((uint16_t)0x1000)
#define	CAN_FFA1R_FFA13   ((uint16_t)0x2000)
#define	CAN_FA1R_FACT   ((uint16_t)0x3FFF)
#define	CAN_FA1R_FACT0   ((uint16_t)0x0001)
#define	CAN_FA1R_FACT1   ((uint16_t)0x0002)
#define	CAN_FA1R_FACT2   ((uint16_t)0x0004)
#define	CAN_FA1R_FACT3   ((uint16_t)0x0008)
#define	CAN_FA1R_FACT4   ((uint16_t)0x0010)
#define	CAN_FA1R_FACT5   ((uint16_t)0x0020)
#define	CAN_FA1R_FACT6   ((uint16_t)0x0040)
#define	CAN_FA1R_FACT7   ((uint16_t)0x0080)
#define	CAN_FA1R_FACT8   ((uint16_t)0x0100)
#define	CAN_FA1R_FACT9   ((uint16_t)0x0200)
#define	CAN_FA1R_FACT10   ((uint16_t)0x0400)
#define	CAN_FA1R_FACT11   ((uint16_t)0x0800)
#define	CAN_FA1R_FACT12   ((uint16_t)0x1000)
#define	CAN_FA1R_FACT13   ((uint16_t)0x2000)
#define	CAN_F0R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F0R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R2_FB31   ((uint32_t)0x80000000)
#define	SPI_CR1_CPHA   ((uint16_t)0x0001)
#define	SPI_CR1_CPOL   ((uint16_t)0x0002)
#define	SPI_CR1_MSTR   ((uint16_t)0x0004)
#define	SPI_CR1_BR   ((uint16_t)0x0038)
#define	SPI_CR1_BR_0   ((uint16_t)0x0008)
#define	SPI_CR1_BR_1   ((uint16_t)0x0010)
#define	SPI_CR1_BR_2   ((uint16_t)0x0020)
#define	SPI_CR1_SPE   ((uint16_t)0x0040)
#define	SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
#define	SPI_CR1_SSI   ((uint16_t)0x0100)
#define	SPI_CR1_SSM   ((uint16_t)0x0200)
#define	SPI_CR1_RXONLY   ((uint16_t)0x0400)
#define	SPI_CR1_DFF   ((uint16_t)0x0800)
#define	SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
#define	SPI_CR1_CRCEN   ((uint16_t)0x2000)
#define	SPI_CR1_BIDIOE   ((uint16_t)0x4000)
#define	SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
#define	SPI_CR2_RXDMAEN   ((uint8_t)0x01)
#define	SPI_CR2_TXDMAEN   ((uint8_t)0x02)
#define	SPI_CR2_SSOE   ((uint8_t)0x04)
#define	SPI_CR2_ERRIE   ((uint8_t)0x20)
#define	SPI_CR2_RXNEIE   ((uint8_t)0x40)
#define	SPI_CR2_TXEIE   ((uint8_t)0x80)
#define	SPI_SR_RXNE   ((uint8_t)0x01)
#define	SPI_SR_TXE   ((uint8_t)0x02)
#define	SPI_SR_CHSIDE   ((uint8_t)0x04)
#define	SPI_SR_UDR   ((uint8_t)0x08)
#define	SPI_SR_CRCERR   ((uint8_t)0x10)
#define	SPI_SR_MODF   ((uint8_t)0x20)
#define	SPI_SR_OVR   ((uint8_t)0x40)
#define	SPI_SR_BSY   ((uint8_t)0x80)
#define	SPI_DR_DR   ((uint16_t)0xFFFF)
#define	SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
#define	SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
#define	SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
#define	SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
#define	SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
#define	SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
#define	SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
#define	SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
#define	SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
#define	SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
#define	SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
#define	SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
#define	SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
#define	SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
#define	SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
#define	SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
#define	SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
#define	SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
#define	SPI_I2SPR_ODD   ((uint16_t)0x0100)
#define	SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
#define	I2C_CR1_PE   ((uint16_t)0x0001)
#define	I2C_CR1_SMBUS   ((uint16_t)0x0002)
#define	I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
#define	I2C_CR1_ENARP   ((uint16_t)0x0010)
#define	I2C_CR1_ENPEC   ((uint16_t)0x0020)
#define	I2C_CR1_ENGC   ((uint16_t)0x0040)
#define	I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
#define	I2C_CR1_START   ((uint16_t)0x0100)
#define	I2C_CR1_STOP   ((uint16_t)0x0200)
#define	I2C_CR1_ACK   ((uint16_t)0x0400)
#define	I2C_CR1_POS   ((uint16_t)0x0800)
#define	I2C_CR1_PEC   ((uint16_t)0x1000)
#define	I2C_CR1_ALERT   ((uint16_t)0x2000)
#define	I2C_CR1_SWRST   ((uint16_t)0x8000)
#define	I2C_CR2_FREQ   ((uint16_t)0x003F)
#define	I2C_CR2_FREQ_0   ((uint16_t)0x0001)
#define	I2C_CR2_FREQ_1   ((uint16_t)0x0002)
#define	I2C_CR2_FREQ_2   ((uint16_t)0x0004)
#define	I2C_CR2_FREQ_3   ((uint16_t)0x0008)
#define	I2C_CR2_FREQ_4   ((uint16_t)0x0010)
#define	I2C_CR2_FREQ_5   ((uint16_t)0x0020)
#define	I2C_CR2_ITERREN   ((uint16_t)0x0100)
#define	I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
#define	I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
#define	I2C_CR2_DMAEN   ((uint16_t)0x0800)
#define	I2C_CR2_LAST   ((uint16_t)0x1000)
#define	I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
#define	I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
#define	I2C_OAR1_ADD0   ((uint16_t)0x0001)
#define	I2C_OAR1_ADD1   ((uint16_t)0x0002)
#define	I2C_OAR1_ADD2   ((uint16_t)0x0004)
#define	I2C_OAR1_ADD3   ((uint16_t)0x0008)
#define	I2C_OAR1_ADD4   ((uint16_t)0x0010)
#define	I2C_OAR1_ADD5   ((uint16_t)0x0020)
#define	I2C_OAR1_ADD6   ((uint16_t)0x0040)
#define	I2C_OAR1_ADD7   ((uint16_t)0x0080)
#define	I2C_OAR1_ADD8   ((uint16_t)0x0100)
#define	I2C_OAR1_ADD9   ((uint16_t)0x0200)
#define	I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
#define	I2C_OAR2_ENDUAL   ((uint8_t)0x01)
#define	I2C_OAR2_ADD2   ((uint8_t)0xFE)
#define	I2C_DR_DR   ((uint8_t)0xFF)
#define	I2C_SR1_SB   ((uint16_t)0x0001)
#define	I2C_SR1_ADDR   ((uint16_t)0x0002)
#define	I2C_SR1_BTF   ((uint16_t)0x0004)
#define	I2C_SR1_ADD10   ((uint16_t)0x0008)
#define	I2C_SR1_STOPF   ((uint16_t)0x0010)
#define	I2C_SR1_RXNE   ((uint16_t)0x0040)
#define	I2C_SR1_TXE   ((uint16_t)0x0080)
#define	I2C_SR1_BERR   ((uint16_t)0x0100)
#define	I2C_SR1_ARLO   ((uint16_t)0x0200)
#define	I2C_SR1_AF   ((uint16_t)0x0400)
#define	I2C_SR1_OVR   ((uint16_t)0x0800)
#define	I2C_SR1_PECERR   ((uint16_t)0x1000)
#define	I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
#define	I2C_SR1_SMBALERT   ((uint16_t)0x8000)
#define	I2C_SR2_MSL   ((uint16_t)0x0001)
#define	I2C_SR2_BUSY   ((uint16_t)0x0002)
#define	I2C_SR2_TRA   ((uint16_t)0x0004)
#define	I2C_SR2_GENCALL   ((uint16_t)0x0010)
#define	I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
#define	I2C_SR2_SMBHOST   ((uint16_t)0x0040)
#define	I2C_SR2_DUALF   ((uint16_t)0x0080)
#define	I2C_SR2_PEC   ((uint16_t)0xFF00)
#define	I2C_CCR_CCR   ((uint16_t)0x0FFF)
#define	I2C_CCR_DUTY   ((uint16_t)0x4000)
#define	I2C_CCR_FS   ((uint16_t)0x8000)
#define	I2C_TRISE_TRISE   ((uint8_t)0x3F)
#define	USART_SR_PE   ((uint16_t)0x0001)
#define	USART_SR_FE   ((uint16_t)0x0002)
#define	USART_SR_NE   ((uint16_t)0x0004)
#define	USART_SR_ORE   ((uint16_t)0x0008)
#define	USART_SR_IDLE   ((uint16_t)0x0010)
#define	USART_SR_RXNE   ((uint16_t)0x0020)
#define	USART_SR_TC   ((uint16_t)0x0040)
#define	USART_SR_TXE   ((uint16_t)0x0080)
#define	USART_SR_LBD   ((uint16_t)0x0100)
#define	USART_SR_CTS   ((uint16_t)0x0200)
#define	USART_DR_DR   ((uint16_t)0x01FF)
#define	USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
#define	USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
#define	USART_CR1_SBK   ((uint16_t)0x0001)
#define	USART_CR1_RWU   ((uint16_t)0x0002)
#define	USART_CR1_RE   ((uint16_t)0x0004)
#define	USART_CR1_TE   ((uint16_t)0x0008)
#define	USART_CR1_IDLEIE   ((uint16_t)0x0010)
#define	USART_CR1_RXNEIE   ((uint16_t)0x0020)
#define	USART_CR1_TCIE   ((uint16_t)0x0040)
#define	USART_CR1_TXEIE   ((uint16_t)0x0080)
#define	USART_CR1_PEIE   ((uint16_t)0x0100)
#define	USART_CR1_PS   ((uint16_t)0x0200)
#define	USART_CR1_PCE   ((uint16_t)0x0400)
#define	USART_CR1_WAKE   ((uint16_t)0x0800)
#define	USART_CR1_M   ((uint16_t)0x1000)
#define	USART_CR1_UE   ((uint16_t)0x2000)
#define	USART_CR1_OVER8   ((uint16_t)0x8000)
#define	USART_CR2_ADD   ((uint16_t)0x000F)
#define	USART_CR2_LBDL   ((uint16_t)0x0020)
#define	USART_CR2_LBDIE   ((uint16_t)0x0040)
#define	USART_CR2_LBCL   ((uint16_t)0x0100)
#define	USART_CR2_CPHA   ((uint16_t)0x0200)
#define	USART_CR2_CPOL   ((uint16_t)0x0400)
#define	USART_CR2_CLKEN   ((uint16_t)0x0800)
#define	USART_CR2_STOP   ((uint16_t)0x3000)
#define	USART_CR2_STOP_0   ((uint16_t)0x1000)
#define	USART_CR2_STOP_1   ((uint16_t)0x2000)
#define	USART_CR2_LINEN   ((uint16_t)0x4000)
#define	USART_CR3_EIE   ((uint16_t)0x0001)
#define	USART_CR3_IREN   ((uint16_t)0x0002)
#define	USART_CR3_IRLP   ((uint16_t)0x0004)
#define	USART_CR3_HDSEL   ((uint16_t)0x0008)
#define	USART_CR3_NACK   ((uint16_t)0x0010)
#define	USART_CR3_SCEN   ((uint16_t)0x0020)
#define	USART_CR3_DMAR   ((uint16_t)0x0040)
#define	USART_CR3_DMAT   ((uint16_t)0x0080)
#define	USART_CR3_RTSE   ((uint16_t)0x0100)
#define	USART_CR3_CTSE   ((uint16_t)0x0200)
#define	USART_CR3_CTSIE   ((uint16_t)0x0400)
#define	USART_CR3_ONEBIT   ((uint16_t)0x0800)
#define	USART_GTPR_PSC   ((uint16_t)0x00FF)
#define	USART_GTPR_PSC_0   ((uint16_t)0x0001)
#define	USART_GTPR_PSC_1   ((uint16_t)0x0002)
#define	USART_GTPR_PSC_2   ((uint16_t)0x0004)
#define	USART_GTPR_PSC_3   ((uint16_t)0x0008)
#define	USART_GTPR_PSC_4   ((uint16_t)0x0010)
#define	USART_GTPR_PSC_5   ((uint16_t)0x0020)
#define	USART_GTPR_PSC_6   ((uint16_t)0x0040)
#define	USART_GTPR_PSC_7   ((uint16_t)0x0080)
#define	USART_GTPR_GT   ((uint16_t)0xFF00)
#define	DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
#define	DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
#define	DBGMCU_IDCODE_REV_ID_0   ((uint32_t)0x00010000)
#define	DBGMCU_IDCODE_REV_ID_1   ((uint32_t)0x00020000)
#define	DBGMCU_IDCODE_REV_ID_2   ((uint32_t)0x00040000)
#define	DBGMCU_IDCODE_REV_ID_3   ((uint32_t)0x00080000)
#define	DBGMCU_IDCODE_REV_ID_4   ((uint32_t)0x00100000)
#define	DBGMCU_IDCODE_REV_ID_5   ((uint32_t)0x00200000)
#define	DBGMCU_IDCODE_REV_ID_6   ((uint32_t)0x00400000)
#define	DBGMCU_IDCODE_REV_ID_7   ((uint32_t)0x00800000)
#define	DBGMCU_IDCODE_REV_ID_8   ((uint32_t)0x01000000)
#define	DBGMCU_IDCODE_REV_ID_9   ((uint32_t)0x02000000)
#define	DBGMCU_IDCODE_REV_ID_10   ((uint32_t)0x04000000)
#define	DBGMCU_IDCODE_REV_ID_11   ((uint32_t)0x08000000)
#define	DBGMCU_IDCODE_REV_ID_12   ((uint32_t)0x10000000)
#define	DBGMCU_IDCODE_REV_ID_13   ((uint32_t)0x20000000)
#define	DBGMCU_IDCODE_REV_ID_14   ((uint32_t)0x40000000)
#define	DBGMCU_IDCODE_REV_ID_15   ((uint32_t)0x80000000)
#define	DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
#define	DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
#define	DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
#define	DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
#define	DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
#define	DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
#define	DBGMCU_CR_DBG_IWDG_STOP   ((uint32_t)0x00000100)
#define	DBGMCU_CR_DBG_WWDG_STOP   ((uint32_t)0x00000200)
#define	DBGMCU_CR_DBG_TIM1_STOP   ((uint32_t)0x00000400)
#define	DBGMCU_CR_DBG_TIM2_STOP   ((uint32_t)0x00000800)
#define	DBGMCU_CR_DBG_TIM3_STOP   ((uint32_t)0x00001000)
#define	DBGMCU_CR_DBG_TIM4_STOP   ((uint32_t)0x00002000)
#define	DBGMCU_CR_DBG_CAN1_STOP   ((uint32_t)0x00004000)
#define	DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00008000)
#define	DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00010000)
#define	DBGMCU_CR_DBG_TIM8_STOP   ((uint32_t)0x00020000)
#define	DBGMCU_CR_DBG_TIM5_STOP   ((uint32_t)0x00040000)
#define	DBGMCU_CR_DBG_TIM6_STOP   ((uint32_t)0x00080000)
#define	DBGMCU_CR_DBG_TIM7_STOP   ((uint32_t)0x00100000)
#define	DBGMCU_CR_DBG_CAN2_STOP   ((uint32_t)0x00200000)
#define	DBGMCU_CR_DBG_TIM15_STOP   ((uint32_t)0x00400000)
#define	DBGMCU_CR_DBG_TIM16_STOP   ((uint32_t)0x00800000)
#define	DBGMCU_CR_DBG_TIM17_STOP   ((uint32_t)0x01000000)
#define	DBGMCU_CR_DBG_TIM12_STOP   ((uint32_t)0x02000000)
#define	DBGMCU_CR_DBG_TIM13_STOP   ((uint32_t)0x04000000)
#define	DBGMCU_CR_DBG_TIM14_STOP   ((uint32_t)0x08000000)
#define	DBGMCU_CR_DBG_TIM9_STOP   ((uint32_t)0x10000000)
#define	DBGMCU_CR_DBG_TIM10_STOP   ((uint32_t)0x20000000)
#define	DBGMCU_CR_DBG_TIM11_STOP   ((uint32_t)0x40000000)
#define	FLASH_ACR_LATENCY   ((uint8_t)0x03)
#define	FLASH_ACR_LATENCY_0   ((uint8_t)0x00)
#define	FLASH_ACR_LATENCY_1   ((uint8_t)0x01)
#define	FLASH_ACR_LATENCY_2   ((uint8_t)0x02)
#define	FLASH_ACR_HLFCYA   ((uint8_t)0x08)
#define	FLASH_ACR_PRFTBE   ((uint8_t)0x10)
#define	FLASH_ACR_PRFTBS   ((uint8_t)0x20)
#define	FLASH_KEYR_FKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_OPTKEYR_OPTKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_SR_BSY   ((uint8_t)0x01)
#define	FLASH_SR_PGERR   ((uint8_t)0x04)
#define	FLASH_SR_WRPRTERR   ((uint8_t)0x10)
#define	FLASH_SR_EOP   ((uint8_t)0x20)
#define	FLASH_CR_PG   ((uint16_t)0x0001)
#define	FLASH_CR_PER   ((uint16_t)0x0002)
#define	FLASH_CR_MER   ((uint16_t)0x0004)
#define	FLASH_CR_OPTPG   ((uint16_t)0x0010)
#define	FLASH_CR_OPTER   ((uint16_t)0x0020)
#define	FLASH_CR_STRT   ((uint16_t)0x0040)
#define	FLASH_CR_LOCK   ((uint16_t)0x0080)
#define	FLASH_CR_OPTWRE   ((uint16_t)0x0200)
#define	FLASH_CR_ERRIE   ((uint16_t)0x0400)
#define	FLASH_CR_EOPIE   ((uint16_t)0x1000)
#define	FLASH_AR_FAR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_OBR_OPTERR   ((uint16_t)0x0001)
#define	FLASH_OBR_RDPRT   ((uint16_t)0x0002)
#define	FLASH_OBR_USER   ((uint16_t)0x03FC)
#define	FLASH_OBR_WDG_SW   ((uint16_t)0x0004)
#define	FLASH_OBR_nRST_STOP   ((uint16_t)0x0008)
#define	FLASH_OBR_nRST_STDBY   ((uint16_t)0x0010)
#define	FLASH_OBR_BFB2   ((uint16_t)0x0020)
#define	FLASH_WRPR_WRP   ((uint32_t)0xFFFFFFFF)
#define	FLASH_RDP_RDP   ((uint32_t)0x000000FF)
#define	FLASH_RDP_nRDP   ((uint32_t)0x0000FF00)
#define	FLASH_USER_USER   ((uint32_t)0x00FF0000)
#define	FLASH_USER_nUSER   ((uint32_t)0xFF000000)
#define	FLASH_Data0_Data0   ((uint32_t)0x000000FF)
#define	FLASH_Data0_nData0   ((uint32_t)0x0000FF00)
#define	FLASH_Data1_Data1   ((uint32_t)0x00FF0000)
#define	FLASH_Data1_nData1   ((uint32_t)0xFF000000)
#define	FLASH_WRP0_WRP0   ((uint32_t)0x000000FF)
#define	FLASH_WRP0_nWRP0   ((uint32_t)0x0000FF00)
#define	FLASH_WRP1_WRP1   ((uint32_t)0x00FF0000)
#define	FLASH_WRP1_nWRP1   ((uint32_t)0xFF000000)
#define	FLASH_WRP2_WRP2   ((uint32_t)0x000000FF)
#define	FLASH_WRP2_nWRP2   ((uint32_t)0x0000FF00)
#define	FLASH_WRP3_WRP3   ((uint32_t)0x00FF0000)
#define	FLASH_WRP3_nWRP3   ((uint32_t)0xFF000000)
#define	ADC_SR_AWD   ((uint8_t)0x01)
#define	ADC_SR_EOC   ((uint8_t)0x02)
#define	ADC_SR_JEOC   ((uint8_t)0x04)
#define	ADC_SR_JSTRT   ((uint8_t)0x08)
#define	ADC_SR_STRT   ((uint8_t)0x10)
#define	ADC_SR_OVR   ((uint8_t)0x20)
#define	ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
#define	ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
#define	ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
#define	ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
#define	ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
#define	ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
#define	ADC_CR1_EOCIE   ((uint32_t)0x00000020)
#define	ADC_CR1_AWDIE   ((uint32_t)0x00000040)
#define	ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
#define	ADC_CR1_SCAN   ((uint32_t)0x00000100)
#define	ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
#define	ADC_CR1_JAUTO   ((uint32_t)0x00000400)
#define	ADC_CR1_DISCEN   ((uint32_t)0x00000800)
#define	ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
#define	ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
#define	ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
#define	ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
#define	ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
#define	ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
#define	ADC_CR1_AWDEN   ((uint32_t)0x00800000)
#define	ADC_CR1_RES   ((uint32_t)0x03000000)
#define	ADC_CR1_RES_0   ((uint32_t)0x01000000)
#define	ADC_CR1_RES_1   ((uint32_t)0x02000000)
#define	ADC_CR1_OVRIE   ((uint32_t)0x04000000)
#define	ADC_CR2_ADON   ((uint32_t)0x00000001)
#define	ADC_CR2_CONT   ((uint32_t)0x00000002)
#define	ADC_CR2_DMA   ((uint32_t)0x00000100)
#define	ADC_CR2_DDS   ((uint32_t)0x00000200)
#define	ADC_CR2_EOCS   ((uint32_t)0x00000400)
#define	ADC_CR2_ALIGN   ((uint32_t)0x00000800)
#define	ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
#define	ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
#define	ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
#define	ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
#define	ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
#define	ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
#define	ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
#define	ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
#define	ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
#define	ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
#define	ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
#define	ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
#define	ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
#define	ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
#define	ADC_CR2_EXTEN   ((uint32_t)0x30000000)
#define	ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
#define	ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
#define	ADC_CR2_SWSTART   ((uint32_t)0x40000000)
#define	ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
#define	ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
#define	ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
#define	ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
#define	ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
#define	ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
#define	ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
#define	ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
#define	ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
#define	ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
#define	ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
#define	ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
#define	ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
#define	ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
#define	ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
#define	ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
#define	ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
#define	ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
#define	ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
#define	ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
#define	ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
#define	ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
#define	ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
#define	ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
#define	ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
#define	ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
#define	ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
#define	ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
#define	ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
#define	ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
#define	ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
#define	ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
#define	ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
#define	ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
#define	ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
#define	ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
#define	ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
#define	ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
#define	ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
#define	ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
#define	ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
#define	ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
#define	ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
#define	ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
#define	ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
#define	ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
#define	ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
#define	ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
#define	ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
#define	ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
#define	ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
#define	ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
#define	ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
#define	ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
#define	ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
#define	ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
#define	ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
#define	ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
#define	ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
#define	ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
#define	ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
#define	ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
#define	ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
#define	ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
#define	ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
#define	ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
#define	ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
#define	ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
#define	ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
#define	ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
#define	ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
#define	ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
#define	ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
#define	ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
#define	ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
#define	ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
#define	ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
#define	ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
#define	ADC_HTR_HT   ((uint16_t)0x0FFF)
#define	ADC_LTR_LT   ((uint16_t)0x0FFF)
#define	ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
#define	ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
#define	ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
#define	ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
#define	ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
#define	ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
#define	ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
#define	ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
#define	ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
#define	ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
#define	ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
#define	ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
#define	ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
#define	ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
#define	ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
#define	ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
#define	ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
#define	ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
#define	ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
#define	ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
#define	ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
#define	ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
#define	ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
#define	ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
#define	ADC_SQR1_L   ((uint32_t)0x00F00000)
#define	ADC_SQR1_L_0   ((uint32_t)0x00100000)
#define	ADC_SQR1_L_1   ((uint32_t)0x00200000)
#define	ADC_SQR1_L_2   ((uint32_t)0x00400000)
#define	ADC_SQR1_L_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
#define	ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
#define	ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
#define	ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
#define	ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
#define	ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
#define	ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
#define	ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
#define	ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
#define	ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
#define	ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
#define	ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
#define	ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
#define	ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
#define	ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
#define	ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
#define	ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
#define	ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
#define	ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
#define	ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
#define	ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
#define	ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
#define	ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
#define	ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
#define	ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
#define	ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
#define	ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
#define	ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
#define	ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
#define	ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
#define	ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
#define	ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
#define	ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
#define	ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
#define	ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
#define	ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
#define	ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
#define	ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
#define	ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
#define	ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
#define	ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
#define	ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
#define	ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
#define	ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
#define	ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
#define	ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
#define	ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
#define	ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
#define	ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
#define	ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
#define	ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
#define	ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
#define	ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
#define	ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
#define	ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
#define	ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
#define	ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
#define	ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
#define	ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
#define	ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
#define	ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
#define	ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
#define	ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
#define	ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
#define	ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
#define	ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
#define	ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
#define	ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
#define	ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
#define	ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
#define	ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
#define	ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
#define	ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
#define	ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
#define	ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
#define	ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
#define	ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
#define	ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
#define	ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
#define	ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
#define	ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
#define	ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
#define	ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
#define	ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
#define	ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
#define	ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
#define	ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
#define	ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
#define	ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
#define	ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
#define	ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
#define	ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
#define	ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
#define	ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
#define	ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
#define	ADC_JSQR_JL   ((uint32_t)0x00300000)
#define	ADC_JSQR_JL_0   ((uint32_t)0x00100000)
#define	ADC_JSQR_JL_1   ((uint32_t)0x00200000)
#define	ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
#define	ADC_DR_DATA   ((uint32_t)0x0000FFFF)
#define	ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
#define	ADC_CSR_AWD1   ((uint32_t)0x00000001)
#define	ADC_CSR_EOC1   ((uint32_t)0x00000002)
#define	ADC_CSR_JEOC1   ((uint32_t)0x00000004)
#define	ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
#define	ADC_CSR_STRT1   ((uint32_t)0x00000010)
#define	ADC_CSR_DOVR1   ((uint32_t)0x00000020)
#define	ADC_CSR_AWD2   ((uint32_t)0x00000100)
#define	ADC_CSR_EOC2   ((uint32_t)0x00000200)
#define	ADC_CSR_JEOC2   ((uint32_t)0x00000400)
#define	ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
#define	ADC_CSR_STRT2   ((uint32_t)0x00001000)
#define	ADC_CSR_DOVR2   ((uint32_t)0x00002000)
#define	ADC_CSR_AWD3   ((uint32_t)0x00010000)
#define	ADC_CSR_EOC3   ((uint32_t)0x00020000)
#define	ADC_CSR_JEOC3   ((uint32_t)0x00040000)
#define	ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
#define	ADC_CSR_STRT3   ((uint32_t)0x00100000)
#define	ADC_CSR_DOVR3   ((uint32_t)0x00200000)
#define	ADC_CCR_MULTI   ((uint32_t)0x0000001F)
#define	ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
#define	ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
#define	ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
#define	ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
#define	ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
#define	ADC_CCR_DELAY   ((uint32_t)0x00000F00)
#define	ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
#define	ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
#define	ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
#define	ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
#define	ADC_CCR_DDS   ((uint32_t)0x00002000)
#define	ADC_CCR_DMA   ((uint32_t)0x0000C000)
#define	ADC_CCR_DMA_0   ((uint32_t)0x00004000)
#define	ADC_CCR_DMA_1   ((uint32_t)0x00008000)
#define	ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
#define	ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
#define	ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
#define	ADC_CCR_VBATE   ((uint32_t)0x00400000)
#define	ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
#define	ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
#define	ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
#define	CAN_MCR_INRQ   ((uint16_t)0x0001)
#define	CAN_MCR_SLEEP   ((uint16_t)0x0002)
#define	CAN_MCR_TXFP   ((uint16_t)0x0004)
#define	CAN_MCR_RFLM   ((uint16_t)0x0008)
#define	CAN_MCR_NART   ((uint16_t)0x0010)
#define	CAN_MCR_AWUM   ((uint16_t)0x0020)
#define	CAN_MCR_ABOM   ((uint16_t)0x0040)
#define	CAN_MCR_TTCM   ((uint16_t)0x0080)
#define	CAN_MCR_RESET   ((uint16_t)0x8000)
#define	CAN_MSR_INAK   ((uint16_t)0x0001)
#define	CAN_MSR_SLAK   ((uint16_t)0x0002)
#define	CAN_MSR_ERRI   ((uint16_t)0x0004)
#define	CAN_MSR_WKUI   ((uint16_t)0x0008)
#define	CAN_MSR_SLAKI   ((uint16_t)0x0010)
#define	CAN_MSR_TXM   ((uint16_t)0x0100)
#define	CAN_MSR_RXM   ((uint16_t)0x0200)
#define	CAN_MSR_SAMP   ((uint16_t)0x0400)
#define	CAN_MSR_RX   ((uint16_t)0x0800)
#define	CAN_TSR_RQCP0   ((uint32_t)0x00000001)
#define	CAN_TSR_TXOK0   ((uint32_t)0x00000002)
#define	CAN_TSR_ALST0   ((uint32_t)0x00000004)
#define	CAN_TSR_TERR0   ((uint32_t)0x00000008)
#define	CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
#define	CAN_TSR_RQCP1   ((uint32_t)0x00000100)
#define	CAN_TSR_TXOK1   ((uint32_t)0x00000200)
#define	CAN_TSR_ALST1   ((uint32_t)0x00000400)
#define	CAN_TSR_TERR1   ((uint32_t)0x00000800)
#define	CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
#define	CAN_TSR_RQCP2   ((uint32_t)0x00010000)
#define	CAN_TSR_TXOK2   ((uint32_t)0x00020000)
#define	CAN_TSR_ALST2   ((uint32_t)0x00040000)
#define	CAN_TSR_TERR2   ((uint32_t)0x00080000)
#define	CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
#define	CAN_TSR_CODE   ((uint32_t)0x03000000)
#define	CAN_TSR_TME   ((uint32_t)0x1C000000)
#define	CAN_TSR_TME0   ((uint32_t)0x04000000)
#define	CAN_TSR_TME1   ((uint32_t)0x08000000)
#define	CAN_TSR_TME2   ((uint32_t)0x10000000)
#define	CAN_TSR_LOW   ((uint32_t)0xE0000000)
#define	CAN_TSR_LOW0   ((uint32_t)0x20000000)
#define	CAN_TSR_LOW1   ((uint32_t)0x40000000)
#define	CAN_TSR_LOW2   ((uint32_t)0x80000000)
#define	CAN_RF0R_FMP0   ((uint8_t)0x03)
#define	CAN_RF0R_FULL0   ((uint8_t)0x08)
#define	CAN_RF0R_FOVR0   ((uint8_t)0x10)
#define	CAN_RF0R_RFOM0   ((uint8_t)0x20)
#define	CAN_RF1R_FMP1   ((uint8_t)0x03)
#define	CAN_RF1R_FULL1   ((uint8_t)0x08)
#define	CAN_RF1R_FOVR1   ((uint8_t)0x10)
#define	CAN_RF1R_RFOM1   ((uint8_t)0x20)
#define	CAN_IER_TMEIE   ((uint32_t)0x00000001)
#define	CAN_IER_FMPIE0   ((uint32_t)0x00000002)
#define	CAN_IER_FFIE0   ((uint32_t)0x00000004)
#define	CAN_IER_FOVIE0   ((uint32_t)0x00000008)
#define	CAN_IER_FMPIE1   ((uint32_t)0x00000010)
#define	CAN_IER_FFIE1   ((uint32_t)0x00000020)
#define	CAN_IER_FOVIE1   ((uint32_t)0x00000040)
#define	CAN_IER_EWGIE   ((uint32_t)0x00000100)
#define	CAN_IER_EPVIE   ((uint32_t)0x00000200)
#define	CAN_IER_BOFIE   ((uint32_t)0x00000400)
#define	CAN_IER_LECIE   ((uint32_t)0x00000800)
#define	CAN_IER_ERRIE   ((uint32_t)0x00008000)
#define	CAN_IER_WKUIE   ((uint32_t)0x00010000)
#define	CAN_IER_SLKIE   ((uint32_t)0x00020000)
#define	CAN_ESR_EWGF   ((uint32_t)0x00000001)
#define	CAN_ESR_EPVF   ((uint32_t)0x00000002)
#define	CAN_ESR_BOFF   ((uint32_t)0x00000004)
#define	CAN_ESR_LEC   ((uint32_t)0x00000070)
#define	CAN_ESR_LEC_0   ((uint32_t)0x00000010)
#define	CAN_ESR_LEC_1   ((uint32_t)0x00000020)
#define	CAN_ESR_LEC_2   ((uint32_t)0x00000040)
#define	CAN_ESR_TEC   ((uint32_t)0x00FF0000)
#define	CAN_ESR_REC   ((uint32_t)0xFF000000)
#define	CAN_BTR_BRP   ((uint32_t)0x000003FF)
#define	CAN_BTR_TS1   ((uint32_t)0x000F0000)
#define	CAN_BTR_TS2   ((uint32_t)0x00700000)
#define	CAN_BTR_SJW   ((uint32_t)0x03000000)
#define	CAN_BTR_LBKM   ((uint32_t)0x40000000)
#define	CAN_BTR_SILM   ((uint32_t)0x80000000)
#define	CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT0R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT1R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI2R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI2R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI2R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT2R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_FMR_FINIT   ((uint8_t)0x01)
#define	CAN_FM1R_FBM   ((uint16_t)0x3FFF)
#define	CAN_FM1R_FBM0   ((uint16_t)0x0001)
#define	CAN_FM1R_FBM1   ((uint16_t)0x0002)
#define	CAN_FM1R_FBM2   ((uint16_t)0x0004)
#define	CAN_FM1R_FBM3   ((uint16_t)0x0008)
#define	CAN_FM1R_FBM4   ((uint16_t)0x0010)
#define	CAN_FM1R_FBM5   ((uint16_t)0x0020)
#define	CAN_FM1R_FBM6   ((uint16_t)0x0040)
#define	CAN_FM1R_FBM7   ((uint16_t)0x0080)
#define	CAN_FM1R_FBM8   ((uint16_t)0x0100)
#define	CAN_FM1R_FBM9   ((uint16_t)0x0200)
#define	CAN_FM1R_FBM10   ((uint16_t)0x0400)
#define	CAN_FM1R_FBM11   ((uint16_t)0x0800)
#define	CAN_FM1R_FBM12   ((uint16_t)0x1000)
#define	CAN_FM1R_FBM13   ((uint16_t)0x2000)
#define	CAN_FS1R_FSC   ((uint16_t)0x3FFF)
#define	CAN_FS1R_FSC0   ((uint16_t)0x0001)
#define	CAN_FS1R_FSC1   ((uint16_t)0x0002)
#define	CAN_FS1R_FSC2   ((uint16_t)0x0004)
#define	CAN_FS1R_FSC3   ((uint16_t)0x0008)
#define	CAN_FS1R_FSC4   ((uint16_t)0x0010)
#define	CAN_FS1R_FSC5   ((uint16_t)0x0020)
#define	CAN_FS1R_FSC6   ((uint16_t)0x0040)
#define	CAN_FS1R_FSC7   ((uint16_t)0x0080)
#define	CAN_FS1R_FSC8   ((uint16_t)0x0100)
#define	CAN_FS1R_FSC9   ((uint16_t)0x0200)
#define	CAN_FS1R_FSC10   ((uint16_t)0x0400)
#define	CAN_FS1R_FSC11   ((uint16_t)0x0800)
#define	CAN_FS1R_FSC12   ((uint16_t)0x1000)
#define	CAN_FS1R_FSC13   ((uint16_t)0x2000)
#define	CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
#define	CAN_FFA1R_FFA0   ((uint16_t)0x0001)
#define	CAN_FFA1R_FFA1   ((uint16_t)0x0002)
#define	CAN_FFA1R_FFA2   ((uint16_t)0x0004)
#define	CAN_FFA1R_FFA3   ((uint16_t)0x0008)
#define	CAN_FFA1R_FFA4   ((uint16_t)0x0010)
#define	CAN_FFA1R_FFA5   ((uint16_t)0x0020)
#define	CAN_FFA1R_FFA6   ((uint16_t)0x0040)
#define	CAN_FFA1R_FFA7   ((uint16_t)0x0080)
#define	CAN_FFA1R_FFA8   ((uint16_t)0x0100)
#define	CAN_FFA1R_FFA9   ((uint16_t)0x0200)
#define	CAN_FFA1R_FFA10   ((uint16_t)0x0400)
#define	CAN_FFA1R_FFA11   ((uint16_t)0x0800)
#define	CAN_FFA1R_FFA12   ((uint16_t)0x1000)
#define	CAN_FFA1R_FFA13   ((uint16_t)0x2000)
#define	CAN_FA1R_FACT   ((uint16_t)0x3FFF)
#define	CAN_FA1R_FACT0   ((uint16_t)0x0001)
#define	CAN_FA1R_FACT1   ((uint16_t)0x0002)
#define	CAN_FA1R_FACT2   ((uint16_t)0x0004)
#define	CAN_FA1R_FACT3   ((uint16_t)0x0008)
#define	CAN_FA1R_FACT4   ((uint16_t)0x0010)
#define	CAN_FA1R_FACT5   ((uint16_t)0x0020)
#define	CAN_FA1R_FACT6   ((uint16_t)0x0040)
#define	CAN_FA1R_FACT7   ((uint16_t)0x0080)
#define	CAN_FA1R_FACT8   ((uint16_t)0x0100)
#define	CAN_FA1R_FACT9   ((uint16_t)0x0200)
#define	CAN_FA1R_FACT10   ((uint16_t)0x0400)
#define	CAN_FA1R_FACT11   ((uint16_t)0x0800)
#define	CAN_FA1R_FACT12   ((uint16_t)0x1000)
#define	CAN_FA1R_FACT13   ((uint16_t)0x2000)
#define	CAN_F0R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F0R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R2_FB31   ((uint32_t)0x80000000)
#define	CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
#define	CRC_IDR_IDR   ((uint8_t)0xFF)
#define	CRC_CR_RESET   ((uint8_t)0x01)
#define	CRYP_CR_ALGODIR   ((uint32_t)0x00000004)
#define	CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)
#define	CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)
#define	CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)
#define	CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)
#define	CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)
#define	CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)
#define	CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)
#define	CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)
#define	CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)
#define	CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)
#define	CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)
#define	CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)
#define	CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)
#define	CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)
#define	CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)
#define	CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)
#define	CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)
#define	CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)
#define	CRYP_CR_FFLUSH   ((uint32_t)0x00004000)
#define	CRYP_CR_CRYPEN   ((uint32_t)0x00008000)
#define	CRYP_SR_IFEM   ((uint32_t)0x00000001)
#define	CRYP_SR_IFNF   ((uint32_t)0x00000002)
#define	CRYP_SR_OFNE   ((uint32_t)0x00000004)
#define	CRYP_SR_OFFU   ((uint32_t)0x00000008)
#define	CRYP_SR_BUSY   ((uint32_t)0x00000010)
#define	CRYP_DMACR_DIEN   ((uint32_t)0x00000001)
#define	CRYP_DMACR_DOEN   ((uint32_t)0x00000002)
#define	CRYP_IMSCR_INIM   ((uint32_t)0x00000001)
#define	CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)
#define	CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)
#define	CRYP_RISR_INRIS   ((uint32_t)0x00000002)
#define	CRYP_MISR_INMIS   ((uint32_t)0x00000001)
#define	CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)
#define	DAC_CR_EN1   ((uint32_t)0x00000001)
#define	DAC_CR_BOFF1   ((uint32_t)0x00000002)
#define	DAC_CR_TEN1   ((uint32_t)0x00000004)
#define	DAC_CR_TSEL1   ((uint32_t)0x00000038)
#define	DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
#define	DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
#define	DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
#define	DAC_CR_WAVE1   ((uint32_t)0x000000C0)
#define	DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
#define	DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
#define	DAC_CR_MAMP1   ((uint32_t)0x00000F00)
#define	DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
#define	DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
#define	DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
#define	DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
#define	DAC_CR_DMAEN1   ((uint32_t)0x00001000)
#define	DAC_CR_EN2   ((uint32_t)0x00010000)
#define	DAC_CR_BOFF2   ((uint32_t)0x00020000)
#define	DAC_CR_TEN2   ((uint32_t)0x00040000)
#define	DAC_CR_TSEL2   ((uint32_t)0x00380000)
#define	DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
#define	DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
#define	DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
#define	DAC_CR_WAVE2   ((uint32_t)0x00C00000)
#define	DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
#define	DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
#define	DAC_CR_MAMP2   ((uint32_t)0x0F000000)
#define	DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
#define	DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
#define	DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
#define	DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
#define	DAC_CR_DMAEN2   ((uint32_t)0x10000000)
#define	DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
#define	DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
#define	DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
#define	DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
#define	DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
#define	DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
#define	DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
#define	DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
#define	DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
#define	DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
#define	DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
#define	DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
#define	DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
#define	DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
#define	DCMI_CR_CAPTURE   ((uint32_t)0x00000001)
#define	DCMI_CR_CM   ((uint32_t)0x00000002)
#define	DCMI_CR_CROP   ((uint32_t)0x00000004)
#define	DCMI_CR_JPEG   ((uint32_t)0x00000008)
#define	DCMI_CR_ESS   ((uint32_t)0x00000010)
#define	DCMI_CR_PCKPOL   ((uint32_t)0x00000020)
#define	DCMI_CR_HSPOL   ((uint32_t)0x00000040)
#define	DCMI_CR_VSPOL   ((uint32_t)0x00000080)
#define	DCMI_CR_FCRC_0   ((uint32_t)0x00000100)
#define	DCMI_CR_FCRC_1   ((uint32_t)0x00000200)
#define	DCMI_CR_EDM_0   ((uint32_t)0x00000400)
#define	DCMI_CR_EDM_1   ((uint32_t)0x00000800)
#define	DCMI_CR_CRE   ((uint32_t)0x00001000)
#define	DCMI_CR_ENABLE   ((uint32_t)0x00004000)
#define	DCMI_SR_HSYNC   ((uint32_t)0x00000001)
#define	DCMI_SR_VSYNC   ((uint32_t)0x00000002)
#define	DCMI_SR_FNE   ((uint32_t)0x00000004)
#define	DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)
#define	DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)
#define	DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)
#define	DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)
#define	DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)
#define	DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)
#define	DCMI_IER_OVF_IE   ((uint32_t)0x00000002)
#define	DCMI_IER_ERR_IE   ((uint32_t)0x00000004)
#define	DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)
#define	DCMI_IER_LINE_IE   ((uint32_t)0x00000010)
#define	DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)
#define	DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)
#define	DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)
#define	DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)
#define	DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)
#define	DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)
#define	DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)
#define	DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)
#define	DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)
#define	DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)
#define	DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)
#define	DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)
#define	DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)
#define	DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)
#define	DMA_SxCR_MBURST   ((uint32_t)0x01800000)
#define	DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)
#define	DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)
#define	DMA_SxCR_PBURST   ((uint32_t)0x00600000)
#define	DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)
#define	DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)
#define	DMA_SxCR_ACK   ((uint32_t)0x00100000)
#define	DMA_SxCR_CT   ((uint32_t)0x00080000)
#define	DMA_SxCR_DBM   ((uint32_t)0x00040000)
#define	DMA_SxCR_PL   ((uint32_t)0x00030000)
#define	DMA_SxCR_PL_0   ((uint32_t)0x00010000)
#define	DMA_SxCR_PL_1   ((uint32_t)0x00020000)
#define	DMA_SxCR_PINCOS   ((uint32_t)0x00008000)
#define	DMA_SxCR_MSIZE   ((uint32_t)0x00006000)
#define	DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)
#define	DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)
#define	DMA_SxCR_PSIZE   ((uint32_t)0x00001800)
#define	DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)
#define	DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)
#define	DMA_SxCR_MINC   ((uint32_t)0x00000400)
#define	DMA_SxCR_PINC   ((uint32_t)0x00000200)
#define	DMA_SxCR_CIRC   ((uint32_t)0x00000100)
#define	DMA_SxCR_DIR   ((uint32_t)0x000000C0)
#define	DMA_SxCR_DIR_0   ((uint32_t)0x00000040)
#define	DMA_SxCR_DIR_1   ((uint32_t)0x00000080)
#define	DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)
#define	DMA_SxCR_TCIE   ((uint32_t)0x00000010)
#define	DMA_SxCR_HTIE   ((uint32_t)0x00000008)
#define	DMA_SxCR_TEIE   ((uint32_t)0x00000004)
#define	DMA_SxCR_DMEIE   ((uint32_t)0x00000002)
#define	DMA_SxCR_EN   ((uint32_t)0x00000001)
#define	DMA_SxNDT   ((uint32_t)0x0000FFFF)
#define	DMA_SxNDT_0   ((uint32_t)0x00000001)
#define	DMA_SxNDT_1   ((uint32_t)0x00000002)
#define	DMA_SxNDT_2   ((uint32_t)0x00000004)
#define	DMA_SxNDT_3   ((uint32_t)0x00000008)
#define	DMA_SxNDT_4   ((uint32_t)0x00000010)
#define	DMA_SxNDT_5   ((uint32_t)0x00000020)
#define	DMA_SxNDT_6   ((uint32_t)0x00000040)
#define	DMA_SxNDT_7   ((uint32_t)0x00000080)
#define	DMA_SxNDT_8   ((uint32_t)0x00000100)
#define	DMA_SxNDT_9   ((uint32_t)0x00000200)
#define	DMA_SxNDT_10   ((uint32_t)0x00000400)
#define	DMA_SxNDT_11   ((uint32_t)0x00000800)
#define	DMA_SxNDT_12   ((uint32_t)0x00001000)
#define	DMA_SxNDT_13   ((uint32_t)0x00002000)
#define	DMA_SxNDT_14   ((uint32_t)0x00004000)
#define	DMA_SxNDT_15   ((uint32_t)0x00008000)
#define	DMA_SxFCR_FEIE   ((uint32_t)0x00000080)
#define	DMA_SxFCR_FS   ((uint32_t)0x00000038)
#define	DMA_SxFCR_FS_0   ((uint32_t)0x00000008)
#define	DMA_SxFCR_FS_1   ((uint32_t)0x00000010)
#define	DMA_SxFCR_FS_2   ((uint32_t)0x00000020)
#define	DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)
#define	DMA_SxFCR_FTH   ((uint32_t)0x00000003)
#define	DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)
#define	DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)
#define	DMA_LISR_TCIF3   ((uint32_t)0x08000000)
#define	DMA_LISR_HTIF3   ((uint32_t)0x04000000)
#define	DMA_LISR_TEIF3   ((uint32_t)0x02000000)
#define	DMA_LISR_DMEIF3   ((uint32_t)0x01000000)
#define	DMA_LISR_FEIF3   ((uint32_t)0x00400000)
#define	DMA_LISR_TCIF2   ((uint32_t)0x00200000)
#define	DMA_LISR_HTIF2   ((uint32_t)0x00100000)
#define	DMA_LISR_TEIF2   ((uint32_t)0x00080000)
#define	DMA_LISR_DMEIF2   ((uint32_t)0x00040000)
#define	DMA_LISR_FEIF2   ((uint32_t)0x00010000)
#define	DMA_LISR_TCIF1   ((uint32_t)0x00000800)
#define	DMA_LISR_HTIF1   ((uint32_t)0x00000400)
#define	DMA_LISR_TEIF1   ((uint32_t)0x00000200)
#define	DMA_LISR_DMEIF1   ((uint32_t)0x00000100)
#define	DMA_LISR_FEIF1   ((uint32_t)0x00000040)
#define	DMA_LISR_TCIF0   ((uint32_t)0x00000020)
#define	DMA_LISR_HTIF0   ((uint32_t)0x00000010)
#define	DMA_LISR_TEIF0   ((uint32_t)0x00000008)
#define	DMA_LISR_DMEIF0   ((uint32_t)0x00000004)
#define	DMA_LISR_FEIF0   ((uint32_t)0x00000001)
#define	DMA_HISR_TCIF7   ((uint32_t)0x08000000)
#define	DMA_HISR_HTIF7   ((uint32_t)0x04000000)
#define	DMA_HISR_TEIF7   ((uint32_t)0x02000000)
#define	DMA_HISR_DMEIF7   ((uint32_t)0x01000000)
#define	DMA_HISR_FEIF7   ((uint32_t)0x00400000)
#define	DMA_HISR_TCIF6   ((uint32_t)0x00200000)
#define	DMA_HISR_HTIF6   ((uint32_t)0x00100000)
#define	DMA_HISR_TEIF6   ((uint32_t)0x00080000)
#define	DMA_HISR_DMEIF6   ((uint32_t)0x00040000)
#define	DMA_HISR_FEIF6   ((uint32_t)0x00010000)
#define	DMA_HISR_TCIF5   ((uint32_t)0x00000800)
#define	DMA_HISR_HTIF5   ((uint32_t)0x00000400)
#define	DMA_HISR_TEIF5   ((uint32_t)0x00000200)
#define	DMA_HISR_DMEIF5   ((uint32_t)0x00000100)
#define	DMA_HISR_FEIF5   ((uint32_t)0x00000040)
#define	DMA_HISR_TCIF4   ((uint32_t)0x00000020)
#define	DMA_HISR_HTIF4   ((uint32_t)0x00000010)
#define	DMA_HISR_TEIF4   ((uint32_t)0x00000008)
#define	DMA_HISR_DMEIF4   ((uint32_t)0x00000004)
#define	DMA_HISR_FEIF4   ((uint32_t)0x00000001)
#define	DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)
#define	DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)
#define	DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)
#define	DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)
#define	DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)
#define	DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)
#define	DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)
#define	DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)
#define	DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)
#define	DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)
#define	DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)
#define	DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)
#define	DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)
#define	DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)
#define	DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)
#define	DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)
#define	DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)
#define	DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)
#define	DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)
#define	DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)
#define	DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)
#define	DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)
#define	DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)
#define	DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)
#define	DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)
#define	DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)
#define	DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)
#define	DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)
#define	DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)
#define	DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)
#define	DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)
#define	DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)
#define	DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)
#define	DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)
#define	DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)
#define	DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)
#define	DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)
#define	DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)
#define	DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)
#define	DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_IMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_IMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_IMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_IMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_IMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_IMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_IMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_IMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_IMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_IMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_IMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_IMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_IMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_IMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_IMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_IMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_IMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_IMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_EMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_EMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_EMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_EMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_EMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_EMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_EMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_EMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_EMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_EMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_EMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_EMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_EMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_EMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_EMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_EMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_EMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_EMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_EMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_EMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_RTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_RTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_RTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_RTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_RTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_RTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_RTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_RTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_RTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_RTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_RTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_RTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_RTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_RTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_RTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_RTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_RTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_RTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_RTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_RTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_FTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_FTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_FTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_FTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_FTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_FTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_FTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_FTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_FTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_FTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_FTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_FTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_FTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_FTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_FTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_FTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_FTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_FTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_FTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_FTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
#define	EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
#define	EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
#define	EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
#define	EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
#define	EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
#define	EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
#define	EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
#define	EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
#define	EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
#define	EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
#define	EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
#define	EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
#define	EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
#define	EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
#define	EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
#define	EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
#define	EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
#define	EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
#define	EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
#define	EXTI_PR_PR0   ((uint32_t)0x00000001)
#define	EXTI_PR_PR1   ((uint32_t)0x00000002)
#define	EXTI_PR_PR2   ((uint32_t)0x00000004)
#define	EXTI_PR_PR3   ((uint32_t)0x00000008)
#define	EXTI_PR_PR4   ((uint32_t)0x00000010)
#define	EXTI_PR_PR5   ((uint32_t)0x00000020)
#define	EXTI_PR_PR6   ((uint32_t)0x00000040)
#define	EXTI_PR_PR7   ((uint32_t)0x00000080)
#define	EXTI_PR_PR8   ((uint32_t)0x00000100)
#define	EXTI_PR_PR9   ((uint32_t)0x00000200)
#define	EXTI_PR_PR10   ((uint32_t)0x00000400)
#define	EXTI_PR_PR11   ((uint32_t)0x00000800)
#define	EXTI_PR_PR12   ((uint32_t)0x00001000)
#define	EXTI_PR_PR13   ((uint32_t)0x00002000)
#define	EXTI_PR_PR14   ((uint32_t)0x00004000)
#define	EXTI_PR_PR15   ((uint32_t)0x00008000)
#define	EXTI_PR_PR16   ((uint32_t)0x00010000)
#define	EXTI_PR_PR17   ((uint32_t)0x00020000)
#define	EXTI_PR_PR18   ((uint32_t)0x00040000)
#define	EXTI_PR_PR19   ((uint32_t)0x00080000)
#define	FLASH_ACR_LATENCY   ((uint32_t)0x00000007)
#define	FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)
#define	FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)
#define	FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)
#define	FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)
#define	FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)
#define	FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)
#define	FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)
#define	FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)
#define	FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)
#define	FLASH_ACR_ICEN   ((uint32_t)0x00000200)
#define	FLASH_ACR_DCEN   ((uint32_t)0x00000400)
#define	FLASH_ACR_ICRST   ((uint32_t)0x00000800)
#define	FLASH_ACR_DCRST   ((uint32_t)0x00001000)
#define	FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
#define	FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)
#define	FLASH_SR_EOP   ((uint32_t)0x00000001)
#define	FLASH_SR_SOP   ((uint32_t)0x00000002)
#define	FLASH_SR_WRPERR   ((uint32_t)0x00000010)
#define	FLASH_SR_PGAERR   ((uint32_t)0x00000020)
#define	FLASH_SR_PGPERR   ((uint32_t)0x00000040)
#define	FLASH_SR_PGSERR   ((uint32_t)0x00000080)
#define	FLASH_SR_BSY   ((uint32_t)0x00010000)
#define	FLASH_CR_PG   ((uint32_t)0x00000001)
#define	FLASH_CR_SER   ((uint32_t)0x00000002)
#define	FLASH_CR_MER   ((uint32_t)0x00000004)
#define	FLASH_CR_SNB_0   ((uint32_t)0x00000008)
#define	FLASH_CR_SNB_1   ((uint32_t)0x00000010)
#define	FLASH_CR_SNB_2   ((uint32_t)0x00000020)
#define	FLASH_CR_SNB_3   ((uint32_t)0x00000040)
#define	FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)
#define	FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)
#define	FLASH_CR_STRT   ((uint32_t)0x00010000)
#define	FLASH_CR_EOPIE   ((uint32_t)0x01000000)
#define	FLASH_CR_LOCK   ((uint32_t)0x80000000)
#define	FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)
#define	FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)
#define	FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)
#define	FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)
#define	FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)
#define	FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)
#define	FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)
#define	FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)
#define	FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)
#define	FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)
#define	FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)
#define	FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)
#define	FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)
#define	FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)
#define	FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)
#define	FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)
#define	FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)
#define	FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)
#define	FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)
#define	FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)
#define	FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)
#define	FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)
#define	FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)
#define	FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)
#define	FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)
#define	FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)
#define	FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)
#define	FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)
#define	FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR1_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR1_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR2_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR2_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR3_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR3_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR4_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR4_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR2_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR3_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR4_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_SR2_IRS   ((uint8_t)0x01)
#define	FSMC_SR2_ILS   ((uint8_t)0x02)
#define	FSMC_SR2_IFS   ((uint8_t)0x04)
#define	FSMC_SR2_IREN   ((uint8_t)0x08)
#define	FSMC_SR2_ILEN   ((uint8_t)0x10)
#define	FSMC_SR2_IFEN   ((uint8_t)0x20)
#define	FSMC_SR2_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR3_IRS   ((uint8_t)0x01)
#define	FSMC_SR3_ILS   ((uint8_t)0x02)
#define	FSMC_SR3_IFS   ((uint8_t)0x04)
#define	FSMC_SR3_IREN   ((uint8_t)0x08)
#define	FSMC_SR3_ILEN   ((uint8_t)0x10)
#define	FSMC_SR3_IFEN   ((uint8_t)0x20)
#define	FSMC_SR3_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR4_IRS   ((uint8_t)0x01)
#define	FSMC_SR4_ILS   ((uint8_t)0x02)
#define	FSMC_SR4_IFS   ((uint8_t)0x04)
#define	FSMC_SR4_IREN   ((uint8_t)0x08)
#define	FSMC_SR4_ILEN   ((uint8_t)0x10)
#define	FSMC_SR4_IFEN   ((uint8_t)0x20)
#define	FSMC_SR4_FEMPT   ((uint8_t)0x40)
#define	FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
#define	FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
#define	FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
#define	FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
#define	FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
#define	FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
#define	FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
#define	FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
#define	FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
#define	GPIO_MODER_MODER0   ((uint32_t)0x00000003)
#define	GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
#define	GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
#define	GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
#define	GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
#define	GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
#define	GPIO_MODER_MODER2   ((uint32_t)0x00000030)
#define	GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
#define	GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
#define	GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
#define	GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
#define	GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
#define	GPIO_MODER_MODER4   ((uint32_t)0x00000300)
#define	GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
#define	GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
#define	GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
#define	GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
#define	GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
#define	GPIO_MODER_MODER6   ((uint32_t)0x00003000)
#define	GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
#define	GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
#define	GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
#define	GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
#define	GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
#define	GPIO_MODER_MODER8   ((uint32_t)0x00030000)
#define	GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
#define	GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
#define	GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
#define	GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
#define	GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
#define	GPIO_MODER_MODER10   ((uint32_t)0x00300000)
#define	GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
#define	GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
#define	GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
#define	GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
#define	GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
#define	GPIO_MODER_MODER12   ((uint32_t)0x03000000)
#define	GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
#define	GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
#define	GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
#define	GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
#define	GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
#define	GPIO_MODER_MODER14   ((uint32_t)0x30000000)
#define	GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
#define	GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
#define	GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
#define	GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
#define	GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
#define	GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
#define	GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
#define	GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
#define	GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
#define	GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
#define	GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
#define	GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
#define	GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
#define	GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
#define	GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
#define	GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
#define	GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
#define	GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
#define	GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
#define	GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
#define	GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
#define	GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
#define	GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
#define	GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
#define	GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
#define	GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
#define	GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
#define	GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
#define	GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
#define	GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
#define	GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
#define	GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
#define	GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
#define	GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
#define	GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
#define	GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
#define	GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
#define	GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
#define	GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
#define	GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
#define	GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
#define	GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
#define	GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
#define	GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
#define	GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
#define	GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
#define	GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
#define	GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
#define	GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
#define	GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
#define	GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
#define	GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
#define	GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
#define	GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
#define	GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
#define	GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
#define	GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
#define	GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
#define	GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
#define	GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
#define	GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
#define	GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
#define	GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
#define	GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
#define	GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
#define	GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
#define	GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
#define	GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
#define	GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
#define	GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
#define	GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
#define	GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
#define	GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
#define	GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
#define	GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
#define	GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
#define	GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
#define	GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
#define	GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
#define	GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
#define	GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
#define	GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
#define	GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
#define	GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
#define	GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
#define	GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
#define	GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
#define	GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
#define	GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
#define	GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
#define	GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
#define	GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
#define	GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
#define	GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
#define	GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
#define	GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
#define	GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
#define	GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
#define	GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
#define	GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
#define	GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
#define	GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
#define	GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
#define	GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
#define	GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
#define	GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
#define	GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
#define	GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
#define	GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
#define	GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
#define	GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
#define	GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
#define	GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
#define	GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
#define	GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
#define	GPIO_OTYPER_IDR_0   ((uint32_t)0x00000001)
#define	GPIO_OTYPER_IDR_1   ((uint32_t)0x00000002)
#define	GPIO_OTYPER_IDR_2   ((uint32_t)0x00000004)
#define	GPIO_OTYPER_IDR_3   ((uint32_t)0x00000008)
#define	GPIO_OTYPER_IDR_4   ((uint32_t)0x00000010)
#define	GPIO_OTYPER_IDR_5   ((uint32_t)0x00000020)
#define	GPIO_OTYPER_IDR_6   ((uint32_t)0x00000040)
#define	GPIO_OTYPER_IDR_7   ((uint32_t)0x00000080)
#define	GPIO_OTYPER_IDR_8   ((uint32_t)0x00000100)
#define	GPIO_OTYPER_IDR_9   ((uint32_t)0x00000200)
#define	GPIO_OTYPER_IDR_10   ((uint32_t)0x00000400)
#define	GPIO_OTYPER_IDR_11   ((uint32_t)0x00000800)
#define	GPIO_OTYPER_IDR_12   ((uint32_t)0x00001000)
#define	GPIO_OTYPER_IDR_13   ((uint32_t)0x00002000)
#define	GPIO_OTYPER_IDR_14   ((uint32_t)0x00004000)
#define	GPIO_OTYPER_IDR_15   ((uint32_t)0x00008000)
#define	GPIO_OTYPER_ODR_0   ((uint32_t)0x00000001)
#define	GPIO_OTYPER_ODR_1   ((uint32_t)0x00000002)
#define	GPIO_OTYPER_ODR_2   ((uint32_t)0x00000004)
#define	GPIO_OTYPER_ODR_3   ((uint32_t)0x00000008)
#define	GPIO_OTYPER_ODR_4   ((uint32_t)0x00000010)
#define	GPIO_OTYPER_ODR_5   ((uint32_t)0x00000020)
#define	GPIO_OTYPER_ODR_6   ((uint32_t)0x00000040)
#define	GPIO_OTYPER_ODR_7   ((uint32_t)0x00000080)
#define	GPIO_OTYPER_ODR_8   ((uint32_t)0x00000100)
#define	GPIO_OTYPER_ODR_9   ((uint32_t)0x00000200)
#define	GPIO_OTYPER_ODR_10   ((uint32_t)0x00000400)
#define	GPIO_OTYPER_ODR_11   ((uint32_t)0x00000800)
#define	GPIO_OTYPER_ODR_12   ((uint32_t)0x00001000)
#define	GPIO_OTYPER_ODR_13   ((uint32_t)0x00002000)
#define	GPIO_OTYPER_ODR_14   ((uint32_t)0x00004000)
#define	GPIO_OTYPER_ODR_15   ((uint32_t)0x00008000)
#define	GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
#define	GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
#define	GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
#define	GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
#define	GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
#define	GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
#define	GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
#define	GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
#define	GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
#define	GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
#define	GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
#define	GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
#define	GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
#define	GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
#define	GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
#define	GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
#define	GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
#define	GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
#define	GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
#define	GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
#define	GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
#define	GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
#define	GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
#define	GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
#define	GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
#define	GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
#define	GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
#define	GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
#define	GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
#define	GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
#define	GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
#define	GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
#define	HASH_CR_INIT   ((uint32_t)0x00000004)
#define	HASH_CR_DMAE   ((uint32_t)0x00000008)
#define	HASH_CR_DATATYPE   ((uint32_t)0x00000030)
#define	HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)
#define	HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)
#define	HASH_CR_MODE   ((uint32_t)0x00000040)
#define	HASH_CR_ALGO   ((uint32_t)0x00000080)
#define	HASH_CR_NBW   ((uint32_t)0x00000F00)
#define	HASH_CR_NBW_0   ((uint32_t)0x00000100)
#define	HASH_CR_NBW_1   ((uint32_t)0x00000200)
#define	HASH_CR_NBW_2   ((uint32_t)0x00000400)
#define	HASH_CR_NBW_3   ((uint32_t)0x00000800)
#define	HASH_CR_DINNE   ((uint32_t)0x00001000)
#define	HASH_CR_LKEY   ((uint32_t)0x00010000)
#define	HASH_STR_NBW   ((uint32_t)0x0000001F)
#define	HASH_STR_NBW_0   ((uint32_t)0x00000001)
#define	HASH_STR_NBW_1   ((uint32_t)0x00000002)
#define	HASH_STR_NBW_2   ((uint32_t)0x00000004)
#define	HASH_STR_NBW_3   ((uint32_t)0x00000008)
#define	HASH_STR_NBW_4   ((uint32_t)0x00000010)
#define	HASH_STR_DCAL   ((uint32_t)0x00000100)
#define	HASH_IMR_DINIM   ((uint32_t)0x00000001)
#define	HASH_IMR_DCIM   ((uint32_t)0x00000002)
#define	HASH_SR_DINIS   ((uint32_t)0x00000001)
#define	HASH_SR_DCIS   ((uint32_t)0x00000002)
#define	HASH_SR_DMAS   ((uint32_t)0x00000004)
#define	HASH_SR_BUSY   ((uint32_t)0x00000008)
#define	I2C_CR1_PE   ((uint16_t)0x0001)
#define	I2C_CR1_SMBUS   ((uint16_t)0x0002)
#define	I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
#define	I2C_CR1_ENARP   ((uint16_t)0x0010)
#define	I2C_CR1_ENPEC   ((uint16_t)0x0020)
#define	I2C_CR1_ENGC   ((uint16_t)0x0040)
#define	I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
#define	I2C_CR1_START   ((uint16_t)0x0100)
#define	I2C_CR1_STOP   ((uint16_t)0x0200)
#define	I2C_CR1_ACK   ((uint16_t)0x0400)
#define	I2C_CR1_POS   ((uint16_t)0x0800)
#define	I2C_CR1_PEC   ((uint16_t)0x1000)
#define	I2C_CR1_ALERT   ((uint16_t)0x2000)
#define	I2C_CR1_SWRST   ((uint16_t)0x8000)
#define	I2C_CR2_FREQ   ((uint16_t)0x003F)
#define	I2C_CR2_FREQ_0   ((uint16_t)0x0001)
#define	I2C_CR2_FREQ_1   ((uint16_t)0x0002)
#define	I2C_CR2_FREQ_2   ((uint16_t)0x0004)
#define	I2C_CR2_FREQ_3   ((uint16_t)0x0008)
#define	I2C_CR2_FREQ_4   ((uint16_t)0x0010)
#define	I2C_CR2_FREQ_5   ((uint16_t)0x0020)
#define	I2C_CR2_ITERREN   ((uint16_t)0x0100)
#define	I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
#define	I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
#define	I2C_CR2_DMAEN   ((uint16_t)0x0800)
#define	I2C_CR2_LAST   ((uint16_t)0x1000)
#define	I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
#define	I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
#define	I2C_OAR1_ADD0   ((uint16_t)0x0001)
#define	I2C_OAR1_ADD1   ((uint16_t)0x0002)
#define	I2C_OAR1_ADD2   ((uint16_t)0x0004)
#define	I2C_OAR1_ADD3   ((uint16_t)0x0008)
#define	I2C_OAR1_ADD4   ((uint16_t)0x0010)
#define	I2C_OAR1_ADD5   ((uint16_t)0x0020)
#define	I2C_OAR1_ADD6   ((uint16_t)0x0040)
#define	I2C_OAR1_ADD7   ((uint16_t)0x0080)
#define	I2C_OAR1_ADD8   ((uint16_t)0x0100)
#define	I2C_OAR1_ADD9   ((uint16_t)0x0200)
#define	I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
#define	I2C_OAR2_ENDUAL   ((uint8_t)0x01)
#define	I2C_OAR2_ADD2   ((uint8_t)0xFE)
#define	I2C_DR_DR   ((uint8_t)0xFF)
#define	I2C_SR1_SB   ((uint16_t)0x0001)
#define	I2C_SR1_ADDR   ((uint16_t)0x0002)
#define	I2C_SR1_BTF   ((uint16_t)0x0004)
#define	I2C_SR1_ADD10   ((uint16_t)0x0008)
#define	I2C_SR1_STOPF   ((uint16_t)0x0010)
#define	I2C_SR1_RXNE   ((uint16_t)0x0040)
#define	I2C_SR1_TXE   ((uint16_t)0x0080)
#define	I2C_SR1_BERR   ((uint16_t)0x0100)
#define	I2C_SR1_ARLO   ((uint16_t)0x0200)
#define	I2C_SR1_AF   ((uint16_t)0x0400)
#define	I2C_SR1_OVR   ((uint16_t)0x0800)
#define	I2C_SR1_PECERR   ((uint16_t)0x1000)
#define	I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
#define	I2C_SR1_SMBALERT   ((uint16_t)0x8000)
#define	I2C_SR2_MSL   ((uint16_t)0x0001)
#define	I2C_SR2_BUSY   ((uint16_t)0x0002)
#define	I2C_SR2_TRA   ((uint16_t)0x0004)
#define	I2C_SR2_GENCALL   ((uint16_t)0x0010)
#define	I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
#define	I2C_SR2_SMBHOST   ((uint16_t)0x0040)
#define	I2C_SR2_DUALF   ((uint16_t)0x0080)
#define	I2C_SR2_PEC   ((uint16_t)0xFF00)
#define	I2C_CCR_CCR   ((uint16_t)0x0FFF)
#define	I2C_CCR_DUTY   ((uint16_t)0x4000)
#define	I2C_CCR_FS   ((uint16_t)0x8000)
#define	I2C_TRISE_TRISE   ((uint8_t)0x3F)
#define	IWDG_KR_KEY   ((uint16_t)0xFFFF)
#define	IWDG_PR_PR   ((uint8_t)0x07)
#define	IWDG_PR_PR_0   ((uint8_t)0x01)
#define	IWDG_PR_PR_1   ((uint8_t)0x02)
#define	IWDG_PR_PR_2   ((uint8_t)0x04)
#define	IWDG_RLR_RL   ((uint16_t)0x0FFF)
#define	IWDG_SR_PVU   ((uint8_t)0x01)
#define	IWDG_SR_RVU   ((uint8_t)0x02)
#define	PWR_CR_LPDS   ((uint16_t)0x0001)
#define	PWR_CR_PDDS   ((uint16_t)0x0002)
#define	PWR_CR_CWUF   ((uint16_t)0x0004)
#define	PWR_CR_CSBF   ((uint16_t)0x0008)
#define	PWR_CR_PVDE   ((uint16_t)0x0010)
#define	PWR_CR_PLS   ((uint16_t)0x00E0)
#define	PWR_CR_PLS_0   ((uint16_t)0x0020)
#define	PWR_CR_PLS_1   ((uint16_t)0x0040)
#define	PWR_CR_PLS_2   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV0   ((uint16_t)0x0000)
#define	PWR_CR_PLS_LEV1   ((uint16_t)0x0020)
#define	PWR_CR_PLS_LEV2   ((uint16_t)0x0040)
#define	PWR_CR_PLS_LEV3   ((uint16_t)0x0060)
#define	PWR_CR_PLS_LEV4   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)
#define	PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)
#define	PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)
#define	PWR_CR_DBP   ((uint16_t)0x0100)
#define	PWR_CR_FPDS   ((uint16_t)0x0200)
#define	PWR_CSR_WUF   ((uint16_t)0x0001)
#define	PWR_CSR_SBF   ((uint16_t)0x0002)
#define	PWR_CSR_PVDO   ((uint16_t)0x0004)
#define	PWR_CSR_BRR   ((uint16_t)0x0008)
#define	PWR_CSR_EWUP   ((uint16_t)0x0100)
#define	PWR_CSR_BRE   ((uint16_t)0x0200)
#define	RCC_CR_HSION   ((uint32_t)0x00000001)
#define	RCC_CR_HSIRDY   ((uint32_t)0x00000002)
#define	RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
#define	RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)
#define	RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)
#define	RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)
#define	RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)
#define	RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)
#define	RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
#define	RCC_CR_HSICAL_0   ((uint32_t)0x00000100)
#define	RCC_CR_HSICAL_1   ((uint32_t)0x00000200)
#define	RCC_CR_HSICAL_2   ((uint32_t)0x00000400)
#define	RCC_CR_HSICAL_3   ((uint32_t)0x00000800)
#define	RCC_CR_HSICAL_4   ((uint32_t)0x00001000)
#define	RCC_CR_HSICAL_5   ((uint32_t)0x00002000)
#define	RCC_CR_HSICAL_6   ((uint32_t)0x00004000)
#define	RCC_CR_HSICAL_7   ((uint32_t)0x00008000)
#define	RCC_CR_HSEON   ((uint32_t)0x00010000)
#define	RCC_CR_HSERDY   ((uint32_t)0x00020000)
#define	RCC_CR_HSEBYP   ((uint32_t)0x00040000)
#define	RCC_CR_CSSON   ((uint32_t)0x00080000)
#define	RCC_CR_PLLON   ((uint32_t)0x01000000)
#define	RCC_CR_PLLRDY   ((uint32_t)0x02000000)
#define	RCC_CR_PLLI2SON   ((uint32_t)0x04000000)
#define	RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)
#define	RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)
#define	RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)
#define	RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)
#define	RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)
#define	RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)
#define	RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)
#define	RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)
#define	RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)
#define	RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)
#define	RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)
#define	RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)
#define	RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)
#define	RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)
#define	RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)
#define	RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)
#define	RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)
#define	RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)
#define	RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)
#define	RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)
#define	RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)
#define	RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)
#define	RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)
#define	RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
#define	RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)
#define	RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)
#define	RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)
#define	RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)
#define	RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)
#define	RCC_CFGR_SW   ((uint32_t)0x00000003)
#define	RCC_CFGR_SW_0   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_1   ((uint32_t)0x00000002)
#define	RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
#define	RCC_CFGR_SWS   ((uint32_t)0x0000000C)
#define	RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
#define	RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
#define	RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
#define	RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
#define	RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
#define	RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
#define	RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
#define	RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
#define	RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
#define	RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
#define	RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
#define	RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
#define	RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
#define	RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
#define	RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
#define	RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
#define	RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
#define	RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
#define	RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
#define	RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
#define	RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
#define	RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
#define	RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
#define	RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
#define	RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E00)
#define	RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)
#define	RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)
#define	RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)
#define	RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)
#define	RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)
#define	RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
#define	RCC_CFGR_MCO1   ((uint32_t)0x00600000)
#define	RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)
#define	RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)
#define	RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)
#define	RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)
#define	RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)
#define	RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)
#define	RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)
#define	RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)
#define	RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)
#define	RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)
#define	RCC_CFGR_MCO2   ((uint32_t)0xC0000000)
#define	RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)
#define	RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)
#define	RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
#define	RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
#define	RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
#define	RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
#define	RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
#define	RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)
#define	RCC_CIR_CSSF   ((uint32_t)0x00000080)
#define	RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
#define	RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
#define	RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
#define	RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
#define	RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
#define	RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)
#define	RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
#define	RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
#define	RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
#define	RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
#define	RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
#define	RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)
#define	RCC_CIR_CSSC   ((uint32_t)0x00800000)
#define	RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)
#define	RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)
#define	RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)
#define	RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)
#define	RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)
#define	RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)
#define	RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)
#define	RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)
#define	RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)
#define	RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)
#define	RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)
#define	RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)
#define	RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)
#define	RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)
#define	RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)
#define	RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)
#define	RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)
#define	RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)
#define	RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)
#define	RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
#define	RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
#define	RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
#define	RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
#define	RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
#define	RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)
#define	RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)
#define	RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)
#define	RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)
#define	RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)
#define	RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
#define	RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
#define	RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
#define	RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
#define	RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
#define	RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
#define	RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)
#define	RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
#define	RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)
#define	RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
#define	RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
#define	RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)
#define	RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)
#define	RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)
#define	RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)
#define	RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)
#define	RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
#define	RCC_APB2RSTR_SPI1   ((uint32_t)0x00001000)
#define	RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)
#define	RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)
#define	RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)
#define	RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)
#define	RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)
#define	RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)
#define	RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)
#define	RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)
#define	RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)
#define	RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)
#define	RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)
#define	RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)
#define	RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)
#define	RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)
#define	RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)
#define	RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)
#define	RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)
#define	RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)
#define	RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)
#define	RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)
#define	RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)
#define	RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)
#define	RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)
#define	RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)
#define	RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)
#define	RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)
#define	RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)
#define	RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)
#define	RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
#define	RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
#define	RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
#define	RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
#define	RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
#define	RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)
#define	RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)
#define	RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)
#define	RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
#define	RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
#define	RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
#define	RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
#define	RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
#define	RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
#define	RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
#define	RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
#define	RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)
#define	RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
#define	RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)
#define	RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
#define	RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
#define	RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)
#define	RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)
#define	RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)
#define	RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)
#define	RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)
#define	RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)
#define	RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)
#define	RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
#define	RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
#define	RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)
#define	RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)
#define	RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)
#define	RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)
#define	RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)
#define	RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)
#define	RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)
#define	RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)
#define	RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)
#define	RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)
#define	RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)
#define	RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)
#define	RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)
#define	RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)
#define	RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)
#define	RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)
#define	RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)
#define	RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)
#define	RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)
#define	RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)
#define	RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)
#define	RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)
#define	RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)
#define	RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)
#define	RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)
#define	RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)
#define	RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)
#define	RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)
#define	RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)
#define	RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)
#define	RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)
#define	RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)
#define	RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
#define	RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
#define	RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
#define	RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
#define	RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
#define	RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
#define	RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)
#define	RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)
#define	RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)
#define	RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
#define	RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
#define	RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
#define	RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
#define	RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
#define	RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
#define	RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
#define	RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
#define	RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
#define	RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)
#define	RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)
#define	RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)
#define	RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
#define	RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
#define	RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)
#define	RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)
#define	RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)
#define	RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)
#define	RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)
#define	RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)
#define	RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)
#define	RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
#define	RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
#define	RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)
#define	RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)
#define	RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)
#define	RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)
#define	RCC_BDCR_LSEON   ((uint32_t)0x00000001)
#define	RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
#define	RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
#define	RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
#define	RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
#define	RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
#define	RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
#define	RCC_BDCR_BDRST   ((uint32_t)0x00010000)
#define	RCC_CSR_LSION   ((uint32_t)0x00000001)
#define	RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
#define	RCC_CSR_RMVF   ((uint32_t)0x01000000)
#define	RCC_CSR_BORRSTF   ((uint32_t)0x02000000)
#define	RCC_CSR_PADRSTF   ((uint32_t)0x04000000)
#define	RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
#define	RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
#define	RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)
#define	RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
#define	RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
#define	RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)
#define	RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)
#define	RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)
#define	RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)
#define	RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)
#define	RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)
#define	RNG_CR_RNGEN   ((uint32_t)0x00000004)
#define	RNG_CR_IE   ((uint32_t)0x00000008)
#define	RNG_SR_DRDY   ((uint32_t)0x00000001)
#define	RNG_SR_CECS   ((uint32_t)0x00000002)
#define	RNG_SR_SECS   ((uint32_t)0x00000004)
#define	RNG_SR_CEIS   ((uint32_t)0x00000020)
#define	RNG_SR_SEIS   ((uint32_t)0x00000040)
#define	RTC_TR_PM   ((uint32_t)0x00400000)
#define	RTC_TR_HT   ((uint32_t)0x00300000)
#define	RTC_TR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TR_HU   ((uint32_t)0x000F0000)
#define	RTC_TR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TR_MNT   ((uint32_t)0x00007000)
#define	RTC_TR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TR_ST   ((uint32_t)0x00000070)
#define	RTC_TR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TR_SU   ((uint32_t)0x0000000F)
#define	RTC_TR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TR_SU_3   ((uint32_t)0x00000008)
#define	RTC_DR_YT   ((uint32_t)0x00F00000)
#define	RTC_DR_YT_0   ((uint32_t)0x00100000)
#define	RTC_DR_YT_1   ((uint32_t)0x00200000)
#define	RTC_DR_YT_2   ((uint32_t)0x00400000)
#define	RTC_DR_YT_3   ((uint32_t)0x00800000)
#define	RTC_DR_YU   ((uint32_t)0x000F0000)
#define	RTC_DR_YU_0   ((uint32_t)0x00010000)
#define	RTC_DR_YU_1   ((uint32_t)0x00020000)
#define	RTC_DR_YU_2   ((uint32_t)0x00040000)
#define	RTC_DR_YU_3   ((uint32_t)0x00080000)
#define	RTC_DR_WDU   ((uint32_t)0x0000E000)
#define	RTC_DR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_DR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_DR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_DR_MT   ((uint32_t)0x00001000)
#define	RTC_DR_MU   ((uint32_t)0x00000F00)
#define	RTC_DR_MU_0   ((uint32_t)0x00000100)
#define	RTC_DR_MU_1   ((uint32_t)0x00000200)
#define	RTC_DR_MU_2   ((uint32_t)0x00000400)
#define	RTC_DR_MU_3   ((uint32_t)0x00000800)
#define	RTC_DR_DT   ((uint32_t)0x00000030)
#define	RTC_DR_DT_0   ((uint32_t)0x00000010)
#define	RTC_DR_DT_1   ((uint32_t)0x00000020)
#define	RTC_DR_DU   ((uint32_t)0x0000000F)
#define	RTC_DR_DU_0   ((uint32_t)0x00000001)
#define	RTC_DR_DU_1   ((uint32_t)0x00000002)
#define	RTC_DR_DU_2   ((uint32_t)0x00000004)
#define	RTC_DR_DU_3   ((uint32_t)0x00000008)
#define	RTC_CR_COE   ((uint32_t)0x00800000)
#define	RTC_CR_OSEL   ((uint32_t)0x00600000)
#define	RTC_CR_OSEL_0   ((uint32_t)0x00200000)
#define	RTC_CR_OSEL_1   ((uint32_t)0x00400000)
#define	RTC_CR_POL   ((uint32_t)0x00100000)
#define	RTC_CR_BCK   ((uint32_t)0x00040000)
#define	RTC_CR_SUB1H   ((uint32_t)0x00020000)
#define	RTC_CR_ADD1H   ((uint32_t)0x00010000)
#define	RTC_CR_TSIE   ((uint32_t)0x00008000)
#define	RTC_CR_WUTIE   ((uint32_t)0x00004000)
#define	RTC_CR_ALRBIE   ((uint32_t)0x00002000)
#define	RTC_CR_ALRAIE   ((uint32_t)0x00001000)
#define	RTC_CR_TSE   ((uint32_t)0x00000800)
#define	RTC_CR_WUTE   ((uint32_t)0x00000400)
#define	RTC_CR_ALRBE   ((uint32_t)0x00000200)
#define	RTC_CR_ALRAE   ((uint32_t)0x00000100)
#define	RTC_CR_DCE   ((uint32_t)0x00000080)
#define	RTC_CR_FMT   ((uint32_t)0x00000040)
#define	RTC_CR_REFCKON   ((uint32_t)0x00000010)
#define	RTC_CR_TSEDGE   ((uint32_t)0x00000008)
#define	RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
#define	RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
#define	RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
#define	RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
#define	RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
#define	RTC_ISR_TSOVF   ((uint32_t)0x00001000)
#define	RTC_ISR_TSF   ((uint32_t)0x00000800)
#define	RTC_ISR_WUTF   ((uint32_t)0x00000400)
#define	RTC_ISR_ALRBF   ((uint32_t)0x00000200)
#define	RTC_ISR_ALRAF   ((uint32_t)0x00000100)
#define	RTC_ISR_INIT   ((uint32_t)0x00000080)
#define	RTC_ISR_INITF   ((uint32_t)0x00000040)
#define	RTC_ISR_RSF   ((uint32_t)0x00000020)
#define	RTC_ISR_INITS   ((uint32_t)0x00000010)
#define	RTC_ISR_WUTWF   ((uint32_t)0x00000004)
#define	RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
#define	RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
#define	RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
#define	RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)
#define	RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
#define	RTC_CALIBR_DCS   ((uint32_t)0x00000080)
#define	RTC_CALIBR_DC   ((uint32_t)0x0000001F)
#define	RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMAR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMAR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMAR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMAR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
#define	RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMBR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMBR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMBR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMBR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
#define	RTC_WPR_KEY   ((uint32_t)0x000000FF)
#define	RTC_TSTR_PM   ((uint32_t)0x00400000)
#define	RTC_TSTR_HT   ((uint32_t)0x00300000)
#define	RTC_TSTR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TSTR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TSTR_HU   ((uint32_t)0x000F0000)
#define	RTC_TSTR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TSTR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TSTR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TSTR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TSTR_MNT   ((uint32_t)0x00007000)
#define	RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TSTR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TSTR_ST   ((uint32_t)0x00000070)
#define	RTC_TSTR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TSTR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TSTR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TSTR_SU   ((uint32_t)0x0000000F)
#define	RTC_TSTR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TSTR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TSTR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TSTR_SU_3   ((uint32_t)0x00000008)
#define	RTC_TSDR_WDU   ((uint32_t)0x0000E000)
#define	RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_TSDR_MT   ((uint32_t)0x00001000)
#define	RTC_TSDR_MU   ((uint32_t)0x00000F00)
#define	RTC_TSDR_MU_0   ((uint32_t)0x00000100)
#define	RTC_TSDR_MU_1   ((uint32_t)0x00000200)
#define	RTC_TSDR_MU_2   ((uint32_t)0x00000400)
#define	RTC_TSDR_MU_3   ((uint32_t)0x00000800)
#define	RTC_TSDR_DT   ((uint32_t)0x00000030)
#define	RTC_TSDR_DT_0   ((uint32_t)0x00000010)
#define	RTC_TSDR_DT_1   ((uint32_t)0x00000020)
#define	RTC_TSDR_DU   ((uint32_t)0x0000000F)
#define	RTC_TSDR_DU_0   ((uint32_t)0x00000001)
#define	RTC_TSDR_DU_1   ((uint32_t)0x00000002)
#define	RTC_TSDR_DU_2   ((uint32_t)0x00000004)
#define	RTC_TSDR_DU_3   ((uint32_t)0x00000008)
#define	RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
#define	RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)
#define	RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)
#define	RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
#define	RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
#define	RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
#define	RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
#define	SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
#define	SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
#define	SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
#define	SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
#define	SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
#define	SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
#define	SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
#define	SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
#define	SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
#define	SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
#define	SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
#define	SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
#define	SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
#define	SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
#define	SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
#define	SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
#define	SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
#define	SDIO_CMD_WAITINT   ((uint16_t)0x0100)
#define	SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
#define	SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
#define	SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
#define	SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
#define	SDIO_CMD_NIEN   ((uint16_t)0x2000)
#define	SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
#define	SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
#define	SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
#define	SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
#define	SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
#define	SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
#define	SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
#define	SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
#define	SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
#define	SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
#define	SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
#define	SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
#define	SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
#define	SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
#define	SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
#define	SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
#define	SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
#define	SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
#define	SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
#define	SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
#define	SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
#define	SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
#define	SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
#define	SDIO_STA_CMDREND   ((uint32_t)0x00000040)
#define	SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
#define	SDIO_STA_DATAEND   ((uint32_t)0x00000100)
#define	SDIO_STA_STBITERR   ((uint32_t)0x00000200)
#define	SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
#define	SDIO_STA_CMDACT   ((uint32_t)0x00000800)
#define	SDIO_STA_TXACT   ((uint32_t)0x00001000)
#define	SDIO_STA_RXACT   ((uint32_t)0x00002000)
#define	SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
#define	SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
#define	SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
#define	SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
#define	SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
#define	SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
#define	SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
#define	SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
#define	SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
#define	SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
#define	SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
#define	SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
#define	SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
#define	SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
#define	SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
#define	SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
#define	SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
#define	SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
#define	SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
#define	SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
#define	SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
#define	SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
#define	SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
#define	SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
#define	SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
#define	SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
#define	SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
#define	SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
#define	SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
#define	SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
#define	SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
#define	SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
#define	SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
#define	SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
#define	SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
#define	SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
#define	SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
#define	SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
#define	SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
#define	SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
#define	SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
#define	SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
#define	SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
#define	SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
#define	SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
#define	SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
#define	SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
#define	SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
#define	SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
#define	SPI_CR1_CPHA   ((uint16_t)0x0001)
#define	SPI_CR1_CPOL   ((uint16_t)0x0002)
#define	SPI_CR1_MSTR   ((uint16_t)0x0004)
#define	SPI_CR1_BR   ((uint16_t)0x0038)
#define	SPI_CR1_BR_0   ((uint16_t)0x0008)
#define	SPI_CR1_BR_1   ((uint16_t)0x0010)
#define	SPI_CR1_BR_2   ((uint16_t)0x0020)
#define	SPI_CR1_SPE   ((uint16_t)0x0040)
#define	SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
#define	SPI_CR1_SSI   ((uint16_t)0x0100)
#define	SPI_CR1_SSM   ((uint16_t)0x0200)
#define	SPI_CR1_RXONLY   ((uint16_t)0x0400)
#define	SPI_CR1_DFF   ((uint16_t)0x0800)
#define	SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
#define	SPI_CR1_CRCEN   ((uint16_t)0x2000)
#define	SPI_CR1_BIDIOE   ((uint16_t)0x4000)
#define	SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
#define	SPI_CR2_RXDMAEN   ((uint8_t)0x01)
#define	SPI_CR2_TXDMAEN   ((uint8_t)0x02)
#define	SPI_CR2_SSOE   ((uint8_t)0x04)
#define	SPI_CR2_ERRIE   ((uint8_t)0x20)
#define	SPI_CR2_RXNEIE   ((uint8_t)0x40)
#define	SPI_CR2_TXEIE   ((uint8_t)0x80)
#define	SPI_SR_RXNE   ((uint8_t)0x01)
#define	SPI_SR_TXE   ((uint8_t)0x02)
#define	SPI_SR_CHSIDE   ((uint8_t)0x04)
#define	SPI_SR_UDR   ((uint8_t)0x08)
#define	SPI_SR_CRCERR   ((uint8_t)0x10)
#define	SPI_SR_MODF   ((uint8_t)0x20)
#define	SPI_SR_OVR   ((uint8_t)0x40)
#define	SPI_SR_BSY   ((uint8_t)0x80)
#define	SPI_DR_DR   ((uint16_t)0xFFFF)
#define	SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
#define	SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
#define	SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
#define	SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
#define	SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
#define	SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
#define	SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
#define	SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
#define	SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
#define	SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
#define	SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
#define	SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
#define	SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
#define	SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
#define	SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
#define	SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
#define	SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
#define	SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
#define	SPI_I2SPR_ODD   ((uint16_t)0x0100)
#define	SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
#define	SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)
#define	SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
#define	SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
#define	SYSCFG_PMC_MII_RMII   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
	EXTI0 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
	EXTI1 configuration.
#define	SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
	EXTI2 configuration.
#define	SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
	EXTI3 configuration.
#define	SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
	EXTI4 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
	EXTI5 configuration.
#define	SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
	EXTI6 configuration.
#define	SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
	EXTI7 configuration.
#define	SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
	EXTI8 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
	EXTI9 configuration.
#define	SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
	EXTI10 configuration.
#define	SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
	EXTI11 configuration.
#define	SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
	EXTI12 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
	EXTI13 configuration.
#define	SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
	EXTI14 configuration.
#define	SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
	EXTI15 configuration.
#define	SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)
#define	SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
#define	SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
#define	TIM_CR1_CEN   ((uint16_t)0x0001)
#define	TIM_CR1_UDIS   ((uint16_t)0x0002)
#define	TIM_CR1_URS   ((uint16_t)0x0004)
#define	TIM_CR1_OPM   ((uint16_t)0x0008)
#define	TIM_CR1_DIR   ((uint16_t)0x0010)
#define	TIM_CR1_CMS   ((uint16_t)0x0060)
#define	TIM_CR1_CMS_0   ((uint16_t)0x0020)
#define	TIM_CR1_CMS_1   ((uint16_t)0x0040)
#define	TIM_CR1_ARPE   ((uint16_t)0x0080)
#define	TIM_CR1_CKD   ((uint16_t)0x0300)
#define	TIM_CR1_CKD_0   ((uint16_t)0x0100)
#define	TIM_CR1_CKD_1   ((uint16_t)0x0200)
#define	TIM_CR2_CCPC   ((uint16_t)0x0001)
#define	TIM_CR2_CCUS   ((uint16_t)0x0004)
#define	TIM_CR2_CCDS   ((uint16_t)0x0008)
#define	TIM_CR2_MMS   ((uint16_t)0x0070)
#define	TIM_CR2_MMS_0   ((uint16_t)0x0010)
#define	TIM_CR2_MMS_1   ((uint16_t)0x0020)
#define	TIM_CR2_MMS_2   ((uint16_t)0x0040)
#define	TIM_CR2_TI1S   ((uint16_t)0x0080)
#define	TIM_CR2_OIS1   ((uint16_t)0x0100)
#define	TIM_CR2_OIS1N   ((uint16_t)0x0200)
#define	TIM_CR2_OIS2   ((uint16_t)0x0400)
#define	TIM_CR2_OIS2N   ((uint16_t)0x0800)
#define	TIM_CR2_OIS3   ((uint16_t)0x1000)
#define	TIM_CR2_OIS3N   ((uint16_t)0x2000)
#define	TIM_CR2_OIS4   ((uint16_t)0x4000)
#define	TIM_SMCR_SMS   ((uint16_t)0x0007)
#define	TIM_SMCR_SMS_0   ((uint16_t)0x0001)
#define	TIM_SMCR_SMS_1   ((uint16_t)0x0002)
#define	TIM_SMCR_SMS_2   ((uint16_t)0x0004)
#define	TIM_SMCR_TS   ((uint16_t)0x0070)
#define	TIM_SMCR_TS_0   ((uint16_t)0x0010)
#define	TIM_SMCR_TS_1   ((uint16_t)0x0020)
#define	TIM_SMCR_TS_2   ((uint16_t)0x0040)
#define	TIM_SMCR_MSM   ((uint16_t)0x0080)
#define	TIM_SMCR_ETF   ((uint16_t)0x0F00)
#define	TIM_SMCR_ETF_0   ((uint16_t)0x0100)
#define	TIM_SMCR_ETF_1   ((uint16_t)0x0200)
#define	TIM_SMCR_ETF_2   ((uint16_t)0x0400)
#define	TIM_SMCR_ETF_3   ((uint16_t)0x0800)
#define	TIM_SMCR_ETPS   ((uint16_t)0x3000)
#define	TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
#define	TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
#define	TIM_SMCR_ECE   ((uint16_t)0x4000)
#define	TIM_SMCR_ETP   ((uint16_t)0x8000)
#define	TIM_DIER_UIE   ((uint16_t)0x0001)
#define	TIM_DIER_CC1IE   ((uint16_t)0x0002)
#define	TIM_DIER_CC2IE   ((uint16_t)0x0004)
#define	TIM_DIER_CC3IE   ((uint16_t)0x0008)
#define	TIM_DIER_CC4IE   ((uint16_t)0x0010)
#define	TIM_DIER_COMIE   ((uint16_t)0x0020)
#define	TIM_DIER_TIE   ((uint16_t)0x0040)
#define	TIM_DIER_BIE   ((uint16_t)0x0080)
#define	TIM_DIER_UDE   ((uint16_t)0x0100)
#define	TIM_DIER_CC1DE   ((uint16_t)0x0200)
#define	TIM_DIER_CC2DE   ((uint16_t)0x0400)
#define	TIM_DIER_CC3DE   ((uint16_t)0x0800)
#define	TIM_DIER_CC4DE   ((uint16_t)0x1000)
#define	TIM_DIER_COMDE   ((uint16_t)0x2000)
#define	TIM_DIER_TDE   ((uint16_t)0x4000)
#define	TIM_SR_UIF   ((uint16_t)0x0001)
#define	TIM_SR_CC1IF   ((uint16_t)0x0002)
#define	TIM_SR_CC2IF   ((uint16_t)0x0004)
#define	TIM_SR_CC3IF   ((uint16_t)0x0008)
#define	TIM_SR_CC4IF   ((uint16_t)0x0010)
#define	TIM_SR_COMIF   ((uint16_t)0x0020)
#define	TIM_SR_TIF   ((uint16_t)0x0040)
#define	TIM_SR_BIF   ((uint16_t)0x0080)
#define	TIM_SR_CC1OF   ((uint16_t)0x0200)
#define	TIM_SR_CC2OF   ((uint16_t)0x0400)
#define	TIM_SR_CC3OF   ((uint16_t)0x0800)
#define	TIM_SR_CC4OF   ((uint16_t)0x1000)
#define	TIM_EGR_UG   ((uint8_t)0x01)
#define	TIM_EGR_CC1G   ((uint8_t)0x02)
#define	TIM_EGR_CC2G   ((uint8_t)0x04)
#define	TIM_EGR_CC3G   ((uint8_t)0x08)
#define	TIM_EGR_CC4G   ((uint8_t)0x10)
#define	TIM_EGR_COMG   ((uint8_t)0x20)
#define	TIM_EGR_TG   ((uint8_t)0x40)
#define	TIM_EGR_BG   ((uint8_t)0x80)
#define	TIM_CCMR1_CC1S   ((uint16_t)0x0003)
#define	TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
#define	TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
#define	TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
#define	TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
#define	TIM_CCMR1_OC1M   ((uint16_t)0x0070)
#define	TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
#define	TIM_CCMR1_CC2S   ((uint16_t)0x0300)
#define	TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
#define	TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
#define	TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
#define	TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
#define	TIM_CCMR1_OC2M   ((uint16_t)0x7000)
#define	TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
#define	TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
#define	TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
#define	TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
#define	TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR1_IC2F   ((uint16_t)0xF000)
#define	TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
#define	TIM_CCMR2_CC3S   ((uint16_t)0x0003)
#define	TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
#define	TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
#define	TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
#define	TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
#define	TIM_CCMR2_OC3M   ((uint16_t)0x0070)
#define	TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
#define	TIM_CCMR2_CC4S   ((uint16_t)0x0300)
#define	TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
#define	TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
#define	TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
#define	TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
#define	TIM_CCMR2_OC4M   ((uint16_t)0x7000)
#define	TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
#define	TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
#define	TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
#define	TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
#define	TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR2_IC4F   ((uint16_t)0xF000)
#define	TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
#define	TIM_CCER_CC1E   ((uint16_t)0x0001)
#define	TIM_CCER_CC1P   ((uint16_t)0x0002)
#define	TIM_CCER_CC1NE   ((uint16_t)0x0004)
#define	TIM_CCER_CC1NP   ((uint16_t)0x0008)
#define	TIM_CCER_CC2E   ((uint16_t)0x0010)
#define	TIM_CCER_CC2P   ((uint16_t)0x0020)
#define	TIM_CCER_CC2NE   ((uint16_t)0x0040)
#define	TIM_CCER_CC2NP   ((uint16_t)0x0080)
#define	TIM_CCER_CC3E   ((uint16_t)0x0100)
#define	TIM_CCER_CC3P   ((uint16_t)0x0200)
#define	TIM_CCER_CC3NE   ((uint16_t)0x0400)
#define	TIM_CCER_CC3NP   ((uint16_t)0x0800)
#define	TIM_CCER_CC4E   ((uint16_t)0x1000)
#define	TIM_CCER_CC4P   ((uint16_t)0x2000)
#define	TIM_CCER_CC4NP   ((uint16_t)0x8000)
#define	TIM_CNT_CNT   ((uint16_t)0xFFFF)
#define	TIM_PSC_PSC   ((uint16_t)0xFFFF)
#define	TIM_ARR_ARR   ((uint16_t)0xFFFF)
#define	TIM_RCR_REP   ((uint8_t)0xFF)
#define	TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
#define	TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
#define	TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
#define	TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
#define	TIM_BDTR_DTG   ((uint16_t)0x00FF)
#define	TIM_BDTR_DTG_0   ((uint16_t)0x0001)
#define	TIM_BDTR_DTG_1   ((uint16_t)0x0002)
#define	TIM_BDTR_DTG_2   ((uint16_t)0x0004)
#define	TIM_BDTR_DTG_3   ((uint16_t)0x0008)
#define	TIM_BDTR_DTG_4   ((uint16_t)0x0010)
#define	TIM_BDTR_DTG_5   ((uint16_t)0x0020)
#define	TIM_BDTR_DTG_6   ((uint16_t)0x0040)
#define	TIM_BDTR_DTG_7   ((uint16_t)0x0080)
#define	TIM_BDTR_LOCK   ((uint16_t)0x0300)
#define	TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
#define	TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
#define	TIM_BDTR_OSSI   ((uint16_t)0x0400)
#define	TIM_BDTR_OSSR   ((uint16_t)0x0800)
#define	TIM_BDTR_BKE   ((uint16_t)0x1000)
#define	TIM_BDTR_BKP   ((uint16_t)0x2000)
#define	TIM_BDTR_AOE   ((uint16_t)0x4000)
#define	TIM_BDTR_MOE   ((uint16_t)0x8000)
#define	TIM_DCR_DBA   ((uint16_t)0x001F)
#define	TIM_DCR_DBA_0   ((uint16_t)0x0001)
#define	TIM_DCR_DBA_1   ((uint16_t)0x0002)
#define	TIM_DCR_DBA_2   ((uint16_t)0x0004)
#define	TIM_DCR_DBA_3   ((uint16_t)0x0008)
#define	TIM_DCR_DBA_4   ((uint16_t)0x0010)
#define	TIM_DCR_DBL   ((uint16_t)0x1F00)
#define	TIM_DCR_DBL_0   ((uint16_t)0x0100)
#define	TIM_DCR_DBL_1   ((uint16_t)0x0200)
#define	TIM_DCR_DBL_2   ((uint16_t)0x0400)
#define	TIM_DCR_DBL_3   ((uint16_t)0x0800)
#define	TIM_DCR_DBL_4   ((uint16_t)0x1000)
#define	TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
#define	TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
#define	TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
#define	TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
#define	TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
#define	TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
#define	TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
#define	USART_SR_PE   ((uint16_t)0x0001)
#define	USART_SR_FE   ((uint16_t)0x0002)
#define	USART_SR_NE   ((uint16_t)0x0004)
#define	USART_SR_ORE   ((uint16_t)0x0008)
#define	USART_SR_IDLE   ((uint16_t)0x0010)
#define	USART_SR_RXNE   ((uint16_t)0x0020)
#define	USART_SR_TC   ((uint16_t)0x0040)
#define	USART_SR_TXE   ((uint16_t)0x0080)
#define	USART_SR_LBD   ((uint16_t)0x0100)
#define	USART_SR_CTS   ((uint16_t)0x0200)
#define	USART_DR_DR   ((uint16_t)0x01FF)
#define	USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
#define	USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
#define	USART_CR1_SBK   ((uint16_t)0x0001)
#define	USART_CR1_RWU   ((uint16_t)0x0002)
#define	USART_CR1_RE   ((uint16_t)0x0004)
#define	USART_CR1_TE   ((uint16_t)0x0008)
#define	USART_CR1_IDLEIE   ((uint16_t)0x0010)
#define	USART_CR1_RXNEIE   ((uint16_t)0x0020)
#define	USART_CR1_TCIE   ((uint16_t)0x0040)
#define	USART_CR1_TXEIE   ((uint16_t)0x0080)
#define	USART_CR1_PEIE   ((uint16_t)0x0100)
#define	USART_CR1_PS   ((uint16_t)0x0200)
#define	USART_CR1_PCE   ((uint16_t)0x0400)
#define	USART_CR1_WAKE   ((uint16_t)0x0800)
#define	USART_CR1_M   ((uint16_t)0x1000)
#define	USART_CR1_UE   ((uint16_t)0x2000)
#define	USART_CR1_OVER8   ((uint16_t)0x8000)
#define	USART_CR2_ADD   ((uint16_t)0x000F)
#define	USART_CR2_LBDL   ((uint16_t)0x0020)
#define	USART_CR2_LBDIE   ((uint16_t)0x0040)
#define	USART_CR2_LBCL   ((uint16_t)0x0100)
#define	USART_CR2_CPHA   ((uint16_t)0x0200)
#define	USART_CR2_CPOL   ((uint16_t)0x0400)
#define	USART_CR2_CLKEN   ((uint16_t)0x0800)
#define	USART_CR2_STOP   ((uint16_t)0x3000)
#define	USART_CR2_STOP_0   ((uint16_t)0x1000)
#define	USART_CR2_STOP_1   ((uint16_t)0x2000)
#define	USART_CR2_LINEN   ((uint16_t)0x4000)
#define	USART_CR3_EIE   ((uint16_t)0x0001)
#define	USART_CR3_IREN   ((uint16_t)0x0002)
#define	USART_CR3_IRLP   ((uint16_t)0x0004)
#define	USART_CR3_HDSEL   ((uint16_t)0x0008)
#define	USART_CR3_NACK   ((uint16_t)0x0010)
#define	USART_CR3_SCEN   ((uint16_t)0x0020)
#define	USART_CR3_DMAR   ((uint16_t)0x0040)
#define	USART_CR3_DMAT   ((uint16_t)0x0080)
#define	USART_CR3_RTSE   ((uint16_t)0x0100)
#define	USART_CR3_CTSE   ((uint16_t)0x0200)
#define	USART_CR3_CTSIE   ((uint16_t)0x0400)
#define	USART_CR3_ONEBIT   ((uint16_t)0x0800)
#define	USART_GTPR_PSC   ((uint16_t)0x00FF)
#define	USART_GTPR_PSC_0   ((uint16_t)0x0001)
#define	USART_GTPR_PSC_1   ((uint16_t)0x0002)
#define	USART_GTPR_PSC_2   ((uint16_t)0x0004)
#define	USART_GTPR_PSC_3   ((uint16_t)0x0008)
#define	USART_GTPR_PSC_4   ((uint16_t)0x0010)
#define	USART_GTPR_PSC_5   ((uint16_t)0x0020)
#define	USART_GTPR_PSC_6   ((uint16_t)0x0040)
#define	USART_GTPR_PSC_7   ((uint16_t)0x0080)
#define	USART_GTPR_GT   ((uint16_t)0xFF00)
#define	WWDG_CR_T   ((uint8_t)0x7F)
#define	WWDG_CR_T0   ((uint8_t)0x01)
#define	WWDG_CR_T1   ((uint8_t)0x02)
#define	WWDG_CR_T2   ((uint8_t)0x04)
#define	WWDG_CR_T3   ((uint8_t)0x08)
#define	WWDG_CR_T4   ((uint8_t)0x10)
#define	WWDG_CR_T5   ((uint8_t)0x20)
#define	WWDG_CR_T6   ((uint8_t)0x40)
#define	WWDG_CR_WDGA   ((uint8_t)0x80)
#define	WWDG_CFR_W   ((uint16_t)0x007F)
#define	WWDG_CFR_W0   ((uint16_t)0x0001)
#define	WWDG_CFR_W1   ((uint16_t)0x0002)
#define	WWDG_CFR_W2   ((uint16_t)0x0004)
#define	WWDG_CFR_W3   ((uint16_t)0x0008)
#define	WWDG_CFR_W4   ((uint16_t)0x0010)
#define	WWDG_CFR_W5   ((uint16_t)0x0020)
#define	WWDG_CFR_W6   ((uint16_t)0x0040)
#define	WWDG_CFR_WDGTB   ((uint16_t)0x0180)
#define	WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
#define	WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
#define	WWDG_CFR_EWI   ((uint16_t)0x0200)
#define	WWDG_SR_EWIF   ((uint8_t)0x01)
#define	DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
#define	DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
#define	DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
#define	DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
#define	DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
#define	DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
#define	DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
#define	DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)
#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)
#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
#define	DBGMCU_APB1_FZ_DBG_IWDEG_STOP   ((uint32_t)0x00001000)
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)
#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)
#define	DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)
#define	DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)
#define	DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)
#define	DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)
#define	ETH_MACCR_WD   ((uint32_t)0x00800000)
#define	ETH_MACCR_JD   ((uint32_t)0x00400000)
#define	ETH_MACCR_IFG   ((uint32_t)0x000E0000)
#define	ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000)
#define	ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000)
#define	ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000)
#define	ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000)
#define	ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000)
#define	ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000)
#define	ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000)
#define	ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000)
#define	ETH_MACCR_CSD   ((uint32_t)0x00010000)
#define	ETH_MACCR_FES   ((uint32_t)0x00004000)
#define	ETH_MACCR_ROD   ((uint32_t)0x00002000)
#define	ETH_MACCR_LM   ((uint32_t)0x00001000)
#define	ETH_MACCR_DM   ((uint32_t)0x00000800)
#define	ETH_MACCR_IPCO   ((uint32_t)0x00000400)
#define	ETH_MACCR_RD   ((uint32_t)0x00000200)
#define	ETH_MACCR_APCS   ((uint32_t)0x00000080)
#define	ETH_MACCR_BL   ((uint32_t)0x00000060)
#define	ETH_MACCR_BL_10   ((uint32_t)0x00000000)
#define	ETH_MACCR_BL_8   ((uint32_t)0x00000020)
#define	ETH_MACCR_BL_4   ((uint32_t)0x00000040)
#define	ETH_MACCR_BL_1   ((uint32_t)0x00000060)
#define	ETH_MACCR_DC   ((uint32_t)0x00000010)
#define	ETH_MACCR_TE   ((uint32_t)0x00000008)
#define	ETH_MACCR_RE   ((uint32_t)0x00000004)
#define	ETH_MACFFR_RA   ((uint32_t)0x80000000)
#define	ETH_MACFFR_HPF   ((uint32_t)0x00000400)
#define	ETH_MACFFR_SAF   ((uint32_t)0x00000200)
#define	ETH_MACFFR_SAIF   ((uint32_t)0x00000100)
#define	ETH_MACFFR_PCF   ((uint32_t)0x000000C0)
#define	ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040)
#define	ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080)
#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0)
#define	ETH_MACFFR_BFD   ((uint32_t)0x00000020)
#define	ETH_MACFFR_PAM   ((uint32_t)0x00000010)
#define	ETH_MACFFR_DAIF   ((uint32_t)0x00000008)
#define	ETH_MACFFR_HM   ((uint32_t)0x00000004)
#define	ETH_MACFFR_HU   ((uint32_t)0x00000002)
#define	ETH_MACFFR_PM   ((uint32_t)0x00000001)
#define	ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)
#define	ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)
#define	ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)
#define	ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)
#define	ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)
#define	ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)
#define	ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)
#define	ETH_MACMIIAR_MW   ((uint32_t)0x00000002)
#define	ETH_MACMIIAR_MB   ((uint32_t)0x00000001)
#define	ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)
#define	ETH_MACFCR_PT   ((uint32_t)0xFFFF0000)
#define	ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)
#define	ETH_MACFCR_PLT   ((uint32_t)0x00000030)
#define	ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)
#define	ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010)
#define	ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020)
#define	ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030)
#define	ETH_MACFCR_UPFD   ((uint32_t)0x00000008)
#define	ETH_MACFCR_RFCE   ((uint32_t)0x00000004)
#define	ETH_MACFCR_TFCE   ((uint32_t)0x00000002)
#define	ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001)
#define	ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000)
#define	ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF)
#define	ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000)
#define	ETH_MACPMTCSR_GU   ((uint32_t)0x00000200)
#define	ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040)
#define	ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020)
#define	ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004)
#define	ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002)
#define	ETH_MACPMTCSR_PD   ((uint32_t)0x00000001)
#define	ETH_MACSR_TSTS   ((uint32_t)0x00000200)
#define	ETH_MACSR_MMCTS   ((uint32_t)0x00000040)
#define	ETH_MACSR_MMMCRS   ((uint32_t)0x00000020)
#define	ETH_MACSR_MMCS   ((uint32_t)0x00000010)
#define	ETH_MACSR_PMTS   ((uint32_t)0x00000008)
#define	ETH_MACIMR_TSTIM   ((uint32_t)0x00000200)
#define	ETH_MACIMR_PMTIM   ((uint32_t)0x00000008)
#define	ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA1HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA1HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA1HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA2HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA2HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA2HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA3HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA3HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA3HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCCR_MCFHP   ((uint32_t)0x00000020)
#define	ETH_MMCCR_MCP   ((uint32_t)0x00000010)
#define	ETH_MMCCR_MCF   ((uint32_t)0x00000008)
#define	ETH_MMCCR_ROR   ((uint32_t)0x00000004)
#define	ETH_MMCCR_CSR   ((uint32_t)0x00000002)
#define	ETH_MMCCR_CR   ((uint32_t)0x00000001)
#define	ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000)
#define	ETH_MMCRIR_RFAES   ((uint32_t)0x00000040)
#define	ETH_MMCRIR_RFCES   ((uint32_t)0x00000020)
#define	ETH_MMCTIR_TGFS   ((uint32_t)0x00200000)
#define	ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)
#define	ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000)
#define	ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000)
#define	ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040)
#define	ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020)
#define	ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000)
#define	ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000)
#define	ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)
#define	ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000)
#define	ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000)
#define	ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000)
#define	ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)
#define	ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)
#define	ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800)
#define	ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400)
#define	ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200)
#define	ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100)
#define	ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020)
#define	ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010)
#define	ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008)
#define	ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004)
#define	ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002)
#define	ETH_PTPTSCR_TSE   ((uint32_t)0x00000001)
#define	ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF)
#define	ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000)
#define	ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF)
#define	ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000)
#define	ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)
#define	ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020)
#define	ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010)
#define	ETH_DMABMR_AAB   ((uint32_t)0x02000000)
#define	ETH_DMABMR_FPM   ((uint32_t)0x01000000)
#define	ETH_DMABMR_USP   ((uint32_t)0x00800000)
#define	ETH_DMABMR_RDP   ((uint32_t)0x007E0000)
#define	ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000)
#define	ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000)
#define	ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000)
#define	ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000)
#define	ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)
#define	ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)
#define	ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)
#define	ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)
#define	ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000)
#define	ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000)
#define	ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000)
#define	ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000)
#define	ETH_DMABMR_FB   ((uint32_t)0x00010000)
#define	ETH_DMABMR_RTPR   ((uint32_t)0x0000C000)
#define	ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000)
#define	ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000)
#define	ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000)
#define	ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000)
#define	ETH_DMABMR_PBL   ((uint32_t)0x00003F00)
#define	ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100)
#define	ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200)
#define	ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400)
#define	ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800)
#define	ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)
#define	ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)
#define	ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)
#define	ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)
#define	ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400)
#define	ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800)
#define	ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000)
#define	ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000)
#define	ETH_DMABMR_EDE   ((uint32_t)0x00000080)
#define	ETH_DMABMR_DSL   ((uint32_t)0x0000007C)
#define	ETH_DMABMR_DA   ((uint32_t)0x00000002)
#define	ETH_DMABMR_SR   ((uint32_t)0x00000001)
#define	ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMASR_TSTS   ((uint32_t)0x20000000)
#define	ETH_DMASR_PMTS   ((uint32_t)0x10000000)
#define	ETH_DMASR_MMCS   ((uint32_t)0x08000000)
#define	ETH_DMASR_EBS   ((uint32_t)0x03800000)
#define	ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000)
#define	ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000)
#define	ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000)
#define	ETH_DMASR_TPS   ((uint32_t)0x00700000)
#define	ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000)
#define	ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000)
#define	ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000)
#define	ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000)
#define	ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000)
#define	ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000)
#define	ETH_DMASR_RPS   ((uint32_t)0x000E0000)
#define	ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000)
#define	ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000)
#define	ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000)
#define	ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000)
#define	ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000)
#define	ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000)
#define	ETH_DMASR_NIS   ((uint32_t)0x00010000)
#define	ETH_DMASR_AIS   ((uint32_t)0x00008000)
#define	ETH_DMASR_ERS   ((uint32_t)0x00004000)
#define	ETH_DMASR_FBES   ((uint32_t)0x00002000)
#define	ETH_DMASR_ETS   ((uint32_t)0x00000400)
#define	ETH_DMASR_RWTS   ((uint32_t)0x00000200)
#define	ETH_DMASR_RPSS   ((uint32_t)0x00000100)
#define	ETH_DMASR_RBUS   ((uint32_t)0x00000080)
#define	ETH_DMASR_RS   ((uint32_t)0x00000040)
#define	ETH_DMASR_TUS   ((uint32_t)0x00000020)
#define	ETH_DMASR_ROS   ((uint32_t)0x00000010)
#define	ETH_DMASR_TJTS   ((uint32_t)0x00000008)
#define	ETH_DMASR_TBUS   ((uint32_t)0x00000004)
#define	ETH_DMASR_TPSS   ((uint32_t)0x00000002)
#define	ETH_DMASR_TS   ((uint32_t)0x00000001)
#define	ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000)
#define	ETH_DMAOMR_RSF   ((uint32_t)0x02000000)
#define	ETH_DMAOMR_DFRF   ((uint32_t)0x01000000)
#define	ETH_DMAOMR_TSF   ((uint32_t)0x00200000)
#define	ETH_DMAOMR_FTF   ((uint32_t)0x00100000)
#define	ETH_DMAOMR_TTC   ((uint32_t)0x0001C000)
#define	ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000)
#define	ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000)
#define	ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000)
#define	ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000)
#define	ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000)
#define	ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000)
#define	ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000)
#define	ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000)
#define	ETH_DMAOMR_ST   ((uint32_t)0x00002000)
#define	ETH_DMAOMR_FEF   ((uint32_t)0x00000080)
#define	ETH_DMAOMR_FUGF   ((uint32_t)0x00000040)
#define	ETH_DMAOMR_RTC   ((uint32_t)0x00000018)
#define	ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000)
#define	ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008)
#define	ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010)
#define	ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018)
#define	ETH_DMAOMR_OSF   ((uint32_t)0x00000004)
#define	ETH_DMAOMR_SR   ((uint32_t)0x00000002)
#define	ETH_DMAIER_NISE   ((uint32_t)0x00010000)
#define	ETH_DMAIER_AISE   ((uint32_t)0x00008000)
#define	ETH_DMAIER_ERIE   ((uint32_t)0x00004000)
#define	ETH_DMAIER_FBEIE   ((uint32_t)0x00002000)
#define	ETH_DMAIER_ETIE   ((uint32_t)0x00000400)
#define	ETH_DMAIER_RWTIE   ((uint32_t)0x00000200)
#define	ETH_DMAIER_RPSIE   ((uint32_t)0x00000100)
#define	ETH_DMAIER_RBUIE   ((uint32_t)0x00000080)
#define	ETH_DMAIER_RIE   ((uint32_t)0x00000040)
#define	ETH_DMAIER_TUIE   ((uint32_t)0x00000020)
#define	ETH_DMAIER_ROIE   ((uint32_t)0x00000010)
#define	ETH_DMAIER_TJTIE   ((uint32_t)0x00000008)
#define	ETH_DMAIER_TBUIE   ((uint32_t)0x00000004)
#define	ETH_DMAIER_TPSIE   ((uint32_t)0x00000002)
#define	ETH_DMAIER_TIE   ((uint32_t)0x00000001)
#define	ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)
#define	ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000)
#define	ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)
#define	ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF)
#define	ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF)
#define	ADC_SR_AWD   ((uint8_t)0x01)
#define	ADC_SR_EOC   ((uint8_t)0x02)
#define	ADC_SR_JEOC   ((uint8_t)0x04)
#define	ADC_SR_JSTRT   ((uint8_t)0x08)
#define	ADC_SR_STRT   ((uint8_t)0x10)
#define	ADC_SR_OVR   ((uint8_t)0x20)
#define	ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
#define	ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
#define	ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
#define	ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
#define	ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
#define	ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
#define	ADC_CR1_EOCIE   ((uint32_t)0x00000020)
#define	ADC_CR1_AWDIE   ((uint32_t)0x00000040)
#define	ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
#define	ADC_CR1_SCAN   ((uint32_t)0x00000100)
#define	ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
#define	ADC_CR1_JAUTO   ((uint32_t)0x00000400)
#define	ADC_CR1_DISCEN   ((uint32_t)0x00000800)
#define	ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
#define	ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
#define	ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
#define	ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
#define	ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
#define	ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
#define	ADC_CR1_AWDEN   ((uint32_t)0x00800000)
#define	ADC_CR1_RES   ((uint32_t)0x03000000)
#define	ADC_CR1_RES_0   ((uint32_t)0x01000000)
#define	ADC_CR1_RES_1   ((uint32_t)0x02000000)
#define	ADC_CR1_OVRIE   ((uint32_t)0x04000000)
#define	ADC_CR2_ADON   ((uint32_t)0x00000001)
#define	ADC_CR2_CONT   ((uint32_t)0x00000002)
#define	ADC_CR2_DMA   ((uint32_t)0x00000100)
#define	ADC_CR2_DDS   ((uint32_t)0x00000200)
#define	ADC_CR2_EOCS   ((uint32_t)0x00000400)
#define	ADC_CR2_ALIGN   ((uint32_t)0x00000800)
#define	ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
#define	ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
#define	ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
#define	ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
#define	ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
#define	ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
#define	ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
#define	ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
#define	ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
#define	ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
#define	ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
#define	ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
#define	ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
#define	ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
#define	ADC_CR2_EXTEN   ((uint32_t)0x30000000)
#define	ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
#define	ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
#define	ADC_CR2_SWSTART   ((uint32_t)0x40000000)
#define	ADC_SMPR1_SMP10   ((uint32_t)0x00000007)
#define	ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)
#define	ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)
#define	ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)
#define	ADC_SMPR1_SMP11   ((uint32_t)0x00000038)
#define	ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)
#define	ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)
#define	ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)
#define	ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)
#define	ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)
#define	ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)
#define	ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)
#define	ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)
#define	ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)
#define	ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)
#define	ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)
#define	ADC_SMPR1_SMP14   ((uint32_t)0x00007000)
#define	ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)
#define	ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)
#define	ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)
#define	ADC_SMPR1_SMP15   ((uint32_t)0x00038000)
#define	ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)
#define	ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)
#define	ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)
#define	ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)
#define	ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)
#define	ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)
#define	ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)
#define	ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)
#define	ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)
#define	ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)
#define	ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)
#define	ADC_SMPR1_SMP18   ((uint32_t)0x07000000)
#define	ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)
#define	ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)
#define	ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP0   ((uint32_t)0x00000007)
#define	ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)
#define	ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)
#define	ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)
#define	ADC_SMPR2_SMP1   ((uint32_t)0x00000038)
#define	ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)
#define	ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)
#define	ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)
#define	ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)
#define	ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)
#define	ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)
#define	ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)
#define	ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)
#define	ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)
#define	ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)
#define	ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)
#define	ADC_SMPR2_SMP4   ((uint32_t)0x00007000)
#define	ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)
#define	ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)
#define	ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)
#define	ADC_SMPR2_SMP5   ((uint32_t)0x00038000)
#define	ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)
#define	ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)
#define	ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)
#define	ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)
#define	ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)
#define	ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)
#define	ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)
#define	ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)
#define	ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)
#define	ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)
#define	ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)
#define	ADC_SMPR2_SMP8   ((uint32_t)0x07000000)
#define	ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)
#define	ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)
#define	ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP9   ((uint32_t)0x38000000)
#define	ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)
#define	ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)
#define	ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)
#define	ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)
#define	ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)
#define	ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)
#define	ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)
#define	ADC_HTR_HT   ((uint16_t)0x0FFF)
#define	ADC_LTR_LT   ((uint16_t)0x0FFF)
#define	ADC_SQR1_SQ13   ((uint32_t)0x0000001F)
#define	ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)
#define	ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)
#define	ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)
#define	ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)
#define	ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)
#define	ADC_SQR1_SQ14   ((uint32_t)0x000003E0)
#define	ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)
#define	ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)
#define	ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)
#define	ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)
#define	ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)
#define	ADC_SQR1_SQ15   ((uint32_t)0x00007C00)
#define	ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)
#define	ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)
#define	ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)
#define	ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)
#define	ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)
#define	ADC_SQR1_SQ16   ((uint32_t)0x000F8000)
#define	ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)
#define	ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)
#define	ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)
#define	ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)
#define	ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)
#define	ADC_SQR1_L   ((uint32_t)0x00F00000)
#define	ADC_SQR1_L_0   ((uint32_t)0x00100000)
#define	ADC_SQR1_L_1   ((uint32_t)0x00200000)
#define	ADC_SQR1_L_2   ((uint32_t)0x00400000)
#define	ADC_SQR1_L_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ7   ((uint32_t)0x0000001F)
#define	ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)
#define	ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)
#define	ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)
#define	ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)
#define	ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)
#define	ADC_SQR2_SQ8   ((uint32_t)0x000003E0)
#define	ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)
#define	ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)
#define	ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)
#define	ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)
#define	ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)
#define	ADC_SQR2_SQ9   ((uint32_t)0x00007C00)
#define	ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)
#define	ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)
#define	ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)
#define	ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)
#define	ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)
#define	ADC_SQR2_SQ10   ((uint32_t)0x000F8000)
#define	ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)
#define	ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)
#define	ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)
#define	ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)
#define	ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)
#define	ADC_SQR2_SQ11   ((uint32_t)0x01F00000)
#define	ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)
#define	ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)
#define	ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)
#define	ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)
#define	ADC_SQR2_SQ12   ((uint32_t)0x3E000000)
#define	ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)
#define	ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)
#define	ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)
#define	ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)
#define	ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)
#define	ADC_SQR3_SQ1   ((uint32_t)0x0000001F)
#define	ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)
#define	ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)
#define	ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)
#define	ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)
#define	ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)
#define	ADC_SQR3_SQ2   ((uint32_t)0x000003E0)
#define	ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)
#define	ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)
#define	ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)
#define	ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)
#define	ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)
#define	ADC_SQR3_SQ3   ((uint32_t)0x00007C00)
#define	ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)
#define	ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)
#define	ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)
#define	ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)
#define	ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)
#define	ADC_SQR3_SQ4   ((uint32_t)0x000F8000)
#define	ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)
#define	ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)
#define	ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)
#define	ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)
#define	ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)
#define	ADC_SQR3_SQ5   ((uint32_t)0x01F00000)
#define	ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)
#define	ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)
#define	ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)
#define	ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)
#define	ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)
#define	ADC_SQR3_SQ6   ((uint32_t)0x3E000000)
#define	ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)
#define	ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)
#define	ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)
#define	ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)
#define	ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)
#define	ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
#define	ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
#define	ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
#define	ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
#define	ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
#define	ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
#define	ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
#define	ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
#define	ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
#define	ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
#define	ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
#define	ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
#define	ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
#define	ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
#define	ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
#define	ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
#define	ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
#define	ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
#define	ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
#define	ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
#define	ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
#define	ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
#define	ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
#define	ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
#define	ADC_JSQR_JL   ((uint32_t)0x00300000)
#define	ADC_JSQR_JL_0   ((uint32_t)0x00100000)
#define	ADC_JSQR_JL_1   ((uint32_t)0x00200000)
#define	ADC_JDR1_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR2_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR3_JDATA   ((uint16_t)0xFFFF)
#define	ADC_JDR4_JDATA   ((uint16_t)0xFFFF)
#define	ADC_DR_DATA   ((uint32_t)0x0000FFFF)
#define	ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)
#define	ADC_CSR_AWD1   ((uint32_t)0x00000001)
#define	ADC_CSR_EOC1   ((uint32_t)0x00000002)
#define	ADC_CSR_JEOC1   ((uint32_t)0x00000004)
#define	ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
#define	ADC_CSR_STRT1   ((uint32_t)0x00000010)
#define	ADC_CSR_DOVR1   ((uint32_t)0x00000020)
#define	ADC_CSR_AWD2   ((uint32_t)0x00000100)
#define	ADC_CSR_EOC2   ((uint32_t)0x00000200)
#define	ADC_CSR_JEOC2   ((uint32_t)0x00000400)
#define	ADC_CSR_JSTRT2   ((uint32_t)0x00000800)
#define	ADC_CSR_STRT2   ((uint32_t)0x00001000)
#define	ADC_CSR_DOVR2   ((uint32_t)0x00002000)
#define	ADC_CSR_AWD3   ((uint32_t)0x00010000)
#define	ADC_CSR_EOC3   ((uint32_t)0x00020000)
#define	ADC_CSR_JEOC3   ((uint32_t)0x00040000)
#define	ADC_CSR_JSTRT3   ((uint32_t)0x00080000)
#define	ADC_CSR_STRT3   ((uint32_t)0x00100000)
#define	ADC_CSR_DOVR3   ((uint32_t)0x00200000)
#define	ADC_CCR_MULTI   ((uint32_t)0x0000001F)
#define	ADC_CCR_MULTI_0   ((uint32_t)0x00000001)
#define	ADC_CCR_MULTI_1   ((uint32_t)0x00000002)
#define	ADC_CCR_MULTI_2   ((uint32_t)0x00000004)
#define	ADC_CCR_MULTI_3   ((uint32_t)0x00000008)
#define	ADC_CCR_MULTI_4   ((uint32_t)0x00000010)
#define	ADC_CCR_DELAY   ((uint32_t)0x00000F00)
#define	ADC_CCR_DELAY_0   ((uint32_t)0x00000100)
#define	ADC_CCR_DELAY_1   ((uint32_t)0x00000200)
#define	ADC_CCR_DELAY_2   ((uint32_t)0x00000400)
#define	ADC_CCR_DELAY_3   ((uint32_t)0x00000800)
#define	ADC_CCR_DDS   ((uint32_t)0x00002000)
#define	ADC_CCR_DMA   ((uint32_t)0x0000C000)
#define	ADC_CCR_DMA_0   ((uint32_t)0x00004000)
#define	ADC_CCR_DMA_1   ((uint32_t)0x00008000)
#define	ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
#define	ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
#define	ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
#define	ADC_CCR_VBATE   ((uint32_t)0x00400000)
#define	ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
#define	ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)
#define	ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)
#define	CAN_MCR_INRQ   ((uint16_t)0x0001)
#define	CAN_MCR_SLEEP   ((uint16_t)0x0002)
#define	CAN_MCR_TXFP   ((uint16_t)0x0004)
#define	CAN_MCR_RFLM   ((uint16_t)0x0008)
#define	CAN_MCR_NART   ((uint16_t)0x0010)
#define	CAN_MCR_AWUM   ((uint16_t)0x0020)
#define	CAN_MCR_ABOM   ((uint16_t)0x0040)
#define	CAN_MCR_TTCM   ((uint16_t)0x0080)
#define	CAN_MCR_RESET   ((uint16_t)0x8000)
#define	CAN_MSR_INAK   ((uint16_t)0x0001)
#define	CAN_MSR_SLAK   ((uint16_t)0x0002)
#define	CAN_MSR_ERRI   ((uint16_t)0x0004)
#define	CAN_MSR_WKUI   ((uint16_t)0x0008)
#define	CAN_MSR_SLAKI   ((uint16_t)0x0010)
#define	CAN_MSR_TXM   ((uint16_t)0x0100)
#define	CAN_MSR_RXM   ((uint16_t)0x0200)
#define	CAN_MSR_SAMP   ((uint16_t)0x0400)
#define	CAN_MSR_RX   ((uint16_t)0x0800)
#define	CAN_TSR_RQCP0   ((uint32_t)0x00000001)
#define	CAN_TSR_TXOK0   ((uint32_t)0x00000002)
#define	CAN_TSR_ALST0   ((uint32_t)0x00000004)
#define	CAN_TSR_TERR0   ((uint32_t)0x00000008)
#define	CAN_TSR_ABRQ0   ((uint32_t)0x00000080)
#define	CAN_TSR_RQCP1   ((uint32_t)0x00000100)
#define	CAN_TSR_TXOK1   ((uint32_t)0x00000200)
#define	CAN_TSR_ALST1   ((uint32_t)0x00000400)
#define	CAN_TSR_TERR1   ((uint32_t)0x00000800)
#define	CAN_TSR_ABRQ1   ((uint32_t)0x00008000)
#define	CAN_TSR_RQCP2   ((uint32_t)0x00010000)
#define	CAN_TSR_TXOK2   ((uint32_t)0x00020000)
#define	CAN_TSR_ALST2   ((uint32_t)0x00040000)
#define	CAN_TSR_TERR2   ((uint32_t)0x00080000)
#define	CAN_TSR_ABRQ2   ((uint32_t)0x00800000)
#define	CAN_TSR_CODE   ((uint32_t)0x03000000)
#define	CAN_TSR_TME   ((uint32_t)0x1C000000)
#define	CAN_TSR_TME0   ((uint32_t)0x04000000)
#define	CAN_TSR_TME1   ((uint32_t)0x08000000)
#define	CAN_TSR_TME2   ((uint32_t)0x10000000)
#define	CAN_TSR_LOW   ((uint32_t)0xE0000000)
#define	CAN_TSR_LOW0   ((uint32_t)0x20000000)
#define	CAN_TSR_LOW1   ((uint32_t)0x40000000)
#define	CAN_TSR_LOW2   ((uint32_t)0x80000000)
#define	CAN_RF0R_FMP0   ((uint8_t)0x03)
#define	CAN_RF0R_FULL0   ((uint8_t)0x08)
#define	CAN_RF0R_FOVR0   ((uint8_t)0x10)
#define	CAN_RF0R_RFOM0   ((uint8_t)0x20)
#define	CAN_RF1R_FMP1   ((uint8_t)0x03)
#define	CAN_RF1R_FULL1   ((uint8_t)0x08)
#define	CAN_RF1R_FOVR1   ((uint8_t)0x10)
#define	CAN_RF1R_RFOM1   ((uint8_t)0x20)
#define	CAN_IER_TMEIE   ((uint32_t)0x00000001)
#define	CAN_IER_FMPIE0   ((uint32_t)0x00000002)
#define	CAN_IER_FFIE0   ((uint32_t)0x00000004)
#define	CAN_IER_FOVIE0   ((uint32_t)0x00000008)
#define	CAN_IER_FMPIE1   ((uint32_t)0x00000010)
#define	CAN_IER_FFIE1   ((uint32_t)0x00000020)
#define	CAN_IER_FOVIE1   ((uint32_t)0x00000040)
#define	CAN_IER_EWGIE   ((uint32_t)0x00000100)
#define	CAN_IER_EPVIE   ((uint32_t)0x00000200)
#define	CAN_IER_BOFIE   ((uint32_t)0x00000400)
#define	CAN_IER_LECIE   ((uint32_t)0x00000800)
#define	CAN_IER_ERRIE   ((uint32_t)0x00008000)
#define	CAN_IER_WKUIE   ((uint32_t)0x00010000)
#define	CAN_IER_SLKIE   ((uint32_t)0x00020000)
#define	CAN_ESR_EWGF   ((uint32_t)0x00000001)
#define	CAN_ESR_EPVF   ((uint32_t)0x00000002)
#define	CAN_ESR_BOFF   ((uint32_t)0x00000004)
#define	CAN_ESR_LEC   ((uint32_t)0x00000070)
#define	CAN_ESR_LEC_0   ((uint32_t)0x00000010)
#define	CAN_ESR_LEC_1   ((uint32_t)0x00000020)
#define	CAN_ESR_LEC_2   ((uint32_t)0x00000040)
#define	CAN_ESR_TEC   ((uint32_t)0x00FF0000)
#define	CAN_ESR_REC   ((uint32_t)0xFF000000)
#define	CAN_BTR_BRP   ((uint32_t)0x000003FF)
#define	CAN_BTR_TS1   ((uint32_t)0x000F0000)
#define	CAN_BTR_TS2   ((uint32_t)0x00700000)
#define	CAN_BTR_SJW   ((uint32_t)0x03000000)
#define	CAN_BTR_LBKM   ((uint32_t)0x40000000)
#define	CAN_BTR_SILM   ((uint32_t)0x80000000)
#define	CAN_TI0R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT0R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI1R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT1R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_TI2R_TXRQ   ((uint32_t)0x00000001)
#define	CAN_TI2R_RTR   ((uint32_t)0x00000002)
#define	CAN_TI2R_IDE   ((uint32_t)0x00000004)
#define	CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_TI2R_STID   ((uint32_t)0xFFE00000)
#define	CAN_TDT2R_DLC   ((uint32_t)0x0000000F)
#define	CAN_TDT2R_TGT   ((uint32_t)0x00000100)
#define	CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI0R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI0R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI0R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT0R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_RI1R_RTR   ((uint32_t)0x00000002)
#define	CAN_RI1R_IDE   ((uint32_t)0x00000004)
#define	CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)
#define	CAN_RI1R_STID   ((uint32_t)0xFFE00000)
#define	CAN_RDT1R_DLC   ((uint32_t)0x0000000F)
#define	CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)
#define	CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)
#define	CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)
#define	CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)
#define	CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)
#define	CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)
#define	CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)
#define	CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)
#define	CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)
#define	CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)
#define	CAN_FMR_FINIT   ((uint8_t)0x01)
#define	CAN_FM1R_FBM   ((uint16_t)0x3FFF)
#define	CAN_FM1R_FBM0   ((uint16_t)0x0001)
#define	CAN_FM1R_FBM1   ((uint16_t)0x0002)
#define	CAN_FM1R_FBM2   ((uint16_t)0x0004)
#define	CAN_FM1R_FBM3   ((uint16_t)0x0008)
#define	CAN_FM1R_FBM4   ((uint16_t)0x0010)
#define	CAN_FM1R_FBM5   ((uint16_t)0x0020)
#define	CAN_FM1R_FBM6   ((uint16_t)0x0040)
#define	CAN_FM1R_FBM7   ((uint16_t)0x0080)
#define	CAN_FM1R_FBM8   ((uint16_t)0x0100)
#define	CAN_FM1R_FBM9   ((uint16_t)0x0200)
#define	CAN_FM1R_FBM10   ((uint16_t)0x0400)
#define	CAN_FM1R_FBM11   ((uint16_t)0x0800)
#define	CAN_FM1R_FBM12   ((uint16_t)0x1000)
#define	CAN_FM1R_FBM13   ((uint16_t)0x2000)
#define	CAN_FS1R_FSC   ((uint16_t)0x3FFF)
#define	CAN_FS1R_FSC0   ((uint16_t)0x0001)
#define	CAN_FS1R_FSC1   ((uint16_t)0x0002)
#define	CAN_FS1R_FSC2   ((uint16_t)0x0004)
#define	CAN_FS1R_FSC3   ((uint16_t)0x0008)
#define	CAN_FS1R_FSC4   ((uint16_t)0x0010)
#define	CAN_FS1R_FSC5   ((uint16_t)0x0020)
#define	CAN_FS1R_FSC6   ((uint16_t)0x0040)
#define	CAN_FS1R_FSC7   ((uint16_t)0x0080)
#define	CAN_FS1R_FSC8   ((uint16_t)0x0100)
#define	CAN_FS1R_FSC9   ((uint16_t)0x0200)
#define	CAN_FS1R_FSC10   ((uint16_t)0x0400)
#define	CAN_FS1R_FSC11   ((uint16_t)0x0800)
#define	CAN_FS1R_FSC12   ((uint16_t)0x1000)
#define	CAN_FS1R_FSC13   ((uint16_t)0x2000)
#define	CAN_FFA1R_FFA   ((uint16_t)0x3FFF)
#define	CAN_FFA1R_FFA0   ((uint16_t)0x0001)
#define	CAN_FFA1R_FFA1   ((uint16_t)0x0002)
#define	CAN_FFA1R_FFA2   ((uint16_t)0x0004)
#define	CAN_FFA1R_FFA3   ((uint16_t)0x0008)
#define	CAN_FFA1R_FFA4   ((uint16_t)0x0010)
#define	CAN_FFA1R_FFA5   ((uint16_t)0x0020)
#define	CAN_FFA1R_FFA6   ((uint16_t)0x0040)
#define	CAN_FFA1R_FFA7   ((uint16_t)0x0080)
#define	CAN_FFA1R_FFA8   ((uint16_t)0x0100)
#define	CAN_FFA1R_FFA9   ((uint16_t)0x0200)
#define	CAN_FFA1R_FFA10   ((uint16_t)0x0400)
#define	CAN_FFA1R_FFA11   ((uint16_t)0x0800)
#define	CAN_FFA1R_FFA12   ((uint16_t)0x1000)
#define	CAN_FFA1R_FFA13   ((uint16_t)0x2000)
#define	CAN_FA1R_FACT   ((uint16_t)0x3FFF)
#define	CAN_FA1R_FACT0   ((uint16_t)0x0001)
#define	CAN_FA1R_FACT1   ((uint16_t)0x0002)
#define	CAN_FA1R_FACT2   ((uint16_t)0x0004)
#define	CAN_FA1R_FACT3   ((uint16_t)0x0008)
#define	CAN_FA1R_FACT4   ((uint16_t)0x0010)
#define	CAN_FA1R_FACT5   ((uint16_t)0x0020)
#define	CAN_FA1R_FACT6   ((uint16_t)0x0040)
#define	CAN_FA1R_FACT7   ((uint16_t)0x0080)
#define	CAN_FA1R_FACT8   ((uint16_t)0x0100)
#define	CAN_FA1R_FACT9   ((uint16_t)0x0200)
#define	CAN_FA1R_FACT10   ((uint16_t)0x0400)
#define	CAN_FA1R_FACT11   ((uint16_t)0x0800)
#define	CAN_FA1R_FACT12   ((uint16_t)0x1000)
#define	CAN_FA1R_FACT13   ((uint16_t)0x2000)
#define	CAN_F0R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R1_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R1_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R1_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R1_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R1_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R1_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R1_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R1_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R1_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R1_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R1_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R1_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R1_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R1_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R1_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R1_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R1_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R1_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R1_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R1_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R1_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R1_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R1_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R1_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R1_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R1_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R1_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R1_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R1_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R1_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R1_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R1_FB31   ((uint32_t)0x80000000)
#define	CAN_F0R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F0R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F0R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F0R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F0R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F0R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F0R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F0R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F0R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F0R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F0R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F0R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F0R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F0R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F0R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F0R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F0R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F0R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F0R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F0R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F0R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F0R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F0R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F0R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F0R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F0R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F0R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F0R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F0R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F0R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F0R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F0R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F1R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F1R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F1R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F1R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F1R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F1R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F1R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F1R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F1R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F1R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F1R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F1R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F1R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F1R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F1R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F1R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F1R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F1R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F1R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F1R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F1R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F1R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F1R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F1R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F1R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F1R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F1R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F1R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F1R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F1R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F1R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F1R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F2R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F2R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F2R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F2R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F2R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F2R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F2R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F2R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F2R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F2R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F2R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F2R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F2R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F2R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F2R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F2R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F2R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F2R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F2R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F2R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F2R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F2R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F2R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F2R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F2R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F2R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F2R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F2R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F2R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F2R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F2R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F2R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F3R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F3R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F3R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F3R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F3R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F3R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F3R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F3R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F3R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F3R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F3R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F3R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F3R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F3R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F3R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F3R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F3R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F3R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F3R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F3R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F3R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F3R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F3R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F3R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F3R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F3R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F3R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F3R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F3R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F3R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F3R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F3R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F4R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F4R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F4R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F4R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F4R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F4R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F4R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F4R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F4R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F4R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F4R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F4R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F4R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F4R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F4R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F4R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F4R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F4R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F4R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F4R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F4R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F4R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F4R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F4R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F4R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F4R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F4R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F4R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F4R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F4R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F4R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F4R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F5R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F5R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F5R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F5R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F5R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F5R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F5R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F5R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F5R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F5R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F5R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F5R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F5R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F5R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F5R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F5R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F5R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F5R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F5R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F5R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F5R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F5R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F5R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F5R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F5R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F5R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F5R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F5R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F5R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F5R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F5R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F5R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F6R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F6R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F6R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F6R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F6R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F6R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F6R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F6R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F6R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F6R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F6R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F6R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F6R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F6R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F6R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F6R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F6R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F6R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F6R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F6R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F6R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F6R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F6R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F6R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F6R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F6R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F6R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F6R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F6R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F6R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F6R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F6R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F7R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F7R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F7R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F7R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F7R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F7R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F7R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F7R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F7R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F7R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F7R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F7R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F7R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F7R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F7R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F7R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F7R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F7R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F7R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F7R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F7R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F7R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F7R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F7R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F7R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F7R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F7R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F7R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F7R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F7R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F7R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F7R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F8R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F8R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F8R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F8R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F8R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F8R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F8R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F8R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F8R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F8R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F8R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F8R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F8R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F8R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F8R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F8R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F8R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F8R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F8R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F8R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F8R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F8R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F8R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F8R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F8R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F8R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F8R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F8R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F8R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F8R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F8R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F8R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F9R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F9R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F9R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F9R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F9R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F9R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F9R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F9R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F9R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F9R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F9R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F9R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F9R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F9R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F9R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F9R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F9R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F9R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F9R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F9R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F9R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F9R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F9R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F9R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F9R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F9R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F9R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F9R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F9R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F9R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F9R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F9R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F10R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F10R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F10R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F10R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F10R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F10R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F10R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F10R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F10R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F10R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F10R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F10R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F10R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F10R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F10R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F10R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F10R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F10R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F10R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F10R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F10R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F10R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F10R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F10R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F10R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F10R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F10R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F10R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F10R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F10R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F10R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F10R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F11R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F11R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F11R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F11R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F11R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F11R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F11R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F11R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F11R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F11R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F11R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F11R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F11R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F11R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F11R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F11R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F11R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F11R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F11R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F11R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F11R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F11R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F11R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F11R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F11R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F11R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F11R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F11R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F11R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F11R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F11R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F11R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F12R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F12R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F12R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F12R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F12R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F12R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F12R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F12R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F12R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F12R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F12R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F12R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F12R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F12R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F12R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F12R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F12R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F12R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F12R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F12R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F12R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F12R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F12R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F12R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F12R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F12R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F12R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F12R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F12R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F12R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F12R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F12R2_FB31   ((uint32_t)0x80000000)
#define	CAN_F13R2_FB0   ((uint32_t)0x00000001)
#define	CAN_F13R2_FB1   ((uint32_t)0x00000002)
#define	CAN_F13R2_FB2   ((uint32_t)0x00000004)
#define	CAN_F13R2_FB3   ((uint32_t)0x00000008)
#define	CAN_F13R2_FB4   ((uint32_t)0x00000010)
#define	CAN_F13R2_FB5   ((uint32_t)0x00000020)
#define	CAN_F13R2_FB6   ((uint32_t)0x00000040)
#define	CAN_F13R2_FB7   ((uint32_t)0x00000080)
#define	CAN_F13R2_FB8   ((uint32_t)0x00000100)
#define	CAN_F13R2_FB9   ((uint32_t)0x00000200)
#define	CAN_F13R2_FB10   ((uint32_t)0x00000400)
#define	CAN_F13R2_FB11   ((uint32_t)0x00000800)
#define	CAN_F13R2_FB12   ((uint32_t)0x00001000)
#define	CAN_F13R2_FB13   ((uint32_t)0x00002000)
#define	CAN_F13R2_FB14   ((uint32_t)0x00004000)
#define	CAN_F13R2_FB15   ((uint32_t)0x00008000)
#define	CAN_F13R2_FB16   ((uint32_t)0x00010000)
#define	CAN_F13R2_FB17   ((uint32_t)0x00020000)
#define	CAN_F13R2_FB18   ((uint32_t)0x00040000)
#define	CAN_F13R2_FB19   ((uint32_t)0x00080000)
#define	CAN_F13R2_FB20   ((uint32_t)0x00100000)
#define	CAN_F13R2_FB21   ((uint32_t)0x00200000)
#define	CAN_F13R2_FB22   ((uint32_t)0x00400000)
#define	CAN_F13R2_FB23   ((uint32_t)0x00800000)
#define	CAN_F13R2_FB24   ((uint32_t)0x01000000)
#define	CAN_F13R2_FB25   ((uint32_t)0x02000000)
#define	CAN_F13R2_FB26   ((uint32_t)0x04000000)
#define	CAN_F13R2_FB27   ((uint32_t)0x08000000)
#define	CAN_F13R2_FB28   ((uint32_t)0x10000000)
#define	CAN_F13R2_FB29   ((uint32_t)0x20000000)
#define	CAN_F13R2_FB30   ((uint32_t)0x40000000)
#define	CAN_F13R2_FB31   ((uint32_t)0x80000000)
#define	CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
#define	CRC_IDR_IDR   ((uint8_t)0xFF)
#define	CRC_CR_RESET   ((uint8_t)0x01)
#define	CRYP_CR_ALGODIR   ((uint32_t)0x00000004)
#define	CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)
#define	CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)
#define	CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)
#define	CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)
#define	CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)
#define	CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)
#define	CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)
#define	CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)
#define	CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)
#define	CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)
#define	CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)
#define	CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)
#define	CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)
#define	CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)
#define	CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)
#define	CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)
#define	CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)
#define	CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)
#define	CRYP_CR_FFLUSH   ((uint32_t)0x00004000)
#define	CRYP_CR_CRYPEN   ((uint32_t)0x00008000)
#define	CRYP_SR_IFEM   ((uint32_t)0x00000001)
#define	CRYP_SR_IFNF   ((uint32_t)0x00000002)
#define	CRYP_SR_OFNE   ((uint32_t)0x00000004)
#define	CRYP_SR_OFFU   ((uint32_t)0x00000008)
#define	CRYP_SR_BUSY   ((uint32_t)0x00000010)
#define	CRYP_DMACR_DIEN   ((uint32_t)0x00000001)
#define	CRYP_DMACR_DOEN   ((uint32_t)0x00000002)
#define	CRYP_IMSCR_INIM   ((uint32_t)0x00000001)
#define	CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)
#define	CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)
#define	CRYP_RISR_INRIS   ((uint32_t)0x00000002)
#define	CRYP_MISR_INMIS   ((uint32_t)0x00000001)
#define	CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)
#define	DAC_CR_EN1   ((uint32_t)0x00000001)
#define	DAC_CR_BOFF1   ((uint32_t)0x00000002)
#define	DAC_CR_TEN1   ((uint32_t)0x00000004)
#define	DAC_CR_TSEL1   ((uint32_t)0x00000038)
#define	DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
#define	DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
#define	DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
#define	DAC_CR_WAVE1   ((uint32_t)0x000000C0)
#define	DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
#define	DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
#define	DAC_CR_MAMP1   ((uint32_t)0x00000F00)
#define	DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
#define	DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
#define	DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
#define	DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
#define	DAC_CR_DMAEN1   ((uint32_t)0x00001000)
#define	DAC_CR_EN2   ((uint32_t)0x00010000)
#define	DAC_CR_BOFF2   ((uint32_t)0x00020000)
#define	DAC_CR_TEN2   ((uint32_t)0x00040000)
#define	DAC_CR_TSEL2   ((uint32_t)0x00380000)
#define	DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
#define	DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
#define	DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
#define	DAC_CR_WAVE2   ((uint32_t)0x00C00000)
#define	DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
#define	DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
#define	DAC_CR_MAMP2   ((uint32_t)0x0F000000)
#define	DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
#define	DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
#define	DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
#define	DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
#define	DAC_CR_DMAEN2   ((uint32_t)0x10000000)
#define	DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
#define	DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
#define	DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
#define	DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
#define	DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
#define	DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
#define	DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
#define	DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
#define	DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
#define	DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
#define	DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
#define	DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
#define	DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
#define	DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
#define	DCMI_CR_CAPTURE   ((uint32_t)0x00000001)
#define	DCMI_CR_CM   ((uint32_t)0x00000002)
#define	DCMI_CR_CROP   ((uint32_t)0x00000004)
#define	DCMI_CR_JPEG   ((uint32_t)0x00000008)
#define	DCMI_CR_ESS   ((uint32_t)0x00000010)
#define	DCMI_CR_PCKPOL   ((uint32_t)0x00000020)
#define	DCMI_CR_HSPOL   ((uint32_t)0x00000040)
#define	DCMI_CR_VSPOL   ((uint32_t)0x00000080)
#define	DCMI_CR_FCRC_0   ((uint32_t)0x00000100)
#define	DCMI_CR_FCRC_1   ((uint32_t)0x00000200)
#define	DCMI_CR_EDM_0   ((uint32_t)0x00000400)
#define	DCMI_CR_EDM_1   ((uint32_t)0x00000800)
#define	DCMI_CR_CRE   ((uint32_t)0x00001000)
#define	DCMI_CR_ENABLE   ((uint32_t)0x00004000)
#define	DCMI_SR_HSYNC   ((uint32_t)0x00000001)
#define	DCMI_SR_VSYNC   ((uint32_t)0x00000002)
#define	DCMI_SR_FNE   ((uint32_t)0x00000004)
#define	DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)
#define	DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)
#define	DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)
#define	DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)
#define	DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)
#define	DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)
#define	DCMI_IER_OVF_IE   ((uint32_t)0x00000002)
#define	DCMI_IER_ERR_IE   ((uint32_t)0x00000004)
#define	DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)
#define	DCMI_IER_LINE_IE   ((uint32_t)0x00000010)
#define	DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)
#define	DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)
#define	DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)
#define	DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)
#define	DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)
#define	DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)
#define	DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)
#define	DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)
#define	DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)
#define	DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)
#define	DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)
#define	DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)
#define	DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)
#define	DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)
#define	DMA_SxCR_MBURST   ((uint32_t)0x01800000)
#define	DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)
#define	DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)
#define	DMA_SxCR_PBURST   ((uint32_t)0x00600000)
#define	DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)
#define	DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)
#define	DMA_SxCR_ACK   ((uint32_t)0x00100000)
#define	DMA_SxCR_CT   ((uint32_t)0x00080000)
#define	DMA_SxCR_DBM   ((uint32_t)0x00040000)
#define	DMA_SxCR_PL   ((uint32_t)0x00030000)
#define	DMA_SxCR_PL_0   ((uint32_t)0x00010000)
#define	DMA_SxCR_PL_1   ((uint32_t)0x00020000)
#define	DMA_SxCR_PINCOS   ((uint32_t)0x00008000)
#define	DMA_SxCR_MSIZE   ((uint32_t)0x00006000)
#define	DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)
#define	DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)
#define	DMA_SxCR_PSIZE   ((uint32_t)0x00001800)
#define	DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)
#define	DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)
#define	DMA_SxCR_MINC   ((uint32_t)0x00000400)
#define	DMA_SxCR_PINC   ((uint32_t)0x00000200)
#define	DMA_SxCR_CIRC   ((uint32_t)0x00000100)
#define	DMA_SxCR_DIR   ((uint32_t)0x000000C0)
#define	DMA_SxCR_DIR_0   ((uint32_t)0x00000040)
#define	DMA_SxCR_DIR_1   ((uint32_t)0x00000080)
#define	DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)
#define	DMA_SxCR_TCIE   ((uint32_t)0x00000010)
#define	DMA_SxCR_HTIE   ((uint32_t)0x00000008)
#define	DMA_SxCR_TEIE   ((uint32_t)0x00000004)
#define	DMA_SxCR_DMEIE   ((uint32_t)0x00000002)
#define	DMA_SxCR_EN   ((uint32_t)0x00000001)
#define	DMA_SxNDT   ((uint32_t)0x0000FFFF)
#define	DMA_SxNDT_0   ((uint32_t)0x00000001)
#define	DMA_SxNDT_1   ((uint32_t)0x00000002)
#define	DMA_SxNDT_2   ((uint32_t)0x00000004)
#define	DMA_SxNDT_3   ((uint32_t)0x00000008)
#define	DMA_SxNDT_4   ((uint32_t)0x00000010)
#define	DMA_SxNDT_5   ((uint32_t)0x00000020)
#define	DMA_SxNDT_6   ((uint32_t)0x00000040)
#define	DMA_SxNDT_7   ((uint32_t)0x00000080)
#define	DMA_SxNDT_8   ((uint32_t)0x00000100)
#define	DMA_SxNDT_9   ((uint32_t)0x00000200)
#define	DMA_SxNDT_10   ((uint32_t)0x00000400)
#define	DMA_SxNDT_11   ((uint32_t)0x00000800)
#define	DMA_SxNDT_12   ((uint32_t)0x00001000)
#define	DMA_SxNDT_13   ((uint32_t)0x00002000)
#define	DMA_SxNDT_14   ((uint32_t)0x00004000)
#define	DMA_SxNDT_15   ((uint32_t)0x00008000)
#define	DMA_SxFCR_FEIE   ((uint32_t)0x00000080)
#define	DMA_SxFCR_FS   ((uint32_t)0x00000038)
#define	DMA_SxFCR_FS_0   ((uint32_t)0x00000008)
#define	DMA_SxFCR_FS_1   ((uint32_t)0x00000010)
#define	DMA_SxFCR_FS_2   ((uint32_t)0x00000020)
#define	DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)
#define	DMA_SxFCR_FTH   ((uint32_t)0x00000003)
#define	DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)
#define	DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)
#define	DMA_LISR_TCIF3   ((uint32_t)0x08000000)
#define	DMA_LISR_HTIF3   ((uint32_t)0x04000000)
#define	DMA_LISR_TEIF3   ((uint32_t)0x02000000)
#define	DMA_LISR_DMEIF3   ((uint32_t)0x01000000)
#define	DMA_LISR_FEIF3   ((uint32_t)0x00400000)
#define	DMA_LISR_TCIF2   ((uint32_t)0x00200000)
#define	DMA_LISR_HTIF2   ((uint32_t)0x00100000)
#define	DMA_LISR_TEIF2   ((uint32_t)0x00080000)
#define	DMA_LISR_DMEIF2   ((uint32_t)0x00040000)
#define	DMA_LISR_FEIF2   ((uint32_t)0x00010000)
#define	DMA_LISR_TCIF1   ((uint32_t)0x00000800)
#define	DMA_LISR_HTIF1   ((uint32_t)0x00000400)
#define	DMA_LISR_TEIF1   ((uint32_t)0x00000200)
#define	DMA_LISR_DMEIF1   ((uint32_t)0x00000100)
#define	DMA_LISR_FEIF1   ((uint32_t)0x00000040)
#define	DMA_LISR_TCIF0   ((uint32_t)0x00000020)
#define	DMA_LISR_HTIF0   ((uint32_t)0x00000010)
#define	DMA_LISR_TEIF0   ((uint32_t)0x00000008)
#define	DMA_LISR_DMEIF0   ((uint32_t)0x00000004)
#define	DMA_LISR_FEIF0   ((uint32_t)0x00000001)
#define	DMA_HISR_TCIF7   ((uint32_t)0x08000000)
#define	DMA_HISR_HTIF7   ((uint32_t)0x04000000)
#define	DMA_HISR_TEIF7   ((uint32_t)0x02000000)
#define	DMA_HISR_DMEIF7   ((uint32_t)0x01000000)
#define	DMA_HISR_FEIF7   ((uint32_t)0x00400000)
#define	DMA_HISR_TCIF6   ((uint32_t)0x00200000)
#define	DMA_HISR_HTIF6   ((uint32_t)0x00100000)
#define	DMA_HISR_TEIF6   ((uint32_t)0x00080000)
#define	DMA_HISR_DMEIF6   ((uint32_t)0x00040000)
#define	DMA_HISR_FEIF6   ((uint32_t)0x00010000)
#define	DMA_HISR_TCIF5   ((uint32_t)0x00000800)
#define	DMA_HISR_HTIF5   ((uint32_t)0x00000400)
#define	DMA_HISR_TEIF5   ((uint32_t)0x00000200)
#define	DMA_HISR_DMEIF5   ((uint32_t)0x00000100)
#define	DMA_HISR_FEIF5   ((uint32_t)0x00000040)
#define	DMA_HISR_TCIF4   ((uint32_t)0x00000020)
#define	DMA_HISR_HTIF4   ((uint32_t)0x00000010)
#define	DMA_HISR_TEIF4   ((uint32_t)0x00000008)
#define	DMA_HISR_DMEIF4   ((uint32_t)0x00000004)
#define	DMA_HISR_FEIF4   ((uint32_t)0x00000001)
#define	DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)
#define	DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)
#define	DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)
#define	DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)
#define	DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)
#define	DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)
#define	DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)
#define	DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)
#define	DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)
#define	DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)
#define	DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)
#define	DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)
#define	DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)
#define	DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)
#define	DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)
#define	DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)
#define	DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)
#define	DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)
#define	DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)
#define	DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)
#define	DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)
#define	DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)
#define	DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)
#define	DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)
#define	DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)
#define	DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)
#define	DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)
#define	DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)
#define	DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)
#define	DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)
#define	DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)
#define	DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)
#define	DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)
#define	DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)
#define	DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)
#define	DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)
#define	DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)
#define	DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)
#define	DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)
#define	DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_IMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_IMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_IMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_IMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_IMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_IMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_IMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_IMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_IMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_IMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_IMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_IMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_IMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_IMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_IMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_IMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_IMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_IMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_EMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_EMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_EMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_EMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_EMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_EMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_EMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_EMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_EMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_EMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_EMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_EMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_EMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_EMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_EMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_EMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_EMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_EMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_EMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_EMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_RTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_RTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_RTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_RTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_RTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_RTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_RTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_RTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_RTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_RTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_RTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_RTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_RTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_RTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_RTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_RTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_RTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_RTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_RTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_RTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_FTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_FTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_FTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_FTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_FTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_FTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_FTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_FTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_FTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_FTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_FTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_FTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_FTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_FTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_FTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_FTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_FTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_FTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_FTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_FTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
#define	EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
#define	EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
#define	EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
#define	EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
#define	EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
#define	EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
#define	EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
#define	EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
#define	EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
#define	EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
#define	EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
#define	EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
#define	EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
#define	EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
#define	EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
#define	EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
#define	EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
#define	EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
#define	EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
#define	EXTI_PR_PR0   ((uint32_t)0x00000001)
#define	EXTI_PR_PR1   ((uint32_t)0x00000002)
#define	EXTI_PR_PR2   ((uint32_t)0x00000004)
#define	EXTI_PR_PR3   ((uint32_t)0x00000008)
#define	EXTI_PR_PR4   ((uint32_t)0x00000010)
#define	EXTI_PR_PR5   ((uint32_t)0x00000020)
#define	EXTI_PR_PR6   ((uint32_t)0x00000040)
#define	EXTI_PR_PR7   ((uint32_t)0x00000080)
#define	EXTI_PR_PR8   ((uint32_t)0x00000100)
#define	EXTI_PR_PR9   ((uint32_t)0x00000200)
#define	EXTI_PR_PR10   ((uint32_t)0x00000400)
#define	EXTI_PR_PR11   ((uint32_t)0x00000800)
#define	EXTI_PR_PR12   ((uint32_t)0x00001000)
#define	EXTI_PR_PR13   ((uint32_t)0x00002000)
#define	EXTI_PR_PR14   ((uint32_t)0x00004000)
#define	EXTI_PR_PR15   ((uint32_t)0x00008000)
#define	EXTI_PR_PR16   ((uint32_t)0x00010000)
#define	EXTI_PR_PR17   ((uint32_t)0x00020000)
#define	EXTI_PR_PR18   ((uint32_t)0x00040000)
#define	EXTI_PR_PR19   ((uint32_t)0x00080000)
#define	FLASH_ACR_LATENCY   ((uint32_t)0x00000007)
#define	FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)
#define	FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)
#define	FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)
#define	FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)
#define	FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)
#define	FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)
#define	FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)
#define	FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)
#define	FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)
#define	FLASH_ACR_ICEN   ((uint32_t)0x00000200)
#define	FLASH_ACR_DCEN   ((uint32_t)0x00000400)
#define	FLASH_ACR_ICRST   ((uint32_t)0x00000800)
#define	FLASH_ACR_DCRST   ((uint32_t)0x00001000)
#define	FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)
#define	FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)
#define	FLASH_SR_EOP   ((uint32_t)0x00000001)
#define	FLASH_SR_SOP   ((uint32_t)0x00000002)
#define	FLASH_SR_WRPERR   ((uint32_t)0x00000010)
#define	FLASH_SR_PGAERR   ((uint32_t)0x00000020)
#define	FLASH_SR_PGPERR   ((uint32_t)0x00000040)
#define	FLASH_SR_PGSERR   ((uint32_t)0x00000080)
#define	FLASH_SR_BSY   ((uint32_t)0x00010000)
#define	FLASH_CR_PG   ((uint32_t)0x00000001)
#define	FLASH_CR_SER   ((uint32_t)0x00000002)
#define	FLASH_CR_MER   ((uint32_t)0x00000004)
#define	FLASH_CR_SNB_0   ((uint32_t)0x00000008)
#define	FLASH_CR_SNB_1   ((uint32_t)0x00000010)
#define	FLASH_CR_SNB_2   ((uint32_t)0x00000020)
#define	FLASH_CR_SNB_3   ((uint32_t)0x00000040)
#define	FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)
#define	FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)
#define	FLASH_CR_STRT   ((uint32_t)0x00010000)
#define	FLASH_CR_EOPIE   ((uint32_t)0x01000000)
#define	FLASH_CR_LOCK   ((uint32_t)0x80000000)
#define	FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)
#define	FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)
#define	FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)
#define	FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)
#define	FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)
#define	FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)
#define	FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)
#define	FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)
#define	FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)
#define	FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)
#define	FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)
#define	FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)
#define	FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)
#define	FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)
#define	FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)
#define	FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)
#define	FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)
#define	FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)
#define	FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)
#define	FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)
#define	FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)
#define	FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)
#define	FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)
#define	FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)
#define	FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)
#define	FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)
#define	FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)
#define	FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)
#define	FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR1_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR1_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR2_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR2_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR3_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR3_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR4_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR4_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR2_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR2_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR2_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR3_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR3_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR3_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)
#define	FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)
#define	FSMC_PCR4_PTYP   ((uint32_t)0x00000008)
#define	FSMC_PCR4_PWID   ((uint32_t)0x00000030)
#define	FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)
#define	FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)
#define	FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)
#define	FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)
#define	FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)
#define	FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)
#define	FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)
#define	FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)
#define	FSMC_PCR4_TAR   ((uint32_t)0x0001E000)
#define	FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)
#define	FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)
#define	FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)
#define	FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)
#define	FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)
#define	FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)
#define	FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)
#define	FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)
#define	FSMC_SR2_IRS   ((uint8_t)0x01)
#define	FSMC_SR2_ILS   ((uint8_t)0x02)
#define	FSMC_SR2_IFS   ((uint8_t)0x04)
#define	FSMC_SR2_IREN   ((uint8_t)0x08)
#define	FSMC_SR2_ILEN   ((uint8_t)0x10)
#define	FSMC_SR2_IFEN   ((uint8_t)0x20)
#define	FSMC_SR2_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR3_IRS   ((uint8_t)0x01)
#define	FSMC_SR3_ILS   ((uint8_t)0x02)
#define	FSMC_SR3_IFS   ((uint8_t)0x04)
#define	FSMC_SR3_IREN   ((uint8_t)0x08)
#define	FSMC_SR3_ILEN   ((uint8_t)0x10)
#define	FSMC_SR3_IFEN   ((uint8_t)0x20)
#define	FSMC_SR3_FEMPT   ((uint8_t)0x40)
#define	FSMC_SR4_IRS   ((uint8_t)0x01)
#define	FSMC_SR4_ILS   ((uint8_t)0x02)
#define	FSMC_SR4_IFS   ((uint8_t)0x04)
#define	FSMC_SR4_IREN   ((uint8_t)0x08)
#define	FSMC_SR4_ILEN   ((uint8_t)0x10)
#define	FSMC_SR4_IFEN   ((uint8_t)0x20)
#define	FSMC_SR4_FEMPT   ((uint8_t)0x40)
#define	FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)
#define	FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)
#define	FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)
#define	FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)
#define	FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)
#define	FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)
#define	FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)
#define	FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)
#define	FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)
#define	FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)
#define	FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)
#define	FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)
#define	FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)
#define	FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)
#define	FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)
#define	FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)
#define	FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)
#define	FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)
#define	FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)
#define	FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)
#define	FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)
#define	FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)
#define	FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)
#define	FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)
#define	FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)
#define	FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)
#define	FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)
#define	FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)
#define	FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)
#define	FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)
#define	FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)
#define	FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)
#define	FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)
#define	FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)
#define	FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)
#define	FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)
#define	FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)
#define	FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)
#define	FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)
#define	FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)
#define	FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)
#define	FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)
#define	FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)
#define	FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)
#define	FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)
#define	FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)
#define	FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)
#define	FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)
#define	FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)
#define	FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)
#define	FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)
#define	FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)
#define	FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)
#define	FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)
#define	FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)
#define	FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)
#define	FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)
#define	FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)
#define	FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)
#define	FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)
#define	FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)
#define	FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)
#define	FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)
#define	FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)
#define	FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)
#define	FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)
#define	FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)
#define	FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)
#define	FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)
#define	FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)
#define	FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)
#define	FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)
#define	FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)
#define	FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)
#define	FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)
#define	FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)
#define	FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)
#define	FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)
#define	FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)
#define	FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)
#define	FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)
#define	FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)
#define	FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)
#define	FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)
#define	FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)
#define	FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)
#define	FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)
#define	FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)
#define	FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)
#define	FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)
#define	FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)
#define	FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)
#define	FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)
#define	FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)
#define	FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)
#define	FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)
#define	FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)
#define	FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)
#define	FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)
#define	FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)
#define	FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)
#define	FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)
#define	FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)
#define	FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)
#define	FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)
#define	FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)
#define	FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)
#define	FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)
#define	FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)
#define	FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)
#define	FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)
#define	FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)
#define	FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)
#define	FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)
#define	GPIO_MODER_MODER0   ((uint32_t)0x00000003)
#define	GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
#define	GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
#define	GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
#define	GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
#define	GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
#define	GPIO_MODER_MODER2   ((uint32_t)0x00000030)
#define	GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
#define	GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
#define	GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
#define	GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
#define	GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
#define	GPIO_MODER_MODER4   ((uint32_t)0x00000300)
#define	GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
#define	GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
#define	GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
#define	GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
#define	GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
#define	GPIO_MODER_MODER6   ((uint32_t)0x00003000)
#define	GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
#define	GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
#define	GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
#define	GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
#define	GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
#define	GPIO_MODER_MODER8   ((uint32_t)0x00030000)
#define	GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
#define	GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
#define	GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
#define	GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
#define	GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
#define	GPIO_MODER_MODER10   ((uint32_t)0x00300000)
#define	GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
#define	GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
#define	GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
#define	GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
#define	GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
#define	GPIO_MODER_MODER12   ((uint32_t)0x03000000)
#define	GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
#define	GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
#define	GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
#define	GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
#define	GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
#define	GPIO_MODER_MODER14   ((uint32_t)0x30000000)
#define	GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
#define	GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
#define	GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
#define	GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
#define	GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
#define	GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
#define	GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
#define	GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
#define	GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
#define	GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
#define	GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
#define	GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
#define	GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
#define	GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
#define	GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
#define	GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
#define	GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
#define	GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
#define	GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
#define	GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
#define	GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
#define	GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
#define	GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
#define	GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
#define	GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
#define	GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
#define	GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
#define	GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
#define	GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
#define	GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
#define	GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
#define	GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
#define	GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
#define	GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
#define	GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
#define	GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
#define	GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
#define	GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
#define	GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
#define	GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
#define	GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
#define	GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
#define	GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
#define	GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
#define	GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
#define	GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
#define	GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
#define	GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
#define	GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
#define	GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
#define	GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
#define	GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
#define	GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
#define	GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
#define	GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
#define	GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
#define	GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
#define	GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
#define	GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
#define	GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
#define	GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
#define	GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
#define	GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
#define	GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
#define	GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
#define	GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
#define	GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
#define	GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
#define	GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
#define	GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
#define	GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
#define	GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
#define	GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
#define	GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
#define	GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
#define	GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
#define	GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
#define	GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
#define	GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
#define	GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
#define	GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
#define	GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
#define	GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
#define	GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
#define	GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
#define	GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
#define	GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
#define	GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
#define	GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
#define	GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
#define	GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
#define	GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
#define	GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
#define	GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
#define	GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
#define	GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
#define	GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
#define	GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
#define	GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
#define	GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
#define	GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
#define	GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
#define	GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
#define	GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
#define	GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
#define	GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
#define	GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
#define	GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
#define	GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
#define	GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
#define	GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
#define	GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
#define	GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
#define	GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
#define	GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
#define	GPIO_IDR_IDR_0   ((uint32_t)0x00000001)
#define	GPIO_IDR_IDR_1   ((uint32_t)0x00000002)
#define	GPIO_IDR_IDR_2   ((uint32_t)0x00000004)
#define	GPIO_IDR_IDR_3   ((uint32_t)0x00000008)
#define	GPIO_IDR_IDR_4   ((uint32_t)0x00000010)
#define	GPIO_IDR_IDR_5   ((uint32_t)0x00000020)
#define	GPIO_IDR_IDR_6   ((uint32_t)0x00000040)
#define	GPIO_IDR_IDR_7   ((uint32_t)0x00000080)
#define	GPIO_IDR_IDR_8   ((uint32_t)0x00000100)
#define	GPIO_IDR_IDR_9   ((uint32_t)0x00000200)
#define	GPIO_IDR_IDR_10   ((uint32_t)0x00000400)
#define	GPIO_IDR_IDR_11   ((uint32_t)0x00000800)
#define	GPIO_IDR_IDR_12   ((uint32_t)0x00001000)
#define	GPIO_IDR_IDR_13   ((uint32_t)0x00002000)
#define	GPIO_IDR_IDR_14   ((uint32_t)0x00004000)
#define	GPIO_IDR_IDR_15   ((uint32_t)0x00008000)
#define	GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0
#define	GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1
#define	GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2
#define	GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3
#define	GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4
#define	GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5
#define	GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6
#define	GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7
#define	GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8
#define	GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9
#define	GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10
#define	GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11
#define	GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12
#define	GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13
#define	GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14
#define	GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15
#define	GPIO_ODR_ODR_0   ((uint32_t)0x00000001)
#define	GPIO_ODR_ODR_1   ((uint32_t)0x00000002)
#define	GPIO_ODR_ODR_2   ((uint32_t)0x00000004)
#define	GPIO_ODR_ODR_3   ((uint32_t)0x00000008)
#define	GPIO_ODR_ODR_4   ((uint32_t)0x00000010)
#define	GPIO_ODR_ODR_5   ((uint32_t)0x00000020)
#define	GPIO_ODR_ODR_6   ((uint32_t)0x00000040)
#define	GPIO_ODR_ODR_7   ((uint32_t)0x00000080)
#define	GPIO_ODR_ODR_8   ((uint32_t)0x00000100)
#define	GPIO_ODR_ODR_9   ((uint32_t)0x00000200)
#define	GPIO_ODR_ODR_10   ((uint32_t)0x00000400)
#define	GPIO_ODR_ODR_11   ((uint32_t)0x00000800)
#define	GPIO_ODR_ODR_12   ((uint32_t)0x00001000)
#define	GPIO_ODR_ODR_13   ((uint32_t)0x00002000)
#define	GPIO_ODR_ODR_14   ((uint32_t)0x00004000)
#define	GPIO_ODR_ODR_15   ((uint32_t)0x00008000)
#define	GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0
#define	GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1
#define	GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2
#define	GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3
#define	GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4
#define	GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5
#define	GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6
#define	GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7
#define	GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8
#define	GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9
#define	GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10
#define	GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11
#define	GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12
#define	GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13
#define	GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14
#define	GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15
#define	GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
#define	GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
#define	GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
#define	GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
#define	GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
#define	GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
#define	GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
#define	GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
#define	GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
#define	GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
#define	GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
#define	GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
#define	GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
#define	GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
#define	GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
#define	GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
#define	GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
#define	GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
#define	GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
#define	GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
#define	GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
#define	GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
#define	GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
#define	GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
#define	GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
#define	GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
#define	GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
#define	GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
#define	GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
#define	GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
#define	GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
#define	GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
#define	HASH_CR_INIT   ((uint32_t)0x00000004)
#define	HASH_CR_DMAE   ((uint32_t)0x00000008)
#define	HASH_CR_DATATYPE   ((uint32_t)0x00000030)
#define	HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)
#define	HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)
#define	HASH_CR_MODE   ((uint32_t)0x00000040)
#define	HASH_CR_ALGO   ((uint32_t)0x00000080)
#define	HASH_CR_NBW   ((uint32_t)0x00000F00)
#define	HASH_CR_NBW_0   ((uint32_t)0x00000100)
#define	HASH_CR_NBW_1   ((uint32_t)0x00000200)
#define	HASH_CR_NBW_2   ((uint32_t)0x00000400)
#define	HASH_CR_NBW_3   ((uint32_t)0x00000800)
#define	HASH_CR_DINNE   ((uint32_t)0x00001000)
#define	HASH_CR_LKEY   ((uint32_t)0x00010000)
#define	HASH_STR_NBW   ((uint32_t)0x0000001F)
#define	HASH_STR_NBW_0   ((uint32_t)0x00000001)
#define	HASH_STR_NBW_1   ((uint32_t)0x00000002)
#define	HASH_STR_NBW_2   ((uint32_t)0x00000004)
#define	HASH_STR_NBW_3   ((uint32_t)0x00000008)
#define	HASH_STR_NBW_4   ((uint32_t)0x00000010)
#define	HASH_STR_DCAL   ((uint32_t)0x00000100)
#define	HASH_IMR_DINIM   ((uint32_t)0x00000001)
#define	HASH_IMR_DCIM   ((uint32_t)0x00000002)
#define	HASH_SR_DINIS   ((uint32_t)0x00000001)
#define	HASH_SR_DCIS   ((uint32_t)0x00000002)
#define	HASH_SR_DMAS   ((uint32_t)0x00000004)
#define	HASH_SR_BUSY   ((uint32_t)0x00000008)
#define	I2C_CR1_PE   ((uint16_t)0x0001)
#define	I2C_CR1_SMBUS   ((uint16_t)0x0002)
#define	I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
#define	I2C_CR1_ENARP   ((uint16_t)0x0010)
#define	I2C_CR1_ENPEC   ((uint16_t)0x0020)
#define	I2C_CR1_ENGC   ((uint16_t)0x0040)
#define	I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
#define	I2C_CR1_START   ((uint16_t)0x0100)
#define	I2C_CR1_STOP   ((uint16_t)0x0200)
#define	I2C_CR1_ACK   ((uint16_t)0x0400)
#define	I2C_CR1_POS   ((uint16_t)0x0800)
#define	I2C_CR1_PEC   ((uint16_t)0x1000)
#define	I2C_CR1_ALERT   ((uint16_t)0x2000)
#define	I2C_CR1_SWRST   ((uint16_t)0x8000)
#define	I2C_CR2_FREQ   ((uint16_t)0x003F)
#define	I2C_CR2_FREQ_0   ((uint16_t)0x0001)
#define	I2C_CR2_FREQ_1   ((uint16_t)0x0002)
#define	I2C_CR2_FREQ_2   ((uint16_t)0x0004)
#define	I2C_CR2_FREQ_3   ((uint16_t)0x0008)
#define	I2C_CR2_FREQ_4   ((uint16_t)0x0010)
#define	I2C_CR2_FREQ_5   ((uint16_t)0x0020)
#define	I2C_CR2_ITERREN   ((uint16_t)0x0100)
#define	I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
#define	I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
#define	I2C_CR2_DMAEN   ((uint16_t)0x0800)
#define	I2C_CR2_LAST   ((uint16_t)0x1000)
#define	I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
#define	I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
#define	I2C_OAR1_ADD0   ((uint16_t)0x0001)
#define	I2C_OAR1_ADD1   ((uint16_t)0x0002)
#define	I2C_OAR1_ADD2   ((uint16_t)0x0004)
#define	I2C_OAR1_ADD3   ((uint16_t)0x0008)
#define	I2C_OAR1_ADD4   ((uint16_t)0x0010)
#define	I2C_OAR1_ADD5   ((uint16_t)0x0020)
#define	I2C_OAR1_ADD6   ((uint16_t)0x0040)
#define	I2C_OAR1_ADD7   ((uint16_t)0x0080)
#define	I2C_OAR1_ADD8   ((uint16_t)0x0100)
#define	I2C_OAR1_ADD9   ((uint16_t)0x0200)
#define	I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
#define	I2C_OAR2_ENDUAL   ((uint8_t)0x01)
#define	I2C_OAR2_ADD2   ((uint8_t)0xFE)
#define	I2C_DR_DR   ((uint8_t)0xFF)
#define	I2C_SR1_SB   ((uint16_t)0x0001)
#define	I2C_SR1_ADDR   ((uint16_t)0x0002)
#define	I2C_SR1_BTF   ((uint16_t)0x0004)
#define	I2C_SR1_ADD10   ((uint16_t)0x0008)
#define	I2C_SR1_STOPF   ((uint16_t)0x0010)
#define	I2C_SR1_RXNE   ((uint16_t)0x0040)
#define	I2C_SR1_TXE   ((uint16_t)0x0080)
#define	I2C_SR1_BERR   ((uint16_t)0x0100)
#define	I2C_SR1_ARLO   ((uint16_t)0x0200)
#define	I2C_SR1_AF   ((uint16_t)0x0400)
#define	I2C_SR1_OVR   ((uint16_t)0x0800)
#define	I2C_SR1_PECERR   ((uint16_t)0x1000)
#define	I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
#define	I2C_SR1_SMBALERT   ((uint16_t)0x8000)
#define	I2C_SR2_MSL   ((uint16_t)0x0001)
#define	I2C_SR2_BUSY   ((uint16_t)0x0002)
#define	I2C_SR2_TRA   ((uint16_t)0x0004)
#define	I2C_SR2_GENCALL   ((uint16_t)0x0010)
#define	I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
#define	I2C_SR2_SMBHOST   ((uint16_t)0x0040)
#define	I2C_SR2_DUALF   ((uint16_t)0x0080)
#define	I2C_SR2_PEC   ((uint16_t)0xFF00)
#define	I2C_CCR_CCR   ((uint16_t)0x0FFF)
#define	I2C_CCR_DUTY   ((uint16_t)0x4000)
#define	I2C_CCR_FS   ((uint16_t)0x8000)
#define	I2C_TRISE_TRISE   ((uint8_t)0x3F)
#define	IWDG_KR_KEY   ((uint16_t)0xFFFF)
#define	IWDG_PR_PR   ((uint8_t)0x07)
#define	IWDG_PR_PR_0   ((uint8_t)0x01)
#define	IWDG_PR_PR_1   ((uint8_t)0x02)
#define	IWDG_PR_PR_2   ((uint8_t)0x04)
#define	IWDG_RLR_RL   ((uint16_t)0x0FFF)
#define	IWDG_SR_PVU   ((uint8_t)0x01)
#define	IWDG_SR_RVU   ((uint8_t)0x02)
#define	PWR_CR_LPDS   ((uint16_t)0x0001)
#define	PWR_CR_PDDS   ((uint16_t)0x0002)
#define	PWR_CR_CWUF   ((uint16_t)0x0004)
#define	PWR_CR_CSBF   ((uint16_t)0x0008)
#define	PWR_CR_PVDE   ((uint16_t)0x0010)
#define	PWR_CR_PLS   ((uint16_t)0x00E0)
#define	PWR_CR_PLS_0   ((uint16_t)0x0020)
#define	PWR_CR_PLS_1   ((uint16_t)0x0040)
#define	PWR_CR_PLS_2   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV0   ((uint16_t)0x0000)
#define	PWR_CR_PLS_LEV1   ((uint16_t)0x0020)
#define	PWR_CR_PLS_LEV2   ((uint16_t)0x0040)
#define	PWR_CR_PLS_LEV3   ((uint16_t)0x0060)
#define	PWR_CR_PLS_LEV4   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)
#define	PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)
#define	PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)
#define	PWR_CR_DBP   ((uint16_t)0x0100)
#define	PWR_CR_FPDS   ((uint16_t)0x0200)
#define	PWR_CR_VOS   ((uint16_t)0x4000)
#define	PWR_CR_PMODE   PWR_CR_VOS
#define	PWR_CSR_WUF   ((uint16_t)0x0001)
#define	PWR_CSR_SBF   ((uint16_t)0x0002)
#define	PWR_CSR_PVDO   ((uint16_t)0x0004)
#define	PWR_CSR_BRR   ((uint16_t)0x0008)
#define	PWR_CSR_EWUP   ((uint16_t)0x0100)
#define	PWR_CSR_BRE   ((uint16_t)0x0200)
#define	PWR_CSR_VOSRDY   ((uint16_t)0x4000)
#define	PWR_CSR_REGRDY   PWR_CSR_VOSRDY
#define	RCC_CR_HSION   ((uint32_t)0x00000001)
#define	RCC_CR_HSIRDY   ((uint32_t)0x00000002)
#define	RCC_CR_HSITRIM   ((uint32_t)0x000000F8)
#define	RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)
#define	RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)
#define	RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)
#define	RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)
#define	RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)
#define	RCC_CR_HSICAL   ((uint32_t)0x0000FF00)
#define	RCC_CR_HSICAL_0   ((uint32_t)0x00000100)
#define	RCC_CR_HSICAL_1   ((uint32_t)0x00000200)
#define	RCC_CR_HSICAL_2   ((uint32_t)0x00000400)
#define	RCC_CR_HSICAL_3   ((uint32_t)0x00000800)
#define	RCC_CR_HSICAL_4   ((uint32_t)0x00001000)
#define	RCC_CR_HSICAL_5   ((uint32_t)0x00002000)
#define	RCC_CR_HSICAL_6   ((uint32_t)0x00004000)
#define	RCC_CR_HSICAL_7   ((uint32_t)0x00008000)
#define	RCC_CR_HSEON   ((uint32_t)0x00010000)
#define	RCC_CR_HSERDY   ((uint32_t)0x00020000)
#define	RCC_CR_HSEBYP   ((uint32_t)0x00040000)
#define	RCC_CR_CSSON   ((uint32_t)0x00080000)
#define	RCC_CR_PLLON   ((uint32_t)0x01000000)
#define	RCC_CR_PLLRDY   ((uint32_t)0x02000000)
#define	RCC_CR_PLLI2SON   ((uint32_t)0x04000000)
#define	RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)
#define	RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)
#define	RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)
#define	RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)
#define	RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)
#define	RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)
#define	RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)
#define	RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)
#define	RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)
#define	RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)
#define	RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)
#define	RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)
#define	RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)
#define	RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)
#define	RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)
#define	RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)
#define	RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)
#define	RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)
#define	RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)
#define	RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)
#define	RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)
#define	RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)
#define	RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)
#define	RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
#define	RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)
#define	RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)
#define	RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)
#define	RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)
#define	RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)
#define	RCC_CFGR_SW   ((uint32_t)0x00000003)
#define	RCC_CFGR_SW_0   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_1   ((uint32_t)0x00000002)
#define	RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)
#define	RCC_CFGR_SWS   ((uint32_t)0x0000000C)
#define	RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
#define	RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)
#define	RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
#define	RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
#define	RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
#define	RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
#define	RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
#define	RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
#define	RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
#define	RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
#define	RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
#define	RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
#define	RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
#define	RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)
#define	RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)
#define	RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)
#define	RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)
#define	RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)
#define	RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)
#define	RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)
#define	RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)
#define	RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)
#define	RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)
#define	RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)
#define	RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)
#define	RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)
#define	RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)
#define	RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)
#define	RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)
#define	RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)
#define	RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)
#define	RCC_CFGR_MCO1   ((uint32_t)0x00600000)
#define	RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)
#define	RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)
#define	RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)
#define	RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)
#define	RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)
#define	RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)
#define	RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)
#define	RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)
#define	RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)
#define	RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)
#define	RCC_CFGR_MCO2   ((uint32_t)0xC0000000)
#define	RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)
#define	RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)
#define	RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
#define	RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
#define	RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
#define	RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
#define	RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
#define	RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)
#define	RCC_CIR_CSSF   ((uint32_t)0x00000080)
#define	RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
#define	RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
#define	RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
#define	RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
#define	RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
#define	RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)
#define	RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
#define	RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
#define	RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
#define	RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
#define	RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
#define	RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)
#define	RCC_CIR_CSSC   ((uint32_t)0x00800000)
#define	RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)
#define	RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)
#define	RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)
#define	RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)
#define	RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)
#define	RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)
#define	RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)
#define	RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)
#define	RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)
#define	RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)
#define	RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)
#define	RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)
#define	RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)
#define	RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)
#define	RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)
#define	RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)
#define	RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)
#define	RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)
#define	RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)
#define	RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
#define	RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
#define	RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
#define	RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
#define	RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
#define	RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)
#define	RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)
#define	RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)
#define	RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)
#define	RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)
#define	RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
#define	RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
#define	RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
#define	RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
#define	RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
#define	RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
#define	RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)
#define	RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)
#define	RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)
#define	RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
#define	RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
#define	RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)
#define	RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)
#define	RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)
#define	RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)
#define	RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)
#define	RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
#define	RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
#define	RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)
#define	RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)
#define	RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)
#define	RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)
#define	RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST
#define	RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)
#define	RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)
#define	RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)
#define	RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)
#define	RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)
#define	RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)
#define	RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)
#define	RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)
#define	RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)
#define	RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)
#define	RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)
#define	RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)
#define	RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)
#define	RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)
#define	RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)
#define	RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)
#define	RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)
#define	RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)
#define	RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)
#define	RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)
#define	RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)
#define	RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)
#define	RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)
#define	RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)
#define	RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)
#define	RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
#define	RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
#define	RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
#define	RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
#define	RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
#define	RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)
#define	RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)
#define	RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)
#define	RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
#define	RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
#define	RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
#define	RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
#define	RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
#define	RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
#define	RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
#define	RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
#define	RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)
#define	RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)
#define	RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)
#define	RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
#define	RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
#define	RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)
#define	RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)
#define	RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)
#define	RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)
#define	RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)
#define	RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)
#define	RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)
#define	RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
#define	RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
#define	RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)
#define	RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)
#define	RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)
#define	RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)
#define	RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)
#define	RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)
#define	RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)
#define	RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)
#define	RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)
#define	RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)
#define	RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)
#define	RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)
#define	RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)
#define	RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)
#define	RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)
#define	RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)
#define	RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)
#define	RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)
#define	RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)
#define	RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)
#define	RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)
#define	RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)
#define	RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)
#define	RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)
#define	RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)
#define	RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)
#define	RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)
#define	RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)
#define	RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)
#define	RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)
#define	RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)
#define	RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)
#define	RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
#define	RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
#define	RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
#define	RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
#define	RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
#define	RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
#define	RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)
#define	RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)
#define	RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)
#define	RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
#define	RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
#define	RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
#define	RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
#define	RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
#define	RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
#define	RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
#define	RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
#define	RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
#define	RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)
#define	RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)
#define	RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)
#define	RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
#define	RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
#define	RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)
#define	RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)
#define	RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)
#define	RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)
#define	RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)
#define	RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)
#define	RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)
#define	RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
#define	RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
#define	RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)
#define	RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)
#define	RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)
#define	RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)
#define	RCC_BDCR_LSEON   ((uint32_t)0x00000001)
#define	RCC_BDCR_LSERDY   ((uint32_t)0x00000002)
#define	RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)
#define	RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)
#define	RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)
#define	RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)
#define	RCC_BDCR_RTCEN   ((uint32_t)0x00008000)
#define	RCC_BDCR_BDRST   ((uint32_t)0x00010000)
#define	RCC_CSR_LSION   ((uint32_t)0x00000001)
#define	RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
#define	RCC_CSR_RMVF   ((uint32_t)0x01000000)
#define	RCC_CSR_BORRSTF   ((uint32_t)0x02000000)
#define	RCC_CSR_PADRSTF   ((uint32_t)0x04000000)
#define	RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
#define	RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
#define	RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)
#define	RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
#define	RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
#define	RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)
#define	RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)
#define	RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)
#define	RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)
#define	RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)
#define	RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)
#define	RNG_CR_RNGEN   ((uint32_t)0x00000004)
#define	RNG_CR_IE   ((uint32_t)0x00000008)
#define	RNG_SR_DRDY   ((uint32_t)0x00000001)
#define	RNG_SR_CECS   ((uint32_t)0x00000002)
#define	RNG_SR_SECS   ((uint32_t)0x00000004)
#define	RNG_SR_CEIS   ((uint32_t)0x00000020)
#define	RNG_SR_SEIS   ((uint32_t)0x00000040)
#define	RTC_TR_PM   ((uint32_t)0x00400000)
#define	RTC_TR_HT   ((uint32_t)0x00300000)
#define	RTC_TR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TR_HU   ((uint32_t)0x000F0000)
#define	RTC_TR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TR_MNT   ((uint32_t)0x00007000)
#define	RTC_TR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TR_ST   ((uint32_t)0x00000070)
#define	RTC_TR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TR_SU   ((uint32_t)0x0000000F)
#define	RTC_TR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TR_SU_3   ((uint32_t)0x00000008)
#define	RTC_DR_YT   ((uint32_t)0x00F00000)
#define	RTC_DR_YT_0   ((uint32_t)0x00100000)
#define	RTC_DR_YT_1   ((uint32_t)0x00200000)
#define	RTC_DR_YT_2   ((uint32_t)0x00400000)
#define	RTC_DR_YT_3   ((uint32_t)0x00800000)
#define	RTC_DR_YU   ((uint32_t)0x000F0000)
#define	RTC_DR_YU_0   ((uint32_t)0x00010000)
#define	RTC_DR_YU_1   ((uint32_t)0x00020000)
#define	RTC_DR_YU_2   ((uint32_t)0x00040000)
#define	RTC_DR_YU_3   ((uint32_t)0x00080000)
#define	RTC_DR_WDU   ((uint32_t)0x0000E000)
#define	RTC_DR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_DR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_DR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_DR_MT   ((uint32_t)0x00001000)
#define	RTC_DR_MU   ((uint32_t)0x00000F00)
#define	RTC_DR_MU_0   ((uint32_t)0x00000100)
#define	RTC_DR_MU_1   ((uint32_t)0x00000200)
#define	RTC_DR_MU_2   ((uint32_t)0x00000400)
#define	RTC_DR_MU_3   ((uint32_t)0x00000800)
#define	RTC_DR_DT   ((uint32_t)0x00000030)
#define	RTC_DR_DT_0   ((uint32_t)0x00000010)
#define	RTC_DR_DT_1   ((uint32_t)0x00000020)
#define	RTC_DR_DU   ((uint32_t)0x0000000F)
#define	RTC_DR_DU_0   ((uint32_t)0x00000001)
#define	RTC_DR_DU_1   ((uint32_t)0x00000002)
#define	RTC_DR_DU_2   ((uint32_t)0x00000004)
#define	RTC_DR_DU_3   ((uint32_t)0x00000008)
#define	RTC_CR_COE   ((uint32_t)0x00800000)
#define	RTC_CR_OSEL   ((uint32_t)0x00600000)
#define	RTC_CR_OSEL_0   ((uint32_t)0x00200000)
#define	RTC_CR_OSEL_1   ((uint32_t)0x00400000)
#define	RTC_CR_POL   ((uint32_t)0x00100000)
#define	RTC_CR_COSEL   ((uint32_t)0x00080000)
#define	RTC_CR_BCK   ((uint32_t)0x00040000)
#define	RTC_CR_SUB1H   ((uint32_t)0x00020000)
#define	RTC_CR_ADD1H   ((uint32_t)0x00010000)
#define	RTC_CR_TSIE   ((uint32_t)0x00008000)
#define	RTC_CR_WUTIE   ((uint32_t)0x00004000)
#define	RTC_CR_ALRBIE   ((uint32_t)0x00002000)
#define	RTC_CR_ALRAIE   ((uint32_t)0x00001000)
#define	RTC_CR_TSE   ((uint32_t)0x00000800)
#define	RTC_CR_WUTE   ((uint32_t)0x00000400)
#define	RTC_CR_ALRBE   ((uint32_t)0x00000200)
#define	RTC_CR_ALRAE   ((uint32_t)0x00000100)
#define	RTC_CR_DCE   ((uint32_t)0x00000080)
#define	RTC_CR_FMT   ((uint32_t)0x00000040)
#define	RTC_CR_BYPSHAD   ((uint32_t)0x00000020)
#define	RTC_CR_REFCKON   ((uint32_t)0x00000010)
#define	RTC_CR_TSEDGE   ((uint32_t)0x00000008)
#define	RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
#define	RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
#define	RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
#define	RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
#define	RTC_ISR_RECALPF   ((uint32_t)0x00010000)
#define	RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
#define	RTC_ISR_TSOVF   ((uint32_t)0x00001000)
#define	RTC_ISR_TSF   ((uint32_t)0x00000800)
#define	RTC_ISR_WUTF   ((uint32_t)0x00000400)
#define	RTC_ISR_ALRBF   ((uint32_t)0x00000200)
#define	RTC_ISR_ALRAF   ((uint32_t)0x00000100)
#define	RTC_ISR_INIT   ((uint32_t)0x00000080)
#define	RTC_ISR_INITF   ((uint32_t)0x00000040)
#define	RTC_ISR_RSF   ((uint32_t)0x00000020)
#define	RTC_ISR_INITS   ((uint32_t)0x00000010)
#define	RTC_ISR_SHPF   ((uint32_t)0x00000008)
#define	RTC_ISR_WUTWF   ((uint32_t)0x00000004)
#define	RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
#define	RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
#define	RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
#define	RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)
#define	RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
#define	RTC_CALIBR_DCS   ((uint32_t)0x00000080)
#define	RTC_CALIBR_DC   ((uint32_t)0x0000001F)
#define	RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMAR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMAR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMAR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMAR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
#define	RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMBR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMBR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMBR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMBR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
#define	RTC_WPR_KEY   ((uint32_t)0x000000FF)
#define	RTC_SSR_SS   ((uint32_t)0x0000FFFF)
#define	RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)
#define	RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)
#define	RTC_TSTR_PM   ((uint32_t)0x00400000)
#define	RTC_TSTR_HT   ((uint32_t)0x00300000)
#define	RTC_TSTR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TSTR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TSTR_HU   ((uint32_t)0x000F0000)
#define	RTC_TSTR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TSTR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TSTR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TSTR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TSTR_MNT   ((uint32_t)0x00007000)
#define	RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TSTR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TSTR_ST   ((uint32_t)0x00000070)
#define	RTC_TSTR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TSTR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TSTR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TSTR_SU   ((uint32_t)0x0000000F)
#define	RTC_TSTR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TSTR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TSTR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TSTR_SU_3   ((uint32_t)0x00000008)
#define	RTC_TSDR_WDU   ((uint32_t)0x0000E000)
#define	RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_TSDR_MT   ((uint32_t)0x00001000)
#define	RTC_TSDR_MU   ((uint32_t)0x00000F00)
#define	RTC_TSDR_MU_0   ((uint32_t)0x00000100)
#define	RTC_TSDR_MU_1   ((uint32_t)0x00000200)
#define	RTC_TSDR_MU_2   ((uint32_t)0x00000400)
#define	RTC_TSDR_MU_3   ((uint32_t)0x00000800)
#define	RTC_TSDR_DT   ((uint32_t)0x00000030)
#define	RTC_TSDR_DT_0   ((uint32_t)0x00000010)
#define	RTC_TSDR_DT_1   ((uint32_t)0x00000020)
#define	RTC_TSDR_DU   ((uint32_t)0x0000000F)
#define	RTC_TSDR_DU_0   ((uint32_t)0x00000001)
#define	RTC_TSDR_DU_1   ((uint32_t)0x00000002)
#define	RTC_TSDR_DU_2   ((uint32_t)0x00000004)
#define	RTC_TSDR_DU_3   ((uint32_t)0x00000008)
#define	RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)
#define	RTC_CALR_CALP   ((uint32_t)0x00008000)
#define	RTC_CALR_CALW8   ((uint32_t)0x00004000)
#define	RTC_CALR_CALW16   ((uint32_t)0x00002000)
#define	RTC_CALR_CALM   ((uint32_t)0x000001FF)
#define	RTC_CALR_CALM_0   ((uint32_t)0x00000001)
#define	RTC_CALR_CALM_1   ((uint32_t)0x00000002)
#define	RTC_CALR_CALM_2   ((uint32_t)0x00000004)
#define	RTC_CALR_CALM_3   ((uint32_t)0x00000008)
#define	RTC_CALR_CALM_4   ((uint32_t)0x00000010)
#define	RTC_CALR_CALM_5   ((uint32_t)0x00000020)
#define	RTC_CALR_CALM_6   ((uint32_t)0x00000040)
#define	RTC_CALR_CALM_7   ((uint32_t)0x00000080)
#define	RTC_CALR_CALM_8   ((uint32_t)0x00000100)
#define	RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
#define	RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)
#define	RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)
#define	RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)
#define	RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)
#define	RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)
#define	RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)
#define	RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)
#define	RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)
#define	RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)
#define	RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)
#define	RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)
#define	RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)
#define	RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)
#define	RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)
#define	RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
#define	RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
#define	RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
#define	RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)
#define	RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)
#define	RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)
#define	RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)
#define	RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)
#define	RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)
#define	RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)
#define	RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)
#define	RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)
#define	RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)
#define	RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)
#define	RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)
#define	RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
#define	SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
#define	SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
#define	SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
#define	SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
#define	SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
#define	SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
#define	SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
#define	SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
#define	SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
#define	SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
#define	SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
#define	SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
#define	SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
#define	SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
#define	SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
#define	SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
#define	SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
#define	SDIO_CMD_WAITINT   ((uint16_t)0x0100)
#define	SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
#define	SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
#define	SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
#define	SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
#define	SDIO_CMD_NIEN   ((uint16_t)0x2000)
#define	SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
#define	SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
#define	SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
#define	SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
#define	SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
#define	SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
#define	SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
#define	SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
#define	SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
#define	SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
#define	SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
#define	SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
#define	SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
#define	SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
#define	SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
#define	SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
#define	SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
#define	SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
#define	SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
#define	SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
#define	SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
#define	SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
#define	SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
#define	SDIO_STA_CMDREND   ((uint32_t)0x00000040)
#define	SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
#define	SDIO_STA_DATAEND   ((uint32_t)0x00000100)
#define	SDIO_STA_STBITERR   ((uint32_t)0x00000200)
#define	SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
#define	SDIO_STA_CMDACT   ((uint32_t)0x00000800)
#define	SDIO_STA_TXACT   ((uint32_t)0x00001000)
#define	SDIO_STA_RXACT   ((uint32_t)0x00002000)
#define	SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
#define	SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
#define	SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
#define	SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
#define	SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
#define	SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
#define	SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
#define	SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
#define	SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
#define	SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
#define	SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
#define	SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
#define	SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
#define	SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
#define	SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
#define	SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
#define	SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
#define	SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
#define	SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
#define	SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
#define	SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
#define	SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
#define	SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
#define	SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
#define	SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
#define	SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
#define	SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
#define	SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
#define	SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
#define	SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
#define	SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
#define	SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
#define	SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
#define	SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
#define	SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
#define	SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
#define	SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
#define	SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
#define	SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
#define	SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
#define	SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
#define	SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
#define	SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
#define	SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
#define	SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
#define	SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
#define	SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
#define	SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
#define	SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
#define	SPI_CR1_CPHA   ((uint16_t)0x0001)
#define	SPI_CR1_CPOL   ((uint16_t)0x0002)
#define	SPI_CR1_MSTR   ((uint16_t)0x0004)
#define	SPI_CR1_BR   ((uint16_t)0x0038)
#define	SPI_CR1_BR_0   ((uint16_t)0x0008)
#define	SPI_CR1_BR_1   ((uint16_t)0x0010)
#define	SPI_CR1_BR_2   ((uint16_t)0x0020)
#define	SPI_CR1_SPE   ((uint16_t)0x0040)
#define	SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
#define	SPI_CR1_SSI   ((uint16_t)0x0100)
#define	SPI_CR1_SSM   ((uint16_t)0x0200)
#define	SPI_CR1_RXONLY   ((uint16_t)0x0400)
#define	SPI_CR1_DFF   ((uint16_t)0x0800)
#define	SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
#define	SPI_CR1_CRCEN   ((uint16_t)0x2000)
#define	SPI_CR1_BIDIOE   ((uint16_t)0x4000)
#define	SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
#define	SPI_CR2_RXDMAEN   ((uint8_t)0x01)
#define	SPI_CR2_TXDMAEN   ((uint8_t)0x02)
#define	SPI_CR2_SSOE   ((uint8_t)0x04)
#define	SPI_CR2_ERRIE   ((uint8_t)0x20)
#define	SPI_CR2_RXNEIE   ((uint8_t)0x40)
#define	SPI_CR2_TXEIE   ((uint8_t)0x80)
#define	SPI_SR_RXNE   ((uint8_t)0x01)
#define	SPI_SR_TXE   ((uint8_t)0x02)
#define	SPI_SR_CHSIDE   ((uint8_t)0x04)
#define	SPI_SR_UDR   ((uint8_t)0x08)
#define	SPI_SR_CRCERR   ((uint8_t)0x10)
#define	SPI_SR_MODF   ((uint8_t)0x20)
#define	SPI_SR_OVR   ((uint8_t)0x40)
#define	SPI_SR_BSY   ((uint8_t)0x80)
#define	SPI_DR_DR   ((uint16_t)0xFFFF)
#define	SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
#define	SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
#define	SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
#define	SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
#define	SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
#define	SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
#define	SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
#define	SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
#define	SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
#define	SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
#define	SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
#define	SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
#define	SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
#define	SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
#define	SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
#define	SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
#define	SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
#define	SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
#define	SPI_I2SPR_ODD   ((uint16_t)0x0100)
#define	SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
#define	SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)
#define	SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
#define	SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
#define	SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)
#define	SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL
#define	SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
	EXTI0 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
	EXTI1 configuration.
#define	SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
	EXTI2 configuration.
#define	SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
	EXTI3 configuration.
#define	SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
	EXTI4 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
	EXTI5 configuration.
#define	SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
	EXTI6 configuration.
#define	SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
	EXTI7 configuration.
#define	SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
	EXTI8 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)
#define	SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
	EXTI9 configuration.
#define	SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)
#define	SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
	EXTI10 configuration.
#define	SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)
#define	SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
	EXTI11 configuration.
#define	SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)
#define	SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
	EXTI12 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
	EXTI13 configuration.
#define	SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
	EXTI14 configuration.
#define	SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
	EXTI15 configuration.
#define	SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)
#define	SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)
#define	SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)
#define	SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)
#define	TIM_CR1_CEN   ((uint16_t)0x0001)
#define	TIM_CR1_UDIS   ((uint16_t)0x0002)
#define	TIM_CR1_URS   ((uint16_t)0x0004)
#define	TIM_CR1_OPM   ((uint16_t)0x0008)
#define	TIM_CR1_DIR   ((uint16_t)0x0010)
#define	TIM_CR1_CMS   ((uint16_t)0x0060)
#define	TIM_CR1_CMS_0   ((uint16_t)0x0020)
#define	TIM_CR1_CMS_1   ((uint16_t)0x0040)
#define	TIM_CR1_ARPE   ((uint16_t)0x0080)
#define	TIM_CR1_CKD   ((uint16_t)0x0300)
#define	TIM_CR1_CKD_0   ((uint16_t)0x0100)
#define	TIM_CR1_CKD_1   ((uint16_t)0x0200)
#define	TIM_CR2_CCPC   ((uint16_t)0x0001)
#define	TIM_CR2_CCUS   ((uint16_t)0x0004)
#define	TIM_CR2_CCDS   ((uint16_t)0x0008)
#define	TIM_CR2_MMS   ((uint16_t)0x0070)
#define	TIM_CR2_MMS_0   ((uint16_t)0x0010)
#define	TIM_CR2_MMS_1   ((uint16_t)0x0020)
#define	TIM_CR2_MMS_2   ((uint16_t)0x0040)
#define	TIM_CR2_TI1S   ((uint16_t)0x0080)
#define	TIM_CR2_OIS1   ((uint16_t)0x0100)
#define	TIM_CR2_OIS1N   ((uint16_t)0x0200)
#define	TIM_CR2_OIS2   ((uint16_t)0x0400)
#define	TIM_CR2_OIS2N   ((uint16_t)0x0800)
#define	TIM_CR2_OIS3   ((uint16_t)0x1000)
#define	TIM_CR2_OIS3N   ((uint16_t)0x2000)
#define	TIM_CR2_OIS4   ((uint16_t)0x4000)
#define	TIM_SMCR_SMS   ((uint16_t)0x0007)
#define	TIM_SMCR_SMS_0   ((uint16_t)0x0001)
#define	TIM_SMCR_SMS_1   ((uint16_t)0x0002)
#define	TIM_SMCR_SMS_2   ((uint16_t)0x0004)
#define	TIM_SMCR_TS   ((uint16_t)0x0070)
#define	TIM_SMCR_TS_0   ((uint16_t)0x0010)
#define	TIM_SMCR_TS_1   ((uint16_t)0x0020)
#define	TIM_SMCR_TS_2   ((uint16_t)0x0040)
#define	TIM_SMCR_MSM   ((uint16_t)0x0080)
#define	TIM_SMCR_ETF   ((uint16_t)0x0F00)
#define	TIM_SMCR_ETF_0   ((uint16_t)0x0100)
#define	TIM_SMCR_ETF_1   ((uint16_t)0x0200)
#define	TIM_SMCR_ETF_2   ((uint16_t)0x0400)
#define	TIM_SMCR_ETF_3   ((uint16_t)0x0800)
#define	TIM_SMCR_ETPS   ((uint16_t)0x3000)
#define	TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
#define	TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
#define	TIM_SMCR_ECE   ((uint16_t)0x4000)
#define	TIM_SMCR_ETP   ((uint16_t)0x8000)
#define	TIM_DIER_UIE   ((uint16_t)0x0001)
#define	TIM_DIER_CC1IE   ((uint16_t)0x0002)
#define	TIM_DIER_CC2IE   ((uint16_t)0x0004)
#define	TIM_DIER_CC3IE   ((uint16_t)0x0008)
#define	TIM_DIER_CC4IE   ((uint16_t)0x0010)
#define	TIM_DIER_COMIE   ((uint16_t)0x0020)
#define	TIM_DIER_TIE   ((uint16_t)0x0040)
#define	TIM_DIER_BIE   ((uint16_t)0x0080)
#define	TIM_DIER_UDE   ((uint16_t)0x0100)
#define	TIM_DIER_CC1DE   ((uint16_t)0x0200)
#define	TIM_DIER_CC2DE   ((uint16_t)0x0400)
#define	TIM_DIER_CC3DE   ((uint16_t)0x0800)
#define	TIM_DIER_CC4DE   ((uint16_t)0x1000)
#define	TIM_DIER_COMDE   ((uint16_t)0x2000)
#define	TIM_DIER_TDE   ((uint16_t)0x4000)
#define	TIM_SR_UIF   ((uint16_t)0x0001)
#define	TIM_SR_CC1IF   ((uint16_t)0x0002)
#define	TIM_SR_CC2IF   ((uint16_t)0x0004)
#define	TIM_SR_CC3IF   ((uint16_t)0x0008)
#define	TIM_SR_CC4IF   ((uint16_t)0x0010)
#define	TIM_SR_COMIF   ((uint16_t)0x0020)
#define	TIM_SR_TIF   ((uint16_t)0x0040)
#define	TIM_SR_BIF   ((uint16_t)0x0080)
#define	TIM_SR_CC1OF   ((uint16_t)0x0200)
#define	TIM_SR_CC2OF   ((uint16_t)0x0400)
#define	TIM_SR_CC3OF   ((uint16_t)0x0800)
#define	TIM_SR_CC4OF   ((uint16_t)0x1000)
#define	TIM_EGR_UG   ((uint8_t)0x01)
#define	TIM_EGR_CC1G   ((uint8_t)0x02)
#define	TIM_EGR_CC2G   ((uint8_t)0x04)
#define	TIM_EGR_CC3G   ((uint8_t)0x08)
#define	TIM_EGR_CC4G   ((uint8_t)0x10)
#define	TIM_EGR_COMG   ((uint8_t)0x20)
#define	TIM_EGR_TG   ((uint8_t)0x40)
#define	TIM_EGR_BG   ((uint8_t)0x80)
#define	TIM_CCMR1_CC1S   ((uint16_t)0x0003)
#define	TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
#define	TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
#define	TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
#define	TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
#define	TIM_CCMR1_OC1M   ((uint16_t)0x0070)
#define	TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
#define	TIM_CCMR1_CC2S   ((uint16_t)0x0300)
#define	TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
#define	TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
#define	TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
#define	TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
#define	TIM_CCMR1_OC2M   ((uint16_t)0x7000)
#define	TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
#define	TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
#define	TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
#define	TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
#define	TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR1_IC2F   ((uint16_t)0xF000)
#define	TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
#define	TIM_CCMR2_CC3S   ((uint16_t)0x0003)
#define	TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
#define	TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
#define	TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
#define	TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
#define	TIM_CCMR2_OC3M   ((uint16_t)0x0070)
#define	TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
#define	TIM_CCMR2_CC4S   ((uint16_t)0x0300)
#define	TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
#define	TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
#define	TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
#define	TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
#define	TIM_CCMR2_OC4M   ((uint16_t)0x7000)
#define	TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
#define	TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
#define	TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
#define	TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
#define	TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR2_IC4F   ((uint16_t)0xF000)
#define	TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
#define	TIM_CCER_CC1E   ((uint16_t)0x0001)
#define	TIM_CCER_CC1P   ((uint16_t)0x0002)
#define	TIM_CCER_CC1NE   ((uint16_t)0x0004)
#define	TIM_CCER_CC1NP   ((uint16_t)0x0008)
#define	TIM_CCER_CC2E   ((uint16_t)0x0010)
#define	TIM_CCER_CC2P   ((uint16_t)0x0020)
#define	TIM_CCER_CC2NE   ((uint16_t)0x0040)
#define	TIM_CCER_CC2NP   ((uint16_t)0x0080)
#define	TIM_CCER_CC3E   ((uint16_t)0x0100)
#define	TIM_CCER_CC3P   ((uint16_t)0x0200)
#define	TIM_CCER_CC3NE   ((uint16_t)0x0400)
#define	TIM_CCER_CC3NP   ((uint16_t)0x0800)
#define	TIM_CCER_CC4E   ((uint16_t)0x1000)
#define	TIM_CCER_CC4P   ((uint16_t)0x2000)
#define	TIM_CCER_CC4NP   ((uint16_t)0x8000)
#define	TIM_CNT_CNT   ((uint16_t)0xFFFF)
#define	TIM_PSC_PSC   ((uint16_t)0xFFFF)
#define	TIM_ARR_ARR   ((uint16_t)0xFFFF)
#define	TIM_RCR_REP   ((uint8_t)0xFF)
#define	TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
#define	TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
#define	TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
#define	TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
#define	TIM_BDTR_DTG   ((uint16_t)0x00FF)
#define	TIM_BDTR_DTG_0   ((uint16_t)0x0001)
#define	TIM_BDTR_DTG_1   ((uint16_t)0x0002)
#define	TIM_BDTR_DTG_2   ((uint16_t)0x0004)
#define	TIM_BDTR_DTG_3   ((uint16_t)0x0008)
#define	TIM_BDTR_DTG_4   ((uint16_t)0x0010)
#define	TIM_BDTR_DTG_5   ((uint16_t)0x0020)
#define	TIM_BDTR_DTG_6   ((uint16_t)0x0040)
#define	TIM_BDTR_DTG_7   ((uint16_t)0x0080)
#define	TIM_BDTR_LOCK   ((uint16_t)0x0300)
#define	TIM_BDTR_LOCK_0   ((uint16_t)0x0100)
#define	TIM_BDTR_LOCK_1   ((uint16_t)0x0200)
#define	TIM_BDTR_OSSI   ((uint16_t)0x0400)
#define	TIM_BDTR_OSSR   ((uint16_t)0x0800)
#define	TIM_BDTR_BKE   ((uint16_t)0x1000)
#define	TIM_BDTR_BKP   ((uint16_t)0x2000)
#define	TIM_BDTR_AOE   ((uint16_t)0x4000)
#define	TIM_BDTR_MOE   ((uint16_t)0x8000)
#define	TIM_DCR_DBA   ((uint16_t)0x001F)
#define	TIM_DCR_DBA_0   ((uint16_t)0x0001)
#define	TIM_DCR_DBA_1   ((uint16_t)0x0002)
#define	TIM_DCR_DBA_2   ((uint16_t)0x0004)
#define	TIM_DCR_DBA_3   ((uint16_t)0x0008)
#define	TIM_DCR_DBA_4   ((uint16_t)0x0010)
#define	TIM_DCR_DBL   ((uint16_t)0x1F00)
#define	TIM_DCR_DBL_0   ((uint16_t)0x0100)
#define	TIM_DCR_DBL_1   ((uint16_t)0x0200)
#define	TIM_DCR_DBL_2   ((uint16_t)0x0400)
#define	TIM_DCR_DBL_3   ((uint16_t)0x0800)
#define	TIM_DCR_DBL_4   ((uint16_t)0x1000)
#define	TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
#define	TIM_OR_TI4_RMP   ((uint16_t)0x00C0)
#define	TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)
#define	TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)
#define	TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)
#define	TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)
#define	TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)
#define	USART_SR_PE   ((uint16_t)0x0001)
#define	USART_SR_FE   ((uint16_t)0x0002)
#define	USART_SR_NE   ((uint16_t)0x0004)
#define	USART_SR_ORE   ((uint16_t)0x0008)
#define	USART_SR_IDLE   ((uint16_t)0x0010)
#define	USART_SR_RXNE   ((uint16_t)0x0020)
#define	USART_SR_TC   ((uint16_t)0x0040)
#define	USART_SR_TXE   ((uint16_t)0x0080)
#define	USART_SR_LBD   ((uint16_t)0x0100)
#define	USART_SR_CTS   ((uint16_t)0x0200)
#define	USART_DR_DR   ((uint16_t)0x01FF)
#define	USART_BRR_DIV_Fraction   ((uint16_t)0x000F)
#define	USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)
#define	USART_CR1_SBK   ((uint16_t)0x0001)
#define	USART_CR1_RWU   ((uint16_t)0x0002)
#define	USART_CR1_RE   ((uint16_t)0x0004)
#define	USART_CR1_TE   ((uint16_t)0x0008)
#define	USART_CR1_IDLEIE   ((uint16_t)0x0010)
#define	USART_CR1_RXNEIE   ((uint16_t)0x0020)
#define	USART_CR1_TCIE   ((uint16_t)0x0040)
#define	USART_CR1_TXEIE   ((uint16_t)0x0080)
#define	USART_CR1_PEIE   ((uint16_t)0x0100)
#define	USART_CR1_PS   ((uint16_t)0x0200)
#define	USART_CR1_PCE   ((uint16_t)0x0400)
#define	USART_CR1_WAKE   ((uint16_t)0x0800)
#define	USART_CR1_M   ((uint16_t)0x1000)
#define	USART_CR1_UE   ((uint16_t)0x2000)
#define	USART_CR1_OVER8   ((uint16_t)0x8000)
#define	USART_CR2_ADD   ((uint16_t)0x000F)
#define	USART_CR2_LBDL   ((uint16_t)0x0020)
#define	USART_CR2_LBDIE   ((uint16_t)0x0040)
#define	USART_CR2_LBCL   ((uint16_t)0x0100)
#define	USART_CR2_CPHA   ((uint16_t)0x0200)
#define	USART_CR2_CPOL   ((uint16_t)0x0400)
#define	USART_CR2_CLKEN   ((uint16_t)0x0800)
#define	USART_CR2_STOP   ((uint16_t)0x3000)
#define	USART_CR2_STOP_0   ((uint16_t)0x1000)
#define	USART_CR2_STOP_1   ((uint16_t)0x2000)
#define	USART_CR2_LINEN   ((uint16_t)0x4000)
#define	USART_CR3_EIE   ((uint16_t)0x0001)
#define	USART_CR3_IREN   ((uint16_t)0x0002)
#define	USART_CR3_IRLP   ((uint16_t)0x0004)
#define	USART_CR3_HDSEL   ((uint16_t)0x0008)
#define	USART_CR3_NACK   ((uint16_t)0x0010)
#define	USART_CR3_SCEN   ((uint16_t)0x0020)
#define	USART_CR3_DMAR   ((uint16_t)0x0040)
#define	USART_CR3_DMAT   ((uint16_t)0x0080)
#define	USART_CR3_RTSE   ((uint16_t)0x0100)
#define	USART_CR3_CTSE   ((uint16_t)0x0200)
#define	USART_CR3_CTSIE   ((uint16_t)0x0400)
#define	USART_CR3_ONEBIT   ((uint16_t)0x0800)
#define	USART_GTPR_PSC   ((uint16_t)0x00FF)
#define	USART_GTPR_PSC_0   ((uint16_t)0x0001)
#define	USART_GTPR_PSC_1   ((uint16_t)0x0002)
#define	USART_GTPR_PSC_2   ((uint16_t)0x0004)
#define	USART_GTPR_PSC_3   ((uint16_t)0x0008)
#define	USART_GTPR_PSC_4   ((uint16_t)0x0010)
#define	USART_GTPR_PSC_5   ((uint16_t)0x0020)
#define	USART_GTPR_PSC_6   ((uint16_t)0x0040)
#define	USART_GTPR_PSC_7   ((uint16_t)0x0080)
#define	USART_GTPR_GT   ((uint16_t)0xFF00)
#define	WWDG_CR_T   ((uint8_t)0x7F)
#define	WWDG_CR_T0   ((uint8_t)0x01)
#define	WWDG_CR_T1   ((uint8_t)0x02)
#define	WWDG_CR_T2   ((uint8_t)0x04)
#define	WWDG_CR_T3   ((uint8_t)0x08)
#define	WWDG_CR_T4   ((uint8_t)0x10)
#define	WWDG_CR_T5   ((uint8_t)0x20)
#define	WWDG_CR_T6   ((uint8_t)0x40)
#define	WWDG_CR_WDGA   ((uint8_t)0x80)
#define	WWDG_CFR_W   ((uint16_t)0x007F)
#define	WWDG_CFR_W0   ((uint16_t)0x0001)
#define	WWDG_CFR_W1   ((uint16_t)0x0002)
#define	WWDG_CFR_W2   ((uint16_t)0x0004)
#define	WWDG_CFR_W3   ((uint16_t)0x0008)
#define	WWDG_CFR_W4   ((uint16_t)0x0010)
#define	WWDG_CFR_W5   ((uint16_t)0x0020)
#define	WWDG_CFR_W6   ((uint16_t)0x0040)
#define	WWDG_CFR_WDGTB   ((uint16_t)0x0180)
#define	WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
#define	WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
#define	WWDG_CFR_EWI   ((uint16_t)0x0200)
#define	WWDG_SR_EWIF   ((uint8_t)0x01)
#define	DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
#define	DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
#define	DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
#define	DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
#define	DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
#define	DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
#define	DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
#define	DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
#define	DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)
#define	DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)
#define	DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
#define	DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)
#define	DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)
#define	DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)
#define	DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP
#define	DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)
#define	DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)
#define	DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)
#define	DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)
#define	ETH_MACCR_WD   ((uint32_t)0x00800000)
#define	ETH_MACCR_JD   ((uint32_t)0x00400000)
#define	ETH_MACCR_IFG   ((uint32_t)0x000E0000)
#define	ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000)
#define	ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000)
#define	ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000)
#define	ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000)
#define	ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000)
#define	ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000)
#define	ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000)
#define	ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000)
#define	ETH_MACCR_CSD   ((uint32_t)0x00010000)
#define	ETH_MACCR_FES   ((uint32_t)0x00004000)
#define	ETH_MACCR_ROD   ((uint32_t)0x00002000)
#define	ETH_MACCR_LM   ((uint32_t)0x00001000)
#define	ETH_MACCR_DM   ((uint32_t)0x00000800)
#define	ETH_MACCR_IPCO   ((uint32_t)0x00000400)
#define	ETH_MACCR_RD   ((uint32_t)0x00000200)
#define	ETH_MACCR_APCS   ((uint32_t)0x00000080)
#define	ETH_MACCR_BL   ((uint32_t)0x00000060)
#define	ETH_MACCR_BL_10   ((uint32_t)0x00000000)
#define	ETH_MACCR_BL_8   ((uint32_t)0x00000020)
#define	ETH_MACCR_BL_4   ((uint32_t)0x00000040)
#define	ETH_MACCR_BL_1   ((uint32_t)0x00000060)
#define	ETH_MACCR_DC   ((uint32_t)0x00000010)
#define	ETH_MACCR_TE   ((uint32_t)0x00000008)
#define	ETH_MACCR_RE   ((uint32_t)0x00000004)
#define	ETH_MACFFR_RA   ((uint32_t)0x80000000)
#define	ETH_MACFFR_HPF   ((uint32_t)0x00000400)
#define	ETH_MACFFR_SAF   ((uint32_t)0x00000200)
#define	ETH_MACFFR_SAIF   ((uint32_t)0x00000100)
#define	ETH_MACFFR_PCF   ((uint32_t)0x000000C0)
#define	ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040)
#define	ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080)
#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0)
#define	ETH_MACFFR_BFD   ((uint32_t)0x00000020)
#define	ETH_MACFFR_PAM   ((uint32_t)0x00000010)
#define	ETH_MACFFR_DAIF   ((uint32_t)0x00000008)
#define	ETH_MACFFR_HM   ((uint32_t)0x00000004)
#define	ETH_MACFFR_HU   ((uint32_t)0x00000002)
#define	ETH_MACFFR_PM   ((uint32_t)0x00000001)
#define	ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)
#define	ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)
#define	ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)
#define	ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)
#define	ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)
#define	ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)
#define	ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)
#define	ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010)
#define	ETH_MACMIIAR_MW   ((uint32_t)0x00000002)
#define	ETH_MACMIIAR_MB   ((uint32_t)0x00000001)
#define	ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)
#define	ETH_MACFCR_PT   ((uint32_t)0xFFFF0000)
#define	ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)
#define	ETH_MACFCR_PLT   ((uint32_t)0x00000030)
#define	ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)
#define	ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010)
#define	ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020)
#define	ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030)
#define	ETH_MACFCR_UPFD   ((uint32_t)0x00000008)
#define	ETH_MACFCR_RFCE   ((uint32_t)0x00000004)
#define	ETH_MACFCR_TFCE   ((uint32_t)0x00000002)
#define	ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001)
#define	ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000)
#define	ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF)
#define	ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000)
#define	ETH_MACPMTCSR_GU   ((uint32_t)0x00000200)
#define	ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040)
#define	ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020)
#define	ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004)
#define	ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002)
#define	ETH_MACPMTCSR_PD   ((uint32_t)0x00000001)
#define	ETH_MACSR_TSTS   ((uint32_t)0x00000200)
#define	ETH_MACSR_MMCTS   ((uint32_t)0x00000040)
#define	ETH_MACSR_MMMCRS   ((uint32_t)0x00000020)
#define	ETH_MACSR_MMCS   ((uint32_t)0x00000010)
#define	ETH_MACSR_PMTS   ((uint32_t)0x00000008)
#define	ETH_MACIMR_TSTIM   ((uint32_t)0x00000200)
#define	ETH_MACIMR_PMTIM   ((uint32_t)0x00000008)
#define	ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA1HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA1HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA1HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA2HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA2HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA2HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MACA3HR_AE   ((uint32_t)0x80000000)
#define	ETH_MACA3HR_SA   ((uint32_t)0x40000000)
#define	ETH_MACA3HR_MBC   ((uint32_t)0x3F000000)
#define	ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000)
#define	ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000)
#define	ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)
#define	ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)
#define	ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000)
#define	ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000)
#define	ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)
#define	ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCCR_MCFHP   ((uint32_t)0x00000020)
#define	ETH_MMCCR_MCP   ((uint32_t)0x00000010)
#define	ETH_MMCCR_MCF   ((uint32_t)0x00000008)
#define	ETH_MMCCR_ROR   ((uint32_t)0x00000004)
#define	ETH_MMCCR_CSR   ((uint32_t)0x00000002)
#define	ETH_MMCCR_CR   ((uint32_t)0x00000001)
#define	ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000)
#define	ETH_MMCRIR_RFAES   ((uint32_t)0x00000040)
#define	ETH_MMCRIR_RFCES   ((uint32_t)0x00000020)
#define	ETH_MMCTIR_TGFS   ((uint32_t)0x00200000)
#define	ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)
#define	ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000)
#define	ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000)
#define	ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040)
#define	ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020)
#define	ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000)
#define	ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000)
#define	ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)
#define	ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF)
#define	ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000)
#define	ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000)
#define	ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000)
#define	ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)
#define	ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)
#define	ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800)
#define	ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400)
#define	ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200)
#define	ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100)
#define	ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020)
#define	ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010)
#define	ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008)
#define	ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004)
#define	ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002)
#define	ETH_PTPTSCR_TSE   ((uint32_t)0x00000001)
#define	ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF)
#define	ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000)
#define	ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF)
#define	ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000)
#define	ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)
#define	ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF)
#define	ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020)
#define	ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010)
#define	ETH_DMABMR_AAB   ((uint32_t)0x02000000)
#define	ETH_DMABMR_FPM   ((uint32_t)0x01000000)
#define	ETH_DMABMR_USP   ((uint32_t)0x00800000)
#define	ETH_DMABMR_RDP   ((uint32_t)0x007E0000)
#define	ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000)
#define	ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000)
#define	ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000)
#define	ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000)
#define	ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)
#define	ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)
#define	ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)
#define	ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)
#define	ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000)
#define	ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000)
#define	ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000)
#define	ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000)
#define	ETH_DMABMR_FB   ((uint32_t)0x00010000)
#define	ETH_DMABMR_RTPR   ((uint32_t)0x0000C000)
#define	ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000)
#define	ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000)
#define	ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000)
#define	ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000)
#define	ETH_DMABMR_PBL   ((uint32_t)0x00003F00)
#define	ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100)
#define	ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200)
#define	ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400)
#define	ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800)
#define	ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)
#define	ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)
#define	ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)
#define	ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)
#define	ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400)
#define	ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800)
#define	ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000)
#define	ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000)
#define	ETH_DMABMR_EDE   ((uint32_t)0x00000080)
#define	ETH_DMABMR_DSL   ((uint32_t)0x0000007C)
#define	ETH_DMABMR_DA   ((uint32_t)0x00000002)
#define	ETH_DMABMR_SR   ((uint32_t)0x00000001)
#define	ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMASR_TSTS   ((uint32_t)0x20000000)
#define	ETH_DMASR_PMTS   ((uint32_t)0x10000000)
#define	ETH_DMASR_MMCS   ((uint32_t)0x08000000)
#define	ETH_DMASR_EBS   ((uint32_t)0x03800000)
#define	ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000)
#define	ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000)
#define	ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000)
#define	ETH_DMASR_TPS   ((uint32_t)0x00700000)
#define	ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000)
#define	ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000)
#define	ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000)
#define	ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000)
#define	ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000)
#define	ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000)
#define	ETH_DMASR_RPS   ((uint32_t)0x000E0000)
#define	ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000)
#define	ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000)
#define	ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000)
#define	ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000)
#define	ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000)
#define	ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000)
#define	ETH_DMASR_NIS   ((uint32_t)0x00010000)
#define	ETH_DMASR_AIS   ((uint32_t)0x00008000)
#define	ETH_DMASR_ERS   ((uint32_t)0x00004000)
#define	ETH_DMASR_FBES   ((uint32_t)0x00002000)
#define	ETH_DMASR_ETS   ((uint32_t)0x00000400)
#define	ETH_DMASR_RWTS   ((uint32_t)0x00000200)
#define	ETH_DMASR_RPSS   ((uint32_t)0x00000100)
#define	ETH_DMASR_RBUS   ((uint32_t)0x00000080)
#define	ETH_DMASR_RS   ((uint32_t)0x00000040)
#define	ETH_DMASR_TUS   ((uint32_t)0x00000020)
#define	ETH_DMASR_ROS   ((uint32_t)0x00000010)
#define	ETH_DMASR_TJTS   ((uint32_t)0x00000008)
#define	ETH_DMASR_TBUS   ((uint32_t)0x00000004)
#define	ETH_DMASR_TPSS   ((uint32_t)0x00000002)
#define	ETH_DMASR_TS   ((uint32_t)0x00000001)
#define	ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000)
#define	ETH_DMAOMR_RSF   ((uint32_t)0x02000000)
#define	ETH_DMAOMR_DFRF   ((uint32_t)0x01000000)
#define	ETH_DMAOMR_TSF   ((uint32_t)0x00200000)
#define	ETH_DMAOMR_FTF   ((uint32_t)0x00100000)
#define	ETH_DMAOMR_TTC   ((uint32_t)0x0001C000)
#define	ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000)
#define	ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000)
#define	ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000)
#define	ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000)
#define	ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000)
#define	ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000)
#define	ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000)
#define	ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000)
#define	ETH_DMAOMR_ST   ((uint32_t)0x00002000)
#define	ETH_DMAOMR_FEF   ((uint32_t)0x00000080)
#define	ETH_DMAOMR_FUGF   ((uint32_t)0x00000040)
#define	ETH_DMAOMR_RTC   ((uint32_t)0x00000018)
#define	ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000)
#define	ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008)
#define	ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010)
#define	ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018)
#define	ETH_DMAOMR_OSF   ((uint32_t)0x00000004)
#define	ETH_DMAOMR_SR   ((uint32_t)0x00000002)
#define	ETH_DMAIER_NISE   ((uint32_t)0x00010000)
#define	ETH_DMAIER_AISE   ((uint32_t)0x00008000)
#define	ETH_DMAIER_ERIE   ((uint32_t)0x00004000)
#define	ETH_DMAIER_FBEIE   ((uint32_t)0x00002000)
#define	ETH_DMAIER_ETIE   ((uint32_t)0x00000400)
#define	ETH_DMAIER_RWTIE   ((uint32_t)0x00000200)
#define	ETH_DMAIER_RPSIE   ((uint32_t)0x00000100)
#define	ETH_DMAIER_RBUIE   ((uint32_t)0x00000080)
#define	ETH_DMAIER_RIE   ((uint32_t)0x00000040)
#define	ETH_DMAIER_TUIE   ((uint32_t)0x00000020)
#define	ETH_DMAIER_ROIE   ((uint32_t)0x00000010)
#define	ETH_DMAIER_TJTIE   ((uint32_t)0x00000008)
#define	ETH_DMAIER_TBUIE   ((uint32_t)0x00000004)
#define	ETH_DMAIER_TPSIE   ((uint32_t)0x00000002)
#define	ETH_DMAIER_TIE   ((uint32_t)0x00000001)
#define	ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)
#define	ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000)
#define	ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)
#define	ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF)
#define	ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF)
#define	ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF)
#define	ADC_SR_AWD   ((uint32_t)0x00000001)
#define	ADC_SR_EOC   ((uint32_t)0x00000002)
#define	ADC_SR_JEOC   ((uint32_t)0x00000004)
#define	ADC_SR_JSTRT   ((uint32_t)0x00000008)
#define	ADC_SR_STRT   ((uint32_t)0x00000010)
#define	ADC_SR_OVR   ((uint32_t)0x00000020)
#define	ADC_SR_ADONS   ((uint32_t)0x00000040)
#define	ADC_SR_RCNR   ((uint32_t)0x00000100)
#define	ADC_SR_JCNR   ((uint32_t)0x00000200)
#define	ADC_CR1_AWDCH   ((uint32_t)0x0000001F)
#define	ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)
#define	ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)
#define	ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)
#define	ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)
#define	ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)
#define	ADC_CR1_EOCIE   ((uint32_t)0x00000020)
#define	ADC_CR1_AWDIE   ((uint32_t)0x00000040)
#define	ADC_CR1_JEOCIE   ((uint32_t)0x00000080)
#define	ADC_CR1_SCAN   ((uint32_t)0x00000100)
#define	ADC_CR1_AWDSGL   ((uint32_t)0x00000200)
#define	ADC_CR1_JAUTO   ((uint32_t)0x00000400)
#define	ADC_CR1_DISCEN   ((uint32_t)0x00000800)
#define	ADC_CR1_JDISCEN   ((uint32_t)0x00001000)
#define	ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)
#define	ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)
#define	ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)
#define	ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)
#define	ADC_CR1_PDD   ((uint32_t)0x00010000)
#define	ADC_CR1_PDI   ((uint32_t)0x00020000)
#define	ADC_CR1_JAWDEN   ((uint32_t)0x00400000)
#define	ADC_CR1_AWDEN   ((uint32_t)0x00800000)
#define	ADC_CR1_RES   ((uint32_t)0x03000000)
#define	ADC_CR1_RES_0   ((uint32_t)0x01000000)
#define	ADC_CR1_RES_1   ((uint32_t)0x02000000)
#define	ADC_CR1_OVRIE   ((uint32_t)0x04000000)
#define	ADC_CR2_ADON   ((uint32_t)0x00000001)
#define	ADC_CR2_CONT   ((uint32_t)0x00000002)
#define	ADC_CR2_CFG   ((uint32_t)0x00000004)
#define	ADC_CR2_DELS   ((uint32_t)0x00000070)
#define	ADC_CR2_DELS_0   ((uint32_t)0x00000010)
#define	ADC_CR2_DELS_1   ((uint32_t)0x00000020)
#define	ADC_CR2_DELS_2   ((uint32_t)0x00000040)
#define	ADC_CR2_DMA   ((uint32_t)0x00000100)
#define	ADC_CR2_DDS   ((uint32_t)0x00000200)
#define	ADC_CR2_EOCS   ((uint32_t)0x00000400)
#define	ADC_CR2_ALIGN   ((uint32_t)0x00000800)
#define	ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)
#define	ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)
#define	ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)
#define	ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)
#define	ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)
#define	ADC_CR2_JEXTEN   ((uint32_t)0x00300000)
#define	ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)
#define	ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)
#define	ADC_CR2_JSWSTART   ((uint32_t)0x00400000)
#define	ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)
#define	ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)
#define	ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)
#define	ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)
#define	ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)
#define	ADC_CR2_EXTEN   ((uint32_t)0x30000000)
#define	ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)
#define	ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)
#define	ADC_CR2_SWSTART   ((uint32_t)0x40000000)
#define	ADC_SMPR1_SMP20   ((uint32_t)0x00000007)
#define	ADC_SMPR1_SMP20_0   ((uint32_t)0x00000001)
#define	ADC_SMPR1_SMP20_1   ((uint32_t)0x00000002)
#define	ADC_SMPR1_SMP20_2   ((uint32_t)0x00000004)
#define	ADC_SMPR1_SMP21   ((uint32_t)0x00000038)
#define	ADC_SMPR1_SMP21_0   ((uint32_t)0x00000008)
#define	ADC_SMPR1_SMP21_1   ((uint32_t)0x00000010)
#define	ADC_SMPR1_SMP21_2   ((uint32_t)0x00000020)
#define	ADC_SMPR1_SMP22   ((uint32_t)0x000001C0)
#define	ADC_SMPR1_SMP22_0   ((uint32_t)0x00000040)
#define	ADC_SMPR1_SMP22_1   ((uint32_t)0x00000080)
#define	ADC_SMPR1_SMP22_2   ((uint32_t)0x00000100)
#define	ADC_SMPR1_SMP23   ((uint32_t)0x00000E00)
#define	ADC_SMPR1_SMP23_0   ((uint32_t)0x00000200)
#define	ADC_SMPR1_SMP23_1   ((uint32_t)0x00000400)
#define	ADC_SMPR1_SMP23_2   ((uint32_t)0x00000800)
#define	ADC_SMPR1_SMP24   ((uint32_t)0x00007000)
#define	ADC_SMPR1_SMP24_0   ((uint32_t)0x00001000)
#define	ADC_SMPR1_SMP24_1   ((uint32_t)0x00002000)
#define	ADC_SMPR1_SMP24_2   ((uint32_t)0x00004000)
#define	ADC_SMPR1_SMP25   ((uint32_t)0x00038000)
#define	ADC_SMPR1_SMP25_0   ((uint32_t)0x00008000)
#define	ADC_SMPR1_SMP25_1   ((uint32_t)0x00010000)
#define	ADC_SMPR1_SMP25_2   ((uint32_t)0x00020000)
#define	ADC_SMPR1_SMP26   ((uint32_t)0x001C0000)
#define	ADC_SMPR1_SMP26_0   ((uint32_t)0x00040000)
#define	ADC_SMPR1_SMP26_1   ((uint32_t)0x00080000)
#define	ADC_SMPR1_SMP26_2   ((uint32_t)0x00100000)
#define	ADC_SMPR1_SMP27   ((uint32_t)0x00E00000)
#define	ADC_SMPR1_SMP27_0   ((uint32_t)0x00200000)
#define	ADC_SMPR1_SMP27_1   ((uint32_t)0x00400000)
#define	ADC_SMPR1_SMP27_2   ((uint32_t)0x00800000)
#define	ADC_SMPR1_SMP28   ((uint32_t)0x07000000)
#define	ADC_SMPR1_SMP28_0   ((uint32_t)0x01000000)
#define	ADC_SMPR1_SMP28_1   ((uint32_t)0x02000000)
#define	ADC_SMPR1_SMP28_2   ((uint32_t)0x04000000)
#define	ADC_SMPR1_SMP29   ((uint32_t)0x38000000)
#define	ADC_SMPR1_SMP29_0   ((uint32_t)0x08000000)
#define	ADC_SMPR1_SMP29_1   ((uint32_t)0x10000000)
#define	ADC_SMPR1_SMP29_2   ((uint32_t)0x20000000)
#define	ADC_SMPR2_SMP10   ((uint32_t)0x00000007)
#define	ADC_SMPR2_SMP10_0   ((uint32_t)0x00000001)
#define	ADC_SMPR2_SMP10_1   ((uint32_t)0x00000002)
#define	ADC_SMPR2_SMP10_2   ((uint32_t)0x00000004)
#define	ADC_SMPR2_SMP11   ((uint32_t)0x00000038)
#define	ADC_SMPR2_SMP11_0   ((uint32_t)0x00000008)
#define	ADC_SMPR2_SMP11_1   ((uint32_t)0x00000010)
#define	ADC_SMPR2_SMP11_2   ((uint32_t)0x00000020)
#define	ADC_SMPR2_SMP12   ((uint32_t)0x000001C0)
#define	ADC_SMPR2_SMP12_0   ((uint32_t)0x00000040)
#define	ADC_SMPR2_SMP12_1   ((uint32_t)0x00000080)
#define	ADC_SMPR2_SMP12_2   ((uint32_t)0x00000100)
#define	ADC_SMPR2_SMP13   ((uint32_t)0x00000E00)
#define	ADC_SMPR2_SMP13_0   ((uint32_t)0x00000200)
#define	ADC_SMPR2_SMP13_1   ((uint32_t)0x00000400)
#define	ADC_SMPR2_SMP13_2   ((uint32_t)0x00000800)
#define	ADC_SMPR2_SMP14   ((uint32_t)0x00007000)
#define	ADC_SMPR2_SMP14_0   ((uint32_t)0x00001000)
#define	ADC_SMPR2_SMP14_1   ((uint32_t)0x00002000)
#define	ADC_SMPR2_SMP14_2   ((uint32_t)0x00004000)
#define	ADC_SMPR2_SMP15   ((uint32_t)0x00038000)
#define	ADC_SMPR2_SMP15_0   ((uint32_t)0x00008000)
#define	ADC_SMPR2_SMP15_1   ((uint32_t)0x00010000)
#define	ADC_SMPR2_SMP15_2   ((uint32_t)0x00020000)
#define	ADC_SMPR2_SMP16   ((uint32_t)0x001C0000)
#define	ADC_SMPR2_SMP16_0   ((uint32_t)0x00040000)
#define	ADC_SMPR2_SMP16_1   ((uint32_t)0x00080000)
#define	ADC_SMPR2_SMP16_2   ((uint32_t)0x00100000)
#define	ADC_SMPR2_SMP17   ((uint32_t)0x00E00000)
#define	ADC_SMPR2_SMP17_0   ((uint32_t)0x00200000)
#define	ADC_SMPR2_SMP17_1   ((uint32_t)0x00400000)
#define	ADC_SMPR2_SMP17_2   ((uint32_t)0x00800000)
#define	ADC_SMPR2_SMP18   ((uint32_t)0x07000000)
#define	ADC_SMPR2_SMP18_0   ((uint32_t)0x01000000)
#define	ADC_SMPR2_SMP18_1   ((uint32_t)0x02000000)
#define	ADC_SMPR2_SMP18_2   ((uint32_t)0x04000000)
#define	ADC_SMPR2_SMP19   ((uint32_t)0x38000000)
#define	ADC_SMPR2_SMP19_0   ((uint32_t)0x08000000)
#define	ADC_SMPR2_SMP19_1   ((uint32_t)0x10000000)
#define	ADC_SMPR2_SMP19_2   ((uint32_t)0x20000000)
#define	ADC_SMPR3_SMP0   ((uint32_t)0x00000007)
#define	ADC_SMPR3_SMP0_0   ((uint32_t)0x00000001)
#define	ADC_SMPR3_SMP0_1   ((uint32_t)0x00000002)
#define	ADC_SMPR3_SMP0_2   ((uint32_t)0x00000004)
#define	ADC_SMPR3_SMP1   ((uint32_t)0x00000038)
#define	ADC_SMPR3_SMP1_0   ((uint32_t)0x00000008)
#define	ADC_SMPR3_SMP1_1   ((uint32_t)0x00000010)
#define	ADC_SMPR3_SMP1_2   ((uint32_t)0x00000020)
#define	ADC_SMPR3_SMP2   ((uint32_t)0x000001C0)
#define	ADC_SMPR3_SMP2_0   ((uint32_t)0x00000040)
#define	ADC_SMPR3_SMP2_1   ((uint32_t)0x00000080)
#define	ADC_SMPR3_SMP2_2   ((uint32_t)0x00000100)
#define	ADC_SMPR3_SMP3   ((uint32_t)0x00000E00)
#define	ADC_SMPR3_SMP3_0   ((uint32_t)0x00000200)
#define	ADC_SMPR3_SMP3_1   ((uint32_t)0x00000400)
#define	ADC_SMPR3_SMP3_2   ((uint32_t)0x00000800)
#define	ADC_SMPR3_SMP4   ((uint32_t)0x00007000)
#define	ADC_SMPR3_SMP4_0   ((uint32_t)0x00001000)
#define	ADC_SMPR3_SMP4_1   ((uint32_t)0x00002000)
#define	ADC_SMPR3_SMP4_2   ((uint32_t)0x00004000)
#define	ADC_SMPR3_SMP5   ((uint32_t)0x00038000)
#define	ADC_SMPR3_SMP5_0   ((uint32_t)0x00008000)
#define	ADC_SMPR3_SMP5_1   ((uint32_t)0x00010000)
#define	ADC_SMPR3_SMP5_2   ((uint32_t)0x00020000)
#define	ADC_SMPR3_SMP6   ((uint32_t)0x001C0000)
#define	ADC_SMPR3_SMP6_0   ((uint32_t)0x00040000)
#define	ADC_SMPR3_SMP6_1   ((uint32_t)0x00080000)
#define	ADC_SMPR3_SMP6_2   ((uint32_t)0x00100000)
#define	ADC_SMPR3_SMP7   ((uint32_t)0x00E00000)
#define	ADC_SMPR3_SMP7_0   ((uint32_t)0x00200000)
#define	ADC_SMPR3_SMP7_1   ((uint32_t)0x00400000)
#define	ADC_SMPR3_SMP7_2   ((uint32_t)0x00800000)
#define	ADC_SMPR3_SMP8   ((uint32_t)0x07000000)
#define	ADC_SMPR3_SMP8_0   ((uint32_t)0x01000000)
#define	ADC_SMPR3_SMP8_1   ((uint32_t)0x02000000)
#define	ADC_SMPR3_SMP8_2   ((uint32_t)0x04000000)
#define	ADC_SMPR3_SMP9   ((uint32_t)0x38000000)
#define	ADC_SMPR3_SMP9_0   ((uint32_t)0x08000000)
#define	ADC_SMPR3_SMP9_1   ((uint32_t)0x10000000)
#define	ADC_SMPR3_SMP9_2   ((uint32_t)0x20000000)
#define	ADC_JOFR1_JOFFSET1   ((uint32_t)0x00000FFF)
#define	ADC_JOFR2_JOFFSET2   ((uint32_t)0x00000FFF)
#define	ADC_JOFR3_JOFFSET3   ((uint32_t)0x00000FFF)
#define	ADC_JOFR4_JOFFSET4   ((uint32_t)0x00000FFF)
#define	ADC_HTR_HT   ((uint32_t)0x00000FFF)
#define	ADC_LTR_LT   ((uint32_t)0x00000FFF)
#define	ADC_SQR1_L   ((uint32_t)0x00F00000)
#define	ADC_SQR1_L_0   ((uint32_t)0x00100000)
#define	ADC_SQR1_L_1   ((uint32_t)0x00200000)
#define	ADC_SQR1_L_2   ((uint32_t)0x00400000)
#define	ADC_SQR1_L_3   ((uint32_t)0x00800000)
#define	ADC_SQR1_SQ28   ((uint32_t)0x000F8000)
#define	ADC_SQR1_SQ28_0   ((uint32_t)0x00008000)
#define	ADC_SQR1_SQ28_1   ((uint32_t)0x00010000)
#define	ADC_SQR1_SQ28_2   ((uint32_t)0x00020000)
#define	ADC_SQR1_SQ28_3   ((uint32_t)0x00040000)
#define	ADC_SQR1_SQ28_4   ((uint32_t)0x00080000)
#define	ADC_SQR1_SQ27   ((uint32_t)0x00007C00)
#define	ADC_SQR1_SQ27_0   ((uint32_t)0x00000400)
#define	ADC_SQR1_SQ27_1   ((uint32_t)0x00000800)
#define	ADC_SQR1_SQ27_2   ((uint32_t)0x00001000)
#define	ADC_SQR1_SQ27_3   ((uint32_t)0x00002000)
#define	ADC_SQR1_SQ27_4   ((uint32_t)0x00004000)
#define	ADC_SQR1_SQ26   ((uint32_t)0x000003E0)
#define	ADC_SQR1_SQ26_0   ((uint32_t)0x00000020)
#define	ADC_SQR1_SQ26_1   ((uint32_t)0x00000040)
#define	ADC_SQR1_SQ26_2   ((uint32_t)0x00000080)
#define	ADC_SQR1_SQ26_3   ((uint32_t)0x00000100)
#define	ADC_SQR1_SQ26_4   ((uint32_t)0x00000200)
#define	ADC_SQR1_SQ25   ((uint32_t)0x0000001F)
#define	ADC_SQR1_SQ25_0   ((uint32_t)0x00000001)
#define	ADC_SQR1_SQ25_1   ((uint32_t)0x00000002)
#define	ADC_SQR1_SQ25_2   ((uint32_t)0x00000004)
#define	ADC_SQR1_SQ25_3   ((uint32_t)0x00000008)
#define	ADC_SQR1_SQ25_4   ((uint32_t)0x00000010)
#define	ADC_SQR2_SQ19   ((uint32_t)0x0000001F)
#define	ADC_SQR2_SQ19_0   ((uint32_t)0x00000001)
#define	ADC_SQR2_SQ19_1   ((uint32_t)0x00000002)
#define	ADC_SQR2_SQ19_2   ((uint32_t)0x00000004)
#define	ADC_SQR2_SQ19_3   ((uint32_t)0x00000008)
#define	ADC_SQR2_SQ19_4   ((uint32_t)0x00000010)
#define	ADC_SQR2_SQ20   ((uint32_t)0x000003E0)
#define	ADC_SQR2_SQ20_0   ((uint32_t)0x00000020)
#define	ADC_SQR2_SQ20_1   ((uint32_t)0x00000040)
#define	ADC_SQR2_SQ20_2   ((uint32_t)0x00000080)
#define	ADC_SQR2_SQ20_3   ((uint32_t)0x00000100)
#define	ADC_SQR2_SQ20_4   ((uint32_t)0x00000200)
#define	ADC_SQR2_SQ21   ((uint32_t)0x00007C00)
#define	ADC_SQR2_SQ21_0   ((uint32_t)0x00000400)
#define	ADC_SQR2_SQ21_1   ((uint32_t)0x00000800)
#define	ADC_SQR2_SQ21_2   ((uint32_t)0x00001000)
#define	ADC_SQR2_SQ21_3   ((uint32_t)0x00002000)
#define	ADC_SQR2_SQ21_4   ((uint32_t)0x00004000)
#define	ADC_SQR2_SQ22   ((uint32_t)0x000F8000)
#define	ADC_SQR2_SQ22_0   ((uint32_t)0x00008000)
#define	ADC_SQR2_SQ22_1   ((uint32_t)0x00010000)
#define	ADC_SQR2_SQ22_2   ((uint32_t)0x00020000)
#define	ADC_SQR2_SQ22_3   ((uint32_t)0x00040000)
#define	ADC_SQR2_SQ22_4   ((uint32_t)0x00080000)
#define	ADC_SQR2_SQ23   ((uint32_t)0x01F00000)
#define	ADC_SQR2_SQ23_0   ((uint32_t)0x00100000)
#define	ADC_SQR2_SQ23_1   ((uint32_t)0x00200000)
#define	ADC_SQR2_SQ23_2   ((uint32_t)0x00400000)
#define	ADC_SQR2_SQ23_3   ((uint32_t)0x00800000)
#define	ADC_SQR2_SQ23_4   ((uint32_t)0x01000000)
#define	ADC_SQR2_SQ24   ((uint32_t)0x3E000000)
#define	ADC_SQR2_SQ24_0   ((uint32_t)0x02000000)
#define	ADC_SQR2_SQ24_1   ((uint32_t)0x04000000)
#define	ADC_SQR2_SQ24_2   ((uint32_t)0x08000000)
#define	ADC_SQR2_SQ24_3   ((uint32_t)0x10000000)
#define	ADC_SQR2_SQ24_4   ((uint32_t)0x20000000)
#define	ADC_SQR3_SQ13   ((uint32_t)0x0000001F)
#define	ADC_SQR3_SQ13_0   ((uint32_t)0x00000001)
#define	ADC_SQR3_SQ13_1   ((uint32_t)0x00000002)
#define	ADC_SQR3_SQ13_2   ((uint32_t)0x00000004)
#define	ADC_SQR3_SQ13_3   ((uint32_t)0x00000008)
#define	ADC_SQR3_SQ13_4   ((uint32_t)0x00000010)
#define	ADC_SQR3_SQ14   ((uint32_t)0x000003E0)
#define	ADC_SQR3_SQ14_0   ((uint32_t)0x00000020)
#define	ADC_SQR3_SQ14_1   ((uint32_t)0x00000040)
#define	ADC_SQR3_SQ14_2   ((uint32_t)0x00000080)
#define	ADC_SQR3_SQ14_3   ((uint32_t)0x00000100)
#define	ADC_SQR3_SQ14_4   ((uint32_t)0x00000200)
#define	ADC_SQR3_SQ15   ((uint32_t)0x00007C00)
#define	ADC_SQR3_SQ15_0   ((uint32_t)0x00000400)
#define	ADC_SQR3_SQ15_1   ((uint32_t)0x00000800)
#define	ADC_SQR3_SQ15_2   ((uint32_t)0x00001000)
#define	ADC_SQR3_SQ15_3   ((uint32_t)0x00002000)
#define	ADC_SQR3_SQ15_4   ((uint32_t)0x00004000)
#define	ADC_SQR3_SQ16   ((uint32_t)0x000F8000)
#define	ADC_SQR3_SQ16_0   ((uint32_t)0x00008000)
#define	ADC_SQR3_SQ16_1   ((uint32_t)0x00010000)
#define	ADC_SQR3_SQ16_2   ((uint32_t)0x00020000)
#define	ADC_SQR3_SQ16_3   ((uint32_t)0x00040000)
#define	ADC_SQR3_SQ16_4   ((uint32_t)0x00080000)
#define	ADC_SQR3_SQ17   ((uint32_t)0x01F00000)
#define	ADC_SQR3_SQ17_0   ((uint32_t)0x00100000)
#define	ADC_SQR3_SQ17_1   ((uint32_t)0x00200000)
#define	ADC_SQR3_SQ17_2   ((uint32_t)0x00400000)
#define	ADC_SQR3_SQ17_3   ((uint32_t)0x00800000)
#define	ADC_SQR3_SQ17_4   ((uint32_t)0x01000000)
#define	ADC_SQR3_SQ18   ((uint32_t)0x3E000000)
#define	ADC_SQR3_SQ18_0   ((uint32_t)0x02000000)
#define	ADC_SQR3_SQ18_1   ((uint32_t)0x04000000)
#define	ADC_SQR3_SQ18_2   ((uint32_t)0x08000000)
#define	ADC_SQR3_SQ18_3   ((uint32_t)0x10000000)
#define	ADC_SQR3_SQ18_4   ((uint32_t)0x20000000)
#define	ADC_SQR4_SQ7   ((uint32_t)0x0000001F)
#define	ADC_SQR4_SQ7_0   ((uint32_t)0x00000001)
#define	ADC_SQR4_SQ7_1   ((uint32_t)0x00000002)
#define	ADC_SQR4_SQ7_2   ((uint32_t)0x00000004)
#define	ADC_SQR4_SQ7_3   ((uint32_t)0x00000008)
#define	ADC_SQR4_SQ7_4   ((uint32_t)0x00000010)
#define	ADC_SQR4_SQ8   ((uint32_t)0x000003E0)
#define	ADC_SQR4_SQ8_0   ((uint32_t)0x00000020)
#define	ADC_SQR4_SQ8_1   ((uint32_t)0x00000040)
#define	ADC_SQR4_SQ8_2   ((uint32_t)0x00000080)
#define	ADC_SQR4_SQ8_3   ((uint32_t)0x00000100)
#define	ADC_SQR4_SQ8_4   ((uint32_t)0x00000200)
#define	ADC_SQR4_SQ9   ((uint32_t)0x00007C00)
#define	ADC_SQR4_SQ9_0   ((uint32_t)0x00000400)
#define	ADC_SQR4_SQ9_1   ((uint32_t)0x00000800)
#define	ADC_SQR4_SQ9_2   ((uint32_t)0x00001000)
#define	ADC_SQR4_SQ9_3   ((uint32_t)0x00002000)
#define	ADC_SQR4_SQ9_4   ((uint32_t)0x00004000)
#define	ADC_SQR4_SQ10   ((uint32_t)0x000F8000)
#define	ADC_SQR4_SQ10_0   ((uint32_t)0x00008000)
#define	ADC_SQR4_SQ10_1   ((uint32_t)0x00010000)
#define	ADC_SQR4_SQ10_2   ((uint32_t)0x00020000)
#define	ADC_SQR4_SQ10_3   ((uint32_t)0x00040000)
#define	ADC_SQR4_SQ10_4   ((uint32_t)0x00080000)
#define	ADC_SQR4_SQ11   ((uint32_t)0x01F00000)
#define	ADC_SQR4_SQ11_0   ((uint32_t)0x00100000)
#define	ADC_SQR4_SQ11_1   ((uint32_t)0x00200000)
#define	ADC_SQR4_SQ11_2   ((uint32_t)0x00400000)
#define	ADC_SQR4_SQ11_3   ((uint32_t)0x00800000)
#define	ADC_SQR4_SQ11_4   ((uint32_t)0x01000000)
#define	ADC_SQR4_SQ12   ((uint32_t)0x3E000000)
#define	ADC_SQR4_SQ12_0   ((uint32_t)0x02000000)
#define	ADC_SQR4_SQ12_1   ((uint32_t)0x04000000)
#define	ADC_SQR4_SQ12_2   ((uint32_t)0x08000000)
#define	ADC_SQR4_SQ12_3   ((uint32_t)0x10000000)
#define	ADC_SQR4_SQ12_4   ((uint32_t)0x20000000)
#define	ADC_SQR5_SQ1   ((uint32_t)0x0000001F)
#define	ADC_SQR5_SQ1_0   ((uint32_t)0x00000001)
#define	ADC_SQR5_SQ1_1   ((uint32_t)0x00000002)
#define	ADC_SQR5_SQ1_2   ((uint32_t)0x00000004)
#define	ADC_SQR5_SQ1_3   ((uint32_t)0x00000008)
#define	ADC_SQR5_SQ1_4   ((uint32_t)0x00000010)
#define	ADC_SQR5_SQ2   ((uint32_t)0x000003E0)
#define	ADC_SQR5_SQ2_0   ((uint32_t)0x00000020)
#define	ADC_SQR5_SQ2_1   ((uint32_t)0x00000040)
#define	ADC_SQR5_SQ2_2   ((uint32_t)0x00000080)
#define	ADC_SQR5_SQ2_3   ((uint32_t)0x00000100)
#define	ADC_SQR5_SQ2_4   ((uint32_t)0x00000200)
#define	ADC_SQR5_SQ3   ((uint32_t)0x00007C00)
#define	ADC_SQR5_SQ3_0   ((uint32_t)0x00000400)
#define	ADC_SQR5_SQ3_1   ((uint32_t)0x00000800)
#define	ADC_SQR5_SQ3_2   ((uint32_t)0x00001000)
#define	ADC_SQR5_SQ3_3   ((uint32_t)0x00002000)
#define	ADC_SQR5_SQ3_4   ((uint32_t)0x00004000)
#define	ADC_SQR5_SQ4   ((uint32_t)0x000F8000)
#define	ADC_SQR5_SQ4_0   ((uint32_t)0x00008000)
#define	ADC_SQR5_SQ4_1   ((uint32_t)0x00010000)
#define	ADC_SQR5_SQ4_2   ((uint32_t)0x00020000)
#define	ADC_SQR5_SQ4_3   ((uint32_t)0x00040000)
#define	ADC_SQR5_SQ4_4   ((uint32_t)0x00080000)
#define	ADC_SQR5_SQ5   ((uint32_t)0x01F00000)
#define	ADC_SQR5_SQ5_0   ((uint32_t)0x00100000)
#define	ADC_SQR5_SQ5_1   ((uint32_t)0x00200000)
#define	ADC_SQR5_SQ5_2   ((uint32_t)0x00400000)
#define	ADC_SQR5_SQ5_3   ((uint32_t)0x00800000)
#define	ADC_SQR5_SQ5_4   ((uint32_t)0x01000000)
#define	ADC_SQR5_SQ6   ((uint32_t)0x3E000000)
#define	ADC_SQR5_SQ6_0   ((uint32_t)0x02000000)
#define	ADC_SQR5_SQ6_1   ((uint32_t)0x04000000)
#define	ADC_SQR5_SQ6_2   ((uint32_t)0x08000000)
#define	ADC_SQR5_SQ6_3   ((uint32_t)0x10000000)
#define	ADC_SQR5_SQ6_4   ((uint32_t)0x20000000)
#define	ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)
#define	ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)
#define	ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)
#define	ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)
#define	ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)
#define	ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)
#define	ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)
#define	ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)
#define	ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)
#define	ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)
#define	ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)
#define	ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)
#define	ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)
#define	ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)
#define	ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)
#define	ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)
#define	ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)
#define	ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)
#define	ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)
#define	ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)
#define	ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)
#define	ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)
#define	ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)
#define	ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)
#define	ADC_JSQR_JL   ((uint32_t)0x00300000)
#define	ADC_JSQR_JL_0   ((uint32_t)0x00100000)
#define	ADC_JSQR_JL_1   ((uint32_t)0x00200000)
#define	ADC_JDR1_JDATA   ((uint32_t)0x0000FFFF)
#define	ADC_JDR2_JDATA   ((uint32_t)0x0000FFFF)
#define	ADC_JDR3_JDATA   ((uint32_t)0x0000FFFF)
#define	ADC_JDR4_JDATA   ((uint32_t)0x0000FFFF)
#define	ADC_DR_DATA   ((uint32_t)0x0000FFFF)
#define	ADC_SMPR3_SMP30   ((uint32_t)0x00000007)
#define	ADC_SMPR3_SMP30_0   ((uint32_t)0x00000001)
#define	ADC_SMPR3_SMP30_1   ((uint32_t)0x00000002)
#define	ADC_SMPR3_SMP30_2   ((uint32_t)0x00000004)
#define	ADC_SMPR3_SMP31   ((uint32_t)0x00000038)
#define	ADC_SMPR3_SMP31_0   ((uint32_t)0x00000008)
#define	ADC_SMPR3_SMP31_1   ((uint32_t)0x00000010)
#define	ADC_SMPR3_SMP31_2   ((uint32_t)0x00000020)
#define	ADC_CSR_AWD1   ((uint32_t)0x00000001)
#define	ADC_CSR_EOC1   ((uint32_t)0x00000002)
#define	ADC_CSR_JEOC1   ((uint32_t)0x00000004)
#define	ADC_CSR_JSTRT1   ((uint32_t)0x00000008)
#define	ADC_CSR_STRT1   ((uint32_t)0x00000010)
#define	ADC_CSR_OVR1   ((uint32_t)0x00000020)
#define	ADC_CSR_ADONS1   ((uint32_t)0x00000040)
#define	ADC_CCR_ADCPRE   ((uint32_t)0x00030000)
#define	ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)
#define	ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)
#define	ADC_CCR_TSVREFE   ((uint32_t)0x00800000)
#define	AES_CR_EN   ((uint32_t)0x00000001)
#define	AES_CR_DATATYPE   ((uint32_t)0x00000006)
#define	AES_CR_DATATYPE_0   ((uint32_t)0x00000002)
#define	AES_CR_DATATYPE_1   ((uint32_t)0x00000004)
#define	AES_CR_MODE   ((uint32_t)0x00000018)
#define	AES_CR_MODE_0   ((uint32_t)0x00000008)
#define	AES_CR_MODE_1   ((uint32_t)0x00000010)
#define	AES_CR_CHMOD   ((uint32_t)0x00000060)
#define	AES_CR_CHMOD_0   ((uint32_t)0x00000020)
#define	AES_CR_CHMOD_1   ((uint32_t)0x00000040)
#define	AES_CR_CCFC   ((uint32_t)0x00000080)
#define	AES_CR_ERRC   ((uint32_t)0x00000100)
#define	AES_CR_CCIE   ((uint32_t)0x00000200)
#define	AES_CR_ERRIE   ((uint32_t)0x00000400)
#define	AES_CR_DMAINEN   ((uint32_t)0x00000800)
#define	AES_CR_DMAOUTEN   ((uint32_t)0x00001000)
#define	AES_SR_CCF   ((uint32_t)0x00000001)
#define	AES_SR_RDERR   ((uint32_t)0x00000002)
#define	AES_SR_WRERR   ((uint32_t)0x00000004)
#define	AES_DINR   ((uint32_t)0x0000FFFF)
#define	AES_DOUTR   ((uint32_t)0x0000FFFF)
#define	AES_KEYR0   ((uint32_t)0x0000FFFF)
#define	AES_KEYR1   ((uint32_t)0x0000FFFF)
#define	AES_KEYR2   ((uint32_t)0x0000FFFF)
#define	AES_KEYR3   ((uint32_t)0x0000FFFF)
#define	AES_IVR0   ((uint32_t)0x0000FFFF)
#define	AES_IVR1   ((uint32_t)0x0000FFFF)
#define	AES_IVR2   ((uint32_t)0x0000FFFF)
#define	AES_IVR3   ((uint32_t)0x0000FFFF)
#define	COMP_CSR_10KPU   ((uint32_t)0x00000001)
#define	COMP_CSR_400KPU   ((uint32_t)0x00000002)
#define	COMP_CSR_10KPD   ((uint32_t)0x00000004)
#define	COMP_CSR_400KPD   ((uint32_t)0x00000008)
#define	COMP_CSR_CMP1EN   ((uint32_t)0x00000010)
#define	COMP_CSR_SW1   ((uint32_t)0x00000020)
#define	COMP_CSR_CMP1OUT   ((uint32_t)0x00000080)
#define	COMP_CSR_SPEED   ((uint32_t)0x00001000)
#define	COMP_CSR_CMP2OUT   ((uint32_t)0x00002000)
#define	COMP_CSR_VREFOUTEN   ((uint32_t)0x00010000)
#define	COMP_CSR_WNDWE   ((uint32_t)0x00020000)
#define	COMP_CSR_INSEL   ((uint32_t)0x001C0000)
#define	COMP_CSR_INSEL_0   ((uint32_t)0x00040000)
#define	COMP_CSR_INSEL_1   ((uint32_t)0x00080000)
#define	COMP_CSR_INSEL_2   ((uint32_t)0x00100000)
#define	COMP_CSR_OUTSEL   ((uint32_t)0x00E00000)
#define	COMP_CSR_OUTSEL_0   ((uint32_t)0x00200000)
#define	COMP_CSR_OUTSEL_1   ((uint32_t)0x00400000)
#define	COMP_CSR_OUTSEL_2   ((uint32_t)0x00800000)
#define	COMP_CSR_FCH3   ((uint32_t)0x04000000)
#define	COMP_CSR_FCH8   ((uint32_t)0x08000000)
#define	COMP_CSR_RCH13   ((uint32_t)0x10000000)
#define	COMP_CSR_CAIE   ((uint32_t)0x20000000)
#define	COMP_CSR_CAIF   ((uint32_t)0x40000000)
#define	COMP_CSR_TSUSP   ((uint32_t)0x80000000)
#define	OPAMP_CSR_OPA1PD   ((uint32_t)0x00000001)
#define	OPAMP_CSR_S3SEL1   ((uint32_t)0x00000002)
#define	OPAMP_CSR_S4SEL1   ((uint32_t)0x00000004)
#define	OPAMP_CSR_S5SEL1   ((uint32_t)0x00000008)
#define	OPAMP_CSR_S6SEL1   ((uint32_t)0x00000010)
#define	OPAMP_CSR_OPA1CAL_L   ((uint32_t)0x00000020)
#define	OPAMP_CSR_OPA1CAL_H   ((uint32_t)0x00000040)
#define	OPAMP_CSR_OPA1LPM   ((uint32_t)0x00000080)
#define	OPAMP_CSR_OPA2PD   ((uint32_t)0x00000100)
#define	OPAMP_CSR_S3SEL2   ((uint32_t)0x00000200)
#define	OPAMP_CSR_S4SEL2   ((uint32_t)0x00000400)
#define	OPAMP_CSR_S5SEL2   ((uint32_t)0x00000800)
#define	OPAMP_CSR_S6SEL2   ((uint32_t)0x00001000)
#define	OPAMP_CSR_OPA2CAL_L   ((uint32_t)0x00002000)
#define	OPAMP_CSR_OPA2CAL_H   ((uint32_t)0x00004000)
#define	OPAMP_CSR_OPA2LPM   ((uint32_t)0x00008000)
#define	OPAMP_CSR_OPA3PD   ((uint32_t)0x00010000)
#define	OPAMP_CSR_S3SEL3   ((uint32_t)0x00020000)
#define	OPAMP_CSR_S4SEL3   ((uint32_t)0x00040000)
#define	OPAMP_CSR_S5SEL3   ((uint32_t)0x00080000)
#define	OPAMP_CSR_S6SEL3   ((uint32_t)0x00100000)
#define	OPAMP_CSR_OPA3CAL_L   ((uint32_t)0x00200000)
#define	OPAMP_CSR_OPA3CAL_H   ((uint32_t)0x00400000)
#define	OPAMP_CSR_OPA3LPM   ((uint32_t)0x00800000)
#define	OPAMP_CSR_ANAWSEL1   ((uint32_t)0x01000000)
#define	OPAMP_CSR_ANAWSEL2   ((uint32_t)0x02000000)
#define	OPAMP_CSR_ANAWSEL3   ((uint32_t)0x04000000)
#define	OPAMP_CSR_S7SEL2   ((uint32_t)0x08000000)
#define	OPAMP_CSR_AOP_RANGE   ((uint32_t)0x10000000)
#define	OPAMP_CSR_OPA1CALOUT   ((uint32_t)0x20000000)
#define	OPAMP_CSR_OPA2CALOUT   ((uint32_t)0x40000000)
#define	OPAMP_CSR_OPA3CALOUT   ((uint32_t)0x80000000)
#define	OPAMP_OTR_AO1_OPT_OFFSET_TRIM   ((uint32_t)0x000003FF)
#define	OPAMP_OTR_AO2_OPT_OFFSET_TRIM   ((uint32_t)0x000FFC00)
#define	OPAMP_OTR_AO3_OPT_OFFSET_TRIM   ((uint32_t)0x3FF00000)
#define	OPAMP_OTR_OT_USER   ((uint32_t)0x80000000)
#define	OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP   ((uint32_t)0x000003FF)
#define	OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP   ((uint32_t)0x000FFC00)
#define	OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP   ((uint32_t)0x3FF00000)
#define	CRC_DR_DR   ((uint32_t)0xFFFFFFFF)
#define	CRC_IDR_IDR   ((uint8_t)0xFF)
#define	CRC_CR_RESET   ((uint32_t)0x00000001)
#define	DAC_CR_EN1   ((uint32_t)0x00000001)
#define	DAC_CR_BOFF1   ((uint32_t)0x00000002)
#define	DAC_CR_TEN1   ((uint32_t)0x00000004)
#define	DAC_CR_TSEL1   ((uint32_t)0x00000038)
#define	DAC_CR_TSEL1_0   ((uint32_t)0x00000008)
#define	DAC_CR_TSEL1_1   ((uint32_t)0x00000010)
#define	DAC_CR_TSEL1_2   ((uint32_t)0x00000020)
#define	DAC_CR_WAVE1   ((uint32_t)0x000000C0)
#define	DAC_CR_WAVE1_0   ((uint32_t)0x00000040)
#define	DAC_CR_WAVE1_1   ((uint32_t)0x00000080)
#define	DAC_CR_MAMP1   ((uint32_t)0x00000F00)
#define	DAC_CR_MAMP1_0   ((uint32_t)0x00000100)
#define	DAC_CR_MAMP1_1   ((uint32_t)0x00000200)
#define	DAC_CR_MAMP1_2   ((uint32_t)0x00000400)
#define	DAC_CR_MAMP1_3   ((uint32_t)0x00000800)
#define	DAC_CR_DMAEN1   ((uint32_t)0x00001000)
#define	DAC_CR_DMAUDRIE1   ((uint32_t)0x00002000)
#define	DAC_CR_EN2   ((uint32_t)0x00010000)
#define	DAC_CR_BOFF2   ((uint32_t)0x00020000)
#define	DAC_CR_TEN2   ((uint32_t)0x00040000)
#define	DAC_CR_TSEL2   ((uint32_t)0x00380000)
#define	DAC_CR_TSEL2_0   ((uint32_t)0x00080000)
#define	DAC_CR_TSEL2_1   ((uint32_t)0x00100000)
#define	DAC_CR_TSEL2_2   ((uint32_t)0x00200000)
#define	DAC_CR_WAVE2   ((uint32_t)0x00C00000)
#define	DAC_CR_WAVE2_0   ((uint32_t)0x00400000)
#define	DAC_CR_WAVE2_1   ((uint32_t)0x00800000)
#define	DAC_CR_MAMP2   ((uint32_t)0x0F000000)
#define	DAC_CR_MAMP2_0   ((uint32_t)0x01000000)
#define	DAC_CR_MAMP2_1   ((uint32_t)0x02000000)
#define	DAC_CR_MAMP2_2   ((uint32_t)0x04000000)
#define	DAC_CR_MAMP2_3   ((uint32_t)0x08000000)
#define	DAC_CR_DMAEN2   ((uint32_t)0x10000000)
#define	DAC_CR_DMAUDRIE2   ((uint32_t)0x20000000)
#define	DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)
#define	DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)
#define	DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)
#define	DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)
#define	DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)
#define	DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)
#define	DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)
#define	DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)
#define	DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)
#define	DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)
#define	DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)
#define	DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)
#define	DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)
#define	DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)
#define	DAC_SR_DMAUDR1   ((uint32_t)0x00002000)
#define	DAC_SR_DMAUDR2   ((uint32_t)0x20000000)
#define	DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)
#define	DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)
#define	DBGMCU_IDCODE_REV_ID_0   ((uint32_t)0x00010000)
#define	DBGMCU_IDCODE_REV_ID_1   ((uint32_t)0x00020000)
#define	DBGMCU_IDCODE_REV_ID_2   ((uint32_t)0x00040000)
#define	DBGMCU_IDCODE_REV_ID_3   ((uint32_t)0x00080000)
#define	DBGMCU_IDCODE_REV_ID_4   ((uint32_t)0x00100000)
#define	DBGMCU_IDCODE_REV_ID_5   ((uint32_t)0x00200000)
#define	DBGMCU_IDCODE_REV_ID_6   ((uint32_t)0x00400000)
#define	DBGMCU_IDCODE_REV_ID_7   ((uint32_t)0x00800000)
#define	DBGMCU_IDCODE_REV_ID_8   ((uint32_t)0x01000000)
#define	DBGMCU_IDCODE_REV_ID_9   ((uint32_t)0x02000000)
#define	DBGMCU_IDCODE_REV_ID_10   ((uint32_t)0x04000000)
#define	DBGMCU_IDCODE_REV_ID_11   ((uint32_t)0x08000000)
#define	DBGMCU_IDCODE_REV_ID_12   ((uint32_t)0x10000000)
#define	DBGMCU_IDCODE_REV_ID_13   ((uint32_t)0x20000000)
#define	DBGMCU_IDCODE_REV_ID_14   ((uint32_t)0x40000000)
#define	DBGMCU_IDCODE_REV_ID_15   ((uint32_t)0x80000000)
#define	DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)
#define	DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)
#define	DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)
#define	DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)
#define	DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)
#define	DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)
#define	DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)
#define	DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)
#define	DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)
#define	DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)
#define	DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)
#define	DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)
#define	DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)
#define	DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)
#define	DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)
#define	DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)
#define	DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)
#define	DBGMCU_APB2_FZ_DBG_TIM9_STOP   ((uint32_t)0x00000004)
#define	DBGMCU_APB2_FZ_DBG_TIM10_STOP   ((uint32_t)0x00000008)
#define	DBGMCU_APB2_FZ_DBG_TIM11_STOP   ((uint32_t)0x00000010)
#define	DMA_ISR_GIF1   ((uint32_t)0x00000001)
#define	DMA_ISR_TCIF1   ((uint32_t)0x00000002)
#define	DMA_ISR_HTIF1   ((uint32_t)0x00000004)
#define	DMA_ISR_TEIF1   ((uint32_t)0x00000008)
#define	DMA_ISR_GIF2   ((uint32_t)0x00000010)
#define	DMA_ISR_TCIF2   ((uint32_t)0x00000020)
#define	DMA_ISR_HTIF2   ((uint32_t)0x00000040)
#define	DMA_ISR_TEIF2   ((uint32_t)0x00000080)
#define	DMA_ISR_GIF3   ((uint32_t)0x00000100)
#define	DMA_ISR_TCIF3   ((uint32_t)0x00000200)
#define	DMA_ISR_HTIF3   ((uint32_t)0x00000400)
#define	DMA_ISR_TEIF3   ((uint32_t)0x00000800)
#define	DMA_ISR_GIF4   ((uint32_t)0x00001000)
#define	DMA_ISR_TCIF4   ((uint32_t)0x00002000)
#define	DMA_ISR_HTIF4   ((uint32_t)0x00004000)
#define	DMA_ISR_TEIF4   ((uint32_t)0x00008000)
#define	DMA_ISR_GIF5   ((uint32_t)0x00010000)
#define	DMA_ISR_TCIF5   ((uint32_t)0x00020000)
#define	DMA_ISR_HTIF5   ((uint32_t)0x00040000)
#define	DMA_ISR_TEIF5   ((uint32_t)0x00080000)
#define	DMA_ISR_GIF6   ((uint32_t)0x00100000)
#define	DMA_ISR_TCIF6   ((uint32_t)0x00200000)
#define	DMA_ISR_HTIF6   ((uint32_t)0x00400000)
#define	DMA_ISR_TEIF6   ((uint32_t)0x00800000)
#define	DMA_ISR_GIF7   ((uint32_t)0x01000000)
#define	DMA_ISR_TCIF7   ((uint32_t)0x02000000)
#define	DMA_ISR_HTIF7   ((uint32_t)0x04000000)
#define	DMA_ISR_TEIF7   ((uint32_t)0x08000000)
#define	DMA_IFCR_CGIF1   ((uint32_t)0x00000001)
#define	DMA_IFCR_CTCIF1   ((uint32_t)0x00000002)
#define	DMA_IFCR_CHTIF1   ((uint32_t)0x00000004)
#define	DMA_IFCR_CTEIF1   ((uint32_t)0x00000008)
#define	DMA_IFCR_CGIF2   ((uint32_t)0x00000010)
#define	DMA_IFCR_CTCIF2   ((uint32_t)0x00000020)
#define	DMA_IFCR_CHTIF2   ((uint32_t)0x00000040)
#define	DMA_IFCR_CTEIF2   ((uint32_t)0x00000080)
#define	DMA_IFCR_CGIF3   ((uint32_t)0x00000100)
#define	DMA_IFCR_CTCIF3   ((uint32_t)0x00000200)
#define	DMA_IFCR_CHTIF3   ((uint32_t)0x00000400)
#define	DMA_IFCR_CTEIF3   ((uint32_t)0x00000800)
#define	DMA_IFCR_CGIF4   ((uint32_t)0x00001000)
#define	DMA_IFCR_CTCIF4   ((uint32_t)0x00002000)
#define	DMA_IFCR_CHTIF4   ((uint32_t)0x00004000)
#define	DMA_IFCR_CTEIF4   ((uint32_t)0x00008000)
#define	DMA_IFCR_CGIF5   ((uint32_t)0x00010000)
#define	DMA_IFCR_CTCIF5   ((uint32_t)0x00020000)
#define	DMA_IFCR_CHTIF5   ((uint32_t)0x00040000)
#define	DMA_IFCR_CTEIF5   ((uint32_t)0x00080000)
#define	DMA_IFCR_CGIF6   ((uint32_t)0x00100000)
#define	DMA_IFCR_CTCIF6   ((uint32_t)0x00200000)
#define	DMA_IFCR_CHTIF6   ((uint32_t)0x00400000)
#define	DMA_IFCR_CTEIF6   ((uint32_t)0x00800000)
#define	DMA_IFCR_CGIF7   ((uint32_t)0x01000000)
#define	DMA_IFCR_CTCIF7   ((uint32_t)0x02000000)
#define	DMA_IFCR_CHTIF7   ((uint32_t)0x04000000)
#define	DMA_IFCR_CTEIF7   ((uint32_t)0x08000000)
#define	DMA_CCR1_EN   ((uint16_t)0x0001)
#define	DMA_CCR1_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR1_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR1_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR1_DIR   ((uint16_t)0x0010)
#define	DMA_CCR1_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR1_PINC   ((uint16_t)0x0040)
#define	DMA_CCR1_MINC   ((uint16_t)0x0080)
#define	DMA_CCR1_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR1_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR1_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR1_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR1_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR1_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR1_PL   ((uint16_t)0x3000)
#define	DMA_CCR1_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR1_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR1_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR2_EN   ((uint16_t)0x0001)
#define	DMA_CCR2_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR2_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR2_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR2_DIR   ((uint16_t)0x0010)
#define	DMA_CCR2_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR2_PINC   ((uint16_t)0x0040)
#define	DMA_CCR2_MINC   ((uint16_t)0x0080)
#define	DMA_CCR2_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR2_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR2_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR2_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR2_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR2_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR2_PL   ((uint16_t)0x3000)
#define	DMA_CCR2_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR2_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR2_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR3_EN   ((uint16_t)0x0001)
#define	DMA_CCR3_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR3_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR3_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR3_DIR   ((uint16_t)0x0010)
#define	DMA_CCR3_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR3_PINC   ((uint16_t)0x0040)
#define	DMA_CCR3_MINC   ((uint16_t)0x0080)
#define	DMA_CCR3_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR3_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR3_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR3_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR3_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR3_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR3_PL   ((uint16_t)0x3000)
#define	DMA_CCR3_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR3_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR3_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR4_EN   ((uint16_t)0x0001)
#define	DMA_CCR4_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR4_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR4_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR4_DIR   ((uint16_t)0x0010)
#define	DMA_CCR4_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR4_PINC   ((uint16_t)0x0040)
#define	DMA_CCR4_MINC   ((uint16_t)0x0080)
#define	DMA_CCR4_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR4_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR4_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR4_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR4_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR4_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR4_PL   ((uint16_t)0x3000)
#define	DMA_CCR4_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR4_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR4_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR5_EN   ((uint16_t)0x0001)
#define	DMA_CCR5_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR5_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR5_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR5_DIR   ((uint16_t)0x0010)
#define	DMA_CCR5_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR5_PINC   ((uint16_t)0x0040)
#define	DMA_CCR5_MINC   ((uint16_t)0x0080)
#define	DMA_CCR5_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR5_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR5_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR5_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR5_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR5_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR5_PL   ((uint16_t)0x3000)
#define	DMA_CCR5_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR5_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR5_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR6_EN   ((uint16_t)0x0001)
#define	DMA_CCR6_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR6_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR6_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR6_DIR   ((uint16_t)0x0010)
#define	DMA_CCR6_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR6_PINC   ((uint16_t)0x0040)
#define	DMA_CCR6_MINC   ((uint16_t)0x0080)
#define	DMA_CCR6_PSIZE   ((uint16_t)0x0300)
#define	DMA_CCR6_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR6_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR6_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR6_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR6_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR6_PL   ((uint16_t)0x3000)
#define	DMA_CCR6_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR6_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR6_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CCR7_EN   ((uint16_t)0x0001)
#define	DMA_CCR7_TCIE   ((uint16_t)0x0002)
#define	DMA_CCR7_HTIE   ((uint16_t)0x0004)
#define	DMA_CCR7_TEIE   ((uint16_t)0x0008)
#define	DMA_CCR7_DIR   ((uint16_t)0x0010)
#define	DMA_CCR7_CIRC   ((uint16_t)0x0020)
#define	DMA_CCR7_PINC   ((uint16_t)0x0040)
#define	DMA_CCR7_MINC   ((uint16_t)0x0080)
#define	DMA_CCR7_PSIZE   , ((uint16_t)0x0300)
#define	DMA_CCR7_PSIZE_0   ((uint16_t)0x0100)
#define	DMA_CCR7_PSIZE_1   ((uint16_t)0x0200)
#define	DMA_CCR7_MSIZE   ((uint16_t)0x0C00)
#define	DMA_CCR7_MSIZE_0   ((uint16_t)0x0400)
#define	DMA_CCR7_MSIZE_1   ((uint16_t)0x0800)
#define	DMA_CCR7_PL   ((uint16_t)0x3000)
#define	DMA_CCR7_PL_0   ((uint16_t)0x1000)
#define	DMA_CCR7_PL_1   ((uint16_t)0x2000)
#define	DMA_CCR7_MEM2MEM   ((uint16_t)0x4000)
#define	DMA_CNDTR1_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR2_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR3_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR4_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR5_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR6_NDT   ((uint16_t)0xFFFF)
#define	DMA_CNDTR7_NDT   ((uint16_t)0xFFFF)
#define	DMA_CPAR1_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR2_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR3_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR4_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR5_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR6_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CPAR7_PA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR1_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR2_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR3_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR4_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR5_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR6_MA   ((uint32_t)0xFFFFFFFF)
#define	DMA_CMAR7_MA   ((uint32_t)0xFFFFFFFF)
#define	EXTI_IMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_IMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_IMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_IMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_IMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_IMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_IMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_IMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_IMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_IMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_IMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_IMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_IMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_IMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_IMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_IMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_IMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_IMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_IMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_IMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_IMR_MR20   ((uint32_t)0x00100000)
#define	EXTI_IMR_MR21   ((uint32_t)0x00200000)
#define	EXTI_IMR_MR22   ((uint32_t)0x00400000)
#define	EXTI_IMR_MR23   ((uint32_t)0x00800000)
#define	EXTI_EMR_MR0   ((uint32_t)0x00000001)
#define	EXTI_EMR_MR1   ((uint32_t)0x00000002)
#define	EXTI_EMR_MR2   ((uint32_t)0x00000004)
#define	EXTI_EMR_MR3   ((uint32_t)0x00000008)
#define	EXTI_EMR_MR4   ((uint32_t)0x00000010)
#define	EXTI_EMR_MR5   ((uint32_t)0x00000020)
#define	EXTI_EMR_MR6   ((uint32_t)0x00000040)
#define	EXTI_EMR_MR7   ((uint32_t)0x00000080)
#define	EXTI_EMR_MR8   ((uint32_t)0x00000100)
#define	EXTI_EMR_MR9   ((uint32_t)0x00000200)
#define	EXTI_EMR_MR10   ((uint32_t)0x00000400)
#define	EXTI_EMR_MR11   ((uint32_t)0x00000800)
#define	EXTI_EMR_MR12   ((uint32_t)0x00001000)
#define	EXTI_EMR_MR13   ((uint32_t)0x00002000)
#define	EXTI_EMR_MR14   ((uint32_t)0x00004000)
#define	EXTI_EMR_MR15   ((uint32_t)0x00008000)
#define	EXTI_EMR_MR16   ((uint32_t)0x00010000)
#define	EXTI_EMR_MR17   ((uint32_t)0x00020000)
#define	EXTI_EMR_MR18   ((uint32_t)0x00040000)
#define	EXTI_EMR_MR19   ((uint32_t)0x00080000)
#define	EXTI_EMR_MR20   ((uint32_t)0x00100000)
#define	EXTI_EMR_MR21   ((uint32_t)0x00200000)
#define	EXTI_EMR_MR22   ((uint32_t)0x00400000)
#define	EXTI_EMR_MR23   ((uint32_t)0x00800000)
#define	EXTI_RTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_RTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_RTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_RTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_RTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_RTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_RTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_RTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_RTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_RTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_RTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_RTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_RTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_RTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_RTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_RTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_RTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_RTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_RTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_RTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_RTSR_TR20   ((uint32_t)0x00100000)
#define	EXTI_RTSR_TR21   ((uint32_t)0x00200000)
#define	EXTI_RTSR_TR22   ((uint32_t)0x00400000)
#define	EXTI_RTSR_TR23   ((uint32_t)0x00800000)
#define	EXTI_FTSR_TR0   ((uint32_t)0x00000001)
#define	EXTI_FTSR_TR1   ((uint32_t)0x00000002)
#define	EXTI_FTSR_TR2   ((uint32_t)0x00000004)
#define	EXTI_FTSR_TR3   ((uint32_t)0x00000008)
#define	EXTI_FTSR_TR4   ((uint32_t)0x00000010)
#define	EXTI_FTSR_TR5   ((uint32_t)0x00000020)
#define	EXTI_FTSR_TR6   ((uint32_t)0x00000040)
#define	EXTI_FTSR_TR7   ((uint32_t)0x00000080)
#define	EXTI_FTSR_TR8   ((uint32_t)0x00000100)
#define	EXTI_FTSR_TR9   ((uint32_t)0x00000200)
#define	EXTI_FTSR_TR10   ((uint32_t)0x00000400)
#define	EXTI_FTSR_TR11   ((uint32_t)0x00000800)
#define	EXTI_FTSR_TR12   ((uint32_t)0x00001000)
#define	EXTI_FTSR_TR13   ((uint32_t)0x00002000)
#define	EXTI_FTSR_TR14   ((uint32_t)0x00004000)
#define	EXTI_FTSR_TR15   ((uint32_t)0x00008000)
#define	EXTI_FTSR_TR16   ((uint32_t)0x00010000)
#define	EXTI_FTSR_TR17   ((uint32_t)0x00020000)
#define	EXTI_FTSR_TR18   ((uint32_t)0x00040000)
#define	EXTI_FTSR_TR19   ((uint32_t)0x00080000)
#define	EXTI_FTSR_TR20   ((uint32_t)0x00100000)
#define	EXTI_FTSR_TR21   ((uint32_t)0x00200000)
#define	EXTI_FTSR_TR22   ((uint32_t)0x00400000)
#define	EXTI_FTSR_TR23   ((uint32_t)0x00800000)
#define	EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)
#define	EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)
#define	EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)
#define	EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)
#define	EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)
#define	EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)
#define	EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)
#define	EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)
#define	EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)
#define	EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)
#define	EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)
#define	EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)
#define	EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)
#define	EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)
#define	EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)
#define	EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)
#define	EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)
#define	EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)
#define	EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)
#define	EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)
#define	EXTI_SWIER_SWIER20   ((uint32_t)0x00100000)
#define	EXTI_SWIER_SWIER21   ((uint32_t)0x00200000)
#define	EXTI_SWIER_SWIER22   ((uint32_t)0x00400000)
#define	EXTI_SWIER_SWIER23   ((uint32_t)0x00800000)
#define	EXTI_PR_PR0   ((uint32_t)0x00000001)
#define	EXTI_PR_PR1   ((uint32_t)0x00000002)
#define	EXTI_PR_PR2   ((uint32_t)0x00000004)
#define	EXTI_PR_PR3   ((uint32_t)0x00000008)
#define	EXTI_PR_PR4   ((uint32_t)0x00000010)
#define	EXTI_PR_PR5   ((uint32_t)0x00000020)
#define	EXTI_PR_PR6   ((uint32_t)0x00000040)
#define	EXTI_PR_PR7   ((uint32_t)0x00000080)
#define	EXTI_PR_PR8   ((uint32_t)0x00000100)
#define	EXTI_PR_PR9   ((uint32_t)0x00000200)
#define	EXTI_PR_PR10   ((uint32_t)0x00000400)
#define	EXTI_PR_PR11   ((uint32_t)0x00000800)
#define	EXTI_PR_PR12   ((uint32_t)0x00001000)
#define	EXTI_PR_PR13   ((uint32_t)0x00002000)
#define	EXTI_PR_PR14   ((uint32_t)0x00004000)
#define	EXTI_PR_PR15   ((uint32_t)0x00008000)
#define	EXTI_PR_PR16   ((uint32_t)0x00010000)
#define	EXTI_PR_PR17   ((uint32_t)0x00020000)
#define	EXTI_PR_PR18   ((uint32_t)0x00040000)
#define	EXTI_PR_PR19   ((uint32_t)0x00080000)
#define	EXTI_PR_PR20   ((uint32_t)0x00100000)
#define	EXTI_PR_PR21   ((uint32_t)0x00200000)
#define	EXTI_PR_PR22   ((uint32_t)0x00400000)
#define	EXTI_PR_PR23   ((uint32_t)0x00800000)
#define	FLASH_ACR_LATENCY   ((uint32_t)0x00000001)
#define	FLASH_ACR_PRFTEN   ((uint32_t)0x00000002)
#define	FLASH_ACR_ACC64   ((uint32_t)0x00000004)
#define	FLASH_ACR_SLEEP_PD   ((uint32_t)0x00000008)
#define	FLASH_ACR_RUN_PD   ((uint32_t)0x00000010)
#define	FLASH_PECR_PELOCK   ((uint32_t)0x00000001)
#define	FLASH_PECR_PRGLOCK   ((uint32_t)0x00000002)
#define	FLASH_PECR_OPTLOCK   ((uint32_t)0x00000004)
#define	FLASH_PECR_PROG   ((uint32_t)0x00000008)
#define	FLASH_PECR_DATA   ((uint32_t)0x00000010)
#define	FLASH_PECR_FTDW   ((uint32_t)0x00000100)
#define	FLASH_PECR_ERASE   ((uint32_t)0x00000200)
#define	FLASH_PECR_FPRG   ((uint32_t)0x00000400)
#define	FLASH_PECR_PARALLBANK   ((uint32_t)0x00008000)
#define	FLASH_PECR_EOPIE   ((uint32_t)0x00010000)
#define	FLASH_PECR_ERRIE   ((uint32_t)0x00020000)
#define	FLASH_PECR_OBL_LAUNCH   ((uint32_t)0x00040000)
#define	FLASH_PDKEYR_PDKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_PEKEYR_PEKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_PRGKEYR_PRGKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_OPTKEYR_OPTKEYR   ((uint32_t)0xFFFFFFFF)
#define	FLASH_SR_BSY   ((uint32_t)0x00000001)
#define	FLASH_SR_EOP   ((uint32_t)0x00000002)
#define	FLASH_SR_ENHV   ((uint32_t)0x00000004)
#define	FLASH_SR_READY   ((uint32_t)0x00000008)
#define	FLASH_SR_WRPERR   ((uint32_t)0x00000100)
#define	FLASH_SR_PGAERR   ((uint32_t)0x00000200)
#define	FLASH_SR_SIZERR   ((uint32_t)0x00000400)
#define	FLASH_SR_OPTVERR   ((uint32_t)0x00000800)
#define	FLASH_SR_OPTVERRUSR   ((uint32_t)0x00001000)
#define	FLASH_OBR_RDPRT   ((uint16_t)0x000000AA)
#define	FLASH_OBR_BOR_LEV   ((uint16_t)0x000F0000)
#define	FLASH_OBR_USER   ((uint32_t)0x00700000)
#define	FLASH_OBR_IWDG_SW   ((uint32_t)0x00100000)
#define	FLASH_OBR_nRST_STOP   ((uint32_t)0x00200000)
#define	FLASH_OBR_nRST_STDBY   ((uint32_t)0x00400000)
#define	FLASH_OBR_nRST_BFB2   ((uint32_t)0x00800000)
#define	FLASH_WRPR_WRP   ((uint32_t)0xFFFFFFFF)
#define	FLASH_WRPR1_WRP   ((uint32_t)0xFFFFFFFF)
#define	FLASH_WRPR2_WRP   ((uint32_t)0xFFFFFFFF)
#define	FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR1_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR1_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR2_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR2_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR3_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR3_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)
#define	FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)
#define	FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)
#define	FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)
#define	FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)
#define	FSMC_BCR4_MWID   ((uint32_t)0x00000030)
#define	FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)
#define	FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)
#define	FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)
#define	FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)
#define	FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)
#define	FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)
#define	FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)
#define	FSMC_BCR4_WREN   ((uint32_t)0x00001000)
#define	FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)
#define	FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)
#define	FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)
#define	FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)
#define	FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)
#define	FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)
#define	FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)
#define	FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)
#define	FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)
#define	FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)
#define	FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)
#define	FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)
#define	FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)
#define	FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)
#define	FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)
#define	FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)
#define	FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)
#define	FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)
#define	FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)
#define	FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)
#define	FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)
#define	FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)
#define	FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)
#define	FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)
#define	FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)
#define	FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)
#define	FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)
#define	FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)
#define	FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)
#define	FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)
#define	FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)
#define	FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)
#define	FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)
#define	FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)
#define	FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)
#define	FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)
#define	FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)
#define	FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)
#define	GPIO_MODER_MODER0   ((uint32_t)0x00000003)
#define	GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)
#define	GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)
#define	GPIO_MODER_MODER1   ((uint32_t)0x0000000C)
#define	GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)
#define	GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)
#define	GPIO_MODER_MODER2   ((uint32_t)0x00000030)
#define	GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)
#define	GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)
#define	GPIO_MODER_MODER3   ((uint32_t)0x000000C0)
#define	GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)
#define	GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)
#define	GPIO_MODER_MODER4   ((uint32_t)0x00000300)
#define	GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)
#define	GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)
#define	GPIO_MODER_MODER5   ((uint32_t)0x00000C00)
#define	GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)
#define	GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)
#define	GPIO_MODER_MODER6   ((uint32_t)0x00003000)
#define	GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)
#define	GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)
#define	GPIO_MODER_MODER7   ((uint32_t)0x0000C000)
#define	GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)
#define	GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)
#define	GPIO_MODER_MODER8   ((uint32_t)0x00030000)
#define	GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)
#define	GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)
#define	GPIO_MODER_MODER9   ((uint32_t)0x000C0000)
#define	GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)
#define	GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)
#define	GPIO_MODER_MODER10   ((uint32_t)0x00300000)
#define	GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)
#define	GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)
#define	GPIO_MODER_MODER11   ((uint32_t)0x00C00000)
#define	GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)
#define	GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)
#define	GPIO_MODER_MODER12   ((uint32_t)0x03000000)
#define	GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)
#define	GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)
#define	GPIO_MODER_MODER13   ((uint32_t)0x0C000000)
#define	GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)
#define	GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)
#define	GPIO_MODER_MODER14   ((uint32_t)0x30000000)
#define	GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)
#define	GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)
#define	GPIO_MODER_MODER15   ((uint32_t)0xC0000000)
#define	GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)
#define	GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)
#define	GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)
#define	GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)
#define	GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)
#define	GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)
#define	GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)
#define	GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)
#define	GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)
#define	GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)
#define	GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)
#define	GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)
#define	GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)
#define	GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)
#define	GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)
#define	GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)
#define	GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)
#define	GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)
#define	GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
#define	GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
#define	GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)
#define	GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
#define	GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
#define	GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)
#define	GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
#define	GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
#define	GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)
#define	GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
#define	GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
#define	GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)
#define	GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
#define	GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
#define	GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)
#define	GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
#define	GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
#define	GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)
#define	GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
#define	GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
#define	GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)
#define	GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
#define	GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
#define	GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)
#define	GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
#define	GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
#define	GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)
#define	GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
#define	GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
#define	GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)
#define	GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)
#define	GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)
#define	GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)
#define	GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)
#define	GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)
#define	GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)
#define	GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)
#define	GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)
#define	GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)
#define	GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)
#define	GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)
#define	GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)
#define	GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)
#define	GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)
#define	GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)
#define	GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)
#define	GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)
#define	GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)
#define	GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)
#define	GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)
#define	GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)
#define	GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)
#define	GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)
#define	GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)
#define	GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)
#define	GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)
#define	GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)
#define	GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)
#define	GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)
#define	GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)
#define	GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)
#define	GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)
#define	GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)
#define	GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)
#define	GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)
#define	GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)
#define	GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)
#define	GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)
#define	GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)
#define	GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)
#define	GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)
#define	GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)
#define	GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)
#define	GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)
#define	GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)
#define	GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)
#define	GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)
#define	GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)
#define	GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)
#define	GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)
#define	GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)
#define	GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)
#define	GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)
#define	GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)
#define	GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)
#define	GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)
#define	GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)
#define	GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)
#define	GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)
#define	GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)
#define	GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)
#define	GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)
#define	GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)
#define	GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)
#define	GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)
#define	GPIO_IDR_IDR_0   ((uint32_t)0x00000001)
#define	GPIO_IDR_IDR_1   ((uint32_t)0x00000002)
#define	GPIO_IDR_IDR_2   ((uint32_t)0x00000004)
#define	GPIO_IDR_IDR_3   ((uint32_t)0x00000008)
#define	GPIO_IDR_IDR_4   ((uint32_t)0x00000010)
#define	GPIO_IDR_IDR_5   ((uint32_t)0x00000020)
#define	GPIO_IDR_IDR_6   ((uint32_t)0x00000040)
#define	GPIO_IDR_IDR_7   ((uint32_t)0x00000080)
#define	GPIO_IDR_IDR_8   ((uint32_t)0x00000100)
#define	GPIO_IDR_IDR_9   ((uint32_t)0x00000200)
#define	GPIO_IDR_IDR_10   ((uint32_t)0x00000400)
#define	GPIO_IDR_IDR_11   ((uint32_t)0x00000800)
#define	GPIO_IDR_IDR_12   ((uint32_t)0x00001000)
#define	GPIO_IDR_IDR_13   ((uint32_t)0x00002000)
#define	GPIO_IDR_IDR_14   ((uint32_t)0x00004000)
#define	GPIO_IDR_IDR_15   ((uint32_t)0x00008000)
#define	GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0
#define	GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1
#define	GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2
#define	GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3
#define	GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4
#define	GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5
#define	GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6
#define	GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7
#define	GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8
#define	GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9
#define	GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10
#define	GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11
#define	GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12
#define	GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13
#define	GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14
#define	GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15
#define	GPIO_ODR_ODR_0   ((uint32_t)0x00000001)
#define	GPIO_ODR_ODR_1   ((uint32_t)0x00000002)
#define	GPIO_ODR_ODR_2   ((uint32_t)0x00000004)
#define	GPIO_ODR_ODR_3   ((uint32_t)0x00000008)
#define	GPIO_ODR_ODR_4   ((uint32_t)0x00000010)
#define	GPIO_ODR_ODR_5   ((uint32_t)0x00000020)
#define	GPIO_ODR_ODR_6   ((uint32_t)0x00000040)
#define	GPIO_ODR_ODR_7   ((uint32_t)0x00000080)
#define	GPIO_ODR_ODR_8   ((uint32_t)0x00000100)
#define	GPIO_ODR_ODR_9   ((uint32_t)0x00000200)
#define	GPIO_ODR_ODR_10   ((uint32_t)0x00000400)
#define	GPIO_ODR_ODR_11   ((uint32_t)0x00000800)
#define	GPIO_ODR_ODR_12   ((uint32_t)0x00001000)
#define	GPIO_ODR_ODR_13   ((uint32_t)0x00002000)
#define	GPIO_ODR_ODR_14   ((uint32_t)0x00004000)
#define	GPIO_ODR_ODR_15   ((uint32_t)0x00008000)
#define	GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0
#define	GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1
#define	GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2
#define	GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3
#define	GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4
#define	GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5
#define	GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6
#define	GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7
#define	GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8
#define	GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9
#define	GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10
#define	GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11
#define	GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12
#define	GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13
#define	GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14
#define	GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15
#define	GPIO_BSRR_BS_0   ((uint32_t)0x00000001)
#define	GPIO_BSRR_BS_1   ((uint32_t)0x00000002)
#define	GPIO_BSRR_BS_2   ((uint32_t)0x00000004)
#define	GPIO_BSRR_BS_3   ((uint32_t)0x00000008)
#define	GPIO_BSRR_BS_4   ((uint32_t)0x00000010)
#define	GPIO_BSRR_BS_5   ((uint32_t)0x00000020)
#define	GPIO_BSRR_BS_6   ((uint32_t)0x00000040)
#define	GPIO_BSRR_BS_7   ((uint32_t)0x00000080)
#define	GPIO_BSRR_BS_8   ((uint32_t)0x00000100)
#define	GPIO_BSRR_BS_9   ((uint32_t)0x00000200)
#define	GPIO_BSRR_BS_10   ((uint32_t)0x00000400)
#define	GPIO_BSRR_BS_11   ((uint32_t)0x00000800)
#define	GPIO_BSRR_BS_12   ((uint32_t)0x00001000)
#define	GPIO_BSRR_BS_13   ((uint32_t)0x00002000)
#define	GPIO_BSRR_BS_14   ((uint32_t)0x00004000)
#define	GPIO_BSRR_BS_15   ((uint32_t)0x00008000)
#define	GPIO_BSRR_BR_0   ((uint32_t)0x00010000)
#define	GPIO_BSRR_BR_1   ((uint32_t)0x00020000)
#define	GPIO_BSRR_BR_2   ((uint32_t)0x00040000)
#define	GPIO_BSRR_BR_3   ((uint32_t)0x00080000)
#define	GPIO_BSRR_BR_4   ((uint32_t)0x00100000)
#define	GPIO_BSRR_BR_5   ((uint32_t)0x00200000)
#define	GPIO_BSRR_BR_6   ((uint32_t)0x00400000)
#define	GPIO_BSRR_BR_7   ((uint32_t)0x00800000)
#define	GPIO_BSRR_BR_8   ((uint32_t)0x01000000)
#define	GPIO_BSRR_BR_9   ((uint32_t)0x02000000)
#define	GPIO_BSRR_BR_10   ((uint32_t)0x04000000)
#define	GPIO_BSRR_BR_11   ((uint32_t)0x08000000)
#define	GPIO_BSRR_BR_12   ((uint32_t)0x10000000)
#define	GPIO_BSRR_BR_13   ((uint32_t)0x20000000)
#define	GPIO_BSRR_BR_14   ((uint32_t)0x40000000)
#define	GPIO_BSRR_BR_15   ((uint32_t)0x80000000)
#define	GPIO_LCKR_LCK0   ((uint32_t)0x00000001)
#define	GPIO_LCKR_LCK1   ((uint32_t)0x00000002)
#define	GPIO_LCKR_LCK2   ((uint32_t)0x00000004)
#define	GPIO_LCKR_LCK3   ((uint32_t)0x00000008)
#define	GPIO_LCKR_LCK4   ((uint32_t)0x00000010)
#define	GPIO_LCKR_LCK5   ((uint32_t)0x00000020)
#define	GPIO_LCKR_LCK6   ((uint32_t)0x00000040)
#define	GPIO_LCKR_LCK7   ((uint32_t)0x00000080)
#define	GPIO_LCKR_LCK8   ((uint32_t)0x00000100)
#define	GPIO_LCKR_LCK9   ((uint32_t)0x00000200)
#define	GPIO_LCKR_LCK10   ((uint32_t)0x00000400)
#define	GPIO_LCKR_LCK11   ((uint32_t)0x00000800)
#define	GPIO_LCKR_LCK12   ((uint32_t)0x00001000)
#define	GPIO_LCKR_LCK13   ((uint32_t)0x00002000)
#define	GPIO_LCKR_LCK14   ((uint32_t)0x00004000)
#define	GPIO_LCKR_LCK15   ((uint32_t)0x00008000)
#define	GPIO_LCKR_LCKK   ((uint32_t)0x00010000)
#define	GPIO_AFRL_AFRL0   ((uint32_t)0x0000000F)
#define	GPIO_AFRL_AFRL1   ((uint32_t)0x000000F0)
#define	GPIO_AFRL_AFRL2   ((uint32_t)0x00000F00)
#define	GPIO_AFRL_AFRL3   ((uint32_t)0x0000F000)
#define	GPIO_AFRL_AFRL4   ((uint32_t)0x000F0000)
#define	GPIO_AFRL_AFRL5   ((uint32_t)0x00F00000)
#define	GPIO_AFRL_AFRL6   ((uint32_t)0x0F000000)
#define	GPIO_AFRL_AFRL7   ((uint32_t)0xF0000000)
#define	GPIO_AFRH_AFRH8   ((uint32_t)0x0000000F)
#define	GPIO_AFRH_AFRH9   ((uint32_t)0x000000F0)
#define	GPIO_AFRH_AFRH10   ((uint32_t)0x00000F00)
#define	GPIO_AFRH_AFRH11   ((uint32_t)0x0000F000)
#define	GPIO_AFRH_AFRH12   ((uint32_t)0x000F0000)
#define	GPIO_AFRH_AFRH13   ((uint32_t)0x00F00000)
#define	GPIO_AFRH_AFRH14   ((uint32_t)0x0F000000)
#define	GPIO_AFRH_AFRH15   ((uint32_t)0xF0000000)
#define	I2C_CR1_PE   ((uint16_t)0x0001)
#define	I2C_CR1_SMBUS   ((uint16_t)0x0002)
#define	I2C_CR1_SMBTYPE   ((uint16_t)0x0008)
#define	I2C_CR1_ENARP   ((uint16_t)0x0010)
#define	I2C_CR1_ENPEC   ((uint16_t)0x0020)
#define	I2C_CR1_ENGC   ((uint16_t)0x0040)
#define	I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)
#define	I2C_CR1_START   ((uint16_t)0x0100)
#define	I2C_CR1_STOP   ((uint16_t)0x0200)
#define	I2C_CR1_ACK   ((uint16_t)0x0400)
#define	I2C_CR1_POS   ((uint16_t)0x0800)
#define	I2C_CR1_PEC   ((uint16_t)0x1000)
#define	I2C_CR1_ALERT   ((uint16_t)0x2000)
#define	I2C_CR1_SWRST   ((uint16_t)0x8000)
#define	I2C_CR2_FREQ   ((uint16_t)0x003F)
#define	I2C_CR2_FREQ_0   ((uint16_t)0x0001)
#define	I2C_CR2_FREQ_1   ((uint16_t)0x0002)
#define	I2C_CR2_FREQ_2   ((uint16_t)0x0004)
#define	I2C_CR2_FREQ_3   ((uint16_t)0x0008)
#define	I2C_CR2_FREQ_4   ((uint16_t)0x0010)
#define	I2C_CR2_FREQ_5   ((uint16_t)0x0020)
#define	I2C_CR2_ITERREN   ((uint16_t)0x0100)
#define	I2C_CR2_ITEVTEN   ((uint16_t)0x0200)
#define	I2C_CR2_ITBUFEN   ((uint16_t)0x0400)
#define	I2C_CR2_DMAEN   ((uint16_t)0x0800)
#define	I2C_CR2_LAST   ((uint16_t)0x1000)
#define	I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)
#define	I2C_OAR1_ADD8_9   ((uint16_t)0x0300)
#define	I2C_OAR1_ADD0   ((uint16_t)0x0001)
#define	I2C_OAR1_ADD1   ((uint16_t)0x0002)
#define	I2C_OAR1_ADD2   ((uint16_t)0x0004)
#define	I2C_OAR1_ADD3   ((uint16_t)0x0008)
#define	I2C_OAR1_ADD4   ((uint16_t)0x0010)
#define	I2C_OAR1_ADD5   ((uint16_t)0x0020)
#define	I2C_OAR1_ADD6   ((uint16_t)0x0040)
#define	I2C_OAR1_ADD7   ((uint16_t)0x0080)
#define	I2C_OAR1_ADD8   ((uint16_t)0x0100)
#define	I2C_OAR1_ADD9   ((uint16_t)0x0200)
#define	I2C_OAR1_ADDMODE   ((uint16_t)0x8000)
#define	I2C_OAR2_ENDUAL   ((uint8_t)0x01)
#define	I2C_OAR2_ADD2   ((uint8_t)0xFE)
#define	I2C_DR_DR   ((uint8_t)0xFF)
#define	I2C_SR1_SB   ((uint16_t)0x0001)
#define	I2C_SR1_ADDR   ((uint16_t)0x0002)
#define	I2C_SR1_BTF   ((uint16_t)0x0004)
#define	I2C_SR1_ADD10   ((uint16_t)0x0008)
#define	I2C_SR1_STOPF   ((uint16_t)0x0010)
#define	I2C_SR1_RXNE   ((uint16_t)0x0040)
#define	I2C_SR1_TXE   ((uint16_t)0x0080)
#define	I2C_SR1_BERR   ((uint16_t)0x0100)
#define	I2C_SR1_ARLO   ((uint16_t)0x0200)
#define	I2C_SR1_AF   ((uint16_t)0x0400)
#define	I2C_SR1_OVR   ((uint16_t)0x0800)
#define	I2C_SR1_PECERR   ((uint16_t)0x1000)
#define	I2C_SR1_TIMEOUT   ((uint16_t)0x4000)
#define	I2C_SR1_SMBALERT   ((uint16_t)0x8000)
#define	I2C_SR2_MSL   ((uint16_t)0x0001)
#define	I2C_SR2_BUSY   ((uint16_t)0x0002)
#define	I2C_SR2_TRA   ((uint16_t)0x0004)
#define	I2C_SR2_GENCALL   ((uint16_t)0x0010)
#define	I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)
#define	I2C_SR2_SMBHOST   ((uint16_t)0x0040)
#define	I2C_SR2_DUALF   ((uint16_t)0x0080)
#define	I2C_SR2_PEC   ((uint16_t)0xFF00)
#define	I2C_CCR_CCR   ((uint16_t)0x0FFF)
#define	I2C_CCR_DUTY   ((uint16_t)0x4000)
#define	I2C_CCR_FS   ((uint16_t)0x8000)
#define	I2C_TRISE_TRISE   ((uint8_t)0x3F)
#define	IWDG_KR_KEY   ((uint16_t)0xFFFF)
#define	IWDG_PR_PR   ((uint8_t)0x07)
#define	IWDG_PR_PR_0   ((uint8_t)0x01)
#define	IWDG_PR_PR_1   ((uint8_t)0x02)
#define	IWDG_PR_PR_2   ((uint8_t)0x04)
#define	IWDG_RLR_RL   ((uint16_t)0x0FFF)
#define	IWDG_SR_PVU   ((uint8_t)0x01)
#define	IWDG_SR_RVU   ((uint8_t)0x02)
#define	LCD_CR_LCDEN   ((uint32_t)0x00000001)
#define	LCD_CR_VSEL   ((uint32_t)0x00000002)
#define	LCD_CR_DUTY   ((uint32_t)0x0000001C)
#define	LCD_CR_DUTY_0   ((uint32_t)0x00000004)
#define	LCD_CR_DUTY_1   ((uint32_t)0x00000008)
#define	LCD_CR_DUTY_2   ((uint32_t)0x00000010)
#define	LCD_CR_BIAS   ((uint32_t)0x00000060)
#define	LCD_CR_BIAS_0   ((uint32_t)0x00000020)
#define	LCD_CR_BIAS_1   ((uint32_t)0x00000040)
#define	LCD_CR_MUX_SEG   ((uint32_t)0x00000080)
#define	LCD_FCR_HD   ((uint32_t)0x00000001)
#define	LCD_FCR_SOFIE   ((uint32_t)0x00000002)
#define	LCD_FCR_UDDIE   ((uint32_t)0x00000008)
#define	LCD_FCR_PON   ((uint32_t)0x00000070)
#define	LCD_FCR_PON_0   ((uint32_t)0x00000010)
#define	LCD_FCR_PON_1   ((uint32_t)0x00000020)
#define	LCD_FCR_PON_2   ((uint32_t)0x00000040)
#define	LCD_FCR_DEAD   ((uint32_t)0x00000380)
#define	LCD_FCR_DEAD_0   ((uint32_t)0x00000080)
#define	LCD_FCR_DEAD_1   ((uint32_t)0x00000100)
#define	LCD_FCR_DEAD_2   ((uint32_t)0x00000200)
#define	LCD_FCR_CC   ((uint32_t)0x00001C00)
#define	LCD_FCR_CC_0   ((uint32_t)0x00000400)
#define	LCD_FCR_CC_1   ((uint32_t)0x00000800)
#define	LCD_FCR_CC_2   ((uint32_t)0x00001000)
#define	LCD_FCR_BLINKF   ((uint32_t)0x0000E000)
#define	LCD_FCR_BLINKF_0   ((uint32_t)0x00002000)
#define	LCD_FCR_BLINKF_1   ((uint32_t)0x00004000)
#define	LCD_FCR_BLINKF_2   ((uint32_t)0x00008000)
#define	LCD_FCR_BLINK   ((uint32_t)0x00030000)
#define	LCD_FCR_BLINK_0   ((uint32_t)0x00010000)
#define	LCD_FCR_BLINK_1   ((uint32_t)0x00020000)
#define	LCD_FCR_DIV   ((uint32_t)0x003C0000)
#define	LCD_FCR_PS   ((uint32_t)0x03C00000)
#define	LCD_SR_ENS   ((uint32_t)0x00000001)
#define	LCD_SR_SOF   ((uint32_t)0x00000002)
#define	LCD_SR_UDR   ((uint32_t)0x00000004)
#define	LCD_SR_UDD   ((uint32_t)0x00000008)
#define	LCD_SR_RDY   ((uint32_t)0x00000010)
#define	LCD_SR_FCRSR   ((uint32_t)0x00000020)
#define	LCD_CLR_SOFC   ((uint32_t)0x00000002)
#define	LCD_CLR_UDDC   ((uint32_t)0x00000008)
#define	LCD_RAM_SEGMENT_DATA   ((uint32_t)0xFFFFFFFF)
#define	PWR_CR_LPSDSR   ((uint16_t)0x0001)
#define	PWR_CR_PDDS   ((uint16_t)0x0002)
#define	PWR_CR_CWUF   ((uint16_t)0x0004)
#define	PWR_CR_CSBF   ((uint16_t)0x0008)
#define	PWR_CR_PVDE   ((uint16_t)0x0010)
#define	PWR_CR_PLS   ((uint16_t)0x00E0)
#define	PWR_CR_PLS_0   ((uint16_t)0x0020)
#define	PWR_CR_PLS_1   ((uint16_t)0x0040)
#define	PWR_CR_PLS_2   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV0   ((uint16_t)0x0000)
#define	PWR_CR_PLS_LEV1   ((uint16_t)0x0020)
#define	PWR_CR_PLS_LEV2   ((uint16_t)0x0040)
#define	PWR_CR_PLS_LEV3   ((uint16_t)0x0060)
#define	PWR_CR_PLS_LEV4   ((uint16_t)0x0080)
#define	PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)
#define	PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)
#define	PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)
#define	PWR_CR_DBP   ((uint16_t)0x0100)
#define	PWR_CR_ULP   ((uint16_t)0x0200)
#define	PWR_CR_FWU   ((uint16_t)0x0400)
#define	PWR_CR_VOS   ((uint16_t)0x1800)
#define	PWR_CR_VOS_0   ((uint16_t)0x0800)
#define	PWR_CR_VOS_1   ((uint16_t)0x1000)
#define	PWR_CR_LPRUN   ((uint16_t)0x4000)
#define	PWR_CSR_WUF   ((uint16_t)0x0001)
#define	PWR_CSR_SBF   ((uint16_t)0x0002)
#define	PWR_CSR_PVDO   ((uint16_t)0x0004)
#define	PWR_CSR_VREFINTRDYF   ((uint16_t)0x0008)
#define	PWR_CSR_VOSF   ((uint16_t)0x0010)
#define	PWR_CSR_REGLPF   ((uint16_t)0x0020)
#define	PWR_CSR_EWUP1   ((uint16_t)0x0100)
#define	PWR_CSR_EWUP2   ((uint16_t)0x0200)
#define	PWR_CSR_EWUP3   ((uint16_t)0x0400)
#define	RCC_CR_HSION   ((uint32_t)0x00000001)
#define	RCC_CR_HSIRDY   ((uint32_t)0x00000002)
#define	RCC_CR_MSION   ((uint32_t)0x00000100)
#define	RCC_CR_MSIRDY   ((uint32_t)0x00000200)
#define	RCC_CR_HSEON   ((uint32_t)0x00010000)
#define	RCC_CR_HSERDY   ((uint32_t)0x00020000)
#define	RCC_CR_HSEBYP   ((uint32_t)0x00040000)
#define	RCC_CR_PLLON   ((uint32_t)0x01000000)
#define	RCC_CR_PLLRDY   ((uint32_t)0x02000000)
#define	RCC_CR_CSSON   ((uint32_t)0x10000000)
#define	RCC_CR_RTCPRE   ((uint32_t)0x60000000)
#define	RCC_CR_RTCPRE_0   ((uint32_t)0x20000000)
#define	RCC_CR_RTCPRE_1   ((uint32_t)0x40000000)
#define	RCC_ICSCR_HSICAL   ((uint32_t)0x000000FF)
#define	RCC_ICSCR_HSITRIM   ((uint32_t)0x00001F00)
#define	RCC_ICSCR_MSIRANGE   ((uint32_t)0x0000E000)
#define	RCC_ICSCR_MSIRANGE_0   ((uint32_t)0x00000000)
#define	RCC_ICSCR_MSIRANGE_1   ((uint32_t)0x00002000)
#define	RCC_ICSCR_MSIRANGE_2   ((uint32_t)0x00004000)
#define	RCC_ICSCR_MSIRANGE_3   ((uint32_t)0x00006000)
#define	RCC_ICSCR_MSIRANGE_4   ((uint32_t)0x00008000)
#define	RCC_ICSCR_MSIRANGE_5   ((uint32_t)0x0000A000)
#define	RCC_ICSCR_MSIRANGE_6   ((uint32_t)0x0000C000)
#define	RCC_ICSCR_MSICAL   ((uint32_t)0x00FF0000)
#define	RCC_ICSCR_MSITRIM   ((uint32_t)0xFF000000)
#define	RCC_CFGR_SW   ((uint32_t)0x00000003)
#define	RCC_CFGR_SW_0   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_1   ((uint32_t)0x00000002)
#define	RCC_CFGR_SW_MSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SW_HSI   ((uint32_t)0x00000001)
#define	RCC_CFGR_SW_HSE   ((uint32_t)0x00000002)
#define	RCC_CFGR_SW_PLL   ((uint32_t)0x00000003)
#define	RCC_CFGR_SWS   ((uint32_t)0x0000000C)
#define	RCC_CFGR_SWS_0   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_1   ((uint32_t)0x00000008)
#define	RCC_CFGR_SWS_MSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_SWS_HSI   ((uint32_t)0x00000004)
#define	RCC_CFGR_SWS_HSE   ((uint32_t)0x00000008)
#define	RCC_CFGR_SWS_PLL   ((uint32_t)0x0000000C)
#define	RCC_CFGR_HPRE   ((uint32_t)0x000000F0)
#define	RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)
#define	RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)
#define	RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)
#define	RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)
#define	RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)
#define	RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)
#define	RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)
#define	RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)
#define	RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)
#define	RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)
#define	RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)
#define	RCC_CFGR_PPRE1   ((uint32_t)0x00000700)
#define	RCC_CFGR_PPRE1_0   ((uint32_t)0x00000100)
#define	RCC_CFGR_PPRE1_1   ((uint32_t)0x00000200)
#define	RCC_CFGR_PPRE1_2   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00000400)
#define	RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00000500)
#define	RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00000600)
#define	RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00000700)
#define	RCC_CFGR_PPRE2   ((uint32_t)0x00003800)
#define	RCC_CFGR_PPRE2_0   ((uint32_t)0x00000800)
#define	RCC_CFGR_PPRE2_1   ((uint32_t)0x00001000)
#define	RCC_CFGR_PPRE2_2   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00002000)
#define	RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x00002800)
#define	RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x00003000)
#define	RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x00003800)
#define	RCC_CFGR_PLLSRC   ((uint32_t)0x00010000)
#define	RCC_CFGR_PLLSRC_HSI   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLSRC_HSE   ((uint32_t)0x00010000)
#define	RCC_CFGR_PLLMUL   ((uint32_t)0x003C0000)
#define	RCC_CFGR_PLLMUL_0   ((uint32_t)0x00040000)
#define	RCC_CFGR_PLLMUL_1   ((uint32_t)0x00080000)
#define	RCC_CFGR_PLLMUL_2   ((uint32_t)0x00100000)
#define	RCC_CFGR_PLLMUL_3   ((uint32_t)0x00200000)
#define	RCC_CFGR_PLLMUL3   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLMUL4   ((uint32_t)0x00040000)
#define	RCC_CFGR_PLLMUL6   ((uint32_t)0x00080000)
#define	RCC_CFGR_PLLMUL8   ((uint32_t)0x000C0000)
#define	RCC_CFGR_PLLMUL12   ((uint32_t)0x00100000)
#define	RCC_CFGR_PLLMUL16   ((uint32_t)0x00140000)
#define	RCC_CFGR_PLLMUL24   ((uint32_t)0x00180000)
#define	RCC_CFGR_PLLMUL32   ((uint32_t)0x001C0000)
#define	RCC_CFGR_PLLMUL48   ((uint32_t)0x00200000)
#define	RCC_CFGR_PLLDIV   ((uint32_t)0x00C00000)
#define	RCC_CFGR_PLLDIV_0   ((uint32_t)0x00400000)
#define	RCC_CFGR_PLLDIV_1   ((uint32_t)0x00800000)
#define	RCC_CFGR_PLLDIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_PLLDIV2   ((uint32_t)0x00400000)
#define	RCC_CFGR_PLLDIV3   ((uint32_t)0x00800000)
#define	RCC_CFGR_PLLDIV4   ((uint32_t)0x00C00000)
#define	RCC_CFGR_MCOSEL   ((uint32_t)0x07000000)
#define	RCC_CFGR_MCOSEL_0   ((uint32_t)0x01000000)
#define	RCC_CFGR_MCOSEL_1   ((uint32_t)0x02000000)
#define	RCC_CFGR_MCOSEL_2   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO_NOCLOCK   ((uint32_t)0x00000000)
#define	RCC_CFGR_MCO_SYSCLK   ((uint32_t)0x01000000)
#define	RCC_CFGR_MCO_HSI   ((uint32_t)0x02000000)
#define	RCC_CFGR_MCO_MSI   ((uint32_t)0x03000000)
#define	RCC_CFGR_MCO_HSE   ((uint32_t)0x04000000)
#define	RCC_CFGR_MCO_PLL   ((uint32_t)0x05000000)
#define	RCC_CFGR_MCO_LSI   ((uint32_t)0x06000000)
#define	RCC_CFGR_MCO_LSE   ((uint32_t)0x07000000)
#define	RCC_CFGR_MCOPRE   ((uint32_t)0x70000000)
#define	RCC_CFGR_MCOPRE_0   ((uint32_t)0x10000000)
#define	RCC_CFGR_MCOPRE_1   ((uint32_t)0x20000000)
#define	RCC_CFGR_MCOPRE_2   ((uint32_t)0x40000000)
#define	RCC_CFGR_MCO_DIV1   ((uint32_t)0x00000000)
#define	RCC_CFGR_MCO_DIV2   ((uint32_t)0x10000000)
#define	RCC_CFGR_MCO_DIV4   ((uint32_t)0x20000000)
#define	RCC_CFGR_MCO_DIV8   ((uint32_t)0x30000000)
#define	RCC_CFGR_MCO_DIV16   ((uint32_t)0x40000000)
#define	RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)
#define	RCC_CIR_LSERDYF   ((uint32_t)0x00000002)
#define	RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)
#define	RCC_CIR_HSERDYF   ((uint32_t)0x00000008)
#define	RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)
#define	RCC_CIR_MSIRDYF   ((uint32_t)0x00000020)
#define	RCC_CIR_LSECSS   ((uint32_t)0x00000040)
#define	RCC_CIR_CSSF   ((uint32_t)0x00000080)
#define	RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)
#define	RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)
#define	RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)
#define	RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)
#define	RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)
#define	RCC_CIR_MSIRDYIE   ((uint32_t)0x00002000)
#define	RCC_CIR_LSECSSIE   ((uint32_t)0x00004000)
#define	RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)
#define	RCC_CIR_LSERDYC   ((uint32_t)0x00020000)
#define	RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)
#define	RCC_CIR_HSERDYC   ((uint32_t)0x00080000)
#define	RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)
#define	RCC_CIR_MSIRDYC   ((uint32_t)0x00200000)
#define	RCC_CIR_LSECSSC   ((uint32_t)0x00400000)
#define	RCC_CIR_CSSC   ((uint32_t)0x00800000)
#define	RCC_AHBRSTR_GPIOARST   ((uint32_t)0x00000001)
#define	RCC_AHBRSTR_GPIOBRST   ((uint32_t)0x00000002)
#define	RCC_AHBRSTR_GPIOCRST   ((uint32_t)0x00000004)
#define	RCC_AHBRSTR_GPIODRST   ((uint32_t)0x00000008)
#define	RCC_AHBRSTR_GPIOERST   ((uint32_t)0x00000010)
#define	RCC_AHBRSTR_GPIOHRST   ((uint32_t)0x00000020)
#define	RCC_AHBRSTR_GPIOFRST   ((uint32_t)0x00000040)
#define	RCC_AHBRSTR_GPIOGRST   ((uint32_t)0x00000080)
#define	RCC_AHBRSTR_CRCRST   ((uint32_t)0x00001000)
#define	RCC_AHBRSTR_FLITFRST   ((uint32_t)0x00008000)
#define	RCC_AHBRSTR_DMA1RST   ((uint32_t)0x01000000)
#define	RCC_AHBRSTR_DMA2RST   ((uint32_t)0x02000000)
#define	RCC_AHBRSTR_AESRST   ((uint32_t)0x08000000)
#define	RCC_AHBRSTR_FSMCRST   ((uint32_t)0x40000000)
#define	RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00000001)
#define	RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00000004)
#define	RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00000008)
#define	RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00000010)
#define	RCC_APB2RSTR_ADC1RST   ((uint32_t)0x00000200)
#define	RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)
#define	RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)
#define	RCC_APB2RSTR_USART1RST   ((uint32_t)0x00004000)
#define	RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)
#define	RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)
#define	RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)
#define	RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)
#define	RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)
#define	RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)
#define	RCC_APB1RSTR_LCDRST   ((uint32_t)0x00000200)
#define	RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)
#define	RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)
#define	RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00008000)
#define	RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)
#define	RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)
#define	RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)
#define	RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)
#define	RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)
#define	RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)
#define	RCC_APB1RSTR_USBRST   ((uint32_t)0x00800000)
#define	RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)
#define	RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)
#define	RCC_APB1RSTR_COMPRST   ((uint32_t)0x80000000)
#define	RCC_AHBENR_GPIOAEN   ((uint32_t)0x00000001)
#define	RCC_AHBENR_GPIOBEN   ((uint32_t)0x00000002)
#define	RCC_AHBENR_GPIOCEN   ((uint32_t)0x00000004)
#define	RCC_AHBENR_GPIODEN   ((uint32_t)0x00000008)
#define	RCC_AHBENR_GPIOEEN   ((uint32_t)0x00000010)
#define	RCC_AHBENR_GPIOHEN   ((uint32_t)0x00000020)
#define	RCC_AHBENR_GPIOFEN   ((uint32_t)0x00000040)
#define	RCC_AHBENR_GPIOGEN   ((uint32_t)0x00000080)
#define	RCC_AHBENR_CRCEN   ((uint32_t)0x00001000)
#define	RCC_AHBENR_FLITFEN   ((uint32_t)0x00008000)
#define	RCC_AHBENR_DMA1EN   ((uint32_t)0x01000000)
#define	RCC_AHBENR_DMA2EN   ((uint32_t)0x02000000)
#define	RCC_AHBENR_AESEN   ((uint32_t)0x08000000)
#define	RCC_AHBENR_FSMCEN   ((uint32_t)0x40000000)
#define	RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00000001)
#define	RCC_APB2ENR_TIM9EN   ((uint32_t)0x00000004)
#define	RCC_APB2ENR_TIM10EN   ((uint32_t)0x00000008)
#define	RCC_APB2ENR_TIM11EN   ((uint32_t)0x00000010)
#define	RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000200)
#define	RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)
#define	RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)
#define	RCC_APB2ENR_USART1EN   ((uint32_t)0x00004000)
#define	RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)
#define	RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)
#define	RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)
#define	RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)
#define	RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)
#define	RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)
#define	RCC_APB1ENR_LCDEN   ((uint32_t)0x00000200)
#define	RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)
#define	RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)
#define	RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)
#define	RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)
#define	RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)
#define	RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)
#define	RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)
#define	RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)
#define	RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)
#define	RCC_APB1ENR_USBEN   ((uint32_t)0x00800000)
#define	RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)
#define	RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)
#define	RCC_APB1ENR_COMPEN   ((uint32_t)0x80000000)
#define	RCC_AHBLPENR_GPIOALPEN   ((uint32_t)0x00000001)
#define	RCC_AHBLPENR_GPIOBLPEN   ((uint32_t)0x00000002)
#define	RCC_AHBLPENR_GPIOCLPEN   ((uint32_t)0x00000004)
#define	RCC_AHBLPENR_GPIODLPEN   ((uint32_t)0x00000008)
#define	RCC_AHBLPENR_GPIOELPEN   ((uint32_t)0x00000010)
#define	RCC_AHBLPENR_GPIOHLPEN   ((uint32_t)0x00000020)
#define	RCC_AHBLPENR_GPIOFLPEN   ((uint32_t)0x00000040)
#define	RCC_AHBLPENR_GPIOGLPEN   ((uint32_t)0x00000080)
#define	RCC_AHBLPENR_CRCLPEN   ((uint32_t)0x00001000)
#define	RCC_AHBLPENR_FLITFLPEN   ((uint32_t)0x00008000)
#define	RCC_AHBLPENR_SRAMLPEN   ((uint32_t)0x00010000)
#define	RCC_AHBLPENR_DMA1LPEN   ((uint32_t)0x01000000)
#define	RCC_AHBLPENR_DMA2LPEN   ((uint32_t)0x02000000)
#define	RCC_AHBLPENR_AESLPEN   ((uint32_t)0x08000000)
#define	RCC_AHBLPENR_FSMCLPEN   ((uint32_t)0x40000000)
#define	RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00000001)
#define	RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00000004)
#define	RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00000008)
#define	RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00000010)
#define	RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000200)
#define	RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)
#define	RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)
#define	RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00004000)
#define	RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)
#define	RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)
#define	RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)
#define	RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)
#define	RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)
#define	RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)
#define	RCC_APB1LPENR_LCDLPEN   ((uint32_t)0x00000200)
#define	RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)
#define	RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)
#define	RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)
#define	RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)
#define	RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)
#define	RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)
#define	RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)
#define	RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)
#define	RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)
#define	RCC_APB1LPENR_USBLPEN   ((uint32_t)0x00800000)
#define	RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)
#define	RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)
#define	RCC_APB1LPENR_COMPLPEN   ((uint32_t)0x80000000)
#define	RCC_CSR_LSION   ((uint32_t)0x00000001)
#define	RCC_CSR_LSIRDY   ((uint32_t)0x00000002)
#define	RCC_CSR_LSEON   ((uint32_t)0x00000100)
#define	RCC_CSR_LSERDY   ((uint32_t)0x00000200)
#define	RCC_CSR_LSEBYP   ((uint32_t)0x00000400)
#define	RCC_CSR_LSECSSON   ((uint32_t)0x00000800)
#define	RCC_CSR_LSECSSD   ((uint32_t)0x00001000)
#define	RCC_CSR_RTCSEL   ((uint32_t)0x00030000)
#define	RCC_CSR_RTCSEL_0   ((uint32_t)0x00010000)
#define	RCC_CSR_RTCSEL_1   ((uint32_t)0x00020000)
#define	RCC_CSR_RTCSEL_NOCLOCK   ((uint32_t)0x00000000)
#define	RCC_CSR_RTCSEL_LSE   ((uint32_t)0x00010000)
#define	RCC_CSR_RTCSEL_LSI   ((uint32_t)0x00020000)
#define	RCC_CSR_RTCSEL_HSE   ((uint32_t)0x00030000)
#define	RCC_CSR_RTCEN   ((uint32_t)0x00400000)
#define	RCC_CSR_RTCRST   ((uint32_t)0x00800000)
#define	RCC_CSR_RMVF   ((uint32_t)0x01000000)
#define	RCC_CSR_OBLRSTF   ((uint32_t)0x02000000)
#define	RCC_CSR_PINRSTF   ((uint32_t)0x04000000)
#define	RCC_CSR_PORRSTF   ((uint32_t)0x08000000)
#define	RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)
#define	RCC_CSR_IWDGRSTF   ((uint32_t)0x20000000)
#define	RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)
#define	RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)
#define	RTC_TR_PM   ((uint32_t)0x00400000)
#define	RTC_TR_HT   ((uint32_t)0x00300000)
#define	RTC_TR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TR_HU   ((uint32_t)0x000F0000)
#define	RTC_TR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TR_MNT   ((uint32_t)0x00007000)
#define	RTC_TR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TR_ST   ((uint32_t)0x00000070)
#define	RTC_TR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TR_SU   ((uint32_t)0x0000000F)
#define	RTC_TR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TR_SU_3   ((uint32_t)0x00000008)
#define	RTC_DR_YT   ((uint32_t)0x00F00000)
#define	RTC_DR_YT_0   ((uint32_t)0x00100000)
#define	RTC_DR_YT_1   ((uint32_t)0x00200000)
#define	RTC_DR_YT_2   ((uint32_t)0x00400000)
#define	RTC_DR_YT_3   ((uint32_t)0x00800000)
#define	RTC_DR_YU   ((uint32_t)0x000F0000)
#define	RTC_DR_YU_0   ((uint32_t)0x00010000)
#define	RTC_DR_YU_1   ((uint32_t)0x00020000)
#define	RTC_DR_YU_2   ((uint32_t)0x00040000)
#define	RTC_DR_YU_3   ((uint32_t)0x00080000)
#define	RTC_DR_WDU   ((uint32_t)0x0000E000)
#define	RTC_DR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_DR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_DR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_DR_MT   ((uint32_t)0x00001000)
#define	RTC_DR_MU   ((uint32_t)0x00000F00)
#define	RTC_DR_MU_0   ((uint32_t)0x00000100)
#define	RTC_DR_MU_1   ((uint32_t)0x00000200)
#define	RTC_DR_MU_2   ((uint32_t)0x00000400)
#define	RTC_DR_MU_3   ((uint32_t)0x00000800)
#define	RTC_DR_DT   ((uint32_t)0x00000030)
#define	RTC_DR_DT_0   ((uint32_t)0x00000010)
#define	RTC_DR_DT_1   ((uint32_t)0x00000020)
#define	RTC_DR_DU   ((uint32_t)0x0000000F)
#define	RTC_DR_DU_0   ((uint32_t)0x00000001)
#define	RTC_DR_DU_1   ((uint32_t)0x00000002)
#define	RTC_DR_DU_2   ((uint32_t)0x00000004)
#define	RTC_DR_DU_3   ((uint32_t)0x00000008)
#define	RTC_CR_COE   ((uint32_t)0x00800000)
#define	RTC_CR_OSEL   ((uint32_t)0x00600000)
#define	RTC_CR_OSEL_0   ((uint32_t)0x00200000)
#define	RTC_CR_OSEL_1   ((uint32_t)0x00400000)
#define	RTC_CR_POL   ((uint32_t)0x00100000)
#define	RTC_CR_COSEL   ((uint32_t)0x00080000)
#define	RTC_CR_BCK   ((uint32_t)0x00040000)
#define	RTC_CR_SUB1H   ((uint32_t)0x00020000)
#define	RTC_CR_ADD1H   ((uint32_t)0x00010000)
#define	RTC_CR_TSIE   ((uint32_t)0x00008000)
#define	RTC_CR_WUTIE   ((uint32_t)0x00004000)
#define	RTC_CR_ALRBIE   ((uint32_t)0x00002000)
#define	RTC_CR_ALRAIE   ((uint32_t)0x00001000)
#define	RTC_CR_TSE   ((uint32_t)0x00000800)
#define	RTC_CR_WUTE   ((uint32_t)0x00000400)
#define	RTC_CR_ALRBE   ((uint32_t)0x00000200)
#define	RTC_CR_ALRAE   ((uint32_t)0x00000100)
#define	RTC_CR_DCE   ((uint32_t)0x00000080)
#define	RTC_CR_FMT   ((uint32_t)0x00000040)
#define	RTC_CR_BYPSHAD   ((uint32_t)0x00000020)
#define	RTC_CR_REFCKON   ((uint32_t)0x00000010)
#define	RTC_CR_TSEDGE   ((uint32_t)0x00000008)
#define	RTC_CR_WUCKSEL   ((uint32_t)0x00000007)
#define	RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)
#define	RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)
#define	RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)
#define	RTC_ISR_RECALPF   ((uint32_t)0x00010000)
#define	RTC_ISR_TAMP3F   ((uint32_t)0x00008000)
#define	RTC_ISR_TAMP2F   ((uint32_t)0x00004000)
#define	RTC_ISR_TAMP1F   ((uint32_t)0x00002000)
#define	RTC_ISR_TSOVF   ((uint32_t)0x00001000)
#define	RTC_ISR_TSF   ((uint32_t)0x00000800)
#define	RTC_ISR_WUTF   ((uint32_t)0x00000400)
#define	RTC_ISR_ALRBF   ((uint32_t)0x00000200)
#define	RTC_ISR_ALRAF   ((uint32_t)0x00000100)
#define	RTC_ISR_INIT   ((uint32_t)0x00000080)
#define	RTC_ISR_INITF   ((uint32_t)0x00000040)
#define	RTC_ISR_RSF   ((uint32_t)0x00000020)
#define	RTC_ISR_INITS   ((uint32_t)0x00000010)
#define	RTC_ISR_SHPF   ((uint32_t)0x00000008)
#define	RTC_ISR_WUTWF   ((uint32_t)0x00000004)
#define	RTC_ISR_ALRBWF   ((uint32_t)0x00000002)
#define	RTC_ISR_ALRAWF   ((uint32_t)0x00000001)
#define	RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)
#define	RTC_PRER_PREDIV_S   ((uint32_t)0x00007FFF)
#define	RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)
#define	RTC_CALIBR_DCS   ((uint32_t)0x00000080)
#define	RTC_CALIBR_DC   ((uint32_t)0x0000001F)
#define	RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMAR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMAR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMAR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMAR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMAR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMAR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMAR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMAR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)
#define	RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)
#define	RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)
#define	RTC_ALRMBR_DT   ((uint32_t)0x30000000)
#define	RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)
#define	RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)
#define	RTC_ALRMBR_DU   ((uint32_t)0x0F000000)
#define	RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)
#define	RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)
#define	RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)
#define	RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)
#define	RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)
#define	RTC_ALRMBR_PM   ((uint32_t)0x00400000)
#define	RTC_ALRMBR_HT   ((uint32_t)0x00300000)
#define	RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)
#define	RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)
#define	RTC_ALRMBR_HU   ((uint32_t)0x000F0000)
#define	RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)
#define	RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)
#define	RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)
#define	RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)
#define	RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)
#define	RTC_ALRMBR_MNT   ((uint32_t)0x00007000)
#define	RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)
#define	RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)
#define	RTC_ALRMBR_ST   ((uint32_t)0x00000070)
#define	RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)
#define	RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)
#define	RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)
#define	RTC_ALRMBR_SU   ((uint32_t)0x0000000F)
#define	RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)
#define	RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)
#define	RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)
#define	RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)
#define	RTC_WPR_KEY   ((uint32_t)0x000000FF)
#define	RTC_SSR_SS   ((uint32_t)0x0000FFFF)
#define	RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)
#define	RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)
#define	RTC_TSTR_PM   ((uint32_t)0x00400000)
#define	RTC_TSTR_HT   ((uint32_t)0x00300000)
#define	RTC_TSTR_HT_0   ((uint32_t)0x00100000)
#define	RTC_TSTR_HT_1   ((uint32_t)0x00200000)
#define	RTC_TSTR_HU   ((uint32_t)0x000F0000)
#define	RTC_TSTR_HU_0   ((uint32_t)0x00010000)
#define	RTC_TSTR_HU_1   ((uint32_t)0x00020000)
#define	RTC_TSTR_HU_2   ((uint32_t)0x00040000)
#define	RTC_TSTR_HU_3   ((uint32_t)0x00080000)
#define	RTC_TSTR_MNT   ((uint32_t)0x00007000)
#define	RTC_TSTR_MNT_0   ((uint32_t)0x00001000)
#define	RTC_TSTR_MNT_1   ((uint32_t)0x00002000)
#define	RTC_TSTR_MNT_2   ((uint32_t)0x00004000)
#define	RTC_TSTR_MNU   ((uint32_t)0x00000F00)
#define	RTC_TSTR_MNU_0   ((uint32_t)0x00000100)
#define	RTC_TSTR_MNU_1   ((uint32_t)0x00000200)
#define	RTC_TSTR_MNU_2   ((uint32_t)0x00000400)
#define	RTC_TSTR_MNU_3   ((uint32_t)0x00000800)
#define	RTC_TSTR_ST   ((uint32_t)0x00000070)
#define	RTC_TSTR_ST_0   ((uint32_t)0x00000010)
#define	RTC_TSTR_ST_1   ((uint32_t)0x00000020)
#define	RTC_TSTR_ST_2   ((uint32_t)0x00000040)
#define	RTC_TSTR_SU   ((uint32_t)0x0000000F)
#define	RTC_TSTR_SU_0   ((uint32_t)0x00000001)
#define	RTC_TSTR_SU_1   ((uint32_t)0x00000002)
#define	RTC_TSTR_SU_2   ((uint32_t)0x00000004)
#define	RTC_TSTR_SU_3   ((uint32_t)0x00000008)
#define	RTC_TSDR_WDU   ((uint32_t)0x0000E000)
#define	RTC_TSDR_WDU_0   ((uint32_t)0x00002000)
#define	RTC_TSDR_WDU_1   ((uint32_t)0x00004000)
#define	RTC_TSDR_WDU_2   ((uint32_t)0x00008000)
#define	RTC_TSDR_MT   ((uint32_t)0x00001000)
#define	RTC_TSDR_MU   ((uint32_t)0x00000F00)
#define	RTC_TSDR_MU_0   ((uint32_t)0x00000100)
#define	RTC_TSDR_MU_1   ((uint32_t)0x00000200)
#define	RTC_TSDR_MU_2   ((uint32_t)0x00000400)
#define	RTC_TSDR_MU_3   ((uint32_t)0x00000800)
#define	RTC_TSDR_DT   ((uint32_t)0x00000030)
#define	RTC_TSDR_DT_0   ((uint32_t)0x00000010)
#define	RTC_TSDR_DT_1   ((uint32_t)0x00000020)
#define	RTC_TSDR_DU   ((uint32_t)0x0000000F)
#define	RTC_TSDR_DU_0   ((uint32_t)0x00000001)
#define	RTC_TSDR_DU_1   ((uint32_t)0x00000002)
#define	RTC_TSDR_DU_2   ((uint32_t)0x00000004)
#define	RTC_TSDR_DU_3   ((uint32_t)0x00000008)
#define	RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)
#define	RTC_CALR_CALP   ((uint32_t)0x00008000)
#define	RTC_CALR_CALW8   ((uint32_t)0x00004000)
#define	RTC_CALR_CALW16   ((uint32_t)0x00002000)
#define	RTC_CALR_CALM   ((uint32_t)0x000001FF)
#define	RTC_CALR_CALM_0   ((uint32_t)0x00000001)
#define	RTC_CALR_CALM_1   ((uint32_t)0x00000002)
#define	RTC_CALR_CALM_2   ((uint32_t)0x00000004)
#define	RTC_CALR_CALM_3   ((uint32_t)0x00000008)
#define	RTC_CALR_CALM_4   ((uint32_t)0x00000010)
#define	RTC_CALR_CALM_5   ((uint32_t)0x00000020)
#define	RTC_CALR_CALM_6   ((uint32_t)0x00000040)
#define	RTC_CALR_CALM_7   ((uint32_t)0x00000080)
#define	RTC_CALR_CALM_8   ((uint32_t)0x00000100)
#define	RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)
#define	RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)
#define	RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)
#define	RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)
#define	RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)
#define	RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)
#define	RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)
#define	RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)
#define	RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)
#define	RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)
#define	RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)
#define	RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)
#define	RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)
#define	RTC_TAFCR_TAMP3TRG   ((uint32_t)0x00000040)
#define	RTC_TAFCR_TAMP3E   ((uint32_t)0x00000020)
#define	RTC_TAFCR_TAMP2TRG   ((uint32_t)0x00000010)
#define	RTC_TAFCR_TAMP2E   ((uint32_t)0x00000008)
#define	RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)
#define	RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)
#define	RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)
#define	RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)
#define	RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)
#define	RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)
#define	RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)
#define	RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)
#define	RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)
#define	RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)
#define	RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)
#define	RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)
#define	RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)
#define	RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)
#define	RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)
#define	RTC_BKP0R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP1R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP2R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP3R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP4R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP5R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP6R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP7R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP8R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP9R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP10R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP11R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP12R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP13R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP14R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP15R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP16R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP17R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP18R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP19R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP20R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP21R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP22R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP23R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP24R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP25R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP26R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP27R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP28R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP29R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP30R   ((uint32_t)0xFFFFFFFF)
#define	RTC_BKP31R   ((uint32_t)0xFFFFFFFF)
#define	SDIO_POWER_PWRCTRL   ((uint8_t)0x03)
#define	SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)
#define	SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)
#define	SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)
#define	SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)
#define	SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)
#define	SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)
#define	SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)
#define	SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)
#define	SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)
#define	SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)
#define	SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)
#define	SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)
#define	SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)
#define	SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)
#define	SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)
#define	SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)
#define	SDIO_CMD_WAITINT   ((uint16_t)0x0100)
#define	SDIO_CMD_WAITPEND   ((uint16_t)0x0200)
#define	SDIO_CMD_CPSMEN   ((uint16_t)0x0400)
#define	SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)
#define	SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)
#define	SDIO_CMD_NIEN   ((uint16_t)0x2000)
#define	SDIO_CMD_CEATACMD   ((uint16_t)0x4000)
#define	SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)
#define	SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)
#define	SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)
#define	SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)
#define	SDIO_DCTRL_DTEN   ((uint16_t)0x0001)
#define	SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)
#define	SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)
#define	SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)
#define	SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)
#define	SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)
#define	SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)
#define	SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)
#define	SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)
#define	SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)
#define	SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)
#define	SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)
#define	SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)
#define	SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)
#define	SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)
#define	SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)
#define	SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)
#define	SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)
#define	SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)
#define	SDIO_STA_RXOVERR   ((uint32_t)0x00000020)
#define	SDIO_STA_CMDREND   ((uint32_t)0x00000040)
#define	SDIO_STA_CMDSENT   ((uint32_t)0x00000080)
#define	SDIO_STA_DATAEND   ((uint32_t)0x00000100)
#define	SDIO_STA_STBITERR   ((uint32_t)0x00000200)
#define	SDIO_STA_DBCKEND   ((uint32_t)0x00000400)
#define	SDIO_STA_CMDACT   ((uint32_t)0x00000800)
#define	SDIO_STA_TXACT   ((uint32_t)0x00001000)
#define	SDIO_STA_RXACT   ((uint32_t)0x00002000)
#define	SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)
#define	SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)
#define	SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)
#define	SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)
#define	SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)
#define	SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)
#define	SDIO_STA_TXDAVL   ((uint32_t)0x00100000)
#define	SDIO_STA_RXDAVL   ((uint32_t)0x00200000)
#define	SDIO_STA_SDIOIT   ((uint32_t)0x00400000)
#define	SDIO_STA_CEATAEND   ((uint32_t)0x00800000)
#define	SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)
#define	SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)
#define	SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)
#define	SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)
#define	SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)
#define	SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)
#define	SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)
#define	SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)
#define	SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)
#define	SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)
#define	SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)
#define	SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)
#define	SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)
#define	SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)
#define	SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)
#define	SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)
#define	SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)
#define	SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)
#define	SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)
#define	SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)
#define	SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)
#define	SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)
#define	SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)
#define	SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)
#define	SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)
#define	SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)
#define	SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)
#define	SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)
#define	SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)
#define	SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)
#define	SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)
#define	SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)
#define	SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)
#define	SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)
#define	SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)
#define	SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)
#define	SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)
#define	SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)
#define	SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)
#define	SPI_CR1_CPHA   ((uint16_t)0x0001)
#define	SPI_CR1_CPOL   ((uint16_t)0x0002)
#define	SPI_CR1_MSTR   ((uint16_t)0x0004)
#define	SPI_CR1_BR   ((uint16_t)0x0038)
#define	SPI_CR1_BR_0   ((uint16_t)0x0008)
#define	SPI_CR1_BR_1   ((uint16_t)0x0010)
#define	SPI_CR1_BR_2   ((uint16_t)0x0020)
#define	SPI_CR1_SPE   ((uint16_t)0x0040)
#define	SPI_CR1_LSBFIRST   ((uint16_t)0x0080)
#define	SPI_CR1_SSI   ((uint16_t)0x0100)
#define	SPI_CR1_SSM   ((uint16_t)0x0200)
#define	SPI_CR1_RXONLY   ((uint16_t)0x0400)
#define	SPI_CR1_DFF   ((uint16_t)0x0800)
#define	SPI_CR1_CRCNEXT   ((uint16_t)0x1000)
#define	SPI_CR1_CRCEN   ((uint16_t)0x2000)
#define	SPI_CR1_BIDIOE   ((uint16_t)0x4000)
#define	SPI_CR1_BIDIMODE   ((uint16_t)0x8000)
#define	SPI_CR2_RXDMAEN   ((uint8_t)0x01)
#define	SPI_CR2_TXDMAEN   ((uint8_t)0x02)
#define	SPI_CR2_SSOE   ((uint8_t)0x04)
#define	SPI_CR2_FRF   ((uint8_t)0x08)
#define	SPI_CR2_ERRIE   ((uint8_t)0x20)
#define	SPI_CR2_RXNEIE   ((uint8_t)0x40)
#define	SPI_CR2_TXEIE   ((uint8_t)0x80)
#define	SPI_SR_RXNE   ((uint8_t)0x01)
#define	SPI_SR_TXE   ((uint8_t)0x02)
#define	SPI_SR_CHSIDE   ((uint8_t)0x04)
#define	SPI_SR_UDR   ((uint8_t)0x08)
#define	SPI_SR_CRCERR   ((uint8_t)0x10)
#define	SPI_SR_MODF   ((uint8_t)0x20)
#define	SPI_SR_OVR   ((uint8_t)0x40)
#define	SPI_SR_BSY   ((uint8_t)0x80)
#define	SPI_DR_DR   ((uint16_t)0xFFFF)
#define	SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)
#define	SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)
#define	SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)
#define	SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)
#define	SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)
#define	SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)
#define	SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)
#define	SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)
#define	SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)
#define	SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)
#define	SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)
#define	SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)
#define	SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)
#define	SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)
#define	SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)
#define	SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)
#define	SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)
#define	SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)
#define	SPI_I2SPR_ODD   ((uint16_t)0x0100)
#define	SPI_I2SPR_MCKOE   ((uint16_t)0x0200)
#define	SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)
#define	SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)
#define	SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)
#define	SYSCFG_MEMRMP_BOOT_MODE   ((uint32_t)0x00000300)
#define	SYSCFG_MEMRMP_BOOT_MODE_0   ((uint32_t)0x00000100)
#define	SYSCFG_MEMRMP_BOOT_MODE_1   ((uint32_t)0x00000200)
#define	SYSCFG_PMC_USB_PU   ((uint32_t)0x00000001)
#define	SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)
	EXTI0 configuration.
#define	SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0005)
#define	SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)
	EXTI1 configuration.
#define	SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0050)
#define	SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)
	EXTI2 configuration.
#define	SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0500)
#define	SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)
	EXTI3 configuration.
#define	SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)
	EXTI4 configuration.
#define	SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)
	EXTI5 configuration.
#define	SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)
	EXTI6 configuration.
#define	SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)
	EXTI7 configuration.
#define	SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)
	EXTI8 configuration.
#define	SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)
	EXTI9 configuration.
#define	SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)
	EXTI10 configuration.
#define	SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)
	EXTI11 configuration.
#define	SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x7000)
#define	SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)
#define	SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)
#define	SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)
#define	SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)
#define	SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)
	EXTI12 configuration.
#define	SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)
#define	SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)
#define	SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)
#define	SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)
#define	SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0006)
#define	SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0007)
#define	SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)
	EXTI13 configuration.
#define	SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)
#define	SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)
#define	SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)
#define	SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)
#define	SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0060)
#define	SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0070)
#define	SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)
	EXTI14 configuration.
#define	SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)
#define	SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)
#define	SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)
#define	SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)
#define	SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0600)
#define	SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0700)
#define	SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)
	EXTI15 configuration.
#define	SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)
#define	SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)
#define	SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)
#define	SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)
#define	SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x6000)
#define	SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x7000)
#define	RI_ICR_IC1Z   ((uint32_t)0x0000000F)
#define	RI_ICR_IC1Z_0   ((uint32_t)0x00000001)
#define	RI_ICR_IC1Z_1   ((uint32_t)0x00000002)
#define	RI_ICR_IC1Z_2   ((uint32_t)0x00000004)
#define	RI_ICR_IC1Z_3   ((uint32_t)0x00000008)
#define	RI_ICR_IC2Z   ((uint32_t)0x000000F0)
#define	RI_ICR_IC2Z_0   ((uint32_t)0x00000010)
#define	RI_ICR_IC2Z_1   ((uint32_t)0x00000020)
#define	RI_ICR_IC2Z_2   ((uint32_t)0x00000040)
#define	RI_ICR_IC2Z_3   ((uint32_t)0x00000080)
#define	RI_ICR_IC3Z   ((uint32_t)0x00000F00)
#define	RI_ICR_IC3Z_0   ((uint32_t)0x00000100)
#define	RI_ICR_IC3Z_1   ((uint32_t)0x00000200)
#define	RI_ICR_IC3Z_2   ((uint32_t)0x00000400)
#define	RI_ICR_IC3Z_3   ((uint32_t)0x00000800)
#define	RI_ICR_IC4Z   ((uint32_t)0x0000F000)
#define	RI_ICR_IC4Z_0   ((uint32_t)0x00001000)
#define	RI_ICR_IC4Z_1   ((uint32_t)0x00002000)
#define	RI_ICR_IC4Z_2   ((uint32_t)0x00004000)
#define	RI_ICR_IC4Z_3   ((uint32_t)0x00008000)
#define	RI_ICR_TIM   ((uint32_t)0x00030000)
#define	RI_ICR_TIM_0   ((uint32_t)0x00010000)
#define	RI_ICR_TIM_1   ((uint32_t)0x00020000)
#define	RI_ICR_IC1   ((uint32_t)0x00040000)
#define	RI_ICR_IC2   ((uint32_t)0x00080000)
#define	RI_ICR_IC3   ((uint32_t)0x00100000)
#define	RI_ICR_IC4   ((uint32_t)0x00200000)
#define	RI_ASCR1_CH   ((uint32_t)0x03FCFFFF)
#define	RI_ASCR1_CH_0   ((uint32_t)0x00000001)
#define	RI_ASCR1_CH_1   ((uint32_t)0x00000002)
#define	RI_ASCR1_CH_2   ((uint32_t)0x00000004)
#define	RI_ASCR1_CH_3   ((uint32_t)0x00000008)
#define	RI_ASCR1_CH_4   ((uint32_t)0x00000010)
#define	RI_ASCR1_CH_5   ((uint32_t)0x00000020)
#define	RI_ASCR1_CH_6   ((uint32_t)0x00000040)
#define	RI_ASCR1_CH_7   ((uint32_t)0x00000080)
#define	RI_ASCR1_CH_8   ((uint32_t)0x00000100)
#define	RI_ASCR1_CH_9   ((uint32_t)0x00000200)
#define	RI_ASCR1_CH_10   ((uint32_t)0x00000400)
#define	RI_ASCR1_CH_11   ((uint32_t)0x00000800)
#define	RI_ASCR1_CH_12   ((uint32_t)0x00001000)
#define	RI_ASCR1_CH_13   ((uint32_t)0x00002000)
#define	RI_ASCR1_CH_14   ((uint32_t)0x00004000)
#define	RI_ASCR1_CH_15   ((uint32_t)0x00008000)
#define	RI_ASCR1_CH_31   ((uint32_t)0x00010000)
#define	RI_ASCR1_CH_18   ((uint32_t)0x00040000)
#define	RI_ASCR1_CH_19   ((uint32_t)0x00080000)
#define	RI_ASCR1_CH_20   ((uint32_t)0x00100000)
#define	RI_ASCR1_CH_21   ((uint32_t)0x00200000)
#define	RI_ASCR1_CH_22   ((uint32_t)0x00400000)
#define	RI_ASCR1_CH_23   ((uint32_t)0x00800000)
#define	RI_ASCR1_CH_24   ((uint32_t)0x01000000)
#define	RI_ASCR1_CH_25   ((uint32_t)0x02000000)
#define	RI_ASCR1_VCOMP   ((uint32_t)0x04000000)
#define	RI_ASCR1_CH_27   ((uint32_t)0x00400000)
#define	RI_ASCR1_CH_28   ((uint32_t)0x00800000)
#define	RI_ASCR1_CH_29   ((uint32_t)0x01000000)
#define	RI_ASCR1_CH_30   ((uint32_t)0x02000000)
#define	RI_ASCR1_SCM   ((uint32_t)0x80000000)
#define	RI_ASCR2_GR10_1   ((uint32_t)0x00000001)
#define	RI_ASCR2_GR10_2   ((uint32_t)0x00000002)
#define	RI_ASCR2_GR10_3   ((uint32_t)0x00000004)
#define	RI_ASCR2_GR10_4   ((uint32_t)0x00000008)
#define	RI_ASCR2_GR6_1   ((uint32_t)0x00000010)
#define	RI_ASCR2_GR6_2   ((uint32_t)0x00000020)
#define	RI_ASCR2_GR5_1   ((uint32_t)0x00000040)
#define	RI_ASCR2_GR5_2   ((uint32_t)0x00000080)
#define	RI_ASCR2_GR5_3   ((uint32_t)0x00000100)
#define	RI_ASCR2_GR4_1   ((uint32_t)0x00000200)
#define	RI_ASCR2_GR4_2   ((uint32_t)0x00000400)
#define	RI_ASCR2_GR4_3   ((uint32_t)0x00000800)
#define	RI_ASCR2_GR4_4   ((uint32_t)0x00008000)
#define	RI_ASCR2_CH0b   ((uint32_t)0x00010000)
#define	RI_ASCR2_CH1b   ((uint32_t)0x00020000)
#define	RI_ASCR2_CH2b   ((uint32_t)0x00040000)
#define	RI_ASCR2_CH3b   ((uint32_t)0x00080000)
#define	RI_ASCR2_CH6b   ((uint32_t)0x00100000)
#define	RI_ASCR2_CH7b   ((uint32_t)0x00200000)
#define	RI_ASCR2_CH8b   ((uint32_t)0x00400000)
#define	RI_ASCR2_CH9b   ((uint32_t)0x00800000)
#define	RI_ASCR2_CH10b   ((uint32_t)0x01000000)
#define	RI_ASCR2_CH11b   ((uint32_t)0x02000000)
#define	RI_ASCR2_CH12b   ((uint32_t)0x04000000)
#define	RI_ASCR2_GR6_3   ((uint32_t)0x08000000)
#define	RI_ASCR2_GR6_4   ((uint32_t)0x10000000)
#define	RI_ASCR2_GR5_4   ((uint32_t)0x20000000)
#define	RI_HYSCR1_PA   ((uint32_t)0x0000FFFF)
#define	RI_HYSCR1_PA_0   ((uint32_t)0x00000001)
#define	RI_HYSCR1_PA_1   ((uint32_t)0x00000002)
#define	RI_HYSCR1_PA_2   ((uint32_t)0x00000004)
#define	RI_HYSCR1_PA_3   ((uint32_t)0x00000008)
#define	RI_HYSCR1_PA_4   ((uint32_t)0x00000010)
#define	RI_HYSCR1_PA_5   ((uint32_t)0x00000020)
#define	RI_HYSCR1_PA_6   ((uint32_t)0x00000040)
#define	RI_HYSCR1_PA_7   ((uint32_t)0x00000080)
#define	RI_HYSCR1_PA_8   ((uint32_t)0x00000100)
#define	RI_HYSCR1_PA_9   ((uint32_t)0x00000200)
#define	RI_HYSCR1_PA_10   ((uint32_t)0x00000400)
#define	RI_HYSCR1_PA_11   ((uint32_t)0x00000800)
#define	RI_HYSCR1_PA_12   ((uint32_t)0x00001000)
#define	RI_HYSCR1_PA_13   ((uint32_t)0x00002000)
#define	RI_HYSCR1_PA_14   ((uint32_t)0x00004000)
#define	RI_HYSCR1_PA_15   ((uint32_t)0x00008000)
#define	RI_HYSCR1_PB   ((uint32_t)0xFFFF0000)
#define	RI_HYSCR1_PB_0   ((uint32_t)0x00010000)
#define	RI_HYSCR1_PB_1   ((uint32_t)0x00020000)
#define	RI_HYSCR1_PB_2   ((uint32_t)0x00040000)
#define	RI_HYSCR1_PB_3   ((uint32_t)0x00080000)
#define	RI_HYSCR1_PB_4   ((uint32_t)0x00100000)
#define	RI_HYSCR1_PB_5   ((uint32_t)0x00200000)
#define	RI_HYSCR1_PB_6   ((uint32_t)0x00400000)
#define	RI_HYSCR1_PB_7   ((uint32_t)0x00800000)
#define	RI_HYSCR1_PB_8   ((uint32_t)0x01000000)
#define	RI_HYSCR1_PB_9   ((uint32_t)0x02000000)
#define	RI_HYSCR1_PB_10   ((uint32_t)0x04000000)
#define	RI_HYSCR1_PB_11   ((uint32_t)0x08000000)
#define	RI_HYSCR1_PB_12   ((uint32_t)0x10000000)
#define	RI_HYSCR1_PB_13   ((uint32_t)0x20000000)
#define	RI_HYSCR1_PB_14   ((uint32_t)0x40000000)
#define	RI_HYSCR1_PB_15   ((uint32_t)0x80000000)
#define	RI_HYSCR2_PC   ((uint32_t)0x0000FFFF)
#define	RI_HYSCR2_PC_0   ((uint32_t)0x00000001)
#define	RI_HYSCR2_PC_1   ((uint32_t)0x00000002)
#define	RI_HYSCR2_PC_2   ((uint32_t)0x00000004)
#define	RI_HYSCR2_PC_3   ((uint32_t)0x00000008)
#define	RI_HYSCR2_PC_4   ((uint32_t)0x00000010)
#define	RI_HYSCR2_PC_5   ((uint32_t)0x00000020)
#define	RI_HYSCR2_PC_6   ((uint32_t)0x00000040)
#define	RI_HYSCR2_PC_7   ((uint32_t)0x00000080)
#define	RI_HYSCR2_PC_8   ((uint32_t)0x00000100)
#define	RI_HYSCR2_PC_9   ((uint32_t)0x00000200)
#define	RI_HYSCR2_PC_10   ((uint32_t)0x00000400)
#define	RI_HYSCR2_PC_11   ((uint32_t)0x00000800)
#define	RI_HYSCR2_PC_12   ((uint32_t)0x00001000)
#define	RI_HYSCR2_PC_13   ((uint32_t)0x00002000)
#define	RI_HYSCR2_PC_14   ((uint32_t)0x00004000)
#define	RI_HYSCR2_PC_15   ((uint32_t)0x00008000)
#define	RI_HYSCR2_PD   ((uint32_t)0xFFFF0000)
#define	RI_HYSCR2_PD_0   ((uint32_t)0x00010000)
#define	RI_HYSCR2_PD_1   ((uint32_t)0x00020000)
#define	RI_HYSCR2_PD_2   ((uint32_t)0x00040000)
#define	RI_HYSCR2_PD_3   ((uint32_t)0x00080000)
#define	RI_HYSCR2_PD_4   ((uint32_t)0x00100000)
#define	RI_HYSCR2_PD_5   ((uint32_t)0x00200000)
#define	RI_HYSCR2_PD_6   ((uint32_t)0x00400000)
#define	RI_HYSCR2_PD_7   ((uint32_t)0x00800000)
#define	RI_HYSCR2_PD_8   ((uint32_t)0x01000000)
#define	RI_HYSCR2_PD_9   ((uint32_t)0x02000000)
#define	RI_HYSCR2_PD_10   ((uint32_t)0x04000000)
#define	RI_HYSCR2_PD_11   ((uint32_t)0x08000000)
#define	RI_HYSCR2_PD_12   ((uint32_t)0x10000000)
#define	RI_HYSCR2_PD_13   ((uint32_t)0x20000000)
#define	RI_HYSCR2_PD_14   ((uint32_t)0x40000000)
#define	RI_HYSCR2_PD_15   ((uint32_t)0x80000000)
#define	RI_HYSCR2_PE   ((uint32_t)0x0000FFFF)
#define	RI_HYSCR2_PE_0   ((uint32_t)0x00000001)
#define	RI_HYSCR2_PE_1   ((uint32_t)0x00000002)
#define	RI_HYSCR2_PE_2   ((uint32_t)0x00000004)
#define	RI_HYSCR2_PE_3   ((uint32_t)0x00000008)
#define	RI_HYSCR2_PE_4   ((uint32_t)0x00000010)
#define	RI_HYSCR2_PE_5   ((uint32_t)0x00000020)
#define	RI_HYSCR2_PE_6   ((uint32_t)0x00000040)
#define	RI_HYSCR2_PE_7   ((uint32_t)0x00000080)
#define	RI_HYSCR2_PE_8   ((uint32_t)0x00000100)
#define	RI_HYSCR2_PE_9   ((uint32_t)0x00000200)
#define	RI_HYSCR2_PE_10   ((uint32_t)0x00000400)
#define	RI_HYSCR2_PE_11   ((uint32_t)0x00000800)
#define	RI_HYSCR2_PE_12   ((uint32_t)0x00001000)
#define	RI_HYSCR2_PE_13   ((uint32_t)0x00002000)
#define	RI_HYSCR2_PE_14   ((uint32_t)0x00004000)
#define	RI_HYSCR2_PE_15   ((uint32_t)0x00008000)
#define	RI_HYSCR3_PF   ((uint32_t)0xFFFF0000)
#define	RI_HYSCR3_PF_0   ((uint32_t)0x00010000)
#define	RI_HYSCR3_PF_1   ((uint32_t)0x00020000)
#define	RI_HYSCR3_PF_2   ((uint32_t)0x00040000)
#define	RI_HYSCR3_PF_3   ((uint32_t)0x00080000)
#define	RI_HYSCR3_PF_4   ((uint32_t)0x00100000)
#define	RI_HYSCR3_PF_5   ((uint32_t)0x00200000)
#define	RI_HYSCR3_PF_6   ((uint32_t)0x00400000)
#define	RI_HYSCR3_PF_7   ((uint32_t)0x00800000)
#define	RI_HYSCR3_PF_8   ((uint32_t)0x01000000)
#define	RI_HYSCR3_PF_9   ((uint32_t)0x02000000)
#define	RI_HYSCR3_PF_10   ((uint32_t)0x04000000)
#define	RI_HYSCR3_PF_11   ((uint32_t)0x08000000)
#define	RI_HYSCR3_PF_12   ((uint32_t)0x10000000)
#define	RI_HYSCR3_PF_13   ((uint32_t)0x20000000)
#define	RI_HYSCR3_PF_14   ((uint32_t)0x40000000)
#define	RI_HYSCR3_PF_15   ((uint32_t)0x80000000)
#define	RI_HYSCR4_PG   ((uint32_t)0x0000FFFF)
#define	RI_HYSCR4_PG_0   ((uint32_t)0x00000001)
#define	RI_HYSCR4_PG_1   ((uint32_t)0x00000002)
#define	RI_HYSCR4_PG_2   ((uint32_t)0x00000004)
#define	RI_HYSCR4_PG_3   ((uint32_t)0x00000008)
#define	RI_HYSCR4_PG_4   ((uint32_t)0x00000010)
#define	RI_HYSCR4_PG_5   ((uint32_t)0x00000020)
#define	RI_HYSCR4_PG_6   ((uint32_t)0x00000040)
#define	RI_HYSCR4_PG_7   ((uint32_t)0x00000080)
#define	RI_HYSCR4_PG_8   ((uint32_t)0x00000100)
#define	RI_HYSCR4_PG_9   ((uint32_t)0x00000200)
#define	RI_HYSCR4_PG_10   ((uint32_t)0x00000400)
#define	RI_HYSCR4_PG_11   ((uint32_t)0x00000800)
#define	RI_HYSCR4_PG_12   ((uint32_t)0x00001000)
#define	RI_HYSCR4_PG_13   ((uint32_t)0x00002000)
#define	RI_HYSCR4_PG_14   ((uint32_t)0x00004000)
#define	RI_HYSCR4_PG_15   ((uint32_t)0x00008000)
#define	TIM_CR1_CEN   ((uint16_t)0x0001)
#define	TIM_CR1_UDIS   ((uint16_t)0x0002)
#define	TIM_CR1_URS   ((uint16_t)0x0004)
#define	TIM_CR1_OPM   ((uint16_t)0x0008)
#define	TIM_CR1_DIR   ((uint16_t)0x0010)
#define	TIM_CR1_CMS   ((uint16_t)0x0060)
#define	TIM_CR1_CMS_0   ((uint16_t)0x0020)
#define	TIM_CR1_CMS_1   ((uint16_t)0x0040)
#define	TIM_CR1_ARPE   ((uint16_t)0x0080)
#define	TIM_CR1_CKD   ((uint16_t)0x0300)
#define	TIM_CR1_CKD_0   ((uint16_t)0x0100)
#define	TIM_CR1_CKD_1   ((uint16_t)0x0200)
#define	TIM_CR2_CCDS   ((uint16_t)0x0008)
#define	TIM_CR2_MMS   ((uint16_t)0x0070)
#define	TIM_CR2_MMS_0   ((uint16_t)0x0010)
#define	TIM_CR2_MMS_1   ((uint16_t)0x0020)
#define	TIM_CR2_MMS_2   ((uint16_t)0x0040)
#define	TIM_CR2_TI1S   ((uint16_t)0x0080)
#define	TIM_SMCR_SMS   ((uint16_t)0x0007)
#define	TIM_SMCR_SMS_0   ((uint16_t)0x0001)
#define	TIM_SMCR_SMS_1   ((uint16_t)0x0002)
#define	TIM_SMCR_SMS_2   ((uint16_t)0x0004)
#define	TIM_SMCR_OCCS   ((uint16_t)0x0008)
#define	TIM_SMCR_TS   ((uint16_t)0x0070)
#define	TIM_SMCR_TS_0   ((uint16_t)0x0010)
#define	TIM_SMCR_TS_1   ((uint16_t)0x0020)
#define	TIM_SMCR_TS_2   ((uint16_t)0x0040)
#define	TIM_SMCR_MSM   ((uint16_t)0x0080)
#define	TIM_SMCR_ETF   ((uint16_t)0x0F00)
#define	TIM_SMCR_ETF_0   ((uint16_t)0x0100)
#define	TIM_SMCR_ETF_1   ((uint16_t)0x0200)
#define	TIM_SMCR_ETF_2   ((uint16_t)0x0400)
#define	TIM_SMCR_ETF_3   ((uint16_t)0x0800)
#define	TIM_SMCR_ETPS   ((uint16_t)0x3000)
#define	TIM_SMCR_ETPS_0   ((uint16_t)0x1000)
#define	TIM_SMCR_ETPS_1   ((uint16_t)0x2000)
#define	TIM_SMCR_ECE   ((uint16_t)0x4000)
#define	TIM_SMCR_ETP   ((uint16_t)0x8000)
#define	TIM_DIER_UIE   ((uint16_t)0x0001)
#define	TIM_DIER_CC1IE   ((uint16_t)0x0002)
#define	TIM_DIER_CC2IE   ((uint16_t)0x0004)
#define	TIM_DIER_CC3IE   ((uint16_t)0x0008)
#define	TIM_DIER_CC4IE   ((uint16_t)0x0010)
#define	TIM_DIER_TIE   ((uint16_t)0x0040)
#define	TIM_DIER_UDE   ((uint16_t)0x0100)
#define	TIM_DIER_CC1DE   ((uint16_t)0x0200)
#define	TIM_DIER_CC2DE   ((uint16_t)0x0400)
#define	TIM_DIER_CC3DE   ((uint16_t)0x0800)
#define	TIM_DIER_CC4DE   ((uint16_t)0x1000)
#define	TIM_DIER_TDE   ((uint16_t)0x4000)
#define	TIM_SR_UIF   ((uint16_t)0x0001)
#define	TIM_SR_CC1IF   ((uint16_t)0x0002)
#define	TIM_SR_CC2IF   ((uint16_t)0x0004)
#define	TIM_SR_CC3IF   ((uint16_t)0x0008)
#define	TIM_SR_CC4IF   ((uint16_t)0x0010)
#define	TIM_SR_TIF   ((uint16_t)0x0040)
#define	TIM_SR_CC1OF   ((uint16_t)0x0200)
#define	TIM_SR_CC2OF   ((uint16_t)0x0400)
#define	TIM_SR_CC3OF   ((uint16_t)0x0800)
#define	TIM_SR_CC4OF   ((uint16_t)0x1000)
#define	TIM_EGR_UG   ((uint8_t)0x01)
#define	TIM_EGR_CC1G   ((uint8_t)0x02)
#define	TIM_EGR_CC2G   ((uint8_t)0x04)
#define	TIM_EGR_CC3G   ((uint8_t)0x08)
#define	TIM_EGR_CC4G   ((uint8_t)0x10)
#define	TIM_EGR_TG   ((uint8_t)0x40)
#define	TIM_CCMR1_CC1S   ((uint16_t)0x0003)
#define	TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)
#define	TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)
#define	TIM_CCMR1_OC1FE   ((uint16_t)0x0004)
#define	TIM_CCMR1_OC1PE   ((uint16_t)0x0008)
#define	TIM_CCMR1_OC1M   ((uint16_t)0x0070)
#define	TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_OC1CE   ((uint16_t)0x0080)
#define	TIM_CCMR1_CC2S   ((uint16_t)0x0300)
#define	TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)
#define	TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)
#define	TIM_CCMR1_OC2FE   ((uint16_t)0x0400)
#define	TIM_CCMR1_OC2PE   ((uint16_t)0x0800)
#define	TIM_CCMR1_OC2M   ((uint16_t)0x7000)
#define	TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_OC2CE   ((uint16_t)0x8000)
#define	TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)
#define	TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR1_IC1F   ((uint16_t)0x00F0)
#define	TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)
#define	TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)
#define	TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)
#define	TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)
#define	TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR1_IC2F   ((uint16_t)0xF000)
#define	TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)
#define	TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)
#define	TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)
#define	TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)
#define	TIM_CCMR2_CC3S   ((uint16_t)0x0003)
#define	TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)
#define	TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)
#define	TIM_CCMR2_OC3FE   ((uint16_t)0x0004)
#define	TIM_CCMR2_OC3PE   ((uint16_t)0x0008)
#define	TIM_CCMR2_OC3M   ((uint16_t)0x0070)
#define	TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_OC3CE   ((uint16_t)0x0080)
#define	TIM_CCMR2_CC4S   ((uint16_t)0x0300)
#define	TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)
#define	TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)
#define	TIM_CCMR2_OC4FE   ((uint16_t)0x0400)
#define	TIM_CCMR2_OC4PE   ((uint16_t)0x0800)
#define	TIM_CCMR2_OC4M   ((uint16_t)0x7000)
#define	TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_OC4CE   ((uint16_t)0x8000)
#define	TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)
#define	TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)
#define	TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)
#define	TIM_CCMR2_IC3F   ((uint16_t)0x00F0)
#define	TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)
#define	TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)
#define	TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)
#define	TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)
#define	TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)
#define	TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)
#define	TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)
#define	TIM_CCMR2_IC4F   ((uint16_t)0xF000)
#define	TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)
#define	TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)
#define	TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)
#define	TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)
#define	TIM_CCER_CC1E   ((uint16_t)0x0001)
#define	TIM_CCER_CC1P   ((uint16_t)0x0002)
#define	TIM_CCER_CC1NP   ((uint16_t)0x0008)
#define	TIM_CCER_CC2E   ((uint16_t)0x0010)
#define	TIM_CCER_CC2P   ((uint16_t)0x0020)
#define	TIM_CCER_CC2NP   ((uint16_t)0x0080)
#define	TIM_CCER_CC3E   ((uint16_t)0x0100)
#define	TIM_CCER_CC3P   ((uint16_t)0x0200)
#define	TIM_CCER_CC3NP   ((uint16_t)0x0800)
#define	TIM_CCER_CC4E   ((uint16_t)0x1000)
#define	TIM_CCER_CC4P   ((uint16_t)0x2000)
#define	TIM_CCER_CC4NP   ((uint16_t)0x8000)
#define	TIM_CNT_CNT   ((uint16_t)0xFFFF)
#define	TIM_PSC_PSC   ((uint16_t)0xFFFF)
#define	TIM_ARR_ARR   ((uint16_t)0xFFFF)
#define	TIM_CCR1_CCR1   ((uint16_t)0xFFFF)
#define	TIM_CCR2_CCR2   ((uint16_t)0xFFFF)
#define	TIM_CCR3_CCR3   ((uint16_t)0xFFFF)
#define	TIM_CCR4_CCR4   ((uint16_t)0xFFFF)
#define	TIM_DCR_DBA   ((uint16_t)0x001F)
#define	TIM_DCR_DBA_0   ((uint16_t)0x0001)
#define	TIM_DCR_DBA_1   ((uint16_t)0x0002)
#define	TIM_DCR_DBA_2   ((uint16_t)0x0004)
#define	TIM_DCR_DBA_3   ((uint16_t)0x0008)
#define	TIM_DCR_DBA_4   ((uint16_t)0x0010)
#define	TIM_DCR_DBL   ((uint16_t)0x1F00)
#define	TIM_DCR_DBL_0   ((uint16_t)0x0100)
#define	TIM_DCR_DBL_1   ((uint16_t)0x0200)
#define	TIM_DCR_DBL_2   ((uint16_t)0x0400)
#define	TIM_DCR_DBL_3   ((uint16_t)0x0800)
#define	TIM_DCR_DBL_4   ((uint16_t)0x1000)
#define	TIM_DMAR_DMAB   ((uint16_t)0xFFFF)
#define	TIM_OR_TI1RMP   ((uint16_t)0x0003)
#define	TIM_OR_TI1RMP_0   ((uint16_t)0x0001)
#define	TIM_OR_TI1RMP_1   ((uint16_t)0x0002)
#define	USART_SR_PE   ((uint16_t)0x0001)
#define	USART_SR_FE   ((uint16_t)0x0002)
#define	USART_SR_NE   ((uint16_t)0x0004)
#define	USART_SR_ORE   ((uint16_t)0x0008)
#define	USART_SR_IDLE   ((uint16_t)0x0010)
#define	USART_SR_RXNE   ((uint16_t)0x0020)
#define	USART_SR_TC   ((uint16_t)0x0040)
#define	USART_SR_TXE   ((uint16_t)0x0080)
#define	USART_SR_LBD   ((uint16_t)0x0100)
#define	USART_SR_CTS   ((uint16_t)0x0200)
#define	USART_DR_DR   ((uint16_t)0x01FF)
#define	USART_BRR_DIV_FRACTION   ((uint16_t)0x000F)
#define	USART_BRR_DIV_MANTISSA   ((uint16_t)0xFFF0)
#define	USART_CR1_SBK   ((uint16_t)0x0001)
#define	USART_CR1_RWU   ((uint16_t)0x0002)
#define	USART_CR1_RE   ((uint16_t)0x0004)
#define	USART_CR1_TE   ((uint16_t)0x0008)
#define	USART_CR1_IDLEIE   ((uint16_t)0x0010)
#define	USART_CR1_RXNEIE   ((uint16_t)0x0020)
#define	USART_CR1_TCIE   ((uint16_t)0x0040)
#define	USART_CR1_TXEIE   ((uint16_t)0x0080)
#define	USART_CR1_PEIE   ((uint16_t)0x0100)
#define	USART_CR1_PS   ((uint16_t)0x0200)
#define	USART_CR1_PCE   ((uint16_t)0x0400)
#define	USART_CR1_WAKE   ((uint16_t)0x0800)
#define	USART_CR1_M   ((uint16_t)0x1000)
#define	USART_CR1_UE   ((uint16_t)0x2000)
#define	USART_CR1_OVER8   ((uint16_t)0x8000)
#define	USART_CR2_ADD   ((uint16_t)0x000F)
#define	USART_CR2_LBDL   ((uint16_t)0x0020)
#define	USART_CR2_LBDIE   ((uint16_t)0x0040)
#define	USART_CR2_LBCL   ((uint16_t)0x0100)
#define	USART_CR2_CPHA   ((uint16_t)0x0200)
#define	USART_CR2_CPOL   ((uint16_t)0x0400)
#define	USART_CR2_CLKEN   ((uint16_t)0x0800)
#define	USART_CR2_STOP   ((uint16_t)0x3000)
#define	USART_CR2_STOP_0   ((uint16_t)0x1000)
#define	USART_CR2_STOP_1   ((uint16_t)0x2000)
#define	USART_CR2_LINEN   ((uint16_t)0x4000)
#define	USART_CR3_EIE   ((uint16_t)0x0001)
#define	USART_CR3_IREN   ((uint16_t)0x0002)
#define	USART_CR3_IRLP   ((uint16_t)0x0004)
#define	USART_CR3_HDSEL   ((uint16_t)0x0008)
#define	USART_CR3_NACK   ((uint16_t)0x0010)
#define	USART_CR3_SCEN   ((uint16_t)0x0020)
#define	USART_CR3_DMAR   ((uint16_t)0x0040)
#define	USART_CR3_DMAT   ((uint16_t)0x0080)
#define	USART_CR3_RTSE   ((uint16_t)0x0100)
#define	USART_CR3_CTSE   ((uint16_t)0x0200)
#define	USART_CR3_CTSIE   ((uint16_t)0x0400)
#define	USART_CR3_ONEBIT   ((uint16_t)0x0800)
#define	USART_GTPR_PSC   ((uint16_t)0x00FF)
#define	USART_GTPR_PSC_0   ((uint16_t)0x0001)
#define	USART_GTPR_PSC_1   ((uint16_t)0x0002)
#define	USART_GTPR_PSC_2   ((uint16_t)0x0004)
#define	USART_GTPR_PSC_3   ((uint16_t)0x0008)
#define	USART_GTPR_PSC_4   ((uint16_t)0x0010)
#define	USART_GTPR_PSC_5   ((uint16_t)0x0020)
#define	USART_GTPR_PSC_6   ((uint16_t)0x0040)
#define	USART_GTPR_PSC_7   ((uint16_t)0x0080)
#define	USART_GTPR_GT   ((uint16_t)0xFF00)
#define	USB_EP0R_EA   ((uint16_t)0x000F)
#define	USB_EP0R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP0R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP0R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP0R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP0R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP0R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP0R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP0R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP0R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP0R_SETUP   ((uint16_t)0x0800)
#define	USB_EP0R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP0R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP0R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP0R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP0R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP1R_EA   ((uint16_t)0x000F)
#define	USB_EP1R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP1R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP1R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP1R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP1R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP1R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP1R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP1R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP1R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP1R_SETUP   ((uint16_t)0x0800)
#define	USB_EP1R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP1R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP1R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP1R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP1R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP2R_EA   ((uint16_t)0x000F)
#define	USB_EP2R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP2R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP2R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP2R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP2R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP2R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP2R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP2R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP2R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP2R_SETUP   ((uint16_t)0x0800)
#define	USB_EP2R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP2R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP2R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP2R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP2R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP3R_EA   ((uint16_t)0x000F)
#define	USB_EP3R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP3R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP3R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP3R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP3R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP3R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP3R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP3R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP3R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP3R_SETUP   ((uint16_t)0x0800)
#define	USB_EP3R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP3R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP3R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP3R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP3R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP4R_EA   ((uint16_t)0x000F)
#define	USB_EP4R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP4R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP4R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP4R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP4R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP4R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP4R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP4R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP4R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP4R_SETUP   ((uint16_t)0x0800)
#define	USB_EP4R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP4R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP4R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP4R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP4R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP5R_EA   ((uint16_t)0x000F)
#define	USB_EP5R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP5R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP5R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP5R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP5R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP5R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP5R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP5R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP5R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP5R_SETUP   ((uint16_t)0x0800)
#define	USB_EP5R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP5R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP5R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP5R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP5R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP6R_EA   ((uint16_t)0x000F)
#define	USB_EP6R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP6R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP6R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP6R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP6R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP6R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP6R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP6R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP6R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP6R_SETUP   ((uint16_t)0x0800)
#define	USB_EP6R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP6R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP6R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP6R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP6R_CTR_RX   ((uint16_t)0x8000)
#define	USB_EP7R_EA   ((uint16_t)0x000F)
#define	USB_EP7R_STAT_TX   ((uint16_t)0x0030)
#define	USB_EP7R_STAT_TX_0   ((uint16_t)0x0010)
#define	USB_EP7R_STAT_TX_1   ((uint16_t)0x0020)
#define	USB_EP7R_DTOG_TX   ((uint16_t)0x0040)
#define	USB_EP7R_CTR_TX   ((uint16_t)0x0080)
#define	USB_EP7R_EP_KIND   ((uint16_t)0x0100)
#define	USB_EP7R_EP_TYPE   ((uint16_t)0x0600)
#define	USB_EP7R_EP_TYPE_0   ((uint16_t)0x0200)
#define	USB_EP7R_EP_TYPE_1   ((uint16_t)0x0400)
#define	USB_EP7R_SETUP   ((uint16_t)0x0800)
#define	USB_EP7R_STAT_RX   ((uint16_t)0x3000)
#define	USB_EP7R_STAT_RX_0   ((uint16_t)0x1000)
#define	USB_EP7R_STAT_RX_1   ((uint16_t)0x2000)
#define	USB_EP7R_DTOG_RX   ((uint16_t)0x4000)
#define	USB_EP7R_CTR_RX   ((uint16_t)0x8000)
#define	USB_CNTR_FRES   ((uint16_t)0x0001)
#define	USB_CNTR_PDWN   ((uint16_t)0x0002)
#define	USB_CNTR_LP_MODE   ((uint16_t)0x0004)
#define	USB_CNTR_FSUSP   ((uint16_t)0x0008)
#define	USB_CNTR_RESUME   ((uint16_t)0x0010)
#define	USB_CNTR_ESOFM   ((uint16_t)0x0100)
#define	USB_CNTR_SOFM   ((uint16_t)0x0200)
#define	USB_CNTR_RESETM   ((uint16_t)0x0400)
#define	USB_CNTR_SUSPM   ((uint16_t)0x0800)
#define	USB_CNTR_WKUPM   ((uint16_t)0x1000)
#define	USB_CNTR_ERRM   ((uint16_t)0x2000)
#define	USB_CNTR_PMAOVRM   ((uint16_t)0x4000)
#define	USB_CNTR_CTRM   ((uint16_t)0x8000)
#define	USB_ISTR_EP_ID   ((uint16_t)0x000F)
#define	USB_ISTR_DIR   ((uint16_t)0x0010)
#define	USB_ISTR_ESOF   ((uint16_t)0x0100)
#define	USB_ISTR_SOF   ((uint16_t)0x0200)
#define	USB_ISTR_RESET   ((uint16_t)0x0400)
#define	USB_ISTR_SUSP   ((uint16_t)0x0800)
#define	USB_ISTR_WKUP   ((uint16_t)0x1000)
#define	USB_ISTR_ERR   ((uint16_t)0x2000)
#define	USB_ISTR_PMAOVR   ((uint16_t)0x4000)
#define	USB_ISTR_CTR   ((uint16_t)0x8000)
#define	USB_FNR_FN   ((uint16_t)0x07FF)
#define	USB_FNR_LSOF   ((uint16_t)0x1800)
#define	USB_FNR_LCK   ((uint16_t)0x2000)
#define	USB_FNR_RXDM   ((uint16_t)0x4000)
#define	USB_FNR_RXDP   ((uint16_t)0x8000)
#define	USB_DADDR_ADD   ((uint8_t)0x7F)
#define	USB_DADDR_ADD0   ((uint8_t)0x01)
#define	USB_DADDR_ADD1   ((uint8_t)0x02)
#define	USB_DADDR_ADD2   ((uint8_t)0x04)
#define	USB_DADDR_ADD3   ((uint8_t)0x08)
#define	USB_DADDR_ADD4   ((uint8_t)0x10)
#define	USB_DADDR_ADD5   ((uint8_t)0x20)
#define	USB_DADDR_ADD6   ((uint8_t)0x40)
#define	USB_DADDR_EF   ((uint8_t)0x80)
#define	USB_BTABLE_BTABLE   ((uint16_t)0xFFF8)
#define	USB_ADDR0_TX_ADDR0_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR1_TX_ADDR1_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR2_TX_ADDR2_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR3_TX_ADDR3_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR4_TX_ADDR4_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR5_TX_ADDR5_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR6_TX_ADDR6_TX   ((uint16_t)0xFFFE)
#define	USB_ADDR7_TX_ADDR7_TX   ((uint16_t)0xFFFE)
#define	USB_COUNT0_TX_COUNT0_TX   ((uint16_t)0x03FF)
#define	USB_COUNT1_TX_COUNT1_TX   ((uint16_t)0x03FF)
#define	USB_COUNT2_TX_COUNT2_TX   ((uint16_t)0x03FF)
#define	USB_COUNT3_TX_COUNT3_TX   ((uint16_t)0x03FF)
#define	USB_COUNT4_TX_COUNT4_TX   ((uint16_t)0x03FF)
#define	USB_COUNT5_TX_COUNT5_TX   ((uint16_t)0x03FF)
#define	USB_COUNT6_TX_COUNT6_TX   ((uint16_t)0x03FF)
#define	USB_COUNT7_TX_COUNT7_TX   ((uint16_t)0x03FF)
#define	USB_COUNT0_TX_0_COUNT0_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT0_TX_1_COUNT0_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT1_TX_0_COUNT1_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT1_TX_1_COUNT1_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT2_TX_0_COUNT2_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT2_TX_1_COUNT2_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT3_TX_0_COUNT3_TX_0   ((uint16_t)0x000003FF)
#define	USB_COUNT3_TX_1_COUNT3_TX_1   ((uint16_t)0x03FF0000)
#define	USB_COUNT4_TX_0_COUNT4_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT4_TX_1_COUNT4_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT5_TX_0_COUNT5_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT5_TX_1_COUNT5_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT6_TX_0_COUNT6_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT6_TX_1_COUNT6_TX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT7_TX_0_COUNT7_TX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT7_TX_1_COUNT7_TX_1   ((uint32_t)0x03FF0000)
#define	USB_ADDR0_RX_ADDR0_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR1_RX_ADDR1_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR2_RX_ADDR2_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR3_RX_ADDR3_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR4_RX_ADDR4_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR5_RX_ADDR5_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR6_RX_ADDR6_RX   ((uint16_t)0xFFFE)
#define	USB_ADDR7_RX_ADDR7_RX   ((uint16_t)0xFFFE)
#define	USB_COUNT0_RX_COUNT0_RX   ((uint16_t)0x03FF)
#define	USB_COUNT0_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT0_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT0_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT0_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT0_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT0_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT0_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT1_RX_COUNT1_RX   ((uint16_t)0x03FF)
#define	USB_COUNT1_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT1_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT1_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT1_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT1_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT1_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT1_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT2_RX_COUNT2_RX   ((uint16_t)0x03FF)
#define	USB_COUNT2_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT2_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT2_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT2_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT2_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT2_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT2_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT3_RX_COUNT3_RX   ((uint16_t)0x03FF)
#define	USB_COUNT3_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT3_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT3_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT3_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT3_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT3_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT3_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT4_RX_COUNT4_RX   ((uint16_t)0x03FF)
#define	USB_COUNT4_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT4_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT4_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT4_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT4_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT4_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT4_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT5_RX_COUNT5_RX   ((uint16_t)0x03FF)
#define	USB_COUNT5_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT5_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT5_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT5_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT5_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT5_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT5_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT6_RX_COUNT6_RX   ((uint16_t)0x03FF)
#define	USB_COUNT6_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT6_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT6_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT6_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT6_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT6_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT6_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT7_RX_COUNT7_RX   ((uint16_t)0x03FF)
#define	USB_COUNT7_RX_NUM_BLOCK   ((uint16_t)0x7C00)
#define	USB_COUNT7_RX_NUM_BLOCK_0   ((uint16_t)0x0400)
#define	USB_COUNT7_RX_NUM_BLOCK_1   ((uint16_t)0x0800)
#define	USB_COUNT7_RX_NUM_BLOCK_2   ((uint16_t)0x1000)
#define	USB_COUNT7_RX_NUM_BLOCK_3   ((uint16_t)0x2000)
#define	USB_COUNT7_RX_NUM_BLOCK_4   ((uint16_t)0x4000)
#define	USB_COUNT7_RX_BLSIZE   ((uint16_t)0x8000)
#define	USB_COUNT0_RX_0_COUNT0_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT0_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT0_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT0_RX_1_COUNT0_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT0_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT0_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT1_RX_0_COUNT1_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT1_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT1_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT1_RX_1_COUNT1_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT1_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT1_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT2_RX_0_COUNT2_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT2_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT2_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT2_RX_1_COUNT2_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT2_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT2_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT3_RX_0_COUNT3_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT3_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT3_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT3_RX_1_COUNT3_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT3_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT3_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT4_RX_0_COUNT4_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT4_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT4_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT4_RX_1_COUNT4_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT4_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT4_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT5_RX_0_COUNT5_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT5_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT5_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT5_RX_1_COUNT5_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT5_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT5_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT6_RX_0_COUNT6_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT6_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT6_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT6_RX_1_COUNT6_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT6_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT6_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	USB_COUNT7_RX_0_COUNT7_RX_0   ((uint32_t)0x000003FF)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)
#define	USB_COUNT7_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)
#define	USB_COUNT7_RX_0_BLSIZE_0   ((uint32_t)0x00008000)
#define	USB_COUNT7_RX_1_COUNT7_RX_1   ((uint32_t)0x03FF0000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)
#define	USB_COUNT7_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)
#define	USB_COUNT7_RX_1_BLSIZE_1   ((uint32_t)0x80000000)
#define	WWDG_CR_T   ((uint8_t)0x7F)
#define	WWDG_CR_T0   ((uint8_t)0x01)
#define	WWDG_CR_T1   ((uint8_t)0x02)
#define	WWDG_CR_T2   ((uint8_t)0x04)
#define	WWDG_CR_T3   ((uint8_t)0x08)
#define	WWDG_CR_T4   ((uint8_t)0x10)
#define	WWDG_CR_T5   ((uint8_t)0x20)
#define	WWDG_CR_T6   ((uint8_t)0x40)
#define	WWDG_CR_WDGA   ((uint8_t)0x80)
#define	WWDG_CFR_W   ((uint16_t)0x007F)
#define	WWDG_CFR_W0   ((uint16_t)0x0001)
#define	WWDG_CFR_W1   ((uint16_t)0x0002)
#define	WWDG_CFR_W2   ((uint16_t)0x0004)
#define	WWDG_CFR_W3   ((uint16_t)0x0008)
#define	WWDG_CFR_W4   ((uint16_t)0x0010)
#define	WWDG_CFR_W5   ((uint16_t)0x0020)
#define	WWDG_CFR_W6   ((uint16_t)0x0040)
#define	WWDG_CFR_WDGTB   ((uint16_t)0x0180)
#define	WWDG_CFR_WDGTB0   ((uint16_t)0x0080)
#define	WWDG_CFR_WDGTB1   ((uint16_t)0x0100)
#define	WWDG_CFR_EWI   ((uint16_t)0x0200)
#define	WWDG_SR_EWIF   ((uint8_t)0x01)
#define	SysTick_CTRL_ENABLE   ((uint32_t)0x00000001)
#define	SysTick_CTRL_TICKINT   ((uint32_t)0x00000002)
#define	SysTick_CTRL_CLKSOURCE   ((uint32_t)0x00000004)
#define	SysTick_CTRL_COUNTFLAG   ((uint32_t)0x00010000)
#define	SysTick_LOAD_RELOAD   ((uint32_t)0x00FFFFFF)
#define	SysTick_VAL_CURRENT   ((uint32_t)0x00FFFFFF)
#define	SysTick_CALIB_TENMS   ((uint32_t)0x00FFFFFF)
#define	SysTick_CALIB_SKEW   ((uint32_t)0x40000000)
#define	SysTick_CALIB_NOREF   ((uint32_t)0x80000000)
#define	NVIC_ISER_SETENA   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ISER_SETENA_0   ((uint32_t)0x00000001)
#define	NVIC_ISER_SETENA_1   ((uint32_t)0x00000002)
#define	NVIC_ISER_SETENA_2   ((uint32_t)0x00000004)
#define	NVIC_ISER_SETENA_3   ((uint32_t)0x00000008)
#define	NVIC_ISER_SETENA_4   ((uint32_t)0x00000010)
#define	NVIC_ISER_SETENA_5   ((uint32_t)0x00000020)
#define	NVIC_ISER_SETENA_6   ((uint32_t)0x00000040)
#define	NVIC_ISER_SETENA_7   ((uint32_t)0x00000080)
#define	NVIC_ISER_SETENA_8   ((uint32_t)0x00000100)
#define	NVIC_ISER_SETENA_9   ((uint32_t)0x00000200)
#define	NVIC_ISER_SETENA_10   ((uint32_t)0x00000400)
#define	NVIC_ISER_SETENA_11   ((uint32_t)0x00000800)
#define	NVIC_ISER_SETENA_12   ((uint32_t)0x00001000)
#define	NVIC_ISER_SETENA_13   ((uint32_t)0x00002000)
#define	NVIC_ISER_SETENA_14   ((uint32_t)0x00004000)
#define	NVIC_ISER_SETENA_15   ((uint32_t)0x00008000)
#define	NVIC_ISER_SETENA_16   ((uint32_t)0x00010000)
#define	NVIC_ISER_SETENA_17   ((uint32_t)0x00020000)
#define	NVIC_ISER_SETENA_18   ((uint32_t)0x00040000)
#define	NVIC_ISER_SETENA_19   ((uint32_t)0x00080000)
#define	NVIC_ISER_SETENA_20   ((uint32_t)0x00100000)
#define	NVIC_ISER_SETENA_21   ((uint32_t)0x00200000)
#define	NVIC_ISER_SETENA_22   ((uint32_t)0x00400000)
#define	NVIC_ISER_SETENA_23   ((uint32_t)0x00800000)
#define	NVIC_ISER_SETENA_24   ((uint32_t)0x01000000)
#define	NVIC_ISER_SETENA_25   ((uint32_t)0x02000000)
#define	NVIC_ISER_SETENA_26   ((uint32_t)0x04000000)
#define	NVIC_ISER_SETENA_27   ((uint32_t)0x08000000)
#define	NVIC_ISER_SETENA_28   ((uint32_t)0x10000000)
#define	NVIC_ISER_SETENA_29   ((uint32_t)0x20000000)
#define	NVIC_ISER_SETENA_30   ((uint32_t)0x40000000)
#define	NVIC_ISER_SETENA_31   ((uint32_t)0x80000000)
#define	NVIC_ICER_CLRENA   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ICER_CLRENA_0   ((uint32_t)0x00000001)
#define	NVIC_ICER_CLRENA_1   ((uint32_t)0x00000002)
#define	NVIC_ICER_CLRENA_2   ((uint32_t)0x00000004)
#define	NVIC_ICER_CLRENA_3   ((uint32_t)0x00000008)
#define	NVIC_ICER_CLRENA_4   ((uint32_t)0x00000010)
#define	NVIC_ICER_CLRENA_5   ((uint32_t)0x00000020)
#define	NVIC_ICER_CLRENA_6   ((uint32_t)0x00000040)
#define	NVIC_ICER_CLRENA_7   ((uint32_t)0x00000080)
#define	NVIC_ICER_CLRENA_8   ((uint32_t)0x00000100)
#define	NVIC_ICER_CLRENA_9   ((uint32_t)0x00000200)
#define	NVIC_ICER_CLRENA_10   ((uint32_t)0x00000400)
#define	NVIC_ICER_CLRENA_11   ((uint32_t)0x00000800)
#define	NVIC_ICER_CLRENA_12   ((uint32_t)0x00001000)
#define	NVIC_ICER_CLRENA_13   ((uint32_t)0x00002000)
#define	NVIC_ICER_CLRENA_14   ((uint32_t)0x00004000)
#define	NVIC_ICER_CLRENA_15   ((uint32_t)0x00008000)
#define	NVIC_ICER_CLRENA_16   ((uint32_t)0x00010000)
#define	NVIC_ICER_CLRENA_17   ((uint32_t)0x00020000)
#define	NVIC_ICER_CLRENA_18   ((uint32_t)0x00040000)
#define	NVIC_ICER_CLRENA_19   ((uint32_t)0x00080000)
#define	NVIC_ICER_CLRENA_20   ((uint32_t)0x00100000)
#define	NVIC_ICER_CLRENA_21   ((uint32_t)0x00200000)
#define	NVIC_ICER_CLRENA_22   ((uint32_t)0x00400000)
#define	NVIC_ICER_CLRENA_23   ((uint32_t)0x00800000)
#define	NVIC_ICER_CLRENA_24   ((uint32_t)0x01000000)
#define	NVIC_ICER_CLRENA_25   ((uint32_t)0x02000000)
#define	NVIC_ICER_CLRENA_26   ((uint32_t)0x04000000)
#define	NVIC_ICER_CLRENA_27   ((uint32_t)0x08000000)
#define	NVIC_ICER_CLRENA_28   ((uint32_t)0x10000000)
#define	NVIC_ICER_CLRENA_29   ((uint32_t)0x20000000)
#define	NVIC_ICER_CLRENA_30   ((uint32_t)0x40000000)
#define	NVIC_ICER_CLRENA_31   ((uint32_t)0x80000000)
#define	NVIC_ISPR_SETPEND   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ISPR_SETPEND_0   ((uint32_t)0x00000001)
#define	NVIC_ISPR_SETPEND_1   ((uint32_t)0x00000002)
#define	NVIC_ISPR_SETPEND_2   ((uint32_t)0x00000004)
#define	NVIC_ISPR_SETPEND_3   ((uint32_t)0x00000008)
#define	NVIC_ISPR_SETPEND_4   ((uint32_t)0x00000010)
#define	NVIC_ISPR_SETPEND_5   ((uint32_t)0x00000020)
#define	NVIC_ISPR_SETPEND_6   ((uint32_t)0x00000040)
#define	NVIC_ISPR_SETPEND_7   ((uint32_t)0x00000080)
#define	NVIC_ISPR_SETPEND_8   ((uint32_t)0x00000100)
#define	NVIC_ISPR_SETPEND_9   ((uint32_t)0x00000200)
#define	NVIC_ISPR_SETPEND_10   ((uint32_t)0x00000400)
#define	NVIC_ISPR_SETPEND_11   ((uint32_t)0x00000800)
#define	NVIC_ISPR_SETPEND_12   ((uint32_t)0x00001000)
#define	NVIC_ISPR_SETPEND_13   ((uint32_t)0x00002000)
#define	NVIC_ISPR_SETPEND_14   ((uint32_t)0x00004000)
#define	NVIC_ISPR_SETPEND_15   ((uint32_t)0x00008000)
#define	NVIC_ISPR_SETPEND_16   ((uint32_t)0x00010000)
#define	NVIC_ISPR_SETPEND_17   ((uint32_t)0x00020000)
#define	NVIC_ISPR_SETPEND_18   ((uint32_t)0x00040000)
#define	NVIC_ISPR_SETPEND_19   ((uint32_t)0x00080000)
#define	NVIC_ISPR_SETPEND_20   ((uint32_t)0x00100000)
#define	NVIC_ISPR_SETPEND_21   ((uint32_t)0x00200000)
#define	NVIC_ISPR_SETPEND_22   ((uint32_t)0x00400000)
#define	NVIC_ISPR_SETPEND_23   ((uint32_t)0x00800000)
#define	NVIC_ISPR_SETPEND_24   ((uint32_t)0x01000000)
#define	NVIC_ISPR_SETPEND_25   ((uint32_t)0x02000000)
#define	NVIC_ISPR_SETPEND_26   ((uint32_t)0x04000000)
#define	NVIC_ISPR_SETPEND_27   ((uint32_t)0x08000000)
#define	NVIC_ISPR_SETPEND_28   ((uint32_t)0x10000000)
#define	NVIC_ISPR_SETPEND_29   ((uint32_t)0x20000000)
#define	NVIC_ISPR_SETPEND_30   ((uint32_t)0x40000000)
#define	NVIC_ISPR_SETPEND_31   ((uint32_t)0x80000000)
#define	NVIC_ICPR_CLRPEND   ((uint32_t)0xFFFFFFFF)
#define	NVIC_ICPR_CLRPEND_0   ((uint32_t)0x00000001)
#define	NVIC_ICPR_CLRPEND_1   ((uint32_t)0x00000002)
#define	NVIC_ICPR_CLRPEND_2   ((uint32_t)0x00000004)
#define	NVIC_ICPR_CLRPEND_3   ((uint32_t)0x00000008)
#define	NVIC_ICPR_CLRPEND_4   ((uint32_t)0x00000010)
#define	NVIC_ICPR_CLRPEND_5   ((uint32_t)0x00000020)
#define	NVIC_ICPR_CLRPEND_6   ((uint32_t)0x00000040)
#define	NVIC_ICPR_CLRPEND_7   ((uint32_t)0x00000080)
#define	NVIC_ICPR_CLRPEND_8   ((uint32_t)0x00000100)
#define	NVIC_ICPR_CLRPEND_9   ((uint32_t)0x00000200)
#define	NVIC_ICPR_CLRPEND_10   ((uint32_t)0x00000400)
#define	NVIC_ICPR_CLRPEND_11   ((uint32_t)0x00000800)
#define	NVIC_ICPR_CLRPEND_12   ((uint32_t)0x00001000)
#define	NVIC_ICPR_CLRPEND_13   ((uint32_t)0x00002000)
#define	NVIC_ICPR_CLRPEND_14   ((uint32_t)0x00004000)
#define	NVIC_ICPR_CLRPEND_15   ((uint32_t)0x00008000)
#define	NVIC_ICPR_CLRPEND_16   ((uint32_t)0x00010000)
#define	NVIC_ICPR_CLRPEND_17   ((uint32_t)0x00020000)
#define	NVIC_ICPR_CLRPEND_18   ((uint32_t)0x00040000)
#define	NVIC_ICPR_CLRPEND_19   ((uint32_t)0x00080000)
#define	NVIC_ICPR_CLRPEND_20   ((uint32_t)0x00100000)
#define	NVIC_ICPR_CLRPEND_21   ((uint32_t)0x00200000)
#define	NVIC_ICPR_CLRPEND_22   ((uint32_t)0x00400000)
#define	NVIC_ICPR_CLRPEND_23   ((uint32_t)0x00800000)
#define	NVIC_ICPR_CLRPEND_24   ((uint32_t)0x01000000)
#define	NVIC_ICPR_CLRPEND_25   ((uint32_t)0x02000000)
#define	NVIC_ICPR_CLRPEND_26   ((uint32_t)0x04000000)
#define	NVIC_ICPR_CLRPEND_27   ((uint32_t)0x08000000)
#define	NVIC_ICPR_CLRPEND_28   ((uint32_t)0x10000000)
#define	NVIC_ICPR_CLRPEND_29   ((uint32_t)0x20000000)
#define	NVIC_ICPR_CLRPEND_30   ((uint32_t)0x40000000)
#define	NVIC_ICPR_CLRPEND_31   ((uint32_t)0x80000000)
#define	NVIC_IABR_ACTIVE   ((uint32_t)0xFFFFFFFF)
#define	NVIC_IABR_ACTIVE_0   ((uint32_t)0x00000001)
#define	NVIC_IABR_ACTIVE_1   ((uint32_t)0x00000002)
#define	NVIC_IABR_ACTIVE_2   ((uint32_t)0x00000004)
#define	NVIC_IABR_ACTIVE_3   ((uint32_t)0x00000008)
#define	NVIC_IABR_ACTIVE_4   ((uint32_t)0x00000010)
#define	NVIC_IABR_ACTIVE_5   ((uint32_t)0x00000020)
#define	NVIC_IABR_ACTIVE_6   ((uint32_t)0x00000040)
#define	NVIC_IABR_ACTIVE_7   ((uint32_t)0x00000080)
#define	NVIC_IABR_ACTIVE_8   ((uint32_t)0x00000100)
#define	NVIC_IABR_ACTIVE_9   ((uint32_t)0x00000200)
#define	NVIC_IABR_ACTIVE_10   ((uint32_t)0x00000400)
#define	NVIC_IABR_ACTIVE_11   ((uint32_t)0x00000800)
#define	NVIC_IABR_ACTIVE_12   ((uint32_t)0x00001000)
#define	NVIC_IABR_ACTIVE_13   ((uint32_t)0x00002000)
#define	NVIC_IABR_ACTIVE_14   ((uint32_t)0x00004000)
#define	NVIC_IABR_ACTIVE_15   ((uint32_t)0x00008000)
#define	NVIC_IABR_ACTIVE_16   ((uint32_t)0x00010000)
#define	NVIC_IABR_ACTIVE_17   ((uint32_t)0x00020000)
#define	NVIC_IABR_ACTIVE_18   ((uint32_t)0x00040000)
#define	NVIC_IABR_ACTIVE_19   ((uint32_t)0x00080000)
#define	NVIC_IABR_ACTIVE_20   ((uint32_t)0x00100000)
#define	NVIC_IABR_ACTIVE_21   ((uint32_t)0x00200000)
#define	NVIC_IABR_ACTIVE_22   ((uint32_t)0x00400000)
#define	NVIC_IABR_ACTIVE_23   ((uint32_t)0x00800000)
#define	NVIC_IABR_ACTIVE_24   ((uint32_t)0x01000000)
#define	NVIC_IABR_ACTIVE_25   ((uint32_t)0x02000000)
#define	NVIC_IABR_ACTIVE_26   ((uint32_t)0x04000000)
#define	NVIC_IABR_ACTIVE_27   ((uint32_t)0x08000000)
#define	NVIC_IABR_ACTIVE_28   ((uint32_t)0x10000000)
#define	NVIC_IABR_ACTIVE_29   ((uint32_t)0x20000000)
#define	NVIC_IABR_ACTIVE_30   ((uint32_t)0x40000000)
#define	NVIC_IABR_ACTIVE_31   ((uint32_t)0x80000000)
#define	NVIC_IPR0_PRI_0   ((uint32_t)0x000000FF)
#define	NVIC_IPR0_PRI_1   ((uint32_t)0x0000FF00)
#define	NVIC_IPR0_PRI_2   ((uint32_t)0x00FF0000)
#define	NVIC_IPR0_PRI_3   ((uint32_t)0xFF000000)
#define	NVIC_IPR1_PRI_4   ((uint32_t)0x000000FF)
#define	NVIC_IPR1_PRI_5   ((uint32_t)0x0000FF00)
#define	NVIC_IPR1_PRI_6   ((uint32_t)0x00FF0000)
#define	NVIC_IPR1_PRI_7   ((uint32_t)0xFF000000)
#define	NVIC_IPR2_PRI_8   ((uint32_t)0x000000FF)
#define	NVIC_IPR2_PRI_9   ((uint32_t)0x0000FF00)
#define	NVIC_IPR2_PRI_10   ((uint32_t)0x00FF0000)
#define	NVIC_IPR2_PRI_11   ((uint32_t)0xFF000000)
#define	NVIC_IPR3_PRI_12   ((uint32_t)0x000000FF)
#define	NVIC_IPR3_PRI_13   ((uint32_t)0x0000FF00)
#define	NVIC_IPR3_PRI_14   ((uint32_t)0x00FF0000)
#define	NVIC_IPR3_PRI_15   ((uint32_t)0xFF000000)
#define	NVIC_IPR4_PRI_16   ((uint32_t)0x000000FF)
#define	NVIC_IPR4_PRI_17   ((uint32_t)0x0000FF00)
#define	NVIC_IPR4_PRI_18   ((uint32_t)0x00FF0000)
#define	NVIC_IPR4_PRI_19   ((uint32_t)0xFF000000)
#define	NVIC_IPR5_PRI_20   ((uint32_t)0x000000FF)
#define	NVIC_IPR5_PRI_21   ((uint32_t)0x0000FF00)
#define	NVIC_IPR5_PRI_22   ((uint32_t)0x00FF0000)
#define	NVIC_IPR5_PRI_23   ((uint32_t)0xFF000000)
#define	NVIC_IPR6_PRI_24   ((uint32_t)0x000000FF)
#define	NVIC_IPR6_PRI_25   ((uint32_t)0x0000FF00)
#define	NVIC_IPR6_PRI_26   ((uint32_t)0x00FF0000)
#define	NVIC_IPR6_PRI_27   ((uint32_t)0xFF000000)
#define	NVIC_IPR7_PRI_28   ((uint32_t)0x000000FF)
#define	NVIC_IPR7_PRI_29   ((uint32_t)0x0000FF00)
#define	NVIC_IPR7_PRI_30   ((uint32_t)0x00FF0000)
#define	NVIC_IPR7_PRI_31   ((uint32_t)0xFF000000)
#define	SCB_CPUID_REVISION   ((uint32_t)0x0000000F)
#define	SCB_CPUID_PARTNO   ((uint32_t)0x0000FFF0)
#define	SCB_CPUID_Constant   ((uint32_t)0x000F0000)
#define	SCB_CPUID_VARIANT   ((uint32_t)0x00F00000)
#define	SCB_CPUID_IMPLEMENTER   ((uint32_t)0xFF000000)
#define	SCB_ICSR_VECTACTIVE   ((uint32_t)0x000001FF)
#define	SCB_ICSR_RETTOBASE   ((uint32_t)0x00000800)
#define	SCB_ICSR_VECTPENDING   ((uint32_t)0x003FF000)
#define	SCB_ICSR_ISRPENDING   ((uint32_t)0x00400000)
#define	SCB_ICSR_ISRPREEMPT   ((uint32_t)0x00800000)
#define	SCB_ICSR_PENDSTCLR   ((uint32_t)0x02000000)
#define	SCB_ICSR_PENDSTSET   ((uint32_t)0x04000000)
#define	SCB_ICSR_PENDSVCLR   ((uint32_t)0x08000000)
#define	SCB_ICSR_PENDSVSET   ((uint32_t)0x10000000)
#define	SCB_ICSR_NMIPENDSET   ((uint32_t)0x80000000)
#define	SCB_VTOR_TBLOFF   ((uint32_t)0x1FFFFF80)
#define	SCB_VTOR_TBLBASE   ((uint32_t)0x20000000)
#define	SCB_AIRCR_VECTRESET   ((uint32_t)0x00000001)
#define	SCB_AIRCR_VECTCLRACTIVE   ((uint32_t)0x00000002)
#define	SCB_AIRCR_SYSRESETREQ   ((uint32_t)0x00000004)
#define	SCB_AIRCR_PRIGROUP   ((uint32_t)0x00000700)
#define	SCB_AIRCR_PRIGROUP_0   ((uint32_t)0x00000100)
#define	SCB_AIRCR_PRIGROUP_1   ((uint32_t)0x00000200)
#define	SCB_AIRCR_PRIGROUP_2   ((uint32_t)0x00000400)
#define	SCB_AIRCR_PRIGROUP0   ((uint32_t)0x00000000)
#define	SCB_AIRCR_PRIGROUP1   ((uint32_t)0x00000100)
#define	SCB_AIRCR_PRIGROUP2   ((uint32_t)0x00000200)
#define	SCB_AIRCR_PRIGROUP3   ((uint32_t)0x00000300)
#define	SCB_AIRCR_PRIGROUP4   ((uint32_t)0x00000400)
#define	SCB_AIRCR_PRIGROUP5   ((uint32_t)0x00000500)
#define	SCB_AIRCR_PRIGROUP6   ((uint32_t)0x00000600)
#define	SCB_AIRCR_PRIGROUP7   ((uint32_t)0x00000700)
#define	SCB_AIRCR_ENDIANESS   ((uint32_t)0x00008000)
#define	SCB_AIRCR_VECTKEY   ((uint32_t)0xFFFF0000)
#define	SCB_SCR_SLEEPONEXIT   ((uint8_t)0x02)
#define	SCB_SCR_SLEEPDEEP   ((uint8_t)0x04)
#define	SCB_SCR_SEVONPEND   ((uint8_t)0x10)
#define	SCB_CCR_NONBASETHRDENA   ((uint16_t)0x0001)
#define	SCB_CCR_USERSETMPEND   ((uint16_t)0x0002)
#define	SCB_CCR_UNALIGN_TRP   ((uint16_t)0x0008)
#define	SCB_CCR_DIV_0_TRP   ((uint16_t)0x0010)
#define	SCB_CCR_BFHFNMIGN   ((uint16_t)0x0100)
#define	SCB_CCR_STKALIGN   ((uint16_t)0x0200)
#define	SCB_SHPR_PRI_N   ((uint32_t)0x000000FF)
#define	SCB_SHPR_PRI_N1   ((uint32_t)0x0000FF00)
#define	SCB_SHPR_PRI_N2   ((uint32_t)0x00FF0000)
#define	SCB_SHPR_PRI_N3   ((uint32_t)0xFF000000)
#define	SCB_SHCSR_MEMFAULTACT   ((uint32_t)0x00000001)
#define	SCB_SHCSR_BUSFAULTACT   ((uint32_t)0x00000002)
#define	SCB_SHCSR_USGFAULTACT   ((uint32_t)0x00000008)
#define	SCB_SHCSR_SVCALLACT   ((uint32_t)0x00000080)
#define	SCB_SHCSR_MONITORACT   ((uint32_t)0x00000100)
#define	SCB_SHCSR_PENDSVACT   ((uint32_t)0x00000400)
#define	SCB_SHCSR_SYSTICKACT   ((uint32_t)0x00000800)
#define	SCB_SHCSR_USGFAULTPENDED   ((uint32_t)0x00001000)
#define	SCB_SHCSR_MEMFAULTPENDED   ((uint32_t)0x00002000)
#define	SCB_SHCSR_BUSFAULTPENDED   ((uint32_t)0x00004000)
#define	SCB_SHCSR_SVCALLPENDED   ((uint32_t)0x00008000)
#define	SCB_SHCSR_MEMFAULTENA   ((uint32_t)0x00010000)
#define	SCB_SHCSR_BUSFAULTENA   ((uint32_t)0x00020000)
#define	SCB_SHCSR_USGFAULTENA   ((uint32_t)0x00040000)
#define	SCB_CFSR_IACCVIOL   ((uint32_t)0x00000001)
#define	SCB_CFSR_DACCVIOL   ((uint32_t)0x00000002)
#define	SCB_CFSR_MUNSTKERR   ((uint32_t)0x00000008)
#define	SCB_CFSR_MSTKERR   ((uint32_t)0x00000010)
#define	SCB_CFSR_MMARVALID   ((uint32_t)0x00000080)
#define	SCB_CFSR_IBUSERR   ((uint32_t)0x00000100)
#define	SCB_CFSR_PRECISERR   ((uint32_t)0x00000200)
#define	SCB_CFSR_IMPRECISERR   ((uint32_t)0x00000400)
#define	SCB_CFSR_UNSTKERR   ((uint32_t)0x00000800)
#define	SCB_CFSR_STKERR   ((uint32_t)0x00001000)
#define	SCB_CFSR_BFARVALID   ((uint32_t)0x00008000)
#define	SCB_CFSR_UNDEFINSTR   ((uint32_t)0x00010000)
#define	SCB_CFSR_INVSTATE   ((uint32_t)0x00020000)
#define	SCB_CFSR_INVPC   ((uint32_t)0x00040000)
#define	SCB_CFSR_NOCP   ((uint32_t)0x00080000)
#define	SCB_CFSR_UNALIGNED   ((uint32_t)0x01000000)
#define	SCB_CFSR_DIVBYZERO   ((uint32_t)0x02000000)
#define	SCB_HFSR_VECTTBL   ((uint32_t)0x00000002)
#define	SCB_HFSR_FORCED   ((uint32_t)0x40000000)
#define	SCB_HFSR_DEBUGEVT   ((uint32_t)0x80000000)
#define	SCB_DFSR_HALTED   ((uint8_t)0x01)
#define	SCB_DFSR_BKPT   ((uint8_t)0x02)
#define	SCB_DFSR_DWTTRAP   ((uint8_t)0x04)
#define	SCB_DFSR_VCATCH   ((uint8_t)0x08)
#define	SCB_DFSR_EXTERNAL   ((uint8_t)0x10)
#define	SCB_MMFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)
#define	SCB_BFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)
#define	SCB_AFSR_IMPDEF   ((uint32_t)0xFFFFFFFF)

---

Define Documentation

#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)

Data register bits

#define CRC_IDR_IDR   ((uint8_t)0xFF)

General-purpose 8-bit data register bits

#define CRC_CR_RESET   ((uint8_t)0x01)

RESET bit

Referenced by CRC_Init(), and CRC_ResetDR().

#define PWR_CR_LPDS   ((uint16_t)0x0001)

Low-Power Deepsleep

#define PWR_CR_PDDS   ((uint16_t)0x0002)

Power Down Deepsleep

#define PWR_CR_CWUF   ((uint16_t)0x0004)

Clear Wakeup Flag

#define PWR_CR_CSBF   ((uint16_t)0x0008)

Clear Standby Flag

#define PWR_CR_PVDE   ((uint16_t)0x0010)

Power Voltage Detector Enable

#define PWR_CR_PLS   ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

#define PWR_CR_PLS_0   ((uint16_t)0x0020)

Bit 0

#define PWR_CR_PLS_1   ((uint16_t)0x0040)

Bit 1

#define PWR_CR_PLS_2   ((uint16_t)0x0080)

Bit 2 PVD level configuration

#define PWR_CR_PLS_2V2   ((uint16_t)0x0000)

PVD level 2.2V

#define PWR_CR_PLS_2V3   ((uint16_t)0x0020)

PVD level 2.3V

#define PWR_CR_PLS_2V4   ((uint16_t)0x0040)

PVD level 2.4V

#define PWR_CR_PLS_2V5   ((uint16_t)0x0060)

PVD level 2.5V

#define PWR_CR_PLS_2V6   ((uint16_t)0x0080)

PVD level 2.6V

#define PWR_CR_PLS_2V7   ((uint16_t)0x00A0)

PVD level 2.7V

#define PWR_CR_PLS_2V8   ((uint16_t)0x00C0)

PVD level 2.8V

#define PWR_CR_PLS_2V9   ((uint16_t)0x00E0)

PVD level 2.9V

#define PWR_CR_DBP   ((uint16_t)0x0100)

Disable Backup Domain write protection

Referenced by Stm32RtcInit().

#define PWR_CSR_WUF   ((uint16_t)0x0001)

Wakeup Flag

#define PWR_CSR_SBF   ((uint16_t)0x0002)

Standby Flag

#define PWR_CSR_PVDO   ((uint16_t)0x0004)

PVD Output

#define PWR_CSR_EWUP   ((uint16_t)0x0100)

Enable WKUP pin

#define BKP_DR1_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR2_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR3_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR4_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR5_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR6_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR7_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR8_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR9_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR10_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR11_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR12_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR13_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR14_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR15_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR16_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR17_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR18_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR19_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR20_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR21_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR22_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR23_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR24_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR25_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR26_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR27_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR28_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR29_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR30_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR31_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR32_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR33_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR34_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR35_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR36_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR37_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR38_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR39_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR40_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR41_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_DR42_D   ((uint16_t)0xFFFF)

Backup data

#define BKP_RTCCR_CAL   ((uint16_t)0x007F)

Calibration value

#define BKP_RTCCR_CCO   ((uint16_t)0x0080)

Calibration Clock Output

#define BKP_RTCCR_ASOE   ((uint16_t)0x0100)

Alarm or Second Output Enable

#define BKP_RTCCR_ASOS   ((uint16_t)0x0200)

Alarm or Second Output Selection

#define BKP_CR_TPE   ((uint8_t)0x01)

TAMPER pin enable

#define BKP_CR_TPAL   ((uint8_t)0x02)

TAMPER pin active level

#define BKP_CSR_CTE   ((uint16_t)0x0001)

Clear Tamper event

#define BKP_CSR_CTI   ((uint16_t)0x0002)

Clear Tamper Interrupt

#define BKP_CSR_TPIE   ((uint16_t)0x0004)

TAMPER Pin interrupt enable

#define BKP_CSR_TEF   ((uint16_t)0x0100)

Tamper Event Flag

#define BKP_CSR_TIF   ((uint16_t)0x0200)

Tamper Interrupt Flag

#define RCC_CR_HSION   ((uint32_t)0x00000001)

Internal High Speed clock enable

Referenced by CtlHseClock(), and CtlHsiClock().

#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)

Internal High Speed clock ready flag

Referenced by CtlHsiClock().

#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)

Internal High Speed clock trimming

Referenced by RCC_AdjustHSICalibrationValue().

#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)

Internal High Speed clock Calibration

#define RCC_CR_HSEON   ((uint32_t)0x00010000)

External High Speed clock enable

Referenced by CtlHseClock().

#define RCC_CR_HSERDY   ((uint32_t)0x00020000)

External High Speed clock ready flag

Referenced by CtlHseClock().

#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)

External High Speed clock Bypass

#define RCC_CR_CSSON   ((uint32_t)0x00080000)

Clock Security System enable

#define RCC_CR_PLLON   ((uint32_t)0x01000000)

PLL enable

Referenced by CtlPllClock().

#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)

PLL clock ready flag

Referenced by CtlPllClock().

#define RCC_CFGR_SW   ((uint32_t)0x00000003)

< SW configuration SW[1:0] bits (System clock Switch)

Referenced by RCC_SYSCLKConfig(), and SetSysClockSource().

#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)

Bit 0

#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)

Bit 1

#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)

HSI selected as system clock

Referenced by SetSysClockSource().

#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)

HSE selected as system clock

Referenced by SetSysClockSource().

#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)

PLL selected as system clock SWS configuration

Referenced by SetSysClockSource().

#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

Referenced by RCC_GetClocksFreq(), RCC_GetSYSCLKSource(), SetSysClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)

Bit 0

#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)

Bit 1

#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)

HSI oscillator used as system clock

Referenced by SetSysClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)

HSE oscillator used as system clock

Referenced by SetSysClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)

PLL used as system clock HPRE configuration

Referenced by SetSysClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

Referenced by RCC_GetClocksFreq(), RCC_HCLKConfig(), SetSysClock(), and SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)

Bit 0

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)

Bit 1

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)

Bit 2

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)

Bit 3

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)

SYSCLK not divided

Referenced by SetSysClock().

#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)

SYSCLK divided by 2

#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)

SYSCLK divided by 4

#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)

SYSCLK divided by 8

#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)

SYSCLK divided by 16

#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)

SYSCLK divided by 64

#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)

SYSCLK divided by 128

#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)

SYSCLK divided by 256

#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)

SYSCLK divided by 512 PPRE1 configuration

#define RCC_CFGR_PPRE1   ((uint32_t)0x00000700)

PRE1[2:0] bits (APB1 prescaler)

Referenced by RCC_GetClocksFreq(), RCC_PCLK1Config(), and SetSysClock().

#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000100)

Bit 0

#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000200)

Bit 1

#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00000400)

Bit 2

#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)

HCLK not divided

Referenced by SetSysClock().

#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00000400)

HCLK divided by 2

#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00000500)

HCLK divided by 4

#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00000600)

HCLK divided by 8

#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00000700)

HCLK divided by 16 PPRE2 configuration

#define RCC_CFGR_PPRE2   ((uint32_t)0x00003800)

PRE2[2:0] bits (APB2 prescaler)

Referenced by RCC_GetClocksFreq(), RCC_PCLK2Config(), and SetSysClock().

#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00000800)

Bit 0

#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00001000)

Bit 1

#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00002000)

Bit 2

#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)

HCLK not divided

Referenced by SetSysClock().

#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00002000)

HCLK divided by 2

#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x00002800)

HCLK divided by 4

#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x00003000)

HCLK divided by 8

#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x00003800)

HCLK divided by 16 ADCPPRE configuration

#define RCC_CFGR_ADCPRE   ((uint32_t)0x0000C000)

ADCPRE[1:0] bits (ADC prescaler)

#define RCC_CFGR_ADCPRE_0   ((uint32_t)0x00004000)

Bit 0

#define RCC_CFGR_ADCPRE_1   ((uint32_t)0x00008000)

Bit 1

#define RCC_CFGR_ADCPRE_DIV2   ((uint32_t)0x00000000)

PCLK2 divided by 2

#define RCC_CFGR_ADCPRE_DIV4   ((uint32_t)0x00004000)

PCLK2 divided by 4

#define RCC_CFGR_ADCPRE_DIV6   ((uint32_t)0x00008000)

PCLK2 divided by 6

#define RCC_CFGR_ADCPRE_DIV8   ((uint32_t)0x0000C000)

PCLK2 divided by 8

#define RCC_CFGR_PLLSRC   ((uint32_t)0x00010000)

PLL entry clock source

Referenced by SetPllClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLXTPRE   ((uint32_t)0x00020000)

HSE divider for PLL entry PLLMUL configuration

Referenced by SetPllClockSource(), and SystemCoreClockUpdate().

#define RCC_CFGR_PLLMULL   ((uint32_t)0x003C0000)

PLLMUL[3:0] bits (PLL multiplication factor)

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMULL_0   ((uint32_t)0x00040000)

Bit 0

#define RCC_CFGR_PLLMULL_1   ((uint32_t)0x00080000)

Bit 1

#define RCC_CFGR_PLLMULL_2   ((uint32_t)0x00100000)

Bit 2

#define RCC_CFGR_PLLMULL_3   ((uint32_t)0x00200000)

Bit 3

#define RCC_CFGR_PLLSRC_HSI_Div2   ((uint32_t)0x00000000)

HSI clock divided by 2 selected as PLL entry clock source

#define RCC_CFGR_PLLSRC_HSE   ((uint32_t)0x00010000)

HSE clock selected as PLL entry clock source

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLXTPRE_HSE   ((uint32_t)0x00000000)

HSE clock not divided for PLL entry

#define RCC_CFGR_PLLXTPRE_HSE_Div2   ((uint32_t)0x00020000)

HSE clock divided by 2 for PLL entry

#define RCC_CFGR_PLLMULL2   ((uint32_t)0x00000000)

PLL input clock*2

#define RCC_CFGR_PLLMULL3   ((uint32_t)0x00040000)

PLL input clock*3

#define RCC_CFGR_PLLMULL4   ((uint32_t)0x00080000)

PLL input clock*4

#define RCC_CFGR_PLLMULL5   ((uint32_t)0x000C0000)

PLL input clock*5

#define RCC_CFGR_PLLMULL6   ((uint32_t)0x00100000)

PLL input clock*6

#define RCC_CFGR_PLLMULL7   ((uint32_t)0x00140000)

PLL input clock*7

#define RCC_CFGR_PLLMULL8   ((uint32_t)0x00180000)

PLL input clock*8

#define RCC_CFGR_PLLMULL9   ((uint32_t)0x001C0000)

PLL input clock*9

#define RCC_CFGR_PLLMULL10   ((uint32_t)0x00200000)

PLL input clock10

#define RCC_CFGR_PLLMULL11   ((uint32_t)0x00240000)

PLL input clock*11

#define RCC_CFGR_PLLMULL12   ((uint32_t)0x00280000)

PLL input clock*12

#define RCC_CFGR_PLLMULL13   ((uint32_t)0x002C0000)

PLL input clock*13

#define RCC_CFGR_PLLMULL14   ((uint32_t)0x00300000)

PLL input clock*14

#define RCC_CFGR_PLLMULL15   ((uint32_t)0x00340000)

PLL input clock*15

#define RCC_CFGR_PLLMULL16   ((uint32_t)0x00380000)

PLL input clock*16

#define RCC_CFGR_USBPRE   ((uint32_t)0x00400000)

USB Device prescaler MCO configuration

#define RCC_CFGR_MCO   ((uint32_t)0x07000000)

MCO[2:0] bits (Microcontroller Clock Output)

#define RCC_CFGR_MCO_0   ((uint32_t)0x01000000)

Bit 0

#define RCC_CFGR_MCO_1   ((uint32_t)0x02000000)

Bit 1

#define RCC_CFGR_MCO_2   ((uint32_t)0x04000000)

Bit 2

#define RCC_CFGR_MCO_NOCLOCK   ((uint32_t)0x00000000)

No clock

#define RCC_CFGR_MCO_SYSCLK   ((uint32_t)0x04000000)

System clock selected as MCO source

#define RCC_CFGR_MCO_HSI   ((uint32_t)0x05000000)

HSI clock selected as MCO source

#define RCC_CFGR_MCO_HSE   ((uint32_t)0x06000000)

HSE clock selected as MCO source

#define RCC_CFGR_MCO_PLL   ((uint32_t)0x07000000)

PLL clock divided by 2 selected as MCO source

#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)

<****************** Bit definition for RCC_CIR register LSI Ready Interrupt flag

#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)

LSE Ready Interrupt flag

#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)

HSI Ready Interrupt flag

#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)

HSE Ready Interrupt flag

#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)

PLL Ready Interrupt flag

#define RCC_CIR_CSSF   ((uint32_t)0x00000080)

Clock Security System Interrupt flag

#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)

LSI Ready Interrupt Enable

#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)

LSE Ready Interrupt Enable

#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)

HSI Ready Interrupt Enable

#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)

HSE Ready Interrupt Enable

#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)

PLL Ready Interrupt Enable

#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)

LSI Ready Interrupt Clear

#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)

LSE Ready Interrupt Clear

#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)

HSI Ready Interrupt Clear

#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)

HSE Ready Interrupt Clear

#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)

PLL Ready Interrupt Clear

#define RCC_CIR_CSSC   ((uint32_t)0x00800000)

Clock Security System Interrupt Clear

#define RCC_APB2RSTR_AFIORST   ((uint32_t)0x00000001)

Alternate Function I/O reset

#define RCC_APB2RSTR_IOPARST   ((uint32_t)0x00000004)

I/O port A reset

#define RCC_APB2RSTR_IOPBRST   ((uint32_t)0x00000008)

I/O port B reset

#define RCC_APB2RSTR_IOPCRST   ((uint32_t)0x00000010)

I/O port C reset

#define RCC_APB2RSTR_IOPDRST   ((uint32_t)0x00000020)

I/O port D reset

#define RCC_APB2RSTR_ADC1RST   ((uint32_t)0x00000200)

ADC 1 interface reset

#define RCC_APB2RSTR_ADC2RST   ((uint32_t)0x00000400)

ADC 2 interface reset

#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000800)

TIM1 Timer reset

#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)

SPI 1 reset

#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00004000)

USART1 reset

#define RCC_APB2RSTR_IOPERST   ((uint32_t)0x00000040)

I/O port E reset

#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)

Timer 2 reset

#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)

Timer 3 reset

#define RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)

Window Watchdog reset

#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)

USART 2 reset

#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)

I2C 1 reset

#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)

CAN1 reset

Referenced by Stm32CanHw1Init(), and Stm32CanHw2Init().

#define RCC_APB1RSTR_BKPRST   ((uint32_t)0x08000000)

Backup interface reset

#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)

Power interface reset

#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)

Timer 4 reset

#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)

SPI 2 reset

#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)

RUSART 3 reset

#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)

I2C 2 reset

#define RCC_AHBENR_DMA1EN   ((uint16_t)0x0001)

DMA1 clock enable

Referenced by DMA_Init().

#define RCC_AHBENR_SRAMEN   ((uint16_t)0x0004)

SRAM interface clock enable

#define RCC_AHBENR_FLITFEN   ((uint16_t)0x0010)

FLITF clock enable

#define RCC_AHBENR_CRCEN   ((uint16_t)0x0040)

CRC clock enable

#define RCC_APB2ENR_AFIOEN   ((uint32_t)0x00000001)

Alternate Function I/O clock enable

#define RCC_APB2ENR_IOPAEN   ((uint32_t)0x00000004)

I/O port A clock enable

#define RCC_APB2ENR_IOPBEN   ((uint32_t)0x00000008)

I/O port B clock enable

#define RCC_APB2ENR_IOPCEN   ((uint32_t)0x00000010)

I/O port C clock enable

#define RCC_APB2ENR_IOPDEN   ((uint32_t)0x00000020)

I/O port D clock enable

#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000200)

ADC 1 interface clock enable

#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000400)

ADC 2 interface clock enable

#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000800)

TIM1 Timer clock enable

#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)

SPI 1 clock enable

#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00004000)

USART1 clock enable

#define RCC_APB2ENR_IOPEEN   ((uint32_t)0x00000040)

I/O port E clock enable

#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)

Timer 2 clock enabled

#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)

Timer 3 clock enable

#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)

Window Watchdog clock enable

#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)

USART 2 clock enable

#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)

I2C 1 clock enable

#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)

CAN1 clock enable

Referenced by Stm32CanHw1Init(), and Stm32CanHw2Init().

#define RCC_APB1ENR_BKPEN   ((uint32_t)0x08000000)

Backup interface clock enable

#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)

Power interface clock enable

#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)

Timer 4 clock enable

#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)

SPI 2 clock enable

#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)

USART 3 clock enable

#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)

I2C 2 clock enable

#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)

External Low Speed oscillator enable

#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)

External Low Speed oscillator Ready

#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)

External Low Speed oscillator Bypass

#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)

RTCSEL[1:0] bits (RTC clock source selection)

#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)

Bit 0

#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)

Bit 1 RTC congiguration

#define RCC_BDCR_RTCSEL_NOCLOCK   ((uint32_t)0x00000000)

No clock

#define RCC_BDCR_RTCSEL_LSE   ((uint32_t)0x00000100)

LSE oscillator clock used as RTC clock

#define RCC_BDCR_RTCSEL_LSI   ((uint32_t)0x00000200)

LSI oscillator clock used as RTC clock

#define RCC_BDCR_RTCSEL_HSE   ((uint32_t)0x00000300)

HSE oscillator clock divided by 128 used as RTC clock

#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)

RTC clock enable

#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)

Backup domain software reset

#define RCC_CSR_LSION   ((uint32_t)0x00000001)

Internal Low Speed oscillator enable

#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)

Internal Low Speed oscillator Ready

#define RCC_CSR_RMVF   ((uint32_t)0x01000000)

Remove reset flag

Referenced by RCC_ClearFlag().

#define RCC_CSR_PINRSTF   ((uint32_t)0x04000000)

PIN reset flag

#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)

POR/PDR reset flag

#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)

Software Reset flag

#define RCC_CSR_IWDGRSTF   ((uint32_t)0x20000000)

Independent Watchdog reset flag

#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)

Window watchdog reset flag

#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)

Low-Power reset flag

#define GPIO_CRL_MODE   ((uint32_t)0x33333333)

Port x mode bits

#define GPIO_CRL_MODE0   ((uint32_t)0x00000003)

MODE0[1:0] bits (Port x mode bits, pin 0)

#define GPIO_CRL_MODE0_0   ((uint32_t)0x00000001)

Bit 0

#define GPIO_CRL_MODE0_1   ((uint32_t)0x00000002)

Bit 1

#define GPIO_CRL_MODE1   ((uint32_t)0x00000030)

MODE1[1:0] bits (Port x mode bits, pin 1)

#define GPIO_CRL_MODE1_0   ((uint32_t)0x00000010)

Bit 0

#define GPIO_CRL_MODE1_1   ((uint32_t)0x00000020)

Bit 1

#define GPIO_CRL_MODE2   ((uint32_t)0x00000300)

MODE2[1:0] bits (Port x mode bits, pin 2)

#define GPIO_CRL_MODE2_0   ((uint32_t)0x00000100)

Bit 0

#define GPIO_CRL_MODE2_1   ((uint32_t)0x00000200)

Bit 1

#define GPIO_CRL_MODE3   ((uint32_t)0x00003000)

MODE3[1:0] bits (Port x mode bits, pin 3)

#define GPIO_CRL_MODE3_0   ((uint32_t)0x00001000)

Bit 0

#define GPIO_CRL_MODE3_1   ((uint32_t)0x00002000)

Bit 1

#define GPIO_CRL_MODE4   ((uint32_t)0x00030000)

MODE4[1:0] bits (Port x mode bits, pin 4)

#define GPIO_CRL_MODE4_0   ((uint32_t)0x00010000)

Bit 0

#define GPIO_CRL_MODE4_1   ((uint32_t)0x00020000)

Bit 1

#define GPIO_CRL_MODE5   ((uint32_t)0x00300000)

MODE5[1:0] bits (Port x mode bits, pin 5)

#define GPIO_CRL_MODE5_0   ((uint32_t)0x00100000)

Bit 0

#define GPIO_CRL_MODE5_1   ((uint32_t)0x00200000)

Bit 1

#define GPIO_CRL_MODE6   ((uint32_t)0x03000000)

MODE6[1:0] bits (Port x mode bits, pin 6)

#define GPIO_CRL_MODE6_0   ((uint32_t)0x01000000)

Bit 0

#define GPIO_CRL_MODE6_1   ((uint32_t)0x02000000)

Bit 1

#define GPIO_CRL_MODE7   ((uint32_t)0x30000000)

MODE7[1:0] bits (Port x mode bits, pin 7)

#define GPIO_CRL_MODE7_0   ((uint32_t)0x10000000)

Bit 0

#define GPIO_CRL_MODE7_1   ((uint32_t)0x20000000)

Bit 1

#define GPIO_CRL_CNF   ((uint32_t)0xCCCCCCCC)

Port x configuration bits

#define GPIO_CRL_CNF0   ((uint32_t)0x0000000C)

CNF0[1:0] bits (Port x configuration bits, pin 0)

#define GPIO_CRL_CNF0_0   ((uint32_t)0x00000004)

Bit 0

#define GPIO_CRL_CNF0_1   ((uint32_t)0x00000008)

Bit 1

#define GPIO_CRL_CNF1   ((uint32_t)0x000000C0)

CNF1[1:0] bits (Port x configuration bits, pin 1)

#define GPIO_CRL_CNF1_0   ((uint32_t)0x00000040)

Bit 0

#define GPIO_CRL_CNF1_1   ((uint32_t)0x00000080)

Bit 1

#define GPIO_CRL_CNF2   ((uint32_t)0x00000C00)

CNF2[1:0] bits (Port x configuration bits, pin 2)

#define GPIO_CRL_CNF2_0   ((uint32_t)0x00000400)

Bit 0

#define GPIO_CRL_CNF2_1   ((uint32_t)0x00000800)

Bit 1

#define GPIO_CRL_CNF3   ((uint32_t)0x0000C000)

CNF3[1:0] bits (Port x configuration bits, pin 3)

#define GPIO_CRL_CNF3_0   ((uint32_t)0x00004000)

Bit 0

#define GPIO_CRL_CNF3_1   ((uint32_t)0x00008000)

Bit 1

#define GPIO_CRL_CNF4   ((uint32_t)0x000C0000)

CNF4[1:0] bits (Port x configuration bits, pin 4)

#define GPIO_CRL_CNF4_0   ((uint32_t)0x00040000)

Bit 0

#define GPIO_CRL_CNF4_1   ((uint32_t)0x00080000)

Bit 1

#define GPIO_CRL_CNF5   ((uint32_t)0x00C00000)

CNF5[1:0] bits (Port x configuration bits, pin 5)

#define GPIO_CRL_CNF5_0   ((uint32_t)0x00400000)

Bit 0

#define GPIO_CRL_CNF5_1   ((uint32_t)0x00800000)

Bit 1

#define GPIO_CRL_CNF6   ((uint32_t)0x0C000000)

CNF6[1:0] bits (Port x configuration bits, pin 6)

#define GPIO_CRL_CNF6_0   ((uint32_t)0x04000000)

Bit 0

#define GPIO_CRL_CNF6_1   ((uint32_t)0x08000000)

Bit 1

#define GPIO_CRL_CNF7   ((uint32_t)0xC0000000)

CNF7[1:0] bits (Port x configuration bits, pin 7)

#define GPIO_CRL_CNF7_0   ((uint32_t)0x40000000)

Bit 0

#define GPIO_CRL_CNF7_1   ((uint32_t)0x80000000)

Bit 1

#define GPIO_CRH_MODE   ((uint32_t)0x33333333)

Port x mode bits

#define GPIO_CRH_MODE8   ((uint32_t)0x00000003)

MODE8[1:0] bits (Port x mode bits, pin 8)

#define GPIO_CRH_MODE8_0   ((uint32_t)0x00000001)

Bit 0

#define GPIO_CRH_MODE8_1   ((uint32_t)0x00000002)

Bit 1

#define GPIO_CRH_MODE9   ((uint32_t)0x00000030)

MODE9[1:0] bits (Port x mode bits, pin 9)

#define GPIO_CRH_MODE9_0   ((uint32_t)0x00000010)

Bit 0

#define GPIO_CRH_MODE9_1   ((uint32_t)0x00000020)

Bit 1

#define GPIO_CRH_MODE10   ((uint32_t)0x00000300)

MODE10[1:0] bits (Port x mode bits, pin 10)

#define GPIO_CRH_MODE10_0   ((uint32_t)0x00000100)

Bit 0

#define GPIO_CRH_MODE10_1   ((uint32_t)0x00000200)

Bit 1

#define GPIO_CRH_MODE11   ((uint32_t)0x00003000)

MODE11[1:0] bits (Port x mode bits, pin 11)

#define GPIO_CRH_MODE11_0   ((uint32_t)0x00001000)

Bit 0

#define GPIO_CRH_MODE11_1   ((uint32_t)0x00002000)

Bit 1

#define GPIO_CRH_MODE12   ((uint32_t)0x00030000)

MODE12[1:0] bits (Port x mode bits, pin 12)

#define GPIO_CRH_MODE12_0   ((uint32_t)0x00010000)

Bit 0

#define GPIO_CRH_MODE12_1   ((uint32_t)0x00020000)

Bit 1

#define GPIO_CRH_MODE13   ((uint32_t)0x00300000)

MODE13[1:0] bits (Port x mode bits, pin 13)

#define GPIO_CRH_MODE13_0   ((uint32_t)0x00100000)

Bit 0

#define GPIO_CRH_MODE13_1   ((uint32_t)0x00200000)

Bit 1

#define GPIO_CRH_MODE14   ((uint32_t)0x03000000)

MODE14[1:0] bits (Port x mode bits, pin 14)

#define GPIO_CRH_MODE14_0   ((uint32_t)0x01000000)

Bit 0

#define GPIO_CRH_MODE14_1   ((uint32_t)0x02000000)

Bit 1

#define GPIO_CRH_MODE15   ((uint32_t)0x30000000)

MODE15[1:0] bits (Port x mode bits, pin 15)

#define GPIO_CRH_MODE15_0   ((uint32_t)0x10000000)

Bit 0

#define GPIO_CRH_MODE15_1   ((uint32_t)0x20000000)

Bit 1

#define GPIO_CRH_CNF   ((uint32_t)0xCCCCCCCC)

Port x configuration bits

#define GPIO_CRH_CNF8   ((uint32_t)0x0000000C)

CNF8[1:0] bits (Port x configuration bits, pin 8)

#define GPIO_CRH_CNF8_0   ((uint32_t)0x00000004)

Bit 0

#define GPIO_CRH_CNF8_1   ((uint32_t)0x00000008)

Bit 1

#define GPIO_CRH_CNF9   ((uint32_t)0x000000C0)

CNF9[1:0] bits (Port x configuration bits, pin 9)

#define GPIO_CRH_CNF9_0   ((uint32_t)0x00000040)

Bit 0

#define GPIO_CRH_CNF9_1   ((uint32_t)0x00000080)

Bit 1

#define GPIO_CRH_CNF10   ((uint32_t)0x00000C00)

CNF10[1:0] bits (Port x configuration bits, pin 10)

#define GPIO_CRH_CNF10_0   ((uint32_t)0x00000400)

Bit 0

#define GPIO_CRH_CNF10_1   ((uint32_t)0x00000800)

Bit 1

#define GPIO_CRH_CNF11   ((uint32_t)0x0000C000)

CNF11[1:0] bits (Port x configuration bits, pin 11)

#define GPIO_CRH_CNF11_0   ((uint32_t)0x00004000)

Bit 0

#define GPIO_CRH_CNF11_1   ((uint32_t)0x00008000)

Bit 1

#define GPIO_CRH_CNF12   ((uint32_t)0x000C0000)

CNF12[1:0] bits (Port x configuration bits, pin 12)

#define GPIO_CRH_CNF12_0   ((uint32_t)0x00040000)

Bit 0

#define GPIO_CRH_CNF12_1   ((uint32_t)0x00080000)

Bit 1

#define GPIO_CRH_CNF13   ((uint32_t)0x00C00000)

CNF13[1:0] bits (Port x configuration bits, pin 13)

#define GPIO_CRH_CNF13_0   ((uint32_t)0x00400000)

Bit 0

#define GPIO_CRH_CNF13_1   ((uint32_t)0x00800000)

Bit 1

#define GPIO_CRH_CNF14   ((uint32_t)0x0C000000)

CNF14[1:0] bits (Port x configuration bits, pin 14)

#define GPIO_CRH_CNF14_0   ((uint32_t)0x04000000)

Bit 0

#define GPIO_CRH_CNF14_1   ((uint32_t)0x08000000)

Bit 1

#define GPIO_CRH_CNF15   ((uint32_t)0xC0000000)

CNF15[1:0] bits (Port x configuration bits, pin 15)

#define GPIO_CRH_CNF15_0   ((uint32_t)0x40000000)

Bit 0

#define GPIO_CRH_CNF15_1   ((uint32_t)0x80000000)

Bit 1 ****************** Bit definition for GPIO_IDR register

#define GPIO_IDR_IDR0   ((uint16_t)0x0001)

Port input data, bit 0

#define GPIO_IDR_IDR1   ((uint16_t)0x0002)

Port input data, bit 1

#define GPIO_IDR_IDR2   ((uint16_t)0x0004)

Port input data, bit 2

#define GPIO_IDR_IDR3   ((uint16_t)0x0008)

Port input data, bit 3

#define GPIO_IDR_IDR4   ((uint16_t)0x0010)

Port input data, bit 4

#define GPIO_IDR_IDR5   ((uint16_t)0x0020)

Port input data, bit 5

#define GPIO_IDR_IDR6   ((uint16_t)0x0040)

Port input data, bit 6

#define GPIO_IDR_IDR7   ((uint16_t)0x0080)

Port input data, bit 7

#define GPIO_IDR_IDR8   ((uint16_t)0x0100)

Port input data, bit 8

#define GPIO_IDR_IDR9   ((uint16_t)0x0200)

Port input data, bit 9

#define GPIO_IDR_IDR10   ((uint16_t)0x0400)

Port input data, bit 10

#define GPIO_IDR_IDR11   ((uint16_t)0x0800)

Port input data, bit 11

#define GPIO_IDR_IDR12   ((uint16_t)0x1000)

Port input data, bit 12

#define GPIO_IDR_IDR13   ((uint16_t)0x2000)

Port input data, bit 13

#define GPIO_IDR_IDR14   ((uint16_t)0x4000)

Port input data, bit 14

#define GPIO_IDR_IDR15   ((uint16_t)0x8000)

Port input data, bit 15

#define GPIO_ODR_ODR0   ((uint16_t)0x0001)

Port output data, bit 0

#define GPIO_ODR_ODR1   ((uint16_t)0x0002)

Port output data, bit 1

#define GPIO_ODR_ODR2   ((uint16_t)0x0004)

Port output data, bit 2

#define GPIO_ODR_ODR3   ((uint16_t)0x0008)

Port output data, bit 3

#define GPIO_ODR_ODR4   ((uint16_t)0x0010)

Port output data, bit 4

#define GPIO_ODR_ODR5   ((uint16_t)0x0020)

Port output data, bit 5

#define GPIO_ODR_ODR6   ((uint16_t)0x0040)

Port output data, bit 6

#define GPIO_ODR_ODR7   ((uint16_t)0x0080)

Port output data, bit 7

#define GPIO_ODR_ODR8   ((uint16_t)0x0100)

Port output data, bit 8

#define GPIO_ODR_ODR9   ((uint16_t)0x0200)

Port output data, bit 9

#define GPIO_ODR_ODR10   ((uint16_t)0x0400)

Port output data, bit 10

#define GPIO_ODR_ODR11   ((uint16_t)0x0800)

Port output data, bit 11

#define GPIO_ODR_ODR12   ((uint16_t)0x1000)

Port output data, bit 12

#define GPIO_ODR_ODR13   ((uint16_t)0x2000)

Port output data, bit 13

#define GPIO_ODR_ODR14   ((uint16_t)0x4000)

Port output data, bit 14

#define GPIO_ODR_ODR15   ((uint16_t)0x8000)

Port output data, bit 15

#define GPIO_BSRR_BS0   ((uint32_t)0x00000001)

Port x Set bit 0

#define GPIO_BSRR_BS1   ((uint32_t)0x00000002)

Port x Set bit 1

#define GPIO_BSRR_BS2   ((uint32_t)0x00000004)

Port x Set bit 2

#define GPIO_BSRR_BS3   ((uint32_t)0x00000008)

Port x Set bit 3

#define GPIO_BSRR_BS4   ((uint32_t)0x00000010)

Port x Set bit 4

#define GPIO_BSRR_BS5   ((uint32_t)0x00000020)

Port x Set bit 5

#define GPIO_BSRR_BS6   ((uint32_t)0x00000040)

Port x Set bit 6

#define GPIO_BSRR_BS7   ((uint32_t)0x00000080)

Port x Set bit 7

#define GPIO_BSRR_BS8   ((uint32_t)0x00000100)

Port x Set bit 8

#define GPIO_BSRR_BS9   ((uint32_t)0x00000200)

Port x Set bit 9

#define GPIO_BSRR_BS10   ((uint32_t)0x00000400)

Port x Set bit 10

#define GPIO_BSRR_BS11   ((uint32_t)0x00000800)

Port x Set bit 11

#define GPIO_BSRR_BS12   ((uint32_t)0x00001000)

Port x Set bit 12

#define GPIO_BSRR_BS13   ((uint32_t)0x00002000)

Port x Set bit 13

#define GPIO_BSRR_BS14   ((uint32_t)0x00004000)

Port x Set bit 14

#define GPIO_BSRR_BS15   ((uint32_t)0x00008000)

Port x Set bit 15

#define GPIO_BSRR_BR0   ((uint32_t)0x00010000)

Port x Reset bit 0

#define GPIO_BSRR_BR1   ((uint32_t)0x00020000)

Port x Reset bit 1

#define GPIO_BSRR_BR2   ((uint32_t)0x00040000)

Port x Reset bit 2

#define GPIO_BSRR_BR3   ((uint32_t)0x00080000)

Port x Reset bit 3

#define GPIO_BSRR_BR4   ((uint32_t)0x00100000)

Port x Reset bit 4

#define GPIO_BSRR_BR5   ((uint32_t)0x00200000)

Port x Reset bit 5

#define GPIO_BSRR_BR6   ((uint32_t)0x00400000)

Port x Reset bit 6

#define GPIO_BSRR_BR7   ((uint32_t)0x00800000)

Port x Reset bit 7

#define GPIO_BSRR_BR8   ((uint32_t)0x01000000)

Port x Reset bit 8

#define GPIO_BSRR_BR9   ((uint32_t)0x02000000)

Port x Reset bit 9

#define GPIO_BSRR_BR10   ((uint32_t)0x04000000)

Port x Reset bit 10

#define GPIO_BSRR_BR11   ((uint32_t)0x08000000)

Port x Reset bit 11

#define GPIO_BSRR_BR12   ((uint32_t)0x10000000)

Port x Reset bit 12

#define GPIO_BSRR_BR13   ((uint32_t)0x20000000)

Port x Reset bit 13

#define GPIO_BSRR_BR14   ((uint32_t)0x40000000)

Port x Reset bit 14

#define GPIO_BSRR_BR15   ((uint32_t)0x80000000)

Port x Reset bit 15

#define GPIO_BRR_BR0   ((uint16_t)0x0001)

Port x Reset bit 0

#define GPIO_BRR_BR1   ((uint16_t)0x0002)

Port x Reset bit 1

#define GPIO_BRR_BR2   ((uint16_t)0x0004)

Port x Reset bit 2

#define GPIO_BRR_BR3   ((uint16_t)0x0008)

Port x Reset bit 3

#define GPIO_BRR_BR4   ((uint16_t)0x0010)

Port x Reset bit 4

#define GPIO_BRR_BR5   ((uint16_t)0x0020)

Port x Reset bit 5

#define GPIO_BRR_BR6   ((uint16_t)0x0040)

Port x Reset bit 6

#define GPIO_BRR_BR7   ((uint16_t)0x0080)

Port x Reset bit 7

#define GPIO_BRR_BR8   ((uint16_t)0x0100)

Port x Reset bit 8

#define GPIO_BRR_BR9   ((uint16_t)0x0200)

Port x Reset bit 9

#define GPIO_BRR_BR10   ((uint16_t)0x0400)

Port x Reset bit 10

#define GPIO_BRR_BR11   ((uint16_t)0x0800)

Port x Reset bit 11

#define GPIO_BRR_BR12   ((uint16_t)0x1000)

Port x Reset bit 12

#define GPIO_BRR_BR13   ((uint16_t)0x2000)

Port x Reset bit 13

#define GPIO_BRR_BR14   ((uint16_t)0x4000)

Port x Reset bit 14

#define GPIO_BRR_BR15   ((uint16_t)0x8000)

Port x Reset bit 15

#define GPIO_LCKR_LCK0   ((uint32_t)0x00000001)

Port x Lock bit 0

#define GPIO_LCKR_LCK1   ((uint32_t)0x00000002)

Port x Lock bit 1

#define GPIO_LCKR_LCK2   ((uint32_t)0x00000004)

Port x Lock bit 2

#define GPIO_LCKR_LCK3   ((uint32_t)0x00000008)

Port x Lock bit 3

#define GPIO_LCKR_LCK4   ((uint32_t)0x00000010)

Port x Lock bit 4

#define GPIO_LCKR_LCK5   ((uint32_t)0x00000020)

Port x Lock bit 5

#define GPIO_LCKR_LCK6   ((uint32_t)0x00000040)

Port x Lock bit 6

#define GPIO_LCKR_LCK7   ((uint32_t)0x00000080)

Port x Lock bit 7

#define GPIO_LCKR_LCK8   ((uint32_t)0x00000100)

Port x Lock bit 8

#define GPIO_LCKR_LCK9   ((uint32_t)0x00000200)

Port x Lock bit 9

#define GPIO_LCKR_LCK10   ((uint32_t)0x00000400)

Port x Lock bit 10

#define GPIO_LCKR_LCK11   ((uint32_t)0x00000800)

Port x Lock bit 11

#define GPIO_LCKR_LCK12   ((uint32_t)0x00001000)

Port x Lock bit 12

#define GPIO_LCKR_LCK13   ((uint32_t)0x00002000)

Port x Lock bit 13

#define GPIO_LCKR_LCK14   ((uint32_t)0x00004000)

Port x Lock bit 14

#define GPIO_LCKR_LCK15   ((uint32_t)0x00008000)

Port x Lock bit 15

#define GPIO_LCKR_LCKK   ((uint32_t)0x00010000)

Lock key

#define AFIO_EVCR_PIN   ((uint8_t)0x0F)

PIN[3:0] bits (Pin selection)

#define AFIO_EVCR_PIN_0   ((uint8_t)0x01)

Bit 0

#define AFIO_EVCR_PIN_1   ((uint8_t)0x02)

Bit 1

#define AFIO_EVCR_PIN_2   ((uint8_t)0x04)

Bit 2

#define AFIO_EVCR_PIN_3   ((uint8_t)0x08)

Bit 3 PIN configuration

#define AFIO_EVCR_PIN_PX0   ((uint8_t)0x00)

Pin 0 selected

#define AFIO_EVCR_PIN_PX1   ((uint8_t)0x01)

Pin 1 selected

#define AFIO_EVCR_PIN_PX2   ((uint8_t)0x02)

Pin 2 selected

#define AFIO_EVCR_PIN_PX3   ((uint8_t)0x03)

Pin 3 selected

#define AFIO_EVCR_PIN_PX4   ((uint8_t)0x04)

Pin 4 selected

#define AFIO_EVCR_PIN_PX5   ((uint8_t)0x05)

Pin 5 selected

#define AFIO_EVCR_PIN_PX6   ((uint8_t)0x06)

Pin 6 selected

#define AFIO_EVCR_PIN_PX7   ((uint8_t)0x07)

Pin 7 selected

#define AFIO_EVCR_PIN_PX8   ((uint8_t)0x08)

Pin 8 selected

#define AFIO_EVCR_PIN_PX9   ((uint8_t)0x09)

Pin 9 selected

#define AFIO_EVCR_PIN_PX10   ((uint8_t)0x0A)

Pin 10 selected

#define AFIO_EVCR_PIN_PX11   ((uint8_t)0x0B)

Pin 11 selected

#define AFIO_EVCR_PIN_PX12   ((uint8_t)0x0C)

Pin 12 selected

#define AFIO_EVCR_PIN_PX13   ((uint8_t)0x0D)

Pin 13 selected

#define AFIO_EVCR_PIN_PX14   ((uint8_t)0x0E)

Pin 14 selected

#define AFIO_EVCR_PIN_PX15   ((uint8_t)0x0F)

Pin 15 selected

#define AFIO_EVCR_PORT   ((uint8_t)0x70)

PORT[2:0] bits (Port selection)

#define AFIO_EVCR_PORT_0   ((uint8_t)0x10)

Bit 0

#define AFIO_EVCR_PORT_1   ((uint8_t)0x20)

Bit 1

#define AFIO_EVCR_PORT_2   ((uint8_t)0x40)

Bit 2 PORT configuration

#define AFIO_EVCR_PORT_PA   ((uint8_t)0x00)

Port A selected

#define AFIO_EVCR_PORT_PB   ((uint8_t)0x10)

Port B selected

#define AFIO_EVCR_PORT_PC   ((uint8_t)0x20)

Port C selected

#define AFIO_EVCR_PORT_PD   ((uint8_t)0x30)

Port D selected

#define AFIO_EVCR_PORT_PE   ((uint8_t)0x40)

Port E selected

#define AFIO_EVCR_EVOE   ((uint8_t)0x80)

Event Output Enable

#define AFIO_MAPR_SPI1_REMAP   ((uint32_t)0x00000001)

SPI1 remapping

#define AFIO_MAPR_I2C1_REMAP   ((uint32_t)0x00000002)

I2C1 remapping

#define AFIO_MAPR_USART1_REMAP   ((uint32_t)0x00000004)

USART1 remapping

#define AFIO_MAPR_USART2_REMAP   ((uint32_t)0x00000008)

USART2 remapping

#define AFIO_MAPR_USART3_REMAP   ((uint32_t)0x00000030)

USART3_REMAP[1:0] bits (USART3 remapping)

#define AFIO_MAPR_USART3_REMAP_0   ((uint32_t)0x00000010)

Bit 0

#define AFIO_MAPR_USART3_REMAP_1   ((uint32_t)0x00000020)

Bit 1

#define AFIO_MAPR_USART3_REMAP_NOREMAP   ((uint32_t)0x00000000)

No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)

#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP   ((uint32_t)0x00000010)

Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)

#define AFIO_MAPR_USART3_REMAP_FULLREMAP   ((uint32_t)0x00000030)

Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12)

#define AFIO_MAPR_TIM1_REMAP   ((uint32_t)0x000000C0)

TIM1_REMAP[1:0] bits (TIM1 remapping)

#define AFIO_MAPR_TIM1_REMAP_0   ((uint32_t)0x00000040)

Bit 0

#define AFIO_MAPR_TIM1_REMAP_1   ((uint32_t)0x00000080)

Bit 1 TIM1_REMAP configuration

#define AFIO_MAPR_TIM1_REMAP_NOREMAP   ((uint32_t)0x00000000)

No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)

#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP   ((uint32_t)0x00000040)

Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1)

#define AFIO_MAPR_TIM1_REMAP_FULLREMAP   ((uint32_t)0x000000C0)

Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12)

#define AFIO_MAPR_TIM2_REMAP   ((uint32_t)0x00000300)

TIM2_REMAP[1:0] bits (TIM2 remapping)

#define AFIO_MAPR_TIM2_REMAP_0   ((uint32_t)0x00000100)

Bit 0

#define AFIO_MAPR_TIM2_REMAP_1   ((uint32_t)0x00000200)

Bit 1 TIM2_REMAP configuration

#define AFIO_MAPR_TIM2_REMAP_NOREMAP   ((uint32_t)0x00000000)

No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3)

#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1   ((uint32_t)0x00000100)

Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3)

#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2   ((uint32_t)0x00000200)

Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11)

#define AFIO_MAPR_TIM2_REMAP_FULLREMAP   ((uint32_t)0x00000300)

Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)

#define AFIO_MAPR_TIM3_REMAP   ((uint32_t)0x00000C00)

TIM3_REMAP[1:0] bits (TIM3 remapping)

#define AFIO_MAPR_TIM3_REMAP_0   ((uint32_t)0x00000400)

Bit 0

#define AFIO_MAPR_TIM3_REMAP_1   ((uint32_t)0x00000800)

Bit 1 TIM3_REMAP configuration

#define AFIO_MAPR_TIM3_REMAP_NOREMAP   ((uint32_t)0x00000000)

No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1)

#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP   ((uint32_t)0x00000800)

Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1)

#define AFIO_MAPR_TIM3_REMAP_FULLREMAP   ((uint32_t)0x00000C00)

Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9)

#define AFIO_MAPR_TIM4_REMAP   ((uint32_t)0x00001000)

TIM4_REMAP bit (TIM4 remapping)

#define AFIO_MAPR_CAN_REMAP   ((uint32_t)0x00006000)

CAN_REMAP[1:0] bits (CAN Alternate function remapping)

#define AFIO_MAPR_CAN_REMAP_0   ((uint32_t)0x00002000)

Bit 0

#define AFIO_MAPR_CAN_REMAP_1   ((uint32_t)0x00004000)

Bit 1 CAN_REMAP configuration

#define AFIO_MAPR_CAN_REMAP_REMAP1   ((uint32_t)0x00000000)

CANRX mapped to PA11, CANTX mapped to PA12

#define AFIO_MAPR_CAN_REMAP_REMAP2   ((uint32_t)0x00004000)

CANRX mapped to PB8, CANTX mapped to PB9

#define AFIO_MAPR_CAN_REMAP_REMAP3   ((uint32_t)0x00006000)

CANRX mapped to PD0, CANTX mapped to PD1

#define AFIO_MAPR_PD01_REMAP   ((uint32_t)0x00008000)

Port D0/Port D1 mapping on OSC_IN/OSC_OUT

#define AFIO_MAPR_TIM5CH4_IREMAP   ((uint32_t)0x00010000)

TIM5 Channel4 Internal Remap

#define AFIO_MAPR_ADC1_ETRGINJ_REMAP   ((uint32_t)0x00020000)

ADC 1 External Trigger Injected Conversion remapping

#define AFIO_MAPR_ADC1_ETRGREG_REMAP   ((uint32_t)0x00040000)

ADC 1 External Trigger Regular Conversion remapping

#define AFIO_MAPR_ADC2_ETRGINJ_REMAP   ((uint32_t)0x00080000)

ADC 2 External Trigger Injected Conversion remapping

#define AFIO_MAPR_ADC2_ETRGREG_REMAP   ((uint32_t)0x00100000)

ADC 2 External Trigger Regular Conversion remapping SWJ_CFG configuration

#define AFIO_MAPR_SWJ_CFG   ((uint32_t)0x07000000)

SWJ_CFG[2:0] bits (Serial Wire JTAG configuration)

#define AFIO_MAPR_SWJ_CFG_0   ((uint32_t)0x01000000)

Bit 0

#define AFIO_MAPR_SWJ_CFG_1   ((uint32_t)0x02000000)

Bit 1

#define AFIO_MAPR_SWJ_CFG_2   ((uint32_t)0x04000000)

Bit 2

#define AFIO_MAPR_SWJ_CFG_RESET   ((uint32_t)0x00000000)

Full SWJ (JTAG-DP + SW-DP) : Reset State

#define AFIO_MAPR_SWJ_CFG_NOJNTRST   ((uint32_t)0x01000000)

Full SWJ (JTAG-DP + SW-DP) but without JNTRST

#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE   ((uint32_t)0x02000000)

JTAG-DP Disabled and SW-DP Enabled

#define AFIO_MAPR_SWJ_CFG_DISABLE   ((uint32_t)0x04000000)

JTAG-DP Disabled and SW-DP Disabled

#define AFIO_EXTICR1_EXTI0   ((uint16_t)0x000F)

EXTI 0 configuration

#define AFIO_EXTICR1_EXTI1   ((uint16_t)0x00F0)

EXTI 1 configuration

#define AFIO_EXTICR1_EXTI2   ((uint16_t)0x0F00)

EXTI 2 configuration

#define AFIO_EXTICR1_EXTI3   ((uint16_t)0xF000)

EXTI 3 configuration EXTI0 configuration

#define AFIO_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)

PA[0] pin

#define AFIO_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)

PB[0] pin

#define AFIO_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)

PC[0] pin

#define AFIO_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)

PD[0] pin

#define AFIO_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)

PE[0] pin

#define AFIO_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)

PF[0] pin

#define AFIO_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)

PG[0] pin EXTI1 configuration

#define AFIO_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)

PA[1] pin

#define AFIO_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)

PB[1] pin

#define AFIO_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)

PC[1] pin

#define AFIO_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)

PD[1] pin

#define AFIO_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)

PE[1] pin

#define AFIO_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)

PF[1] pin

#define AFIO_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)

PG[1] pin EXTI2 configuration

#define AFIO_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)

PA[2] pin

#define AFIO_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)

PB[2] pin

#define AFIO_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)

PC[2] pin

#define AFIO_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)

PD[2] pin

#define AFIO_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)

PE[2] pin

#define AFIO_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)

PF[2] pin

#define AFIO_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)

PG[2] pin EXTI3 configuration

#define AFIO_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)

PA[3] pin

#define AFIO_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)

PB[3] pin

#define AFIO_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)

PC[3] pin

#define AFIO_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)

PD[3] pin

#define AFIO_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)

PE[3] pin

#define AFIO_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)

PF[3] pin

#define AFIO_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)

PG[3] pin

#define AFIO_EXTICR2_EXTI4   ((uint16_t)0x000F)

EXTI 4 configuration

#define AFIO_EXTICR2_EXTI5   ((uint16_t)0x00F0)

EXTI 5 configuration

#define AFIO_EXTICR2_EXTI6   ((uint16_t)0x0F00)

EXTI 6 configuration

#define AFIO_EXTICR2_EXTI7   ((uint16_t)0xF000)

EXTI 7 configuration EXTI4 configuration

#define AFIO_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)

PA[4] pin

#define AFIO_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)

PB[4] pin

#define AFIO_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)

PC[4] pin

#define AFIO_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)

PD[4] pin

#define AFIO_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)

PE[4] pin

#define AFIO_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)

PF[4] pin

#define AFIO_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)

PG[4] pin

#define AFIO_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)

PA[5] pin

#define AFIO_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)

PB[5] pin

#define AFIO_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)

PC[5] pin

#define AFIO_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)

PD[5] pin

#define AFIO_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)

PE[5] pin

#define AFIO_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)

PF[5] pin

#define AFIO_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)

PG[5] pin EXTI6 configuration

#define AFIO_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)

PA[6] pin

#define AFIO_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)

PB[6] pin

#define AFIO_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)

PC[6] pin

#define AFIO_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)

PD[6] pin

#define AFIO_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)

PE[6] pin

#define AFIO_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)

PF[6] pin

#define AFIO_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)

PG[6] pin EXTI7 configuration

#define AFIO_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)

PA[7] pin

#define AFIO_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)

PB[7] pin

#define AFIO_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)

PC[7] pin

#define AFIO_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)

PD[7] pin

#define AFIO_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)

PE[7] pin

#define AFIO_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)

PF[7] pin

#define AFIO_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)

PG[7] pin

#define AFIO_EXTICR3_EXTI8   ((uint16_t)0x000F)

EXTI 8 configuration

#define AFIO_EXTICR3_EXTI9   ((uint16_t)0x00F0)

EXTI 9 configuration

#define AFIO_EXTICR3_EXTI10   ((uint16_t)0x0F00)

EXTI 10 configuration

#define AFIO_EXTICR3_EXTI11   ((uint16_t)0xF000)

EXTI 11 configuration EXTI8 configuration

#define AFIO_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)

PA[8] pin

#define AFIO_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)

PB[8] pin

#define AFIO_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)

PC[8] pin

#define AFIO_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)

PD[8] pin

#define AFIO_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)

PE[8] pin

#define AFIO_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)

PF[8] pin

#define AFIO_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)

PG[8] pin EXTI9 configuration

#define AFIO_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)

PA[9] pin

#define AFIO_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)

PB[9] pin

#define AFIO_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)

PC[9] pin

#define AFIO_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)

PD[9] pin

#define AFIO_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)

PE[9] pin

#define AFIO_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)

PF[9] pin

#define AFIO_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)

PG[9] pin EXTI10 configuration

#define AFIO_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)

PA[10] pin

#define AFIO_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)

PB[10] pin

#define AFIO_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)

PC[10] pin

#define AFIO_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)

PD[10] pin

#define AFIO_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)

PE[10] pin

#define AFIO_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)

PF[10] pin

#define AFIO_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)

PG[10] pin EXTI11 configuration

#define AFIO_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)

PA[11] pin

#define AFIO_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)

PB[11] pin

#define AFIO_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)

PC[11] pin

#define AFIO_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)

PD[11] pin

#define AFIO_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)

PE[11] pin

#define AFIO_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)

PF[11] pin

#define AFIO_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)

PG[11] pin

#define AFIO_EXTICR4_EXTI12   ((uint16_t)0x000F)

EXTI 12 configuration

#define AFIO_EXTICR4_EXTI13   ((uint16_t)0x00F0)

EXTI 13 configuration

#define AFIO_EXTICR4_EXTI14   ((uint16_t)0x0F00)

EXTI 14 configuration

#define AFIO_EXTICR4_EXTI15   ((uint16_t)0xF000)

EXTI 15 configuration

#define AFIO_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)

PA[12] pin

#define AFIO_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)

PB[12] pin

#define AFIO_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)

PC[12] pin

#define AFIO_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)

PD[12] pin

#define AFIO_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)

PE[12] pin

#define AFIO_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)

PF[12] pin

#define AFIO_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)

PG[12] pin

#define AFIO_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)

PA[13] pin

#define AFIO_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)

PB[13] pin

#define AFIO_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)

PC[13] pin

#define AFIO_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)

PD[13] pin

#define AFIO_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)

PE[13] pin

#define AFIO_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)

PF[13] pin

#define AFIO_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)

PG[13] pin EXTI14 configuration

#define AFIO_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)

PA[14] pin

#define AFIO_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)

PB[14] pin

#define AFIO_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)

PC[14] pin

#define AFIO_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)

PD[14] pin

#define AFIO_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)

PE[14] pin

#define AFIO_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)

PF[14] pin

#define AFIO_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)

PG[14] pin EXTI15 configuration

#define AFIO_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)

PA[15] pin

#define AFIO_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)

PB[15] pin

#define AFIO_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)

PC[15] pin

#define AFIO_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)

PD[15] pin

#define AFIO_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)

PE[15] pin

#define AFIO_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)

PF[15] pin

#define AFIO_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)

PG[15] pin

#define SysTick_CTRL_ENABLE   ((uint32_t)0x00000001)

Counter enable

#define SysTick_CTRL_TICKINT   ((uint32_t)0x00000002)

Counting down to 0 pends the SysTick handler

#define SysTick_CTRL_CLKSOURCE   ((uint32_t)0x00000004)

Clock source

#define SysTick_CTRL_COUNTFLAG   ((uint32_t)0x00010000)

Count Flag

#define SysTick_LOAD_RELOAD   ((uint32_t)0x00FFFFFF)

Value to load into the SysTick Current Value Register when the counter reaches 0

#define SysTick_VAL_CURRENT   ((uint32_t)0x00FFFFFF)

Current value at the time the register is accessed

#define SysTick_CALIB_TENMS   ((uint32_t)0x00FFFFFF)

Reload value to use for 10ms timing

#define SysTick_CALIB_SKEW   ((uint32_t)0x40000000)

Calibration value is not exactly 10 ms

#define SysTick_CALIB_NOREF   ((uint32_t)0x80000000)

The reference clock is not provided

#define NVIC_ISER_SETENA   ((uint32_t)0xFFFFFFFF)

Interrupt set enable bits

#define NVIC_ISER_SETENA_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ISER_SETENA_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ISER_SETENA_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ISER_SETENA_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ISER_SETENA_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ISER_SETENA_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ISER_SETENA_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ISER_SETENA_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ISER_SETENA_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ISER_SETENA_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ISER_SETENA_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ISER_SETENA_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ISER_SETENA_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ISER_SETENA_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ISER_SETENA_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ISER_SETENA_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ISER_SETENA_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ISER_SETENA_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ISER_SETENA_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ISER_SETENA_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ISER_SETENA_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ISER_SETENA_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ISER_SETENA_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ISER_SETENA_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ISER_SETENA_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ISER_SETENA_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ISER_SETENA_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ISER_SETENA_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ISER_SETENA_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ISER_SETENA_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ISER_SETENA_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ISER_SETENA_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ICER_CLRENA   ((uint32_t)0xFFFFFFFF)

Interrupt clear-enable bits

#define NVIC_ICER_CLRENA_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ICER_CLRENA_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ICER_CLRENA_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ICER_CLRENA_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ICER_CLRENA_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ICER_CLRENA_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ICER_CLRENA_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ICER_CLRENA_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ICER_CLRENA_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ICER_CLRENA_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ICER_CLRENA_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ICER_CLRENA_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ICER_CLRENA_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ICER_CLRENA_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ICER_CLRENA_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ICER_CLRENA_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ICER_CLRENA_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ICER_CLRENA_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ICER_CLRENA_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ICER_CLRENA_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ICER_CLRENA_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ICER_CLRENA_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ICER_CLRENA_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ICER_CLRENA_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ICER_CLRENA_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ICER_CLRENA_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ICER_CLRENA_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ICER_CLRENA_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ICER_CLRENA_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ICER_CLRENA_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ICER_CLRENA_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ICER_CLRENA_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ISPR_SETPEND   ((uint32_t)0xFFFFFFFF)

Interrupt set-pending bits

#define NVIC_ISPR_SETPEND_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ISPR_SETPEND_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ISPR_SETPEND_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ISPR_SETPEND_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ISPR_SETPEND_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ISPR_SETPEND_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ISPR_SETPEND_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ISPR_SETPEND_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ISPR_SETPEND_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ISPR_SETPEND_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ISPR_SETPEND_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ISPR_SETPEND_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ISPR_SETPEND_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ISPR_SETPEND_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ISPR_SETPEND_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ISPR_SETPEND_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ISPR_SETPEND_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ISPR_SETPEND_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ISPR_SETPEND_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ISPR_SETPEND_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ISPR_SETPEND_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ISPR_SETPEND_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ISPR_SETPEND_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ISPR_SETPEND_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ISPR_SETPEND_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ISPR_SETPEND_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ISPR_SETPEND_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ISPR_SETPEND_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ISPR_SETPEND_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ISPR_SETPEND_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ISPR_SETPEND_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ISPR_SETPEND_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ICPR_CLRPEND   ((uint32_t)0xFFFFFFFF)

Interrupt clear-pending bits

#define NVIC_ICPR_CLRPEND_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ICPR_CLRPEND_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ICPR_CLRPEND_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ICPR_CLRPEND_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ICPR_CLRPEND_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ICPR_CLRPEND_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ICPR_CLRPEND_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ICPR_CLRPEND_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ICPR_CLRPEND_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ICPR_CLRPEND_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ICPR_CLRPEND_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ICPR_CLRPEND_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ICPR_CLRPEND_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ICPR_CLRPEND_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ICPR_CLRPEND_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ICPR_CLRPEND_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ICPR_CLRPEND_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ICPR_CLRPEND_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ICPR_CLRPEND_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ICPR_CLRPEND_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ICPR_CLRPEND_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ICPR_CLRPEND_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ICPR_CLRPEND_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ICPR_CLRPEND_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ICPR_CLRPEND_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ICPR_CLRPEND_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ICPR_CLRPEND_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ICPR_CLRPEND_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ICPR_CLRPEND_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ICPR_CLRPEND_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ICPR_CLRPEND_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ICPR_CLRPEND_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_IABR_ACTIVE   ((uint32_t)0xFFFFFFFF)

Interrupt active flags

#define NVIC_IABR_ACTIVE_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_IABR_ACTIVE_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_IABR_ACTIVE_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_IABR_ACTIVE_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_IABR_ACTIVE_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_IABR_ACTIVE_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_IABR_ACTIVE_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_IABR_ACTIVE_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_IABR_ACTIVE_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_IABR_ACTIVE_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_IABR_ACTIVE_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_IABR_ACTIVE_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_IABR_ACTIVE_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_IABR_ACTIVE_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_IABR_ACTIVE_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_IABR_ACTIVE_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_IABR_ACTIVE_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_IABR_ACTIVE_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_IABR_ACTIVE_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_IABR_ACTIVE_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_IABR_ACTIVE_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_IABR_ACTIVE_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_IABR_ACTIVE_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_IABR_ACTIVE_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_IABR_ACTIVE_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_IABR_ACTIVE_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_IABR_ACTIVE_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_IABR_ACTIVE_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_IABR_ACTIVE_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_IABR_ACTIVE_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_IABR_ACTIVE_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_IABR_ACTIVE_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_IPR0_PRI_0   ((uint32_t)0x000000FF)

Priority of interrupt 0

#define NVIC_IPR0_PRI_1   ((uint32_t)0x0000FF00)

Priority of interrupt 1

#define NVIC_IPR0_PRI_2   ((uint32_t)0x00FF0000)

Priority of interrupt 2

#define NVIC_IPR0_PRI_3   ((uint32_t)0xFF000000)

Priority of interrupt 3

#define NVIC_IPR1_PRI_4   ((uint32_t)0x000000FF)

Priority of interrupt 4

#define NVIC_IPR1_PRI_5   ((uint32_t)0x0000FF00)

Priority of interrupt 5

#define NVIC_IPR1_PRI_6   ((uint32_t)0x00FF0000)

Priority of interrupt 6

#define NVIC_IPR1_PRI_7   ((uint32_t)0xFF000000)

Priority of interrupt 7

#define NVIC_IPR2_PRI_8   ((uint32_t)0x000000FF)

Priority of interrupt 8

#define NVIC_IPR2_PRI_9   ((uint32_t)0x0000FF00)

Priority of interrupt 9

#define NVIC_IPR2_PRI_10   ((uint32_t)0x00FF0000)

Priority of interrupt 10

#define NVIC_IPR2_PRI_11   ((uint32_t)0xFF000000)

Priority of interrupt 11

#define NVIC_IPR3_PRI_12   ((uint32_t)0x000000FF)

Priority of interrupt 12

#define NVIC_IPR3_PRI_13   ((uint32_t)0x0000FF00)

Priority of interrupt 13

#define NVIC_IPR3_PRI_14   ((uint32_t)0x00FF0000)

Priority of interrupt 14

#define NVIC_IPR3_PRI_15   ((uint32_t)0xFF000000)

Priority of interrupt 15

#define NVIC_IPR4_PRI_16   ((uint32_t)0x000000FF)

Priority of interrupt 16

#define NVIC_IPR4_PRI_17   ((uint32_t)0x0000FF00)

Priority of interrupt 17

#define NVIC_IPR4_PRI_18   ((uint32_t)0x00FF0000)

Priority of interrupt 18

#define NVIC_IPR4_PRI_19   ((uint32_t)0xFF000000)

Priority of interrupt 19

#define NVIC_IPR5_PRI_20   ((uint32_t)0x000000FF)

Priority of interrupt 20

#define NVIC_IPR5_PRI_21   ((uint32_t)0x0000FF00)

Priority of interrupt 21

#define NVIC_IPR5_PRI_22   ((uint32_t)0x00FF0000)

Priority of interrupt 22

#define NVIC_IPR5_PRI_23   ((uint32_t)0xFF000000)

Priority of interrupt 23

#define NVIC_IPR6_PRI_24   ((uint32_t)0x000000FF)

Priority of interrupt 24

#define NVIC_IPR6_PRI_25   ((uint32_t)0x0000FF00)

Priority of interrupt 25

#define NVIC_IPR6_PRI_26   ((uint32_t)0x00FF0000)

Priority of interrupt 26

#define NVIC_IPR6_PRI_27   ((uint32_t)0xFF000000)

Priority of interrupt 27

#define NVIC_IPR7_PRI_28   ((uint32_t)0x000000FF)

Priority of interrupt 28

#define NVIC_IPR7_PRI_29   ((uint32_t)0x0000FF00)

Priority of interrupt 29

#define NVIC_IPR7_PRI_30   ((uint32_t)0x00FF0000)

Priority of interrupt 30

#define NVIC_IPR7_PRI_31   ((uint32_t)0xFF000000)

Priority of interrupt 31

#define SCB_CPUID_REVISION   ((uint32_t)0x0000000F)

Implementation defined revision number

#define SCB_CPUID_PARTNO   ((uint32_t)0x0000FFF0)

Number of processor within family

#define SCB_CPUID_Constant   ((uint32_t)0x000F0000)

Reads as 0x0F

#define SCB_CPUID_VARIANT   ((uint32_t)0x00F00000)

Implementation defined variant number

#define SCB_CPUID_IMPLEMENTER   ((uint32_t)0xFF000000)

Implementer code. ARM is 0x41

#define SCB_ICSR_VECTACTIVE   ((uint32_t)0x000001FF)

Active ISR number field

#define SCB_ICSR_RETTOBASE   ((uint32_t)0x00000800)

All active exceptions minus the IPSR_current_exception yields the empty set

#define SCB_ICSR_VECTPENDING   ((uint32_t)0x003FF000)

Pending ISR number field

#define SCB_ICSR_ISRPENDING   ((uint32_t)0x00400000)

Interrupt pending flag

#define SCB_ICSR_ISRPREEMPT   ((uint32_t)0x00800000)

It indicates that a pending interrupt becomes active in the next running cycle

#define SCB_ICSR_PENDSTCLR   ((uint32_t)0x02000000)

Clear pending SysTick bit

#define SCB_ICSR_PENDSTSET   ((uint32_t)0x04000000)

Set pending SysTick bit

#define SCB_ICSR_PENDSVCLR   ((uint32_t)0x08000000)

Clear pending pendSV bit

#define SCB_ICSR_PENDSVSET   ((uint32_t)0x10000000)

Set pending pendSV bit

#define SCB_ICSR_NMIPENDSET   ((uint32_t)0x80000000)

Set pending NMI bit

#define SCB_VTOR_TBLOFF   ((uint32_t)0x1FFFFF80)

Vector table base offset field

#define SCB_VTOR_TBLBASE   ((uint32_t)0x20000000)

Table base in code(0) or RAM(1) ***************** Bit definition for SCB_AIRCR register

#define SCB_AIRCR_VECTRESET   ((uint32_t)0x00000001)

System Reset bit

#define SCB_AIRCR_VECTCLRACTIVE   ((uint32_t)0x00000002)

Clear active vector bit

#define SCB_AIRCR_SYSRESETREQ   ((uint32_t)0x00000004)

Requests chip control logic to generate a reset

#define SCB_AIRCR_PRIGROUP   ((uint32_t)0x00000700)

PRIGROUP[2:0] bits (Priority group)

#define SCB_AIRCR_PRIGROUP_0   ((uint32_t)0x00000100)

Bit 0

#define SCB_AIRCR_PRIGROUP_1   ((uint32_t)0x00000200)

Bit 1

#define SCB_AIRCR_PRIGROUP_2   ((uint32_t)0x00000400)

Bit 2

#define SCB_AIRCR_PRIGROUP0   ((uint32_t)0x00000000)

Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)

#define SCB_AIRCR_PRIGROUP1   ((uint32_t)0x00000100)

Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)

#define SCB_AIRCR_PRIGROUP2   ((uint32_t)0x00000200)

Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)

#define SCB_AIRCR_PRIGROUP3   ((uint32_t)0x00000300)

Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)

#define SCB_AIRCR_PRIGROUP4   ((uint32_t)0x00000400)

Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)

#define SCB_AIRCR_PRIGROUP5   ((uint32_t)0x00000500)

Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)

#define SCB_AIRCR_PRIGROUP6   ((uint32_t)0x00000600)

Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)

#define SCB_AIRCR_PRIGROUP7   ((uint32_t)0x00000700)

Priority group=7 (no pre-emption priority, 8 bits of subpriority)

#define SCB_AIRCR_ENDIANESS   ((uint32_t)0x00008000)

Data endianness bit

#define SCB_AIRCR_VECTKEY   ((uint32_t)0xFFFF0000)

Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)

#define SCB_SCR_SLEEPONEXIT   ((uint8_t)0x02)

Sleep on exit bit

#define SCB_SCR_SLEEPDEEP   ((uint8_t)0x04)

Sleep deep bit

#define SCB_SCR_SEVONPEND   ((uint8_t)0x10)

Wake up from WFE

#define SCB_CCR_NONBASETHRDENA   ((uint16_t)0x0001)

Thread mode can be entered from any level in Handler mode by controlled return value

#define SCB_CCR_USERSETMPEND   ((uint16_t)0x0002)

Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception

#define SCB_CCR_UNALIGN_TRP   ((uint16_t)0x0008)

Trap for unaligned access

#define SCB_CCR_DIV_0_TRP   ((uint16_t)0x0010)

Trap on Divide by 0

#define SCB_CCR_BFHFNMIGN   ((uint16_t)0x0100)

Handlers running at priority -1 and -2

#define SCB_CCR_STKALIGN   ((uint16_t)0x0200)

On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned

#define SCB_SHPR_PRI_N   ((uint32_t)0x000000FF)

Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor

#define SCB_SHPR_PRI_N1   ((uint32_t)0x0000FF00)

Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved

#define SCB_SHPR_PRI_N2   ((uint32_t)0x00FF0000)

Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV

#define SCB_SHPR_PRI_N3   ((uint32_t)0xFF000000)

Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick

#define SCB_SHCSR_MEMFAULTACT   ((uint32_t)0x00000001)

MemManage is active

#define SCB_SHCSR_BUSFAULTACT   ((uint32_t)0x00000002)

BusFault is active

#define SCB_SHCSR_USGFAULTACT   ((uint32_t)0x00000008)

UsageFault is active

#define SCB_SHCSR_SVCALLACT   ((uint32_t)0x00000080)

SVCall is active

#define SCB_SHCSR_MONITORACT   ((uint32_t)0x00000100)

Monitor is active

#define SCB_SHCSR_PENDSVACT   ((uint32_t)0x00000400)

PendSV is active

#define SCB_SHCSR_SYSTICKACT   ((uint32_t)0x00000800)

SysTick is active

#define SCB_SHCSR_USGFAULTPENDED   ((uint32_t)0x00001000)

Usage Fault is pended

#define SCB_SHCSR_MEMFAULTPENDED   ((uint32_t)0x00002000)

MemManage is pended

#define SCB_SHCSR_BUSFAULTPENDED   ((uint32_t)0x00004000)

Bus Fault is pended

#define SCB_SHCSR_SVCALLPENDED   ((uint32_t)0x00008000)

SVCall is pended

#define SCB_SHCSR_MEMFAULTENA   ((uint32_t)0x00010000)

MemManage enable

Referenced by CortexExceptHandler().

#define SCB_SHCSR_BUSFAULTENA   ((uint32_t)0x00020000)

Bus Fault enable

Referenced by CortexExceptHandler().

#define SCB_SHCSR_USGFAULTENA   ((uint32_t)0x00040000)

UsageFault enable

Referenced by CortexExceptHandler().

#define SCB_CFSR_IACCVIOL   ((uint32_t)0x00000001)

< MFSR Instruction access violation

#define SCB_CFSR_DACCVIOL   ((uint32_t)0x00000002)

Data access violation

#define SCB_CFSR_MUNSTKERR   ((uint32_t)0x00000008)

Unstacking error

#define SCB_CFSR_MSTKERR   ((uint32_t)0x00000010)

Stacking error

#define SCB_CFSR_MMARVALID   ((uint32_t)0x00000080)

Memory Manage Address Register address valid flag BFSR

#define SCB_CFSR_IBUSERR   ((uint32_t)0x00000100)

Instruction bus error flag

#define SCB_CFSR_PRECISERR   ((uint32_t)0x00000200)

Precise data bus error

#define SCB_CFSR_IMPRECISERR   ((uint32_t)0x00000400)

Imprecise data bus error

#define SCB_CFSR_UNSTKERR   ((uint32_t)0x00000800)

Unstacking error

#define SCB_CFSR_STKERR   ((uint32_t)0x00001000)

Stacking error

#define SCB_CFSR_BFARVALID   ((uint32_t)0x00008000)

Bus Fault Address Register address valid flag UFSR

#define SCB_CFSR_UNDEFINSTR   ((uint32_t)0x00010000)

The processor attempt to excecute an undefined instruction

#define SCB_CFSR_INVSTATE   ((uint32_t)0x00020000)

Invalid combination of EPSR and instruction

#define SCB_CFSR_INVPC   ((uint32_t)0x00040000)

Attempt to load EXC_RETURN into pc illegally

#define SCB_CFSR_NOCP   ((uint32_t)0x00080000)

Attempt to use a coprocessor instruction

#define SCB_CFSR_UNALIGNED   ((uint32_t)0x01000000)

Fault occurs when there is an attempt to make an unaligned memory access

#define SCB_CFSR_DIVBYZERO   ((uint32_t)0x02000000)

Fault occurs when SDIV or DIV instruction is used with a divisor of 0

#define SCB_HFSR_VECTTBL   ((uint32_t)0x00000002)

Fault occures because of vector table read on exception processing

#define SCB_HFSR_FORCED   ((uint32_t)0x40000000)

Hard Fault activated when a configurable Fault was received and cannot activate

#define SCB_HFSR_DEBUGEVT   ((uint32_t)0x80000000)

Fault related to debug

#define SCB_DFSR_HALTED   ((uint8_t)0x01)

Halt request flag

#define SCB_DFSR_BKPT   ((uint8_t)0x02)

BKPT flag

#define SCB_DFSR_DWTTRAP   ((uint8_t)0x04)

Data Watchpoint and Trace (DWT) flag

#define SCB_DFSR_VCATCH   ((uint8_t)0x08)

Vector catch flag

#define SCB_DFSR_EXTERNAL   ((uint8_t)0x10)

External debug request flag

#define SCB_MMFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)

Mem Manage fault address field

#define SCB_BFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)

Bus fault address field

#define SCB_AFSR_IMPDEF   ((uint32_t)0xFFFFFFFF)

Implementation defined

#define EXTI_IMR_MR0   ((uint32_t)0x00000001)

Interrupt Mask on line 0

#define EXTI_IMR_MR1   ((uint32_t)0x00000002)

Interrupt Mask on line 1

#define EXTI_IMR_MR2   ((uint32_t)0x00000004)

Interrupt Mask on line 2

#define EXTI_IMR_MR3   ((uint32_t)0x00000008)

Interrupt Mask on line 3

#define EXTI_IMR_MR4   ((uint32_t)0x00000010)

Interrupt Mask on line 4

#define EXTI_IMR_MR5   ((uint32_t)0x00000020)

Interrupt Mask on line 5

#define EXTI_IMR_MR6   ((uint32_t)0x00000040)

Interrupt Mask on line 6

#define EXTI_IMR_MR7   ((uint32_t)0x00000080)

Interrupt Mask on line 7

#define EXTI_IMR_MR8   ((uint32_t)0x00000100)

Interrupt Mask on line 8

#define EXTI_IMR_MR9   ((uint32_t)0x00000200)

Interrupt Mask on line 9

#define EXTI_IMR_MR10   ((uint32_t)0x00000400)

Interrupt Mask on line 10

#define EXTI_IMR_MR11   ((uint32_t)0x00000800)

Interrupt Mask on line 11

#define EXTI_IMR_MR12   ((uint32_t)0x00001000)

Interrupt Mask on line 12

#define EXTI_IMR_MR13   ((uint32_t)0x00002000)

Interrupt Mask on line 13

#define EXTI_IMR_MR14   ((uint32_t)0x00004000)

Interrupt Mask on line 14

#define EXTI_IMR_MR15   ((uint32_t)0x00008000)

Interrupt Mask on line 15

#define EXTI_IMR_MR16   ((uint32_t)0x00010000)

Interrupt Mask on line 16

#define EXTI_IMR_MR17   ((uint32_t)0x00020000)

Interrupt Mask on line 17

#define EXTI_IMR_MR18   ((uint32_t)0x00040000)

Interrupt Mask on line 18

#define EXTI_IMR_MR19   ((uint32_t)0x00080000)

Interrupt Mask on line 19

#define EXTI_EMR_MR0   ((uint32_t)0x00000001)

Event Mask on line 0

#define EXTI_EMR_MR1   ((uint32_t)0x00000002)

Event Mask on line 1

#define EXTI_EMR_MR2   ((uint32_t)0x00000004)

Event Mask on line 2

#define EXTI_EMR_MR3   ((uint32_t)0x00000008)

Event Mask on line 3

#define EXTI_EMR_MR4   ((uint32_t)0x00000010)

Event Mask on line 4

#define EXTI_EMR_MR5   ((uint32_t)0x00000020)

Event Mask on line 5

#define EXTI_EMR_MR6   ((uint32_t)0x00000040)

Event Mask on line 6

#define EXTI_EMR_MR7   ((uint32_t)0x00000080)

Event Mask on line 7

#define EXTI_EMR_MR8   ((uint32_t)0x00000100)

Event Mask on line 8

#define EXTI_EMR_MR9   ((uint32_t)0x00000200)

Event Mask on line 9

#define EXTI_EMR_MR10   ((uint32_t)0x00000400)

Event Mask on line 10

#define EXTI_EMR_MR11   ((uint32_t)0x00000800)

Event Mask on line 11

#define EXTI_EMR_MR12   ((uint32_t)0x00001000)

Event Mask on line 12

#define EXTI_EMR_MR13   ((uint32_t)0x00002000)

Event Mask on line 13

#define EXTI_EMR_MR14   ((uint32_t)0x00004000)

Event Mask on line 14

#define EXTI_EMR_MR15   ((uint32_t)0x00008000)

Event Mask on line 15

#define EXTI_EMR_MR16   ((uint32_t)0x00010000)

Event Mask on line 16

#define EXTI_EMR_MR17   ((uint32_t)0x00020000)

Event Mask on line 17

#define EXTI_EMR_MR18   ((uint32_t)0x00040000)

Event Mask on line 18

#define EXTI_EMR_MR19   ((uint32_t)0x00080000)

Event Mask on line 19

#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)

Software Interrupt on line 0

#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)

Software Interrupt on line 1

#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)

Software Interrupt on line 2

#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)

Software Interrupt on line 3

#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)

Software Interrupt on line 4

#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)

Software Interrupt on line 5

#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)

Software Interrupt on line 6

#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)

Software Interrupt on line 7

#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)

Software Interrupt on line 8

#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)

Software Interrupt on line 9

#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)

Software Interrupt on line 10

#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)

Software Interrupt on line 11

#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)

Software Interrupt on line 12

#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)

Software Interrupt on line 13

#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)

Software Interrupt on line 14

#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)

Software Interrupt on line 15

#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)

Software Interrupt on line 16

#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)

Software Interrupt on line 17

#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)

Software Interrupt on line 18

#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)

Software Interrupt on line 19

#define EXTI_PR_PR0   ((uint32_t)0x00000001)

Pending bit for line 0

#define EXTI_PR_PR1   ((uint32_t)0x00000002)

Pending bit for line 1

#define EXTI_PR_PR2   ((uint32_t)0x00000004)

Pending bit for line 2

#define EXTI_PR_PR3   ((uint32_t)0x00000008)

Pending bit for line 3

#define EXTI_PR_PR4   ((uint32_t)0x00000010)

Pending bit for line 4

#define EXTI_PR_PR5   ((uint32_t)0x00000020)

Pending bit for line 5

#define EXTI_PR_PR6   ((uint32_t)0x00000040)

Pending bit for line 6

#define EXTI_PR_PR7   ((uint32_t)0x00000080)

Pending bit for line 7

#define EXTI_PR_PR8   ((uint32_t)0x00000100)

Pending bit for line 8

#define EXTI_PR_PR9   ((uint32_t)0x00000200)

Pending bit for line 9

#define EXTI_PR_PR10   ((uint32_t)0x00000400)

Pending bit for line 10

#define EXTI_PR_PR11   ((uint32_t)0x00000800)

Pending bit for line 11

#define EXTI_PR_PR12   ((uint32_t)0x00001000)

Pending bit for line 12

#define EXTI_PR_PR13   ((uint32_t)0x00002000)

Pending bit for line 13

#define EXTI_PR_PR14   ((uint32_t)0x00004000)

Pending bit for line 14

#define EXTI_PR_PR15   ((uint32_t)0x00008000)

Pending bit for line 15

#define EXTI_PR_PR16   ((uint32_t)0x00010000)

Pending bit for line 16

#define EXTI_PR_PR17   ((uint32_t)0x00020000)

Pending bit for line 17

#define EXTI_PR_PR18   ((uint32_t)0x00040000)

Pending bit for line 18

#define EXTI_PR_PR19   ((uint32_t)0x00080000)

Pending bit for line 19

#define DMA_ISR_GIF1   ((uint32_t)0x00000001)

Channel 1 Global interrupt flag

#define DMA_ISR_TCIF1   ((uint32_t)0x00000002)

Channel 1 Transfer Complete flag

#define DMA_ISR_HTIF1   ((uint32_t)0x00000004)

Channel 1 Half Transfer flag

#define DMA_ISR_TEIF1   ((uint32_t)0x00000008)

Channel 1 Transfer Error flag

#define DMA_ISR_GIF2   ((uint32_t)0x00000010)

Channel 2 Global interrupt flag

#define DMA_ISR_TCIF2   ((uint32_t)0x00000020)

Channel 2 Transfer Complete flag

#define DMA_ISR_HTIF2   ((uint32_t)0x00000040)

Channel 2 Half Transfer flag

#define DMA_ISR_TEIF2   ((uint32_t)0x00000080)

Channel 2 Transfer Error flag

#define DMA_ISR_GIF3   ((uint32_t)0x00000100)

Channel 3 Global interrupt flag

#define DMA_ISR_TCIF3   ((uint32_t)0x00000200)

Channel 3 Transfer Complete flag

#define DMA_ISR_HTIF3   ((uint32_t)0x00000400)

Channel 3 Half Transfer flag

#define DMA_ISR_TEIF3   ((uint32_t)0x00000800)

Channel 3 Transfer Error flag

#define DMA_ISR_GIF4   ((uint32_t)0x00001000)

Channel 4 Global interrupt flag

#define DMA_ISR_TCIF4   ((uint32_t)0x00002000)

Channel 4 Transfer Complete flag

#define DMA_ISR_HTIF4   ((uint32_t)0x00004000)

Channel 4 Half Transfer flag

#define DMA_ISR_TEIF4   ((uint32_t)0x00008000)

Channel 4 Transfer Error flag

#define DMA_ISR_GIF5   ((uint32_t)0x00010000)

Channel 5 Global interrupt flag

#define DMA_ISR_TCIF5   ((uint32_t)0x00020000)

Channel 5 Transfer Complete flag

#define DMA_ISR_HTIF5   ((uint32_t)0x00040000)

Channel 5 Half Transfer flag

#define DMA_ISR_TEIF5   ((uint32_t)0x00080000)

Channel 5 Transfer Error flag

#define DMA_ISR_GIF6   ((uint32_t)0x00100000)

Channel 6 Global interrupt flag

#define DMA_ISR_TCIF6   ((uint32_t)0x00200000)

Channel 6 Transfer Complete flag

#define DMA_ISR_HTIF6   ((uint32_t)0x00400000)

Channel 6 Half Transfer flag

#define DMA_ISR_TEIF6   ((uint32_t)0x00800000)

Channel 6 Transfer Error flag

#define DMA_ISR_GIF7   ((uint32_t)0x01000000)

Channel 7 Global interrupt flag

#define DMA_ISR_TCIF7   ((uint32_t)0x02000000)

Channel 7 Transfer Complete flag

#define DMA_ISR_HTIF7   ((uint32_t)0x04000000)

Channel 7 Half Transfer flag

#define DMA_ISR_TEIF7   ((uint32_t)0x08000000)

Channel 7 Transfer Error flag

#define DMA_IFCR_CGIF1   ((uint32_t)0x00000001)

Channel 1 Global interrupt clearr

#define DMA_IFCR_CTCIF1   ((uint32_t)0x00000002)

Channel 1 Transfer Complete clear

#define DMA_IFCR_CHTIF1   ((uint32_t)0x00000004)

Channel 1 Half Transfer clear

#define DMA_IFCR_CTEIF1   ((uint32_t)0x00000008)

Channel 1 Transfer Error clear

#define DMA_IFCR_CGIF2   ((uint32_t)0x00000010)

Channel 2 Global interrupt clear

#define DMA_IFCR_CTCIF2   ((uint32_t)0x00000020)

Channel 2 Transfer Complete clear

#define DMA_IFCR_CHTIF2   ((uint32_t)0x00000040)

Channel 2 Half Transfer clear

#define DMA_IFCR_CTEIF2   ((uint32_t)0x00000080)

Channel 2 Transfer Error clear

#define DMA_IFCR_CGIF3   ((uint32_t)0x00000100)

Channel 3 Global interrupt clear

#define DMA_IFCR_CTCIF3   ((uint32_t)0x00000200)

Channel 3 Transfer Complete clear

#define DMA_IFCR_CHTIF3   ((uint32_t)0x00000400)

Channel 3 Half Transfer clear

#define DMA_IFCR_CTEIF3   ((uint32_t)0x00000800)

Channel 3 Transfer Error clear

#define DMA_IFCR_CGIF4   ((uint32_t)0x00001000)

Channel 4 Global interrupt clear

#define DMA_IFCR_CTCIF4   ((uint32_t)0x00002000)

Channel 4 Transfer Complete clear

#define DMA_IFCR_CHTIF4   ((uint32_t)0x00004000)

Channel 4 Half Transfer clear

#define DMA_IFCR_CTEIF4   ((uint32_t)0x00008000)

Channel 4 Transfer Error clear

#define DMA_IFCR_CGIF5   ((uint32_t)0x00010000)

Channel 5 Global interrupt clear

#define DMA_IFCR_CTCIF5   ((uint32_t)0x00020000)

Channel 5 Transfer Complete clear

#define DMA_IFCR_CHTIF5   ((uint32_t)0x00040000)

Channel 5 Half Transfer clear

#define DMA_IFCR_CTEIF5   ((uint32_t)0x00080000)

Channel 5 Transfer Error clear

#define DMA_IFCR_CGIF6   ((uint32_t)0x00100000)

Channel 6 Global interrupt clear

#define DMA_IFCR_CTCIF6   ((uint32_t)0x00200000)

Channel 6 Transfer Complete clear

#define DMA_IFCR_CHTIF6   ((uint32_t)0x00400000)

Channel 6 Half Transfer clear

#define DMA_IFCR_CTEIF6   ((uint32_t)0x00800000)

Channel 6 Transfer Error clear

#define DMA_IFCR_CGIF7   ((uint32_t)0x01000000)

Channel 7 Global interrupt clear

#define DMA_IFCR_CTCIF7   ((uint32_t)0x02000000)

Channel 7 Transfer Complete clear

#define DMA_IFCR_CHTIF7   ((uint32_t)0x04000000)

Channel 7 Half Transfer clear

#define DMA_IFCR_CTEIF7   ((uint32_t)0x08000000)

Channel 7 Transfer Error clear

#define DMA_CCR1_EN   ((uint16_t)0x0001)

Channel enable

Referenced by DMA_Disable(), DMA_Enable(), and DMA_Setup().

#define DMA_CCR1_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR1_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR1_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR1_DIR   ((uint16_t)0x0010)

Data transfer direction

Referenced by DMA_Setup().

#define DMA_CCR1_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR1_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR1_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR1_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR1_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR1_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR1_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR1_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR1_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR1_PL   ((uint16_t)0x3000)

PL[1:0] bits(Channel Priority level)

#define DMA_CCR1_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR1_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR1_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

Referenced by DMA_Setup().

#define DMA_CCR2_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR2_TCIE   ((uint16_t)0x0002)

ransfer complete interrupt enable

#define DMA_CCR2_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR2_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR2_DIR   ((uint16_t)0x0010)

Data transfer direction

Referenced by DMA_Setup().

#define DMA_CCR2_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR2_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR2_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR2_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR2_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR2_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR2_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR2_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR2_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR2_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR2_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR2_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR2_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR3_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR3_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR3_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR3_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR3_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR3_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR3_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR3_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR3_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR3_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR3_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR3_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR3_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR3_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR3_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR3_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR3_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR3_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode ****************** Bit definition for DMA_CCR4 register

#define DMA_CCR4_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR4_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR4_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR4_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR4_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR4_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR4_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR4_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR4_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR4_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR4_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR4_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR4_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR4_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR4_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR4_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR4_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR4_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR5_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR5_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR5_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR5_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR5_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR5_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR5_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR5_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR5_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR5_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR5_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR5_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR5_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR5_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR5_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR5_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR5_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR5_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode enable

#define DMA_CCR6_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR6_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR6_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR6_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR6_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR6_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR6_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR6_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR6_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR6_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR6_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR6_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR6_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR6_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR6_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR6_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR6_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR6_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR7_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR7_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR7_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR7_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR7_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR7_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR7_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR7_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR7_PSIZE   , ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR7_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR7_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR7_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR7_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR7_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR7_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR7_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR7_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR7_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode enable

#define DMA_CNDTR1_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR2_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR3_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR4_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR5_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR6_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR7_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CPAR1_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR2_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR3_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR4_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR5_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR6_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR7_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CMAR1_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR2_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR3_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR4_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR5_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR6_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR7_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define ADC_SR_AWD   ((uint8_t)0x01)

Analog watchdog flag

#define ADC_SR_EOC   ((uint8_t)0x02)

End of conversion

#define ADC_SR_JEOC   ((uint8_t)0x04)

Injected channel end of conversion

#define ADC_SR_JSTRT   ((uint8_t)0x08)

Injected channel Start flag

#define ADC_SR_STRT   ((uint8_t)0x10)

Regular channel Start flag

#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)

Interrupt enable for EOC

#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)

AAnalog Watchdog interrupt enable

#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)

Interrupt enable for injected channels

#define ADC_CR1_SCAN   ((uint32_t)0x00000100)

Scan mode

#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)

Automatic injected group conversion

#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)

Discontinuous mode on regular channels

#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)

Discontinuous mode on injected channels

#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)

Bit 0

#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)

Bit 1

#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)

Bit 2

#define ADC_CR1_DUALMOD   ((uint32_t)0x000F0000)

DUALMOD[3:0] bits (Dual mode selection)

#define ADC_CR1_DUALMOD_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CR1_DUALMOD_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CR1_DUALMOD_2   ((uint32_t)0x00040000)

Bit 2

#define ADC_CR1_DUALMOD_3   ((uint32_t)0x00080000)

Bit 3

#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

#define ADC_CR2_ADON   ((uint32_t)0x00000001)

A/D Converter ON / OFF

#define ADC_CR2_CONT   ((uint32_t)0x00000002)

Continuous Conversion

#define ADC_CR2_CAL   ((uint32_t)0x00000004)

A/D Calibration

#define ADC_CR2_RSTCAL   ((uint32_t)0x00000008)

Reset Calibration

#define ADC_CR2_DMA   ((uint32_t)0x00000100)

Direct Memory access mode

#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)

Data Alignment

#define ADC_CR2_JEXTSEL   ((uint32_t)0x00007000)

JEXTSEL[2:0] bits (External event select for injected group)

#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_CR2_JEXTTRIG   ((uint32_t)0x00008000)

External Trigger Conversion mode for injected channels

#define ADC_CR2_EXTSEL   ((uint32_t)0x000E0000)

EXTSEL[2:0] bits (External Event Select for regular group)

#define ADC_CR2_EXTSEL_0   ((uint32_t)0x00020000)

Bit 0

#define ADC_CR2_EXTSEL_1   ((uint32_t)0x00040000)

Bit 1

#define ADC_CR2_EXTSEL_2   ((uint32_t)0x00080000)

Bit 2

#define ADC_CR2_EXTTRIG   ((uint32_t)0x00100000)

External Trigger Conversion mode for regular channels

#define ADC_CR2_JSWSTART   ((uint32_t)0x00200000)

Start Conversion of injected channels

#define ADC_CR2_SWSTART   ((uint32_t)0x00400000)

Start Conversion of regular channels

#define ADC_CR2_TSVREFE   ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)

Data offset for injected channel 1

#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)

Data offset for injected channel 2

#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)

Data offset for injected channel 3

#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)

Data offset for injected channel 4

#define ADC_HTR_HT   ((uint16_t)0x0FFF)

Analog watchdog high threshold

#define ADC_LTR_LT   ((uint16_t)0x0FFF)

Analog watchdog low threshold

#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR1_L   ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

#define ADC_SQR1_L_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR1_L_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR1_L_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR1_L_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_JSQR_JL   ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)

Regular data

#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)

ADC2 data

#define DAC_CR_EN1   ((uint32_t)0x00000001)

DAC channel1 enable

#define DAC_CR_BOFF1   ((uint32_t)0x00000002)

DAC channel1 output buffer disable

#define DAC_CR_TEN1   ((uint32_t)0x00000004)

DAC channel1 Trigger enable

#define DAC_CR_TSEL1   ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)

Bit 0

#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)

Bit 1

#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)

Bit 2

#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)

Bit 0

#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)

Bit 1

#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)

Bit 0

#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)

Bit 1

#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)

Bit 2

#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)

Bit 3

#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)

DAC channel1 DMA enable

#define DAC_CR_EN2   ((uint32_t)0x00010000)

DAC channel2 enable

#define DAC_CR_BOFF2   ((uint32_t)0x00020000)

DAC channel2 output buffer disable

#define DAC_CR_TEN2   ((uint32_t)0x00040000)

DAC channel2 Trigger enable

#define DAC_CR_TSEL2   ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)

Bit 0

#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)

Bit 1

#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)

Bit 2

#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)

Bit 0

#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)

Bit 1

#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)

Bit 0

#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)

Bit 1

#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)

Bit 2

#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)

Bit 3

#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)

DAC channel2 DMA enabled

#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)

DAC channel1 software trigger

#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)

DAC channel2 software trigger

#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)

DAC channel1 data output

#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)

DAC channel2 data output

#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

#define CEC_CFGR_PE   ((uint16_t)0x0001)

Peripheral Enable

#define CEC_CFGR_IE   ((uint16_t)0x0002)

Interrupt Enable

#define CEC_CFGR_BTEM   ((uint16_t)0x0004)

Bit Timing Error Mode

#define CEC_CFGR_BPEM   ((uint16_t)0x0008)

Bit Period Error Mode

#define CEC_OAR_OA   ((uint16_t)0x000F)

OA[3:0]: Own Address

#define CEC_OAR_OA_0   ((uint16_t)0x0001)

Bit 0

#define CEC_OAR_OA_1   ((uint16_t)0x0002)

Bit 1

#define CEC_OAR_OA_2   ((uint16_t)0x0004)

Bit 2

#define CEC_OAR_OA_3   ((uint16_t)0x0008)

Bit 3

#define CEC_PRES_PRES   ((uint16_t)0x3FFF)

Prescaler Counter Value

#define CEC_ESR_BTE   ((uint16_t)0x0001)

Bit Timing Error

#define CEC_ESR_BPE   ((uint16_t)0x0002)

Bit Period Error

#define CEC_ESR_RBTFE   ((uint16_t)0x0004)

Rx Block Transfer Finished Error

#define CEC_ESR_SBE   ((uint16_t)0x0008)

Start Bit Error

#define CEC_ESR_ACKE   ((uint16_t)0x0010)

Block Acknowledge Error

#define CEC_ESR_LINE   ((uint16_t)0x0020)

Line Error

#define CEC_ESR_TBTFE   ((uint16_t)0x0040)

Tx Block Transfer Finsihed Error

#define CEC_CSR_TSOM   ((uint16_t)0x0001)

Tx Start Of Message

#define CEC_CSR_TEOM   ((uint16_t)0x0002)

Tx End Of Message

#define CEC_CSR_TERR   ((uint16_t)0x0004)

Tx Error

#define CEC_CSR_TBTRF   ((uint16_t)0x0008)

Tx Byte Transfer Request or Block Transfer Finished

#define CEC_CSR_RSOM   ((uint16_t)0x0010)

Rx Start Of Message

#define CEC_CSR_REOM   ((uint16_t)0x0020)

Rx End Of Message

#define CEC_CSR_RERR   ((uint16_t)0x0040)

Rx Error

#define CEC_CSR_RBTF   ((uint16_t)0x0080)

Rx Block Transfer Finished

#define CEC_TXD_TXD   ((uint16_t)0x00FF)

Tx Data register

#define CEC_RXD_RXD   ((uint16_t)0x00FF)

Rx Data register

#define TIM_CR1_CEN   ((uint16_t)0x0001)

Counter enable

Referenced by TIM_Cmd().

#define TIM_CR1_UDIS   ((uint16_t)0x0002)

Update disable

Referenced by TIM_UpdateDisableConfig().

#define TIM_CR1_URS   ((uint16_t)0x0004)

Update request source

Referenced by TIM_UpdateRequestConfig().

#define TIM_CR1_OPM   ((uint16_t)0x0008)

One pulse mode

Referenced by TIM_SelectOnePulseMode().

#define TIM_CR1_DIR   ((uint16_t)0x0010)

Direction

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_CMS   ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

Referenced by TIM_CounterModeConfig(), and TIM_TimeBaseInit().

#define TIM_CR1_CMS_0   ((uint16_t)0x0020)

Bit 0

#define TIM_CR1_CMS_1   ((uint16_t)0x0040)

Bit 1

#define TIM_CR1_ARPE   ((uint16_t)0x0080)

Auto-reload preload enable

Referenced by TIM_ARRPreloadConfig().

#define TIM_CR1_CKD   ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

Referenced by TIM_SetClockDivision(), and TIM_TimeBaseInit().

#define TIM_CR1_CKD_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CR1_CKD_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CR2_CCPC   ((uint16_t)0x0001)

Capture/Compare Preloaded Control

Referenced by TIM_CCPreloadControl().

#define TIM_CR2_CCUS   ((uint16_t)0x0004)

Capture/Compare Control Update Selection

Referenced by TIM_SelectCOM().

#define TIM_CR2_CCDS   ((uint16_t)0x0008)

Capture/Compare DMA Selection

Referenced by TIM_SelectCCDMA().

#define TIM_CR2_MMS   ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

Referenced by TIM_SelectOutputTrigger().

#define TIM_CR2_MMS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CR2_MMS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CR2_MMS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CR2_TI1S   ((uint16_t)0x0080)

TI1 Selection

Referenced by TIM_SelectHallSensor().

#define TIM_CR2_OIS1   ((uint16_t)0x0100)

Output Idle state 1 (OC1 output)

Referenced by TIM_OC1Init().

#define TIM_CR2_OIS1N   ((uint16_t)0x0200)

Output Idle state 1 (OC1N output)

Referenced by TIM_OC1Init().

#define TIM_CR2_OIS2   ((uint16_t)0x0400)

Output Idle state 2 (OC2 output)

Referenced by TIM_OC2Init().

#define TIM_CR2_OIS2N   ((uint16_t)0x0800)

Output Idle state 2 (OC2N output)

Referenced by TIM_OC2Init().

#define TIM_CR2_OIS3   ((uint16_t)0x1000)

Output Idle state 3 (OC3 output)

Referenced by TIM_OC3Init().

#define TIM_CR2_OIS3N   ((uint16_t)0x2000)

Output Idle state 3 (OC3N output)

Referenced by TIM_OC3Init().

#define TIM_CR2_OIS4   ((uint16_t)0x4000)

Output Idle state 4 (OC4 output)

Referenced by TIM_OC4Init().

#define TIM_SMCR_SMS   ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

Referenced by TIM_EncoderInterfaceConfig(), TIM_ETRClockMode1Config(), TIM_InternalClockConfig(), and TIM_SelectSlaveMode().

#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)

Bit 0

#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)

Bit 1

#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)

Bit 2

#define TIM_SMCR_TS   ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

Referenced by TIM_ETRClockMode1Config(), and TIM_SelectInputTrigger().

#define TIM_SMCR_TS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_SMCR_TS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_SMCR_TS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_SMCR_MSM   ((uint16_t)0x0080)

Master/slave mode

Referenced by TIM_SelectMasterSlaveMode().

#define TIM_SMCR_ETF   ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)

Bit 0

#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)

Bit 1

#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)

Bit 2

#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)

Bit 3

#define TIM_SMCR_ETPS   ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)

Bit 0

#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)

Bit 1

#define TIM_SMCR_ECE   ((uint16_t)0x4000)

External clock enable

Referenced by TIM_ETRClockMode2Config().

#define TIM_SMCR_ETP   ((uint16_t)0x8000)

External trigger polarity

#define TIM_DIER_UIE   ((uint16_t)0x0001)

Update interrupt enable

#define TIM_DIER_CC1IE   ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

#define TIM_DIER_CC2IE   ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

#define TIM_DIER_CC3IE   ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

#define TIM_DIER_CC4IE   ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

#define TIM_DIER_COMIE   ((uint16_t)0x0020)

COM interrupt enable

#define TIM_DIER_TIE   ((uint16_t)0x0040)

Trigger interrupt enable

#define TIM_DIER_BIE   ((uint16_t)0x0080)

Break interrupt enable

#define TIM_DIER_UDE   ((uint16_t)0x0100)

Update DMA request enable

#define TIM_DIER_CC1DE   ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

#define TIM_DIER_CC2DE   ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

#define TIM_DIER_CC3DE   ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

#define TIM_DIER_CC4DE   ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

#define TIM_DIER_COMDE   ((uint16_t)0x2000)

COM DMA request enable

#define TIM_DIER_TDE   ((uint16_t)0x4000)

Trigger DMA request enable

#define TIM_SR_UIF   ((uint16_t)0x0001)

Update interrupt Flag

#define TIM_SR_CC1IF   ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

#define TIM_SR_CC2IF   ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

#define TIM_SR_CC3IF   ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

#define TIM_SR_CC4IF   ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

#define TIM_SR_COMIF   ((uint16_t)0x0020)

COM interrupt Flag

#define TIM_SR_TIF   ((uint16_t)0x0040)

Trigger interrupt Flag

#define TIM_SR_BIF   ((uint16_t)0x0080)

Break interrupt Flag

#define TIM_SR_CC1OF   ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

#define TIM_SR_CC2OF   ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

#define TIM_SR_CC3OF   ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

#define TIM_SR_CC4OF   ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

#define TIM_EGR_UG   ((uint8_t)0x01)

Update Generation

#define TIM_EGR_CC1G   ((uint8_t)0x02)

Capture/Compare 1 Generation

#define TIM_EGR_CC2G   ((uint8_t)0x04)

Capture/Compare 2 Generation

#define TIM_EGR_CC3G   ((uint8_t)0x08)

Capture/Compare 3 Generation

#define TIM_EGR_CC4G   ((uint8_t)0x10)

Capture/Compare 4 Generation

#define TIM_EGR_COMG   ((uint8_t)0x20)

Capture/Compare Control Update Generation

#define TIM_EGR_TG   ((uint8_t)0x40)

Trigger Generation

#define TIM_EGR_BG   ((uint8_t)0x80)

Break Generation

#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

Referenced by TIM_EncoderInterfaceConfig(), and TIM_OC1Init().

#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)

Bit 0

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)

Output Compare 1 Fast enable

Referenced by TIM_OC1FastConfig().

#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)

Output Compare 1 Preload enable

Referenced by TIM_OC1PreloadConfig().

#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

Referenced by TIM_ForcedOC1Config(), TIM_OC1Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)

Output Compare 1Clear Enable

Referenced by TIM_ClearOC1Ref().

#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

Referenced by TIM_EncoderInterfaceConfig(), and TIM_OC2Init().

#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)

Bit 0

Referenced by TIM_EncoderInterfaceConfig().

#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)

Output Compare 2 Fast enable

Referenced by TIM_OC2FastConfig().

#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)

Output Compare 2 Preload enable

Referenced by TIM_OC2PreloadConfig().

#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

Referenced by TIM_ForcedOC2Config(), TIM_OC2Init(), and TIM_SelectOCxM().

#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)

Output Compare 2 Clear Enable

Referenced by TIM_ClearOC2Ref().

#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

Referenced by TIM_SetIC1Prescaler().

#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

Referenced by TIM_SetIC2Prescaler().

#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

Referenced by TIM_OC3Init().

#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)

Output Compare 3 Fast enable

Referenced by TIM_OC3FastConfig().

#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)

Output Compare 3 Preload enable

Referenced by TIM_OC3PreloadConfig().

#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

Referenced by TIM_ForcedOC3Config(), and TIM_OC3Init().

#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)

Output Compare 3 Clear Enable

Referenced by TIM_ClearOC3Ref().

#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

Referenced by TIM_OC4Init().

#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)

Output Compare 4 Fast enable

Referenced by TIM_OC4FastConfig().

#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)

Output Compare 4 Preload enable

Referenced by TIM_OC4PreloadConfig().

#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

Referenced by TIM_ForcedOC4Config(), and TIM_OC4Init().

#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)

Output Compare 4 Clear Enable

Referenced by TIM_ClearOC4Ref().

#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

Referenced by TIM_SetIC3Prescaler().

#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

Referenced by TIM_SetIC4Prescaler().

#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCER_CC1E   ((uint16_t)0x0001)

Capture/Compare 1 output enable

Referenced by TIM_OC1Init().

#define TIM_CCER_CC1P   ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

Referenced by TIM_EncoderInterfaceConfig(), TIM_OC1Init(), and TIM_OC1PolarityConfig().

#define TIM_CCER_CC1NE   ((uint16_t)0x0004)

Capture/Compare 1 Complementary output enable

Referenced by TIM_OC1Init().

#define TIM_CCER_CC1NP   ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

Referenced by TIM_OC1Init(), and TIM_OC1NPolarityConfig().

#define TIM_CCER_CC2E   ((uint16_t)0x0010)

Capture/Compare 2 output enable

Referenced by TIM_OC2Init().

#define TIM_CCER_CC2P   ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

Referenced by TIM_EncoderInterfaceConfig(), TIM_OC2Init(), and TIM_OC2PolarityConfig().

#define TIM_CCER_CC2NE   ((uint16_t)0x0040)

Capture/Compare 2 Complementary output enable

Referenced by TIM_OC2Init().

#define TIM_CCER_CC2NP   ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

Referenced by TIM_OC2Init(), and TIM_OC2NPolarityConfig().

#define TIM_CCER_CC3E   ((uint16_t)0x0100)

Capture/Compare 3 output enable

Referenced by TIM_OC3Init().

#define TIM_CCER_CC3P   ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

Referenced by TIM_OC3Init(), and TIM_OC3PolarityConfig().

#define TIM_CCER_CC3NE   ((uint16_t)0x0400)

Capture/Compare 3 Complementary output enable

Referenced by TIM_OC3Init().

#define TIM_CCER_CC3NP   ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

Referenced by TIM_OC3Init(), and TIM_OC3NPolarityConfig().

#define TIM_CCER_CC4E   ((uint16_t)0x1000)

Capture/Compare 4 output enable

Referenced by TIM_OC4Init().

#define TIM_CCER_CC4P   ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

Referenced by TIM_OC4Init(), and TIM_OC4PolarityConfig().

#define TIM_CNT_CNT   ((uint16_t)0xFFFF)

Counter Value

#define TIM_PSC_PSC   ((uint16_t)0xFFFF)

Prescaler Value

#define TIM_ARR_ARR   ((uint16_t)0xFFFF)

actual auto-reload Value

#define TIM_RCR_REP   ((uint8_t)0xFF)

Repetition Counter Value

#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)

Capture/Compare 1 Value

#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)

Capture/Compare 2 Value

#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)

Capture/Compare 3 Value

#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)

Capture/Compare 4 Value

#define TIM_BDTR_DTG   ((uint16_t)0x00FF)

DTG[0:7] bits (Dead-Time Generator set-up)

#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)

Bit 0

#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)

Bit 1

#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)

Bit 2

#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)

Bit 3

#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)

Bit 4

#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)

Bit 5

#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)

Bit 6

#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)

Bit 7

#define TIM_BDTR_LOCK   ((uint16_t)0x0300)

LOCK[1:0] bits (Lock Configuration)

#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)

Bit 0

#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)

Bit 1

#define TIM_BDTR_OSSI   ((uint16_t)0x0400)

Off-State Selection for Idle mode

#define TIM_BDTR_OSSR   ((uint16_t)0x0800)

Off-State Selection for Run mode

#define TIM_BDTR_BKE   ((uint16_t)0x1000)

Break enable

#define TIM_BDTR_BKP   ((uint16_t)0x2000)

Break Polarity

#define TIM_BDTR_AOE   ((uint16_t)0x4000)

Automatic Output enable

#define TIM_BDTR_MOE   ((uint16_t)0x8000)

Main Output enable

Referenced by TIM_CtrlPWMOutputs().

#define TIM_DCR_DBA   ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

#define TIM_DCR_DBA_0   ((uint16_t)0x0001)

Bit 0

#define TIM_DCR_DBA_1   ((uint16_t)0x0002)

Bit 1

#define TIM_DCR_DBA_2   ((uint16_t)0x0004)

Bit 2

#define TIM_DCR_DBA_3   ((uint16_t)0x0008)

Bit 3

#define TIM_DCR_DBA_4   ((uint16_t)0x0010)

Bit 4

#define TIM_DCR_DBL   ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

#define TIM_DCR_DBL_0   ((uint16_t)0x0100)

Bit 0

#define TIM_DCR_DBL_1   ((uint16_t)0x0200)

Bit 1

#define TIM_DCR_DBL_2   ((uint16_t)0x0400)

Bit 2

#define TIM_DCR_DBL_3   ((uint16_t)0x0800)

Bit 3

#define TIM_DCR_DBL_4   ((uint16_t)0x1000)

Bit 4

#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)

DMA register for burst accesses

#define RTC_CRH_SECIE   ((uint8_t)0x01)

Second Interrupt Enable

#define RTC_CRH_ALRIE   ((uint8_t)0x02)

Alarm Interrupt Enable

#define RTC_CRH_OWIE   ((uint8_t)0x04)

OverfloW Interrupt Enable

#define RTC_CRL_SECF   ((uint8_t)0x01)

Second Flag

#define RTC_CRL_ALRF   ((uint8_t)0x02)

Alarm Flag

#define RTC_CRL_OWF   ((uint8_t)0x04)

OverfloW Flag

#define RTC_CRL_RSF   ((uint8_t)0x08)

Registers Synchronized Flag

#define RTC_CRL_CNF   ((uint8_t)0x10)

Configuration Flag

#define RTC_CRL_RTOFF   ((uint8_t)0x20)

RTC operation OFF

#define RTC_PRLH_PRL   ((uint16_t)0x000F)

RTC Prescaler Reload Value High

#define RTC_PRLL_PRL   ((uint16_t)0xFFFF)

RTC Prescaler Reload Value Low

#define RTC_DIVH_RTC_DIV   ((uint16_t)0x000F)

RTC Clock Divider High

#define RTC_DIVL_RTC_DIV   ((uint16_t)0xFFFF)

RTC Clock Divider Low

#define RTC_CNTH_RTC_CNT   ((uint16_t)0xFFFF)

RTC Counter High

#define RTC_CNTL_RTC_CNT   ((uint16_t)0xFFFF)

RTC Counter Low

#define RTC_ALRH_RTC_ALR   ((uint16_t)0xFFFF)

RTC Alarm High

#define RTC_ALRL_RTC_ALR   ((uint16_t)0xFFFF)

RTC Alarm Low

#define IWDG_KR_KEY   ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

#define IWDG_PR_PR   ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

#define IWDG_PR_PR_0   ((uint8_t)0x01)

Bit 0

#define IWDG_PR_PR_1   ((uint8_t)0x02)

Bit 1

#define IWDG_PR_PR_2   ((uint8_t)0x04)

Bit 2

#define IWDG_RLR_RL   ((uint16_t)0x0FFF)

Watchdog counter reload value

#define IWDG_SR_PVU   ((uint8_t)0x01)

Watchdog prescaler value update

#define IWDG_SR_RVU   ((uint8_t)0x02)

Watchdog counter reload value update

#define WWDG_CR_T   ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

#define WWDG_CR_T0   ((uint8_t)0x01)

Bit 0

#define WWDG_CR_T1   ((uint8_t)0x02)

Bit 1

#define WWDG_CR_T2   ((uint8_t)0x04)

Bit 2

#define WWDG_CR_T3   ((uint8_t)0x08)

Bit 3

#define WWDG_CR_T4   ((uint8_t)0x10)

Bit 4

#define WWDG_CR_T5   ((uint8_t)0x20)

Bit 5

#define WWDG_CR_T6   ((uint8_t)0x40)

Bit 6

#define WWDG_CR_WDGA   ((uint8_t)0x80)

Activation bit

#define WWDG_CFR_W   ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

#define WWDG_CFR_W0   ((uint16_t)0x0001)

Bit 0

#define WWDG_CFR_W1   ((uint16_t)0x0002)

Bit 1

#define WWDG_CFR_W2   ((uint16_t)0x0004)

Bit 2

#define WWDG_CFR_W3   ((uint16_t)0x0008)

Bit 3

#define WWDG_CFR_W4   ((uint16_t)0x0010)

Bit 4

#define WWDG_CFR_W5   ((uint16_t)0x0020)

Bit 5

#define WWDG_CFR_W6   ((uint16_t)0x0040)

Bit 6

#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)

Bit 0

#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)

Bit 1

#define WWDG_CFR_EWI   ((uint16_t)0x0200)

Early Wakeup Interrupt

#define WWDG_SR_EWIF   ((uint8_t)0x01)

Early Wakeup Interrupt Flag

#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit.

#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)

ECCPS[1:0] bits (ECC page size)

#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_SR2_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR2_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR2_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR2_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR2_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR2_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR2_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR3_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR3_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR3_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR3_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR3_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR3_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR3_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR4_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR4_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR4_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR4_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR4_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR4_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR4_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)

MEMSET2[7:0] bits (Common memory 2 setup time)

#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)

MEMWAIT2[7:0] bits (Common memory 2 wait time)

#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)

MEMHOLD2[7:0] bits (Common memory 2 hold time)

#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)

MEMSET3[7:0] bits (Common memory 3 setup time)

#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)

MEMWAIT3[7:0] bits (Common memory 3 wait time)

#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)

MEMHOLD3[7:0] bits (Common memory 3 hold time)

#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)

MEMSET4[7:0] bits (Common memory 4 setup time)

#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)

MEMWAIT4[7:0] bits (Common memory 4 wait time)

#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)

MEMHOLD4[7:0] bits (Common memory 4 hold time)

#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)

ATTSET2[7:0] bits (Attribute memory 2 setup time)

#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)

ATTSET3[7:0] bits (Attribute memory 3 setup time)

#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)

ATTSET4[7:0] bits (Attribute memory 4 setup time)

#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)

IOSET4[7:0] bits (I/O 4 setup time)

#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)

IOWAIT4[7:0] bits (I/O 4 wait time)

#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)

IOHOLD4[7:0] bits (I/O 4 hold time)

#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)

ECC result

#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)

ECC result

#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)

Bit 0

#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)

Bit 1

#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)

Clock divide factor

#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)

Clock enable bit

#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)

Power saving configuration bit

#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)

Clock divider bypass enable bit

#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)

Bit 0

#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)

Bit 1

#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)

HW Flow Control enable

#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)

Command argument

#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)

Command Index

#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)

Bit 0

#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)

Bit 1

#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)

SD I/O suspend command

#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)

Enable CMD completion

#define SDIO_CMD_NIEN   ((uint16_t)0x2000)

Not Interrupt Enable

#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)

CE-ATA command

#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)

Response command index

#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)

Data timeout period.

#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)

Data length value

#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)

Data transfer enabled bit

#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)

Data transfer direction selection

#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)

Data transfer mode selection

#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)

DMA enabled bit

#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)

Bit 0

#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)

Bit 1

#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)

Bit 2

#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)

Bit 3

#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)

Read wait start

#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)

Read wait stop

#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)

Read wait mode

#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)

SD I/O enable functions

#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)

Data count value

#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)

Command response received (CRC check failed)

#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)

Command response timeout

#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)

Data timeout

#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)

Transmit FIFO underrun error

#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)

Received FIFO overrun error

#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)

Command response received (CRC check passed)

#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)

Command sent (no response required)

#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)

Command transfer in progress

#define SDIO_STA_TXACT   ((uint32_t)0x00001000)

Data transmit in progress

#define SDIO_STA_RXACT   ((uint32_t)0x00002000)

Data receive in progress

#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)

Transmit FIFO full

#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)

Receive FIFO full

#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)

Transmit FIFO empty

#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)

Receive FIFO empty

#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)

Data available in transmit FIFO

#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)

Data available in receive FIFO

#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)

SDIO interrupt received

#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)

TXUNDERR flag clear bit

#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)

RXOVERR flag clear bit

#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)

CMDREND flag clear bit

#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)

CMDSENT flag clear bit

#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)

DATAEND flag clear bit

#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)

STBITERR flag clear bit

#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)

DBCKEND flag clear bit

#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)

SDIOIT flag clear bit

#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)

CEATAEND flag clear bit

#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)

Command Sent Interrupt Enable

#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)

Data End Interrupt Enable

#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)

Data Block End Interrupt Enable

#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)

CCommand Acting Interrupt Enable

#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)

Data receive acting interrupt enabled

#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

#define USB_EP0R_EA   ((uint16_t)0x000F)

<Endpoint-specific registers Endpoint Address

#define USB_EP0R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP0R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP0R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP0R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP0R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP0R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP0R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP0R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP0R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP0R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP0R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP0R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP0R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP0R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP0R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP1R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP1R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP1R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP1R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP1R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP1R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP1R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP1R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP1R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP1R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP1R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP1R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP1R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP1R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP1R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP1R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP2R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP2R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP2R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP2R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP2R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP2R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP2R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP2R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP2R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP2R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP2R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP2R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP2R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP2R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP2R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP2R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP3R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP3R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP3R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP3R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP3R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP3R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP3R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP3R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP3R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP3R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP3R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP3R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP3R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP3R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP3R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP3R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP4R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP4R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP4R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP4R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP4R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP4R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP4R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP4R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP4R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP4R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP4R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP4R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP4R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP4R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP4R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP4R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP5R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP5R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP5R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP5R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP5R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP5R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP5R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP5R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP5R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP5R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP5R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP5R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP5R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP5R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP5R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP5R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP6R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP6R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP6R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP6R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP6R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP6R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP6R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP6R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP6R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP6R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP6R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP6R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP6R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP6R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP6R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP6R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP7R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP7R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP7R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP7R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP7R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP7R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP7R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP7R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP7R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP7R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP7R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP7R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP7R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP7R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP7R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP7R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception Common registers

#define USB_CNTR_FRES   ((uint16_t)0x0001)

Force USB Reset

#define USB_CNTR_PDWN   ((uint16_t)0x0002)

Power down

#define USB_CNTR_LP_MODE   ((uint16_t)0x0004)

Low-power mode

#define USB_CNTR_FSUSP   ((uint16_t)0x0008)

Force suspend

#define USB_CNTR_RESUME   ((uint16_t)0x0010)

Resume request

#define USB_CNTR_ESOFM   ((uint16_t)0x0100)

Expected Start Of Frame Interrupt Mask

#define USB_CNTR_SOFM   ((uint16_t)0x0200)

Start Of Frame Interrupt Mask

#define USB_CNTR_RESETM   ((uint16_t)0x0400)

RESET Interrupt Mask

#define USB_CNTR_SUSPM   ((uint16_t)0x0800)

Suspend mode Interrupt Mask

#define USB_CNTR_WKUPM   ((uint16_t)0x1000)

Wakeup Interrupt Mask

#define USB_CNTR_ERRM   ((uint16_t)0x2000)

Error Interrupt Mask

#define USB_CNTR_PMAOVRM   ((uint16_t)0x4000)

Packet Memory Area Over / Underrun Interrupt Mask

#define USB_CNTR_CTRM   ((uint16_t)0x8000)

Correct Transfer Interrupt Mask

#define USB_ISTR_EP_ID   ((uint16_t)0x000F)

Endpoint Identifier

#define USB_ISTR_DIR   ((uint16_t)0x0010)

Direction of transaction

#define USB_ISTR_ESOF   ((uint16_t)0x0100)

Expected Start Of Frame

#define USB_ISTR_SOF   ((uint16_t)0x0200)

Start Of Frame

#define USB_ISTR_RESET   ((uint16_t)0x0400)

USB RESET request

#define USB_ISTR_SUSP   ((uint16_t)0x0800)

Suspend mode request

#define USB_ISTR_WKUP   ((uint16_t)0x1000)

Wake up

#define USB_ISTR_ERR   ((uint16_t)0x2000)

Error

#define USB_ISTR_PMAOVR   ((uint16_t)0x4000)

Packet Memory Area Over / Underrun

#define USB_ISTR_CTR   ((uint16_t)0x8000)

Correct Transfer

#define USB_FNR_FN   ((uint16_t)0x07FF)

Frame Number

#define USB_FNR_LSOF   ((uint16_t)0x1800)

Lost SOF

#define USB_FNR_LCK   ((uint16_t)0x2000)

Locked

#define USB_FNR_RXDM   ((uint16_t)0x4000)

Receive Data - Line Status

#define USB_FNR_RXDP   ((uint16_t)0x8000)

Receive Data + Line Status

#define USB_DADDR_ADD   ((uint8_t)0x7F)

ADD[6:0] bits (Device Address)

#define USB_DADDR_ADD0   ((uint8_t)0x01)

Bit 0

#define USB_DADDR_ADD1   ((uint8_t)0x02)

Bit 1

#define USB_DADDR_ADD2   ((uint8_t)0x04)

Bit 2

#define USB_DADDR_ADD3   ((uint8_t)0x08)

Bit 3

#define USB_DADDR_ADD4   ((uint8_t)0x10)

Bit 4

#define USB_DADDR_ADD5   ((uint8_t)0x20)

Bit 5

#define USB_DADDR_ADD6   ((uint8_t)0x40)

Bit 6

#define USB_DADDR_EF   ((uint8_t)0x80)

Enable Function

#define USB_BTABLE_BTABLE   ((uint16_t)0xFFF8)

Buffer Table Buffer descriptor table

#define USB_ADDR0_TX_ADDR0_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 0

#define USB_ADDR1_TX_ADDR1_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 1

#define USB_ADDR2_TX_ADDR2_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 2

#define USB_ADDR3_TX_ADDR3_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 3

#define USB_ADDR4_TX_ADDR4_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 4

#define USB_ADDR5_TX_ADDR5_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 5

#define USB_ADDR6_TX_ADDR6_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 6

#define USB_ADDR7_TX_ADDR7_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 7

#define USB_COUNT0_TX_COUNT0_TX   ((uint16_t)0x03FF)

Transmission Byte Count 0

#define USB_COUNT1_TX_COUNT1_TX   ((uint16_t)0x03FF)

Transmission Byte Count 1

#define USB_COUNT2_TX_COUNT2_TX   ((uint16_t)0x03FF)

Transmission Byte Count 2

#define USB_COUNT3_TX_COUNT3_TX   ((uint16_t)0x03FF)

Transmission Byte Count 3

#define USB_COUNT4_TX_COUNT4_TX   ((uint16_t)0x03FF)

Transmission Byte Count 4

#define USB_COUNT5_TX_COUNT5_TX   ((uint16_t)0x03FF)

Transmission Byte Count 5

#define USB_COUNT6_TX_COUNT6_TX   ((uint16_t)0x03FF)

Transmission Byte Count 6

#define USB_COUNT7_TX_COUNT7_TX   ((uint16_t)0x03FF)

Transmission Byte Count 7

#define USB_COUNT0_TX_0_COUNT0_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 0 (low)

#define USB_COUNT0_TX_1_COUNT0_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 0 (high)

#define USB_COUNT1_TX_0_COUNT1_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 1 (low)

#define USB_COUNT1_TX_1_COUNT1_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 1 (high)

#define USB_COUNT2_TX_0_COUNT2_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 2 (low)

#define USB_COUNT2_TX_1_COUNT2_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 2 (high)

#define USB_COUNT3_TX_0_COUNT3_TX_0   ((uint16_t)0x000003FF)

Transmission Byte Count 3 (low)

#define USB_COUNT3_TX_1_COUNT3_TX_1   ((uint16_t)0x03FF0000)

Transmission Byte Count 3 (high)

#define USB_COUNT4_TX_0_COUNT4_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 4 (low)

#define USB_COUNT4_TX_1_COUNT4_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 4 (high)

#define USB_COUNT5_TX_0_COUNT5_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 5 (low)

#define USB_COUNT5_TX_1_COUNT5_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 5 (high)

#define USB_COUNT6_TX_0_COUNT6_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 6 (low)

#define USB_COUNT6_TX_1_COUNT6_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 6 (high)

#define USB_COUNT7_TX_0_COUNT7_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 7 (low)

#define USB_COUNT7_TX_1_COUNT7_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 7 (high)

#define USB_ADDR0_RX_ADDR0_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 0

#define USB_ADDR1_RX_ADDR1_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 1

#define USB_ADDR2_RX_ADDR2_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 2

#define USB_ADDR3_RX_ADDR3_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 3

#define USB_ADDR4_RX_ADDR4_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 4

#define USB_ADDR5_RX_ADDR5_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 5

#define USB_ADDR6_RX_ADDR6_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 6

#define USB_ADDR7_RX_ADDR7_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 7

#define USB_COUNT0_RX_COUNT0_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT0_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT0_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT0_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT0_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT0_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT0_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT0_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT1_RX_COUNT1_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT1_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT1_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT1_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT1_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT1_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT1_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT1_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT2_RX_COUNT2_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT2_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT2_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT2_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT2_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT2_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT2_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT2_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT3_RX_COUNT3_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT3_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT3_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT3_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT3_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT3_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT3_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT3_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT4_RX_COUNT4_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT4_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT4_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT4_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT4_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT4_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT4_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT4_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT5_RX_COUNT5_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT5_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT5_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT5_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT5_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT5_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT5_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT5_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT6_RX_COUNT6_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT6_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT6_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT6_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT6_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT6_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT6_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT6_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT7_RX_COUNT7_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT7_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT7_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT7_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT7_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT7_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT7_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT7_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT0_RX_0_COUNT0_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT0_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT0_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT0_RX_1_COUNT0_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT0_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT0_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT1_RX_0_COUNT1_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT1_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT1_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT1_RX_1_COUNT1_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT1_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT1_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT2_RX_0_COUNT2_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT2_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT2_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT2_RX_1_COUNT2_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT2_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT2_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT3_RX_0_COUNT3_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT3_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT3_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT3_RX_1_COUNT3_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT3_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT3_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT4_RX_0_COUNT4_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT4_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT4_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT4_RX_1_COUNT4_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT4_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT4_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT5_RX_0_COUNT5_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT5_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT5_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT5_RX_1_COUNT5_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT5_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT5_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT6_RX_0_COUNT6_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT6_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT6_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT6_RX_1_COUNT6_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT6_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT6_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT7_RX_0_COUNT7_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT7_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT7_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT7_RX_1_COUNT7_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT7_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT7_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define CAN_MCR_INRQ   ((uint16_t)0x0001)

<CAN control and status registers Initialization Request

#define CAN_MCR_SLEEP   ((uint16_t)0x0002)

Sleep Mode Request

#define CAN_MCR_TXFP   ((uint16_t)0x0004)

Transmit FIFO Priority

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_RFLM   ((uint16_t)0x0008)

Receive FIFO Locked Mode

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_NART   ((uint16_t)0x0010)

No Automatic Retransmission

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_AWUM   ((uint16_t)0x0020)

Automatic Wakeup Mode

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_ABOM   ((uint16_t)0x0040)

Automatic Bus-Off Management

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_TTCM   ((uint16_t)0x0080)

Time Triggered Communication Mode

Referenced by CanGetFeatures(), and CanSetFeatures().

#define CAN_MCR_RESET   ((uint16_t)0x8000)

bxCAN software master reset

#define CAN_MSR_INAK   ((uint16_t)0x0001)

Initialization Acknowledge

#define CAN_MSR_SLAK   ((uint16_t)0x0002)

Sleep Acknowledge

#define CAN_MSR_ERRI   ((uint16_t)0x0004)

Error Interrupt

#define CAN_MSR_WKUI   ((uint16_t)0x0008)

Wakeup Interrupt

#define CAN_MSR_SLAKI   ((uint16_t)0x0010)

Sleep Acknowledge Interrupt

#define CAN_MSR_TXM   ((uint16_t)0x0100)

Transmit Mode

#define CAN_MSR_RXM   ((uint16_t)0x0200)

Receive Mode

#define CAN_MSR_SAMP   ((uint16_t)0x0400)

Last Sample Point

#define CAN_MSR_RX   ((uint16_t)0x0800)

CAN Rx Signal

#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)

Request Completed Mailbox0

#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)

Transmission OK of Mailbox0

#define CAN_TSR_ALST0   ((uint32_t)0x00000004)

Arbitration Lost for Mailbox0

#define CAN_TSR_TERR0   ((uint32_t)0x00000008)

Transmission Error of Mailbox0

#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)

Abort Request for Mailbox0

#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)

Request Completed Mailbox1

#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)

Transmission OK of Mailbox1

#define CAN_TSR_ALST1   ((uint32_t)0x00000400)

Arbitration Lost for Mailbox1

#define CAN_TSR_TERR1   ((uint32_t)0x00000800)

Transmission Error of Mailbox1

#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)

Abort Request for Mailbox 1

#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)

Request Completed Mailbox2

#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)

Transmission OK of Mailbox 2

#define CAN_TSR_ALST2   ((uint32_t)0x00040000)

Arbitration Lost for mailbox 2

#define CAN_TSR_TERR2   ((uint32_t)0x00080000)

Transmission Error of Mailbox 2

#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)

Abort Request for Mailbox 2

#define CAN_TSR_CODE   ((uint32_t)0x03000000)

Mailbox Code

#define CAN_TSR_TME   ((uint32_t)0x1C000000)

TME[2:0] bits

#define CAN_TSR_TME0   ((uint32_t)0x04000000)

Transmit Mailbox 0 Empty

#define CAN_TSR_TME1   ((uint32_t)0x08000000)

Transmit Mailbox 1 Empty

#define CAN_TSR_TME2   ((uint32_t)0x10000000)

Transmit Mailbox 2 Empty

#define CAN_TSR_LOW   ((uint32_t)0xE0000000)

LOW[2:0] bits

#define CAN_TSR_LOW0   ((uint32_t)0x20000000)

Lowest Priority Flag for Mailbox 0

#define CAN_TSR_LOW1   ((uint32_t)0x40000000)

Lowest Priority Flag for Mailbox 1

#define CAN_TSR_LOW2   ((uint32_t)0x80000000)

Lowest Priority Flag for Mailbox 2

#define CAN_RF0R_FMP0   ((uint8_t)0x03)

FIFO 0 Message Pending

#define CAN_RF0R_FULL0   ((uint8_t)0x08)

FIFO 0 Full

#define CAN_RF0R_FOVR0   ((uint8_t)0x10)

FIFO 0 Overrun

#define CAN_RF0R_RFOM0   ((uint8_t)0x20)

Release FIFO 0 Output Mailbox

#define CAN_RF1R_FMP1   ((uint8_t)0x03)

FIFO 1 Message Pending

#define CAN_RF1R_FULL1   ((uint8_t)0x08)

FIFO 1 Full

#define CAN_RF1R_FOVR1   ((uint8_t)0x10)

FIFO 1 Overrun

#define CAN_RF1R_RFOM1   ((uint8_t)0x20)

Release FIFO 1 Output Mailbox

#define CAN_IER_TMEIE   ((uint32_t)0x00000001)

Transmit Mailbox Empty Interrupt Enable

#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)

FIFO Message Pending Interrupt Enable

Referenced by CanEnableRx(), and CanInput().

#define CAN_IER_FFIE0   ((uint32_t)0x00000004)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)

FIFO Overrun Interrupt Enable

#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)

FIFO Message Pending Interrupt Enable

Referenced by CanEnableRx(), and CanInput().

#define CAN_IER_FFIE1   ((uint32_t)0x00000020)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)

FIFO Overrun Interrupt Enable

#define CAN_IER_EWGIE   ((uint32_t)0x00000100)

Error Warning Interrupt Enable

#define CAN_IER_EPVIE   ((uint32_t)0x00000200)

Error Passive Interrupt Enable

#define CAN_IER_BOFIE   ((uint32_t)0x00000400)

Bus-Off Interrupt Enable

#define CAN_IER_LECIE   ((uint32_t)0x00000800)

Last Error Code Interrupt Enable

#define CAN_IER_ERRIE   ((uint32_t)0x00008000)

Error Interrupt Enable

#define CAN_IER_WKUIE   ((uint32_t)0x00010000)

Wakeup Interrupt Enable

#define CAN_IER_SLKIE   ((uint32_t)0x00020000)

Sleep Interrupt Enable

#define CAN_ESR_EWGF   ((uint32_t)0x00000001)

Error Warning Flag

#define CAN_ESR_EPVF   ((uint32_t)0x00000002)

Error Passive Flag

#define CAN_ESR_BOFF   ((uint32_t)0x00000004)

Bus-Off Flag

#define CAN_ESR_LEC   ((uint32_t)0x00000070)

LEC[2:0] bits (Last Error Code)

#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)

Bit 0

#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)

Bit 1

#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)

Bit 2

#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)

Least significant byte of the 9-bit Transmit Error Counter

#define CAN_ESR_REC   ((uint32_t)0xFF000000)

Receive Error Counter

#define CAN_BTR_BRP   ((uint32_t)0x000003FF)

Baud Rate Prescaler

#define CAN_BTR_TS1   ((uint32_t)0x000F0000)

Time Segment 1

#define CAN_BTR_TS2   ((uint32_t)0x00700000)

Time Segment 2

#define CAN_BTR_SJW   ((uint32_t)0x03000000)

Resynchronization Jump Width

#define CAN_BTR_LBKM   ((uint32_t)0x40000000)

Loop Back Mode (Debug)

#define CAN_BTR_SILM   ((uint32_t)0x80000000)

Silent Mode Mailbox registers

#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI2R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI2R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

Referenced by CanInput().

#define CAN_RI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

Referenced by CanInput().

#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_RI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7 CAN filter registers

#define CAN_FMR_FINIT   ((uint8_t)0x01)

Filter Init Mode

Referenced by CanEnableRx().

#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)

Filter Mode

#define CAN_FM1R_FBM0   ((uint16_t)0x0001)

Filter Init Mode bit 0

#define CAN_FM1R_FBM1   ((uint16_t)0x0002)

Filter Init Mode bit 1

#define CAN_FM1R_FBM2   ((uint16_t)0x0004)

Filter Init Mode bit 2

#define CAN_FM1R_FBM3   ((uint16_t)0x0008)

Filter Init Mode bit 3

#define CAN_FM1R_FBM4   ((uint16_t)0x0010)

Filter Init Mode bit 4

#define CAN_FM1R_FBM5   ((uint16_t)0x0020)

Filter Init Mode bit 5

#define CAN_FM1R_FBM6   ((uint16_t)0x0040)

Filter Init Mode bit 6

#define CAN_FM1R_FBM7   ((uint16_t)0x0080)

Filter Init Mode bit 7

#define CAN_FM1R_FBM8   ((uint16_t)0x0100)

Filter Init Mode bit 8

#define CAN_FM1R_FBM9   ((uint16_t)0x0200)

Filter Init Mode bit 9

#define CAN_FM1R_FBM10   ((uint16_t)0x0400)

Filter Init Mode bit 10

#define CAN_FM1R_FBM11   ((uint16_t)0x0800)

Filter Init Mode bit 11

#define CAN_FM1R_FBM12   ((uint16_t)0x1000)

Filter Init Mode bit 12

#define CAN_FM1R_FBM13   ((uint16_t)0x2000)

Filter Init Mode bit 13

#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)

Filter Scale Configuration

#define CAN_FS1R_FSC0   ((uint16_t)0x0001)

Filter Scale Configuration bit 0

#define CAN_FS1R_FSC1   ((uint16_t)0x0002)

Filter Scale Configuration bit 1

#define CAN_FS1R_FSC2   ((uint16_t)0x0004)

Filter Scale Configuration bit 2

#define CAN_FS1R_FSC3   ((uint16_t)0x0008)

Filter Scale Configuration bit 3

#define CAN_FS1R_FSC4   ((uint16_t)0x0010)

Filter Scale Configuration bit 4

#define CAN_FS1R_FSC5   ((uint16_t)0x0020)

Filter Scale Configuration bit 5

#define CAN_FS1R_FSC6   ((uint16_t)0x0040)

Filter Scale Configuration bit 6

#define CAN_FS1R_FSC7   ((uint16_t)0x0080)

Filter Scale Configuration bit 7

#define CAN_FS1R_FSC8   ((uint16_t)0x0100)

Filter Scale Configuration bit 8

#define CAN_FS1R_FSC9   ((uint16_t)0x0200)

Filter Scale Configuration bit 9

#define CAN_FS1R_FSC10   ((uint16_t)0x0400)

Filter Scale Configuration bit 10

#define CAN_FS1R_FSC11   ((uint16_t)0x0800)

Filter Scale Configuration bit 11

#define CAN_FS1R_FSC12   ((uint16_t)0x1000)

Filter Scale Configuration bit 12

#define CAN_FS1R_FSC13   ((uint16_t)0x2000)

Filter Scale Configuration bit 13

#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)

Filter FIFO Assignment

#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)

Filter FIFO Assignment for Filter 0

#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)

Filter FIFO Assignment for Filter 1

#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)

Filter FIFO Assignment for Filter 2

#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)

Filter FIFO Assignment for Filter 3

#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)

Filter FIFO Assignment for Filter 4

#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)

Filter FIFO Assignment for Filter 5

#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)

Filter FIFO Assignment for Filter 6

#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)

Filter FIFO Assignment for Filter 7

#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)

Filter FIFO Assignment for Filter 8

#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)

Filter FIFO Assignment for Filter 9

#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)

Filter FIFO Assignment for Filter 10

#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)

Filter FIFO Assignment for Filter 11

#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)

Filter FIFO Assignment for Filter 12

#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)

Filter FIFO Assignment for Filter 13

#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)

Filter Active

#define CAN_FA1R_FACT0   ((uint16_t)0x0001)

Filter 0 Active

#define CAN_FA1R_FACT1   ((uint16_t)0x0002)

Filter 1 Active

#define CAN_FA1R_FACT2   ((uint16_t)0x0004)

Filter 2 Active

#define CAN_FA1R_FACT3   ((uint16_t)0x0008)

Filter 3 Active

#define CAN_FA1R_FACT4   ((uint16_t)0x0010)

Filter 4 Active

#define CAN_FA1R_FACT5   ((uint16_t)0x0020)

Filter 5 Active

#define CAN_FA1R_FACT6   ((uint16_t)0x0040)

Filter 6 Active

#define CAN_FA1R_FACT7   ((uint16_t)0x0080)

Filter 7 Active

#define CAN_FA1R_FACT8   ((uint16_t)0x0100)

Filter 8 Active

#define CAN_FA1R_FACT9   ((uint16_t)0x0200)

Filter 9 Active

#define CAN_FA1R_FACT10   ((uint16_t)0x0400)

Filter 10 Active

#define CAN_FA1R_FACT11   ((uint16_t)0x0800)

Filter 11 Active

#define CAN_FA1R_FACT12   ((uint16_t)0x1000)

Filter 12 Active

#define CAN_FA1R_FACT13   ((uint16_t)0x2000)

Filter 13 Active

#define CAN_F0R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F0R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define SPI_CR1_CPHA   ((uint16_t)0x0001)

Clock Phase

#define SPI_CR1_CPOL   ((uint16_t)0x0002)

Clock Polarity

#define SPI_CR1_MSTR   ((uint16_t)0x0004)

Master Selection

#define SPI_CR1_BR   ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

#define SPI_CR1_BR_0   ((uint16_t)0x0008)

Bit 0

#define SPI_CR1_BR_1   ((uint16_t)0x0010)

Bit 1

#define SPI_CR1_BR_2   ((uint16_t)0x0020)

Bit 2

#define SPI_CR1_SPE   ((uint16_t)0x0040)

SPI Enable

#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)

Frame Format

#define SPI_CR1_SSI   ((uint16_t)0x0100)

Internal slave select

#define SPI_CR1_SSM   ((uint16_t)0x0200)

Software slave management

#define SPI_CR1_RXONLY   ((uint16_t)0x0400)

Receive only

#define SPI_CR1_DFF   ((uint16_t)0x0800)

Data Frame Format

#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)

Transmit CRC next

#define SPI_CR1_CRCEN   ((uint16_t)0x2000)

Hardware CRC calculation enable

#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)

Output enable in bidirectional mode

#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)

Bidirectional data mode enable

#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)

Rx Buffer DMA Enable

#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)

Tx Buffer DMA Enable

#define SPI_CR2_SSOE   ((uint8_t)0x04)

SS Output Enable

#define SPI_CR2_ERRIE   ((uint8_t)0x20)

Error Interrupt Enable

#define SPI_CR2_RXNEIE   ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

#define SPI_CR2_TXEIE   ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

#define SPI_SR_RXNE   ((uint8_t)0x01)

Receive buffer Not Empty

#define SPI_SR_TXE   ((uint8_t)0x02)

Transmit buffer Empty

#define SPI_SR_CHSIDE   ((uint8_t)0x04)

Channel side

#define SPI_SR_UDR   ((uint8_t)0x08)

Underrun flag

#define SPI_SR_CRCERR   ((uint8_t)0x10)

CRC Error flag

#define SPI_SR_MODF   ((uint8_t)0x20)

Mode fault

#define SPI_SR_OVR   ((uint8_t)0x40)

Overrun flag

#define SPI_SR_BSY   ((uint8_t)0x80)

Busy flag

#define SPI_DR_DR   ((uint16_t)0xFFFF)

Data Register

#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)

CRC polynomial register

#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)

Rx CRC Register

#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)

Tx CRC Register

#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)

Bit 0

#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)

Bit 1

#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)

steady state clock polarity

#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)

Bit 0

#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)

Bit 1

#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)

PCM frame synchronization

#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)

Bit 0

#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)

Bit 1

#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)

I2S Enable

#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)

I2S mode selection

#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)

I2S Linear prescaler

#define SPI_I2SPR_ODD   ((uint16_t)0x0100)

Odd factor for the prescaler

#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)

Master Clock Output Enable

#define I2C_CR1_PE   ((uint16_t)0x0001)

Peripheral Enable

Referenced by NutRegisterTwiBus(), NutTwiSetSpeed(), and NutTwiStartRolling().

#define I2C_CR1_SMBUS   ((uint16_t)0x0002)

SMBus Mode

Referenced by NutRegisterTwiBus().

#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)

SMBus Type

Referenced by NutRegisterTwiBus().

#define I2C_CR1_ENARP   ((uint16_t)0x0010)

ARP Enable

#define I2C_CR1_ENPEC   ((uint16_t)0x0020)

PEC Enable

#define I2C_CR1_ENGC   ((uint16_t)0x0040)

General Call Enable

#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

#define I2C_CR1_START   ((uint16_t)0x0100)

Start Generation

Referenced by NutTwiStartRolling().

#define I2C_CR1_STOP   ((uint16_t)0x0200)

Stop Generation

#define I2C_CR1_ACK   ((uint16_t)0x0400)

Acknowledge Enable

Referenced by NutRegisterTwiBus(), and NutTwiStartRolling().

#define I2C_CR1_POS   ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

#define I2C_CR1_PEC   ((uint16_t)0x1000)

Packet Error Checking

Referenced by NutRegisterTwiBus().

#define I2C_CR1_ALERT   ((uint16_t)0x2000)

SMBus Alert

#define I2C_CR1_SWRST   ((uint16_t)0x8000)

Software Reset

Referenced by NutRegisterTwiBus(), and NutTwiSoftReset().

#define I2C_CR2_FREQ   ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

Referenced by NutRegisterTwiBus().

#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)

Bit 0

#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)

Bit 1

#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)

Bit 2

#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)

Bit 3

#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)

Bit 4

#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)

Bit 5

#define I2C_CR2_ITERREN   ((uint16_t)0x0100)

Error Interrupt Enable

Referenced by NutRegisterTwiBus(), and NutTwiStartRolling().

#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)

Event Interrupt Enable

Referenced by NutRegisterTwiBus(), and NutTwiStartRolling().

#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)

Buffer Interrupt Enable

Referenced by NutRegisterTwiBus(), and NutTwiStartRolling().

#define I2C_CR2_DMAEN   ((uint16_t)0x0800)

DMA Requests Enable

Referenced by I2C_DMA_Disable(), and I2C_DMA_Enable().

#define I2C_CR2_LAST   ((uint16_t)0x1000)

DMA Last Transfer

#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)

Interface Address

#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)

Interface Address

#define I2C_OAR1_ADD0   ((uint16_t)0x0001)

Bit 0

#define I2C_OAR1_ADD1   ((uint16_t)0x0002)

Bit 1

#define I2C_OAR1_ADD2   ((uint16_t)0x0004)

Bit 2

#define I2C_OAR1_ADD3   ((uint16_t)0x0008)

Bit 3

#define I2C_OAR1_ADD4   ((uint16_t)0x0010)

Bit 4

#define I2C_OAR1_ADD5   ((uint16_t)0x0020)

Bit 5

#define I2C_OAR1_ADD6   ((uint16_t)0x0040)

Bit 6

#define I2C_OAR1_ADD7   ((uint16_t)0x0080)

Bit 7

#define I2C_OAR1_ADD8   ((uint16_t)0x0100)

Bit 8

#define I2C_OAR1_ADD9   ((uint16_t)0x0200)

Bit 9

#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)

Addressing Mode (Slave mode)

#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)

Dual addressing mode enable

#define I2C_OAR2_ADD2   ((uint8_t)0xFE)

Interface address

#define I2C_DR_DR   ((uint8_t)0xFF)

8-bit Data Register

#define I2C_SR1_SB   ((uint16_t)0x0001)

Start Bit (Master mode)

#define I2C_SR1_ADDR   ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

#define I2C_SR1_BTF   ((uint16_t)0x0004)

Byte Transfer Finished

#define I2C_SR1_ADD10   ((uint16_t)0x0008)

10-bit header sent (Master mode)

#define I2C_SR1_STOPF   ((uint16_t)0x0010)

Stop detection (Slave mode)

#define I2C_SR1_RXNE   ((uint16_t)0x0040)

Data Register not Empty (receivers)

#define I2C_SR1_TXE   ((uint16_t)0x0080)

Data Register Empty (transmitters)

#define I2C_SR1_BERR   ((uint16_t)0x0100)

Bus Error

Referenced by TwErrorIrq().

#define I2C_SR1_ARLO   ((uint16_t)0x0200)

Arbitration Lost (master mode)

Referenced by TwErrorIrq().

#define I2C_SR1_AF   ((uint16_t)0x0400)

Acknowledge Failure

Referenced by TwErrorIrq().

#define I2C_SR1_OVR   ((uint16_t)0x0800)

Overrun/Underrun

Referenced by TwErrorIrq().

#define I2C_SR1_PECERR   ((uint16_t)0x1000)

PEC Error in reception

#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)

Timeout or Tlow Error

Referenced by TwErrorIrq().

#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)

SMBus Alert

#define I2C_SR2_MSL   ((uint16_t)0x0001)

Master/Slave

#define I2C_SR2_BUSY   ((uint16_t)0x0002)

Bus Busy

Referenced by I2C_Is_Busy().

#define I2C_SR2_TRA   ((uint16_t)0x0004)

Transmitter/Receiver

#define I2C_SR2_GENCALL   ((uint16_t)0x0010)

General Call Address (Slave mode)

#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

#define I2C_SR2_DUALF   ((uint16_t)0x0080)

Dual Flag (Slave mode)

#define I2C_SR2_PEC   ((uint16_t)0xFF00)

Packet Error Checking Register

#define I2C_CCR_CCR   ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

Referenced by NutTwiGetSpeed(), and NutTwiSetSpeed().

#define I2C_CCR_DUTY   ((uint16_t)0x4000)

Fast Mode Duty Cycle

Referenced by NutTwiSetSpeed().

#define I2C_CCR_FS   ((uint16_t)0x8000)

I2C Master Mode Selection

Referenced by NutTwiGetSpeed(), and NutTwiSetSpeed().

#define I2C_TRISE_TRISE   ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

#define USART_SR_PE   ((uint16_t)0x0001)

Parity Error

#define USART_SR_FE   ((uint16_t)0x0002)

Framing Error

#define USART_SR_NE   ((uint16_t)0x0004)

Noise Error Flag

#define USART_SR_ORE   ((uint16_t)0x0008)

OverRun Error

#define USART_SR_IDLE   ((uint16_t)0x0010)

IDLE line detected

#define USART_SR_RXNE   ((uint16_t)0x0020)

Read Data Register Not Empty

#define USART_SR_TC   ((uint16_t)0x0040)

Transmission Complete

#define USART_SR_TXE   ((uint16_t)0x0080)

Transmit Data Register Empty

#define USART_SR_LBD   ((uint16_t)0x0100)

LIN Break Detection Flag

#define USART_SR_CTS   ((uint16_t)0x0200)

CTS Flag

#define USART_DR_DR   ((uint16_t)0x01FF)

Data value

#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)

Fraction of USARTDIV

#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)

Mantissa of USARTDIV

#define USART_CR1_SBK   ((uint16_t)0x0001)

Send Break

#define USART_CR1_RWU   ((uint16_t)0x0002)

Receiver wakeup

#define USART_CR1_RE   ((uint16_t)0x0004)

Receiver Enable

#define USART_CR1_TE   ((uint16_t)0x0008)

Transmitter Enable

#define USART_CR1_IDLEIE   ((uint16_t)0x0010)

IDLE Interrupt Enable

#define USART_CR1_RXNEIE   ((uint16_t)0x0020)

RXNE Interrupt Enable

#define USART_CR1_TCIE   ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

#define USART_CR1_TXEIE   ((uint16_t)0x0080)

TX Interrupt Enable

#define USART_CR1_PEIE   ((uint16_t)0x0100)

PE Interrupt Enable

#define USART_CR1_PS   ((uint16_t)0x0200)

Parity Selection

#define USART_CR1_PCE   ((uint16_t)0x0400)

Parity Control Enable

#define USART_CR1_WAKE   ((uint16_t)0x0800)

Wakeup method

#define USART_CR1_M   ((uint16_t)0x1000)

Word length

#define USART_CR1_UE   ((uint16_t)0x2000)

USART Enable

#define USART_CR1_OVER8   ((uint16_t)0x8000)

USART Oversmapling 8-bits

#define USART_CR2_ADD   ((uint16_t)0x000F)

Address of the USART node

#define USART_CR2_LBDL   ((uint16_t)0x0020)

LIN Break Detection Length

#define USART_CR2_LBDIE   ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

#define USART_CR2_LBCL   ((uint16_t)0x0100)

Last Bit Clock pulse

#define USART_CR2_CPHA   ((uint16_t)0x0200)

Clock Phase

#define USART_CR2_CPOL   ((uint16_t)0x0400)

Clock Polarity

#define USART_CR2_CLKEN   ((uint16_t)0x0800)

Clock Enable

#define USART_CR2_STOP   ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

Referenced by Stm32UsartSetStopBits().

#define USART_CR2_STOP_0   ((uint16_t)0x1000)

Bit 0

#define USART_CR2_STOP_1   ((uint16_t)0x2000)

Bit 1

Referenced by Stm32UsartSetStopBits().

#define USART_CR2_LINEN   ((uint16_t)0x4000)

LIN mode enable

#define USART_CR3_EIE   ((uint16_t)0x0001)

Error Interrupt Enable

#define USART_CR3_IREN   ((uint16_t)0x0002)

IrDA mode Enable

#define USART_CR3_IRLP   ((uint16_t)0x0004)

IrDA Low-Power

#define USART_CR3_HDSEL   ((uint16_t)0x0008)

Half-Duplex Selection

#define USART_CR3_NACK   ((uint16_t)0x0010)

Smartcard NACK enable

#define USART_CR3_SCEN   ((uint16_t)0x0020)

Smartcard mode enable

#define USART_CR3_DMAR   ((uint16_t)0x0040)

DMA Enable Receiver

#define USART_CR3_DMAT   ((uint16_t)0x0080)

DMA Enable Transmitter

#define USART_CR3_RTSE   ((uint16_t)0x0100)

RTS Enable

#define USART_CR3_CTSE   ((uint16_t)0x0200)

CTS Enable

#define USART_CR3_CTSIE   ((uint16_t)0x0400)

CTS Interrupt Enable

#define USART_CR3_ONEBIT   ((uint16_t)0x0800)

One Bit method

#define USART_GTPR_PSC   ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

#define USART_GTPR_PSC_0   ((uint16_t)0x0001)

Bit 0

#define USART_GTPR_PSC_1   ((uint16_t)0x0002)

Bit 1

#define USART_GTPR_PSC_2   ((uint16_t)0x0004)

Bit 2

#define USART_GTPR_PSC_3   ((uint16_t)0x0008)

Bit 3

#define USART_GTPR_PSC_4   ((uint16_t)0x0010)

Bit 4

#define USART_GTPR_PSC_5   ((uint16_t)0x0020)

Bit 5

#define USART_GTPR_PSC_6   ((uint16_t)0x0040)

Bit 6

#define USART_GTPR_PSC_7   ((uint16_t)0x0080)

Bit 7

#define USART_GTPR_GT   ((uint16_t)0xFF00)

Guard time value

#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)

Device Identifier

#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)

REV_ID[15:0] bits (Revision Identifier)

#define DBGMCU_IDCODE_REV_ID_0   ((uint32_t)0x00010000)

Bit 0

#define DBGMCU_IDCODE_REV_ID_1   ((uint32_t)0x00020000)

Bit 1

#define DBGMCU_IDCODE_REV_ID_2   ((uint32_t)0x00040000)

Bit 2

#define DBGMCU_IDCODE_REV_ID_3   ((uint32_t)0x00080000)

Bit 3

#define DBGMCU_IDCODE_REV_ID_4   ((uint32_t)0x00100000)

Bit 4

#define DBGMCU_IDCODE_REV_ID_5   ((uint32_t)0x00200000)

Bit 5

#define DBGMCU_IDCODE_REV_ID_6   ((uint32_t)0x00400000)

Bit 6

#define DBGMCU_IDCODE_REV_ID_7   ((uint32_t)0x00800000)

Bit 7

#define DBGMCU_IDCODE_REV_ID_8   ((uint32_t)0x01000000)

Bit 8

#define DBGMCU_IDCODE_REV_ID_9   ((uint32_t)0x02000000)

Bit 9

#define DBGMCU_IDCODE_REV_ID_10   ((uint32_t)0x04000000)

Bit 10

#define DBGMCU_IDCODE_REV_ID_11   ((uint32_t)0x08000000)

Bit 11

#define DBGMCU_IDCODE_REV_ID_12   ((uint32_t)0x10000000)

Bit 12

#define DBGMCU_IDCODE_REV_ID_13   ((uint32_t)0x20000000)

Bit 13

#define DBGMCU_IDCODE_REV_ID_14   ((uint32_t)0x40000000)

Bit 14

#define DBGMCU_IDCODE_REV_ID_15   ((uint32_t)0x80000000)

Bit 15

#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)

Debug Sleep Mode

#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)

Debug Stop Mode

#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)

Debug Standby mode

#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)

Trace Pin Assignment Control

#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)

TRACE_MODE[1:0] bits (Trace Pin Assignment Control)

#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)

Bit 0

#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)

Bit 1

#define DBGMCU_CR_DBG_IWDG_STOP   ((uint32_t)0x00000100)

Debug Independent Watchdog stopped when Core is halted

#define DBGMCU_CR_DBG_WWDG_STOP   ((uint32_t)0x00000200)

Debug Window Watchdog stopped when Core is halted

#define DBGMCU_CR_DBG_TIM1_STOP   ((uint32_t)0x00000400)

TIM1 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM2_STOP   ((uint32_t)0x00000800)

TIM2 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM3_STOP   ((uint32_t)0x00001000)

TIM3 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM4_STOP   ((uint32_t)0x00002000)

TIM4 counter stopped when core is halted

#define DBGMCU_CR_DBG_CAN1_STOP   ((uint32_t)0x00004000)

Debug CAN1 stopped when Core is halted

#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00008000)

SMBUS timeout mode stopped when Core is halted

#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00010000)

SMBUS timeout mode stopped when Core is halted

#define DBGMCU_CR_DBG_TIM8_STOP   ((uint32_t)0x00020000)

TIM8 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM5_STOP   ((uint32_t)0x00040000)

TIM5 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM6_STOP   ((uint32_t)0x00080000)

TIM6 counter stopped when core is halted

#define DBGMCU_CR_DBG_TIM7_STOP   ((uint32_t)0x00100000)

TIM7 counter stopped when core is halted

#define DBGMCU_CR_DBG_CAN2_STOP   ((uint32_t)0x00200000)

Debug CAN2 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM15_STOP   ((uint32_t)0x00400000)

Debug TIM15 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM16_STOP   ((uint32_t)0x00800000)

Debug TIM16 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM17_STOP   ((uint32_t)0x01000000)

Debug TIM17 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM12_STOP   ((uint32_t)0x02000000)

Debug TIM12 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM13_STOP   ((uint32_t)0x04000000)

Debug TIM13 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM14_STOP   ((uint32_t)0x08000000)

Debug TIM14 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM9_STOP   ((uint32_t)0x10000000)

Debug TIM9 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM10_STOP   ((uint32_t)0x20000000)

Debug TIM10 stopped when Core is halted

#define DBGMCU_CR_DBG_TIM11_STOP   ((uint32_t)0x40000000)

Debug TIM11 stopped when Core is halted

#define FLASH_ACR_LATENCY   ((uint8_t)0x03)

LATENCY[2:0] bits (Latency)

Referenced by SetSysClock().

#define FLASH_ACR_LATENCY_0   ((uint8_t)0x00)

Bit 0

#define FLASH_ACR_LATENCY_1   ((uint8_t)0x01)

Bit 0

Referenced by SetSysClock().

#define FLASH_ACR_LATENCY_2   ((uint8_t)0x02)

Bit 1

#define FLASH_ACR_HLFCYA   ((uint8_t)0x08)

Flash Half Cycle Access Enable

#define FLASH_ACR_PRFTBE   ((uint8_t)0x10)

Prefetch Buffer Enable

Referenced by SetSysClock().

#define FLASH_ACR_PRFTBS   ((uint8_t)0x20)

Prefetch Buffer Status

Referenced by FLASH_EraseAllPages().

#define FLASH_KEYR_FKEYR   ((uint32_t)0xFFFFFFFF)

FPEC Key

#define FLASH_OPTKEYR_OPTKEYR   ((uint32_t)0xFFFFFFFF)

Option Byte Key

#define FLASH_SR_BSY   ((uint8_t)0x01)

Busy

Referenced by FLASH_GetStatus().

#define FLASH_SR_PGERR   ((uint8_t)0x04)

Programming Error

Referenced by FLASH_EraseAllPages(), and FLASH_GetStatus().

#define FLASH_SR_WRPRTERR   ((uint8_t)0x10)

Write Protection Error

Referenced by FLASH_EraseAllPages(), and FLASH_GetStatus().

#define FLASH_SR_EOP   ((uint8_t)0x20)

End of operation

Referenced by FLASH_EraseAllPages().

#define FLASH_CR_PG   ((uint16_t)0x0001)

Programming

Referenced by FLASH_EraseAllPages().

#define FLASH_CR_PER   ((uint16_t)0x0002)

Page Erase

Referenced by FLASH_EraseAllPages().

#define FLASH_CR_MER   ((uint16_t)0x0004)

Mass Erase

Referenced by FLASH_EraseAllBank1Pages(), and FLASH_EraseAllBank2Pages().

#define FLASH_CR_OPTPG   ((uint16_t)0x0010)

Option Byte Programming

Referenced by FLASH_EraseAllPages().

#define FLASH_CR_OPTER   ((uint16_t)0x0020)

Option Byte Erase

Referenced by FLASH_EraseAllPages().

#define FLASH_CR_STRT   ((uint16_t)0x0040)

Start

Referenced by FLASH_EraseAllBank1Pages(), FLASH_EraseAllBank2Pages(), and FLASH_EraseAllPages().

#define FLASH_CR_LOCK   ((uint16_t)0x0080)

Lock

Referenced by FLASH_Lock(), and FLASH_Unlock().

#define FLASH_CR_OPTWRE   ((uint16_t)0x0200)

Option Bytes Write Enable

#define FLASH_CR_ERRIE   ((uint16_t)0x0400)

Error Interrupt Enable

#define FLASH_CR_EOPIE   ((uint16_t)0x1000)

End of operation interrupt enable

#define FLASH_AR_FAR   ((uint32_t)0xFFFFFFFF)

Flash Address

#define FLASH_OBR_OPTERR   ((uint16_t)0x0001)

Option Byte Error

#define FLASH_OBR_RDPRT   ((uint16_t)0x0002)

Read protection

Referenced by FLASH_EraseAllPages().

#define FLASH_OBR_USER   ((uint16_t)0x03FC)

User Option Bytes

#define FLASH_OBR_WDG_SW   ((uint16_t)0x0004)

WDG_SW

#define FLASH_OBR_nRST_STOP   ((uint16_t)0x0008)

nRST_STOP

#define FLASH_OBR_nRST_STDBY   ((uint16_t)0x0010)

nRST_STDBY

#define FLASH_OBR_BFB2   ((uint16_t)0x0020)

BFB2

#define FLASH_WRPR_WRP   ((uint32_t)0xFFFFFFFF)

Write Protect

#define FLASH_RDP_RDP   ((uint32_t)0x000000FF)

Read protection option byte

#define FLASH_RDP_nRDP   ((uint32_t)0x0000FF00)

Read protection complemented option byte

#define FLASH_USER_USER   ((uint32_t)0x00FF0000)

User option byte

#define FLASH_USER_nUSER   ((uint32_t)0xFF000000)

User complemented option byte

#define FLASH_Data0_Data0   ((uint32_t)0x000000FF)

User data storage option byte

#define FLASH_Data0_nData0   ((uint32_t)0x0000FF00)

User data storage complemented option byte

#define FLASH_Data1_Data1   ((uint32_t)0x00FF0000)

User data storage option byte

#define FLASH_Data1_nData1   ((uint32_t)0xFF000000)

User data storage complemented option byte

#define FLASH_WRP0_WRP0   ((uint32_t)0x000000FF)

Flash memory write protection option bytes

#define FLASH_WRP0_nWRP0   ((uint32_t)0x0000FF00)

Flash memory write protection complemented option bytes

#define FLASH_WRP1_WRP1   ((uint32_t)0x00FF0000)

Flash memory write protection option bytes

#define FLASH_WRP1_nWRP1   ((uint32_t)0xFF000000)

Flash memory write protection complemented option bytes

#define FLASH_WRP2_WRP2   ((uint32_t)0x000000FF)

Flash memory write protection option bytes

#define FLASH_WRP2_nWRP2   ((uint32_t)0x0000FF00)

Flash memory write protection complemented option bytes

#define FLASH_WRP3_WRP3   ((uint32_t)0x00FF0000)

Flash memory write protection option bytes

#define FLASH_WRP3_nWRP3   ((uint32_t)0xFF000000)

Flash memory write protection complemented option bytes

#define ADC_SR_AWD   ((uint8_t)0x01)

Analog watchdog flag

#define ADC_SR_EOC   ((uint8_t)0x02)

End of conversion

#define ADC_SR_JEOC   ((uint8_t)0x04)

Injected channel end of conversion

#define ADC_SR_JSTRT   ((uint8_t)0x08)

Injected channel Start flag

#define ADC_SR_STRT   ((uint8_t)0x10)

Regular channel Start flag

#define ADC_SR_OVR   ((uint8_t)0x20)

Overrun flag

#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)

Interrupt enable for EOC

#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)

AAnalog Watchdog interrupt enable

#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)

Interrupt enable for injected channels

#define ADC_CR1_SCAN   ((uint32_t)0x00000100)

Scan mode

#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)

Automatic injected group conversion

#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)

Discontinuous mode on regular channels

#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)

Discontinuous mode on injected channels

#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)

Bit 0

#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)

Bit 1

#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)

Bit 2

#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

#define ADC_CR1_RES   ((uint32_t)0x03000000)

RES[2:0] bits (Resolution)

#define ADC_CR1_RES_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR1_RES_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)

overrun interrupt enable

#define ADC_CR2_ADON   ((uint32_t)0x00000001)

A/D Converter ON / OFF

#define ADC_CR2_CONT   ((uint32_t)0x00000002)

Continuous Conversion

#define ADC_CR2_DMA   ((uint32_t)0x00000100)

Direct Memory access mode

#define ADC_CR2_DDS   ((uint32_t)0x00000200)

DMA disable selection (Single ADC)

#define ADC_CR2_EOCS   ((uint32_t)0x00000400)

End of conversion selection

#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)

Data Alignment

#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)

JEXTSEL[3:0] bits (External event select for injected group)

#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)

Bit 2

#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)

Bit 3

#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)

Start Conversion of injected channels

#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)

EXTSEL[3:0] bits (External Event Select for regular group)

#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)

Bit 3

#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)

Bit 0

#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)

Bit 1

#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)

Start Conversion of regular channels

#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)

SMP18[2:0] bits (Channel 18 Sample time selection)

#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)

Data offset for injected channel 1

#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)

Data offset for injected channel 2

#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)

Data offset for injected channel 3

#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)

Data offset for injected channel 4

#define ADC_HTR_HT   ((uint16_t)0x0FFF)

Analog watchdog high threshold

#define ADC_LTR_LT   ((uint16_t)0x0FFF)

Analog watchdog low threshold

#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR1_L   ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

#define ADC_SQR1_L_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR1_L_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR1_L_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR1_L_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_JSQR_JL   ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)

Regular data

#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)

ADC2 data

#define ADC_CSR_AWD1   ((uint32_t)0x00000001)

ADC1 Analog watchdog flag

#define ADC_CSR_EOC1   ((uint32_t)0x00000002)

ADC1 End of conversion

#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)

ADC1 Injected channel end of conversion

#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)

ADC1 Injected channel Start flag

#define ADC_CSR_STRT1   ((uint32_t)0x00000010)

ADC1 Regular channel Start flag

#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)

ADC1 DMA overrun flag

#define ADC_CSR_AWD2   ((uint32_t)0x00000100)

ADC2 Analog watchdog flag

#define ADC_CSR_EOC2   ((uint32_t)0x00000200)

ADC2 End of conversion

#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)

ADC2 Injected channel end of conversion

#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)

ADC2 Injected channel Start flag

#define ADC_CSR_STRT2   ((uint32_t)0x00001000)

ADC2 Regular channel Start flag

#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)

ADC2 DMA overrun flag

#define ADC_CSR_AWD3   ((uint32_t)0x00010000)

ADC3 Analog watchdog flag

#define ADC_CSR_EOC3   ((uint32_t)0x00020000)

ADC3 End of conversion

#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)

ADC3 Injected channel end of conversion

#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)

ADC3 Injected channel Start flag

#define ADC_CSR_STRT3   ((uint32_t)0x00100000)

ADC3 Regular channel Start flag

#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)

ADC3 DMA overrun flag

#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)

MULTI[4:0] bits (Multi-ADC mode selection)

#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)

DELAY[3:0] bits (Delay between 2 sampling phases)

#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)

Bit 0

#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)

Bit 1

#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)

Bit 2

#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)

Bit 3

#define ADC_CCR_DDS   ((uint32_t)0x00002000)

DMA disable selection (Multi-ADC mode)

#define ADC_CCR_DMA   ((uint32_t)0x0000C000)

DMA[1:0] bits (Direct Memory Access mode for multimode)

#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)

Bit 0

#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)

Bit 1

#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)

ADCPRE[1:0] bits (ADC prescaler)

#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CCR_VBATE   ((uint32_t)0x00400000)

VBAT Enable

#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)

1st data of a pair of regular conversions

#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)

2nd data of a pair of regular conversions

#define CAN_MCR_INRQ   ((uint16_t)0x0001)

<CAN control and status registers Initialization Request

#define CAN_MCR_SLEEP   ((uint16_t)0x0002)

Sleep Mode Request

#define CAN_MCR_TXFP   ((uint16_t)0x0004)

Transmit FIFO Priority

#define CAN_MCR_RFLM   ((uint16_t)0x0008)

Receive FIFO Locked Mode

#define CAN_MCR_NART   ((uint16_t)0x0010)

No Automatic Retransmission

#define CAN_MCR_AWUM   ((uint16_t)0x0020)

Automatic Wakeup Mode

#define CAN_MCR_ABOM   ((uint16_t)0x0040)

Automatic Bus-Off Management

#define CAN_MCR_TTCM   ((uint16_t)0x0080)

Time Triggered Communication Mode

#define CAN_MCR_RESET   ((uint16_t)0x8000)

bxCAN software master reset

#define CAN_MSR_INAK   ((uint16_t)0x0001)

Initialization Acknowledge

#define CAN_MSR_SLAK   ((uint16_t)0x0002)

Sleep Acknowledge

#define CAN_MSR_ERRI   ((uint16_t)0x0004)

Error Interrupt

#define CAN_MSR_WKUI   ((uint16_t)0x0008)

Wakeup Interrupt

#define CAN_MSR_SLAKI   ((uint16_t)0x0010)

Sleep Acknowledge Interrupt

#define CAN_MSR_TXM   ((uint16_t)0x0100)

Transmit Mode

#define CAN_MSR_RXM   ((uint16_t)0x0200)

Receive Mode

#define CAN_MSR_SAMP   ((uint16_t)0x0400)

Last Sample Point

#define CAN_MSR_RX   ((uint16_t)0x0800)

CAN Rx Signal

#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)

Request Completed Mailbox0

#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)

Transmission OK of Mailbox0

#define CAN_TSR_ALST0   ((uint32_t)0x00000004)

Arbitration Lost for Mailbox0

#define CAN_TSR_TERR0   ((uint32_t)0x00000008)

Transmission Error of Mailbox0

#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)

Abort Request for Mailbox0

#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)

Request Completed Mailbox1

#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)

Transmission OK of Mailbox1

#define CAN_TSR_ALST1   ((uint32_t)0x00000400)

Arbitration Lost for Mailbox1

#define CAN_TSR_TERR1   ((uint32_t)0x00000800)

Transmission Error of Mailbox1

#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)

Abort Request for Mailbox 1

#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)

Request Completed Mailbox2

#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)

Transmission OK of Mailbox 2

#define CAN_TSR_ALST2   ((uint32_t)0x00040000)

Arbitration Lost for mailbox 2

#define CAN_TSR_TERR2   ((uint32_t)0x00080000)

Transmission Error of Mailbox 2

#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)

Abort Request for Mailbox 2

#define CAN_TSR_CODE   ((uint32_t)0x03000000)

Mailbox Code

#define CAN_TSR_TME   ((uint32_t)0x1C000000)

TME[2:0] bits

#define CAN_TSR_TME0   ((uint32_t)0x04000000)

Transmit Mailbox 0 Empty

#define CAN_TSR_TME1   ((uint32_t)0x08000000)

Transmit Mailbox 1 Empty

#define CAN_TSR_TME2   ((uint32_t)0x10000000)

Transmit Mailbox 2 Empty

#define CAN_TSR_LOW   ((uint32_t)0xE0000000)

LOW[2:0] bits

#define CAN_TSR_LOW0   ((uint32_t)0x20000000)

Lowest Priority Flag for Mailbox 0

#define CAN_TSR_LOW1   ((uint32_t)0x40000000)

Lowest Priority Flag for Mailbox 1

#define CAN_TSR_LOW2   ((uint32_t)0x80000000)

Lowest Priority Flag for Mailbox 2

#define CAN_RF0R_FMP0   ((uint8_t)0x03)

FIFO 0 Message Pending

#define CAN_RF0R_FULL0   ((uint8_t)0x08)

FIFO 0 Full

#define CAN_RF0R_FOVR0   ((uint8_t)0x10)

FIFO 0 Overrun

#define CAN_RF0R_RFOM0   ((uint8_t)0x20)

Release FIFO 0 Output Mailbox

#define CAN_RF1R_FMP1   ((uint8_t)0x03)

FIFO 1 Message Pending

#define CAN_RF1R_FULL1   ((uint8_t)0x08)

FIFO 1 Full

#define CAN_RF1R_FOVR1   ((uint8_t)0x10)

FIFO 1 Overrun

#define CAN_RF1R_RFOM1   ((uint8_t)0x20)

Release FIFO 1 Output Mailbox

#define CAN_IER_TMEIE   ((uint32_t)0x00000001)

Transmit Mailbox Empty Interrupt Enable

#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)

FIFO Message Pending Interrupt Enable

#define CAN_IER_FFIE0   ((uint32_t)0x00000004)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)

FIFO Overrun Interrupt Enable

#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)

FIFO Message Pending Interrupt Enable

#define CAN_IER_FFIE1   ((uint32_t)0x00000020)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)

FIFO Overrun Interrupt Enable

#define CAN_IER_EWGIE   ((uint32_t)0x00000100)

Error Warning Interrupt Enable

#define CAN_IER_EPVIE   ((uint32_t)0x00000200)

Error Passive Interrupt Enable

#define CAN_IER_BOFIE   ((uint32_t)0x00000400)

Bus-Off Interrupt Enable

#define CAN_IER_LECIE   ((uint32_t)0x00000800)

Last Error Code Interrupt Enable

#define CAN_IER_ERRIE   ((uint32_t)0x00008000)

Error Interrupt Enable

#define CAN_IER_WKUIE   ((uint32_t)0x00010000)

Wakeup Interrupt Enable

#define CAN_IER_SLKIE   ((uint32_t)0x00020000)

Sleep Interrupt Enable

#define CAN_ESR_EWGF   ((uint32_t)0x00000001)

Error Warning Flag

#define CAN_ESR_EPVF   ((uint32_t)0x00000002)

Error Passive Flag

#define CAN_ESR_BOFF   ((uint32_t)0x00000004)

Bus-Off Flag

#define CAN_ESR_LEC   ((uint32_t)0x00000070)

LEC[2:0] bits (Last Error Code)

#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)

Bit 0

#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)

Bit 1

#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)

Bit 2

#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)

Least significant byte of the 9-bit Transmit Error Counter

#define CAN_ESR_REC   ((uint32_t)0xFF000000)

Receive Error Counter

#define CAN_BTR_BRP   ((uint32_t)0x000003FF)

Baud Rate Prescaler

#define CAN_BTR_TS1   ((uint32_t)0x000F0000)

Time Segment 1

#define CAN_BTR_TS2   ((uint32_t)0x00700000)

Time Segment 2

#define CAN_BTR_SJW   ((uint32_t)0x03000000)

Resynchronization Jump Width

#define CAN_BTR_LBKM   ((uint32_t)0x40000000)

Loop Back Mode (Debug)

#define CAN_BTR_SILM   ((uint32_t)0x80000000)

Silent Mode Mailbox registers

#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI2R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI2R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_RI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_RI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7 CAN filter registers

#define CAN_FMR_FINIT   ((uint8_t)0x01)

Filter Init Mode

#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)

Filter Mode

#define CAN_FM1R_FBM0   ((uint16_t)0x0001)

Filter Init Mode bit 0

#define CAN_FM1R_FBM1   ((uint16_t)0x0002)

Filter Init Mode bit 1

#define CAN_FM1R_FBM2   ((uint16_t)0x0004)

Filter Init Mode bit 2

#define CAN_FM1R_FBM3   ((uint16_t)0x0008)

Filter Init Mode bit 3

#define CAN_FM1R_FBM4   ((uint16_t)0x0010)

Filter Init Mode bit 4

#define CAN_FM1R_FBM5   ((uint16_t)0x0020)

Filter Init Mode bit 5

#define CAN_FM1R_FBM6   ((uint16_t)0x0040)

Filter Init Mode bit 6

#define CAN_FM1R_FBM7   ((uint16_t)0x0080)

Filter Init Mode bit 7

#define CAN_FM1R_FBM8   ((uint16_t)0x0100)

Filter Init Mode bit 8

#define CAN_FM1R_FBM9   ((uint16_t)0x0200)

Filter Init Mode bit 9

#define CAN_FM1R_FBM10   ((uint16_t)0x0400)

Filter Init Mode bit 10

#define CAN_FM1R_FBM11   ((uint16_t)0x0800)

Filter Init Mode bit 11

#define CAN_FM1R_FBM12   ((uint16_t)0x1000)

Filter Init Mode bit 12

#define CAN_FM1R_FBM13   ((uint16_t)0x2000)

Filter Init Mode bit 13

#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)

Filter Scale Configuration

#define CAN_FS1R_FSC0   ((uint16_t)0x0001)

Filter Scale Configuration bit 0

#define CAN_FS1R_FSC1   ((uint16_t)0x0002)

Filter Scale Configuration bit 1

#define CAN_FS1R_FSC2   ((uint16_t)0x0004)

Filter Scale Configuration bit 2

#define CAN_FS1R_FSC3   ((uint16_t)0x0008)

Filter Scale Configuration bit 3

#define CAN_FS1R_FSC4   ((uint16_t)0x0010)

Filter Scale Configuration bit 4

#define CAN_FS1R_FSC5   ((uint16_t)0x0020)

Filter Scale Configuration bit 5

#define CAN_FS1R_FSC6   ((uint16_t)0x0040)

Filter Scale Configuration bit 6

#define CAN_FS1R_FSC7   ((uint16_t)0x0080)

Filter Scale Configuration bit 7

#define CAN_FS1R_FSC8   ((uint16_t)0x0100)

Filter Scale Configuration bit 8

#define CAN_FS1R_FSC9   ((uint16_t)0x0200)

Filter Scale Configuration bit 9

#define CAN_FS1R_FSC10   ((uint16_t)0x0400)

Filter Scale Configuration bit 10

#define CAN_FS1R_FSC11   ((uint16_t)0x0800)

Filter Scale Configuration bit 11

#define CAN_FS1R_FSC12   ((uint16_t)0x1000)

Filter Scale Configuration bit 12

#define CAN_FS1R_FSC13   ((uint16_t)0x2000)

Filter Scale Configuration bit 13

#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)

Filter FIFO Assignment

#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)

Filter FIFO Assignment for Filter 0

#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)

Filter FIFO Assignment for Filter 1

#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)

Filter FIFO Assignment for Filter 2

#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)

Filter FIFO Assignment for Filter 3

#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)

Filter FIFO Assignment for Filter 4

#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)

Filter FIFO Assignment for Filter 5

#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)

Filter FIFO Assignment for Filter 6

#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)

Filter FIFO Assignment for Filter 7

#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)

Filter FIFO Assignment for Filter 8

#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)

Filter FIFO Assignment for Filter 9

#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)

Filter FIFO Assignment for Filter 10

#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)

Filter FIFO Assignment for Filter 11

#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)

Filter FIFO Assignment for Filter 12

#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)

Filter FIFO Assignment for Filter 13

#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)

Filter Active

#define CAN_FA1R_FACT0   ((uint16_t)0x0001)

Filter 0 Active

#define CAN_FA1R_FACT1   ((uint16_t)0x0002)

Filter 1 Active

#define CAN_FA1R_FACT2   ((uint16_t)0x0004)

Filter 2 Active

#define CAN_FA1R_FACT3   ((uint16_t)0x0008)

Filter 3 Active

#define CAN_FA1R_FACT4   ((uint16_t)0x0010)

Filter 4 Active

#define CAN_FA1R_FACT5   ((uint16_t)0x0020)

Filter 5 Active

#define CAN_FA1R_FACT6   ((uint16_t)0x0040)

Filter 6 Active

#define CAN_FA1R_FACT7   ((uint16_t)0x0080)

Filter 7 Active

#define CAN_FA1R_FACT8   ((uint16_t)0x0100)

Filter 8 Active

#define CAN_FA1R_FACT9   ((uint16_t)0x0200)

Filter 9 Active

#define CAN_FA1R_FACT10   ((uint16_t)0x0400)

Filter 10 Active

#define CAN_FA1R_FACT11   ((uint16_t)0x0800)

Filter 11 Active

#define CAN_FA1R_FACT12   ((uint16_t)0x1000)

Filter 12 Active

#define CAN_FA1R_FACT13   ((uint16_t)0x2000)

Filter 13 Active

#define CAN_F0R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F0R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)

Data register bits

#define CRC_IDR_IDR   ((uint8_t)0xFF)

General-purpose 8-bit data register bits

#define CRC_CR_RESET   ((uint8_t)0x01)

RESET bit

#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)

#define CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)

#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)

#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)

#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)

#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)

#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)

#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)

#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)

#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)

#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)

#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)

#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)

#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)

#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)

#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)

#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)

#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)

#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)

#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)

#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)

#define CRYP_SR_IFEM   ((uint32_t)0x00000001)

#define CRYP_SR_IFNF   ((uint32_t)0x00000002)

#define CRYP_SR_OFNE   ((uint32_t)0x00000004)

#define CRYP_SR_OFFU   ((uint32_t)0x00000008)

#define CRYP_SR_BUSY   ((uint32_t)0x00000010)

#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)

#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)

#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)

#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)

#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)

#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)

#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)

#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)

#define DAC_CR_EN1   ((uint32_t)0x00000001)

DAC channel1 enable

#define DAC_CR_BOFF1   ((uint32_t)0x00000002)

DAC channel1 output buffer disable

#define DAC_CR_TEN1   ((uint32_t)0x00000004)

DAC channel1 Trigger enable

#define DAC_CR_TSEL1   ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)

Bit 0

#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)

Bit 1

#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)

Bit 2

#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)

Bit 0

#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)

Bit 1

#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)

Bit 0

#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)

Bit 1

#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)

Bit 2

#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)

Bit 3

#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)

DAC channel1 DMA enable

#define DAC_CR_EN2   ((uint32_t)0x00010000)

DAC channel2 enable

#define DAC_CR_BOFF2   ((uint32_t)0x00020000)

DAC channel2 output buffer disable

#define DAC_CR_TEN2   ((uint32_t)0x00040000)

DAC channel2 Trigger enable

#define DAC_CR_TSEL2   ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)

Bit 0

#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)

Bit 1

#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)

Bit 2

#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)

Bit 0

#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)

Bit 1

#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)

Bit 0

#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)

Bit 1

#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)

Bit 2

#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)

Bit 3

#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)

DAC channel2 DMA enabled

#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)

DAC channel1 software trigger

#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)

DAC channel2 software trigger

#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)

DAC channel1 data output

#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)

DAC channel2 data output

#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)

#define DCMI_CR_CM   ((uint32_t)0x00000002)

#define DCMI_CR_CROP   ((uint32_t)0x00000004)

#define DCMI_CR_JPEG   ((uint32_t)0x00000008)

#define DCMI_CR_ESS   ((uint32_t)0x00000010)

#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)

#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)

#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)

#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)

#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)

#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)

#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)

#define DCMI_CR_CRE   ((uint32_t)0x00001000)

#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)

#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)

#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)

#define DCMI_SR_FNE   ((uint32_t)0x00000004)

#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)

#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)

#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)

#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)

#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)

#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)

#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)

#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)

#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)

#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)

#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)

#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)

#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)

#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)

#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)

#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)

#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)

#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)

#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)

#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)

#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)

Referenced by DMA_Setup().

#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)

Referenced by DMA_Setup().

#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)

#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)

#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)

#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)

#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)

#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)

#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)

#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)

#define DMA_SxCR_ACK   ((uint32_t)0x00100000)

#define DMA_SxCR_CT   ((uint32_t)0x00080000)

#define DMA_SxCR_DBM   ((uint32_t)0x00040000)

#define DMA_SxCR_PL   ((uint32_t)0x00030000)

#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)

#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)

#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)

#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)

#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)

#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)

#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)

#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)

#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)

#define DMA_SxCR_MINC   ((uint32_t)0x00000400)

#define DMA_SxCR_PINC   ((uint32_t)0x00000200)

#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)

#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)

Referenced by DMA_Setup().

#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)

Referenced by DMA_Setup().

#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)

Referenced by DMA_Setup().

#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)

#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)

Referenced by DMA_IrqMask().

#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)

Referenced by DMA_IrqMask().

#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)

Referenced by DMA_IrqMask().

#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)

#define DMA_SxCR_EN   ((uint32_t)0x00000001)

Referenced by DMA_Disable(), DMA_Enable(), and DMA_Setup().

#define DMA_SxNDT   ((uint32_t)0x0000FFFF)

#define DMA_SxNDT_0   ((uint32_t)0x00000001)

#define DMA_SxNDT_1   ((uint32_t)0x00000002)

#define DMA_SxNDT_2   ((uint32_t)0x00000004)

#define DMA_SxNDT_3   ((uint32_t)0x00000008)

#define DMA_SxNDT_4   ((uint32_t)0x00000010)

#define DMA_SxNDT_5   ((uint32_t)0x00000020)

#define DMA_SxNDT_6   ((uint32_t)0x00000040)

#define DMA_SxNDT_7   ((uint32_t)0x00000080)

#define DMA_SxNDT_8   ((uint32_t)0x00000100)

#define DMA_SxNDT_9   ((uint32_t)0x00000200)

#define DMA_SxNDT_10   ((uint32_t)0x00000400)

#define DMA_SxNDT_11   ((uint32_t)0x00000800)

#define DMA_SxNDT_12   ((uint32_t)0x00001000)

#define DMA_SxNDT_13   ((uint32_t)0x00002000)

#define DMA_SxNDT_14   ((uint32_t)0x00004000)

#define DMA_SxNDT_15   ((uint32_t)0x00008000)

#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)

#define DMA_SxFCR_FS   ((uint32_t)0x00000038)

#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)

#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)

#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)

#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)

#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)

#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)

#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)

#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)

#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)

#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)

#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)

#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)

#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)

#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)

#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)

#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)

#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)

#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)

#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)

#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)

#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)

#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)

#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)

Referenced by DMA_GetFlag().

#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)

Referenced by DMA_GetFlag().

#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)

Referenced by DMA_GetFlag().

#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)

#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)

#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)

#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)

#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)

#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)

#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)

#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)

#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)

#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)

#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)

#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)

#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)

#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)

#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)

#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)

#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)

#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)

#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)

#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)

#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)

#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)

#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)

#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)

#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)

#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)

#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)

#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)

#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)

#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)

#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)

#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)

#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)

#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)

#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)

#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)

#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)

#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)

Referenced by DMA_ClearFlag(), and DMA_IrqMask().

#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)

Referenced by DMA_ClearFlag(), and DMA_IrqMask().

#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)

Referenced by DMA_ClearFlag(), and DMA_IrqMask().

#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)

Referenced by DMA_ClearFlag(), and DMA_IrqMask().

#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)

Referenced by DMA_ClearFlag(), and DMA_IrqMask().

#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)

#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)

#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)

#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)

#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)

#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)

#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)

#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)

#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)

#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)

#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)

#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)

#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)

#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)

#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)

#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)

#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)

#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)

#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)

#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)

#define EXTI_IMR_MR0   ((uint32_t)0x00000001)

Interrupt Mask on line 0

#define EXTI_IMR_MR1   ((uint32_t)0x00000002)

Interrupt Mask on line 1

#define EXTI_IMR_MR2   ((uint32_t)0x00000004)

Interrupt Mask on line 2

#define EXTI_IMR_MR3   ((uint32_t)0x00000008)

Interrupt Mask on line 3

#define EXTI_IMR_MR4   ((uint32_t)0x00000010)

Interrupt Mask on line 4

#define EXTI_IMR_MR5   ((uint32_t)0x00000020)

Interrupt Mask on line 5

#define EXTI_IMR_MR6   ((uint32_t)0x00000040)

Interrupt Mask on line 6

#define EXTI_IMR_MR7   ((uint32_t)0x00000080)

Interrupt Mask on line 7

#define EXTI_IMR_MR8   ((uint32_t)0x00000100)

Interrupt Mask on line 8

#define EXTI_IMR_MR9   ((uint32_t)0x00000200)

Interrupt Mask on line 9

#define EXTI_IMR_MR10   ((uint32_t)0x00000400)

Interrupt Mask on line 10

#define EXTI_IMR_MR11   ((uint32_t)0x00000800)

Interrupt Mask on line 11

#define EXTI_IMR_MR12   ((uint32_t)0x00001000)

Interrupt Mask on line 12

#define EXTI_IMR_MR13   ((uint32_t)0x00002000)

Interrupt Mask on line 13

#define EXTI_IMR_MR14   ((uint32_t)0x00004000)

Interrupt Mask on line 14

#define EXTI_IMR_MR15   ((uint32_t)0x00008000)

Interrupt Mask on line 15

#define EXTI_IMR_MR16   ((uint32_t)0x00010000)

Interrupt Mask on line 16

#define EXTI_IMR_MR17   ((uint32_t)0x00020000)

Interrupt Mask on line 17

#define EXTI_IMR_MR18   ((uint32_t)0x00040000)

Interrupt Mask on line 18

#define EXTI_IMR_MR19   ((uint32_t)0x00080000)

Interrupt Mask on line 19

#define EXTI_EMR_MR0   ((uint32_t)0x00000001)

Event Mask on line 0

#define EXTI_EMR_MR1   ((uint32_t)0x00000002)

Event Mask on line 1

#define EXTI_EMR_MR2   ((uint32_t)0x00000004)

Event Mask on line 2

#define EXTI_EMR_MR3   ((uint32_t)0x00000008)

Event Mask on line 3

#define EXTI_EMR_MR4   ((uint32_t)0x00000010)

Event Mask on line 4

#define EXTI_EMR_MR5   ((uint32_t)0x00000020)

Event Mask on line 5

#define EXTI_EMR_MR6   ((uint32_t)0x00000040)

Event Mask on line 6

#define EXTI_EMR_MR7   ((uint32_t)0x00000080)

Event Mask on line 7

#define EXTI_EMR_MR8   ((uint32_t)0x00000100)

Event Mask on line 8

#define EXTI_EMR_MR9   ((uint32_t)0x00000200)

Event Mask on line 9

#define EXTI_EMR_MR10   ((uint32_t)0x00000400)

Event Mask on line 10

#define EXTI_EMR_MR11   ((uint32_t)0x00000800)

Event Mask on line 11

#define EXTI_EMR_MR12   ((uint32_t)0x00001000)

Event Mask on line 12

#define EXTI_EMR_MR13   ((uint32_t)0x00002000)

Event Mask on line 13

#define EXTI_EMR_MR14   ((uint32_t)0x00004000)

Event Mask on line 14

#define EXTI_EMR_MR15   ((uint32_t)0x00008000)

Event Mask on line 15

#define EXTI_EMR_MR16   ((uint32_t)0x00010000)

Event Mask on line 16

#define EXTI_EMR_MR17   ((uint32_t)0x00020000)

Event Mask on line 17

#define EXTI_EMR_MR18   ((uint32_t)0x00040000)

Event Mask on line 18

#define EXTI_EMR_MR19   ((uint32_t)0x00080000)

Event Mask on line 19

#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)

Software Interrupt on line 0

#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)

Software Interrupt on line 1

#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)

Software Interrupt on line 2

#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)

Software Interrupt on line 3

#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)

Software Interrupt on line 4

#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)

Software Interrupt on line 5

#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)

Software Interrupt on line 6

#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)

Software Interrupt on line 7

#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)

Software Interrupt on line 8

#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)

Software Interrupt on line 9

#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)

Software Interrupt on line 10

#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)

Software Interrupt on line 11

#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)

Software Interrupt on line 12

#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)

Software Interrupt on line 13

#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)

Software Interrupt on line 14

#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)

Software Interrupt on line 15

#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)

Software Interrupt on line 16

#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)

Software Interrupt on line 17

#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)

Software Interrupt on line 18

#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)

Software Interrupt on line 19

#define EXTI_PR_PR0   ((uint32_t)0x00000001)

Pending bit for line 0

#define EXTI_PR_PR1   ((uint32_t)0x00000002)

Pending bit for line 1

#define EXTI_PR_PR2   ((uint32_t)0x00000004)

Pending bit for line 2

#define EXTI_PR_PR3   ((uint32_t)0x00000008)

Pending bit for line 3

#define EXTI_PR_PR4   ((uint32_t)0x00000010)

Pending bit for line 4

#define EXTI_PR_PR5   ((uint32_t)0x00000020)

Pending bit for line 5

#define EXTI_PR_PR6   ((uint32_t)0x00000040)

Pending bit for line 6

#define EXTI_PR_PR7   ((uint32_t)0x00000080)

Pending bit for line 7

#define EXTI_PR_PR8   ((uint32_t)0x00000100)

Pending bit for line 8

#define EXTI_PR_PR9   ((uint32_t)0x00000200)

Pending bit for line 9

#define EXTI_PR_PR10   ((uint32_t)0x00000400)

Pending bit for line 10

#define EXTI_PR_PR11   ((uint32_t)0x00000800)

Pending bit for line 11

#define EXTI_PR_PR12   ((uint32_t)0x00001000)

Pending bit for line 12

#define EXTI_PR_PR13   ((uint32_t)0x00002000)

Pending bit for line 13

#define EXTI_PR_PR14   ((uint32_t)0x00004000)

Pending bit for line 14

#define EXTI_PR_PR15   ((uint32_t)0x00008000)

Pending bit for line 15

#define EXTI_PR_PR16   ((uint32_t)0x00010000)

Pending bit for line 16

#define EXTI_PR_PR17   ((uint32_t)0x00020000)

Pending bit for line 17

#define EXTI_PR_PR18   ((uint32_t)0x00040000)

Pending bit for line 18

#define EXTI_PR_PR19   ((uint32_t)0x00080000)

Pending bit for line 19

#define FLASH_ACR_LATENCY   ((uint32_t)0x00000007)

#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)

#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)

#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)

#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)

#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)

#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)

#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)

#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)

#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)

#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)

#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)

#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)

#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)

#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)

#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)

#define FLASH_SR_EOP   ((uint32_t)0x00000001)

#define FLASH_SR_SOP   ((uint32_t)0x00000002)

#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)

#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)

#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)

#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)

#define FLASH_SR_BSY   ((uint32_t)0x00010000)

#define FLASH_CR_PG   ((uint32_t)0x00000001)

#define FLASH_CR_SER   ((uint32_t)0x00000002)

#define FLASH_CR_MER   ((uint32_t)0x00000004)

#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)

#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)

#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)

#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)

#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)

#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)

#define FLASH_CR_STRT   ((uint32_t)0x00010000)

#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)

#define FLASH_CR_LOCK   ((uint32_t)0x80000000)

#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)

#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)

#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)

#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)

#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)

#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)

#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)

#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)

#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)

#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)

#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)

#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)

#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)

#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)

#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)

#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)

#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)

#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)

#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)

#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)

#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)

#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)

#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)

#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)

#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)

#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)

#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)

#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)

#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit.

#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)

ECCPS[1:0] bits (ECC page size)

#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_SR2_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR2_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR2_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR2_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR2_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR2_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR2_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR3_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR3_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR3_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR3_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR3_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR3_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR3_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR4_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR4_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR4_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR4_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR4_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR4_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR4_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)

MEMSET2[7:0] bits (Common memory 2 setup time)

#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)

MEMWAIT2[7:0] bits (Common memory 2 wait time)

#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)

MEMHOLD2[7:0] bits (Common memory 2 hold time)

#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)

MEMSET3[7:0] bits (Common memory 3 setup time)

#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)

MEMWAIT3[7:0] bits (Common memory 3 wait time)

#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)

MEMHOLD3[7:0] bits (Common memory 3 hold time)

#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)

MEMSET4[7:0] bits (Common memory 4 setup time)

#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)

MEMWAIT4[7:0] bits (Common memory 4 wait time)

#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)

MEMHOLD4[7:0] bits (Common memory 4 hold time)

#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)

ATTSET2[7:0] bits (Attribute memory 2 setup time)

#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)

ATTSET3[7:0] bits (Attribute memory 3 setup time)

#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)

ATTSET4[7:0] bits (Attribute memory 4 setup time)

#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)

IOSET4[7:0] bits (I/O 4 setup time)

#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)

IOWAIT4[7:0] bits (I/O 4 wait time)

#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)

IOHOLD4[7:0] bits (I/O 4 hold time)

#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)

ECC result

#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)

ECC result

#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)

#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)

#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)

#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)

#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)

#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)

#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)

#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)

#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)

#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)

#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)

#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)

#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)

#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)

#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)

#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)

#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)

#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)

#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)

#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)

#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)

#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)

#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)

#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)

#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)

#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)

#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)

#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)

#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)

#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)

#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)

#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)

#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)

#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)

#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)

#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)

#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)

#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)

#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)

#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)

#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)

#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)

#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)

#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)

#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)

#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)

#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)

#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)

#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)

#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)

#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)

#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)

#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)

#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)

#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)

#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)

#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)

#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)

#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)

#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)

#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)

#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)

#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)

#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)

#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)

#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)

#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)

#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)

#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)

#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)

#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)

#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)

#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)

#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)

#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)

#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)

#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)

#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)

#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)

#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)

#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)

#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)

#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)

#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)

#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)

#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)

#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)

#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)

#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)

#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)

#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)

#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)

#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)

#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)

#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)

#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)

#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)

#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)

#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)

#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)

#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)

#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)

#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)

#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)

#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)

#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)

#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)

#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)

#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)

#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)

#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)

#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)

#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)

#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)

#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)

#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)

#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)

#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)

#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)

#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)

#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)

#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)

#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)

#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)

#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)

#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)

#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)

#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)

#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)

#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)

#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)

#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)

#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)

#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)

#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)

#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)

#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)

#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)

#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)

#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)

#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)

#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)

#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)

#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)

#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)

#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)

#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)

#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)

#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)

#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)

#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)

#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)

#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)

#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)

#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)

#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)

#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)

#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)

#define GPIO_OTYPER_IDR_0   ((uint32_t)0x00000001)

#define GPIO_OTYPER_IDR_1   ((uint32_t)0x00000002)

#define GPIO_OTYPER_IDR_2   ((uint32_t)0x00000004)

#define GPIO_OTYPER_IDR_3   ((uint32_t)0x00000008)

#define GPIO_OTYPER_IDR_4   ((uint32_t)0x00000010)

#define GPIO_OTYPER_IDR_5   ((uint32_t)0x00000020)

#define GPIO_OTYPER_IDR_6   ((uint32_t)0x00000040)

#define GPIO_OTYPER_IDR_7   ((uint32_t)0x00000080)

#define GPIO_OTYPER_IDR_8   ((uint32_t)0x00000100)

#define GPIO_OTYPER_IDR_9   ((uint32_t)0x00000200)

#define GPIO_OTYPER_IDR_10   ((uint32_t)0x00000400)

#define GPIO_OTYPER_IDR_11   ((uint32_t)0x00000800)

#define GPIO_OTYPER_IDR_12   ((uint32_t)0x00001000)

#define GPIO_OTYPER_IDR_13   ((uint32_t)0x00002000)

#define GPIO_OTYPER_IDR_14   ((uint32_t)0x00004000)

#define GPIO_OTYPER_IDR_15   ((uint32_t)0x00008000)

#define GPIO_OTYPER_ODR_0   ((uint32_t)0x00000001)

#define GPIO_OTYPER_ODR_1   ((uint32_t)0x00000002)

#define GPIO_OTYPER_ODR_2   ((uint32_t)0x00000004)

#define GPIO_OTYPER_ODR_3   ((uint32_t)0x00000008)

#define GPIO_OTYPER_ODR_4   ((uint32_t)0x00000010)

#define GPIO_OTYPER_ODR_5   ((uint32_t)0x00000020)

#define GPIO_OTYPER_ODR_6   ((uint32_t)0x00000040)

#define GPIO_OTYPER_ODR_7   ((uint32_t)0x00000080)

#define GPIO_OTYPER_ODR_8   ((uint32_t)0x00000100)

#define GPIO_OTYPER_ODR_9   ((uint32_t)0x00000200)

#define GPIO_OTYPER_ODR_10   ((uint32_t)0x00000400)

#define GPIO_OTYPER_ODR_11   ((uint32_t)0x00000800)

#define GPIO_OTYPER_ODR_12   ((uint32_t)0x00001000)

#define GPIO_OTYPER_ODR_13   ((uint32_t)0x00002000)

#define GPIO_OTYPER_ODR_14   ((uint32_t)0x00004000)

#define GPIO_OTYPER_ODR_15   ((uint32_t)0x00008000)

#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)

#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)

#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)

#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)

#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)

#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)

#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)

#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)

#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)

#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)

#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)

#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)

#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)

#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)

#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)

#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)

#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)

#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)

#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)

#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)

#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)

#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)

#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)

#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)

#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)

#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)

#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)

#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)

#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)

#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)

#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)

#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)

#define HASH_CR_INIT   ((uint32_t)0x00000004)

#define HASH_CR_DMAE   ((uint32_t)0x00000008)

#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)

#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)

#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)

#define HASH_CR_MODE   ((uint32_t)0x00000040)

#define HASH_CR_ALGO   ((uint32_t)0x00000080)

#define HASH_CR_NBW   ((uint32_t)0x00000F00)

#define HASH_CR_NBW_0   ((uint32_t)0x00000100)

#define HASH_CR_NBW_1   ((uint32_t)0x00000200)

#define HASH_CR_NBW_2   ((uint32_t)0x00000400)

#define HASH_CR_NBW_3   ((uint32_t)0x00000800)

#define HASH_CR_DINNE   ((uint32_t)0x00001000)

#define HASH_CR_LKEY   ((uint32_t)0x00010000)

#define HASH_STR_NBW   ((uint32_t)0x0000001F)

#define HASH_STR_NBW_0   ((uint32_t)0x00000001)

#define HASH_STR_NBW_1   ((uint32_t)0x00000002)

#define HASH_STR_NBW_2   ((uint32_t)0x00000004)

#define HASH_STR_NBW_3   ((uint32_t)0x00000008)

#define HASH_STR_NBW_4   ((uint32_t)0x00000010)

#define HASH_STR_DCAL   ((uint32_t)0x00000100)

#define HASH_IMR_DINIM   ((uint32_t)0x00000001)

#define HASH_IMR_DCIM   ((uint32_t)0x00000002)

#define HASH_SR_DINIS   ((uint32_t)0x00000001)

#define HASH_SR_DCIS   ((uint32_t)0x00000002)

#define HASH_SR_DMAS   ((uint32_t)0x00000004)

#define HASH_SR_BUSY   ((uint32_t)0x00000008)

#define I2C_CR1_PE   ((uint16_t)0x0001)

Peripheral Enable

#define I2C_CR1_SMBUS   ((uint16_t)0x0002)

SMBus Mode

#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)

SMBus Type

#define I2C_CR1_ENARP   ((uint16_t)0x0010)

ARP Enable

#define I2C_CR1_ENPEC   ((uint16_t)0x0020)

PEC Enable

#define I2C_CR1_ENGC   ((uint16_t)0x0040)

General Call Enable

#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

#define I2C_CR1_START   ((uint16_t)0x0100)

Start Generation

#define I2C_CR1_STOP   ((uint16_t)0x0200)

Stop Generation

#define I2C_CR1_ACK   ((uint16_t)0x0400)

Acknowledge Enable

#define I2C_CR1_POS   ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

#define I2C_CR1_PEC   ((uint16_t)0x1000)

Packet Error Checking

#define I2C_CR1_ALERT   ((uint16_t)0x2000)

SMBus Alert

#define I2C_CR1_SWRST   ((uint16_t)0x8000)

Software Reset

#define I2C_CR2_FREQ   ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)

Bit 0

#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)

Bit 1

#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)

Bit 2

#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)

Bit 3

#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)

Bit 4

#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)

Bit 5

#define I2C_CR2_ITERREN   ((uint16_t)0x0100)

Error Interrupt Enable

#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)

Event Interrupt Enable

#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)

Buffer Interrupt Enable

#define I2C_CR2_DMAEN   ((uint16_t)0x0800)

DMA Requests Enable

#define I2C_CR2_LAST   ((uint16_t)0x1000)

DMA Last Transfer

#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)

Interface Address

#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)

Interface Address

#define I2C_OAR1_ADD0   ((uint16_t)0x0001)

Bit 0

#define I2C_OAR1_ADD1   ((uint16_t)0x0002)

Bit 1

#define I2C_OAR1_ADD2   ((uint16_t)0x0004)

Bit 2

#define I2C_OAR1_ADD3   ((uint16_t)0x0008)

Bit 3

#define I2C_OAR1_ADD4   ((uint16_t)0x0010)

Bit 4

#define I2C_OAR1_ADD5   ((uint16_t)0x0020)

Bit 5

#define I2C_OAR1_ADD6   ((uint16_t)0x0040)

Bit 6

#define I2C_OAR1_ADD7   ((uint16_t)0x0080)

Bit 7

#define I2C_OAR1_ADD8   ((uint16_t)0x0100)

Bit 8

#define I2C_OAR1_ADD9   ((uint16_t)0x0200)

Bit 9

#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)

Addressing Mode (Slave mode)

#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)

Dual addressing mode enable

#define I2C_OAR2_ADD2   ((uint8_t)0xFE)

Interface address

#define I2C_DR_DR   ((uint8_t)0xFF)

8-bit Data Register

#define I2C_SR1_SB   ((uint16_t)0x0001)

Start Bit (Master mode)

#define I2C_SR1_ADDR   ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

#define I2C_SR1_BTF   ((uint16_t)0x0004)

Byte Transfer Finished

#define I2C_SR1_ADD10   ((uint16_t)0x0008)

10-bit header sent (Master mode)

#define I2C_SR1_STOPF   ((uint16_t)0x0010)

Stop detection (Slave mode)

#define I2C_SR1_RXNE   ((uint16_t)0x0040)

Data Register not Empty (receivers)

#define I2C_SR1_TXE   ((uint16_t)0x0080)

Data Register Empty (transmitters)

#define I2C_SR1_BERR   ((uint16_t)0x0100)

Bus Error

#define I2C_SR1_ARLO   ((uint16_t)0x0200)

Arbitration Lost (master mode)

#define I2C_SR1_AF   ((uint16_t)0x0400)

Acknowledge Failure

#define I2C_SR1_OVR   ((uint16_t)0x0800)

Overrun/Underrun

#define I2C_SR1_PECERR   ((uint16_t)0x1000)

PEC Error in reception

#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)

Timeout or Tlow Error

#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)

SMBus Alert

#define I2C_SR2_MSL   ((uint16_t)0x0001)

Master/Slave

#define I2C_SR2_BUSY   ((uint16_t)0x0002)

Bus Busy

#define I2C_SR2_TRA   ((uint16_t)0x0004)

Transmitter/Receiver

#define I2C_SR2_GENCALL   ((uint16_t)0x0010)

General Call Address (Slave mode)

#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

#define I2C_SR2_DUALF   ((uint16_t)0x0080)

Dual Flag (Slave mode)

#define I2C_SR2_PEC   ((uint16_t)0xFF00)

Packet Error Checking Register

#define I2C_CCR_CCR   ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

#define I2C_CCR_DUTY   ((uint16_t)0x4000)

Fast Mode Duty Cycle

#define I2C_CCR_FS   ((uint16_t)0x8000)

I2C Master Mode Selection

#define I2C_TRISE_TRISE   ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

#define IWDG_KR_KEY   ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

#define IWDG_PR_PR   ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

#define IWDG_PR_PR_0   ((uint8_t)0x01)

Bit 0

#define IWDG_PR_PR_1   ((uint8_t)0x02)

Bit 1

#define IWDG_PR_PR_2   ((uint8_t)0x04)

Bit 2

#define IWDG_RLR_RL   ((uint16_t)0x0FFF)

Watchdog counter reload value

#define IWDG_SR_PVU   ((uint8_t)0x01)

Watchdog prescaler value update

#define IWDG_SR_RVU   ((uint8_t)0x02)

Watchdog counter reload value update

#define PWR_CR_LPDS   ((uint16_t)0x0001)

Low-Power Deepsleep

#define PWR_CR_PDDS   ((uint16_t)0x0002)

Power Down Deepsleep

#define PWR_CR_CWUF   ((uint16_t)0x0004)

Clear Wakeup Flag

#define PWR_CR_CSBF   ((uint16_t)0x0008)

Clear Standby Flag

#define PWR_CR_PVDE   ((uint16_t)0x0010)

Power Voltage Detector Enable

#define PWR_CR_PLS   ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

#define PWR_CR_PLS_0   ((uint16_t)0x0020)

Bit 0

#define PWR_CR_PLS_1   ((uint16_t)0x0040)

Bit 1

#define PWR_CR_PLS_2   ((uint16_t)0x0080)

Bit 2 PVD level configuration

#define PWR_CR_PLS_LEV0   ((uint16_t)0x0000)

PVD level 0

#define PWR_CR_PLS_LEV1   ((uint16_t)0x0020)

PVD level 1

#define PWR_CR_PLS_LEV2   ((uint16_t)0x0040)

PVD level 2

#define PWR_CR_PLS_LEV3   ((uint16_t)0x0060)

PVD level 3

#define PWR_CR_PLS_LEV4   ((uint16_t)0x0080)

PVD level 4

#define PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)

PVD level 5

#define PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)

PVD level 6

#define PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)

PVD level 7

#define PWR_CR_DBP   ((uint16_t)0x0100)

Disable Backup Domain write protection

#define PWR_CR_FPDS   ((uint16_t)0x0200)

Flash power down in Stop mode

#define PWR_CSR_WUF   ((uint16_t)0x0001)

Wakeup Flag

#define PWR_CSR_SBF   ((uint16_t)0x0002)

Standby Flag

#define PWR_CSR_PVDO   ((uint16_t)0x0004)

PVD Output

#define PWR_CSR_BRR   ((uint16_t)0x0008)

Backup regulator ready

#define PWR_CSR_EWUP   ((uint16_t)0x0100)

Enable WKUP pin

#define PWR_CSR_BRE   ((uint16_t)0x0200)

Backup regulator enable

#define RCC_CR_HSION   ((uint32_t)0x00000001)

#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)

#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)

#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)

Bit 0

#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)

Bit 1

#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)

Bit 2

#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)

Bit 3

#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)

Bit 4

#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)

#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100)

Bit 0

#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200)

Bit 1

#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400)

Bit 2

#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800)

Bit 3

#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000)

Bit 4

#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000)

Bit 5

#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000)

Bit 6

#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000)

Bit 7

#define RCC_CR_HSEON   ((uint32_t)0x00010000)

#define RCC_CR_HSERDY   ((uint32_t)0x00020000)

#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)

#define RCC_CR_CSSON   ((uint32_t)0x00080000)

#define RCC_CR_PLLON   ((uint32_t)0x01000000)

#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)

#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)

#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)

#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)

#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)

#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)

#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)

#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)

#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)

#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)

#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)

#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)

#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)

#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)

#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)

#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)

#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)

#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)

#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)

Referenced by RCC_GetClocksFreq(), and SystemCoreClockUpdate().

#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)

#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)

#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)

Referenced by RCC_GetClocksFreq(), SetPllClockSource(), and SystemCoreClockUpdate().

#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)

#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)

#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)

#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)

#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)

#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)

#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)

#define RCC_CFGR_SW   ((uint32_t)0x00000003)

< SW configuration SW[1:0] bits (System clock Switch)

#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)

Bit 0

#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)

Bit 1

#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)

HSI selected as system clock

#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)

HSE selected as system clock

#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)

PLL selected as system clock SWS configuration

#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)

Bit 0

#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)

Bit 1

#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)

HSI oscillator used as system clock

#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)

HSE oscillator used as system clock

#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)

PLL used as system clock HPRE configuration

#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)

Bit 0

#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)

Bit 1

#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)

Bit 2

#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)

Bit 3

#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)

SYSCLK not divided

#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)

SYSCLK divided by 2

#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)

SYSCLK divided by 4

#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)

SYSCLK divided by 8

#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)

SYSCLK divided by 16

#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)

SYSCLK divided by 64

#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)

SYSCLK divided by 128

#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)

SYSCLK divided by 256

#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)

SYSCLK divided by 512 PPRE1 configuration

#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)

PRE1[2:0] bits (APB1 prescaler)

#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)

Bit 0

#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)

Bit 1

#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)

Bit 2

#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)

HCLK divided by 2

#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)

HCLK divided by 4

#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)

HCLK divided by 8

#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)

HCLK divided by 16 PPRE2 configuration

#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)

PRE2[2:0] bits (APB2 prescaler)

#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)

Bit 0

#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)

Bit 1

#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)

Bit 2

#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)

HCLK divided by 2

#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)

HCLK divided by 4

#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)

HCLK divided by 8

#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E00)

HCLK divided by 16 RTCPRE configuration

#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)

Referenced by RCC_RTCCLKConfig().

#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)

#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)

#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)

#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)

#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)

MCO1 configuration

#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)

#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)

#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)

#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)

#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)

#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)

#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)

#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)

#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)

#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)

#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)

#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)

#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)

#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)

#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)

#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)

#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)

#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)

#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)

#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)

#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)

#define RCC_CIR_CSSF   ((uint32_t)0x00000080)

#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)

#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)

#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)

#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)

#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)

#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)

#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)

#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)

#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)

#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)

#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)

#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)

#define RCC_CIR_CSSC   ((uint32_t)0x00800000)

#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)

#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)

#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)

#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)

#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)

#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)

#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)

#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)

#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)

#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)

#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)

Referenced by DMA_Init().

#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)

Referenced by DMA_Init().

#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)

#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)

#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)

#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)

#define RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)

#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)

#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)

#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)

#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)

#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)

#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)

#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)

#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)

#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)

#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)

#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)

#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)

#define RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)

#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)

#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)

#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)

#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)

#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)

#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)

#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)

#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)

#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)

#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)

#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)

Referenced by Stm32CanHw2Init().

#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)

#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)

#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)

#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)

#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)

#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)

#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)

#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)

#define RCC_APB2RSTR_SPI1   ((uint32_t)0x00001000)

#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)

#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)

#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)

#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)

#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)

#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)

#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)

#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)

#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)

#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)

#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)

#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)

#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)

#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)

Referenced by CRC_Init().

#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)

#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)

Referenced by DMA_Init().

#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)

Referenced by DMA_Init().

#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)

#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)

#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)

#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)

#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)

#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)

#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)

#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)

#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)

#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)

#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)

Referenced by Set_USBClock().

#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)

#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)

#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)

#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)

#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)

#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)

#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)

#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)

#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)

#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)

#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)

#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)

#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)

#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)

#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)

#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)

#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)

#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)

#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)

#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)

#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)

#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)

Referenced by Stm32CanHw2Init().

#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)

#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)

#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)

#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)

#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)

#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)

#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)

#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)

#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)

#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)

#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)

#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)

Referenced by GpioPinConfigSet().

#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)

#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)

#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)

#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)

#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)

#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)

#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)

#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)

#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)

#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)

#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)

#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)

#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)

#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)

#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)

#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)

#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)

#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)

#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)

#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)

#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)

#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)

#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)

#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)

#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)

#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)

#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)

#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)

#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)

#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)

#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)

#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)

#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)

#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)

#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)

#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)

#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)

#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)

#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)

#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)

#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)

#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)

#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)

#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)

#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)

#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)

#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)

#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)

#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)

#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)

#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)

#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)

#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)

#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)

#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)

#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)

#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)

#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)

#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)

#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)

#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)

#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)

#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)

#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)

#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)

#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)

#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)

#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)

#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)

#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)

#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)

#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)

#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)

#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)

#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)

#define RCC_CSR_LSION   ((uint32_t)0x00000001)

#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)

#define RCC_CSR_RMVF   ((uint32_t)0x01000000)

#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)

#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)

#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)

#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)

#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)

#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)

#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)

#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)

#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)

#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)

#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)

#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)

#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)

#define RNG_CR_RNGEN   ((uint32_t)0x00000004)

#define RNG_CR_IE   ((uint32_t)0x00000008)

#define RNG_SR_DRDY   ((uint32_t)0x00000001)

#define RNG_SR_CECS   ((uint32_t)0x00000002)

#define RNG_SR_SECS   ((uint32_t)0x00000004)

#define RNG_SR_CEIS   ((uint32_t)0x00000020)

#define RNG_SR_SEIS   ((uint32_t)0x00000040)

#define RTC_TR_PM   ((uint32_t)0x00400000)

#define RTC_TR_HT   ((uint32_t)0x00300000)

#define RTC_TR_HT_0   ((uint32_t)0x00100000)

#define RTC_TR_HT_1   ((uint32_t)0x00200000)

#define RTC_TR_HU   ((uint32_t)0x000F0000)

#define RTC_TR_HU_0   ((uint32_t)0x00010000)

#define RTC_TR_HU_1   ((uint32_t)0x00020000)

#define RTC_TR_HU_2   ((uint32_t)0x00040000)

#define RTC_TR_HU_3   ((uint32_t)0x00080000)

#define RTC_TR_MNT   ((uint32_t)0x00007000)

#define RTC_TR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TR_MNU   ((uint32_t)0x00000F00)

#define RTC_TR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TR_ST   ((uint32_t)0x00000070)

#define RTC_TR_ST_0   ((uint32_t)0x00000010)

#define RTC_TR_ST_1   ((uint32_t)0x00000020)

#define RTC_TR_ST_2   ((uint32_t)0x00000040)

#define RTC_TR_SU   ((uint32_t)0x0000000F)

#define RTC_TR_SU_0   ((uint32_t)0x00000001)

#define RTC_TR_SU_1   ((uint32_t)0x00000002)

#define RTC_TR_SU_2   ((uint32_t)0x00000004)

#define RTC_TR_SU_3   ((uint32_t)0x00000008)

#define RTC_DR_YT   ((uint32_t)0x00F00000)

#define RTC_DR_YT_0   ((uint32_t)0x00100000)

#define RTC_DR_YT_1   ((uint32_t)0x00200000)

#define RTC_DR_YT_2   ((uint32_t)0x00400000)

#define RTC_DR_YT_3   ((uint32_t)0x00800000)

#define RTC_DR_YU   ((uint32_t)0x000F0000)

#define RTC_DR_YU_0   ((uint32_t)0x00010000)

#define RTC_DR_YU_1   ((uint32_t)0x00020000)

#define RTC_DR_YU_2   ((uint32_t)0x00040000)

#define RTC_DR_YU_3   ((uint32_t)0x00080000)

#define RTC_DR_WDU   ((uint32_t)0x0000E000)

#define RTC_DR_WDU_0   ((uint32_t)0x00002000)

#define RTC_DR_WDU_1   ((uint32_t)0x00004000)

#define RTC_DR_WDU_2   ((uint32_t)0x00008000)

#define RTC_DR_MT   ((uint32_t)0x00001000)

#define RTC_DR_MU   ((uint32_t)0x00000F00)

#define RTC_DR_MU_0   ((uint32_t)0x00000100)

#define RTC_DR_MU_1   ((uint32_t)0x00000200)

#define RTC_DR_MU_2   ((uint32_t)0x00000400)

#define RTC_DR_MU_3   ((uint32_t)0x00000800)

#define RTC_DR_DT   ((uint32_t)0x00000030)

#define RTC_DR_DT_0   ((uint32_t)0x00000010)

#define RTC_DR_DT_1   ((uint32_t)0x00000020)

#define RTC_DR_DU   ((uint32_t)0x0000000F)

#define RTC_DR_DU_0   ((uint32_t)0x00000001)

#define RTC_DR_DU_1   ((uint32_t)0x00000002)

#define RTC_DR_DU_2   ((uint32_t)0x00000004)

#define RTC_DR_DU_3   ((uint32_t)0x00000008)

#define RTC_CR_COE   ((uint32_t)0x00800000)

#define RTC_CR_OSEL   ((uint32_t)0x00600000)

#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)

#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)

#define RTC_CR_POL   ((uint32_t)0x00100000)

#define RTC_CR_BCK   ((uint32_t)0x00040000)

#define RTC_CR_SUB1H   ((uint32_t)0x00020000)

#define RTC_CR_ADD1H   ((uint32_t)0x00010000)

#define RTC_CR_TSIE   ((uint32_t)0x00008000)

#define RTC_CR_WUTIE   ((uint32_t)0x00004000)

#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)

#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)

#define RTC_CR_TSE   ((uint32_t)0x00000800)

#define RTC_CR_WUTE   ((uint32_t)0x00000400)

#define RTC_CR_ALRBE   ((uint32_t)0x00000200)

#define RTC_CR_ALRAE   ((uint32_t)0x00000100)

#define RTC_CR_DCE   ((uint32_t)0x00000080)

#define RTC_CR_FMT   ((uint32_t)0x00000040)

#define RTC_CR_REFCKON   ((uint32_t)0x00000010)

#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)

#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)

#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)

#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)

#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)

#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)

#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)

#define RTC_ISR_TSF   ((uint32_t)0x00000800)

#define RTC_ISR_WUTF   ((uint32_t)0x00000400)

#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)

#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)

#define RTC_ISR_INIT   ((uint32_t)0x00000080)

#define RTC_ISR_INITF   ((uint32_t)0x00000040)

#define RTC_ISR_RSF   ((uint32_t)0x00000020)

#define RTC_ISR_INITS   ((uint32_t)0x00000010)

#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)

#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)

#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)

#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)

#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)

#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)

#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)

#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)

#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)

#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)

#define RTC_WPR_KEY   ((uint32_t)0x000000FF)

#define RTC_TSTR_PM   ((uint32_t)0x00400000)

#define RTC_TSTR_HT   ((uint32_t)0x00300000)

#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)

#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)

#define RTC_TSTR_HU   ((uint32_t)0x000F0000)

#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)

#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)

#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)

#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)

#define RTC_TSTR_MNT   ((uint32_t)0x00007000)

#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)

#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TSTR_ST   ((uint32_t)0x00000070)

#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)

#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)

#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)

#define RTC_TSTR_SU   ((uint32_t)0x0000000F)

#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)

#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)

#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)

#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)

#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)

#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)

#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)

#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)

#define RTC_TSDR_MT   ((uint32_t)0x00001000)

#define RTC_TSDR_MU   ((uint32_t)0x00000F00)

#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)

#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)

#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)

#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)

#define RTC_TSDR_DT   ((uint32_t)0x00000030)

#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)

#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)

#define RTC_TSDR_DU   ((uint32_t)0x0000000F)

#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)

#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)

#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)

#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)

#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)

#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)

#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)

#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)

#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)

#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)

#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)

#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)

Bit 0

#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)

Bit 1

#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)

Clock divide factor

#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)

Clock enable bit

#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)

Power saving configuration bit

#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)

Clock divider bypass enable bit

#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)

Bit 0

#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)

Bit 1

#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)

HW Flow Control enable

#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)

Command argument

#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)

Command Index

#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)

Bit 0

#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)

Bit 1

#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)

SD I/O suspend command

#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)

Enable CMD completion

#define SDIO_CMD_NIEN   ((uint16_t)0x2000)

Not Interrupt Enable

#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)

CE-ATA command

#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)

Response command index

#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)

Data timeout period.

#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)

Data length value

#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)

Data transfer enabled bit

#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)

Data transfer direction selection

#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)

Data transfer mode selection

#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)

DMA enabled bit

#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)

Bit 0

#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)

Bit 1

#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)

Bit 2

#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)

Bit 3

#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)

Read wait start

#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)

Read wait stop

#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)

Read wait mode

#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)

SD I/O enable functions

#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)

Data count value

#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)

Command response received (CRC check failed)

#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)

Command response timeout

#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)

Data timeout

#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)

Transmit FIFO underrun error

#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)

Received FIFO overrun error

#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)

Command response received (CRC check passed)

#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)

Command sent (no response required)

#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)

Command transfer in progress

#define SDIO_STA_TXACT   ((uint32_t)0x00001000)

Data transmit in progress

#define SDIO_STA_RXACT   ((uint32_t)0x00002000)

Data receive in progress

#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)

Transmit FIFO full

#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)

Receive FIFO full

#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)

Transmit FIFO empty

#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)

Receive FIFO empty

#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)

Data available in transmit FIFO

#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)

Data available in receive FIFO

#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)

SDIO interrupt received

#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)

TXUNDERR flag clear bit

#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)

RXOVERR flag clear bit

#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)

CMDREND flag clear bit

#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)

CMDSENT flag clear bit

#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)

DATAEND flag clear bit

#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)

STBITERR flag clear bit

#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)

DBCKEND flag clear bit

#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)

SDIOIT flag clear bit

#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)

CEATAEND flag clear bit

#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)

Command Sent Interrupt Enable

#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)

Data End Interrupt Enable

#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)

Data Block End Interrupt Enable

#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)

CCommand Acting Interrupt Enable

#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)

Data receive acting interrupt enabled

#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

#define SPI_CR1_CPHA   ((uint16_t)0x0001)

Clock Phase

#define SPI_CR1_CPOL   ((uint16_t)0x0002)

Clock Polarity

#define SPI_CR1_MSTR   ((uint16_t)0x0004)

Master Selection

#define SPI_CR1_BR   ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

#define SPI_CR1_BR_0   ((uint16_t)0x0008)

Bit 0

#define SPI_CR1_BR_1   ((uint16_t)0x0010)

Bit 1

#define SPI_CR1_BR_2   ((uint16_t)0x0020)

Bit 2

#define SPI_CR1_SPE   ((uint16_t)0x0040)

SPI Enable

#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)

Frame Format

#define SPI_CR1_SSI   ((uint16_t)0x0100)

Internal slave select

#define SPI_CR1_SSM   ((uint16_t)0x0200)

Software slave management

#define SPI_CR1_RXONLY   ((uint16_t)0x0400)

Receive only

#define SPI_CR1_DFF   ((uint16_t)0x0800)

Data Frame Format

#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)

Transmit CRC next

#define SPI_CR1_CRCEN   ((uint16_t)0x2000)

Hardware CRC calculation enable

#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)

Output enable in bidirectional mode

#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)

Bidirectional data mode enable

#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)

Rx Buffer DMA Enable

#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)

Tx Buffer DMA Enable

#define SPI_CR2_SSOE   ((uint8_t)0x04)

SS Output Enable

#define SPI_CR2_ERRIE   ((uint8_t)0x20)

Error Interrupt Enable

#define SPI_CR2_RXNEIE   ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

#define SPI_CR2_TXEIE   ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

#define SPI_SR_RXNE   ((uint8_t)0x01)

Receive buffer Not Empty

#define SPI_SR_TXE   ((uint8_t)0x02)

Transmit buffer Empty

#define SPI_SR_CHSIDE   ((uint8_t)0x04)

Channel side

#define SPI_SR_UDR   ((uint8_t)0x08)

Underrun flag

#define SPI_SR_CRCERR   ((uint8_t)0x10)

CRC Error flag

#define SPI_SR_MODF   ((uint8_t)0x20)

Mode fault

#define SPI_SR_OVR   ((uint8_t)0x40)

Overrun flag

#define SPI_SR_BSY   ((uint8_t)0x80)

Busy flag

#define SPI_DR_DR   ((uint16_t)0xFFFF)

Data Register

#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)

CRC polynomial register

#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)

Rx CRC Register

#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)

Tx CRC Register

#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)

Bit 0

#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)

Bit 1

#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)

steady state clock polarity

#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)

Bit 0

#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)

Bit 1

#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)

PCM frame synchronization

#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)

Bit 0

#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)

Bit 1

#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)

I2S Enable

#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)

I2S mode selection

#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)

I2S Linear prescaler

#define SPI_I2SPR_ODD   ((uint16_t)0x0100)

Odd factor for the prescaler

#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)

Master Clock Output Enable

#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)

SYSCFG_Memory Remap Config

#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)

#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)

#define SYSCFG_PMC_MII_RMII   ((uint16_t)0x0080)

Ethernet PHY interface selection

#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)

EXTI 0 configuration

#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)

EXTI 1 configuration

#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)

EXTI 2 configuration

#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)

EXTI 3 configuration

#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)

EXTI0 configuration.

PA[0] pin

#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)

PB[0] pin

#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)

PC[0] pin

#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)

PD[0] pin

#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)

PE[0] pin

#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)

PF[0] pin

#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)

PG[0] pin

#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)

PH[0] pin

#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)

PI[0] pin

#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)

EXTI1 configuration.

PA[1] pin

#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)

PB[1] pin

#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)

PC[1] pin

#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)

PD[1] pin

#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)

PE[1] pin

#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)

PF[1] pin

#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)

PG[1] pin

#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)

PH[1] pin

#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)

PI[1] pin

#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)

EXTI2 configuration.

PA[2] pin

#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)

PB[2] pin

#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)

PC[2] pin

#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)

PD[2] pin

#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)

PE[2] pin

#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)

PF[2] pin

#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)

PG[2] pin

#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)

PH[2] pin

#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)

PI[2] pin

#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)

EXTI3 configuration.

PA[3] pin

#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)

PB[3] pin

#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)

PC[3] pin

#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)

PD[3] pin

#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)

PE[3] pin

#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)

PF[3] pin

#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)

PG[3] pin

#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)

PH[3] pin

#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)

PI[3] pin

#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)

EXTI 4 configuration

#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)

EXTI 5 configuration

#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)

EXTI 6 configuration

#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)

EXTI 7 configuration

#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)

EXTI4 configuration.

PA[4] pin

#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)

PB[4] pin

#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)

PC[4] pin

#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)

PD[4] pin

#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)

PE[4] pin

#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)

PF[4] pin

#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)

PG[4] pin

#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)

PH[4] pin

#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)

PI[4] pin

#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)

EXTI5 configuration.

PA[5] pin

#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)

PB[5] pin

#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)

PC[5] pin

#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)

PD[5] pin

#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)

PE[5] pin

#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)

PF[5] pin

#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)

PG[5] pin

#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)

PH[5] pin

#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)

PI[5] pin

#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)

EXTI6 configuration.

PA[6] pin

#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)

PB[6] pin

#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)

PC[6] pin

#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)

PD[6] pin

#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)

PE[6] pin

#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)

PF[6] pin

#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)

PG[6] pin

#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)

PH[6] pin

#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)

PI[6] pin

#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)

EXTI7 configuration.

PA[7] pin

#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)

PB[7] pin

#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)

PC[7] pin

#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)

PD[7] pin

#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)

PE[7] pin

#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)

PF[7] pin

#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)

PG[7] pin

#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)

PH[7] pin

#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)

PI[7] pin

#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)

EXTI 8 configuration

#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)

EXTI 9 configuration

#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)

EXTI 10 configuration

#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)

EXTI 11 configuration

#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)

EXTI8 configuration.

PA[8] pin

#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)

PB[8] pin

#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)

PC[8] pin

#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)

PD[8] pin

#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)

PE[8] pin

#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)

PF[8] pin

#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)

PG[8] pin

#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)

PH[8] pin

#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)

PI[8] pin

#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)

EXTI9 configuration.

PA[9] pin

#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)

PB[9] pin

#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)

PC[9] pin

#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)

PD[9] pin

#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)

PE[9] pin

#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)

PF[9] pin

#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)

PG[9] pin

#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)

PH[9] pin

#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)

PI[9] pin

#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)

EXTI10 configuration.

PA[10] pin

#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)

PB[10] pin

#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)

PC[10] pin

#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)

PD[10] pin

#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)

PE[10] pin

#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)

PF[10] pin

#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)

PG[10] pin

#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)

PH[10] pin

#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)

PI[10] pin

#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)

EXTI11 configuration.

PA[11] pin

#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)

PB[11] pin

#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)

PC[11] pin

#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)

PD[11] pin

#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)

PE[11] pin

#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)

PF[11] pin

#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)

PG[11] pin

#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)

PH[11] pin

#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)

PI[11] pin

#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)

EXTI 12 configuration

#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)

EXTI 13 configuration

#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)

EXTI 14 configuration

#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)

EXTI 15 configuration

#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)

EXTI12 configuration.

PA[12] pin

#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)

PB[12] pin

#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)

PC[12] pin

#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)

PD[12] pin

#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)

PE[12] pin

#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)

PF[12] pin

#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)

PG[12] pin

#define SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)

PH[12] pin

#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)

EXTI13 configuration.

PA[13] pin

#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)

PB[13] pin

#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)

PC[13] pin

#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)

PD[13] pin

#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)

PE[13] pin

#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)

PF[13] pin

#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)

PG[13] pin

#define SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)

PH[13] pin

#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)

EXTI14 configuration.

PA[14] pin

#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)

PB[14] pin

#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)

PC[14] pin

#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)

PD[14] pin

#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)

PE[14] pin

#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)

PF[14] pin

#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)

PG[14] pin

#define SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)

PH[14] pin

#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)

EXTI15 configuration.

PA[15] pin

#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)

PB[15] pin

#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)

PC[15] pin

#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)

PD[15] pin

#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)

PE[15] pin

#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)

PF[15] pin

#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)

PG[15] pin

#define SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)

PH[15] pin

#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)

Compensation cell ready flag

Referenced by GpioPinConfigSet().

#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)

Compensation cell power-down

#define TIM_CR1_CEN   ((uint16_t)0x0001)

Counter enable

#define TIM_CR1_UDIS   ((uint16_t)0x0002)

Update disable

#define TIM_CR1_URS   ((uint16_t)0x0004)

Update request source

#define TIM_CR1_OPM   ((uint16_t)0x0008)

One pulse mode

#define TIM_CR1_DIR   ((uint16_t)0x0010)

Direction

#define TIM_CR1_CMS   ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

#define TIM_CR1_CMS_0   ((uint16_t)0x0020)

Bit 0

#define TIM_CR1_CMS_1   ((uint16_t)0x0040)

Bit 1

#define TIM_CR1_ARPE   ((uint16_t)0x0080)

Auto-reload preload enable

#define TIM_CR1_CKD   ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

#define TIM_CR1_CKD_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CR1_CKD_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CR2_CCPC   ((uint16_t)0x0001)

Capture/Compare Preloaded Control

#define TIM_CR2_CCUS   ((uint16_t)0x0004)

Capture/Compare Control Update Selection

#define TIM_CR2_CCDS   ((uint16_t)0x0008)

Capture/Compare DMA Selection

#define TIM_CR2_MMS   ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

#define TIM_CR2_MMS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CR2_MMS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CR2_MMS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CR2_TI1S   ((uint16_t)0x0080)

TI1 Selection

#define TIM_CR2_OIS1   ((uint16_t)0x0100)

Output Idle state 1 (OC1 output)

#define TIM_CR2_OIS1N   ((uint16_t)0x0200)

Output Idle state 1 (OC1N output)

#define TIM_CR2_OIS2   ((uint16_t)0x0400)

Output Idle state 2 (OC2 output)

#define TIM_CR2_OIS2N   ((uint16_t)0x0800)

Output Idle state 2 (OC2N output)

#define TIM_CR2_OIS3   ((uint16_t)0x1000)

Output Idle state 3 (OC3 output)

#define TIM_CR2_OIS3N   ((uint16_t)0x2000)

Output Idle state 3 (OC3N output)

#define TIM_CR2_OIS4   ((uint16_t)0x4000)

Output Idle state 4 (OC4 output)

#define TIM_SMCR_SMS   ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)

Bit 0

#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)

Bit 1

#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)

Bit 2

#define TIM_SMCR_TS   ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

#define TIM_SMCR_TS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_SMCR_TS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_SMCR_TS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_SMCR_MSM   ((uint16_t)0x0080)

Master/slave mode

#define TIM_SMCR_ETF   ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)

Bit 0

#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)

Bit 1

#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)

Bit 2

#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)

Bit 3

#define TIM_SMCR_ETPS   ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)

Bit 0

#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)

Bit 1

#define TIM_SMCR_ECE   ((uint16_t)0x4000)

External clock enable

#define TIM_SMCR_ETP   ((uint16_t)0x8000)

External trigger polarity

#define TIM_DIER_UIE   ((uint16_t)0x0001)

Update interrupt enable

#define TIM_DIER_CC1IE   ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

#define TIM_DIER_CC2IE   ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

#define TIM_DIER_CC3IE   ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

#define TIM_DIER_CC4IE   ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

#define TIM_DIER_COMIE   ((uint16_t)0x0020)

COM interrupt enable

#define TIM_DIER_TIE   ((uint16_t)0x0040)

Trigger interrupt enable

#define TIM_DIER_BIE   ((uint16_t)0x0080)

Break interrupt enable

#define TIM_DIER_UDE   ((uint16_t)0x0100)

Update DMA request enable

#define TIM_DIER_CC1DE   ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

#define TIM_DIER_CC2DE   ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

#define TIM_DIER_CC3DE   ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

#define TIM_DIER_CC4DE   ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

#define TIM_DIER_COMDE   ((uint16_t)0x2000)

COM DMA request enable

#define TIM_DIER_TDE   ((uint16_t)0x4000)

Trigger DMA request enable

#define TIM_SR_UIF   ((uint16_t)0x0001)

Update interrupt Flag

#define TIM_SR_CC1IF   ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

#define TIM_SR_CC2IF   ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

#define TIM_SR_CC3IF   ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

#define TIM_SR_CC4IF   ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

#define TIM_SR_COMIF   ((uint16_t)0x0020)

COM interrupt Flag

#define TIM_SR_TIF   ((uint16_t)0x0040)

Trigger interrupt Flag

#define TIM_SR_BIF   ((uint16_t)0x0080)

Break interrupt Flag

#define TIM_SR_CC1OF   ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

#define TIM_SR_CC2OF   ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

#define TIM_SR_CC3OF   ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

#define TIM_SR_CC4OF   ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

#define TIM_EGR_UG   ((uint8_t)0x01)

Update Generation

#define TIM_EGR_CC1G   ((uint8_t)0x02)

Capture/Compare 1 Generation

#define TIM_EGR_CC2G   ((uint8_t)0x04)

Capture/Compare 2 Generation

#define TIM_EGR_CC3G   ((uint8_t)0x08)

Capture/Compare 3 Generation

#define TIM_EGR_CC4G   ((uint8_t)0x10)

Capture/Compare 4 Generation

#define TIM_EGR_COMG   ((uint8_t)0x20)

Capture/Compare Control Update Generation

#define TIM_EGR_TG   ((uint8_t)0x40)

Trigger Generation

#define TIM_EGR_BG   ((uint8_t)0x80)

Break Generation

#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)

Output Compare 1 Fast enable

#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)

Output Compare 1 Preload enable

#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)

Output Compare 1Clear Enable

#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)

Output Compare 2 Fast enable

#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)

Output Compare 2 Preload enable

#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)

Output Compare 2 Clear Enable

#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)

Output Compare 3 Fast enable

#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)

Output Compare 3 Preload enable

#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)

Output Compare 3 Clear Enable

#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)

Output Compare 4 Fast enable

#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)

Output Compare 4 Preload enable

#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)

Output Compare 4 Clear Enable

#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCER_CC1E   ((uint16_t)0x0001)

Capture/Compare 1 output enable

#define TIM_CCER_CC1P   ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

#define TIM_CCER_CC1NE   ((uint16_t)0x0004)

Capture/Compare 1 Complementary output enable

#define TIM_CCER_CC1NP   ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

#define TIM_CCER_CC2E   ((uint16_t)0x0010)

Capture/Compare 2 output enable

#define TIM_CCER_CC2P   ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

#define TIM_CCER_CC2NE   ((uint16_t)0x0040)

Capture/Compare 2 Complementary output enable

#define TIM_CCER_CC2NP   ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

#define TIM_CCER_CC3E   ((uint16_t)0x0100)

Capture/Compare 3 output enable

#define TIM_CCER_CC3P   ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

#define TIM_CCER_CC3NE   ((uint16_t)0x0400)

Capture/Compare 3 Complementary output enable

#define TIM_CCER_CC3NP   ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

#define TIM_CCER_CC4E   ((uint16_t)0x1000)

Capture/Compare 4 output enable

#define TIM_CCER_CC4P   ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

#define TIM_CCER_CC4NP   ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

#define TIM_CNT_CNT   ((uint16_t)0xFFFF)

Counter Value

#define TIM_PSC_PSC   ((uint16_t)0xFFFF)

Prescaler Value

#define TIM_ARR_ARR   ((uint16_t)0xFFFF)

actual auto-reload Value

#define TIM_RCR_REP   ((uint8_t)0xFF)

Repetition Counter Value

#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)

Capture/Compare 1 Value

#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)

Capture/Compare 2 Value

#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)

Capture/Compare 3 Value

#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)

Capture/Compare 4 Value

#define TIM_BDTR_DTG   ((uint16_t)0x00FF)

DTG[0:7] bits (Dead-Time Generator set-up)

#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)

Bit 0

#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)

Bit 1

#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)

Bit 2

#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)

Bit 3

#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)

Bit 4

#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)

Bit 5

#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)

Bit 6

#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)

Bit 7

#define TIM_BDTR_LOCK   ((uint16_t)0x0300)

LOCK[1:0] bits (Lock Configuration)

#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)

Bit 0

#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)

Bit 1

#define TIM_BDTR_OSSI   ((uint16_t)0x0400)

Off-State Selection for Idle mode

#define TIM_BDTR_OSSR   ((uint16_t)0x0800)

Off-State Selection for Run mode

#define TIM_BDTR_BKE   ((uint16_t)0x1000)

Break enable

#define TIM_BDTR_BKP   ((uint16_t)0x2000)

Break Polarity

#define TIM_BDTR_AOE   ((uint16_t)0x4000)

Automatic Output enable

#define TIM_BDTR_MOE   ((uint16_t)0x8000)

Main Output enable

#define TIM_DCR_DBA   ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

#define TIM_DCR_DBA_0   ((uint16_t)0x0001)

Bit 0

#define TIM_DCR_DBA_1   ((uint16_t)0x0002)

Bit 1

#define TIM_DCR_DBA_2   ((uint16_t)0x0004)

Bit 2

#define TIM_DCR_DBA_3   ((uint16_t)0x0008)

Bit 3

#define TIM_DCR_DBA_4   ((uint16_t)0x0010)

Bit 4

#define TIM_DCR_DBL   ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

#define TIM_DCR_DBL_0   ((uint16_t)0x0100)

Bit 0

#define TIM_DCR_DBL_1   ((uint16_t)0x0200)

Bit 1

#define TIM_DCR_DBL_2   ((uint16_t)0x0400)

Bit 2

#define TIM_DCR_DBL_3   ((uint16_t)0x0800)

Bit 3

#define TIM_DCR_DBL_4   ((uint16_t)0x1000)

Bit 4

#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)

DMA register for burst accesses

#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)

Bit 0

#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)

Bit 1

#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)

Bit 0

#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)

Bit 1

#define USART_SR_PE   ((uint16_t)0x0001)

Parity Error

#define USART_SR_FE   ((uint16_t)0x0002)

Framing Error

#define USART_SR_NE   ((uint16_t)0x0004)

Noise Error Flag

#define USART_SR_ORE   ((uint16_t)0x0008)

OverRun Error

#define USART_SR_IDLE   ((uint16_t)0x0010)

IDLE line detected

#define USART_SR_RXNE   ((uint16_t)0x0020)

Read Data Register Not Empty

#define USART_SR_TC   ((uint16_t)0x0040)

Transmission Complete

#define USART_SR_TXE   ((uint16_t)0x0080)

Transmit Data Register Empty

#define USART_SR_LBD   ((uint16_t)0x0100)

LIN Break Detection Flag

#define USART_SR_CTS   ((uint16_t)0x0200)

CTS Flag

#define USART_DR_DR   ((uint16_t)0x01FF)

Data value

#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)

Fraction of USARTDIV

#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)

Mantissa of USARTDIV

#define USART_CR1_SBK   ((uint16_t)0x0001)

Send Break

#define USART_CR1_RWU   ((uint16_t)0x0002)

Receiver wakeup

#define USART_CR1_RE   ((uint16_t)0x0004)

Receiver Enable

#define USART_CR1_TE   ((uint16_t)0x0008)

Transmitter Enable

#define USART_CR1_IDLEIE   ((uint16_t)0x0010)

IDLE Interrupt Enable

#define USART_CR1_RXNEIE   ((uint16_t)0x0020)

RXNE Interrupt Enable

#define USART_CR1_TCIE   ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

#define USART_CR1_TXEIE   ((uint16_t)0x0080)

PE Interrupt Enable

#define USART_CR1_PEIE   ((uint16_t)0x0100)

PE Interrupt Enable

#define USART_CR1_PS   ((uint16_t)0x0200)

Parity Selection

#define USART_CR1_PCE   ((uint16_t)0x0400)

Parity Control Enable

#define USART_CR1_WAKE   ((uint16_t)0x0800)

Wakeup method

#define USART_CR1_M   ((uint16_t)0x1000)

Word length

#define USART_CR1_UE   ((uint16_t)0x2000)

USART Enable

#define USART_CR1_OVER8   ((uint16_t)0x8000)

USART Oversampling by 8 enable

#define USART_CR2_ADD   ((uint16_t)0x000F)

Address of the USART node

#define USART_CR2_LBDL   ((uint16_t)0x0020)

LIN Break Detection Length

#define USART_CR2_LBDIE   ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

#define USART_CR2_LBCL   ((uint16_t)0x0100)

Last Bit Clock pulse

#define USART_CR2_CPHA   ((uint16_t)0x0200)

Clock Phase

#define USART_CR2_CPOL   ((uint16_t)0x0400)

Clock Polarity

#define USART_CR2_CLKEN   ((uint16_t)0x0800)

Clock Enable

#define USART_CR2_STOP   ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

#define USART_CR2_STOP_0   ((uint16_t)0x1000)

Bit 0

#define USART_CR2_STOP_1   ((uint16_t)0x2000)

Bit 1

#define USART_CR2_LINEN   ((uint16_t)0x4000)

LIN mode enable

#define USART_CR3_EIE   ((uint16_t)0x0001)

Error Interrupt Enable

#define USART_CR3_IREN   ((uint16_t)0x0002)

IrDA mode Enable

#define USART_CR3_IRLP   ((uint16_t)0x0004)

IrDA Low-Power

#define USART_CR3_HDSEL   ((uint16_t)0x0008)

Half-Duplex Selection

#define USART_CR3_NACK   ((uint16_t)0x0010)

Smartcard NACK enable

#define USART_CR3_SCEN   ((uint16_t)0x0020)

Smartcard mode enable

#define USART_CR3_DMAR   ((uint16_t)0x0040)

DMA Enable Receiver

#define USART_CR3_DMAT   ((uint16_t)0x0080)

DMA Enable Transmitter

#define USART_CR3_RTSE   ((uint16_t)0x0100)

RTS Enable

#define USART_CR3_CTSE   ((uint16_t)0x0200)

CTS Enable

#define USART_CR3_CTSIE   ((uint16_t)0x0400)

CTS Interrupt Enable

#define USART_CR3_ONEBIT   ((uint16_t)0x0800)

USART One bit method enable

#define USART_GTPR_PSC   ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

#define USART_GTPR_PSC_0   ((uint16_t)0x0001)

Bit 0

#define USART_GTPR_PSC_1   ((uint16_t)0x0002)

Bit 1

#define USART_GTPR_PSC_2   ((uint16_t)0x0004)

Bit 2

#define USART_GTPR_PSC_3   ((uint16_t)0x0008)

Bit 3

#define USART_GTPR_PSC_4   ((uint16_t)0x0010)

Bit 4

#define USART_GTPR_PSC_5   ((uint16_t)0x0020)

Bit 5

#define USART_GTPR_PSC_6   ((uint16_t)0x0040)

Bit 6

#define USART_GTPR_PSC_7   ((uint16_t)0x0080)

Bit 7

#define USART_GTPR_GT   ((uint16_t)0xFF00)

Guard time value

#define WWDG_CR_T   ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

#define WWDG_CR_T0   ((uint8_t)0x01)

Bit 0

#define WWDG_CR_T1   ((uint8_t)0x02)

Bit 1

#define WWDG_CR_T2   ((uint8_t)0x04)

Bit 2

#define WWDG_CR_T3   ((uint8_t)0x08)

Bit 3

#define WWDG_CR_T4   ((uint8_t)0x10)

Bit 4

#define WWDG_CR_T5   ((uint8_t)0x20)

Bit 5

#define WWDG_CR_T6   ((uint8_t)0x40)

Bit 6

#define WWDG_CR_WDGA   ((uint8_t)0x80)

Activation bit

#define WWDG_CFR_W   ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

#define WWDG_CFR_W0   ((uint16_t)0x0001)

Bit 0

#define WWDG_CFR_W1   ((uint16_t)0x0002)

Bit 1

#define WWDG_CFR_W2   ((uint16_t)0x0004)

Bit 2

#define WWDG_CFR_W3   ((uint16_t)0x0008)

Bit 3

#define WWDG_CFR_W4   ((uint16_t)0x0010)

Bit 4

#define WWDG_CFR_W5   ((uint16_t)0x0020)

Bit 5

#define WWDG_CFR_W6   ((uint16_t)0x0040)

Bit 6

#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)

Bit 0

#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)

Bit 1

#define WWDG_CFR_EWI   ((uint16_t)0x0200)

Early Wakeup Interrupt

#define WWDG_SR_EWIF   ((uint8_t)0x01)

Early Wakeup Interrupt Flag

#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)

#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)

#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)

#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)

#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)

#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)

#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)

#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)

Bit 0

#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)

Bit 1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)

#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   ((uint32_t)0x00001000)

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)

#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)

#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)

#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)

#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)

#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)

#define ETH_MACCR_WD   ((uint32_t)0x00800000)

#define ETH_MACCR_JD   ((uint32_t)0x00400000)

#define ETH_MACCR_IFG   ((uint32_t)0x000E0000)

#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000)

#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000)

#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000)

#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000)

#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000)

#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000)

#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000)

#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000)

#define ETH_MACCR_CSD   ((uint32_t)0x00010000)

#define ETH_MACCR_FES   ((uint32_t)0x00004000)

#define ETH_MACCR_ROD   ((uint32_t)0x00002000)

#define ETH_MACCR_LM   ((uint32_t)0x00001000)

#define ETH_MACCR_DM   ((uint32_t)0x00000800)

#define ETH_MACCR_IPCO   ((uint32_t)0x00000400)

#define ETH_MACCR_RD   ((uint32_t)0x00000200)

#define ETH_MACCR_APCS   ((uint32_t)0x00000080)

#define ETH_MACCR_BL   ((uint32_t)0x00000060)

#define ETH_MACCR_BL_10   ((uint32_t)0x00000000)

#define ETH_MACCR_BL_8   ((uint32_t)0x00000020)

#define ETH_MACCR_BL_4   ((uint32_t)0x00000040)

#define ETH_MACCR_BL_1   ((uint32_t)0x00000060)

#define ETH_MACCR_DC   ((uint32_t)0x00000010)

#define ETH_MACCR_TE   ((uint32_t)0x00000008)

#define ETH_MACCR_RE   ((uint32_t)0x00000004)

#define ETH_MACFFR_RA   ((uint32_t)0x80000000)

#define ETH_MACFFR_HPF   ((uint32_t)0x00000400)

#define ETH_MACFFR_SAF   ((uint32_t)0x00000200)

#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)

#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0)

#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040)

#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080)

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0)

#define ETH_MACFFR_BFD   ((uint32_t)0x00000020)

#define ETH_MACFFR_PAM   ((uint32_t)0x00000010)

#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)

#define ETH_MACFFR_HM   ((uint32_t)0x00000004)

#define ETH_MACFFR_HU   ((uint32_t)0x00000002)

#define ETH_MACFFR_PM   ((uint32_t)0x00000001)

#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)

#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)

#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)

#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)

#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)

#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)

#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)

#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)

#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)

#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)

#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)

#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)

#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000)

#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)

#define ETH_MACFCR_PLT   ((uint32_t)0x00000030)

#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)

#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010)

#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020)

#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030)

#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)

#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)

#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)

#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001)

#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000)

#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF)

#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)

#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000)

#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200)

#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040)

#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020)

#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004)

#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002)

#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001)

#define ETH_MACSR_TSTS   ((uint32_t)0x00000200)

#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040)

#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020)

#define ETH_MACSR_MMCS   ((uint32_t)0x00000010)

#define ETH_MACSR_PMTS   ((uint32_t)0x00000008)

#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200)

#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008)

#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)

#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA1HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA1HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)

#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA2HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA2HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)

#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA3HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA3HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)

#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020)

#define ETH_MMCCR_MCP   ((uint32_t)0x00000010)

#define ETH_MMCCR_MCF   ((uint32_t)0x00000008)

#define ETH_MMCCR_ROR   ((uint32_t)0x00000004)

#define ETH_MMCCR_CSR   ((uint32_t)0x00000002)

#define ETH_MMCCR_CR   ((uint32_t)0x00000001)

#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000)

#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040)

#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020)

#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000)

#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)

#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000)

#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000)

#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040)

#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020)

#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000)

#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000)

#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)

#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000)

#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000)

#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000)

#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)

#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)

#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800)

#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400)

#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200)

#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100)

#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020)

#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010)

#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008)

#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004)

#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002)

#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001)

#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF)

#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000)

#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF)

#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000)

#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)

#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020)

#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010)

#define ETH_DMABMR_AAB   ((uint32_t)0x02000000)

#define ETH_DMABMR_FPM   ((uint32_t)0x01000000)

#define ETH_DMABMR_USP   ((uint32_t)0x00800000)

#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000)

#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000)

#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000)

#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000)

#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000)

#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)

#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)

#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)

#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)

#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000)

#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000)

#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000)

#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000)

#define ETH_DMABMR_FB   ((uint32_t)0x00010000)

#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000)

#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000)

#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000)

#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000)

#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000)

#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00)

#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100)

#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200)

#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400)

#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800)

#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)

#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)

#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)

#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)

#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400)

#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800)

#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000)

#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000)

#define ETH_DMABMR_EDE   ((uint32_t)0x00000080)

#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C)

#define ETH_DMABMR_DA   ((uint32_t)0x00000002)

#define ETH_DMABMR_SR   ((uint32_t)0x00000001)

#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF)

#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF)

#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF)

#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF)

#define ETH_DMASR_TSTS   ((uint32_t)0x20000000)

#define ETH_DMASR_PMTS   ((uint32_t)0x10000000)

#define ETH_DMASR_MMCS   ((uint32_t)0x08000000)

#define ETH_DMASR_EBS   ((uint32_t)0x03800000)

#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000)

#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000)

#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000)

#define ETH_DMASR_TPS   ((uint32_t)0x00700000)

#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000)

#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000)

#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000)

#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000)

#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000)

#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000)

#define ETH_DMASR_RPS   ((uint32_t)0x000E0000)

#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000)

#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000)

#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000)

#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000)

#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000)

#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000)

#define ETH_DMASR_NIS   ((uint32_t)0x00010000)

#define ETH_DMASR_AIS   ((uint32_t)0x00008000)

#define ETH_DMASR_ERS   ((uint32_t)0x00004000)

#define ETH_DMASR_FBES   ((uint32_t)0x00002000)

#define ETH_DMASR_ETS   ((uint32_t)0x00000400)

#define ETH_DMASR_RWTS   ((uint32_t)0x00000200)

#define ETH_DMASR_RPSS   ((uint32_t)0x00000100)

#define ETH_DMASR_RBUS   ((uint32_t)0x00000080)

#define ETH_DMASR_RS   ((uint32_t)0x00000040)

#define ETH_DMASR_TUS   ((uint32_t)0x00000020)

#define ETH_DMASR_ROS   ((uint32_t)0x00000010)

#define ETH_DMASR_TJTS   ((uint32_t)0x00000008)

#define ETH_DMASR_TBUS   ((uint32_t)0x00000004)

#define ETH_DMASR_TPSS   ((uint32_t)0x00000002)

#define ETH_DMASR_TS   ((uint32_t)0x00000001)

#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000)

#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000)

#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000)

#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000)

#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000)

#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000)

#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000)

#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000)

#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000)

#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000)

#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000)

#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000)

#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000)

#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000)

#define ETH_DMAOMR_ST   ((uint32_t)0x00002000)

#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080)

#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040)

#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018)

#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000)

#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008)

#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010)

#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018)

#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004)

#define ETH_DMAOMR_SR   ((uint32_t)0x00000002)

#define ETH_DMAIER_NISE   ((uint32_t)0x00010000)

#define ETH_DMAIER_AISE   ((uint32_t)0x00008000)

#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000)

#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000)

#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400)

#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200)

#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100)

#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080)

#define ETH_DMAIER_RIE   ((uint32_t)0x00000040)

#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020)

#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010)

#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008)

#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004)

#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002)

#define ETH_DMAIER_TIE   ((uint32_t)0x00000001)

#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)

#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000)

#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)

#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF)

#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF)

#define ADC_SR_AWD   ((uint8_t)0x01)

Analog watchdog flag

#define ADC_SR_EOC   ((uint8_t)0x02)

End of conversion

#define ADC_SR_JEOC   ((uint8_t)0x04)

Injected channel end of conversion

#define ADC_SR_JSTRT   ((uint8_t)0x08)

Injected channel Start flag

#define ADC_SR_STRT   ((uint8_t)0x10)

Regular channel Start flag

#define ADC_SR_OVR   ((uint8_t)0x20)

Overrun flag

#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)

Interrupt enable for EOC

#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)

AAnalog Watchdog interrupt enable

#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)

Interrupt enable for injected channels

#define ADC_CR1_SCAN   ((uint32_t)0x00000100)

Scan mode

#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)

Automatic injected group conversion

#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)

Discontinuous mode on regular channels

#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)

Discontinuous mode on injected channels

#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)

Bit 0

#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)

Bit 1

#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)

Bit 2

#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

#define ADC_CR1_RES   ((uint32_t)0x03000000)

RES[2:0] bits (Resolution)

#define ADC_CR1_RES_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR1_RES_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)

overrun interrupt enable

#define ADC_CR2_ADON   ((uint32_t)0x00000001)

A/D Converter ON / OFF

#define ADC_CR2_CONT   ((uint32_t)0x00000002)

Continuous Conversion

#define ADC_CR2_DMA   ((uint32_t)0x00000100)

Direct Memory access mode

#define ADC_CR2_DDS   ((uint32_t)0x00000200)

DMA disable selection (Single ADC)

#define ADC_CR2_EOCS   ((uint32_t)0x00000400)

End of conversion selection

#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)

Data Alignment

#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)

JEXTSEL[3:0] bits (External event select for injected group)

#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)

Bit 2

#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)

Bit 3

#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)

Start Conversion of injected channels

#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)

EXTSEL[3:0] bits (External Event Select for regular group)

#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)

Bit 3

#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)

Bit 0

#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)

Bit 1

#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)

Start Conversion of regular channels

#define ADC_SMPR1_SMP10   ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

#define ADC_SMPR1_SMP10_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR1_SMP10_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR1_SMP10_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR1_SMP11   ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

#define ADC_SMPR1_SMP11_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR1_SMP11_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR1_SMP11_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR1_SMP12   ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

#define ADC_SMPR1_SMP12_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR1_SMP12_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR1_SMP12_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR1_SMP13   ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

#define ADC_SMPR1_SMP13_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR1_SMP13_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR1_SMP13_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR1_SMP14   ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

#define ADC_SMPR1_SMP14_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR1_SMP14_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR1_SMP14_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR1_SMP15   ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 15 Sample time selection)

#define ADC_SMPR1_SMP15_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR1_SMP15_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR1_SMP15_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR1_SMP16   ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

#define ADC_SMPR1_SMP16_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR1_SMP16_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR1_SMP16_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR1_SMP17   ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

#define ADC_SMPR1_SMP17_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR1_SMP17_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR1_SMP17_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR1_SMP18   ((uint32_t)0x07000000)

SMP18[2:0] bits (Channel 18 Sample time selection)

#define ADC_SMPR1_SMP18_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR1_SMP18_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR1_SMP18_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP0   ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

#define ADC_SMPR2_SMP0_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR2_SMP0_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR2_SMP0_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR2_SMP1   ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

#define ADC_SMPR2_SMP1_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR2_SMP1_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR2_SMP1_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR2_SMP2   ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

#define ADC_SMPR2_SMP2_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR2_SMP2_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR2_SMP2_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR2_SMP3   ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

#define ADC_SMPR2_SMP3_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR2_SMP3_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR2_SMP3_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR2_SMP4   ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

#define ADC_SMPR2_SMP4_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR2_SMP4_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR2_SMP4_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR2_SMP5   ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR2_SMP5_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR2_SMP5_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR2_SMP5_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR2_SMP6   ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

#define ADC_SMPR2_SMP6_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR2_SMP6_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR2_SMP6_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR2_SMP7   ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

#define ADC_SMPR2_SMP7_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR2_SMP7_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR2_SMP7_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR2_SMP8   ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

#define ADC_SMPR2_SMP8_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR2_SMP8_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR2_SMP8_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP9   ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

#define ADC_SMPR2_SMP9_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR2_SMP9_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR2_SMP9_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_JOFR1_JOFFSET1   ((uint16_t)0x0FFF)

Data offset for injected channel 1

#define ADC_JOFR2_JOFFSET2   ((uint16_t)0x0FFF)

Data offset for injected channel 2

#define ADC_JOFR3_JOFFSET3   ((uint16_t)0x0FFF)

Data offset for injected channel 3

#define ADC_JOFR4_JOFFSET4   ((uint16_t)0x0FFF)

Data offset for injected channel 4

#define ADC_HTR_HT   ((uint16_t)0x0FFF)

Analog watchdog high threshold

#define ADC_LTR_LT   ((uint16_t)0x0FFF)

Analog watchdog low threshold

#define ADC_SQR1_SQ13   ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

#define ADC_SQR1_SQ13_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR1_SQ13_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR1_SQ13_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR1_SQ13_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR1_SQ13_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR1_SQ14   ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

#define ADC_SQR1_SQ14_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR1_SQ14_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR1_SQ14_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR1_SQ14_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR1_SQ14_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR1_SQ15   ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

#define ADC_SQR1_SQ15_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR1_SQ15_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR1_SQ15_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR1_SQ15_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR1_SQ15_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR1_SQ16   ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

#define ADC_SQR1_SQ16_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR1_SQ16_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR1_SQ16_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR1_SQ16_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR1_SQ16_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR1_L   ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

#define ADC_SQR1_L_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR1_L_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR1_L_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR1_L_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ7   ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

#define ADC_SQR2_SQ7_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR2_SQ7_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR2_SQ7_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR2_SQ7_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR2_SQ7_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR2_SQ8   ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

#define ADC_SQR2_SQ8_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR2_SQ8_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR2_SQ8_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR2_SQ8_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR2_SQ8_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR2_SQ9   ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

#define ADC_SQR2_SQ9_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR2_SQ9_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR2_SQ9_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR2_SQ9_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR2_SQ9_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR2_SQ10   ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

#define ADC_SQR2_SQ10_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR2_SQ10_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR2_SQ10_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR2_SQ10_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR2_SQ10_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR2_SQ11   ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

#define ADC_SQR2_SQ11_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR2_SQ11_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR2_SQ11_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR2_SQ11_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ11_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR2_SQ12   ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

#define ADC_SQR2_SQ12_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR2_SQ12_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR2_SQ12_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR2_SQ12_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR2_SQ12_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR3_SQ1   ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

#define ADC_SQR3_SQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR3_SQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR3_SQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR3_SQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR3_SQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR3_SQ2   ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

#define ADC_SQR3_SQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR3_SQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR3_SQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR3_SQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR3_SQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR3_SQ3   ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

#define ADC_SQR3_SQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR3_SQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR3_SQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR3_SQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR3_SQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR3_SQ4   ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

#define ADC_SQR3_SQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR3_SQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR3_SQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR3_SQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR3_SQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR3_SQ5   ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

#define ADC_SQR3_SQ5_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR3_SQ5_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR3_SQ5_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR3_SQ5_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR3_SQ5_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR3_SQ6   ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

#define ADC_SQR3_SQ6_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR3_SQ6_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR3_SQ6_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR3_SQ6_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR3_SQ6_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_JSQR_JL   ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_JDR1_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR2_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR3_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_JDR4_JDATA   ((uint16_t)0xFFFF)

Injected data

#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)

Regular data

#define ADC_DR_ADC2DATA   ((uint32_t)0xFFFF0000)

ADC2 data

#define ADC_CSR_AWD1   ((uint32_t)0x00000001)

ADC1 Analog watchdog flag

#define ADC_CSR_EOC1   ((uint32_t)0x00000002)

ADC1 End of conversion

#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)

ADC1 Injected channel end of conversion

#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)

ADC1 Injected channel Start flag

#define ADC_CSR_STRT1   ((uint32_t)0x00000010)

ADC1 Regular channel Start flag

#define ADC_CSR_DOVR1   ((uint32_t)0x00000020)

ADC1 DMA overrun flag

#define ADC_CSR_AWD2   ((uint32_t)0x00000100)

ADC2 Analog watchdog flag

#define ADC_CSR_EOC2   ((uint32_t)0x00000200)

ADC2 End of conversion

#define ADC_CSR_JEOC2   ((uint32_t)0x00000400)

ADC2 Injected channel end of conversion

#define ADC_CSR_JSTRT2   ((uint32_t)0x00000800)

ADC2 Injected channel Start flag

#define ADC_CSR_STRT2   ((uint32_t)0x00001000)

ADC2 Regular channel Start flag

#define ADC_CSR_DOVR2   ((uint32_t)0x00002000)

ADC2 DMA overrun flag

#define ADC_CSR_AWD3   ((uint32_t)0x00010000)

ADC3 Analog watchdog flag

#define ADC_CSR_EOC3   ((uint32_t)0x00020000)

ADC3 End of conversion

#define ADC_CSR_JEOC3   ((uint32_t)0x00040000)

ADC3 Injected channel end of conversion

#define ADC_CSR_JSTRT3   ((uint32_t)0x00080000)

ADC3 Injected channel Start flag

#define ADC_CSR_STRT3   ((uint32_t)0x00100000)

ADC3 Regular channel Start flag

#define ADC_CSR_DOVR3   ((uint32_t)0x00200000)

ADC3 DMA overrun flag

#define ADC_CCR_MULTI   ((uint32_t)0x0000001F)

MULTI[4:0] bits (Multi-ADC mode selection)

#define ADC_CCR_MULTI_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CCR_MULTI_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CCR_MULTI_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CCR_MULTI_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CCR_MULTI_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CCR_DELAY   ((uint32_t)0x00000F00)

DELAY[3:0] bits (Delay between 2 sampling phases)

#define ADC_CCR_DELAY_0   ((uint32_t)0x00000100)

Bit 0

#define ADC_CCR_DELAY_1   ((uint32_t)0x00000200)

Bit 1

#define ADC_CCR_DELAY_2   ((uint32_t)0x00000400)

Bit 2

#define ADC_CCR_DELAY_3   ((uint32_t)0x00000800)

Bit 3

#define ADC_CCR_DDS   ((uint32_t)0x00002000)

DMA disable selection (Multi-ADC mode)

#define ADC_CCR_DMA   ((uint32_t)0x0000C000)

DMA[1:0] bits (Direct Memory Access mode for multimode)

#define ADC_CCR_DMA_0   ((uint32_t)0x00004000)

Bit 0

#define ADC_CCR_DMA_1   ((uint32_t)0x00008000)

Bit 1

#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)

ADCPRE[1:0] bits (ADC prescaler)

#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CCR_VBATE   ((uint32_t)0x00400000)

VBAT Enable

#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

#define ADC_CDR_DATA1   ((uint32_t)0x0000FFFF)

1st data of a pair of regular conversions

#define ADC_CDR_DATA2   ((uint32_t)0xFFFF0000)

2nd data of a pair of regular conversions

#define CAN_MCR_INRQ   ((uint16_t)0x0001)

<CAN control and status registers Initialization Request

#define CAN_MCR_SLEEP   ((uint16_t)0x0002)

Sleep Mode Request

#define CAN_MCR_TXFP   ((uint16_t)0x0004)

Transmit FIFO Priority

#define CAN_MCR_RFLM   ((uint16_t)0x0008)

Receive FIFO Locked Mode

#define CAN_MCR_NART   ((uint16_t)0x0010)

No Automatic Retransmission

#define CAN_MCR_AWUM   ((uint16_t)0x0020)

Automatic Wakeup Mode

#define CAN_MCR_ABOM   ((uint16_t)0x0040)

Automatic Bus-Off Management

#define CAN_MCR_TTCM   ((uint16_t)0x0080)

Time Triggered Communication Mode

#define CAN_MCR_RESET   ((uint16_t)0x8000)

bxCAN software master reset

#define CAN_MSR_INAK   ((uint16_t)0x0001)

Initialization Acknowledge

#define CAN_MSR_SLAK   ((uint16_t)0x0002)

Sleep Acknowledge

#define CAN_MSR_ERRI   ((uint16_t)0x0004)

Error Interrupt

#define CAN_MSR_WKUI   ((uint16_t)0x0008)

Wakeup Interrupt

#define CAN_MSR_SLAKI   ((uint16_t)0x0010)

Sleep Acknowledge Interrupt

#define CAN_MSR_TXM   ((uint16_t)0x0100)

Transmit Mode

#define CAN_MSR_RXM   ((uint16_t)0x0200)

Receive Mode

#define CAN_MSR_SAMP   ((uint16_t)0x0400)

Last Sample Point

#define CAN_MSR_RX   ((uint16_t)0x0800)

CAN Rx Signal

#define CAN_TSR_RQCP0   ((uint32_t)0x00000001)

Request Completed Mailbox0

#define CAN_TSR_TXOK0   ((uint32_t)0x00000002)

Transmission OK of Mailbox0

#define CAN_TSR_ALST0   ((uint32_t)0x00000004)

Arbitration Lost for Mailbox0

#define CAN_TSR_TERR0   ((uint32_t)0x00000008)

Transmission Error of Mailbox0

#define CAN_TSR_ABRQ0   ((uint32_t)0x00000080)

Abort Request for Mailbox0

#define CAN_TSR_RQCP1   ((uint32_t)0x00000100)

Request Completed Mailbox1

#define CAN_TSR_TXOK1   ((uint32_t)0x00000200)

Transmission OK of Mailbox1

#define CAN_TSR_ALST1   ((uint32_t)0x00000400)

Arbitration Lost for Mailbox1

#define CAN_TSR_TERR1   ((uint32_t)0x00000800)

Transmission Error of Mailbox1

#define CAN_TSR_ABRQ1   ((uint32_t)0x00008000)

Abort Request for Mailbox 1

#define CAN_TSR_RQCP2   ((uint32_t)0x00010000)

Request Completed Mailbox2

#define CAN_TSR_TXOK2   ((uint32_t)0x00020000)

Transmission OK of Mailbox 2

#define CAN_TSR_ALST2   ((uint32_t)0x00040000)

Arbitration Lost for mailbox 2

#define CAN_TSR_TERR2   ((uint32_t)0x00080000)

Transmission Error of Mailbox 2

#define CAN_TSR_ABRQ2   ((uint32_t)0x00800000)

Abort Request for Mailbox 2

#define CAN_TSR_CODE   ((uint32_t)0x03000000)

Mailbox Code

#define CAN_TSR_TME   ((uint32_t)0x1C000000)

TME[2:0] bits

#define CAN_TSR_TME0   ((uint32_t)0x04000000)

Transmit Mailbox 0 Empty

#define CAN_TSR_TME1   ((uint32_t)0x08000000)

Transmit Mailbox 1 Empty

#define CAN_TSR_TME2   ((uint32_t)0x10000000)

Transmit Mailbox 2 Empty

#define CAN_TSR_LOW   ((uint32_t)0xE0000000)

LOW[2:0] bits

#define CAN_TSR_LOW0   ((uint32_t)0x20000000)

Lowest Priority Flag for Mailbox 0

#define CAN_TSR_LOW1   ((uint32_t)0x40000000)

Lowest Priority Flag for Mailbox 1

#define CAN_TSR_LOW2   ((uint32_t)0x80000000)

Lowest Priority Flag for Mailbox 2

#define CAN_RF0R_FMP0   ((uint8_t)0x03)

FIFO 0 Message Pending

#define CAN_RF0R_FULL0   ((uint8_t)0x08)

FIFO 0 Full

#define CAN_RF0R_FOVR0   ((uint8_t)0x10)

FIFO 0 Overrun

#define CAN_RF0R_RFOM0   ((uint8_t)0x20)

Release FIFO 0 Output Mailbox

#define CAN_RF1R_FMP1   ((uint8_t)0x03)

FIFO 1 Message Pending

#define CAN_RF1R_FULL1   ((uint8_t)0x08)

FIFO 1 Full

#define CAN_RF1R_FOVR1   ((uint8_t)0x10)

FIFO 1 Overrun

#define CAN_RF1R_RFOM1   ((uint8_t)0x20)

Release FIFO 1 Output Mailbox

#define CAN_IER_TMEIE   ((uint32_t)0x00000001)

Transmit Mailbox Empty Interrupt Enable

#define CAN_IER_FMPIE0   ((uint32_t)0x00000002)

FIFO Message Pending Interrupt Enable

#define CAN_IER_FFIE0   ((uint32_t)0x00000004)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE0   ((uint32_t)0x00000008)

FIFO Overrun Interrupt Enable

#define CAN_IER_FMPIE1   ((uint32_t)0x00000010)

FIFO Message Pending Interrupt Enable

#define CAN_IER_FFIE1   ((uint32_t)0x00000020)

FIFO Full Interrupt Enable

#define CAN_IER_FOVIE1   ((uint32_t)0x00000040)

FIFO Overrun Interrupt Enable

#define CAN_IER_EWGIE   ((uint32_t)0x00000100)

Error Warning Interrupt Enable

#define CAN_IER_EPVIE   ((uint32_t)0x00000200)

Error Passive Interrupt Enable

#define CAN_IER_BOFIE   ((uint32_t)0x00000400)

Bus-Off Interrupt Enable

#define CAN_IER_LECIE   ((uint32_t)0x00000800)

Last Error Code Interrupt Enable

#define CAN_IER_ERRIE   ((uint32_t)0x00008000)

Error Interrupt Enable

#define CAN_IER_WKUIE   ((uint32_t)0x00010000)

Wakeup Interrupt Enable

#define CAN_IER_SLKIE   ((uint32_t)0x00020000)

Sleep Interrupt Enable

#define CAN_ESR_EWGF   ((uint32_t)0x00000001)

Error Warning Flag

#define CAN_ESR_EPVF   ((uint32_t)0x00000002)

Error Passive Flag

#define CAN_ESR_BOFF   ((uint32_t)0x00000004)

Bus-Off Flag

#define CAN_ESR_LEC   ((uint32_t)0x00000070)

LEC[2:0] bits (Last Error Code)

#define CAN_ESR_LEC_0   ((uint32_t)0x00000010)

Bit 0

#define CAN_ESR_LEC_1   ((uint32_t)0x00000020)

Bit 1

#define CAN_ESR_LEC_2   ((uint32_t)0x00000040)

Bit 2

#define CAN_ESR_TEC   ((uint32_t)0x00FF0000)

Least significant byte of the 9-bit Transmit Error Counter

#define CAN_ESR_REC   ((uint32_t)0xFF000000)

Receive Error Counter

#define CAN_BTR_BRP   ((uint32_t)0x000003FF)

Baud Rate Prescaler

#define CAN_BTR_TS1   ((uint32_t)0x000F0000)

Time Segment 1

#define CAN_BTR_TS2   ((uint32_t)0x00700000)

Time Segment 2

#define CAN_BTR_SJW   ((uint32_t)0x03000000)

Resynchronization Jump Width

#define CAN_BTR_LBKM   ((uint32_t)0x40000000)

Loop Back Mode (Debug)

#define CAN_BTR_SILM   ((uint32_t)0x80000000)

Silent Mode Mailbox registers

#define CAN_TI0R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT0R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI1R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI1R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_TI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT1R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_TI2R_TXRQ   ((uint32_t)0x00000001)

Transmit Mailbox Request

#define CAN_TI2R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_TI2R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_TI2R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_TI2R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_TDT2R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_TDT2R_TGT   ((uint32_t)0x00000100)

Transmit Global Time

#define CAN_TDT2R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_TDL2R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_TDL2R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_TDL2R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_TDL2R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_TDH2R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_TDH2R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_TDH2R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_TDH2R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI0R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_RI0R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_RI0R_EXID   ((uint32_t)0x001FFFF8)

Extended Identifier

#define CAN_RI0R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT0R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT0R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT0R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL0R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL0R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL0R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL0R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH0R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH0R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH0R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH0R_DATA7   ((uint32_t)0xFF000000)

Data byte 7

#define CAN_RI1R_RTR   ((uint32_t)0x00000002)

Remote Transmission Request

#define CAN_RI1R_IDE   ((uint32_t)0x00000004)

Identifier Extension

#define CAN_RI1R_EXID   ((uint32_t)0x001FFFF8)

Extended identifier

#define CAN_RI1R_STID   ((uint32_t)0xFFE00000)

Standard Identifier or Extended Identifier

#define CAN_RDT1R_DLC   ((uint32_t)0x0000000F)

Data Length Code

#define CAN_RDT1R_FMI   ((uint32_t)0x0000FF00)

Filter Match Index

#define CAN_RDT1R_TIME   ((uint32_t)0xFFFF0000)

Message Time Stamp

#define CAN_RDL1R_DATA0   ((uint32_t)0x000000FF)

Data byte 0

#define CAN_RDL1R_DATA1   ((uint32_t)0x0000FF00)

Data byte 1

#define CAN_RDL1R_DATA2   ((uint32_t)0x00FF0000)

Data byte 2

#define CAN_RDL1R_DATA3   ((uint32_t)0xFF000000)

Data byte 3

#define CAN_RDH1R_DATA4   ((uint32_t)0x000000FF)

Data byte 4

#define CAN_RDH1R_DATA5   ((uint32_t)0x0000FF00)

Data byte 5

#define CAN_RDH1R_DATA6   ((uint32_t)0x00FF0000)

Data byte 6

#define CAN_RDH1R_DATA7   ((uint32_t)0xFF000000)

Data byte 7 CAN filter registers

#define CAN_FMR_FINIT   ((uint8_t)0x01)

Filter Init Mode

#define CAN_FM1R_FBM   ((uint16_t)0x3FFF)

Filter Mode

#define CAN_FM1R_FBM0   ((uint16_t)0x0001)

Filter Init Mode bit 0

#define CAN_FM1R_FBM1   ((uint16_t)0x0002)

Filter Init Mode bit 1

#define CAN_FM1R_FBM2   ((uint16_t)0x0004)

Filter Init Mode bit 2

#define CAN_FM1R_FBM3   ((uint16_t)0x0008)

Filter Init Mode bit 3

#define CAN_FM1R_FBM4   ((uint16_t)0x0010)

Filter Init Mode bit 4

#define CAN_FM1R_FBM5   ((uint16_t)0x0020)

Filter Init Mode bit 5

#define CAN_FM1R_FBM6   ((uint16_t)0x0040)

Filter Init Mode bit 6

#define CAN_FM1R_FBM7   ((uint16_t)0x0080)

Filter Init Mode bit 7

#define CAN_FM1R_FBM8   ((uint16_t)0x0100)

Filter Init Mode bit 8

#define CAN_FM1R_FBM9   ((uint16_t)0x0200)

Filter Init Mode bit 9

#define CAN_FM1R_FBM10   ((uint16_t)0x0400)

Filter Init Mode bit 10

#define CAN_FM1R_FBM11   ((uint16_t)0x0800)

Filter Init Mode bit 11

#define CAN_FM1R_FBM12   ((uint16_t)0x1000)

Filter Init Mode bit 12

#define CAN_FM1R_FBM13   ((uint16_t)0x2000)

Filter Init Mode bit 13

#define CAN_FS1R_FSC   ((uint16_t)0x3FFF)

Filter Scale Configuration

#define CAN_FS1R_FSC0   ((uint16_t)0x0001)

Filter Scale Configuration bit 0

#define CAN_FS1R_FSC1   ((uint16_t)0x0002)

Filter Scale Configuration bit 1

#define CAN_FS1R_FSC2   ((uint16_t)0x0004)

Filter Scale Configuration bit 2

#define CAN_FS1R_FSC3   ((uint16_t)0x0008)

Filter Scale Configuration bit 3

#define CAN_FS1R_FSC4   ((uint16_t)0x0010)

Filter Scale Configuration bit 4

#define CAN_FS1R_FSC5   ((uint16_t)0x0020)

Filter Scale Configuration bit 5

#define CAN_FS1R_FSC6   ((uint16_t)0x0040)

Filter Scale Configuration bit 6

#define CAN_FS1R_FSC7   ((uint16_t)0x0080)

Filter Scale Configuration bit 7

#define CAN_FS1R_FSC8   ((uint16_t)0x0100)

Filter Scale Configuration bit 8

#define CAN_FS1R_FSC9   ((uint16_t)0x0200)

Filter Scale Configuration bit 9

#define CAN_FS1R_FSC10   ((uint16_t)0x0400)

Filter Scale Configuration bit 10

#define CAN_FS1R_FSC11   ((uint16_t)0x0800)

Filter Scale Configuration bit 11

#define CAN_FS1R_FSC12   ((uint16_t)0x1000)

Filter Scale Configuration bit 12

#define CAN_FS1R_FSC13   ((uint16_t)0x2000)

Filter Scale Configuration bit 13

#define CAN_FFA1R_FFA   ((uint16_t)0x3FFF)

Filter FIFO Assignment

#define CAN_FFA1R_FFA0   ((uint16_t)0x0001)

Filter FIFO Assignment for Filter 0

#define CAN_FFA1R_FFA1   ((uint16_t)0x0002)

Filter FIFO Assignment for Filter 1

#define CAN_FFA1R_FFA2   ((uint16_t)0x0004)

Filter FIFO Assignment for Filter 2

#define CAN_FFA1R_FFA3   ((uint16_t)0x0008)

Filter FIFO Assignment for Filter 3

#define CAN_FFA1R_FFA4   ((uint16_t)0x0010)

Filter FIFO Assignment for Filter 4

#define CAN_FFA1R_FFA5   ((uint16_t)0x0020)

Filter FIFO Assignment for Filter 5

#define CAN_FFA1R_FFA6   ((uint16_t)0x0040)

Filter FIFO Assignment for Filter 6

#define CAN_FFA1R_FFA7   ((uint16_t)0x0080)

Filter FIFO Assignment for Filter 7

#define CAN_FFA1R_FFA8   ((uint16_t)0x0100)

Filter FIFO Assignment for Filter 8

#define CAN_FFA1R_FFA9   ((uint16_t)0x0200)

Filter FIFO Assignment for Filter 9

#define CAN_FFA1R_FFA10   ((uint16_t)0x0400)

Filter FIFO Assignment for Filter 10

#define CAN_FFA1R_FFA11   ((uint16_t)0x0800)

Filter FIFO Assignment for Filter 11

#define CAN_FFA1R_FFA12   ((uint16_t)0x1000)

Filter FIFO Assignment for Filter 12

#define CAN_FFA1R_FFA13   ((uint16_t)0x2000)

Filter FIFO Assignment for Filter 13

#define CAN_FA1R_FACT   ((uint16_t)0x3FFF)

Filter Active

#define CAN_FA1R_FACT0   ((uint16_t)0x0001)

Filter 0 Active

#define CAN_FA1R_FACT1   ((uint16_t)0x0002)

Filter 1 Active

#define CAN_FA1R_FACT2   ((uint16_t)0x0004)

Filter 2 Active

#define CAN_FA1R_FACT3   ((uint16_t)0x0008)

Filter 3 Active

#define CAN_FA1R_FACT4   ((uint16_t)0x0010)

Filter 4 Active

#define CAN_FA1R_FACT5   ((uint16_t)0x0020)

Filter 5 Active

#define CAN_FA1R_FACT6   ((uint16_t)0x0040)

Filter 6 Active

#define CAN_FA1R_FACT7   ((uint16_t)0x0080)

Filter 7 Active

#define CAN_FA1R_FACT8   ((uint16_t)0x0100)

Filter 8 Active

#define CAN_FA1R_FACT9   ((uint16_t)0x0200)

Filter 9 Active

#define CAN_FA1R_FACT10   ((uint16_t)0x0400)

Filter 10 Active

#define CAN_FA1R_FACT11   ((uint16_t)0x0800)

Filter 11 Active

#define CAN_FA1R_FACT12   ((uint16_t)0x1000)

Filter 12 Active

#define CAN_FA1R_FACT13   ((uint16_t)0x2000)

Filter 13 Active

#define CAN_F0R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R1_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R1_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R1_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R1_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R1_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R1_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R1_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R1_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R1_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R1_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R1_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R1_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R1_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R1_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R1_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R1_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R1_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R1_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R1_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R1_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R1_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R1_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R1_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R1_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R1_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R1_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R1_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R1_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R1_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R1_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R1_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R1_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F0R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F0R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F0R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F0R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F0R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F0R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F0R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F0R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F0R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F0R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F0R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F0R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F0R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F0R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F0R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F0R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F0R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F0R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F0R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F0R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F0R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F0R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F0R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F0R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F0R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F0R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F0R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F0R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F0R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F0R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F0R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F0R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F1R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F1R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F1R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F1R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F1R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F1R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F1R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F1R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F1R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F1R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F1R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F1R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F1R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F1R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F1R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F1R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F1R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F1R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F1R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F1R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F1R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F1R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F1R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F1R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F1R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F1R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F1R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F1R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F1R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F1R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F1R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F1R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F2R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F2R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F2R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F2R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F2R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F2R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F2R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F2R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F2R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F2R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F2R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F2R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F2R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F2R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F2R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F2R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F2R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F2R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F2R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F2R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F2R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F2R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F2R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F2R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F2R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F2R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F2R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F2R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F2R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F2R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F2R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F2R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F3R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F3R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F3R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F3R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F3R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F3R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F3R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F3R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F3R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F3R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F3R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F3R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F3R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F3R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F3R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F3R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F3R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F3R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F3R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F3R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F3R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F3R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F3R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F3R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F3R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F3R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F3R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F3R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F3R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F3R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F3R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F3R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F4R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F4R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F4R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F4R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F4R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F4R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F4R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F4R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F4R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F4R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F4R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F4R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F4R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F4R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F4R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F4R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F4R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F4R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F4R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F4R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F4R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F4R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F4R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F4R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F4R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F4R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F4R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F4R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F4R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F4R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F4R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F4R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F5R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F5R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F5R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F5R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F5R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F5R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F5R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F5R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F5R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F5R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F5R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F5R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F5R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F5R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F5R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F5R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F5R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F5R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F5R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F5R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F5R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F5R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F5R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F5R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F5R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F5R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F5R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F5R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F5R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F5R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F5R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F5R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F6R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F6R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F6R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F6R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F6R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F6R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F6R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F6R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F6R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F6R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F6R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F6R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F6R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F6R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F6R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F6R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F6R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F6R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F6R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F6R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F6R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F6R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F6R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F6R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F6R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F6R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F6R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F6R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F6R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F6R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F6R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F6R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F7R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F7R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F7R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F7R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F7R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F7R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F7R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F7R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F7R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F7R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F7R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F7R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F7R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F7R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F7R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F7R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F7R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F7R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F7R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F7R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F7R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F7R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F7R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F7R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F7R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F7R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F7R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F7R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F7R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F7R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F7R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F7R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F8R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F8R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F8R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F8R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F8R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F8R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F8R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F8R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F8R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F8R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F8R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F8R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F8R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F8R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F8R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F8R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F8R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F8R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F8R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F8R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F8R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F8R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F8R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F8R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F8R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F8R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F8R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F8R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F8R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F8R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F8R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F8R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F9R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F9R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F9R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F9R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F9R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F9R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F9R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F9R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F9R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F9R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F9R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F9R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F9R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F9R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F9R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F9R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F9R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F9R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F9R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F9R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F9R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F9R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F9R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F9R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F9R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F9R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F9R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F9R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F9R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F9R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F9R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F9R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F10R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F10R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F10R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F10R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F10R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F10R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F10R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F10R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F10R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F10R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F10R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F10R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F10R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F10R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F10R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F10R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F10R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F10R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F10R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F10R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F10R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F10R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F10R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F10R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F10R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F10R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F10R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F10R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F10R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F10R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F10R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F10R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F11R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F11R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F11R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F11R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F11R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F11R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F11R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F11R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F11R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F11R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F11R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F11R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F11R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F11R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F11R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F11R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F11R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F11R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F11R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F11R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F11R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F11R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F11R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F11R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F11R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F11R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F11R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F11R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F11R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F11R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F11R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F11R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F12R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F12R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F12R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F12R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F12R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F12R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F12R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F12R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F12R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F12R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F12R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F12R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F12R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F12R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F12R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F12R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F12R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F12R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F12R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F12R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F12R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F12R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F12R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F12R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F12R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F12R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F12R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F12R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F12R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F12R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F12R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F12R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CAN_F13R2_FB0   ((uint32_t)0x00000001)

Filter bit 0

#define CAN_F13R2_FB1   ((uint32_t)0x00000002)

Filter bit 1

#define CAN_F13R2_FB2   ((uint32_t)0x00000004)

Filter bit 2

#define CAN_F13R2_FB3   ((uint32_t)0x00000008)

Filter bit 3

#define CAN_F13R2_FB4   ((uint32_t)0x00000010)

Filter bit 4

#define CAN_F13R2_FB5   ((uint32_t)0x00000020)

Filter bit 5

#define CAN_F13R2_FB6   ((uint32_t)0x00000040)

Filter bit 6

#define CAN_F13R2_FB7   ((uint32_t)0x00000080)

Filter bit 7

#define CAN_F13R2_FB8   ((uint32_t)0x00000100)

Filter bit 8

#define CAN_F13R2_FB9   ((uint32_t)0x00000200)

Filter bit 9

#define CAN_F13R2_FB10   ((uint32_t)0x00000400)

Filter bit 10

#define CAN_F13R2_FB11   ((uint32_t)0x00000800)

Filter bit 11

#define CAN_F13R2_FB12   ((uint32_t)0x00001000)

Filter bit 12

#define CAN_F13R2_FB13   ((uint32_t)0x00002000)

Filter bit 13

#define CAN_F13R2_FB14   ((uint32_t)0x00004000)

Filter bit 14

#define CAN_F13R2_FB15   ((uint32_t)0x00008000)

Filter bit 15

#define CAN_F13R2_FB16   ((uint32_t)0x00010000)

Filter bit 16

#define CAN_F13R2_FB17   ((uint32_t)0x00020000)

Filter bit 17

#define CAN_F13R2_FB18   ((uint32_t)0x00040000)

Filter bit 18

#define CAN_F13R2_FB19   ((uint32_t)0x00080000)

Filter bit 19

#define CAN_F13R2_FB20   ((uint32_t)0x00100000)

Filter bit 20

#define CAN_F13R2_FB21   ((uint32_t)0x00200000)

Filter bit 21

#define CAN_F13R2_FB22   ((uint32_t)0x00400000)

Filter bit 22

#define CAN_F13R2_FB23   ((uint32_t)0x00800000)

Filter bit 23

#define CAN_F13R2_FB24   ((uint32_t)0x01000000)

Filter bit 24

#define CAN_F13R2_FB25   ((uint32_t)0x02000000)

Filter bit 25

#define CAN_F13R2_FB26   ((uint32_t)0x04000000)

Filter bit 26

#define CAN_F13R2_FB27   ((uint32_t)0x08000000)

Filter bit 27

#define CAN_F13R2_FB28   ((uint32_t)0x10000000)

Filter bit 28

#define CAN_F13R2_FB29   ((uint32_t)0x20000000)

Filter bit 29

#define CAN_F13R2_FB30   ((uint32_t)0x40000000)

Filter bit 30

#define CAN_F13R2_FB31   ((uint32_t)0x80000000)

Filter bit 31

#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)

Data register bits

#define CRC_IDR_IDR   ((uint8_t)0xFF)

General-purpose 8-bit data register bits

#define CRC_CR_RESET   ((uint8_t)0x01)

RESET bit

#define CRYP_CR_ALGODIR   ((uint32_t)0x00000004)

#define CRYP_CR_ALGOMODE   ((uint32_t)0x00000038)

#define CRYP_CR_ALGOMODE_0   ((uint32_t)0x00000008)

#define CRYP_CR_ALGOMODE_1   ((uint32_t)0x00000010)

#define CRYP_CR_ALGOMODE_2   ((uint32_t)0x00000020)

#define CRYP_CR_ALGOMODE_TDES_ECB   ((uint32_t)0x00000000)

#define CRYP_CR_ALGOMODE_TDES_CBC   ((uint32_t)0x00000008)

#define CRYP_CR_ALGOMODE_DES_ECB   ((uint32_t)0x00000010)

#define CRYP_CR_ALGOMODE_DES_CBC   ((uint32_t)0x00000018)

#define CRYP_CR_ALGOMODE_AES_ECB   ((uint32_t)0x00000020)

#define CRYP_CR_ALGOMODE_AES_CBC   ((uint32_t)0x00000028)

#define CRYP_CR_ALGOMODE_AES_CTR   ((uint32_t)0x00000030)

#define CRYP_CR_ALGOMODE_AES_KEY   ((uint32_t)0x00000038)

#define CRYP_CR_DATATYPE   ((uint32_t)0x000000C0)

#define CRYP_CR_DATATYPE_0   ((uint32_t)0x00000040)

#define CRYP_CR_DATATYPE_1   ((uint32_t)0x00000080)

#define CRYP_CR_KEYSIZE   ((uint32_t)0x00000300)

#define CRYP_CR_KEYSIZE_0   ((uint32_t)0x00000100)

#define CRYP_CR_KEYSIZE_1   ((uint32_t)0x00000200)

#define CRYP_CR_FFLUSH   ((uint32_t)0x00004000)

#define CRYP_CR_CRYPEN   ((uint32_t)0x00008000)

#define CRYP_SR_IFEM   ((uint32_t)0x00000001)

#define CRYP_SR_IFNF   ((uint32_t)0x00000002)

#define CRYP_SR_OFNE   ((uint32_t)0x00000004)

#define CRYP_SR_OFFU   ((uint32_t)0x00000008)

#define CRYP_SR_BUSY   ((uint32_t)0x00000010)

#define CRYP_DMACR_DIEN   ((uint32_t)0x00000001)

#define CRYP_DMACR_DOEN   ((uint32_t)0x00000002)

#define CRYP_IMSCR_INIM   ((uint32_t)0x00000001)

#define CRYP_IMSCR_OUTIM   ((uint32_t)0x00000002)

#define CRYP_RISR_OUTRIS   ((uint32_t)0x00000001)

#define CRYP_RISR_INRIS   ((uint32_t)0x00000002)

#define CRYP_MISR_INMIS   ((uint32_t)0x00000001)

#define CRYP_MISR_OUTMIS   ((uint32_t)0x00000002)

#define DAC_CR_EN1   ((uint32_t)0x00000001)

DAC channel1 enable

#define DAC_CR_BOFF1   ((uint32_t)0x00000002)

DAC channel1 output buffer disable

#define DAC_CR_TEN1   ((uint32_t)0x00000004)

DAC channel1 Trigger enable

#define DAC_CR_TSEL1   ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)

Bit 0

#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)

Bit 1

#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)

Bit 2

#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)

Bit 0

#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)

Bit 1

#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)

Bit 0

#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)

Bit 1

#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)

Bit 2

#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)

Bit 3

#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)

DAC channel1 DMA enable

#define DAC_CR_EN2   ((uint32_t)0x00010000)

DAC channel2 enable

#define DAC_CR_BOFF2   ((uint32_t)0x00020000)

DAC channel2 output buffer disable

#define DAC_CR_TEN2   ((uint32_t)0x00040000)

DAC channel2 Trigger enable

#define DAC_CR_TSEL2   ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)

Bit 0

#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)

Bit 1

#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)

Bit 2

#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)

Bit 0

#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)

Bit 1

#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)

Bit 0

#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)

Bit 1

#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)

Bit 2

#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)

Bit 3

#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)

DAC channel2 DMA enabled

#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)

DAC channel1 software trigger

#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)

DAC channel2 software trigger

#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)

DAC channel1 data output

#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)

DAC channel2 data output

#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

#define DCMI_CR_CAPTURE   ((uint32_t)0x00000001)

#define DCMI_CR_CM   ((uint32_t)0x00000002)

#define DCMI_CR_CROP   ((uint32_t)0x00000004)

#define DCMI_CR_JPEG   ((uint32_t)0x00000008)

#define DCMI_CR_ESS   ((uint32_t)0x00000010)

#define DCMI_CR_PCKPOL   ((uint32_t)0x00000020)

#define DCMI_CR_HSPOL   ((uint32_t)0x00000040)

#define DCMI_CR_VSPOL   ((uint32_t)0x00000080)

#define DCMI_CR_FCRC_0   ((uint32_t)0x00000100)

#define DCMI_CR_FCRC_1   ((uint32_t)0x00000200)

#define DCMI_CR_EDM_0   ((uint32_t)0x00000400)

#define DCMI_CR_EDM_1   ((uint32_t)0x00000800)

#define DCMI_CR_CRE   ((uint32_t)0x00001000)

#define DCMI_CR_ENABLE   ((uint32_t)0x00004000)

#define DCMI_SR_HSYNC   ((uint32_t)0x00000001)

#define DCMI_SR_VSYNC   ((uint32_t)0x00000002)

#define DCMI_SR_FNE   ((uint32_t)0x00000004)

#define DCMI_RISR_FRAME_RIS   ((uint32_t)0x00000001)

#define DCMI_RISR_OVF_RIS   ((uint32_t)0x00000002)

#define DCMI_RISR_ERR_RIS   ((uint32_t)0x00000004)

#define DCMI_RISR_VSYNC_RIS   ((uint32_t)0x00000008)

#define DCMI_RISR_LINE_RIS   ((uint32_t)0x00000010)

#define DCMI_IER_FRAME_IE   ((uint32_t)0x00000001)

#define DCMI_IER_OVF_IE   ((uint32_t)0x00000002)

#define DCMI_IER_ERR_IE   ((uint32_t)0x00000004)

#define DCMI_IER_VSYNC_IE   ((uint32_t)0x00000008)

#define DCMI_IER_LINE_IE   ((uint32_t)0x00000010)

#define DCMI_MISR_FRAME_MIS   ((uint32_t)0x00000001)

#define DCMI_MISR_OVF_MIS   ((uint32_t)0x00000002)

#define DCMI_MISR_ERR_MIS   ((uint32_t)0x00000004)

#define DCMI_MISR_VSYNC_MIS   ((uint32_t)0x00000008)

#define DCMI_MISR_LINE_MIS   ((uint32_t)0x00000010)

#define DCMI_ICR_FRAME_ISC   ((uint32_t)0x00000001)

#define DCMI_ICR_OVF_ISC   ((uint32_t)0x00000002)

#define DCMI_ICR_ERR_ISC   ((uint32_t)0x00000004)

#define DCMI_ICR_VSYNC_ISC   ((uint32_t)0x00000008)

#define DCMI_ICR_LINE_ISC   ((uint32_t)0x00000010)

#define DMA_SxCR_CHSEL   ((uint32_t)0x0E000000)

#define DMA_SxCR_CHSEL_0   ((uint32_t)0x02000000)

#define DMA_SxCR_CHSEL_1   ((uint32_t)0x04000000)

#define DMA_SxCR_CHSEL_2   ((uint32_t)0x08000000)

#define DMA_SxCR_MBURST   ((uint32_t)0x01800000)

#define DMA_SxCR_MBURST_0   ((uint32_t)0x00800000)

#define DMA_SxCR_MBURST_1   ((uint32_t)0x01000000)

#define DMA_SxCR_PBURST   ((uint32_t)0x00600000)

#define DMA_SxCR_PBURST_0   ((uint32_t)0x00200000)

#define DMA_SxCR_PBURST_1   ((uint32_t)0x00400000)

#define DMA_SxCR_ACK   ((uint32_t)0x00100000)

#define DMA_SxCR_CT   ((uint32_t)0x00080000)

#define DMA_SxCR_DBM   ((uint32_t)0x00040000)

#define DMA_SxCR_PL   ((uint32_t)0x00030000)

#define DMA_SxCR_PL_0   ((uint32_t)0x00010000)

#define DMA_SxCR_PL_1   ((uint32_t)0x00020000)

#define DMA_SxCR_PINCOS   ((uint32_t)0x00008000)

#define DMA_SxCR_MSIZE   ((uint32_t)0x00006000)

#define DMA_SxCR_MSIZE_0   ((uint32_t)0x00002000)

#define DMA_SxCR_MSIZE_1   ((uint32_t)0x00004000)

#define DMA_SxCR_PSIZE   ((uint32_t)0x00001800)

#define DMA_SxCR_PSIZE_0   ((uint32_t)0x00000800)

#define DMA_SxCR_PSIZE_1   ((uint32_t)0x00001000)

#define DMA_SxCR_MINC   ((uint32_t)0x00000400)

#define DMA_SxCR_PINC   ((uint32_t)0x00000200)

#define DMA_SxCR_CIRC   ((uint32_t)0x00000100)

#define DMA_SxCR_DIR   ((uint32_t)0x000000C0)

#define DMA_SxCR_DIR_0   ((uint32_t)0x00000040)

#define DMA_SxCR_DIR_1   ((uint32_t)0x00000080)

#define DMA_SxCR_PFCTRL   ((uint32_t)0x00000020)

#define DMA_SxCR_TCIE   ((uint32_t)0x00000010)

#define DMA_SxCR_HTIE   ((uint32_t)0x00000008)

#define DMA_SxCR_TEIE   ((uint32_t)0x00000004)

#define DMA_SxCR_DMEIE   ((uint32_t)0x00000002)

#define DMA_SxCR_EN   ((uint32_t)0x00000001)

#define DMA_SxNDT   ((uint32_t)0x0000FFFF)

#define DMA_SxNDT_0   ((uint32_t)0x00000001)

#define DMA_SxNDT_1   ((uint32_t)0x00000002)

#define DMA_SxNDT_2   ((uint32_t)0x00000004)

#define DMA_SxNDT_3   ((uint32_t)0x00000008)

#define DMA_SxNDT_4   ((uint32_t)0x00000010)

#define DMA_SxNDT_5   ((uint32_t)0x00000020)

#define DMA_SxNDT_6   ((uint32_t)0x00000040)

#define DMA_SxNDT_7   ((uint32_t)0x00000080)

#define DMA_SxNDT_8   ((uint32_t)0x00000100)

#define DMA_SxNDT_9   ((uint32_t)0x00000200)

#define DMA_SxNDT_10   ((uint32_t)0x00000400)

#define DMA_SxNDT_11   ((uint32_t)0x00000800)

#define DMA_SxNDT_12   ((uint32_t)0x00001000)

#define DMA_SxNDT_13   ((uint32_t)0x00002000)

#define DMA_SxNDT_14   ((uint32_t)0x00004000)

#define DMA_SxNDT_15   ((uint32_t)0x00008000)

#define DMA_SxFCR_FEIE   ((uint32_t)0x00000080)

#define DMA_SxFCR_FS   ((uint32_t)0x00000038)

#define DMA_SxFCR_FS_0   ((uint32_t)0x00000008)

#define DMA_SxFCR_FS_1   ((uint32_t)0x00000010)

#define DMA_SxFCR_FS_2   ((uint32_t)0x00000020)

#define DMA_SxFCR_DMDIS   ((uint32_t)0x00000004)

#define DMA_SxFCR_FTH   ((uint32_t)0x00000003)

#define DMA_SxFCR_FTH_0   ((uint32_t)0x00000001)

#define DMA_SxFCR_FTH_1   ((uint32_t)0x00000002)

#define DMA_LISR_TCIF3   ((uint32_t)0x08000000)

#define DMA_LISR_HTIF3   ((uint32_t)0x04000000)

#define DMA_LISR_TEIF3   ((uint32_t)0x02000000)

#define DMA_LISR_DMEIF3   ((uint32_t)0x01000000)

#define DMA_LISR_FEIF3   ((uint32_t)0x00400000)

#define DMA_LISR_TCIF2   ((uint32_t)0x00200000)

#define DMA_LISR_HTIF2   ((uint32_t)0x00100000)

#define DMA_LISR_TEIF2   ((uint32_t)0x00080000)

#define DMA_LISR_DMEIF2   ((uint32_t)0x00040000)

#define DMA_LISR_FEIF2   ((uint32_t)0x00010000)

#define DMA_LISR_TCIF1   ((uint32_t)0x00000800)

#define DMA_LISR_HTIF1   ((uint32_t)0x00000400)

#define DMA_LISR_TEIF1   ((uint32_t)0x00000200)

#define DMA_LISR_DMEIF1   ((uint32_t)0x00000100)

#define DMA_LISR_FEIF1   ((uint32_t)0x00000040)

#define DMA_LISR_TCIF0   ((uint32_t)0x00000020)

#define DMA_LISR_HTIF0   ((uint32_t)0x00000010)

#define DMA_LISR_TEIF0   ((uint32_t)0x00000008)

#define DMA_LISR_DMEIF0   ((uint32_t)0x00000004)

#define DMA_LISR_FEIF0   ((uint32_t)0x00000001)

#define DMA_HISR_TCIF7   ((uint32_t)0x08000000)

#define DMA_HISR_HTIF7   ((uint32_t)0x04000000)

#define DMA_HISR_TEIF7   ((uint32_t)0x02000000)

#define DMA_HISR_DMEIF7   ((uint32_t)0x01000000)

#define DMA_HISR_FEIF7   ((uint32_t)0x00400000)

#define DMA_HISR_TCIF6   ((uint32_t)0x00200000)

#define DMA_HISR_HTIF6   ((uint32_t)0x00100000)

#define DMA_HISR_TEIF6   ((uint32_t)0x00080000)

#define DMA_HISR_DMEIF6   ((uint32_t)0x00040000)

#define DMA_HISR_FEIF6   ((uint32_t)0x00010000)

#define DMA_HISR_TCIF5   ((uint32_t)0x00000800)

#define DMA_HISR_HTIF5   ((uint32_t)0x00000400)

#define DMA_HISR_TEIF5   ((uint32_t)0x00000200)

#define DMA_HISR_DMEIF5   ((uint32_t)0x00000100)

#define DMA_HISR_FEIF5   ((uint32_t)0x00000040)

#define DMA_HISR_TCIF4   ((uint32_t)0x00000020)

#define DMA_HISR_HTIF4   ((uint32_t)0x00000010)

#define DMA_HISR_TEIF4   ((uint32_t)0x00000008)

#define DMA_HISR_DMEIF4   ((uint32_t)0x00000004)

#define DMA_HISR_FEIF4   ((uint32_t)0x00000001)

#define DMA_LIFCR_CTCIF3   ((uint32_t)0x08000000)

#define DMA_LIFCR_CHTIF3   ((uint32_t)0x04000000)

#define DMA_LIFCR_CTEIF3   ((uint32_t)0x02000000)

#define DMA_LIFCR_CDMEIF3   ((uint32_t)0x01000000)

#define DMA_LIFCR_CFEIF3   ((uint32_t)0x00400000)

#define DMA_LIFCR_CTCIF2   ((uint32_t)0x00200000)

#define DMA_LIFCR_CHTIF2   ((uint32_t)0x00100000)

#define DMA_LIFCR_CTEIF2   ((uint32_t)0x00080000)

#define DMA_LIFCR_CDMEIF2   ((uint32_t)0x00040000)

#define DMA_LIFCR_CFEIF2   ((uint32_t)0x00010000)

#define DMA_LIFCR_CTCIF1   ((uint32_t)0x00000800)

#define DMA_LIFCR_CHTIF1   ((uint32_t)0x00000400)

#define DMA_LIFCR_CTEIF1   ((uint32_t)0x00000200)

#define DMA_LIFCR_CDMEIF1   ((uint32_t)0x00000100)

#define DMA_LIFCR_CFEIF1   ((uint32_t)0x00000040)

#define DMA_LIFCR_CTCIF0   ((uint32_t)0x00000020)

#define DMA_LIFCR_CHTIF0   ((uint32_t)0x00000010)

#define DMA_LIFCR_CTEIF0   ((uint32_t)0x00000008)

#define DMA_LIFCR_CDMEIF0   ((uint32_t)0x00000004)

#define DMA_LIFCR_CFEIF0   ((uint32_t)0x00000001)

#define DMA_HIFCR_CTCIF7   ((uint32_t)0x08000000)

#define DMA_HIFCR_CHTIF7   ((uint32_t)0x04000000)

#define DMA_HIFCR_CTEIF7   ((uint32_t)0x02000000)

#define DMA_HIFCR_CDMEIF7   ((uint32_t)0x01000000)

#define DMA_HIFCR_CFEIF7   ((uint32_t)0x00400000)

#define DMA_HIFCR_CTCIF6   ((uint32_t)0x00200000)

#define DMA_HIFCR_CHTIF6   ((uint32_t)0x00100000)

#define DMA_HIFCR_CTEIF6   ((uint32_t)0x00080000)

#define DMA_HIFCR_CDMEIF6   ((uint32_t)0x00040000)

#define DMA_HIFCR_CFEIF6   ((uint32_t)0x00010000)

#define DMA_HIFCR_CTCIF5   ((uint32_t)0x00000800)

#define DMA_HIFCR_CHTIF5   ((uint32_t)0x00000400)

#define DMA_HIFCR_CTEIF5   ((uint32_t)0x00000200)

#define DMA_HIFCR_CDMEIF5   ((uint32_t)0x00000100)

#define DMA_HIFCR_CFEIF5   ((uint32_t)0x00000040)

#define DMA_HIFCR_CTCIF4   ((uint32_t)0x00000020)

#define DMA_HIFCR_CHTIF4   ((uint32_t)0x00000010)

#define DMA_HIFCR_CTEIF4   ((uint32_t)0x00000008)

#define DMA_HIFCR_CDMEIF4   ((uint32_t)0x00000004)

#define DMA_HIFCR_CFEIF4   ((uint32_t)0x00000001)

#define EXTI_IMR_MR0   ((uint32_t)0x00000001)

Interrupt Mask on line 0

#define EXTI_IMR_MR1   ((uint32_t)0x00000002)

Interrupt Mask on line 1

#define EXTI_IMR_MR2   ((uint32_t)0x00000004)

Interrupt Mask on line 2

#define EXTI_IMR_MR3   ((uint32_t)0x00000008)

Interrupt Mask on line 3

#define EXTI_IMR_MR4   ((uint32_t)0x00000010)

Interrupt Mask on line 4

#define EXTI_IMR_MR5   ((uint32_t)0x00000020)

Interrupt Mask on line 5

#define EXTI_IMR_MR6   ((uint32_t)0x00000040)

Interrupt Mask on line 6

#define EXTI_IMR_MR7   ((uint32_t)0x00000080)

Interrupt Mask on line 7

#define EXTI_IMR_MR8   ((uint32_t)0x00000100)

Interrupt Mask on line 8

#define EXTI_IMR_MR9   ((uint32_t)0x00000200)

Interrupt Mask on line 9

#define EXTI_IMR_MR10   ((uint32_t)0x00000400)

Interrupt Mask on line 10

#define EXTI_IMR_MR11   ((uint32_t)0x00000800)

Interrupt Mask on line 11

#define EXTI_IMR_MR12   ((uint32_t)0x00001000)

Interrupt Mask on line 12

#define EXTI_IMR_MR13   ((uint32_t)0x00002000)

Interrupt Mask on line 13

#define EXTI_IMR_MR14   ((uint32_t)0x00004000)

Interrupt Mask on line 14

#define EXTI_IMR_MR15   ((uint32_t)0x00008000)

Interrupt Mask on line 15

#define EXTI_IMR_MR16   ((uint32_t)0x00010000)

Interrupt Mask on line 16

#define EXTI_IMR_MR17   ((uint32_t)0x00020000)

Interrupt Mask on line 17

#define EXTI_IMR_MR18   ((uint32_t)0x00040000)

Interrupt Mask on line 18

#define EXTI_IMR_MR19   ((uint32_t)0x00080000)

Interrupt Mask on line 19

#define EXTI_EMR_MR0   ((uint32_t)0x00000001)

Event Mask on line 0

#define EXTI_EMR_MR1   ((uint32_t)0x00000002)

Event Mask on line 1

#define EXTI_EMR_MR2   ((uint32_t)0x00000004)

Event Mask on line 2

#define EXTI_EMR_MR3   ((uint32_t)0x00000008)

Event Mask on line 3

#define EXTI_EMR_MR4   ((uint32_t)0x00000010)

Event Mask on line 4

#define EXTI_EMR_MR5   ((uint32_t)0x00000020)

Event Mask on line 5

#define EXTI_EMR_MR6   ((uint32_t)0x00000040)

Event Mask on line 6

#define EXTI_EMR_MR7   ((uint32_t)0x00000080)

Event Mask on line 7

#define EXTI_EMR_MR8   ((uint32_t)0x00000100)

Event Mask on line 8

#define EXTI_EMR_MR9   ((uint32_t)0x00000200)

Event Mask on line 9

#define EXTI_EMR_MR10   ((uint32_t)0x00000400)

Event Mask on line 10

#define EXTI_EMR_MR11   ((uint32_t)0x00000800)

Event Mask on line 11

#define EXTI_EMR_MR12   ((uint32_t)0x00001000)

Event Mask on line 12

#define EXTI_EMR_MR13   ((uint32_t)0x00002000)

Event Mask on line 13

#define EXTI_EMR_MR14   ((uint32_t)0x00004000)

Event Mask on line 14

#define EXTI_EMR_MR15   ((uint32_t)0x00008000)

Event Mask on line 15

#define EXTI_EMR_MR16   ((uint32_t)0x00010000)

Event Mask on line 16

#define EXTI_EMR_MR17   ((uint32_t)0x00020000)

Event Mask on line 17

#define EXTI_EMR_MR18   ((uint32_t)0x00040000)

Event Mask on line 18

#define EXTI_EMR_MR19   ((uint32_t)0x00080000)

Event Mask on line 19

#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)

Software Interrupt on line 0

#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)

Software Interrupt on line 1

#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)

Software Interrupt on line 2

#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)

Software Interrupt on line 3

#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)

Software Interrupt on line 4

#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)

Software Interrupt on line 5

#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)

Software Interrupt on line 6

#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)

Software Interrupt on line 7

#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)

Software Interrupt on line 8

#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)

Software Interrupt on line 9

#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)

Software Interrupt on line 10

#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)

Software Interrupt on line 11

#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)

Software Interrupt on line 12

#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)

Software Interrupt on line 13

#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)

Software Interrupt on line 14

#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)

Software Interrupt on line 15

#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)

Software Interrupt on line 16

#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)

Software Interrupt on line 17

#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)

Software Interrupt on line 18

#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)

Software Interrupt on line 19

#define EXTI_PR_PR0   ((uint32_t)0x00000001)

Pending bit for line 0

#define EXTI_PR_PR1   ((uint32_t)0x00000002)

Pending bit for line 1

#define EXTI_PR_PR2   ((uint32_t)0x00000004)

Pending bit for line 2

#define EXTI_PR_PR3   ((uint32_t)0x00000008)

Pending bit for line 3

#define EXTI_PR_PR4   ((uint32_t)0x00000010)

Pending bit for line 4

#define EXTI_PR_PR5   ((uint32_t)0x00000020)

Pending bit for line 5

#define EXTI_PR_PR6   ((uint32_t)0x00000040)

Pending bit for line 6

#define EXTI_PR_PR7   ((uint32_t)0x00000080)

Pending bit for line 7

#define EXTI_PR_PR8   ((uint32_t)0x00000100)

Pending bit for line 8

#define EXTI_PR_PR9   ((uint32_t)0x00000200)

Pending bit for line 9

#define EXTI_PR_PR10   ((uint32_t)0x00000400)

Pending bit for line 10

#define EXTI_PR_PR11   ((uint32_t)0x00000800)

Pending bit for line 11

#define EXTI_PR_PR12   ((uint32_t)0x00001000)

Pending bit for line 12

#define EXTI_PR_PR13   ((uint32_t)0x00002000)

Pending bit for line 13

#define EXTI_PR_PR14   ((uint32_t)0x00004000)

Pending bit for line 14

#define EXTI_PR_PR15   ((uint32_t)0x00008000)

Pending bit for line 15

#define EXTI_PR_PR16   ((uint32_t)0x00010000)

Pending bit for line 16

#define EXTI_PR_PR17   ((uint32_t)0x00020000)

Pending bit for line 17

#define EXTI_PR_PR18   ((uint32_t)0x00040000)

Pending bit for line 18

#define EXTI_PR_PR19   ((uint32_t)0x00080000)

Pending bit for line 19

#define FLASH_ACR_LATENCY   ((uint32_t)0x00000007)

#define FLASH_ACR_LATENCY_0WS   ((uint32_t)0x00000000)

#define FLASH_ACR_LATENCY_1WS   ((uint32_t)0x00000001)

#define FLASH_ACR_LATENCY_2WS   ((uint32_t)0x00000002)

#define FLASH_ACR_LATENCY_3WS   ((uint32_t)0x00000003)

#define FLASH_ACR_LATENCY_4WS   ((uint32_t)0x00000004)

#define FLASH_ACR_LATENCY_5WS   ((uint32_t)0x00000005)

#define FLASH_ACR_LATENCY_6WS   ((uint32_t)0x00000006)

#define FLASH_ACR_LATENCY_7WS   ((uint32_t)0x00000007)

#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000100)

#define FLASH_ACR_ICEN   ((uint32_t)0x00000200)

#define FLASH_ACR_DCEN   ((uint32_t)0x00000400)

#define FLASH_ACR_ICRST   ((uint32_t)0x00000800)

#define FLASH_ACR_DCRST   ((uint32_t)0x00001000)

#define FLASH_ACR_BYTE0_ADDRESS   ((uint32_t)0x40023C00)

#define FLASH_ACR_BYTE2_ADDRESS   ((uint32_t)0x40023C03)

#define FLASH_SR_EOP   ((uint32_t)0x00000001)

#define FLASH_SR_SOP   ((uint32_t)0x00000002)

#define FLASH_SR_WRPERR   ((uint32_t)0x00000010)

#define FLASH_SR_PGAERR   ((uint32_t)0x00000020)

#define FLASH_SR_PGPERR   ((uint32_t)0x00000040)

#define FLASH_SR_PGSERR   ((uint32_t)0x00000080)

#define FLASH_SR_BSY   ((uint32_t)0x00010000)

#define FLASH_CR_PG   ((uint32_t)0x00000001)

#define FLASH_CR_SER   ((uint32_t)0x00000002)

#define FLASH_CR_MER   ((uint32_t)0x00000004)

#define FLASH_CR_SNB_0   ((uint32_t)0x00000008)

#define FLASH_CR_SNB_1   ((uint32_t)0x00000010)

#define FLASH_CR_SNB_2   ((uint32_t)0x00000020)

#define FLASH_CR_SNB_3   ((uint32_t)0x00000040)

#define FLASH_CR_PSIZE_0   ((uint32_t)0x00000100)

#define FLASH_CR_PSIZE_1   ((uint32_t)0x00000200)

#define FLASH_CR_STRT   ((uint32_t)0x00010000)

#define FLASH_CR_EOPIE   ((uint32_t)0x01000000)

#define FLASH_CR_LOCK   ((uint32_t)0x80000000)

#define FLASH_OPTCR_OPTLOCK   ((uint32_t)0x00000001)

#define FLASH_OPTCR_OPTSTRT   ((uint32_t)0x00000002)

#define FLASH_OPTCR_BOR_LEV_0   ((uint32_t)0x00000004)

#define FLASH_OPTCR_BOR_LEV_1   ((uint32_t)0x00000008)

#define FLASH_OPTCR_BOR_LEV   ((uint32_t)0x0000000C)

#define FLASH_OPTCR_WDG_SW   ((uint32_t)0x00000020)

#define FLASH_OPTCR_nRST_STOP   ((uint32_t)0x00000040)

#define FLASH_OPTCR_nRST_STDBY   ((uint32_t)0x00000080)

#define FLASH_OPTCR_RDP_0   ((uint32_t)0x00000100)

#define FLASH_OPTCR_RDP_1   ((uint32_t)0x00000200)

#define FLASH_OPTCR_RDP_2   ((uint32_t)0x00000400)

#define FLASH_OPTCR_RDP_3   ((uint32_t)0x00000800)

#define FLASH_OPTCR_RDP_4   ((uint32_t)0x00001000)

#define FLASH_OPTCR_RDP_5   ((uint32_t)0x00002000)

#define FLASH_OPTCR_RDP_6   ((uint32_t)0x00004000)

#define FLASH_OPTCR_RDP_7   ((uint32_t)0x00008000)

#define FLASH_OPTCR_nWRP_0   ((uint32_t)0x00010000)

#define FLASH_OPTCR_nWRP_1   ((uint32_t)0x00020000)

#define FLASH_OPTCR_nWRP_2   ((uint32_t)0x00040000)

#define FLASH_OPTCR_nWRP_3   ((uint32_t)0x00080000)

#define FLASH_OPTCR_nWRP_4   ((uint32_t)0x00100000)

#define FLASH_OPTCR_nWRP_5   ((uint32_t)0x00200000)

#define FLASH_OPTCR_nWRP_6   ((uint32_t)0x00400000)

#define FLASH_OPTCR_nWRP_7   ((uint32_t)0x00800000)

#define FLASH_OPTCR_nWRP_8   ((uint32_t)0x01000000)

#define FLASH_OPTCR_nWRP_9   ((uint32_t)0x02000000)

#define FLASH_OPTCR_nWRP_10   ((uint32_t)0x04000000)

#define FLASH_OPTCR_nWRP_11   ((uint32_t)0x08000000)

#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit.

#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_PCR2_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR2_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR2_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR2_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR2_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR2_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR2_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR2_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR2_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR2_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR2_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR2_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR2_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR2_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR2_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR2_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR2_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR2_ECCPS   ((uint32_t)0x000E0000)

ECCPS[1:0] bits (ECC page size)

#define FSMC_PCR2_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR2_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR2_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR3_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR3_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR3_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR3_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR3_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR3_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR3_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR3_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR3_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR3_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR3_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR3_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR3_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR3_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR3_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR3_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR3_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR3_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR3_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR3_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR3_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_PCR4_PWAITEN   ((uint32_t)0x00000002)

Wait feature enable bit

#define FSMC_PCR4_PBKEN   ((uint32_t)0x00000004)

PC Card/NAND Flash memory bank enable bit

#define FSMC_PCR4_PTYP   ((uint32_t)0x00000008)

Memory type

#define FSMC_PCR4_PWID   ((uint32_t)0x00000030)

PWID[1:0] bits (NAND Flash databus width)

#define FSMC_PCR4_PWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_PCR4_PWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_PCR4_ECCEN   ((uint32_t)0x00000040)

ECC computation logic enable bit

#define FSMC_PCR4_TCLR   ((uint32_t)0x00001E00)

TCLR[3:0] bits (CLE to RE delay)

#define FSMC_PCR4_TCLR_0   ((uint32_t)0x00000200)

Bit 0

#define FSMC_PCR4_TCLR_1   ((uint32_t)0x00000400)

Bit 1

#define FSMC_PCR4_TCLR_2   ((uint32_t)0x00000800)

Bit 2

#define FSMC_PCR4_TCLR_3   ((uint32_t)0x00001000)

Bit 3

#define FSMC_PCR4_TAR   ((uint32_t)0x0001E000)

TAR[3:0] bits (ALE to RE delay)

#define FSMC_PCR4_TAR_0   ((uint32_t)0x00002000)

Bit 0

#define FSMC_PCR4_TAR_1   ((uint32_t)0x00004000)

Bit 1

#define FSMC_PCR4_TAR_2   ((uint32_t)0x00008000)

Bit 2

#define FSMC_PCR4_TAR_3   ((uint32_t)0x00010000)

Bit 3

#define FSMC_PCR4_ECCPS   ((uint32_t)0x000E0000)

ECCPS[2:0] bits (ECC page size)

#define FSMC_PCR4_ECCPS_0   ((uint32_t)0x00020000)

Bit 0

#define FSMC_PCR4_ECCPS_1   ((uint32_t)0x00040000)

Bit 1

#define FSMC_PCR4_ECCPS_2   ((uint32_t)0x00080000)

Bit 2

#define FSMC_SR2_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR2_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR2_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR2_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR2_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR2_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR2_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR3_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR3_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR3_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR3_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR3_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR3_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR3_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_SR4_IRS   ((uint8_t)0x01)

Interrupt Rising Edge status

#define FSMC_SR4_ILS   ((uint8_t)0x02)

Interrupt Level status

#define FSMC_SR4_IFS   ((uint8_t)0x04)

Interrupt Falling Edge status

#define FSMC_SR4_IREN   ((uint8_t)0x08)

Interrupt Rising Edge detection Enable bit

#define FSMC_SR4_ILEN   ((uint8_t)0x10)

Interrupt Level detection Enable bit

#define FSMC_SR4_IFEN   ((uint8_t)0x20)

Interrupt Falling Edge detection Enable bit

#define FSMC_SR4_FEMPT   ((uint8_t)0x40)

FIFO empty

#define FSMC_PMEM2_MEMSET2   ((uint32_t)0x000000FF)

MEMSET2[7:0] bits (Common memory 2 setup time)

#define FSMC_PMEM2_MEMSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM2_MEMSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM2_MEMSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM2_MEMSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM2_MEMSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM2_MEMSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM2_MEMSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM2_MEMSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM2_MEMWAIT2   ((uint32_t)0x0000FF00)

MEMWAIT2[7:0] bits (Common memory 2 wait time)

#define FSMC_PMEM2_MEMWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM2_MEMWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM2_MEMWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM2_MEMWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM2_MEMWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM2_MEMWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM2_MEMWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM2_MEMWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM2_MEMHOLD2   ((uint32_t)0x00FF0000)

MEMHOLD2[7:0] bits (Common memory 2 hold time)

#define FSMC_PMEM2_MEMHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM2_MEMHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM2_MEMHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM2_MEMHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM2_MEMHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM2_MEMHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM2_MEMHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM2_MEMHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM2_MEMHIZ2   ((uint32_t)0xFF000000)

MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time)

#define FSMC_PMEM2_MEMHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM2_MEMHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM2_MEMHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM2_MEMHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM2_MEMHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM2_MEMHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM2_MEMHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM2_MEMHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM3_MEMSET3   ((uint32_t)0x000000FF)

MEMSET3[7:0] bits (Common memory 3 setup time)

#define FSMC_PMEM3_MEMSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM3_MEMSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM3_MEMSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM3_MEMSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM3_MEMSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM3_MEMSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM3_MEMSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM3_MEMSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM3_MEMWAIT3   ((uint32_t)0x0000FF00)

MEMWAIT3[7:0] bits (Common memory 3 wait time)

#define FSMC_PMEM3_MEMWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM3_MEMWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM3_MEMWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM3_MEMWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM3_MEMWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM3_MEMWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM3_MEMWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM3_MEMWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM3_MEMHOLD3   ((uint32_t)0x00FF0000)

MEMHOLD3[7:0] bits (Common memory 3 hold time)

#define FSMC_PMEM3_MEMHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM3_MEMHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM3_MEMHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM3_MEMHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM3_MEMHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM3_MEMHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM3_MEMHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM3_MEMHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM3_MEMHIZ3   ((uint32_t)0xFF000000)

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

#define FSMC_PMEM3_MEMHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM3_MEMHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM3_MEMHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM3_MEMHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM3_MEMHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM3_MEMHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM3_MEMHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM3_MEMHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PMEM4_MEMSET4   ((uint32_t)0x000000FF)

MEMSET4[7:0] bits (Common memory 4 setup time)

#define FSMC_PMEM4_MEMSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PMEM4_MEMSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PMEM4_MEMSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PMEM4_MEMSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PMEM4_MEMSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PMEM4_MEMSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PMEM4_MEMSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PMEM4_MEMSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PMEM4_MEMWAIT4   ((uint32_t)0x0000FF00)

MEMWAIT4[7:0] bits (Common memory 4 wait time)

#define FSMC_PMEM4_MEMWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PMEM4_MEMWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PMEM4_MEMWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PMEM4_MEMWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PMEM4_MEMWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PMEM4_MEMWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PMEM4_MEMWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PMEM4_MEMWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PMEM4_MEMHOLD4   ((uint32_t)0x00FF0000)

MEMHOLD4[7:0] bits (Common memory 4 hold time)

#define FSMC_PMEM4_MEMHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PMEM4_MEMHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PMEM4_MEMHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PMEM4_MEMHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PMEM4_MEMHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PMEM4_MEMHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PMEM4_MEMHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PMEM4_MEMHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PMEM4_MEMHIZ4   ((uint32_t)0xFF000000)

MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time)

#define FSMC_PMEM4_MEMHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PMEM4_MEMHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PMEM4_MEMHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PMEM4_MEMHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PMEM4_MEMHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PMEM4_MEMHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PMEM4_MEMHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PMEM4_MEMHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT2_ATTSET2   ((uint32_t)0x000000FF)

ATTSET2[7:0] bits (Attribute memory 2 setup time)

#define FSMC_PATT2_ATTSET2_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT2_ATTSET2_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT2_ATTSET2_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT2_ATTSET2_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT2_ATTSET2_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT2_ATTSET2_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT2_ATTSET2_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT2_ATTSET2_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT2_ATTWAIT2   ((uint32_t)0x0000FF00)

ATTWAIT2[7:0] bits (Attribute memory 2 wait time)

#define FSMC_PATT2_ATTWAIT2_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT2_ATTWAIT2_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT2_ATTWAIT2_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT2_ATTWAIT2_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT2_ATTWAIT2_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT2_ATTWAIT2_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT2_ATTWAIT2_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT2_ATTWAIT2_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT2_ATTHOLD2   ((uint32_t)0x00FF0000)

ATTHOLD2[7:0] bits (Attribute memory 2 hold time)

#define FSMC_PATT2_ATTHOLD2_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT2_ATTHOLD2_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT2_ATTHOLD2_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT2_ATTHOLD2_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT2_ATTHOLD2_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT2_ATTHOLD2_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT2_ATTHOLD2_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT2_ATTHOLD2_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT2_ATTHIZ2   ((uint32_t)0xFF000000)

ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time)

#define FSMC_PATT2_ATTHIZ2_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT2_ATTHIZ2_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT2_ATTHIZ2_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT2_ATTHIZ2_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT2_ATTHIZ2_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT2_ATTHIZ2_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT2_ATTHIZ2_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT2_ATTHIZ2_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT3_ATTSET3   ((uint32_t)0x000000FF)

ATTSET3[7:0] bits (Attribute memory 3 setup time)

#define FSMC_PATT3_ATTSET3_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT3_ATTSET3_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT3_ATTSET3_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT3_ATTSET3_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT3_ATTSET3_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT3_ATTSET3_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT3_ATTSET3_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT3_ATTSET3_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT3_ATTWAIT3   ((uint32_t)0x0000FF00)

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

#define FSMC_PATT3_ATTWAIT3_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT3_ATTWAIT3_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT3_ATTWAIT3_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT3_ATTWAIT3_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT3_ATTWAIT3_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT3_ATTWAIT3_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT3_ATTWAIT3_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT3_ATTWAIT3_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT3_ATTHOLD3   ((uint32_t)0x00FF0000)

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

#define FSMC_PATT3_ATTHOLD3_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT3_ATTHOLD3_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT3_ATTHOLD3_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT3_ATTHOLD3_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT3_ATTHOLD3_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT3_ATTHOLD3_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT3_ATTHOLD3_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT3_ATTHOLD3_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT3_ATTHIZ3   ((uint32_t)0xFF000000)

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

#define FSMC_PATT3_ATTHIZ3_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT3_ATTHIZ3_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT3_ATTHIZ3_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT3_ATTHIZ3_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT3_ATTHIZ3_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT3_ATTHIZ3_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT3_ATTHIZ3_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT3_ATTHIZ3_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PATT4_ATTSET4   ((uint32_t)0x000000FF)

ATTSET4[7:0] bits (Attribute memory 4 setup time)

#define FSMC_PATT4_ATTSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PATT4_ATTSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PATT4_ATTSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PATT4_ATTSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PATT4_ATTSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PATT4_ATTSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PATT4_ATTSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PATT4_ATTSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PATT4_ATTWAIT4   ((uint32_t)0x0000FF00)

ATTWAIT4[7:0] bits (Attribute memory 4 wait time)

#define FSMC_PATT4_ATTWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PATT4_ATTWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PATT4_ATTWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PATT4_ATTWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PATT4_ATTWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PATT4_ATTWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PATT4_ATTWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PATT4_ATTWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PATT4_ATTHOLD4   ((uint32_t)0x00FF0000)

ATTHOLD4[7:0] bits (Attribute memory 4 hold time)

#define FSMC_PATT4_ATTHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PATT4_ATTHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PATT4_ATTHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PATT4_ATTHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PATT4_ATTHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PATT4_ATTHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PATT4_ATTHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PATT4_ATTHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PATT4_ATTHIZ4   ((uint32_t)0xFF000000)

ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time)

#define FSMC_PATT4_ATTHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PATT4_ATTHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PATT4_ATTHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PATT4_ATTHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PATT4_ATTHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PATT4_ATTHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PATT4_ATTHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PATT4_ATTHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_PIO4_IOSET4   ((uint32_t)0x000000FF)

IOSET4[7:0] bits (I/O 4 setup time)

#define FSMC_PIO4_IOSET4_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_PIO4_IOSET4_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_PIO4_IOSET4_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_PIO4_IOSET4_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_PIO4_IOSET4_4   ((uint32_t)0x00000010)

Bit 4

#define FSMC_PIO4_IOSET4_5   ((uint32_t)0x00000020)

Bit 5

#define FSMC_PIO4_IOSET4_6   ((uint32_t)0x00000040)

Bit 6

#define FSMC_PIO4_IOSET4_7   ((uint32_t)0x00000080)

Bit 7

#define FSMC_PIO4_IOWAIT4   ((uint32_t)0x0000FF00)

IOWAIT4[7:0] bits (I/O 4 wait time)

#define FSMC_PIO4_IOWAIT4_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_PIO4_IOWAIT4_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_PIO4_IOWAIT4_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_PIO4_IOWAIT4_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_PIO4_IOWAIT4_4   ((uint32_t)0x00001000)

Bit 4

#define FSMC_PIO4_IOWAIT4_5   ((uint32_t)0x00002000)

Bit 5

#define FSMC_PIO4_IOWAIT4_6   ((uint32_t)0x00004000)

Bit 6

#define FSMC_PIO4_IOWAIT4_7   ((uint32_t)0x00008000)

Bit 7

#define FSMC_PIO4_IOHOLD4   ((uint32_t)0x00FF0000)

IOHOLD4[7:0] bits (I/O 4 hold time)

#define FSMC_PIO4_IOHOLD4_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_PIO4_IOHOLD4_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_PIO4_IOHOLD4_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_PIO4_IOHOLD4_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_PIO4_IOHOLD4_4   ((uint32_t)0x00100000)

Bit 4

#define FSMC_PIO4_IOHOLD4_5   ((uint32_t)0x00200000)

Bit 5

#define FSMC_PIO4_IOHOLD4_6   ((uint32_t)0x00400000)

Bit 6

#define FSMC_PIO4_IOHOLD4_7   ((uint32_t)0x00800000)

Bit 7

#define FSMC_PIO4_IOHIZ4   ((uint32_t)0xFF000000)

IOHIZ4[7:0] bits (I/O 4 databus HiZ time)

#define FSMC_PIO4_IOHIZ4_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_PIO4_IOHIZ4_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_PIO4_IOHIZ4_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_PIO4_IOHIZ4_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_PIO4_IOHIZ4_4   ((uint32_t)0x10000000)

Bit 4

#define FSMC_PIO4_IOHIZ4_5   ((uint32_t)0x20000000)

Bit 5

#define FSMC_PIO4_IOHIZ4_6   ((uint32_t)0x40000000)

Bit 6

#define FSMC_PIO4_IOHIZ4_7   ((uint32_t)0x80000000)

Bit 7

#define FSMC_ECCR2_ECC2   ((uint32_t)0xFFFFFFFF)

ECC result

#define FSMC_ECCR3_ECC3   ((uint32_t)0xFFFFFFFF)

ECC result

#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)

#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)

#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)

#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)

#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)

#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)

#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)

#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)

#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)

#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)

#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)

#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)

#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)

#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)

#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)

#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)

#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)

#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)

#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)

#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)

#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)

#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)

#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)

#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)

#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)

#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)

#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)

#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)

#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)

#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)

#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)

#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)

#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)

#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)

#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)

#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)

#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)

#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)

#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)

#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)

#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)

#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)

#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)

#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)

#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)

#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)

#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)

#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)

#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)

#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)

#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)

#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)

#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)

#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)

#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)

#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)

#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)

#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)

#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)

#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)

#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)

#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)

#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)

#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)

#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)

#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)

#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)

#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)

#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)

#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)

#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)

#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)

#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)

#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)

#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)

#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)

#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)

#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)

#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)

#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)

#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)

#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)

#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)

#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)

#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)

#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)

#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)

#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)

#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)

#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)

#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)

#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)

#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)

#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)

#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)

#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)

#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)

#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)

#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)

#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)

#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)

#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)

#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)

#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)

#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)

#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)

#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)

#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)

#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)

#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)

#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)

#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)

#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)

#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)

#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)

#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)

#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)

#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)

#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)

#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)

#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)

#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)

#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)

#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)

#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)

#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)

#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)

#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)

#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)

#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)

#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)

#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)

#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)

#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)

#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)

#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)

#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)

#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)

#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)

#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)

#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)

#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)

#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)

#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)

#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)

#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)

#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)

#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)

#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)

#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)

#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)

#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)

#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)

#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)

#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)

#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)

#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)

#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)

#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)

#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)

#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)

#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)

#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)

#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)

#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)

#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)

#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)

#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)

#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)

#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)

#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)

#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)

#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)

#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)

#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0

#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1

#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2

#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3

#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4

#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5

#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6

#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7

#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8

#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9

#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10

#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11

#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12

#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13

#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14

#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15

#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)

#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)

#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)

#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)

#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)

#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)

#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)

#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)

#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)

#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)

#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)

#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)

#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)

#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)

#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)

#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)

#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0

#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1

#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2

#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3

#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4

#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5

#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6

#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7

#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8

#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9

#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10

#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11

#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12

#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13

#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14

#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15

#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)

#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)

#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)

#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)

#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)

#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)

#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)

#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)

#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)

#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)

#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)

#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)

#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)

#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)

#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)

#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)

#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)

#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)

#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)

#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)

#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)

#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)

#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)

#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)

#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)

#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)

#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)

#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)

#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)

#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)

#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)

#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)

#define HASH_CR_INIT   ((uint32_t)0x00000004)

#define HASH_CR_DMAE   ((uint32_t)0x00000008)

#define HASH_CR_DATATYPE   ((uint32_t)0x00000030)

#define HASH_CR_DATATYPE_0   ((uint32_t)0x00000010)

#define HASH_CR_DATATYPE_1   ((uint32_t)0x00000020)

#define HASH_CR_MODE   ((uint32_t)0x00000040)

#define HASH_CR_ALGO   ((uint32_t)0x00000080)

#define HASH_CR_NBW   ((uint32_t)0x00000F00)

#define HASH_CR_NBW_0   ((uint32_t)0x00000100)

#define HASH_CR_NBW_1   ((uint32_t)0x00000200)

#define HASH_CR_NBW_2   ((uint32_t)0x00000400)

#define HASH_CR_NBW_3   ((uint32_t)0x00000800)

#define HASH_CR_DINNE   ((uint32_t)0x00001000)

#define HASH_CR_LKEY   ((uint32_t)0x00010000)

#define HASH_STR_NBW   ((uint32_t)0x0000001F)

#define HASH_STR_NBW_0   ((uint32_t)0x00000001)

#define HASH_STR_NBW_1   ((uint32_t)0x00000002)

#define HASH_STR_NBW_2   ((uint32_t)0x00000004)

#define HASH_STR_NBW_3   ((uint32_t)0x00000008)

#define HASH_STR_NBW_4   ((uint32_t)0x00000010)

#define HASH_STR_DCAL   ((uint32_t)0x00000100)

#define HASH_IMR_DINIM   ((uint32_t)0x00000001)

#define HASH_IMR_DCIM   ((uint32_t)0x00000002)

#define HASH_SR_DINIS   ((uint32_t)0x00000001)

#define HASH_SR_DCIS   ((uint32_t)0x00000002)

#define HASH_SR_DMAS   ((uint32_t)0x00000004)

#define HASH_SR_BUSY   ((uint32_t)0x00000008)

#define I2C_CR1_PE   ((uint16_t)0x0001)

Peripheral Enable

#define I2C_CR1_SMBUS   ((uint16_t)0x0002)

SMBus Mode

#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)

SMBus Type

#define I2C_CR1_ENARP   ((uint16_t)0x0010)

ARP Enable

#define I2C_CR1_ENPEC   ((uint16_t)0x0020)

PEC Enable

#define I2C_CR1_ENGC   ((uint16_t)0x0040)

General Call Enable

#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

#define I2C_CR1_START   ((uint16_t)0x0100)

Start Generation

#define I2C_CR1_STOP   ((uint16_t)0x0200)

Stop Generation

#define I2C_CR1_ACK   ((uint16_t)0x0400)

Acknowledge Enable

#define I2C_CR1_POS   ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

#define I2C_CR1_PEC   ((uint16_t)0x1000)

Packet Error Checking

#define I2C_CR1_ALERT   ((uint16_t)0x2000)

SMBus Alert

#define I2C_CR1_SWRST   ((uint16_t)0x8000)

Software Reset

#define I2C_CR2_FREQ   ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)

Bit 0

#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)

Bit 1

#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)

Bit 2

#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)

Bit 3

#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)

Bit 4

#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)

Bit 5

#define I2C_CR2_ITERREN   ((uint16_t)0x0100)

Error Interrupt Enable

#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)

Event Interrupt Enable

#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)

Buffer Interrupt Enable

#define I2C_CR2_DMAEN   ((uint16_t)0x0800)

DMA Requests Enable

#define I2C_CR2_LAST   ((uint16_t)0x1000)

DMA Last Transfer

#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)

Interface Address

#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)

Interface Address

#define I2C_OAR1_ADD0   ((uint16_t)0x0001)

Bit 0

#define I2C_OAR1_ADD1   ((uint16_t)0x0002)

Bit 1

#define I2C_OAR1_ADD2   ((uint16_t)0x0004)

Bit 2

#define I2C_OAR1_ADD3   ((uint16_t)0x0008)

Bit 3

#define I2C_OAR1_ADD4   ((uint16_t)0x0010)

Bit 4

#define I2C_OAR1_ADD5   ((uint16_t)0x0020)

Bit 5

#define I2C_OAR1_ADD6   ((uint16_t)0x0040)

Bit 6

#define I2C_OAR1_ADD7   ((uint16_t)0x0080)

Bit 7

#define I2C_OAR1_ADD8   ((uint16_t)0x0100)

Bit 8

#define I2C_OAR1_ADD9   ((uint16_t)0x0200)

Bit 9

#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)

Addressing Mode (Slave mode)

#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)

Dual addressing mode enable

#define I2C_OAR2_ADD2   ((uint8_t)0xFE)

Interface address

#define I2C_DR_DR   ((uint8_t)0xFF)

8-bit Data Register

#define I2C_SR1_SB   ((uint16_t)0x0001)

Start Bit (Master mode)

#define I2C_SR1_ADDR   ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

#define I2C_SR1_BTF   ((uint16_t)0x0004)

Byte Transfer Finished

#define I2C_SR1_ADD10   ((uint16_t)0x0008)

10-bit header sent (Master mode)

#define I2C_SR1_STOPF   ((uint16_t)0x0010)

Stop detection (Slave mode)

#define I2C_SR1_RXNE   ((uint16_t)0x0040)

Data Register not Empty (receivers)

#define I2C_SR1_TXE   ((uint16_t)0x0080)

Data Register Empty (transmitters)

#define I2C_SR1_BERR   ((uint16_t)0x0100)

Bus Error

#define I2C_SR1_ARLO   ((uint16_t)0x0200)

Arbitration Lost (master mode)

#define I2C_SR1_AF   ((uint16_t)0x0400)

Acknowledge Failure

#define I2C_SR1_OVR   ((uint16_t)0x0800)

Overrun/Underrun

#define I2C_SR1_PECERR   ((uint16_t)0x1000)

PEC Error in reception

#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)

Timeout or Tlow Error

#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)

SMBus Alert

#define I2C_SR2_MSL   ((uint16_t)0x0001)

Master/Slave

#define I2C_SR2_BUSY   ((uint16_t)0x0002)

Bus Busy

#define I2C_SR2_TRA   ((uint16_t)0x0004)

Transmitter/Receiver

#define I2C_SR2_GENCALL   ((uint16_t)0x0010)

General Call Address (Slave mode)

#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

#define I2C_SR2_DUALF   ((uint16_t)0x0080)

Dual Flag (Slave mode)

#define I2C_SR2_PEC   ((uint16_t)0xFF00)

Packet Error Checking Register

#define I2C_CCR_CCR   ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

#define I2C_CCR_DUTY   ((uint16_t)0x4000)

Fast Mode Duty Cycle

#define I2C_CCR_FS   ((uint16_t)0x8000)

I2C Master Mode Selection

#define I2C_TRISE_TRISE   ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

#define IWDG_KR_KEY   ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

#define IWDG_PR_PR   ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

#define IWDG_PR_PR_0   ((uint8_t)0x01)

Bit 0

#define IWDG_PR_PR_1   ((uint8_t)0x02)

Bit 1

#define IWDG_PR_PR_2   ((uint8_t)0x04)

Bit 2

#define IWDG_RLR_RL   ((uint16_t)0x0FFF)

Watchdog counter reload value

#define IWDG_SR_PVU   ((uint8_t)0x01)

Watchdog prescaler value update

#define IWDG_SR_RVU   ((uint8_t)0x02)

Watchdog counter reload value update

#define PWR_CR_LPDS   ((uint16_t)0x0001)

Low-Power Deepsleep

#define PWR_CR_PDDS   ((uint16_t)0x0002)

Power Down Deepsleep

#define PWR_CR_CWUF   ((uint16_t)0x0004)

Clear Wakeup Flag

#define PWR_CR_CSBF   ((uint16_t)0x0008)

Clear Standby Flag

#define PWR_CR_PVDE   ((uint16_t)0x0010)

Power Voltage Detector Enable

#define PWR_CR_PLS   ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

#define PWR_CR_PLS_0   ((uint16_t)0x0020)

Bit 0

#define PWR_CR_PLS_1   ((uint16_t)0x0040)

Bit 1

#define PWR_CR_PLS_2   ((uint16_t)0x0080)

Bit 2 PVD level configuration

#define PWR_CR_PLS_LEV0   ((uint16_t)0x0000)

PVD level 0

#define PWR_CR_PLS_LEV1   ((uint16_t)0x0020)

PVD level 1

#define PWR_CR_PLS_LEV2   ((uint16_t)0x0040)

PVD level 2

#define PWR_CR_PLS_LEV3   ((uint16_t)0x0060)

PVD level 3

#define PWR_CR_PLS_LEV4   ((uint16_t)0x0080)

PVD level 4

#define PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)

PVD level 5

#define PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)

PVD level 6

#define PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)

PVD level 7

#define PWR_CR_DBP   ((uint16_t)0x0100)

Disable Backup Domain write protection

#define PWR_CR_FPDS   ((uint16_t)0x0200)

Flash power down in Stop mode

#define PWR_CR_VOS   ((uint16_t)0x4000)

Regulator voltage scaling output selection

#define PWR_CR_PMODE   PWR_CR_VOS

#define PWR_CSR_WUF   ((uint16_t)0x0001)

Wakeup Flag

#define PWR_CSR_SBF   ((uint16_t)0x0002)

Standby Flag

#define PWR_CSR_PVDO   ((uint16_t)0x0004)

PVD Output

#define PWR_CSR_BRR   ((uint16_t)0x0008)

Backup regulator ready

#define PWR_CSR_EWUP   ((uint16_t)0x0100)

Enable WKUP pin

#define PWR_CSR_BRE   ((uint16_t)0x0200)

Backup regulator enable

#define PWR_CSR_VOSRDY   ((uint16_t)0x4000)

Regulator voltage scaling output selection ready

#define PWR_CSR_REGRDY   PWR_CSR_VOSRDY

#define RCC_CR_HSION   ((uint32_t)0x00000001)

#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)

#define RCC_CR_HSITRIM   ((uint32_t)0x000000F8)

#define RCC_CR_HSITRIM_0   ((uint32_t)0x00000008)

Bit 0

#define RCC_CR_HSITRIM_1   ((uint32_t)0x00000010)

Bit 1

#define RCC_CR_HSITRIM_2   ((uint32_t)0x00000020)

Bit 2

#define RCC_CR_HSITRIM_3   ((uint32_t)0x00000040)

Bit 3

#define RCC_CR_HSITRIM_4   ((uint32_t)0x00000080)

Bit 4

#define RCC_CR_HSICAL   ((uint32_t)0x0000FF00)

#define RCC_CR_HSICAL_0   ((uint32_t)0x00000100)

Bit 0

#define RCC_CR_HSICAL_1   ((uint32_t)0x00000200)

Bit 1

#define RCC_CR_HSICAL_2   ((uint32_t)0x00000400)

Bit 2

#define RCC_CR_HSICAL_3   ((uint32_t)0x00000800)

Bit 3

#define RCC_CR_HSICAL_4   ((uint32_t)0x00001000)

Bit 4

#define RCC_CR_HSICAL_5   ((uint32_t)0x00002000)

Bit 5

#define RCC_CR_HSICAL_6   ((uint32_t)0x00004000)

Bit 6

#define RCC_CR_HSICAL_7   ((uint32_t)0x00008000)

Bit 7

#define RCC_CR_HSEON   ((uint32_t)0x00010000)

#define RCC_CR_HSERDY   ((uint32_t)0x00020000)

#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)

#define RCC_CR_CSSON   ((uint32_t)0x00080000)

#define RCC_CR_PLLON   ((uint32_t)0x01000000)

#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)

#define RCC_CR_PLLI2SON   ((uint32_t)0x04000000)

#define RCC_CR_PLLI2SRDY   ((uint32_t)0x08000000)

#define RCC_PLLCFGR_PLLM   ((uint32_t)0x0000003F)

#define RCC_PLLCFGR_PLLM_0   ((uint32_t)0x00000001)

#define RCC_PLLCFGR_PLLM_1   ((uint32_t)0x00000002)

#define RCC_PLLCFGR_PLLM_2   ((uint32_t)0x00000004)

#define RCC_PLLCFGR_PLLM_3   ((uint32_t)0x00000008)

#define RCC_PLLCFGR_PLLM_4   ((uint32_t)0x00000010)

#define RCC_PLLCFGR_PLLM_5   ((uint32_t)0x00000020)

#define RCC_PLLCFGR_PLLN   ((uint32_t)0x00007FC0)

#define RCC_PLLCFGR_PLLN_0   ((uint32_t)0x00000040)

#define RCC_PLLCFGR_PLLN_1   ((uint32_t)0x00000080)

#define RCC_PLLCFGR_PLLN_2   ((uint32_t)0x00000100)

#define RCC_PLLCFGR_PLLN_3   ((uint32_t)0x00000200)

#define RCC_PLLCFGR_PLLN_4   ((uint32_t)0x00000400)

#define RCC_PLLCFGR_PLLN_5   ((uint32_t)0x00000800)

#define RCC_PLLCFGR_PLLN_6   ((uint32_t)0x00001000)

#define RCC_PLLCFGR_PLLN_7   ((uint32_t)0x00002000)

#define RCC_PLLCFGR_PLLN_8   ((uint32_t)0x00004000)

#define RCC_PLLCFGR_PLLP   ((uint32_t)0x00030000)

#define RCC_PLLCFGR_PLLP_0   ((uint32_t)0x00010000)

#define RCC_PLLCFGR_PLLP_1   ((uint32_t)0x00020000)

#define RCC_PLLCFGR_PLLSRC   ((uint32_t)0x00400000)

#define RCC_PLLCFGR_PLLSRC_HSE   ((uint32_t)0x00400000)

#define RCC_PLLCFGR_PLLSRC_HSI   ((uint32_t)0x00000000)

#define RCC_PLLCFGR_PLLQ   ((uint32_t)0x0F000000)

#define RCC_PLLCFGR_PLLQ_0   ((uint32_t)0x01000000)

#define RCC_PLLCFGR_PLLQ_1   ((uint32_t)0x02000000)

#define RCC_PLLCFGR_PLLQ_2   ((uint32_t)0x04000000)

#define RCC_PLLCFGR_PLLQ_3   ((uint32_t)0x08000000)

#define RCC_CFGR_SW   ((uint32_t)0x00000003)

< SW configuration SW[1:0] bits (System clock Switch)

#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)

Bit 0

#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)

Bit 1

#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000000)

HSI selected as system clock

#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000001)

HSE selected as system clock

#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000002)

PLL selected as system clock SWS configuration

#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)

Bit 0

#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)

Bit 1

#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000000)

HSI oscillator used as system clock

#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000004)

HSE oscillator used as system clock

#define RCC_CFGR_SWS_PLL   ((uint32_t)0x00000008)

PLL used as system clock HPRE configuration

#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)

Bit 0

#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)

Bit 1

#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)

Bit 2

#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)

Bit 3

#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)

SYSCLK not divided

#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)

SYSCLK divided by 2

#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)

SYSCLK divided by 4

#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)

SYSCLK divided by 8

#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)

SYSCLK divided by 16

#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)

SYSCLK divided by 64

#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)

SYSCLK divided by 128

#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)

SYSCLK divided by 256

#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)

SYSCLK divided by 512 PPRE1 configuration

#define RCC_CFGR_PPRE1   ((uint32_t)0x00001C00)

PRE1[2:0] bits (APB1 prescaler)

#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000400)

Bit 0

#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000800)

Bit 1

#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00001000)

Bit 2

#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00001000)

HCLK divided by 2

#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00001400)

HCLK divided by 4

#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00001800)

HCLK divided by 8

#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00001C00)

HCLK divided by 16 PPRE2 configuration

#define RCC_CFGR_PPRE2   ((uint32_t)0x0000E000)

PRE2[2:0] bits (APB2 prescaler)

#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00002000)

Bit 0

#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00004000)

Bit 1

#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00008000)

Bit 2

#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00008000)

HCLK divided by 2

#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x0000A000)

HCLK divided by 4

#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x0000C000)

HCLK divided by 8

#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x0000E000)

HCLK divided by 16 RTCPRE configuration

#define RCC_CFGR_RTCPRE   ((uint32_t)0x001F0000)

#define RCC_CFGR_RTCPRE_0   ((uint32_t)0x00010000)

#define RCC_CFGR_RTCPRE_1   ((uint32_t)0x00020000)

#define RCC_CFGR_RTCPRE_2   ((uint32_t)0x00040000)

#define RCC_CFGR_RTCPRE_3   ((uint32_t)0x00080000)

#define RCC_CFGR_RTCPRE_4   ((uint32_t)0x00100000)

MCO1 configuration

#define RCC_CFGR_MCO1   ((uint32_t)0x00600000)

#define RCC_CFGR_MCO1_0   ((uint32_t)0x00200000)

#define RCC_CFGR_MCO1_1   ((uint32_t)0x00400000)

#define RCC_CFGR_I2SSRC   ((uint32_t)0x00800000)

#define RCC_CFGR_MCO1PRE   ((uint32_t)0x07000000)

#define RCC_CFGR_MCO1PRE_0   ((uint32_t)0x01000000)

#define RCC_CFGR_MCO1PRE_1   ((uint32_t)0x02000000)

#define RCC_CFGR_MCO1PRE_2   ((uint32_t)0x04000000)

#define RCC_CFGR_MCO2PRE   ((uint32_t)0x38000000)

#define RCC_CFGR_MCO2PRE_0   ((uint32_t)0x08000000)

#define RCC_CFGR_MCO2PRE_1   ((uint32_t)0x10000000)

#define RCC_CFGR_MCO2PRE_2   ((uint32_t)0x20000000)

#define RCC_CFGR_MCO2   ((uint32_t)0xC0000000)

#define RCC_CFGR_MCO2_0   ((uint32_t)0x40000000)

#define RCC_CFGR_MCO2_1   ((uint32_t)0x80000000)

#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)

#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)

#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)

#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)

#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)

#define RCC_CIR_PLLI2SRDYF   ((uint32_t)0x00000020)

#define RCC_CIR_CSSF   ((uint32_t)0x00000080)

#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)

#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)

#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)

#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)

#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)

#define RCC_CIR_PLLI2SRDYIE   ((uint32_t)0x00002000)

#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)

#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)

#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)

#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)

#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)

#define RCC_CIR_PLLI2SRDYC   ((uint32_t)0x00200000)

#define RCC_CIR_CSSC   ((uint32_t)0x00800000)

#define RCC_AHB1RSTR_GPIOARST   ((uint32_t)0x00000001)

#define RCC_AHB1RSTR_GPIOBRST   ((uint32_t)0x00000002)

#define RCC_AHB1RSTR_GPIOCRST   ((uint32_t)0x00000004)

#define RCC_AHB1RSTR_GPIODRST   ((uint32_t)0x00000008)

#define RCC_AHB1RSTR_GPIOERST   ((uint32_t)0x00000010)

#define RCC_AHB1RSTR_GPIOFRST   ((uint32_t)0x00000020)

#define RCC_AHB1RSTR_GPIOGRST   ((uint32_t)0x00000040)

#define RCC_AHB1RSTR_GPIOHRST   ((uint32_t)0x00000080)

#define RCC_AHB1RSTR_GPIOIRST   ((uint32_t)0x00000100)

#define RCC_AHB1RSTR_CRCRST   ((uint32_t)0x00001000)

#define RCC_AHB1RSTR_DMA1RST   ((uint32_t)0x00200000)

#define RCC_AHB1RSTR_DMA2RST   ((uint32_t)0x00400000)

#define RCC_AHB1RSTR_ETHMACRST   ((uint32_t)0x02000000)

#define RCC_AHB1RSTR_OTGHRST   ((uint32_t)0x10000000)

#define RCC_AHB2RSTR_DCMIRST   ((uint32_t)0x00000001)

#define RCC_AHB2RSTR_CRYPRST   ((uint32_t)0x00000010)

#define RCC_AHB2RSTR_HSAHRST   ((uint32_t)0x00000020)

#define RCC_AHB2RSTR_RNGRST   ((uint32_t)0x00000040)

#define RCC_AHB2RSTR_OTGFSRST   ((uint32_t)0x00000080)

#define RCC_AHB3RSTR_FSMCRST   ((uint32_t)0x00000001)

#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)

#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)

#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)

#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)

#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)

#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)

#define RCC_APB1RSTR_TIM12RST   ((uint32_t)0x00000040)

#define RCC_APB1RSTR_TIM13RST   ((uint32_t)0x00000080)

#define RCC_APB1RSTR_TIM14RST   ((uint32_t)0x00000100)

#define RCC_APB1RSTR_WWDGEN   ((uint32_t)0x00000800)

#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00008000)

#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00010000)

#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)

#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)

#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)

#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)

#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)

#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)

#define RCC_APB1RSTR_I2C3RST   ((uint32_t)0x00800000)

#define RCC_APB1RSTR_CAN1RST   ((uint32_t)0x02000000)

#define RCC_APB1RSTR_CAN2RST   ((uint32_t)0x04000000)

#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)

#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)

#define RCC_APB2RSTR_TIM1RST   ((uint32_t)0x00000001)

#define RCC_APB2RSTR_TIM8RST   ((uint32_t)0x00000002)

#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00000010)

#define RCC_APB2RSTR_USART6RST   ((uint32_t)0x00000020)

#define RCC_APB2RSTR_ADCRST   ((uint32_t)0x00000100)

#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)

#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)

#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00004000)

#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00010000)

#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00020000)

#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00040000)

#define RCC_APB2RSTR_SPI1   RCC_APB2RSTR_SPI1RST

#define RCC_AHB1ENR_GPIOAEN   ((uint32_t)0x00000001)

#define RCC_AHB1ENR_GPIOBEN   ((uint32_t)0x00000002)

#define RCC_AHB1ENR_GPIOCEN   ((uint32_t)0x00000004)

#define RCC_AHB1ENR_GPIODEN   ((uint32_t)0x00000008)

#define RCC_AHB1ENR_GPIOEEN   ((uint32_t)0x00000010)

#define RCC_AHB1ENR_GPIOFEN   ((uint32_t)0x00000020)

#define RCC_AHB1ENR_GPIOGEN   ((uint32_t)0x00000040)

#define RCC_AHB1ENR_GPIOHEN   ((uint32_t)0x00000080)

#define RCC_AHB1ENR_GPIOIEN   ((uint32_t)0x00000100)

#define RCC_AHB1ENR_CRCEN   ((uint32_t)0x00001000)

#define RCC_AHB1ENR_BKPSRAMEN   ((uint32_t)0x00040000)

#define RCC_AHB1ENR_CCMDATARAMEN   ((uint32_t)0x00100000)

#define RCC_AHB1ENR_DMA1EN   ((uint32_t)0x00200000)

#define RCC_AHB1ENR_DMA2EN   ((uint32_t)0x00400000)

#define RCC_AHB1ENR_ETHMACEN   ((uint32_t)0x02000000)

#define RCC_AHB1ENR_ETHMACTXEN   ((uint32_t)0x04000000)

#define RCC_AHB1ENR_ETHMACRXEN   ((uint32_t)0x08000000)

#define RCC_AHB1ENR_ETHMACPTPEN   ((uint32_t)0x10000000)

#define RCC_AHB1ENR_OTGHSEN   ((uint32_t)0x20000000)

#define RCC_AHB1ENR_OTGHSULPIEN   ((uint32_t)0x40000000)

#define RCC_AHB2ENR_DCMIEN   ((uint32_t)0x00000001)

#define RCC_AHB2ENR_CRYPEN   ((uint32_t)0x00000010)

#define RCC_AHB2ENR_HASHEN   ((uint32_t)0x00000020)

#define RCC_AHB2ENR_RNGEN   ((uint32_t)0x00000040)

#define RCC_AHB2ENR_OTGFSEN   ((uint32_t)0x00000080)

#define RCC_AHB3ENR_FSMCEN   ((uint32_t)0x00000001)

#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)

#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)

#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)

#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)

#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)

#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)

#define RCC_APB1ENR_TIM12EN   ((uint32_t)0x00000040)

#define RCC_APB1ENR_TIM13EN   ((uint32_t)0x00000080)

#define RCC_APB1ENR_TIM14EN   ((uint32_t)0x00000100)

#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)

#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)

#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)

#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)

#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)

#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)

#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)

#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)

#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)

#define RCC_APB1ENR_I2C3EN   ((uint32_t)0x00800000)

#define RCC_APB1ENR_CAN1EN   ((uint32_t)0x02000000)

#define RCC_APB1ENR_CAN2EN   ((uint32_t)0x04000000)

#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)

#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)

#define RCC_APB2ENR_TIM1EN   ((uint32_t)0x00000001)

#define RCC_APB2ENR_TIM8EN   ((uint32_t)0x00000002)

#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00000010)

#define RCC_APB2ENR_USART6EN   ((uint32_t)0x00000020)

#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000100)

#define RCC_APB2ENR_ADC2EN   ((uint32_t)0x00000200)

#define RCC_APB2ENR_ADC3EN   ((uint32_t)0x00000400)

#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)

#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)

#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00004000)

#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00040000)

#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00020000)

#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00010000)

#define RCC_AHB1LPENR_GPIOALPEN   ((uint32_t)0x00000001)

#define RCC_AHB1LPENR_GPIOBLPEN   ((uint32_t)0x00000002)

#define RCC_AHB1LPENR_GPIOCLPEN   ((uint32_t)0x00000004)

#define RCC_AHB1LPENR_GPIODLPEN   ((uint32_t)0x00000008)

#define RCC_AHB1LPENR_GPIOELPEN   ((uint32_t)0x00000010)

#define RCC_AHB1LPENR_GPIOFLPEN   ((uint32_t)0x00000020)

#define RCC_AHB1LPENR_GPIOGLPEN   ((uint32_t)0x00000040)

#define RCC_AHB1LPENR_GPIOHLPEN   ((uint32_t)0x00000080)

#define RCC_AHB1LPENR_GPIOILPEN   ((uint32_t)0x00000100)

#define RCC_AHB1LPENR_CRCLPEN   ((uint32_t)0x00001000)

#define RCC_AHB1LPENR_FLITFLPEN   ((uint32_t)0x00008000)

#define RCC_AHB1LPENR_SRAM1LPEN   ((uint32_t)0x00010000)

#define RCC_AHB1LPENR_SRAM2LPEN   ((uint32_t)0x00020000)

#define RCC_AHB1LPENR_BKPSRAMLPEN   ((uint32_t)0x00040000)

#define RCC_AHB1LPENR_DMA1LPEN   ((uint32_t)0x00200000)

#define RCC_AHB1LPENR_DMA2LPEN   ((uint32_t)0x00400000)

#define RCC_AHB1LPENR_ETHMACLPEN   ((uint32_t)0x02000000)

#define RCC_AHB1LPENR_ETHMACTXLPEN   ((uint32_t)0x04000000)

#define RCC_AHB1LPENR_ETHMACRXLPEN   ((uint32_t)0x08000000)

#define RCC_AHB1LPENR_ETHMACPTPLPEN   ((uint32_t)0x10000000)

#define RCC_AHB1LPENR_OTGHSLPEN   ((uint32_t)0x20000000)

#define RCC_AHB1LPENR_OTGHSULPILPEN   ((uint32_t)0x40000000)

#define RCC_AHB2LPENR_DCMILPEN   ((uint32_t)0x00000001)

#define RCC_AHB2LPENR_CRYPLPEN   ((uint32_t)0x00000010)

#define RCC_AHB2LPENR_HASHLPEN   ((uint32_t)0x00000020)

#define RCC_AHB2LPENR_RNGLPEN   ((uint32_t)0x00000040)

#define RCC_AHB2LPENR_OTGFSLPEN   ((uint32_t)0x00000080)

#define RCC_AHB3LPENR_FSMCLPEN   ((uint32_t)0x00000001)

#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)

#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)

#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)

#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)

#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)

#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)

#define RCC_APB1LPENR_TIM12LPEN   ((uint32_t)0x00000040)

#define RCC_APB1LPENR_TIM13LPEN   ((uint32_t)0x00000080)

#define RCC_APB1LPENR_TIM14LPEN   ((uint32_t)0x00000100)

#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)

#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)

#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)

#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)

#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)

#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)

#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)

#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)

#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)

#define RCC_APB1LPENR_I2C3LPEN   ((uint32_t)0x00800000)

#define RCC_APB1LPENR_CAN1LPEN   ((uint32_t)0x02000000)

#define RCC_APB1LPENR_CAN2LPEN   ((uint32_t)0x04000000)

#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)

#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)

#define RCC_APB2LPENR_TIM1LPEN   ((uint32_t)0x00000001)

#define RCC_APB2LPENR_TIM8LPEN   ((uint32_t)0x00000002)

#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00000010)

#define RCC_APB2LPENR_USART6LPEN   ((uint32_t)0x00000020)

#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000100)

#define RCC_APB2LPENR_ADC2PEN   ((uint32_t)0x00000200)

#define RCC_APB2LPENR_ADC3LPEN   ((uint32_t)0x00000400)

#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)

#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)

#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00004000)

#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00010000)

#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00020000)

#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00040000)

#define RCC_BDCR_LSEON   ((uint32_t)0x00000001)

#define RCC_BDCR_LSERDY   ((uint32_t)0x00000002)

#define RCC_BDCR_LSEBYP   ((uint32_t)0x00000004)

#define RCC_BDCR_RTCSEL   ((uint32_t)0x00000300)

#define RCC_BDCR_RTCSEL_0   ((uint32_t)0x00000100)

#define RCC_BDCR_RTCSEL_1   ((uint32_t)0x00000200)

#define RCC_BDCR_RTCEN   ((uint32_t)0x00008000)

#define RCC_BDCR_BDRST   ((uint32_t)0x00010000)

#define RCC_CSR_LSION   ((uint32_t)0x00000001)

#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)

#define RCC_CSR_RMVF   ((uint32_t)0x01000000)

#define RCC_CSR_BORRSTF   ((uint32_t)0x02000000)

#define RCC_CSR_PADRSTF   ((uint32_t)0x04000000)

#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)

#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)

#define RCC_CSR_WDGRSTF   ((uint32_t)0x20000000)

#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)

#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)

#define RCC_SSCGR_MODPER   ((uint32_t)0x00001FFF)

#define RCC_SSCGR_INCSTEP   ((uint32_t)0x0FFFE000)

#define RCC_SSCGR_SPREADSEL   ((uint32_t)0x40000000)

#define RCC_SSCGR_SSCGEN   ((uint32_t)0x80000000)

#define RCC_PLLI2SCFGR_PLLI2SN   ((uint32_t)0x00007FC0)

#define RCC_PLLI2SCFGR_PLLI2SR   ((uint32_t)0x70000000)

#define RNG_CR_RNGEN   ((uint32_t)0x00000004)

#define RNG_CR_IE   ((uint32_t)0x00000008)

#define RNG_SR_DRDY   ((uint32_t)0x00000001)

#define RNG_SR_CECS   ((uint32_t)0x00000002)

#define RNG_SR_SECS   ((uint32_t)0x00000004)

#define RNG_SR_CEIS   ((uint32_t)0x00000020)

#define RNG_SR_SEIS   ((uint32_t)0x00000040)

#define RTC_TR_PM   ((uint32_t)0x00400000)

#define RTC_TR_HT   ((uint32_t)0x00300000)

#define RTC_TR_HT_0   ((uint32_t)0x00100000)

#define RTC_TR_HT_1   ((uint32_t)0x00200000)

#define RTC_TR_HU   ((uint32_t)0x000F0000)

#define RTC_TR_HU_0   ((uint32_t)0x00010000)

#define RTC_TR_HU_1   ((uint32_t)0x00020000)

#define RTC_TR_HU_2   ((uint32_t)0x00040000)

#define RTC_TR_HU_3   ((uint32_t)0x00080000)

#define RTC_TR_MNT   ((uint32_t)0x00007000)

#define RTC_TR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TR_MNU   ((uint32_t)0x00000F00)

#define RTC_TR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TR_ST   ((uint32_t)0x00000070)

#define RTC_TR_ST_0   ((uint32_t)0x00000010)

#define RTC_TR_ST_1   ((uint32_t)0x00000020)

#define RTC_TR_ST_2   ((uint32_t)0x00000040)

#define RTC_TR_SU   ((uint32_t)0x0000000F)

#define RTC_TR_SU_0   ((uint32_t)0x00000001)

#define RTC_TR_SU_1   ((uint32_t)0x00000002)

#define RTC_TR_SU_2   ((uint32_t)0x00000004)

#define RTC_TR_SU_3   ((uint32_t)0x00000008)

#define RTC_DR_YT   ((uint32_t)0x00F00000)

#define RTC_DR_YT_0   ((uint32_t)0x00100000)

#define RTC_DR_YT_1   ((uint32_t)0x00200000)

#define RTC_DR_YT_2   ((uint32_t)0x00400000)

#define RTC_DR_YT_3   ((uint32_t)0x00800000)

#define RTC_DR_YU   ((uint32_t)0x000F0000)

#define RTC_DR_YU_0   ((uint32_t)0x00010000)

#define RTC_DR_YU_1   ((uint32_t)0x00020000)

#define RTC_DR_YU_2   ((uint32_t)0x00040000)

#define RTC_DR_YU_3   ((uint32_t)0x00080000)

#define RTC_DR_WDU   ((uint32_t)0x0000E000)

#define RTC_DR_WDU_0   ((uint32_t)0x00002000)

#define RTC_DR_WDU_1   ((uint32_t)0x00004000)

#define RTC_DR_WDU_2   ((uint32_t)0x00008000)

#define RTC_DR_MT   ((uint32_t)0x00001000)

#define RTC_DR_MU   ((uint32_t)0x00000F00)

#define RTC_DR_MU_0   ((uint32_t)0x00000100)

#define RTC_DR_MU_1   ((uint32_t)0x00000200)

#define RTC_DR_MU_2   ((uint32_t)0x00000400)

#define RTC_DR_MU_3   ((uint32_t)0x00000800)

#define RTC_DR_DT   ((uint32_t)0x00000030)

#define RTC_DR_DT_0   ((uint32_t)0x00000010)

#define RTC_DR_DT_1   ((uint32_t)0x00000020)

#define RTC_DR_DU   ((uint32_t)0x0000000F)

#define RTC_DR_DU_0   ((uint32_t)0x00000001)

#define RTC_DR_DU_1   ((uint32_t)0x00000002)

#define RTC_DR_DU_2   ((uint32_t)0x00000004)

#define RTC_DR_DU_3   ((uint32_t)0x00000008)

#define RTC_CR_COE   ((uint32_t)0x00800000)

#define RTC_CR_OSEL   ((uint32_t)0x00600000)

#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)

#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)

#define RTC_CR_POL   ((uint32_t)0x00100000)

#define RTC_CR_COSEL   ((uint32_t)0x00080000)

#define RTC_CR_BCK   ((uint32_t)0x00040000)

#define RTC_CR_SUB1H   ((uint32_t)0x00020000)

#define RTC_CR_ADD1H   ((uint32_t)0x00010000)

#define RTC_CR_TSIE   ((uint32_t)0x00008000)

#define RTC_CR_WUTIE   ((uint32_t)0x00004000)

#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)

#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)

#define RTC_CR_TSE   ((uint32_t)0x00000800)

#define RTC_CR_WUTE   ((uint32_t)0x00000400)

#define RTC_CR_ALRBE   ((uint32_t)0x00000200)

#define RTC_CR_ALRAE   ((uint32_t)0x00000100)

#define RTC_CR_DCE   ((uint32_t)0x00000080)

#define RTC_CR_FMT   ((uint32_t)0x00000040)

#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)

#define RTC_CR_REFCKON   ((uint32_t)0x00000010)

#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)

#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)

#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)

#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)

#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)

#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)

#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)

#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)

#define RTC_ISR_TSF   ((uint32_t)0x00000800)

#define RTC_ISR_WUTF   ((uint32_t)0x00000400)

#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)

#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)

#define RTC_ISR_INIT   ((uint32_t)0x00000080)

#define RTC_ISR_INITF   ((uint32_t)0x00000040)

#define RTC_ISR_RSF   ((uint32_t)0x00000020)

#define RTC_ISR_INITS   ((uint32_t)0x00000010)

#define RTC_ISR_SHPF   ((uint32_t)0x00000008)

#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)

#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)

#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)

#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)

#define RTC_PRER_PREDIV_S   ((uint32_t)0x00001FFF)

#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)

#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)

#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)

#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)

#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)

#define RTC_WPR_KEY   ((uint32_t)0x000000FF)

#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)

#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)

#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)

#define RTC_TSTR_PM   ((uint32_t)0x00400000)

#define RTC_TSTR_HT   ((uint32_t)0x00300000)

#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)

#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)

#define RTC_TSTR_HU   ((uint32_t)0x000F0000)

#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)

#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)

#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)

#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)

#define RTC_TSTR_MNT   ((uint32_t)0x00007000)

#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)

#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TSTR_ST   ((uint32_t)0x00000070)

#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)

#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)

#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)

#define RTC_TSTR_SU   ((uint32_t)0x0000000F)

#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)

#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)

#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)

#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)

#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)

#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)

#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)

#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)

#define RTC_TSDR_MT   ((uint32_t)0x00001000)

#define RTC_TSDR_MU   ((uint32_t)0x00000F00)

#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)

#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)

#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)

#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)

#define RTC_TSDR_DT   ((uint32_t)0x00000030)

#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)

#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)

#define RTC_TSDR_DU   ((uint32_t)0x0000000F)

#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)

#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)

#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)

#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)

#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)

#define RTC_CALR_CALP   ((uint32_t)0x00008000)

#define RTC_CALR_CALW8   ((uint32_t)0x00004000)

#define RTC_CALR_CALW16   ((uint32_t)0x00002000)

#define RTC_CALR_CALM   ((uint32_t)0x000001FF)

#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)

#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)

#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)

#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)

#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)

#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)

#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)

#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)

#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)

#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)

#define RTC_TAFCR_TSINSEL   ((uint32_t)0x00020000)

#define RTC_TAFCR_TAMPINSEL   ((uint32_t)0x00010000)

#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)

#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)

#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)

#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)

#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)

#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)

#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)

#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)

#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)

#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)

#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)

#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)

#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)

#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)

#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)

#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)

#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)

#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)

#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)

#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)

#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)

#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)

#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)

#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)

#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)

#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)

#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)

#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)

#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)

Bit 0

#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)

Bit 1

#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)

Clock divide factor

#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)

Clock enable bit

#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)

Power saving configuration bit

#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)

Clock divider bypass enable bit

#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)

Bit 0

#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)

Bit 1

#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)

HW Flow Control enable

#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)

Command argument

#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)

Command Index

#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)

Bit 0

#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)

Bit 1

#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)

SD I/O suspend command

#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)

Enable CMD completion

#define SDIO_CMD_NIEN   ((uint16_t)0x2000)

Not Interrupt Enable

#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)

CE-ATA command

#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)

Response command index

#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)

Data timeout period.

#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)

Data length value

#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)

Data transfer enabled bit

#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)

Data transfer direction selection

#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)

Data transfer mode selection

#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)

DMA enabled bit

#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)

Bit 0

#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)

Bit 1

#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)

Bit 2

#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)

Bit 3

#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)

Read wait start

#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)

Read wait stop

#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)

Read wait mode

#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)

SD I/O enable functions

#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)

Data count value

#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)

Command response received (CRC check failed)

#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)

Command response timeout

#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)

Data timeout

#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)

Transmit FIFO underrun error

#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)

Received FIFO overrun error

#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)

Command response received (CRC check passed)

#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)

Command sent (no response required)

#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)

Command transfer in progress

#define SDIO_STA_TXACT   ((uint32_t)0x00001000)

Data transmit in progress

#define SDIO_STA_RXACT   ((uint32_t)0x00002000)

Data receive in progress

#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)

Transmit FIFO full

#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)

Receive FIFO full

#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)

Transmit FIFO empty

#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)

Receive FIFO empty

#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)

Data available in transmit FIFO

#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)

Data available in receive FIFO

#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)

SDIO interrupt received

#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)

TXUNDERR flag clear bit

#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)

RXOVERR flag clear bit

#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)

CMDREND flag clear bit

#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)

CMDSENT flag clear bit

#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)

DATAEND flag clear bit

#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)

STBITERR flag clear bit

#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)

DBCKEND flag clear bit

#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)

SDIOIT flag clear bit

#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)

CEATAEND flag clear bit

#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)

Command Sent Interrupt Enable

#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)

Data End Interrupt Enable

#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)

Data Block End Interrupt Enable

#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)

CCommand Acting Interrupt Enable

#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)

Data receive acting interrupt enabled

#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

#define SPI_CR1_CPHA   ((uint16_t)0x0001)

Clock Phase

#define SPI_CR1_CPOL   ((uint16_t)0x0002)

Clock Polarity

#define SPI_CR1_MSTR   ((uint16_t)0x0004)

Master Selection

#define SPI_CR1_BR   ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

#define SPI_CR1_BR_0   ((uint16_t)0x0008)

Bit 0

#define SPI_CR1_BR_1   ((uint16_t)0x0010)

Bit 1

#define SPI_CR1_BR_2   ((uint16_t)0x0020)

Bit 2

#define SPI_CR1_SPE   ((uint16_t)0x0040)

SPI Enable

#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)

Frame Format

#define SPI_CR1_SSI   ((uint16_t)0x0100)

Internal slave select

#define SPI_CR1_SSM   ((uint16_t)0x0200)

Software slave management

#define SPI_CR1_RXONLY   ((uint16_t)0x0400)

Receive only

#define SPI_CR1_DFF   ((uint16_t)0x0800)

Data Frame Format

#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)

Transmit CRC next

#define SPI_CR1_CRCEN   ((uint16_t)0x2000)

Hardware CRC calculation enable

#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)

Output enable in bidirectional mode

#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)

Bidirectional data mode enable

#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)

Rx Buffer DMA Enable

#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)

Tx Buffer DMA Enable

#define SPI_CR2_SSOE   ((uint8_t)0x04)

SS Output Enable

#define SPI_CR2_ERRIE   ((uint8_t)0x20)

Error Interrupt Enable

#define SPI_CR2_RXNEIE   ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

#define SPI_CR2_TXEIE   ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

#define SPI_SR_RXNE   ((uint8_t)0x01)

Receive buffer Not Empty

#define SPI_SR_TXE   ((uint8_t)0x02)

Transmit buffer Empty

#define SPI_SR_CHSIDE   ((uint8_t)0x04)

Channel side

#define SPI_SR_UDR   ((uint8_t)0x08)

Underrun flag

#define SPI_SR_CRCERR   ((uint8_t)0x10)

CRC Error flag

#define SPI_SR_MODF   ((uint8_t)0x20)

Mode fault

#define SPI_SR_OVR   ((uint8_t)0x40)

Overrun flag

#define SPI_SR_BSY   ((uint8_t)0x80)

Busy flag

#define SPI_DR_DR   ((uint16_t)0xFFFF)

Data Register

#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)

CRC polynomial register

#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)

Rx CRC Register

#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)

Tx CRC Register

#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)

Bit 0

#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)

Bit 1

#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)

steady state clock polarity

#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)

Bit 0

#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)

Bit 1

#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)

PCM frame synchronization

#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)

Bit 0

#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)

Bit 1

#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)

I2S Enable

#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)

I2S mode selection

#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)

I2S Linear prescaler

#define SPI_I2SPR_ODD   ((uint16_t)0x0100)

Odd factor for the prescaler

#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)

Master Clock Output Enable

#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)

SYSCFG_Memory Remap Config

#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)

#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)

#define SYSCFG_PMC_MII_RMII_SEL   ((uint32_t)0x00800000)

Ethernet PHY interface selection

#define SYSCFG_PMC_MII_RMII   SYSCFG_PMC_MII_RMII_SEL

#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)

EXTI 0 configuration

#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)

EXTI 1 configuration

#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)

EXTI 2 configuration

#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)

EXTI 3 configuration

#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)

EXTI0 configuration.

PA[0] pin

#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)

PB[0] pin

#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)

PC[0] pin

#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)

PD[0] pin

#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)

PE[0] pin

#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0005)

PF[0] pin

#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0006)

PG[0] pin

#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0007)

PH[0] pin

#define SYSCFG_EXTICR1_EXTI0_PI   ((uint16_t)0x0008)

PI[0] pin

#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)

EXTI1 configuration.

PA[1] pin

#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)

PB[1] pin

#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)

PC[1] pin

#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)

PD[1] pin

#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)

PE[1] pin

#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0050)

PF[1] pin

#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0060)

PG[1] pin

#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0070)

PH[1] pin

#define SYSCFG_EXTICR1_EXTI1_PI   ((uint16_t)0x0080)

PI[1] pin

#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)

EXTI2 configuration.

PA[2] pin

#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)

PB[2] pin

#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)

PC[2] pin

#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)

PD[2] pin

#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)

PE[2] pin

#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0500)

PF[2] pin

#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0600)

PG[2] pin

#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0700)

PH[2] pin

#define SYSCFG_EXTICR1_EXTI2_PI   ((uint16_t)0x0800)

PI[2] pin

#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)

EXTI3 configuration.

PA[3] pin

#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)

PB[3] pin

#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)

PC[3] pin

#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)

PD[3] pin

#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)

PE[3] pin

#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x5000)

PF[3] pin

#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x6000)

PG[3] pin

#define SYSCFG_EXTICR1_EXTI3_PH   ((uint16_t)0x7000)

PH[3] pin

#define SYSCFG_EXTICR1_EXTI3_PI   ((uint16_t)0x8000)

PI[3] pin

#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)

EXTI 4 configuration

#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)

EXTI 5 configuration

#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)

EXTI 6 configuration

#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)

EXTI 7 configuration

#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)

EXTI4 configuration.

PA[4] pin

#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)

PB[4] pin

#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)

PC[4] pin

#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)

PD[4] pin

#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)

PE[4] pin

#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0005)

PF[4] pin

#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0006)

PG[4] pin

#define SYSCFG_EXTICR2_EXTI4_PH   ((uint16_t)0x0007)

PH[4] pin

#define SYSCFG_EXTICR2_EXTI4_PI   ((uint16_t)0x0008)

PI[4] pin

#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)

EXTI5 configuration.

PA[5] pin

#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)

PB[5] pin

#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)

PC[5] pin

#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)

PD[5] pin

#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)

PE[5] pin

#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0050)

PF[5] pin

#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0060)

PG[5] pin

#define SYSCFG_EXTICR2_EXTI5_PH   ((uint16_t)0x0070)

PH[5] pin

#define SYSCFG_EXTICR2_EXTI5_PI   ((uint16_t)0x0080)

PI[5] pin

#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)

EXTI6 configuration.

PA[6] pin

#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)

PB[6] pin

#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)

PC[6] pin

#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)

PD[6] pin

#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)

PE[6] pin

#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0500)

PF[6] pin

#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0600)

PG[6] pin

#define SYSCFG_EXTICR2_EXTI6_PH   ((uint16_t)0x0700)

PH[6] pin

#define SYSCFG_EXTICR2_EXTI6_PI   ((uint16_t)0x0800)

PI[6] pin

#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)

EXTI7 configuration.

PA[7] pin

#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)

PB[7] pin

#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)

PC[7] pin

#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)

PD[7] pin

#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)

PE[7] pin

#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x5000)

PF[7] pin

#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x6000)

PG[7] pin

#define SYSCFG_EXTICR2_EXTI7_PH   ((uint16_t)0x7000)

PH[7] pin

#define SYSCFG_EXTICR2_EXTI7_PI   ((uint16_t)0x8000)

PI[7] pin

#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)

EXTI 8 configuration

#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)

EXTI 9 configuration

#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)

EXTI 10 configuration

#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)

EXTI 11 configuration

#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)

EXTI8 configuration.

PA[8] pin

#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)

PB[8] pin

#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)

PC[8] pin

#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)

PD[8] pin

#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)

PE[8] pin

#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0005)

PF[8] pin

#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0006)

PG[8] pin

#define SYSCFG_EXTICR3_EXTI8_PH   ((uint16_t)0x0007)

PH[8] pin

#define SYSCFG_EXTICR3_EXTI8_PI   ((uint16_t)0x0008)

PI[8] pin

#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)

EXTI9 configuration.

PA[9] pin

#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)

PB[9] pin

#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)

PC[9] pin

#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)

PD[9] pin

#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)

PE[9] pin

#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0050)

PF[9] pin

#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0060)

PG[9] pin

#define SYSCFG_EXTICR3_EXTI9_PH   ((uint16_t)0x0070)

PH[9] pin

#define SYSCFG_EXTICR3_EXTI9_PI   ((uint16_t)0x0080)

PI[9] pin

#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)

EXTI10 configuration.

PA[10] pin

#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)

PB[10] pin

#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)

PC[10] pin

#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)

PD[10] pin

#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)

PE[10] pin

#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0500)

PF[10] pin

#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0600)

PG[10] pin

#define SYSCFG_EXTICR3_EXTI10_PH   ((uint16_t)0x0700)

PH[10] pin

#define SYSCFG_EXTICR3_EXTI10_PI   ((uint16_t)0x0800)

PI[10] pin

#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)

EXTI11 configuration.

PA[11] pin

#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)

PB[11] pin

#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)

PC[11] pin

#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)

PD[11] pin

#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)

PE[11] pin

#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x5000)

PF[11] pin

#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x6000)

PG[11] pin

#define SYSCFG_EXTICR3_EXTI11_PH   ((uint16_t)0x7000)

PH[11] pin

#define SYSCFG_EXTICR3_EXTI11_PI   ((uint16_t)0x8000)

PI[11] pin

#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)

EXTI 12 configuration

#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)

EXTI 13 configuration

#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)

EXTI 14 configuration

#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)

EXTI 15 configuration

#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)

EXTI12 configuration.

PA[12] pin

#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)

PB[12] pin

#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)

PC[12] pin

#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)

PD[12] pin

#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)

PE[12] pin

#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0005)

PF[12] pin

#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0006)

PG[12] pin

#define SYSCFG_EXTICR3_EXTI12_PH   ((uint16_t)0x0007)

PH[12] pin

#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)

EXTI13 configuration.

PA[13] pin

#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)

PB[13] pin

#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)

PC[13] pin

#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)

PD[13] pin

#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)

PE[13] pin

#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0050)

PF[13] pin

#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0060)

PG[13] pin

#define SYSCFG_EXTICR3_EXTI13_PH   ((uint16_t)0x0070)

PH[13] pin

#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)

EXTI14 configuration.

PA[14] pin

#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)

PB[14] pin

#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)

PC[14] pin

#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)

PD[14] pin

#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)

PE[14] pin

#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0500)

PF[14] pin

#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0600)

PG[14] pin

#define SYSCFG_EXTICR3_EXTI14_PH   ((uint16_t)0x0700)

PH[14] pin

#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)

EXTI15 configuration.

PA[15] pin

#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)

PB[15] pin

#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)

PC[15] pin

#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)

PD[15] pin

#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)

PE[15] pin

#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x5000)

PF[15] pin

#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x6000)

PG[15] pin

#define SYSCFG_EXTICR3_EXTI15_PH   ((uint16_t)0x7000)

PH[15] pin

#define SYSCFG_CMPCR_CMP_PD   ((uint32_t)0x00000001)

Compensation cell ready flag

#define SYSCFG_CMPCR_READY   ((uint32_t)0x00000100)

Compensation cell power-down

#define TIM_CR1_CEN   ((uint16_t)0x0001)

Counter enable

#define TIM_CR1_UDIS   ((uint16_t)0x0002)

Update disable

#define TIM_CR1_URS   ((uint16_t)0x0004)

Update request source

#define TIM_CR1_OPM   ((uint16_t)0x0008)

One pulse mode

#define TIM_CR1_DIR   ((uint16_t)0x0010)

Direction

#define TIM_CR1_CMS   ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

#define TIM_CR1_CMS_0   ((uint16_t)0x0020)

Bit 0

#define TIM_CR1_CMS_1   ((uint16_t)0x0040)

Bit 1

#define TIM_CR1_ARPE   ((uint16_t)0x0080)

Auto-reload preload enable

#define TIM_CR1_CKD   ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

#define TIM_CR1_CKD_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CR1_CKD_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CR2_CCPC   ((uint16_t)0x0001)

Capture/Compare Preloaded Control

#define TIM_CR2_CCUS   ((uint16_t)0x0004)

Capture/Compare Control Update Selection

#define TIM_CR2_CCDS   ((uint16_t)0x0008)

Capture/Compare DMA Selection

#define TIM_CR2_MMS   ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

#define TIM_CR2_MMS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CR2_MMS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CR2_MMS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CR2_TI1S   ((uint16_t)0x0080)

TI1 Selection

#define TIM_CR2_OIS1   ((uint16_t)0x0100)

Output Idle state 1 (OC1 output)

#define TIM_CR2_OIS1N   ((uint16_t)0x0200)

Output Idle state 1 (OC1N output)

#define TIM_CR2_OIS2   ((uint16_t)0x0400)

Output Idle state 2 (OC2 output)

#define TIM_CR2_OIS2N   ((uint16_t)0x0800)

Output Idle state 2 (OC2N output)

#define TIM_CR2_OIS3   ((uint16_t)0x1000)

Output Idle state 3 (OC3 output)

#define TIM_CR2_OIS3N   ((uint16_t)0x2000)

Output Idle state 3 (OC3N output)

#define TIM_CR2_OIS4   ((uint16_t)0x4000)

Output Idle state 4 (OC4 output)

#define TIM_SMCR_SMS   ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)

Bit 0

#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)

Bit 1

#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)

Bit 2

#define TIM_SMCR_TS   ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

#define TIM_SMCR_TS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_SMCR_TS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_SMCR_TS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_SMCR_MSM   ((uint16_t)0x0080)

Master/slave mode

#define TIM_SMCR_ETF   ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)

Bit 0

#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)

Bit 1

#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)

Bit 2

#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)

Bit 3

#define TIM_SMCR_ETPS   ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)

Bit 0

#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)

Bit 1

#define TIM_SMCR_ECE   ((uint16_t)0x4000)

External clock enable

#define TIM_SMCR_ETP   ((uint16_t)0x8000)

External trigger polarity

#define TIM_DIER_UIE   ((uint16_t)0x0001)

Update interrupt enable

#define TIM_DIER_CC1IE   ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

#define TIM_DIER_CC2IE   ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

#define TIM_DIER_CC3IE   ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

#define TIM_DIER_CC4IE   ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

#define TIM_DIER_COMIE   ((uint16_t)0x0020)

COM interrupt enable

#define TIM_DIER_TIE   ((uint16_t)0x0040)

Trigger interrupt enable

#define TIM_DIER_BIE   ((uint16_t)0x0080)

Break interrupt enable

#define TIM_DIER_UDE   ((uint16_t)0x0100)

Update DMA request enable

#define TIM_DIER_CC1DE   ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

#define TIM_DIER_CC2DE   ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

#define TIM_DIER_CC3DE   ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

#define TIM_DIER_CC4DE   ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

#define TIM_DIER_COMDE   ((uint16_t)0x2000)

COM DMA request enable

#define TIM_DIER_TDE   ((uint16_t)0x4000)

Trigger DMA request enable

#define TIM_SR_UIF   ((uint16_t)0x0001)

Update interrupt Flag

#define TIM_SR_CC1IF   ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

#define TIM_SR_CC2IF   ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

#define TIM_SR_CC3IF   ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

#define TIM_SR_CC4IF   ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

#define TIM_SR_COMIF   ((uint16_t)0x0020)

COM interrupt Flag

#define TIM_SR_TIF   ((uint16_t)0x0040)

Trigger interrupt Flag

#define TIM_SR_BIF   ((uint16_t)0x0080)

Break interrupt Flag

#define TIM_SR_CC1OF   ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

#define TIM_SR_CC2OF   ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

#define TIM_SR_CC3OF   ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

#define TIM_SR_CC4OF   ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

#define TIM_EGR_UG   ((uint8_t)0x01)

Update Generation

#define TIM_EGR_CC1G   ((uint8_t)0x02)

Capture/Compare 1 Generation

#define TIM_EGR_CC2G   ((uint8_t)0x04)

Capture/Compare 2 Generation

#define TIM_EGR_CC3G   ((uint8_t)0x08)

Capture/Compare 3 Generation

#define TIM_EGR_CC4G   ((uint8_t)0x10)

Capture/Compare 4 Generation

#define TIM_EGR_COMG   ((uint8_t)0x20)

Capture/Compare Control Update Generation

#define TIM_EGR_TG   ((uint8_t)0x40)

Trigger Generation

#define TIM_EGR_BG   ((uint8_t)0x80)

Break Generation

#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)

Output Compare 1 Fast enable

#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)

Output Compare 1 Preload enable

#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)

Output Compare 1Clear Enable

#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)

Output Compare 2 Fast enable

#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)

Output Compare 2 Preload enable

#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)

Output Compare 2 Clear Enable

#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)

Output Compare 3 Fast enable

#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)

Output Compare 3 Preload enable

#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)

Output Compare 3 Clear Enable

#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)

Output Compare 4 Fast enable

#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)

Output Compare 4 Preload enable

#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)

Output Compare 4 Clear Enable

#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCER_CC1E   ((uint16_t)0x0001)

Capture/Compare 1 output enable

#define TIM_CCER_CC1P   ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

#define TIM_CCER_CC1NE   ((uint16_t)0x0004)

Capture/Compare 1 Complementary output enable

#define TIM_CCER_CC1NP   ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

#define TIM_CCER_CC2E   ((uint16_t)0x0010)

Capture/Compare 2 output enable

#define TIM_CCER_CC2P   ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

#define TIM_CCER_CC2NE   ((uint16_t)0x0040)

Capture/Compare 2 Complementary output enable

#define TIM_CCER_CC2NP   ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

#define TIM_CCER_CC3E   ((uint16_t)0x0100)

Capture/Compare 3 output enable

#define TIM_CCER_CC3P   ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

#define TIM_CCER_CC3NE   ((uint16_t)0x0400)

Capture/Compare 3 Complementary output enable

#define TIM_CCER_CC3NP   ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

#define TIM_CCER_CC4E   ((uint16_t)0x1000)

Capture/Compare 4 output enable

#define TIM_CCER_CC4P   ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

#define TIM_CCER_CC4NP   ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

#define TIM_CNT_CNT   ((uint16_t)0xFFFF)

Counter Value

#define TIM_PSC_PSC   ((uint16_t)0xFFFF)

Prescaler Value

#define TIM_ARR_ARR   ((uint16_t)0xFFFF)

actual auto-reload Value

#define TIM_RCR_REP   ((uint8_t)0xFF)

Repetition Counter Value

#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)

Capture/Compare 1 Value

#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)

Capture/Compare 2 Value

#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)

Capture/Compare 3 Value

#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)

Capture/Compare 4 Value

#define TIM_BDTR_DTG   ((uint16_t)0x00FF)

DTG[0:7] bits (Dead-Time Generator set-up)

#define TIM_BDTR_DTG_0   ((uint16_t)0x0001)

Bit 0

#define TIM_BDTR_DTG_1   ((uint16_t)0x0002)

Bit 1

#define TIM_BDTR_DTG_2   ((uint16_t)0x0004)

Bit 2

#define TIM_BDTR_DTG_3   ((uint16_t)0x0008)

Bit 3

#define TIM_BDTR_DTG_4   ((uint16_t)0x0010)

Bit 4

#define TIM_BDTR_DTG_5   ((uint16_t)0x0020)

Bit 5

#define TIM_BDTR_DTG_6   ((uint16_t)0x0040)

Bit 6

#define TIM_BDTR_DTG_7   ((uint16_t)0x0080)

Bit 7

#define TIM_BDTR_LOCK   ((uint16_t)0x0300)

LOCK[1:0] bits (Lock Configuration)

#define TIM_BDTR_LOCK_0   ((uint16_t)0x0100)

Bit 0

#define TIM_BDTR_LOCK_1   ((uint16_t)0x0200)

Bit 1

#define TIM_BDTR_OSSI   ((uint16_t)0x0400)

Off-State Selection for Idle mode

#define TIM_BDTR_OSSR   ((uint16_t)0x0800)

Off-State Selection for Run mode

#define TIM_BDTR_BKE   ((uint16_t)0x1000)

Break enable

#define TIM_BDTR_BKP   ((uint16_t)0x2000)

Break Polarity

#define TIM_BDTR_AOE   ((uint16_t)0x4000)

Automatic Output enable

#define TIM_BDTR_MOE   ((uint16_t)0x8000)

Main Output enable

#define TIM_DCR_DBA   ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

#define TIM_DCR_DBA_0   ((uint16_t)0x0001)

Bit 0

#define TIM_DCR_DBA_1   ((uint16_t)0x0002)

Bit 1

#define TIM_DCR_DBA_2   ((uint16_t)0x0004)

Bit 2

#define TIM_DCR_DBA_3   ((uint16_t)0x0008)

Bit 3

#define TIM_DCR_DBA_4   ((uint16_t)0x0010)

Bit 4

#define TIM_DCR_DBL   ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

#define TIM_DCR_DBL_0   ((uint16_t)0x0100)

Bit 0

#define TIM_DCR_DBL_1   ((uint16_t)0x0200)

Bit 1

#define TIM_DCR_DBL_2   ((uint16_t)0x0400)

Bit 2

#define TIM_DCR_DBL_3   ((uint16_t)0x0800)

Bit 3

#define TIM_DCR_DBL_4   ((uint16_t)0x1000)

Bit 4

#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)

DMA register for burst accesses

#define TIM_OR_TI4_RMP   ((uint16_t)0x00C0)

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

#define TIM_OR_TI4_RMP_0   ((uint16_t)0x0040)

Bit 0

#define TIM_OR_TI4_RMP_1   ((uint16_t)0x0080)

Bit 1

#define TIM_OR_ITR1_RMP   ((uint16_t)0x0C00)

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

#define TIM_OR_ITR1_RMP_0   ((uint16_t)0x0400)

Bit 0

#define TIM_OR_ITR1_RMP_1   ((uint16_t)0x0800)

Bit 1

#define USART_SR_PE   ((uint16_t)0x0001)

Parity Error

#define USART_SR_FE   ((uint16_t)0x0002)

Framing Error

#define USART_SR_NE   ((uint16_t)0x0004)

Noise Error Flag

#define USART_SR_ORE   ((uint16_t)0x0008)

OverRun Error

#define USART_SR_IDLE   ((uint16_t)0x0010)

IDLE line detected

#define USART_SR_RXNE   ((uint16_t)0x0020)

Read Data Register Not Empty

#define USART_SR_TC   ((uint16_t)0x0040)

Transmission Complete

#define USART_SR_TXE   ((uint16_t)0x0080)

Transmit Data Register Empty

#define USART_SR_LBD   ((uint16_t)0x0100)

LIN Break Detection Flag

#define USART_SR_CTS   ((uint16_t)0x0200)

CTS Flag

#define USART_DR_DR   ((uint16_t)0x01FF)

Data value

#define USART_BRR_DIV_Fraction   ((uint16_t)0x000F)

Fraction of USARTDIV

#define USART_BRR_DIV_Mantissa   ((uint16_t)0xFFF0)

Mantissa of USARTDIV

#define USART_CR1_SBK   ((uint16_t)0x0001)

Send Break

#define USART_CR1_RWU   ((uint16_t)0x0002)

Receiver wakeup

#define USART_CR1_RE   ((uint16_t)0x0004)

Receiver Enable

#define USART_CR1_TE   ((uint16_t)0x0008)

Transmitter Enable

#define USART_CR1_IDLEIE   ((uint16_t)0x0010)

IDLE Interrupt Enable

#define USART_CR1_RXNEIE   ((uint16_t)0x0020)

RXNE Interrupt Enable

#define USART_CR1_TCIE   ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

#define USART_CR1_TXEIE   ((uint16_t)0x0080)

PE Interrupt Enable

#define USART_CR1_PEIE   ((uint16_t)0x0100)

PE Interrupt Enable

#define USART_CR1_PS   ((uint16_t)0x0200)

Parity Selection

#define USART_CR1_PCE   ((uint16_t)0x0400)

Parity Control Enable

#define USART_CR1_WAKE   ((uint16_t)0x0800)

Wakeup method

#define USART_CR1_M   ((uint16_t)0x1000)

Word length

#define USART_CR1_UE   ((uint16_t)0x2000)

USART Enable

#define USART_CR1_OVER8   ((uint16_t)0x8000)

USART Oversampling by 8 enable

#define USART_CR2_ADD   ((uint16_t)0x000F)

Address of the USART node

#define USART_CR2_LBDL   ((uint16_t)0x0020)

LIN Break Detection Length

#define USART_CR2_LBDIE   ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

#define USART_CR2_LBCL   ((uint16_t)0x0100)

Last Bit Clock pulse

#define USART_CR2_CPHA   ((uint16_t)0x0200)

Clock Phase

#define USART_CR2_CPOL   ((uint16_t)0x0400)

Clock Polarity

#define USART_CR2_CLKEN   ((uint16_t)0x0800)

Clock Enable

#define USART_CR2_STOP   ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

#define USART_CR2_STOP_0   ((uint16_t)0x1000)

Bit 0

#define USART_CR2_STOP_1   ((uint16_t)0x2000)

Bit 1

#define USART_CR2_LINEN   ((uint16_t)0x4000)

LIN mode enable

#define USART_CR3_EIE   ((uint16_t)0x0001)

Error Interrupt Enable

#define USART_CR3_IREN   ((uint16_t)0x0002)

IrDA mode Enable

#define USART_CR3_IRLP   ((uint16_t)0x0004)

IrDA Low-Power

#define USART_CR3_HDSEL   ((uint16_t)0x0008)

Half-Duplex Selection

#define USART_CR3_NACK   ((uint16_t)0x0010)

Smartcard NACK enable

#define USART_CR3_SCEN   ((uint16_t)0x0020)

Smartcard mode enable

#define USART_CR3_DMAR   ((uint16_t)0x0040)

DMA Enable Receiver

#define USART_CR3_DMAT   ((uint16_t)0x0080)

DMA Enable Transmitter

#define USART_CR3_RTSE   ((uint16_t)0x0100)

RTS Enable

#define USART_CR3_CTSE   ((uint16_t)0x0200)

CTS Enable

#define USART_CR3_CTSIE   ((uint16_t)0x0400)

CTS Interrupt Enable

#define USART_CR3_ONEBIT   ((uint16_t)0x0800)

USART One bit method enable

#define USART_GTPR_PSC   ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

#define USART_GTPR_PSC_0   ((uint16_t)0x0001)

Bit 0

#define USART_GTPR_PSC_1   ((uint16_t)0x0002)

Bit 1

#define USART_GTPR_PSC_2   ((uint16_t)0x0004)

Bit 2

#define USART_GTPR_PSC_3   ((uint16_t)0x0008)

Bit 3

#define USART_GTPR_PSC_4   ((uint16_t)0x0010)

Bit 4

#define USART_GTPR_PSC_5   ((uint16_t)0x0020)

Bit 5

#define USART_GTPR_PSC_6   ((uint16_t)0x0040)

Bit 6

#define USART_GTPR_PSC_7   ((uint16_t)0x0080)

Bit 7

#define USART_GTPR_GT   ((uint16_t)0xFF00)

Guard time value

#define WWDG_CR_T   ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

#define WWDG_CR_T0   ((uint8_t)0x01)

Bit 0

#define WWDG_CR_T1   ((uint8_t)0x02)

Bit 1

#define WWDG_CR_T2   ((uint8_t)0x04)

Bit 2

#define WWDG_CR_T3   ((uint8_t)0x08)

Bit 3

#define WWDG_CR_T4   ((uint8_t)0x10)

Bit 4

#define WWDG_CR_T5   ((uint8_t)0x20)

Bit 5

#define WWDG_CR_T6   ((uint8_t)0x40)

Bit 6

#define WWDG_CR_WDGA   ((uint8_t)0x80)

Activation bit

#define WWDG_CFR_W   ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

#define WWDG_CFR_W0   ((uint16_t)0x0001)

Bit 0

#define WWDG_CFR_W1   ((uint16_t)0x0002)

Bit 1

#define WWDG_CFR_W2   ((uint16_t)0x0004)

Bit 2

#define WWDG_CFR_W3   ((uint16_t)0x0008)

Bit 3

#define WWDG_CFR_W4   ((uint16_t)0x0010)

Bit 4

#define WWDG_CFR_W5   ((uint16_t)0x0020)

Bit 5

#define WWDG_CFR_W6   ((uint16_t)0x0040)

Bit 6

#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)

Bit 0

#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)

Bit 1

#define WWDG_CFR_EWI   ((uint16_t)0x0200)

Early Wakeup Interrupt

#define WWDG_SR_EWIF   ((uint8_t)0x01)

Early Wakeup Interrupt Flag

#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)

#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)

#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)

#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)

#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)

#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)

#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)

#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)

Bit 0

#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)

Bit 1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)

#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   ((uint32_t)0x00000040)

#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   ((uint32_t)0x00000080)

#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   ((uint32_t)0x00000100)

#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)

#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   ((uint32_t)0x02000000)

#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   ((uint32_t)0x04000000)

#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_TIM1_STOP   ((uint32_t)0x00000001)

#define DBGMCU_APB1_FZ_DBG_TIM8_STOP   ((uint32_t)0x00000002)

#define DBGMCU_APB1_FZ_DBG_TIM9_STOP   ((uint32_t)0x00010000)

#define DBGMCU_APB1_FZ_DBG_TIM10_STOP   ((uint32_t)0x00020000)

#define DBGMCU_APB1_FZ_DBG_TIM11_STOP   ((uint32_t)0x00040000)

#define ETH_MACCR_WD   ((uint32_t)0x00800000)

#define ETH_MACCR_JD   ((uint32_t)0x00400000)

#define ETH_MACCR_IFG   ((uint32_t)0x000E0000)

#define ETH_MACCR_IFG_96Bit   ((uint32_t)0x00000000)

#define ETH_MACCR_IFG_88Bit   ((uint32_t)0x00020000)

#define ETH_MACCR_IFG_80Bit   ((uint32_t)0x00040000)

#define ETH_MACCR_IFG_72Bit   ((uint32_t)0x00060000)

#define ETH_MACCR_IFG_64Bit   ((uint32_t)0x00080000)

#define ETH_MACCR_IFG_56Bit   ((uint32_t)0x000A0000)

#define ETH_MACCR_IFG_48Bit   ((uint32_t)0x000C0000)

#define ETH_MACCR_IFG_40Bit   ((uint32_t)0x000E0000)

#define ETH_MACCR_CSD   ((uint32_t)0x00010000)

#define ETH_MACCR_FES   ((uint32_t)0x00004000)

#define ETH_MACCR_ROD   ((uint32_t)0x00002000)

#define ETH_MACCR_LM   ((uint32_t)0x00001000)

#define ETH_MACCR_DM   ((uint32_t)0x00000800)

#define ETH_MACCR_IPCO   ((uint32_t)0x00000400)

#define ETH_MACCR_RD   ((uint32_t)0x00000200)

#define ETH_MACCR_APCS   ((uint32_t)0x00000080)

#define ETH_MACCR_BL   ((uint32_t)0x00000060)

#define ETH_MACCR_BL_10   ((uint32_t)0x00000000)

#define ETH_MACCR_BL_8   ((uint32_t)0x00000020)

#define ETH_MACCR_BL_4   ((uint32_t)0x00000040)

#define ETH_MACCR_BL_1   ((uint32_t)0x00000060)

#define ETH_MACCR_DC   ((uint32_t)0x00000010)

#define ETH_MACCR_TE   ((uint32_t)0x00000008)

#define ETH_MACCR_RE   ((uint32_t)0x00000004)

#define ETH_MACFFR_RA   ((uint32_t)0x80000000)

#define ETH_MACFFR_HPF   ((uint32_t)0x00000400)

#define ETH_MACFFR_SAF   ((uint32_t)0x00000200)

#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)

#define ETH_MACFFR_PCF   ((uint32_t)0x000000C0)

#define ETH_MACFFR_PCF_BlockAll   ((uint32_t)0x00000040)

#define ETH_MACFFR_PCF_ForwardAll   ((uint32_t)0x00000080)

#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   ((uint32_t)0x000000C0)

#define ETH_MACFFR_BFD   ((uint32_t)0x00000020)

#define ETH_MACFFR_PAM   ((uint32_t)0x00000010)

#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)

#define ETH_MACFFR_HM   ((uint32_t)0x00000004)

#define ETH_MACFFR_HU   ((uint32_t)0x00000002)

#define ETH_MACFFR_PM   ((uint32_t)0x00000001)

#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)

#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)

#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)

#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)

#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)

#define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)

#define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)

#define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)

#define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)

#define ETH_MACMIIAR_CR_Div102   ((uint32_t)0x00000010)

#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)

#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)

#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)

#define ETH_MACFCR_PT   ((uint32_t)0xFFFF0000)

#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)

#define ETH_MACFCR_PLT   ((uint32_t)0x00000030)

#define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)

#define ETH_MACFCR_PLT_Minus28   ((uint32_t)0x00000010)

#define ETH_MACFCR_PLT_Minus144   ((uint32_t)0x00000020)

#define ETH_MACFCR_PLT_Minus256   ((uint32_t)0x00000030)

#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)

#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)

#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)

#define ETH_MACFCR_FCBBPA   ((uint32_t)0x00000001)

#define ETH_MACVLANTR_VLANTC   ((uint32_t)0x00010000)

#define ETH_MACVLANTR_VLANTI   ((uint32_t)0x0000FFFF)

#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)

#define ETH_MACPMTCSR_WFFRPR   ((uint32_t)0x80000000)

#define ETH_MACPMTCSR_GU   ((uint32_t)0x00000200)

#define ETH_MACPMTCSR_WFR   ((uint32_t)0x00000040)

#define ETH_MACPMTCSR_MPR   ((uint32_t)0x00000020)

#define ETH_MACPMTCSR_WFE   ((uint32_t)0x00000004)

#define ETH_MACPMTCSR_MPE   ((uint32_t)0x00000002)

#define ETH_MACPMTCSR_PD   ((uint32_t)0x00000001)

#define ETH_MACSR_TSTS   ((uint32_t)0x00000200)

#define ETH_MACSR_MMCTS   ((uint32_t)0x00000040)

#define ETH_MACSR_MMMCRS   ((uint32_t)0x00000020)

#define ETH_MACSR_MMCS   ((uint32_t)0x00000010)

#define ETH_MACSR_PMTS   ((uint32_t)0x00000008)

#define ETH_MACIMR_TSTIM   ((uint32_t)0x00000200)

#define ETH_MACIMR_PMTIM   ((uint32_t)0x00000008)

#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)

#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA1HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA1HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA1HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA1HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA1HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA1HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA1HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)

#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA2HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA2HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA2HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA2HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA2HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA2HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA2HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)

#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)

#define ETH_MACA3HR_AE   ((uint32_t)0x80000000)

#define ETH_MACA3HR_SA   ((uint32_t)0x40000000)

#define ETH_MACA3HR_MBC   ((uint32_t)0x3F000000)

#define ETH_MACA3HR_MBC_HBits15_8   ((uint32_t)0x20000000)

#define ETH_MACA3HR_MBC_HBits7_0   ((uint32_t)0x10000000)

#define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)

#define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)

#define ETH_MACA3HR_MBC_LBits15_8   ((uint32_t)0x02000000)

#define ETH_MACA3HR_MBC_LBits7_0   ((uint32_t)0x01000000)

#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)

#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCCR_MCFHP   ((uint32_t)0x00000020)

#define ETH_MMCCR_MCP   ((uint32_t)0x00000010)

#define ETH_MMCCR_MCF   ((uint32_t)0x00000008)

#define ETH_MMCCR_ROR   ((uint32_t)0x00000004)

#define ETH_MMCCR_CSR   ((uint32_t)0x00000002)

#define ETH_MMCCR_CR   ((uint32_t)0x00000001)

#define ETH_MMCRIR_RGUFS   ((uint32_t)0x00020000)

#define ETH_MMCRIR_RFAES   ((uint32_t)0x00000040)

#define ETH_MMCRIR_RFCES   ((uint32_t)0x00000020)

#define ETH_MMCTIR_TGFS   ((uint32_t)0x00200000)

#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)

#define ETH_MMCTIR_TGFSCS   ((uint32_t)0x00004000)

#define ETH_MMCRIMR_RGUFM   ((uint32_t)0x00020000)

#define ETH_MMCRIMR_RFAEM   ((uint32_t)0x00000040)

#define ETH_MMCRIMR_RFCEM   ((uint32_t)0x00000020)

#define ETH_MMCTIMR_TGFM   ((uint32_t)0x00200000)

#define ETH_MMCTIMR_TGFMSCM   ((uint32_t)0x00008000)

#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)

#define ETH_MMCTGFSCCR_TGFSCC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCTGFCR_TGFC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRFCECR_RFCEC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRFAECR_RFAEC   ((uint32_t)0xFFFFFFFF)

#define ETH_MMCRGUFCR_RGUFC   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSCR_TSCNT   ((uint32_t)0x00030000)

#define ETH_PTPTSSR_TSSMRME   ((uint32_t)0x00008000)

#define ETH_PTPTSSR_TSSEME   ((uint32_t)0x00004000)

#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)

#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)

#define ETH_PTPTSSR_TSSPTPOEFE   ((uint32_t)0x00000800)

#define ETH_PTPTSSR_TSPTPPSV2E   ((uint32_t)0x00000400)

#define ETH_PTPTSSR_TSSSR   ((uint32_t)0x00000200)

#define ETH_PTPTSSR_TSSARFE   ((uint32_t)0x00000100)

#define ETH_PTPTSCR_TSARU   ((uint32_t)0x00000020)

#define ETH_PTPTSCR_TSITE   ((uint32_t)0x00000010)

#define ETH_PTPTSCR_TSSTU   ((uint32_t)0x00000008)

#define ETH_PTPTSCR_TSSTI   ((uint32_t)0x00000004)

#define ETH_PTPTSCR_TSFCU   ((uint32_t)0x00000002)

#define ETH_PTPTSCR_TSE   ((uint32_t)0x00000001)

#define ETH_PTPSSIR_STSSI   ((uint32_t)0x000000FF)

#define ETH_PTPTSHR_STS   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSLR_STPNS   ((uint32_t)0x80000000)

#define ETH_PTPTSLR_STSS   ((uint32_t)0x7FFFFFFF)

#define ETH_PTPTSHUR_TSUS   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSLUR_TSUPNS   ((uint32_t)0x80000000)

#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)

#define ETH_PTPTSAR_TSA   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTTHR_TTSH   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTTLR_TTSL   ((uint32_t)0xFFFFFFFF)

#define ETH_PTPTSSR_TSTTR   ((uint32_t)0x00000020)

#define ETH_PTPTSSR_TSSO   ((uint32_t)0x00000010)

#define ETH_DMABMR_AAB   ((uint32_t)0x02000000)

#define ETH_DMABMR_FPM   ((uint32_t)0x01000000)

#define ETH_DMABMR_USP   ((uint32_t)0x00800000)

#define ETH_DMABMR_RDP   ((uint32_t)0x007E0000)

#define ETH_DMABMR_RDP_1Beat   ((uint32_t)0x00020000)

#define ETH_DMABMR_RDP_2Beat   ((uint32_t)0x00040000)

#define ETH_DMABMR_RDP_4Beat   ((uint32_t)0x00080000)

#define ETH_DMABMR_RDP_8Beat   ((uint32_t)0x00100000)

#define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)

#define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)

#define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)

#define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)

#define ETH_DMABMR_RDP_4xPBL_16Beat   ((uint32_t)0x01080000)

#define ETH_DMABMR_RDP_4xPBL_32Beat   ((uint32_t)0x01100000)

#define ETH_DMABMR_RDP_4xPBL_64Beat   ((uint32_t)0x01200000)

#define ETH_DMABMR_RDP_4xPBL_128Beat   ((uint32_t)0x01400000)

#define ETH_DMABMR_FB   ((uint32_t)0x00010000)

#define ETH_DMABMR_RTPR   ((uint32_t)0x0000C000)

#define ETH_DMABMR_RTPR_1_1   ((uint32_t)0x00000000)

#define ETH_DMABMR_RTPR_2_1   ((uint32_t)0x00004000)

#define ETH_DMABMR_RTPR_3_1   ((uint32_t)0x00008000)

#define ETH_DMABMR_RTPR_4_1   ((uint32_t)0x0000C000)

#define ETH_DMABMR_PBL   ((uint32_t)0x00003F00)

#define ETH_DMABMR_PBL_1Beat   ((uint32_t)0x00000100)

#define ETH_DMABMR_PBL_2Beat   ((uint32_t)0x00000200)

#define ETH_DMABMR_PBL_4Beat   ((uint32_t)0x00000400)

#define ETH_DMABMR_PBL_8Beat   ((uint32_t)0x00000800)

#define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)

#define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)

#define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)

#define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)

#define ETH_DMABMR_PBL_4xPBL_16Beat   ((uint32_t)0x01000400)

#define ETH_DMABMR_PBL_4xPBL_32Beat   ((uint32_t)0x01000800)

#define ETH_DMABMR_PBL_4xPBL_64Beat   ((uint32_t)0x01001000)

#define ETH_DMABMR_PBL_4xPBL_128Beat   ((uint32_t)0x01002000)

#define ETH_DMABMR_EDE   ((uint32_t)0x00000080)

#define ETH_DMABMR_DSL   ((uint32_t)0x0000007C)

#define ETH_DMABMR_DA   ((uint32_t)0x00000002)

#define ETH_DMABMR_SR   ((uint32_t)0x00000001)

#define ETH_DMATPDR_TPD   ((uint32_t)0xFFFFFFFF)

#define ETH_DMARPDR_RPD   ((uint32_t)0xFFFFFFFF)

#define ETH_DMARDLAR_SRL   ((uint32_t)0xFFFFFFFF)

#define ETH_DMATDLAR_STL   ((uint32_t)0xFFFFFFFF)

#define ETH_DMASR_TSTS   ((uint32_t)0x20000000)

#define ETH_DMASR_PMTS   ((uint32_t)0x10000000)

#define ETH_DMASR_MMCS   ((uint32_t)0x08000000)

#define ETH_DMASR_EBS   ((uint32_t)0x03800000)

#define ETH_DMASR_EBS_DescAccess   ((uint32_t)0x02000000)

#define ETH_DMASR_EBS_ReadTransf   ((uint32_t)0x01000000)

#define ETH_DMASR_EBS_DataTransfTx   ((uint32_t)0x00800000)

#define ETH_DMASR_TPS   ((uint32_t)0x00700000)

#define ETH_DMASR_TPS_Stopped   ((uint32_t)0x00000000)

#define ETH_DMASR_TPS_Fetching   ((uint32_t)0x00100000)

#define ETH_DMASR_TPS_Waiting   ((uint32_t)0x00200000)

#define ETH_DMASR_TPS_Reading   ((uint32_t)0x00300000)

#define ETH_DMASR_TPS_Suspended   ((uint32_t)0x00600000)

#define ETH_DMASR_TPS_Closing   ((uint32_t)0x00700000)

#define ETH_DMASR_RPS   ((uint32_t)0x000E0000)

#define ETH_DMASR_RPS_Stopped   ((uint32_t)0x00000000)

#define ETH_DMASR_RPS_Fetching   ((uint32_t)0x00020000)

#define ETH_DMASR_RPS_Waiting   ((uint32_t)0x00060000)

#define ETH_DMASR_RPS_Suspended   ((uint32_t)0x00080000)

#define ETH_DMASR_RPS_Closing   ((uint32_t)0x000A0000)

#define ETH_DMASR_RPS_Queuing   ((uint32_t)0x000E0000)

#define ETH_DMASR_NIS   ((uint32_t)0x00010000)

#define ETH_DMASR_AIS   ((uint32_t)0x00008000)

#define ETH_DMASR_ERS   ((uint32_t)0x00004000)

#define ETH_DMASR_FBES   ((uint32_t)0x00002000)

#define ETH_DMASR_ETS   ((uint32_t)0x00000400)

#define ETH_DMASR_RWTS   ((uint32_t)0x00000200)

#define ETH_DMASR_RPSS   ((uint32_t)0x00000100)

#define ETH_DMASR_RBUS   ((uint32_t)0x00000080)

#define ETH_DMASR_RS   ((uint32_t)0x00000040)

#define ETH_DMASR_TUS   ((uint32_t)0x00000020)

#define ETH_DMASR_ROS   ((uint32_t)0x00000010)

#define ETH_DMASR_TJTS   ((uint32_t)0x00000008)

#define ETH_DMASR_TBUS   ((uint32_t)0x00000004)

#define ETH_DMASR_TPSS   ((uint32_t)0x00000002)

#define ETH_DMASR_TS   ((uint32_t)0x00000001)

#define ETH_DMAOMR_DTCEFD   ((uint32_t)0x04000000)

#define ETH_DMAOMR_RSF   ((uint32_t)0x02000000)

#define ETH_DMAOMR_DFRF   ((uint32_t)0x01000000)

#define ETH_DMAOMR_TSF   ((uint32_t)0x00200000)

#define ETH_DMAOMR_FTF   ((uint32_t)0x00100000)

#define ETH_DMAOMR_TTC   ((uint32_t)0x0001C000)

#define ETH_DMAOMR_TTC_64Bytes   ((uint32_t)0x00000000)

#define ETH_DMAOMR_TTC_128Bytes   ((uint32_t)0x00004000)

#define ETH_DMAOMR_TTC_192Bytes   ((uint32_t)0x00008000)

#define ETH_DMAOMR_TTC_256Bytes   ((uint32_t)0x0000C000)

#define ETH_DMAOMR_TTC_40Bytes   ((uint32_t)0x00010000)

#define ETH_DMAOMR_TTC_32Bytes   ((uint32_t)0x00014000)

#define ETH_DMAOMR_TTC_24Bytes   ((uint32_t)0x00018000)

#define ETH_DMAOMR_TTC_16Bytes   ((uint32_t)0x0001C000)

#define ETH_DMAOMR_ST   ((uint32_t)0x00002000)

#define ETH_DMAOMR_FEF   ((uint32_t)0x00000080)

#define ETH_DMAOMR_FUGF   ((uint32_t)0x00000040)

#define ETH_DMAOMR_RTC   ((uint32_t)0x00000018)

#define ETH_DMAOMR_RTC_64Bytes   ((uint32_t)0x00000000)

#define ETH_DMAOMR_RTC_32Bytes   ((uint32_t)0x00000008)

#define ETH_DMAOMR_RTC_96Bytes   ((uint32_t)0x00000010)

#define ETH_DMAOMR_RTC_128Bytes   ((uint32_t)0x00000018)

#define ETH_DMAOMR_OSF   ((uint32_t)0x00000004)

#define ETH_DMAOMR_SR   ((uint32_t)0x00000002)

#define ETH_DMAIER_NISE   ((uint32_t)0x00010000)

#define ETH_DMAIER_AISE   ((uint32_t)0x00008000)

#define ETH_DMAIER_ERIE   ((uint32_t)0x00004000)

#define ETH_DMAIER_FBEIE   ((uint32_t)0x00002000)

#define ETH_DMAIER_ETIE   ((uint32_t)0x00000400)

#define ETH_DMAIER_RWTIE   ((uint32_t)0x00000200)

#define ETH_DMAIER_RPSIE   ((uint32_t)0x00000100)

#define ETH_DMAIER_RBUIE   ((uint32_t)0x00000080)

#define ETH_DMAIER_RIE   ((uint32_t)0x00000040)

#define ETH_DMAIER_TUIE   ((uint32_t)0x00000020)

#define ETH_DMAIER_ROIE   ((uint32_t)0x00000010)

#define ETH_DMAIER_TJTIE   ((uint32_t)0x00000008)

#define ETH_DMAIER_TBUIE   ((uint32_t)0x00000004)

#define ETH_DMAIER_TPSIE   ((uint32_t)0x00000002)

#define ETH_DMAIER_TIE   ((uint32_t)0x00000001)

#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)

#define ETH_DMAMFBOCR_MFA   ((uint32_t)0x0FFE0000)

#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)

#define ETH_DMAMFBOCR_MFC   ((uint32_t)0x0000FFFF)

#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHTBAR_HTBAP   ((uint32_t)0xFFFFFFFF)

#define ETH_DMACHRBAR_HRBAP   ((uint32_t)0xFFFFFFFF)

#define ADC_SR_AWD   ((uint32_t)0x00000001)

Analog watchdog flag

#define ADC_SR_EOC   ((uint32_t)0x00000002)

End of conversion

#define ADC_SR_JEOC   ((uint32_t)0x00000004)

Injected channel end of conversion

#define ADC_SR_JSTRT   ((uint32_t)0x00000008)

Injected channel Start flag

#define ADC_SR_STRT   ((uint32_t)0x00000010)

Regular channel Start flag

#define ADC_SR_OVR   ((uint32_t)0x00000020)

Overrun flag

#define ADC_SR_ADONS   ((uint32_t)0x00000040)

ADC ON status

#define ADC_SR_RCNR   ((uint32_t)0x00000100)

Regular channel not ready flag

#define ADC_SR_JCNR   ((uint32_t)0x00000200)

Injected channel not ready flag

#define ADC_CR1_AWDCH   ((uint32_t)0x0000001F)

AWDCH[4:0] bits (Analog watchdog channel select bits)

#define ADC_CR1_AWDCH_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_CR1_AWDCH_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_CR1_AWDCH_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_CR1_AWDCH_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_CR1_AWDCH_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_CR1_EOCIE   ((uint32_t)0x00000020)

Interrupt enable for EOC

#define ADC_CR1_AWDIE   ((uint32_t)0x00000040)

Analog Watchdog interrupt enable

#define ADC_CR1_JEOCIE   ((uint32_t)0x00000080)

Interrupt enable for injected channels

#define ADC_CR1_SCAN   ((uint32_t)0x00000100)

Scan mode

#define ADC_CR1_AWDSGL   ((uint32_t)0x00000200)

Enable the watchdog on a single channel in scan mode

#define ADC_CR1_JAUTO   ((uint32_t)0x00000400)

Automatic injected group conversion

#define ADC_CR1_DISCEN   ((uint32_t)0x00000800)

Discontinuous mode on regular channels

#define ADC_CR1_JDISCEN   ((uint32_t)0x00001000)

Discontinuous mode on injected channels

#define ADC_CR1_DISCNUM   ((uint32_t)0x0000E000)

DISCNUM[2:0] bits (Discontinuous mode channel count)

#define ADC_CR1_DISCNUM_0   ((uint32_t)0x00002000)

Bit 0

#define ADC_CR1_DISCNUM_1   ((uint32_t)0x00004000)

Bit 1

#define ADC_CR1_DISCNUM_2   ((uint32_t)0x00008000)

Bit 2

#define ADC_CR1_PDD   ((uint32_t)0x00010000)

Power Down during Delay phase

#define ADC_CR1_PDI   ((uint32_t)0x00020000)

Power Down during Idle phase

#define ADC_CR1_JAWDEN   ((uint32_t)0x00400000)

Analog watchdog enable on injected channels

#define ADC_CR1_AWDEN   ((uint32_t)0x00800000)

Analog watchdog enable on regular channels

#define ADC_CR1_RES   ((uint32_t)0x03000000)

RES[1:0] bits (Resolution)

#define ADC_CR1_RES_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR1_RES_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR1_OVRIE   ((uint32_t)0x04000000)

Overrun interrupt enable

#define ADC_CR2_ADON   ((uint32_t)0x00000001)

A/D Converter ON / OFF

#define ADC_CR2_CONT   ((uint32_t)0x00000002)

Continuous Conversion

#define ADC_CR2_CFG   ((uint32_t)0x00000004)

ADC Configuration

#define ADC_CR2_DELS   ((uint32_t)0x00000070)

DELS[2:0] bits (Delay selection)

#define ADC_CR2_DELS_0   ((uint32_t)0x00000010)

Bit 0

#define ADC_CR2_DELS_1   ((uint32_t)0x00000020)

Bit 1

#define ADC_CR2_DELS_2   ((uint32_t)0x00000040)

Bit 2

#define ADC_CR2_DMA   ((uint32_t)0x00000100)

Direct Memory access mode

#define ADC_CR2_DDS   ((uint32_t)0x00000200)

DMA disable selection (Single ADC)

#define ADC_CR2_EOCS   ((uint32_t)0x00000400)

End of conversion selection

#define ADC_CR2_ALIGN   ((uint32_t)0x00000800)

Data Alignment

#define ADC_CR2_JEXTSEL   ((uint32_t)0x000F0000)

JEXTSEL[3:0] bits (External event select for injected group)

#define ADC_CR2_JEXTSEL_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CR2_JEXTSEL_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CR2_JEXTSEL_2   ((uint32_t)0x00040000)

Bit 2

#define ADC_CR2_JEXTSEL_3   ((uint32_t)0x00080000)

Bit 3

#define ADC_CR2_JEXTEN   ((uint32_t)0x00300000)

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels)

#define ADC_CR2_JEXTEN_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_CR2_JEXTEN_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_CR2_JSWSTART   ((uint32_t)0x00400000)

Start Conversion of injected channels

#define ADC_CR2_EXTSEL   ((uint32_t)0x0F000000)

EXTSEL[3:0] bits (External Event Select for regular group)

#define ADC_CR2_EXTSEL_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_CR2_EXTSEL_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_CR2_EXTSEL_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_CR2_EXTSEL_3   ((uint32_t)0x08000000)

Bit 3

#define ADC_CR2_EXTEN   ((uint32_t)0x30000000)

EXTEN[1:0] bits (External Trigger Conversion mode for regular channels)

#define ADC_CR2_EXTEN_0   ((uint32_t)0x10000000)

Bit 0

#define ADC_CR2_EXTEN_1   ((uint32_t)0x20000000)

Bit 1

#define ADC_CR2_SWSTART   ((uint32_t)0x40000000)

Start Conversion of regular channels

#define ADC_SMPR1_SMP20   ((uint32_t)0x00000007)

SMP20[2:0] bits (Channel 20 Sample time selection)

#define ADC_SMPR1_SMP20_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR1_SMP20_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR1_SMP20_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR1_SMP21   ((uint32_t)0x00000038)

SMP21[2:0] bits (Channel 21 Sample time selection)

#define ADC_SMPR1_SMP21_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR1_SMP21_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR1_SMP21_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR1_SMP22   ((uint32_t)0x000001C0)

SMP22[2:0] bits (Channel 22 Sample time selection)

#define ADC_SMPR1_SMP22_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR1_SMP22_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR1_SMP22_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR1_SMP23   ((uint32_t)0x00000E00)

SMP23[2:0] bits (Channel 23 Sample time selection)

#define ADC_SMPR1_SMP23_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR1_SMP23_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR1_SMP23_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR1_SMP24   ((uint32_t)0x00007000)

SMP24[2:0] bits (Channel 24 Sample time selection)

#define ADC_SMPR1_SMP24_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR1_SMP24_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR1_SMP24_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR1_SMP25   ((uint32_t)0x00038000)

SMP25[2:0] bits (Channel 25 Sample time selection)

#define ADC_SMPR1_SMP25_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR1_SMP25_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR1_SMP25_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR1_SMP26   ((uint32_t)0x001C0000)

SMP26[2:0] bits (Channel 26 Sample time selection)

#define ADC_SMPR1_SMP26_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR1_SMP26_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR1_SMP26_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR1_SMP27   ((uint32_t)0x00E00000)

SMP27[2:0] bits (Channel 27 Sample time selection)

#define ADC_SMPR1_SMP27_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR1_SMP27_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR1_SMP27_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR1_SMP28   ((uint32_t)0x07000000)

SMP28[2:0] bits (Channel 28 Sample time selection)

#define ADC_SMPR1_SMP28_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR1_SMP28_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR1_SMP28_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR1_SMP29   ((uint32_t)0x38000000)

SMP29[2:0] bits (Channel 29 Sample time selection)

#define ADC_SMPR1_SMP29_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR1_SMP29_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR1_SMP29_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_SMPR2_SMP10   ((uint32_t)0x00000007)

SMP10[2:0] bits (Channel 10 Sample time selection)

#define ADC_SMPR2_SMP10_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR2_SMP10_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR2_SMP10_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR2_SMP11   ((uint32_t)0x00000038)

SMP11[2:0] bits (Channel 11 Sample time selection)

#define ADC_SMPR2_SMP11_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR2_SMP11_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR2_SMP11_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR2_SMP12   ((uint32_t)0x000001C0)

SMP12[2:0] bits (Channel 12 Sample time selection)

#define ADC_SMPR2_SMP12_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR2_SMP12_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR2_SMP12_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR2_SMP13   ((uint32_t)0x00000E00)

SMP13[2:0] bits (Channel 13 Sample time selection)

#define ADC_SMPR2_SMP13_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR2_SMP13_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR2_SMP13_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR2_SMP14   ((uint32_t)0x00007000)

SMP14[2:0] bits (Channel 14 Sample time selection)

#define ADC_SMPR2_SMP14_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR2_SMP14_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR2_SMP14_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR2_SMP15   ((uint32_t)0x00038000)

SMP15[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR2_SMP15_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR2_SMP15_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR2_SMP15_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR2_SMP16   ((uint32_t)0x001C0000)

SMP16[2:0] bits (Channel 16 Sample time selection)

#define ADC_SMPR2_SMP16_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR2_SMP16_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR2_SMP16_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR2_SMP17   ((uint32_t)0x00E00000)

SMP17[2:0] bits (Channel 17 Sample time selection)

#define ADC_SMPR2_SMP17_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR2_SMP17_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR2_SMP17_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR2_SMP18   ((uint32_t)0x07000000)

SMP18[2:0] bits (Channel 18 Sample time selection)

#define ADC_SMPR2_SMP18_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR2_SMP18_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR2_SMP18_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR2_SMP19   ((uint32_t)0x38000000)

SMP19[2:0] bits (Channel 19 Sample time selection)

#define ADC_SMPR2_SMP19_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR2_SMP19_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR2_SMP19_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_SMPR3_SMP0   ((uint32_t)0x00000007)

SMP0[2:0] bits (Channel 0 Sample time selection)

#define ADC_SMPR3_SMP0_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR3_SMP0_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR3_SMP0_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR3_SMP1   ((uint32_t)0x00000038)

SMP1[2:0] bits (Channel 1 Sample time selection)

#define ADC_SMPR3_SMP1_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR3_SMP1_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR3_SMP1_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_SMPR3_SMP2   ((uint32_t)0x000001C0)

SMP2[2:0] bits (Channel 2 Sample time selection)

#define ADC_SMPR3_SMP2_0   ((uint32_t)0x00000040)

Bit 0

#define ADC_SMPR3_SMP2_1   ((uint32_t)0x00000080)

Bit 1

#define ADC_SMPR3_SMP2_2   ((uint32_t)0x00000100)

Bit 2

#define ADC_SMPR3_SMP3   ((uint32_t)0x00000E00)

SMP3[2:0] bits (Channel 3 Sample time selection)

#define ADC_SMPR3_SMP3_0   ((uint32_t)0x00000200)

Bit 0

#define ADC_SMPR3_SMP3_1   ((uint32_t)0x00000400)

Bit 1

#define ADC_SMPR3_SMP3_2   ((uint32_t)0x00000800)

Bit 2

#define ADC_SMPR3_SMP4   ((uint32_t)0x00007000)

SMP4[2:0] bits (Channel 4 Sample time selection)

#define ADC_SMPR3_SMP4_0   ((uint32_t)0x00001000)

Bit 0

#define ADC_SMPR3_SMP4_1   ((uint32_t)0x00002000)

Bit 1

#define ADC_SMPR3_SMP4_2   ((uint32_t)0x00004000)

Bit 2

#define ADC_SMPR3_SMP5   ((uint32_t)0x00038000)

SMP5[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR3_SMP5_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SMPR3_SMP5_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SMPR3_SMP5_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SMPR3_SMP6   ((uint32_t)0x001C0000)

SMP6[2:0] bits (Channel 6 Sample time selection)

#define ADC_SMPR3_SMP6_0   ((uint32_t)0x00040000)

Bit 0

#define ADC_SMPR3_SMP6_1   ((uint32_t)0x00080000)

Bit 1

#define ADC_SMPR3_SMP6_2   ((uint32_t)0x00100000)

Bit 2

#define ADC_SMPR3_SMP7   ((uint32_t)0x00E00000)

SMP7[2:0] bits (Channel 7 Sample time selection)

#define ADC_SMPR3_SMP7_0   ((uint32_t)0x00200000)

Bit 0

#define ADC_SMPR3_SMP7_1   ((uint32_t)0x00400000)

Bit 1

#define ADC_SMPR3_SMP7_2   ((uint32_t)0x00800000)

Bit 2

#define ADC_SMPR3_SMP8   ((uint32_t)0x07000000)

SMP8[2:0] bits (Channel 8 Sample time selection)

#define ADC_SMPR3_SMP8_0   ((uint32_t)0x01000000)

Bit 0

#define ADC_SMPR3_SMP8_1   ((uint32_t)0x02000000)

Bit 1

#define ADC_SMPR3_SMP8_2   ((uint32_t)0x04000000)

Bit 2

#define ADC_SMPR3_SMP9   ((uint32_t)0x38000000)

SMP9[2:0] bits (Channel 9 Sample time selection)

#define ADC_SMPR3_SMP9_0   ((uint32_t)0x08000000)

Bit 0

#define ADC_SMPR3_SMP9_1   ((uint32_t)0x10000000)

Bit 1

#define ADC_SMPR3_SMP9_2   ((uint32_t)0x20000000)

Bit 2

#define ADC_JOFR1_JOFFSET1   ((uint32_t)0x00000FFF)

Data offset for injected channel 1

#define ADC_JOFR2_JOFFSET2   ((uint32_t)0x00000FFF)

Data offset for injected channel 2

#define ADC_JOFR3_JOFFSET3   ((uint32_t)0x00000FFF)

Data offset for injected channel 3

#define ADC_JOFR4_JOFFSET4   ((uint32_t)0x00000FFF)

Data offset for injected channel 4

#define ADC_HTR_HT   ((uint32_t)0x00000FFF)

Analog watchdog high threshold

#define ADC_LTR_LT   ((uint32_t)0x00000FFF)

Analog watchdog low threshold

#define ADC_SQR1_L   ((uint32_t)0x00F00000)

L[3:0] bits (Regular channel sequence length)

#define ADC_SQR1_L_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR1_L_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR1_L_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR1_L_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR1_SQ28   ((uint32_t)0x000F8000)

SQ28[4:0] bits (25th conversion in regular sequence)

#define ADC_SQR1_SQ28_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR1_SQ28_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR1_SQ28_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR1_SQ28_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR1_SQ28_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR1_SQ27   ((uint32_t)0x00007C00)

SQ27[4:0] bits (27th conversion in regular sequence)

#define ADC_SQR1_SQ27_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR1_SQ27_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR1_SQ27_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR1_SQ27_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR1_SQ27_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR1_SQ26   ((uint32_t)0x000003E0)

SQ26[4:0] bits (26th conversion in regular sequence)

#define ADC_SQR1_SQ26_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR1_SQ26_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR1_SQ26_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR1_SQ26_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR1_SQ26_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR1_SQ25   ((uint32_t)0x0000001F)

SQ25[4:0] bits (25th conversion in regular sequence)

#define ADC_SQR1_SQ25_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR1_SQ25_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR1_SQ25_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR1_SQ25_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR1_SQ25_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR2_SQ19   ((uint32_t)0x0000001F)

SQ19[4:0] bits (19th conversion in regular sequence)

#define ADC_SQR2_SQ19_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR2_SQ19_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR2_SQ19_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR2_SQ19_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR2_SQ19_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR2_SQ20   ((uint32_t)0x000003E0)

SQ20[4:0] bits (20th conversion in regular sequence)

#define ADC_SQR2_SQ20_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR2_SQ20_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR2_SQ20_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR2_SQ20_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR2_SQ20_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR2_SQ21   ((uint32_t)0x00007C00)

SQ21[4:0] bits (21th conversion in regular sequence)

#define ADC_SQR2_SQ21_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR2_SQ21_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR2_SQ21_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR2_SQ21_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR2_SQ21_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR2_SQ22   ((uint32_t)0x000F8000)

SQ22[4:0] bits (22th conversion in regular sequence)

#define ADC_SQR2_SQ22_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR2_SQ22_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR2_SQ22_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR2_SQ22_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR2_SQ22_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR2_SQ23   ((uint32_t)0x01F00000)

SQ23[4:0] bits (23th conversion in regular sequence)

#define ADC_SQR2_SQ23_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR2_SQ23_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR2_SQ23_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR2_SQ23_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR2_SQ23_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR2_SQ24   ((uint32_t)0x3E000000)

SQ24[4:0] bits (24th conversion in regular sequence)

#define ADC_SQR2_SQ24_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR2_SQ24_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR2_SQ24_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR2_SQ24_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR2_SQ24_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR3_SQ13   ((uint32_t)0x0000001F)

SQ13[4:0] bits (13th conversion in regular sequence)

#define ADC_SQR3_SQ13_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR3_SQ13_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR3_SQ13_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR3_SQ13_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR3_SQ13_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR3_SQ14   ((uint32_t)0x000003E0)

SQ14[4:0] bits (14th conversion in regular sequence)

#define ADC_SQR3_SQ14_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR3_SQ14_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR3_SQ14_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR3_SQ14_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR3_SQ14_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR3_SQ15   ((uint32_t)0x00007C00)

SQ15[4:0] bits (15th conversion in regular sequence)

#define ADC_SQR3_SQ15_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR3_SQ15_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR3_SQ15_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR3_SQ15_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR3_SQ15_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR3_SQ16   ((uint32_t)0x000F8000)

SQ16[4:0] bits (16th conversion in regular sequence)

#define ADC_SQR3_SQ16_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR3_SQ16_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR3_SQ16_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR3_SQ16_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR3_SQ16_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR3_SQ17   ((uint32_t)0x01F00000)

SQ17[4:0] bits (17th conversion in regular sequence)

#define ADC_SQR3_SQ17_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR3_SQ17_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR3_SQ17_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR3_SQ17_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR3_SQ17_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR3_SQ18   ((uint32_t)0x3E000000)

SQ18[4:0] bits (18th conversion in regular sequence)

#define ADC_SQR3_SQ18_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR3_SQ18_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR3_SQ18_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR3_SQ18_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR3_SQ18_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR4_SQ7   ((uint32_t)0x0000001F)

SQ7[4:0] bits (7th conversion in regular sequence)

#define ADC_SQR4_SQ7_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR4_SQ7_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR4_SQ7_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR4_SQ7_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR4_SQ7_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR4_SQ8   ((uint32_t)0x000003E0)

SQ8[4:0] bits (8th conversion in regular sequence)

#define ADC_SQR4_SQ8_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR4_SQ8_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR4_SQ8_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR4_SQ8_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR4_SQ8_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR4_SQ9   ((uint32_t)0x00007C00)

SQ9[4:0] bits (9th conversion in regular sequence)

#define ADC_SQR4_SQ9_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR4_SQ9_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR4_SQ9_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR4_SQ9_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR4_SQ9_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR4_SQ10   ((uint32_t)0x000F8000)

SQ10[4:0] bits (10th conversion in regular sequence)

#define ADC_SQR4_SQ10_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR4_SQ10_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR4_SQ10_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR4_SQ10_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR4_SQ10_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR4_SQ11   ((uint32_t)0x01F00000)

SQ11[4:0] bits (11th conversion in regular sequence)

#define ADC_SQR4_SQ11_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR4_SQ11_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR4_SQ11_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR4_SQ11_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR4_SQ11_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR4_SQ12   ((uint32_t)0x3E000000)

SQ12[4:0] bits (12th conversion in regular sequence)

#define ADC_SQR4_SQ12_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR4_SQ12_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR4_SQ12_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR4_SQ12_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR4_SQ12_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_SQR5_SQ1   ((uint32_t)0x0000001F)

SQ1[4:0] bits (1st conversion in regular sequence)

#define ADC_SQR5_SQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SQR5_SQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SQR5_SQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SQR5_SQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_SQR5_SQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_SQR5_SQ2   ((uint32_t)0x000003E0)

SQ2[4:0] bits (2nd conversion in regular sequence)

#define ADC_SQR5_SQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_SQR5_SQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_SQR5_SQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_SQR5_SQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_SQR5_SQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_SQR5_SQ3   ((uint32_t)0x00007C00)

SQ3[4:0] bits (3rd conversion in regular sequence)

#define ADC_SQR5_SQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_SQR5_SQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_SQR5_SQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_SQR5_SQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_SQR5_SQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_SQR5_SQ4   ((uint32_t)0x000F8000)

SQ4[4:0] bits (4th conversion in regular sequence)

#define ADC_SQR5_SQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_SQR5_SQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_SQR5_SQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_SQR5_SQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_SQR5_SQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_SQR5_SQ5   ((uint32_t)0x01F00000)

SQ5[4:0] bits (5th conversion in regular sequence)

#define ADC_SQR5_SQ5_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_SQR5_SQ5_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_SQR5_SQ5_2   ((uint32_t)0x00400000)

Bit 2

#define ADC_SQR5_SQ5_3   ((uint32_t)0x00800000)

Bit 3

#define ADC_SQR5_SQ5_4   ((uint32_t)0x01000000)

Bit 4

#define ADC_SQR5_SQ6   ((uint32_t)0x3E000000)

SQ6[4:0] bits (6th conversion in regular sequence)

#define ADC_SQR5_SQ6_0   ((uint32_t)0x02000000)

Bit 0

#define ADC_SQR5_SQ6_1   ((uint32_t)0x04000000)

Bit 1

#define ADC_SQR5_SQ6_2   ((uint32_t)0x08000000)

Bit 2

#define ADC_SQR5_SQ6_3   ((uint32_t)0x10000000)

Bit 3

#define ADC_SQR5_SQ6_4   ((uint32_t)0x20000000)

Bit 4

#define ADC_JSQR_JSQ1   ((uint32_t)0x0000001F)

JSQ1[4:0] bits (1st conversion in injected sequence)

#define ADC_JSQR_JSQ1_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_JSQR_JSQ1_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_JSQR_JSQ1_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_JSQR_JSQ1_3   ((uint32_t)0x00000008)

Bit 3

#define ADC_JSQR_JSQ1_4   ((uint32_t)0x00000010)

Bit 4

#define ADC_JSQR_JSQ2   ((uint32_t)0x000003E0)

JSQ2[4:0] bits (2nd conversion in injected sequence)

#define ADC_JSQR_JSQ2_0   ((uint32_t)0x00000020)

Bit 0

#define ADC_JSQR_JSQ2_1   ((uint32_t)0x00000040)

Bit 1

#define ADC_JSQR_JSQ2_2   ((uint32_t)0x00000080)

Bit 2

#define ADC_JSQR_JSQ2_3   ((uint32_t)0x00000100)

Bit 3

#define ADC_JSQR_JSQ2_4   ((uint32_t)0x00000200)

Bit 4

#define ADC_JSQR_JSQ3   ((uint32_t)0x00007C00)

JSQ3[4:0] bits (3rd conversion in injected sequence)

#define ADC_JSQR_JSQ3_0   ((uint32_t)0x00000400)

Bit 0

#define ADC_JSQR_JSQ3_1   ((uint32_t)0x00000800)

Bit 1

#define ADC_JSQR_JSQ3_2   ((uint32_t)0x00001000)

Bit 2

#define ADC_JSQR_JSQ3_3   ((uint32_t)0x00002000)

Bit 3

#define ADC_JSQR_JSQ3_4   ((uint32_t)0x00004000)

Bit 4

#define ADC_JSQR_JSQ4   ((uint32_t)0x000F8000)

JSQ4[4:0] bits (4th conversion in injected sequence)

#define ADC_JSQR_JSQ4_0   ((uint32_t)0x00008000)

Bit 0

#define ADC_JSQR_JSQ4_1   ((uint32_t)0x00010000)

Bit 1

#define ADC_JSQR_JSQ4_2   ((uint32_t)0x00020000)

Bit 2

#define ADC_JSQR_JSQ4_3   ((uint32_t)0x00040000)

Bit 3

#define ADC_JSQR_JSQ4_4   ((uint32_t)0x00080000)

Bit 4

#define ADC_JSQR_JL   ((uint32_t)0x00300000)

JL[1:0] bits (Injected Sequence length)

#define ADC_JSQR_JL_0   ((uint32_t)0x00100000)

Bit 0

#define ADC_JSQR_JL_1   ((uint32_t)0x00200000)

Bit 1

#define ADC_JDR1_JDATA   ((uint32_t)0x0000FFFF)

Injected data

#define ADC_JDR2_JDATA   ((uint32_t)0x0000FFFF)

Injected data

#define ADC_JDR3_JDATA   ((uint32_t)0x0000FFFF)

Injected data

#define ADC_JDR4_JDATA   ((uint32_t)0x0000FFFF)

Injected data

#define ADC_DR_DATA   ((uint32_t)0x0000FFFF)

Regular data

#define ADC_SMPR3_SMP30   ((uint32_t)0x00000007)

SMP30[2:0] bits (Channel 30 Sample time selection)

#define ADC_SMPR3_SMP30_0   ((uint32_t)0x00000001)

Bit 0

#define ADC_SMPR3_SMP30_1   ((uint32_t)0x00000002)

Bit 1

#define ADC_SMPR3_SMP30_2   ((uint32_t)0x00000004)

Bit 2

#define ADC_SMPR3_SMP31   ((uint32_t)0x00000038)

SMP31[2:0] bits (Channel 31 Sample time selection)

#define ADC_SMPR3_SMP31_0   ((uint32_t)0x00000008)

Bit 0

#define ADC_SMPR3_SMP31_1   ((uint32_t)0x00000010)

Bit 1

#define ADC_SMPR3_SMP31_2   ((uint32_t)0x00000020)

Bit 2

#define ADC_CSR_AWD1   ((uint32_t)0x00000001)

ADC1 Analog watchdog flag

#define ADC_CSR_EOC1   ((uint32_t)0x00000002)

ADC1 End of conversion

#define ADC_CSR_JEOC1   ((uint32_t)0x00000004)

ADC1 Injected channel end of conversion

#define ADC_CSR_JSTRT1   ((uint32_t)0x00000008)

ADC1 Injected channel Start flag

#define ADC_CSR_STRT1   ((uint32_t)0x00000010)

ADC1 Regular channel Start flag

#define ADC_CSR_OVR1   ((uint32_t)0x00000020)

ADC1 overrun flag

#define ADC_CSR_ADONS1   ((uint32_t)0x00000040)

ADON status of ADC1

#define ADC_CCR_ADCPRE   ((uint32_t)0x00030000)

ADC prescaler

#define ADC_CCR_ADCPRE_0   ((uint32_t)0x00010000)

Bit 0

#define ADC_CCR_ADCPRE_1   ((uint32_t)0x00020000)

Bit 1

#define ADC_CCR_TSVREFE   ((uint32_t)0x00800000)

Temperature Sensor and VREFINT Enable

#define AES_CR_EN   ((uint32_t)0x00000001)

AES Enable

#define AES_CR_DATATYPE   ((uint32_t)0x00000006)

Data type selection

#define AES_CR_DATATYPE_0   ((uint32_t)0x00000002)

Bit 0

#define AES_CR_DATATYPE_1   ((uint32_t)0x00000004)

Bit 1

#define AES_CR_MODE   ((uint32_t)0x00000018)

AES Mode Of Operation

#define AES_CR_MODE_0   ((uint32_t)0x00000008)

Bit 0

#define AES_CR_MODE_1   ((uint32_t)0x00000010)

Bit 1

#define AES_CR_CHMOD   ((uint32_t)0x00000060)

AES Chaining Mode

#define AES_CR_CHMOD_0   ((uint32_t)0x00000020)

Bit 0

#define AES_CR_CHMOD_1   ((uint32_t)0x00000040)

Bit 1

#define AES_CR_CCFC   ((uint32_t)0x00000080)

Computation Complete Flag Clear

#define AES_CR_ERRC   ((uint32_t)0x00000100)

Error Clear

#define AES_CR_CCIE   ((uint32_t)0x00000200)

Computation Complete Interrupt Enable

#define AES_CR_ERRIE   ((uint32_t)0x00000400)

Error Interrupt Enable

#define AES_CR_DMAINEN   ((uint32_t)0x00000800)

DMA ENable managing the data input phase

#define AES_CR_DMAOUTEN   ((uint32_t)0x00001000)

DMA Enable managing the data output phase

#define AES_SR_CCF   ((uint32_t)0x00000001)

Computation Complete Flag

#define AES_SR_RDERR   ((uint32_t)0x00000002)

Read Error Flag

#define AES_SR_WRERR   ((uint32_t)0x00000004)

Write Error Flag

#define AES_DINR   ((uint32_t)0x0000FFFF)

AES Data Input Register

#define AES_DOUTR   ((uint32_t)0x0000FFFF)

AES Data Output Register

#define AES_KEYR0   ((uint32_t)0x0000FFFF)

AES Key Register 0

#define AES_KEYR1   ((uint32_t)0x0000FFFF)

AES Key Register 1

#define AES_KEYR2   ((uint32_t)0x0000FFFF)

AES Key Register 2

#define AES_KEYR3   ((uint32_t)0x0000FFFF)

AES Key Register 3

#define AES_IVR0   ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 0

#define AES_IVR1   ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 1

#define AES_IVR2   ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 2

#define AES_IVR3   ((uint32_t)0x0000FFFF)

AES Initialization Vector Register 3

#define COMP_CSR_10KPU   ((uint32_t)0x00000001)

10K pull-up resistor

#define COMP_CSR_400KPU   ((uint32_t)0x00000002)

400K pull-up resistor

#define COMP_CSR_10KPD   ((uint32_t)0x00000004)

10K pull-down resistor

#define COMP_CSR_400KPD   ((uint32_t)0x00000008)

400K pull-down resistor

#define COMP_CSR_CMP1EN   ((uint32_t)0x00000010)

Comparator 1 enable

#define COMP_CSR_SW1   ((uint32_t)0x00000020)

SW1 analog switch enable

#define COMP_CSR_CMP1OUT   ((uint32_t)0x00000080)

Comparator 1 output

#define COMP_CSR_SPEED   ((uint32_t)0x00001000)

Comparator 2 speed

#define COMP_CSR_CMP2OUT   ((uint32_t)0x00002000)

Comparator 2 ouput

#define COMP_CSR_VREFOUTEN   ((uint32_t)0x00010000)

Comparator Vref Enable

#define COMP_CSR_WNDWE   ((uint32_t)0x00020000)

Window mode enable

#define COMP_CSR_INSEL   ((uint32_t)0x001C0000)

INSEL[2:0] Inversion input Selection

#define COMP_CSR_INSEL_0   ((uint32_t)0x00040000)

Bit 0

#define COMP_CSR_INSEL_1   ((uint32_t)0x00080000)

Bit 1

#define COMP_CSR_INSEL_2   ((uint32_t)0x00100000)

Bit 2

#define COMP_CSR_OUTSEL   ((uint32_t)0x00E00000)

OUTSEL[2:0] comparator 2 output redirection

#define COMP_CSR_OUTSEL_0   ((uint32_t)0x00200000)

Bit 0

#define COMP_CSR_OUTSEL_1   ((uint32_t)0x00400000)

Bit 1

#define COMP_CSR_OUTSEL_2   ((uint32_t)0x00800000)

Bit 2

#define COMP_CSR_FCH3   ((uint32_t)0x04000000)

Bit 26

#define COMP_CSR_FCH8   ((uint32_t)0x08000000)

Bit 27

#define COMP_CSR_RCH13   ((uint32_t)0x10000000)

Bit 28

#define COMP_CSR_CAIE   ((uint32_t)0x20000000)

Bit 29

#define COMP_CSR_CAIF   ((uint32_t)0x40000000)

Bit 30

#define COMP_CSR_TSUSP   ((uint32_t)0x80000000)

Bit 31

#define OPAMP_CSR_OPA1PD   ((uint32_t)0x00000001)

OPAMP1 disable

#define OPAMP_CSR_S3SEL1   ((uint32_t)0x00000002)

Switch 3 for OPAMP1 Enable

#define OPAMP_CSR_S4SEL1   ((uint32_t)0x00000004)

Switch 4 for OPAMP1 Enable

#define OPAMP_CSR_S5SEL1   ((uint32_t)0x00000008)

Switch 5 for OPAMP1 Enable

#define OPAMP_CSR_S6SEL1   ((uint32_t)0x00000010)

Switch 6 for OPAMP1 Enable

#define OPAMP_CSR_OPA1CAL_L   ((uint32_t)0x00000020)

OPAMP1 Offset calibration for P differential pair

#define OPAMP_CSR_OPA1CAL_H   ((uint32_t)0x00000040)

OPAMP1 Offset calibration for N differential pair

#define OPAMP_CSR_OPA1LPM   ((uint32_t)0x00000080)

OPAMP1 Low power enable

#define OPAMP_CSR_OPA2PD   ((uint32_t)0x00000100)

OPAMP2 disable

#define OPAMP_CSR_S3SEL2   ((uint32_t)0x00000200)

Switch 3 for OPAMP2 Enable

#define OPAMP_CSR_S4SEL2   ((uint32_t)0x00000400)

Switch 4 for OPAMP2 Enable

#define OPAMP_CSR_S5SEL2   ((uint32_t)0x00000800)

Switch 5 for OPAMP2 Enable

#define OPAMP_CSR_S6SEL2   ((uint32_t)0x00001000)

Switch 6 for OPAMP2 Enable

#define OPAMP_CSR_OPA2CAL_L   ((uint32_t)0x00002000)

OPAMP2 Offset calibration for P differential pair

#define OPAMP_CSR_OPA2CAL_H   ((uint32_t)0x00004000)

OPAMP2 Offset calibration for N differential pair

#define OPAMP_CSR_OPA2LPM   ((uint32_t)0x00008000)

OPAMP2 Low power enable

#define OPAMP_CSR_OPA3PD   ((uint32_t)0x00010000)

OPAMP3 disable

#define OPAMP_CSR_S3SEL3   ((uint32_t)0x00020000)

Switch 3 for OPAMP3 Enable

#define OPAMP_CSR_S4SEL3   ((uint32_t)0x00040000)

Switch 4 for OPAMP3 Enable

#define OPAMP_CSR_S5SEL3   ((uint32_t)0x00080000)

Switch 5 for OPAMP3 Enable

#define OPAMP_CSR_S6SEL3   ((uint32_t)0x00100000)

Switch 6 for OPAMP3 Enable

#define OPAMP_CSR_OPA3CAL_L   ((uint32_t)0x00200000)

OPAMP3 Offset calibration for P differential pair

#define OPAMP_CSR_OPA3CAL_H   ((uint32_t)0x00400000)

OPAMP3 Offset calibration for N differential pair

#define OPAMP_CSR_OPA3LPM   ((uint32_t)0x00800000)

OPAMP3 Low power enable

#define OPAMP_CSR_ANAWSEL1   ((uint32_t)0x01000000)

Switch ANA Enable for OPAMP1

#define OPAMP_CSR_ANAWSEL2   ((uint32_t)0x02000000)

Switch ANA Enable for OPAMP2

#define OPAMP_CSR_ANAWSEL3   ((uint32_t)0x04000000)

Switch ANA Enable for OPAMP3

#define OPAMP_CSR_S7SEL2   ((uint32_t)0x08000000)

Switch 7 for OPAMP2 Enable

#define OPAMP_CSR_AOP_RANGE   ((uint32_t)0x10000000)

Power range selection

#define OPAMP_CSR_OPA1CALOUT   ((uint32_t)0x20000000)

OPAMP1 calibration output

#define OPAMP_CSR_OPA2CALOUT   ((uint32_t)0x40000000)

OPAMP2 calibration output

#define OPAMP_CSR_OPA3CALOUT   ((uint32_t)0x80000000)

OPAMP3 calibration output

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM   ((uint32_t)0x000003FF)

Offset trim for OPAMP1

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM   ((uint32_t)0x000FFC00)

Offset trim for OPAMP2

#define OPAMP_OTR_AO3_OPT_OFFSET_TRIM   ((uint32_t)0x3FF00000)

Offset trim for OPAMP2

#define OPAMP_OTR_OT_USER   ((uint32_t)0x80000000)

Switch to OPAMP offset user trimmed values

#define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP   ((uint32_t)0x000003FF)

Offset trim in low power for OPAMP1

#define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP   ((uint32_t)0x000FFC00)

Offset trim in low power for OPAMP2

#define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP   ((uint32_t)0x3FF00000)

Offset trim in low power for OPAMP3

#define CRC_DR_DR   ((uint32_t)0xFFFFFFFF)

Data register bits

#define CRC_IDR_IDR   ((uint8_t)0xFF)

General-purpose 8-bit data register bits

#define CRC_CR_RESET   ((uint32_t)0x00000001)

RESET bit

#define DAC_CR_EN1   ((uint32_t)0x00000001)

DAC channel1 enable

#define DAC_CR_BOFF1   ((uint32_t)0x00000002)

DAC channel1 output buffer disable

#define DAC_CR_TEN1   ((uint32_t)0x00000004)

DAC channel1 Trigger enable

#define DAC_CR_TSEL1   ((uint32_t)0x00000038)

TSEL1[2:0] (DAC channel1 Trigger selection)

#define DAC_CR_TSEL1_0   ((uint32_t)0x00000008)

Bit 0

#define DAC_CR_TSEL1_1   ((uint32_t)0x00000010)

Bit 1

#define DAC_CR_TSEL1_2   ((uint32_t)0x00000020)

Bit 2

#define DAC_CR_WAVE1   ((uint32_t)0x000000C0)

WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)

#define DAC_CR_WAVE1_0   ((uint32_t)0x00000040)

Bit 0

#define DAC_CR_WAVE1_1   ((uint32_t)0x00000080)

Bit 1

#define DAC_CR_MAMP1   ((uint32_t)0x00000F00)

MAMP1[3:0] (DAC channel1 Mask/Amplitude selector)

#define DAC_CR_MAMP1_0   ((uint32_t)0x00000100)

Bit 0

#define DAC_CR_MAMP1_1   ((uint32_t)0x00000200)

Bit 1

#define DAC_CR_MAMP1_2   ((uint32_t)0x00000400)

Bit 2

#define DAC_CR_MAMP1_3   ((uint32_t)0x00000800)

Bit 3

#define DAC_CR_DMAEN1   ((uint32_t)0x00001000)

DAC channel1 DMA enable

#define DAC_CR_DMAUDRIE1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun interrupt enable

#define DAC_CR_EN2   ((uint32_t)0x00010000)

DAC channel2 enable

#define DAC_CR_BOFF2   ((uint32_t)0x00020000)

DAC channel2 output buffer disable

#define DAC_CR_TEN2   ((uint32_t)0x00040000)

DAC channel2 Trigger enable

#define DAC_CR_TSEL2   ((uint32_t)0x00380000)

TSEL2[2:0] (DAC channel2 Trigger selection)

#define DAC_CR_TSEL2_0   ((uint32_t)0x00080000)

Bit 0

#define DAC_CR_TSEL2_1   ((uint32_t)0x00100000)

Bit 1

#define DAC_CR_TSEL2_2   ((uint32_t)0x00200000)

Bit 2

#define DAC_CR_WAVE2   ((uint32_t)0x00C00000)

WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable)

#define DAC_CR_WAVE2_0   ((uint32_t)0x00400000)

Bit 0

#define DAC_CR_WAVE2_1   ((uint32_t)0x00800000)

Bit 1

#define DAC_CR_MAMP2   ((uint32_t)0x0F000000)

MAMP2[3:0] (DAC channel2 Mask/Amplitude selector)

#define DAC_CR_MAMP2_0   ((uint32_t)0x01000000)

Bit 0

#define DAC_CR_MAMP2_1   ((uint32_t)0x02000000)

Bit 1

#define DAC_CR_MAMP2_2   ((uint32_t)0x04000000)

Bit 2

#define DAC_CR_MAMP2_3   ((uint32_t)0x08000000)

Bit 3

#define DAC_CR_DMAEN2   ((uint32_t)0x10000000)

DAC channel2 DMA enabled

#define DAC_CR_DMAUDRIE2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun interrupt enable

#define DAC_SWTRIGR_SWTRIG1   ((uint8_t)0x01)

DAC channel1 software trigger

#define DAC_SWTRIGR_SWTRIG2   ((uint8_t)0x02)

DAC channel2 software trigger

#define DAC_DHR12R1_DACC1DHR   ((uint16_t)0x0FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12L1_DACC1DHR   ((uint16_t)0xFFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR8R1_DACC1DHR   ((uint8_t)0xFF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR12R2_DACC2DHR   ((uint16_t)0x0FFF)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12L2_DACC2DHR   ((uint16_t)0xFFF0)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8R2_DACC2DHR   ((uint8_t)0xFF)

DAC channel2 8-bit Right aligned data

#define DAC_DHR12RD_DACC1DHR   ((uint32_t)0x00000FFF)

DAC channel1 12-bit Right aligned data

#define DAC_DHR12RD_DACC2DHR   ((uint32_t)0x0FFF0000)

DAC channel2 12-bit Right aligned data

#define DAC_DHR12LD_DACC1DHR   ((uint32_t)0x0000FFF0)

DAC channel1 12-bit Left aligned data

#define DAC_DHR12LD_DACC2DHR   ((uint32_t)0xFFF00000)

DAC channel2 12-bit Left aligned data

#define DAC_DHR8RD_DACC1DHR   ((uint16_t)0x00FF)

DAC channel1 8-bit Right aligned data

#define DAC_DHR8RD_DACC2DHR   ((uint16_t)0xFF00)

DAC channel2 8-bit Right aligned data

#define DAC_DOR1_DACC1DOR   ((uint16_t)0x0FFF)

DAC channel1 data output

#define DAC_DOR2_DACC2DOR   ((uint16_t)0x0FFF)

DAC channel2 data output

#define DAC_SR_DMAUDR1   ((uint32_t)0x00002000)

DAC channel1 DMA underrun flag

#define DAC_SR_DMAUDR2   ((uint32_t)0x20000000)

DAC channel2 DMA underrun flag

#define DBGMCU_IDCODE_DEV_ID   ((uint32_t)0x00000FFF)

Device Identifier

#define DBGMCU_IDCODE_REV_ID   ((uint32_t)0xFFFF0000)

REV_ID[15:0] bits (Revision Identifier)

#define DBGMCU_IDCODE_REV_ID_0   ((uint32_t)0x00010000)

Bit 0

#define DBGMCU_IDCODE_REV_ID_1   ((uint32_t)0x00020000)

Bit 1

#define DBGMCU_IDCODE_REV_ID_2   ((uint32_t)0x00040000)

Bit 2

#define DBGMCU_IDCODE_REV_ID_3   ((uint32_t)0x00080000)

Bit 3

#define DBGMCU_IDCODE_REV_ID_4   ((uint32_t)0x00100000)

Bit 4

#define DBGMCU_IDCODE_REV_ID_5   ((uint32_t)0x00200000)

Bit 5

#define DBGMCU_IDCODE_REV_ID_6   ((uint32_t)0x00400000)

Bit 6

#define DBGMCU_IDCODE_REV_ID_7   ((uint32_t)0x00800000)

Bit 7

#define DBGMCU_IDCODE_REV_ID_8   ((uint32_t)0x01000000)

Bit 8

#define DBGMCU_IDCODE_REV_ID_9   ((uint32_t)0x02000000)

Bit 9

#define DBGMCU_IDCODE_REV_ID_10   ((uint32_t)0x04000000)

Bit 10

#define DBGMCU_IDCODE_REV_ID_11   ((uint32_t)0x08000000)

Bit 11

#define DBGMCU_IDCODE_REV_ID_12   ((uint32_t)0x10000000)

Bit 12

#define DBGMCU_IDCODE_REV_ID_13   ((uint32_t)0x20000000)

Bit 13

#define DBGMCU_IDCODE_REV_ID_14   ((uint32_t)0x40000000)

Bit 14

#define DBGMCU_IDCODE_REV_ID_15   ((uint32_t)0x80000000)

Bit 15

#define DBGMCU_CR_DBG_SLEEP   ((uint32_t)0x00000001)

Debug Sleep Mode

#define DBGMCU_CR_DBG_STOP   ((uint32_t)0x00000002)

Debug Stop Mode

#define DBGMCU_CR_DBG_STANDBY   ((uint32_t)0x00000004)

Debug Standby mode

#define DBGMCU_CR_TRACE_IOEN   ((uint32_t)0x00000020)

Trace Pin Assignment Control

#define DBGMCU_CR_TRACE_MODE   ((uint32_t)0x000000C0)

TRACE_MODE[1:0] bits (Trace Pin Assignment Control)

#define DBGMCU_CR_TRACE_MODE_0   ((uint32_t)0x00000040)

Bit 0

#define DBGMCU_CR_TRACE_MODE_1   ((uint32_t)0x00000080)

Bit 1

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   ((uint32_t)0x00000001)

TIM2 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   ((uint32_t)0x00000002)

TIM3 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   ((uint32_t)0x00000004)

TIM4 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   ((uint32_t)0x00000008)

TIM5 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   ((uint32_t)0x00000010)

TIM6 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   ((uint32_t)0x00000020)

TIM7 counter stopped when core is halted

#define DBGMCU_APB1_FZ_DBG_RTC_STOP   ((uint32_t)0x00000400)

RTC Counter stopped when Core is halted

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   ((uint32_t)0x00000800)

Debug Window Watchdog stopped when Core is halted

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   ((uint32_t)0x00001000)

Debug Independent Watchdog stopped when Core is halted

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)

SMBUS timeout mode stopped when Core is halted

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)

SMBUS timeout mode stopped when Core is halted

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP   ((uint32_t)0x00000004)

TIM9 counter stopped when core is halted

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP   ((uint32_t)0x00000008)

TIM10 counter stopped when core is halted

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP   ((uint32_t)0x00000010)

TIM11 counter stopped when core is halted

#define DMA_ISR_GIF1   ((uint32_t)0x00000001)

Channel 1 Global interrupt flag

#define DMA_ISR_TCIF1   ((uint32_t)0x00000002)

Channel 1 Transfer Complete flag

#define DMA_ISR_HTIF1   ((uint32_t)0x00000004)

Channel 1 Half Transfer flag

#define DMA_ISR_TEIF1   ((uint32_t)0x00000008)

Channel 1 Transfer Error flag

#define DMA_ISR_GIF2   ((uint32_t)0x00000010)

Channel 2 Global interrupt flag

#define DMA_ISR_TCIF2   ((uint32_t)0x00000020)

Channel 2 Transfer Complete flag

#define DMA_ISR_HTIF2   ((uint32_t)0x00000040)

Channel 2 Half Transfer flag

#define DMA_ISR_TEIF2   ((uint32_t)0x00000080)

Channel 2 Transfer Error flag

#define DMA_ISR_GIF3   ((uint32_t)0x00000100)

Channel 3 Global interrupt flag

#define DMA_ISR_TCIF3   ((uint32_t)0x00000200)

Channel 3 Transfer Complete flag

#define DMA_ISR_HTIF3   ((uint32_t)0x00000400)

Channel 3 Half Transfer flag

#define DMA_ISR_TEIF3   ((uint32_t)0x00000800)

Channel 3 Transfer Error flag

#define DMA_ISR_GIF4   ((uint32_t)0x00001000)

Channel 4 Global interrupt flag

#define DMA_ISR_TCIF4   ((uint32_t)0x00002000)

Channel 4 Transfer Complete flag

#define DMA_ISR_HTIF4   ((uint32_t)0x00004000)

Channel 4 Half Transfer flag

#define DMA_ISR_TEIF4   ((uint32_t)0x00008000)

Channel 4 Transfer Error flag

#define DMA_ISR_GIF5   ((uint32_t)0x00010000)

Channel 5 Global interrupt flag

#define DMA_ISR_TCIF5   ((uint32_t)0x00020000)

Channel 5 Transfer Complete flag

#define DMA_ISR_HTIF5   ((uint32_t)0x00040000)

Channel 5 Half Transfer flag

#define DMA_ISR_TEIF5   ((uint32_t)0x00080000)

Channel 5 Transfer Error flag

#define DMA_ISR_GIF6   ((uint32_t)0x00100000)

Channel 6 Global interrupt flag

#define DMA_ISR_TCIF6   ((uint32_t)0x00200000)

Channel 6 Transfer Complete flag

#define DMA_ISR_HTIF6   ((uint32_t)0x00400000)

Channel 6 Half Transfer flag

#define DMA_ISR_TEIF6   ((uint32_t)0x00800000)

Channel 6 Transfer Error flag

#define DMA_ISR_GIF7   ((uint32_t)0x01000000)

Channel 7 Global interrupt flag

#define DMA_ISR_TCIF7   ((uint32_t)0x02000000)

Channel 7 Transfer Complete flag

#define DMA_ISR_HTIF7   ((uint32_t)0x04000000)

Channel 7 Half Transfer flag

#define DMA_ISR_TEIF7   ((uint32_t)0x08000000)

Channel 7 Transfer Error flag

#define DMA_IFCR_CGIF1   ((uint32_t)0x00000001)

Channel 1 Global interrupt clearr

#define DMA_IFCR_CTCIF1   ((uint32_t)0x00000002)

Channel 1 Transfer Complete clear

#define DMA_IFCR_CHTIF1   ((uint32_t)0x00000004)

Channel 1 Half Transfer clear

#define DMA_IFCR_CTEIF1   ((uint32_t)0x00000008)

Channel 1 Transfer Error clear

#define DMA_IFCR_CGIF2   ((uint32_t)0x00000010)

Channel 2 Global interrupt clear

#define DMA_IFCR_CTCIF2   ((uint32_t)0x00000020)

Channel 2 Transfer Complete clear

#define DMA_IFCR_CHTIF2   ((uint32_t)0x00000040)

Channel 2 Half Transfer clear

#define DMA_IFCR_CTEIF2   ((uint32_t)0x00000080)

Channel 2 Transfer Error clear

#define DMA_IFCR_CGIF3   ((uint32_t)0x00000100)

Channel 3 Global interrupt clear

#define DMA_IFCR_CTCIF3   ((uint32_t)0x00000200)

Channel 3 Transfer Complete clear

#define DMA_IFCR_CHTIF3   ((uint32_t)0x00000400)

Channel 3 Half Transfer clear

#define DMA_IFCR_CTEIF3   ((uint32_t)0x00000800)

Channel 3 Transfer Error clear

#define DMA_IFCR_CGIF4   ((uint32_t)0x00001000)

Channel 4 Global interrupt clear

#define DMA_IFCR_CTCIF4   ((uint32_t)0x00002000)

Channel 4 Transfer Complete clear

#define DMA_IFCR_CHTIF4   ((uint32_t)0x00004000)

Channel 4 Half Transfer clear

#define DMA_IFCR_CTEIF4   ((uint32_t)0x00008000)

Channel 4 Transfer Error clear

#define DMA_IFCR_CGIF5   ((uint32_t)0x00010000)

Channel 5 Global interrupt clear

#define DMA_IFCR_CTCIF5   ((uint32_t)0x00020000)

Channel 5 Transfer Complete clear

#define DMA_IFCR_CHTIF5   ((uint32_t)0x00040000)

Channel 5 Half Transfer clear

#define DMA_IFCR_CTEIF5   ((uint32_t)0x00080000)

Channel 5 Transfer Error clear

#define DMA_IFCR_CGIF6   ((uint32_t)0x00100000)

Channel 6 Global interrupt clear

#define DMA_IFCR_CTCIF6   ((uint32_t)0x00200000)

Channel 6 Transfer Complete clear

#define DMA_IFCR_CHTIF6   ((uint32_t)0x00400000)

Channel 6 Half Transfer clear

#define DMA_IFCR_CTEIF6   ((uint32_t)0x00800000)

Channel 6 Transfer Error clear

#define DMA_IFCR_CGIF7   ((uint32_t)0x01000000)

Channel 7 Global interrupt clear

#define DMA_IFCR_CTCIF7   ((uint32_t)0x02000000)

Channel 7 Transfer Complete clear

#define DMA_IFCR_CHTIF7   ((uint32_t)0x04000000)

Channel 7 Half Transfer clear

#define DMA_IFCR_CTEIF7   ((uint32_t)0x08000000)

Channel 7 Transfer Error clear

#define DMA_CCR1_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR1_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR1_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR1_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR1_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR1_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR1_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR1_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR1_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR1_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR1_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR1_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR1_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR1_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR1_PL   ((uint16_t)0x3000)

PL[1:0] bits(Channel Priority level)

#define DMA_CCR1_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR1_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR1_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR2_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR2_TCIE   ((uint16_t)0x0002)

ransfer complete interrupt enable

#define DMA_CCR2_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR2_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR2_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR2_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR2_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR2_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR2_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR2_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR2_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR2_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR2_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR2_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR2_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR2_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR2_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR2_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR3_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR3_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR3_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR3_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR3_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR3_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR3_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR3_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR3_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR3_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR3_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR3_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR3_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR3_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR3_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR3_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR3_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR3_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode ****************** Bit definition for DMA_CCR4 register

#define DMA_CCR4_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR4_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR4_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR4_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR4_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR4_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR4_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR4_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR4_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR4_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR4_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR4_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR4_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR4_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR4_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR4_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR4_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR4_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR5_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR5_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR5_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR5_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR5_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR5_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR5_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR5_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR5_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR5_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR5_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR5_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR5_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR5_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR5_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR5_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR5_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR5_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode enable

#define DMA_CCR6_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR6_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR6_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR6_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR6_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR6_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR6_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR6_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR6_PSIZE   ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR6_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR6_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR6_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR6_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR6_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR6_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR6_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR6_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR6_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode

#define DMA_CCR7_EN   ((uint16_t)0x0001)

Channel enable

#define DMA_CCR7_TCIE   ((uint16_t)0x0002)

Transfer complete interrupt enable

#define DMA_CCR7_HTIE   ((uint16_t)0x0004)

Half Transfer interrupt enable

#define DMA_CCR7_TEIE   ((uint16_t)0x0008)

Transfer error interrupt enable

#define DMA_CCR7_DIR   ((uint16_t)0x0010)

Data transfer direction

#define DMA_CCR7_CIRC   ((uint16_t)0x0020)

Circular mode

#define DMA_CCR7_PINC   ((uint16_t)0x0040)

Peripheral increment mode

#define DMA_CCR7_MINC   ((uint16_t)0x0080)

Memory increment mode

#define DMA_CCR7_PSIZE   , ((uint16_t)0x0300)

PSIZE[1:0] bits (Peripheral size)

#define DMA_CCR7_PSIZE_0   ((uint16_t)0x0100)

Bit 0

#define DMA_CCR7_PSIZE_1   ((uint16_t)0x0200)

Bit 1

#define DMA_CCR7_MSIZE   ((uint16_t)0x0C00)

MSIZE[1:0] bits (Memory size)

#define DMA_CCR7_MSIZE_0   ((uint16_t)0x0400)

Bit 0

#define DMA_CCR7_MSIZE_1   ((uint16_t)0x0800)

Bit 1

#define DMA_CCR7_PL   ((uint16_t)0x3000)

PL[1:0] bits (Channel Priority level)

#define DMA_CCR7_PL_0   ((uint16_t)0x1000)

Bit 0

#define DMA_CCR7_PL_1   ((uint16_t)0x2000)

Bit 1

#define DMA_CCR7_MEM2MEM   ((uint16_t)0x4000)

Memory to memory mode enable

#define DMA_CNDTR1_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR2_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR3_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR4_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR5_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR6_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CNDTR7_NDT   ((uint16_t)0xFFFF)

Number of data to Transfer

#define DMA_CPAR1_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR2_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR3_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR4_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR5_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR6_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CPAR7_PA   ((uint32_t)0xFFFFFFFF)

Peripheral Address

#define DMA_CMAR1_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR2_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR3_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR4_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR5_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR6_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define DMA_CMAR7_MA   ((uint32_t)0xFFFFFFFF)

Memory Address

#define EXTI_IMR_MR0   ((uint32_t)0x00000001)

Interrupt Mask on line 0

#define EXTI_IMR_MR1   ((uint32_t)0x00000002)

Interrupt Mask on line 1

#define EXTI_IMR_MR2   ((uint32_t)0x00000004)

Interrupt Mask on line 2

#define EXTI_IMR_MR3   ((uint32_t)0x00000008)

Interrupt Mask on line 3

#define EXTI_IMR_MR4   ((uint32_t)0x00000010)

Interrupt Mask on line 4

#define EXTI_IMR_MR5   ((uint32_t)0x00000020)

Interrupt Mask on line 5

#define EXTI_IMR_MR6   ((uint32_t)0x00000040)

Interrupt Mask on line 6

#define EXTI_IMR_MR7   ((uint32_t)0x00000080)

Interrupt Mask on line 7

#define EXTI_IMR_MR8   ((uint32_t)0x00000100)

Interrupt Mask on line 8

#define EXTI_IMR_MR9   ((uint32_t)0x00000200)

Interrupt Mask on line 9

#define EXTI_IMR_MR10   ((uint32_t)0x00000400)

Interrupt Mask on line 10

#define EXTI_IMR_MR11   ((uint32_t)0x00000800)

Interrupt Mask on line 11

#define EXTI_IMR_MR12   ((uint32_t)0x00001000)

Interrupt Mask on line 12

#define EXTI_IMR_MR13   ((uint32_t)0x00002000)

Interrupt Mask on line 13

#define EXTI_IMR_MR14   ((uint32_t)0x00004000)

Interrupt Mask on line 14

#define EXTI_IMR_MR15   ((uint32_t)0x00008000)

Interrupt Mask on line 15

#define EXTI_IMR_MR16   ((uint32_t)0x00010000)

Interrupt Mask on line 16

#define EXTI_IMR_MR17   ((uint32_t)0x00020000)

Interrupt Mask on line 17

#define EXTI_IMR_MR18   ((uint32_t)0x00040000)

Interrupt Mask on line 18

#define EXTI_IMR_MR19   ((uint32_t)0x00080000)

Interrupt Mask on line 19

#define EXTI_IMR_MR20   ((uint32_t)0x00100000)

Interrupt Mask on line 20

#define EXTI_IMR_MR21   ((uint32_t)0x00200000)

Interrupt Mask on line 21

#define EXTI_IMR_MR22   ((uint32_t)0x00400000)

Interrupt Mask on line 22

#define EXTI_IMR_MR23   ((uint32_t)0x00800000)

Interrupt Mask on line 23

#define EXTI_EMR_MR0   ((uint32_t)0x00000001)

Event Mask on line 0

#define EXTI_EMR_MR1   ((uint32_t)0x00000002)

Event Mask on line 1

#define EXTI_EMR_MR2   ((uint32_t)0x00000004)

Event Mask on line 2

#define EXTI_EMR_MR3   ((uint32_t)0x00000008)

Event Mask on line 3

#define EXTI_EMR_MR4   ((uint32_t)0x00000010)

Event Mask on line 4

#define EXTI_EMR_MR5   ((uint32_t)0x00000020)

Event Mask on line 5

#define EXTI_EMR_MR6   ((uint32_t)0x00000040)

Event Mask on line 6

#define EXTI_EMR_MR7   ((uint32_t)0x00000080)

Event Mask on line 7

#define EXTI_EMR_MR8   ((uint32_t)0x00000100)

Event Mask on line 8

#define EXTI_EMR_MR9   ((uint32_t)0x00000200)

Event Mask on line 9

#define EXTI_EMR_MR10   ((uint32_t)0x00000400)

Event Mask on line 10

#define EXTI_EMR_MR11   ((uint32_t)0x00000800)

Event Mask on line 11

#define EXTI_EMR_MR12   ((uint32_t)0x00001000)

Event Mask on line 12

#define EXTI_EMR_MR13   ((uint32_t)0x00002000)

Event Mask on line 13

#define EXTI_EMR_MR14   ((uint32_t)0x00004000)

Event Mask on line 14

#define EXTI_EMR_MR15   ((uint32_t)0x00008000)

Event Mask on line 15

#define EXTI_EMR_MR16   ((uint32_t)0x00010000)

Event Mask on line 16

#define EXTI_EMR_MR17   ((uint32_t)0x00020000)

Event Mask on line 17

#define EXTI_EMR_MR18   ((uint32_t)0x00040000)

Event Mask on line 18

#define EXTI_EMR_MR19   ((uint32_t)0x00080000)

Event Mask on line 19

#define EXTI_EMR_MR20   ((uint32_t)0x00100000)

Event Mask on line 20

#define EXTI_EMR_MR21   ((uint32_t)0x00200000)

Event Mask on line 21

#define EXTI_EMR_MR22   ((uint32_t)0x00400000)

Event Mask on line 22

#define EXTI_EMR_MR23   ((uint32_t)0x00800000)

Event Mask on line 23

#define EXTI_RTSR_TR0   ((uint32_t)0x00000001)

Rising trigger event configuration bit of line 0

#define EXTI_RTSR_TR1   ((uint32_t)0x00000002)

Rising trigger event configuration bit of line 1

#define EXTI_RTSR_TR2   ((uint32_t)0x00000004)

Rising trigger event configuration bit of line 2

#define EXTI_RTSR_TR3   ((uint32_t)0x00000008)

Rising trigger event configuration bit of line 3

#define EXTI_RTSR_TR4   ((uint32_t)0x00000010)

Rising trigger event configuration bit of line 4

#define EXTI_RTSR_TR5   ((uint32_t)0x00000020)

Rising trigger event configuration bit of line 5

#define EXTI_RTSR_TR6   ((uint32_t)0x00000040)

Rising trigger event configuration bit of line 6

#define EXTI_RTSR_TR7   ((uint32_t)0x00000080)

Rising trigger event configuration bit of line 7

#define EXTI_RTSR_TR8   ((uint32_t)0x00000100)

Rising trigger event configuration bit of line 8

#define EXTI_RTSR_TR9   ((uint32_t)0x00000200)

Rising trigger event configuration bit of line 9

#define EXTI_RTSR_TR10   ((uint32_t)0x00000400)

Rising trigger event configuration bit of line 10

#define EXTI_RTSR_TR11   ((uint32_t)0x00000800)

Rising trigger event configuration bit of line 11

#define EXTI_RTSR_TR12   ((uint32_t)0x00001000)

Rising trigger event configuration bit of line 12

#define EXTI_RTSR_TR13   ((uint32_t)0x00002000)

Rising trigger event configuration bit of line 13

#define EXTI_RTSR_TR14   ((uint32_t)0x00004000)

Rising trigger event configuration bit of line 14

#define EXTI_RTSR_TR15   ((uint32_t)0x00008000)

Rising trigger event configuration bit of line 15

#define EXTI_RTSR_TR16   ((uint32_t)0x00010000)

Rising trigger event configuration bit of line 16

#define EXTI_RTSR_TR17   ((uint32_t)0x00020000)

Rising trigger event configuration bit of line 17

#define EXTI_RTSR_TR18   ((uint32_t)0x00040000)

Rising trigger event configuration bit of line 18

#define EXTI_RTSR_TR19   ((uint32_t)0x00080000)

Rising trigger event configuration bit of line 19

#define EXTI_RTSR_TR20   ((uint32_t)0x00100000)

Rising trigger event configuration bit of line 20

#define EXTI_RTSR_TR21   ((uint32_t)0x00200000)

Rising trigger event configuration bit of line 21

#define EXTI_RTSR_TR22   ((uint32_t)0x00400000)

Rising trigger event configuration bit of line 22

#define EXTI_RTSR_TR23   ((uint32_t)0x00800000)

Rising trigger event configuration bit of line 23

#define EXTI_FTSR_TR0   ((uint32_t)0x00000001)

Falling trigger event configuration bit of line 0

#define EXTI_FTSR_TR1   ((uint32_t)0x00000002)

Falling trigger event configuration bit of line 1

#define EXTI_FTSR_TR2   ((uint32_t)0x00000004)

Falling trigger event configuration bit of line 2

#define EXTI_FTSR_TR3   ((uint32_t)0x00000008)

Falling trigger event configuration bit of line 3

#define EXTI_FTSR_TR4   ((uint32_t)0x00000010)

Falling trigger event configuration bit of line 4

#define EXTI_FTSR_TR5   ((uint32_t)0x00000020)

Falling trigger event configuration bit of line 5

#define EXTI_FTSR_TR6   ((uint32_t)0x00000040)

Falling trigger event configuration bit of line 6

#define EXTI_FTSR_TR7   ((uint32_t)0x00000080)

Falling trigger event configuration bit of line 7

#define EXTI_FTSR_TR8   ((uint32_t)0x00000100)

Falling trigger event configuration bit of line 8

#define EXTI_FTSR_TR9   ((uint32_t)0x00000200)

Falling trigger event configuration bit of line 9

#define EXTI_FTSR_TR10   ((uint32_t)0x00000400)

Falling trigger event configuration bit of line 10

#define EXTI_FTSR_TR11   ((uint32_t)0x00000800)

Falling trigger event configuration bit of line 11

#define EXTI_FTSR_TR12   ((uint32_t)0x00001000)

Falling trigger event configuration bit of line 12

#define EXTI_FTSR_TR13   ((uint32_t)0x00002000)

Falling trigger event configuration bit of line 13

#define EXTI_FTSR_TR14   ((uint32_t)0x00004000)

Falling trigger event configuration bit of line 14

#define EXTI_FTSR_TR15   ((uint32_t)0x00008000)

Falling trigger event configuration bit of line 15

#define EXTI_FTSR_TR16   ((uint32_t)0x00010000)

Falling trigger event configuration bit of line 16

#define EXTI_FTSR_TR17   ((uint32_t)0x00020000)

Falling trigger event configuration bit of line 17

#define EXTI_FTSR_TR18   ((uint32_t)0x00040000)

Falling trigger event configuration bit of line 18

#define EXTI_FTSR_TR19   ((uint32_t)0x00080000)

Falling trigger event configuration bit of line 19

#define EXTI_FTSR_TR20   ((uint32_t)0x00100000)

Falling trigger event configuration bit of line 20

#define EXTI_FTSR_TR21   ((uint32_t)0x00200000)

Falling trigger event configuration bit of line 21

#define EXTI_FTSR_TR22   ((uint32_t)0x00400000)

Falling trigger event configuration bit of line 22

#define EXTI_FTSR_TR23   ((uint32_t)0x00800000)

Falling trigger event configuration bit of line 23

#define EXTI_SWIER_SWIER0   ((uint32_t)0x00000001)

Software Interrupt on line 0

#define EXTI_SWIER_SWIER1   ((uint32_t)0x00000002)

Software Interrupt on line 1

#define EXTI_SWIER_SWIER2   ((uint32_t)0x00000004)

Software Interrupt on line 2

#define EXTI_SWIER_SWIER3   ((uint32_t)0x00000008)

Software Interrupt on line 3

#define EXTI_SWIER_SWIER4   ((uint32_t)0x00000010)

Software Interrupt on line 4

#define EXTI_SWIER_SWIER5   ((uint32_t)0x00000020)

Software Interrupt on line 5

#define EXTI_SWIER_SWIER6   ((uint32_t)0x00000040)

Software Interrupt on line 6

#define EXTI_SWIER_SWIER7   ((uint32_t)0x00000080)

Software Interrupt on line 7

#define EXTI_SWIER_SWIER8   ((uint32_t)0x00000100)

Software Interrupt on line 8

#define EXTI_SWIER_SWIER9   ((uint32_t)0x00000200)

Software Interrupt on line 9

#define EXTI_SWIER_SWIER10   ((uint32_t)0x00000400)

Software Interrupt on line 10

#define EXTI_SWIER_SWIER11   ((uint32_t)0x00000800)

Software Interrupt on line 11

#define EXTI_SWIER_SWIER12   ((uint32_t)0x00001000)

Software Interrupt on line 12

#define EXTI_SWIER_SWIER13   ((uint32_t)0x00002000)

Software Interrupt on line 13

#define EXTI_SWIER_SWIER14   ((uint32_t)0x00004000)

Software Interrupt on line 14

#define EXTI_SWIER_SWIER15   ((uint32_t)0x00008000)

Software Interrupt on line 15

#define EXTI_SWIER_SWIER16   ((uint32_t)0x00010000)

Software Interrupt on line 16

#define EXTI_SWIER_SWIER17   ((uint32_t)0x00020000)

Software Interrupt on line 17

#define EXTI_SWIER_SWIER18   ((uint32_t)0x00040000)

Software Interrupt on line 18

#define EXTI_SWIER_SWIER19   ((uint32_t)0x00080000)

Software Interrupt on line 19

#define EXTI_SWIER_SWIER20   ((uint32_t)0x00100000)

Software Interrupt on line 20

#define EXTI_SWIER_SWIER21   ((uint32_t)0x00200000)

Software Interrupt on line 21

#define EXTI_SWIER_SWIER22   ((uint32_t)0x00400000)

Software Interrupt on line 22

#define EXTI_SWIER_SWIER23   ((uint32_t)0x00800000)

Software Interrupt on line 23

#define EXTI_PR_PR0   ((uint32_t)0x00000001)

Pending bit 0

#define EXTI_PR_PR1   ((uint32_t)0x00000002)

Pending bit 1

#define EXTI_PR_PR2   ((uint32_t)0x00000004)

Pending bit 2

#define EXTI_PR_PR3   ((uint32_t)0x00000008)

Pending bit 3

#define EXTI_PR_PR4   ((uint32_t)0x00000010)

Pending bit 4

#define EXTI_PR_PR5   ((uint32_t)0x00000020)

Pending bit 5

#define EXTI_PR_PR6   ((uint32_t)0x00000040)

Pending bit 6

#define EXTI_PR_PR7   ((uint32_t)0x00000080)

Pending bit 7

#define EXTI_PR_PR8   ((uint32_t)0x00000100)

Pending bit 8

#define EXTI_PR_PR9   ((uint32_t)0x00000200)

Pending bit 9

#define EXTI_PR_PR10   ((uint32_t)0x00000400)

Pending bit 10

#define EXTI_PR_PR11   ((uint32_t)0x00000800)

Pending bit 11

#define EXTI_PR_PR12   ((uint32_t)0x00001000)

Pending bit 12

#define EXTI_PR_PR13   ((uint32_t)0x00002000)

Pending bit 13

#define EXTI_PR_PR14   ((uint32_t)0x00004000)

Pending bit 14

#define EXTI_PR_PR15   ((uint32_t)0x00008000)

Pending bit 15

#define EXTI_PR_PR16   ((uint32_t)0x00010000)

Pending bit 16

#define EXTI_PR_PR17   ((uint32_t)0x00020000)

Pending bit 17

#define EXTI_PR_PR18   ((uint32_t)0x00040000)

Pending bit 18

#define EXTI_PR_PR19   ((uint32_t)0x00080000)

Pending bit 19

#define EXTI_PR_PR20   ((uint32_t)0x00100000)

Pending bit 20

#define EXTI_PR_PR21   ((uint32_t)0x00200000)

Pending bit 21

#define EXTI_PR_PR22   ((uint32_t)0x00400000)

Pending bit 22

#define EXTI_PR_PR23   ((uint32_t)0x00800000)

Pending bit 23

#define FLASH_ACR_LATENCY   ((uint32_t)0x00000001)

Latency

#define FLASH_ACR_PRFTEN   ((uint32_t)0x00000002)

Prefetch Buffer Enable

#define FLASH_ACR_ACC64   ((uint32_t)0x00000004)

Access 64 bits

#define FLASH_ACR_SLEEP_PD   ((uint32_t)0x00000008)

Flash mode during sleep mode

#define FLASH_ACR_RUN_PD   ((uint32_t)0x00000010)

Flash mode during RUN mode

#define FLASH_PECR_PELOCK   ((uint32_t)0x00000001)

FLASH_PECR and Flash data Lock

#define FLASH_PECR_PRGLOCK   ((uint32_t)0x00000002)

Program matrix Lock

#define FLASH_PECR_OPTLOCK   ((uint32_t)0x00000004)

Option byte matrix Lock

#define FLASH_PECR_PROG   ((uint32_t)0x00000008)

Program matrix selection

#define FLASH_PECR_DATA   ((uint32_t)0x00000010)

Data matrix selection

#define FLASH_PECR_FTDW   ((uint32_t)0x00000100)

Fixed Time Data write for Word/Half Word/Byte programming

#define FLASH_PECR_ERASE   ((uint32_t)0x00000200)

Page erasing mode

#define FLASH_PECR_FPRG   ((uint32_t)0x00000400)

Fast Page/Half Page programming mode

#define FLASH_PECR_PARALLBANK   ((uint32_t)0x00008000)

Parallel Bank mode

#define FLASH_PECR_EOPIE   ((uint32_t)0x00010000)

End of programming interrupt

#define FLASH_PECR_ERRIE   ((uint32_t)0x00020000)

Error interrupt

#define FLASH_PECR_OBL_LAUNCH   ((uint32_t)0x00040000)

Launch the option byte loading

#define FLASH_PDKEYR_PDKEYR   ((uint32_t)0xFFFFFFFF)

FLASH_PEC and data matrix Key

#define FLASH_PEKEYR_PEKEYR   ((uint32_t)0xFFFFFFFF)

FLASH_PEC and data matrix Key

#define FLASH_PRGKEYR_PRGKEYR   ((uint32_t)0xFFFFFFFF)

Program matrix Key

#define FLASH_OPTKEYR_OPTKEYR   ((uint32_t)0xFFFFFFFF)

Option bytes matrix Key

#define FLASH_SR_BSY   ((uint32_t)0x00000001)

Busy

#define FLASH_SR_EOP   ((uint32_t)0x00000002)

End Of Programming

#define FLASH_SR_ENHV   ((uint32_t)0x00000004)

End of high voltage

#define FLASH_SR_READY   ((uint32_t)0x00000008)

Flash ready after low power mode

#define FLASH_SR_WRPERR   ((uint32_t)0x00000100)

Write protected error

#define FLASH_SR_PGAERR   ((uint32_t)0x00000200)

Programming Alignment Error

#define FLASH_SR_SIZERR   ((uint32_t)0x00000400)

Size error

#define FLASH_SR_OPTVERR   ((uint32_t)0x00000800)

Option validity error

#define FLASH_SR_OPTVERRUSR   ((uint32_t)0x00001000)

Option User validity error

#define FLASH_OBR_RDPRT   ((uint16_t)0x000000AA)

Read Protection

#define FLASH_OBR_BOR_LEV   ((uint16_t)0x000F0000)

BOR_LEV[3:0] Brown Out Reset Threshold Level

#define FLASH_OBR_USER   ((uint32_t)0x00700000)

User Option Bytes

#define FLASH_OBR_IWDG_SW   ((uint32_t)0x00100000)

IWDG_SW

#define FLASH_OBR_nRST_STOP   ((uint32_t)0x00200000)

nRST_STOP

#define FLASH_OBR_nRST_STDBY   ((uint32_t)0x00400000)

nRST_STDBY

#define FLASH_OBR_nRST_BFB2   ((uint32_t)0x00800000)

BFB2

#define FLASH_WRPR_WRP   ((uint32_t)0xFFFFFFFF)

Write Protect

#define FLASH_WRPR1_WRP   ((uint32_t)0xFFFFFFFF)

Write Protect

#define FLASH_WRPR2_WRP   ((uint32_t)0xFFFFFFFF)

Write Protect

#define FSMC_BCR1_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR1_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR1_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR1_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR1_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR1_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR1_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR1_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR1_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR1_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR1_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR1_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR1_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR1_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR1_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR1_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR1_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR1_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR2_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR2_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR2_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR2_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR2_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR2_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR2_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR2_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR2_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR2_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR2_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR2_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR2_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR2_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR2_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR2_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR2_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR2_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR3_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR3_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR3_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR3_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR3_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR3_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR3_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR3_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR3_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR3_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR3_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit.

#define FSMC_BCR3_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR3_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR3_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR3_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR3_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR3_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR3_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BCR4_MBKEN   ((uint32_t)0x00000001)

Memory bank enable bit

#define FSMC_BCR4_MUXEN   ((uint32_t)0x00000002)

Address/data multiplexing enable bit

#define FSMC_BCR4_MTYP   ((uint32_t)0x0000000C)

MTYP[1:0] bits (Memory type)

#define FSMC_BCR4_MTYP_0   ((uint32_t)0x00000004)

Bit 0

#define FSMC_BCR4_MTYP_1   ((uint32_t)0x00000008)

Bit 1

#define FSMC_BCR4_MWID   ((uint32_t)0x00000030)

MWID[1:0] bits (Memory data bus width)

#define FSMC_BCR4_MWID_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BCR4_MWID_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BCR4_FACCEN   ((uint32_t)0x00000040)

Flash access enable

#define FSMC_BCR4_BURSTEN   ((uint32_t)0x00000100)

Burst enable bit

#define FSMC_BCR4_WAITPOL   ((uint32_t)0x00000200)

Wait signal polarity bit

#define FSMC_BCR4_WRAPMOD   ((uint32_t)0x00000400)

Wrapped burst mode support

#define FSMC_BCR4_WAITCFG   ((uint32_t)0x00000800)

Wait timing configuration

#define FSMC_BCR4_WREN   ((uint32_t)0x00001000)

Write enable bit

#define FSMC_BCR4_WAITEN   ((uint32_t)0x00002000)

Wait enable bit

#define FSMC_BCR4_EXTMOD   ((uint32_t)0x00004000)

Extended mode enable

#define FSMC_BCR4_ASYNCWAIT   ((uint32_t)0x00008000)

Asynchronous wait

#define FSMC_BCR4_CBURSTRW   ((uint32_t)0x00080000)

Write burst enable

#define FSMC_BTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR1_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR1_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR1_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR1_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR1_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR2_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR2_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR2_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR2_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR2_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR3_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR3_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR3_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR3_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR3_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BTR4_BUSTURN   ((uint32_t)0x000F0000)

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FSMC_BTR4_BUSTURN_0   ((uint32_t)0x00010000)

Bit 0

#define FSMC_BTR4_BUSTURN_1   ((uint32_t)0x00020000)

Bit 1

#define FSMC_BTR4_BUSTURN_2   ((uint32_t)0x00040000)

Bit 2

#define FSMC_BTR4_BUSTURN_3   ((uint32_t)0x00080000)

Bit 3

#define FSMC_BTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR1_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR1_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR1_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR1_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR1_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR1_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR1_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR1_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR1_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR1_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR1_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR1_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR1_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR1_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR1_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR1_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR1_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR1_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR1_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR1_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR1_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR1_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR1_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR1_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR1_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR1_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR1_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR1_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR2_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR2_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR2_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR2_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR2_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR2_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR2_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR2_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR2_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR2_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR2_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR2_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR2_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR2_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR2_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR2_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR2_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR2_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR2_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR2_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR2_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR2_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR2_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR2_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR2_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR2_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR2_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR2_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR3_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR3_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR3_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR3_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR3_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR3_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR3_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR3_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR3_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR3_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR3_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR3_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR3_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR3_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR3_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR3_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR3_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR3_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR3_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR3_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR3_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR3_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR3_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR3_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR3_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR3_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR3_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR3_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define FSMC_BWTR4_ADDSET   ((uint32_t)0x0000000F)

ADDSET[3:0] bits (Address setup phase duration)

#define FSMC_BWTR4_ADDSET_0   ((uint32_t)0x00000001)

Bit 0

#define FSMC_BWTR4_ADDSET_1   ((uint32_t)0x00000002)

Bit 1

#define FSMC_BWTR4_ADDSET_2   ((uint32_t)0x00000004)

Bit 2

#define FSMC_BWTR4_ADDSET_3   ((uint32_t)0x00000008)

Bit 3

#define FSMC_BWTR4_ADDHLD   ((uint32_t)0x000000F0)

ADDHLD[3:0] bits (Address-hold phase duration)

#define FSMC_BWTR4_ADDHLD_0   ((uint32_t)0x00000010)

Bit 0

#define FSMC_BWTR4_ADDHLD_1   ((uint32_t)0x00000020)

Bit 1

#define FSMC_BWTR4_ADDHLD_2   ((uint32_t)0x00000040)

Bit 2

#define FSMC_BWTR4_ADDHLD_3   ((uint32_t)0x00000080)

Bit 3

#define FSMC_BWTR4_DATAST   ((uint32_t)0x0000FF00)

DATAST [3:0] bits (Data-phase duration)

#define FSMC_BWTR4_DATAST_0   ((uint32_t)0x00000100)

Bit 0

#define FSMC_BWTR4_DATAST_1   ((uint32_t)0x00000200)

Bit 1

#define FSMC_BWTR4_DATAST_2   ((uint32_t)0x00000400)

Bit 2

#define FSMC_BWTR4_DATAST_3   ((uint32_t)0x00000800)

Bit 3

#define FSMC_BWTR4_CLKDIV   ((uint32_t)0x00F00000)

CLKDIV[3:0] bits (Clock divide ratio)

#define FSMC_BWTR4_CLKDIV_0   ((uint32_t)0x00100000)

Bit 0

#define FSMC_BWTR4_CLKDIV_1   ((uint32_t)0x00200000)

Bit 1

#define FSMC_BWTR4_CLKDIV_2   ((uint32_t)0x00400000)

Bit 2

#define FSMC_BWTR4_CLKDIV_3   ((uint32_t)0x00800000)

Bit 3

#define FSMC_BWTR4_DATLAT   ((uint32_t)0x0F000000)

DATLA[3:0] bits (Data latency)

#define FSMC_BWTR4_DATLAT_0   ((uint32_t)0x01000000)

Bit 0

#define FSMC_BWTR4_DATLAT_1   ((uint32_t)0x02000000)

Bit 1

#define FSMC_BWTR4_DATLAT_2   ((uint32_t)0x04000000)

Bit 2

#define FSMC_BWTR4_DATLAT_3   ((uint32_t)0x08000000)

Bit 3

#define FSMC_BWTR4_ACCMOD   ((uint32_t)0x30000000)

ACCMOD[1:0] bits (Access mode)

#define FSMC_BWTR4_ACCMOD_0   ((uint32_t)0x10000000)

Bit 0

#define FSMC_BWTR4_ACCMOD_1   ((uint32_t)0x20000000)

Bit 1

#define GPIO_MODER_MODER0   ((uint32_t)0x00000003)

#define GPIO_MODER_MODER0_0   ((uint32_t)0x00000001)

#define GPIO_MODER_MODER0_1   ((uint32_t)0x00000002)

#define GPIO_MODER_MODER1   ((uint32_t)0x0000000C)

#define GPIO_MODER_MODER1_0   ((uint32_t)0x00000004)

#define GPIO_MODER_MODER1_1   ((uint32_t)0x00000008)

#define GPIO_MODER_MODER2   ((uint32_t)0x00000030)

#define GPIO_MODER_MODER2_0   ((uint32_t)0x00000010)

#define GPIO_MODER_MODER2_1   ((uint32_t)0x00000020)

#define GPIO_MODER_MODER3   ((uint32_t)0x000000C0)

#define GPIO_MODER_MODER3_0   ((uint32_t)0x00000040)

#define GPIO_MODER_MODER3_1   ((uint32_t)0x00000080)

#define GPIO_MODER_MODER4   ((uint32_t)0x00000300)

#define GPIO_MODER_MODER4_0   ((uint32_t)0x00000100)

#define GPIO_MODER_MODER4_1   ((uint32_t)0x00000200)

#define GPIO_MODER_MODER5   ((uint32_t)0x00000C00)

#define GPIO_MODER_MODER5_0   ((uint32_t)0x00000400)

#define GPIO_MODER_MODER5_1   ((uint32_t)0x00000800)

#define GPIO_MODER_MODER6   ((uint32_t)0x00003000)

#define GPIO_MODER_MODER6_0   ((uint32_t)0x00001000)

#define GPIO_MODER_MODER6_1   ((uint32_t)0x00002000)

#define GPIO_MODER_MODER7   ((uint32_t)0x0000C000)

#define GPIO_MODER_MODER7_0   ((uint32_t)0x00004000)

#define GPIO_MODER_MODER7_1   ((uint32_t)0x00008000)

#define GPIO_MODER_MODER8   ((uint32_t)0x00030000)

#define GPIO_MODER_MODER8_0   ((uint32_t)0x00010000)

#define GPIO_MODER_MODER8_1   ((uint32_t)0x00020000)

#define GPIO_MODER_MODER9   ((uint32_t)0x000C0000)

#define GPIO_MODER_MODER9_0   ((uint32_t)0x00040000)

#define GPIO_MODER_MODER9_1   ((uint32_t)0x00080000)

#define GPIO_MODER_MODER10   ((uint32_t)0x00300000)

#define GPIO_MODER_MODER10_0   ((uint32_t)0x00100000)

#define GPIO_MODER_MODER10_1   ((uint32_t)0x00200000)

#define GPIO_MODER_MODER11   ((uint32_t)0x00C00000)

#define GPIO_MODER_MODER11_0   ((uint32_t)0x00400000)

#define GPIO_MODER_MODER11_1   ((uint32_t)0x00800000)

#define GPIO_MODER_MODER12   ((uint32_t)0x03000000)

#define GPIO_MODER_MODER12_0   ((uint32_t)0x01000000)

#define GPIO_MODER_MODER12_1   ((uint32_t)0x02000000)

#define GPIO_MODER_MODER13   ((uint32_t)0x0C000000)

#define GPIO_MODER_MODER13_0   ((uint32_t)0x04000000)

#define GPIO_MODER_MODER13_1   ((uint32_t)0x08000000)

#define GPIO_MODER_MODER14   ((uint32_t)0x30000000)

#define GPIO_MODER_MODER14_0   ((uint32_t)0x10000000)

#define GPIO_MODER_MODER14_1   ((uint32_t)0x20000000)

#define GPIO_MODER_MODER15   ((uint32_t)0xC0000000)

#define GPIO_MODER_MODER15_0   ((uint32_t)0x40000000)

#define GPIO_MODER_MODER15_1   ((uint32_t)0x80000000)

#define GPIO_OTYPER_OT_0   ((uint32_t)0x00000001)

#define GPIO_OTYPER_OT_1   ((uint32_t)0x00000002)

#define GPIO_OTYPER_OT_2   ((uint32_t)0x00000004)

#define GPIO_OTYPER_OT_3   ((uint32_t)0x00000008)

#define GPIO_OTYPER_OT_4   ((uint32_t)0x00000010)

#define GPIO_OTYPER_OT_5   ((uint32_t)0x00000020)

#define GPIO_OTYPER_OT_6   ((uint32_t)0x00000040)

#define GPIO_OTYPER_OT_7   ((uint32_t)0x00000080)

#define GPIO_OTYPER_OT_8   ((uint32_t)0x00000100)

#define GPIO_OTYPER_OT_9   ((uint32_t)0x00000200)

#define GPIO_OTYPER_OT_10   ((uint32_t)0x00000400)

#define GPIO_OTYPER_OT_11   ((uint32_t)0x00000800)

#define GPIO_OTYPER_OT_12   ((uint32_t)0x00001000)

#define GPIO_OTYPER_OT_13   ((uint32_t)0x00002000)

#define GPIO_OTYPER_OT_14   ((uint32_t)0x00004000)

#define GPIO_OTYPER_OT_15   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR0   ((uint32_t)0x00000003)

#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)

#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)

#define GPIO_OSPEEDER_OSPEEDR1   ((uint32_t)0x0000000C)

#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)

#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)

#define GPIO_OSPEEDER_OSPEEDR2   ((uint32_t)0x00000030)

#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)

#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)

#define GPIO_OSPEEDER_OSPEEDR3   ((uint32_t)0x000000C0)

#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)

#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)

#define GPIO_OSPEEDER_OSPEEDR4   ((uint32_t)0x00000300)

#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)

#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)

#define GPIO_OSPEEDER_OSPEEDR5   ((uint32_t)0x00000C00)

#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)

#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)

#define GPIO_OSPEEDER_OSPEEDR6   ((uint32_t)0x00003000)

#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)

#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)

#define GPIO_OSPEEDER_OSPEEDR7   ((uint32_t)0x0000C000)

#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)

#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)

#define GPIO_OSPEEDER_OSPEEDR8   ((uint32_t)0x00030000)

#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)

#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)

#define GPIO_OSPEEDER_OSPEEDR9   ((uint32_t)0x000C0000)

#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)

#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)

#define GPIO_OSPEEDER_OSPEEDR10   ((uint32_t)0x00300000)

#define GPIO_OSPEEDER_OSPEEDR10_0   ((uint32_t)0x00100000)

#define GPIO_OSPEEDER_OSPEEDR10_1   ((uint32_t)0x00200000)

#define GPIO_OSPEEDER_OSPEEDR11   ((uint32_t)0x00C00000)

#define GPIO_OSPEEDER_OSPEEDR11_0   ((uint32_t)0x00400000)

#define GPIO_OSPEEDER_OSPEEDR11_1   ((uint32_t)0x00800000)

#define GPIO_OSPEEDER_OSPEEDR12   ((uint32_t)0x03000000)

#define GPIO_OSPEEDER_OSPEEDR12_0   ((uint32_t)0x01000000)

#define GPIO_OSPEEDER_OSPEEDR12_1   ((uint32_t)0x02000000)

#define GPIO_OSPEEDER_OSPEEDR13   ((uint32_t)0x0C000000)

#define GPIO_OSPEEDER_OSPEEDR13_0   ((uint32_t)0x04000000)

#define GPIO_OSPEEDER_OSPEEDR13_1   ((uint32_t)0x08000000)

#define GPIO_OSPEEDER_OSPEEDR14   ((uint32_t)0x30000000)

#define GPIO_OSPEEDER_OSPEEDR14_0   ((uint32_t)0x10000000)

#define GPIO_OSPEEDER_OSPEEDR14_1   ((uint32_t)0x20000000)

#define GPIO_OSPEEDER_OSPEEDR15   ((uint32_t)0xC0000000)

#define GPIO_OSPEEDER_OSPEEDR15_0   ((uint32_t)0x40000000)

#define GPIO_OSPEEDER_OSPEEDR15_1   ((uint32_t)0x80000000)

#define GPIO_PUPDR_PUPDR0   ((uint32_t)0x00000003)

#define GPIO_PUPDR_PUPDR0_0   ((uint32_t)0x00000001)

#define GPIO_PUPDR_PUPDR0_1   ((uint32_t)0x00000002)

#define GPIO_PUPDR_PUPDR1   ((uint32_t)0x0000000C)

#define GPIO_PUPDR_PUPDR1_0   ((uint32_t)0x00000004)

#define GPIO_PUPDR_PUPDR1_1   ((uint32_t)0x00000008)

#define GPIO_PUPDR_PUPDR2   ((uint32_t)0x00000030)

#define GPIO_PUPDR_PUPDR2_0   ((uint32_t)0x00000010)

#define GPIO_PUPDR_PUPDR2_1   ((uint32_t)0x00000020)

#define GPIO_PUPDR_PUPDR3   ((uint32_t)0x000000C0)

#define GPIO_PUPDR_PUPDR3_0   ((uint32_t)0x00000040)

#define GPIO_PUPDR_PUPDR3_1   ((uint32_t)0x00000080)

#define GPIO_PUPDR_PUPDR4   ((uint32_t)0x00000300)

#define GPIO_PUPDR_PUPDR4_0   ((uint32_t)0x00000100)

#define GPIO_PUPDR_PUPDR4_1   ((uint32_t)0x00000200)

#define GPIO_PUPDR_PUPDR5   ((uint32_t)0x00000C00)

#define GPIO_PUPDR_PUPDR5_0   ((uint32_t)0x00000400)

#define GPIO_PUPDR_PUPDR5_1   ((uint32_t)0x00000800)

#define GPIO_PUPDR_PUPDR6   ((uint32_t)0x00003000)

#define GPIO_PUPDR_PUPDR6_0   ((uint32_t)0x00001000)

#define GPIO_PUPDR_PUPDR6_1   ((uint32_t)0x00002000)

#define GPIO_PUPDR_PUPDR7   ((uint32_t)0x0000C000)

#define GPIO_PUPDR_PUPDR7_0   ((uint32_t)0x00004000)

#define GPIO_PUPDR_PUPDR7_1   ((uint32_t)0x00008000)

#define GPIO_PUPDR_PUPDR8   ((uint32_t)0x00030000)

#define GPIO_PUPDR_PUPDR8_0   ((uint32_t)0x00010000)

#define GPIO_PUPDR_PUPDR8_1   ((uint32_t)0x00020000)

#define GPIO_PUPDR_PUPDR9   ((uint32_t)0x000C0000)

#define GPIO_PUPDR_PUPDR9_0   ((uint32_t)0x00040000)

#define GPIO_PUPDR_PUPDR9_1   ((uint32_t)0x00080000)

#define GPIO_PUPDR_PUPDR10   ((uint32_t)0x00300000)

#define GPIO_PUPDR_PUPDR10_0   ((uint32_t)0x00100000)

#define GPIO_PUPDR_PUPDR10_1   ((uint32_t)0x00200000)

#define GPIO_PUPDR_PUPDR11   ((uint32_t)0x00C00000)

#define GPIO_PUPDR_PUPDR11_0   ((uint32_t)0x00400000)

#define GPIO_PUPDR_PUPDR11_1   ((uint32_t)0x00800000)

#define GPIO_PUPDR_PUPDR12   ((uint32_t)0x03000000)

#define GPIO_PUPDR_PUPDR12_0   ((uint32_t)0x01000000)

#define GPIO_PUPDR_PUPDR12_1   ((uint32_t)0x02000000)

#define GPIO_PUPDR_PUPDR13   ((uint32_t)0x0C000000)

#define GPIO_PUPDR_PUPDR13_0   ((uint32_t)0x04000000)

#define GPIO_PUPDR_PUPDR13_1   ((uint32_t)0x08000000)

#define GPIO_PUPDR_PUPDR14   ((uint32_t)0x30000000)

#define GPIO_PUPDR_PUPDR14_0   ((uint32_t)0x10000000)

#define GPIO_PUPDR_PUPDR14_1   ((uint32_t)0x20000000)

#define GPIO_PUPDR_PUPDR15   ((uint32_t)0xC0000000)

#define GPIO_PUPDR_PUPDR15_0   ((uint32_t)0x40000000)

#define GPIO_PUPDR_PUPDR15_1   ((uint32_t)0x80000000)

#define GPIO_IDR_IDR_0   ((uint32_t)0x00000001)

#define GPIO_IDR_IDR_1   ((uint32_t)0x00000002)

#define GPIO_IDR_IDR_2   ((uint32_t)0x00000004)

#define GPIO_IDR_IDR_3   ((uint32_t)0x00000008)

#define GPIO_IDR_IDR_4   ((uint32_t)0x00000010)

#define GPIO_IDR_IDR_5   ((uint32_t)0x00000020)

#define GPIO_IDR_IDR_6   ((uint32_t)0x00000040)

#define GPIO_IDR_IDR_7   ((uint32_t)0x00000080)

#define GPIO_IDR_IDR_8   ((uint32_t)0x00000100)

#define GPIO_IDR_IDR_9   ((uint32_t)0x00000200)

#define GPIO_IDR_IDR_10   ((uint32_t)0x00000400)

#define GPIO_IDR_IDR_11   ((uint32_t)0x00000800)

#define GPIO_IDR_IDR_12   ((uint32_t)0x00001000)

#define GPIO_IDR_IDR_13   ((uint32_t)0x00002000)

#define GPIO_IDR_IDR_14   ((uint32_t)0x00004000)

#define GPIO_IDR_IDR_15   ((uint32_t)0x00008000)

#define GPIO_OTYPER_IDR_0   GPIO_IDR_IDR_0

#define GPIO_OTYPER_IDR_1   GPIO_IDR_IDR_1

#define GPIO_OTYPER_IDR_2   GPIO_IDR_IDR_2

#define GPIO_OTYPER_IDR_3   GPIO_IDR_IDR_3

#define GPIO_OTYPER_IDR_4   GPIO_IDR_IDR_4

#define GPIO_OTYPER_IDR_5   GPIO_IDR_IDR_5

#define GPIO_OTYPER_IDR_6   GPIO_IDR_IDR_6

#define GPIO_OTYPER_IDR_7   GPIO_IDR_IDR_7

#define GPIO_OTYPER_IDR_8   GPIO_IDR_IDR_8

#define GPIO_OTYPER_IDR_9   GPIO_IDR_IDR_9

#define GPIO_OTYPER_IDR_10   GPIO_IDR_IDR_10

#define GPIO_OTYPER_IDR_11   GPIO_IDR_IDR_11

#define GPIO_OTYPER_IDR_12   GPIO_IDR_IDR_12

#define GPIO_OTYPER_IDR_13   GPIO_IDR_IDR_13

#define GPIO_OTYPER_IDR_14   GPIO_IDR_IDR_14

#define GPIO_OTYPER_IDR_15   GPIO_IDR_IDR_15

#define GPIO_ODR_ODR_0   ((uint32_t)0x00000001)

#define GPIO_ODR_ODR_1   ((uint32_t)0x00000002)

#define GPIO_ODR_ODR_2   ((uint32_t)0x00000004)

#define GPIO_ODR_ODR_3   ((uint32_t)0x00000008)

#define GPIO_ODR_ODR_4   ((uint32_t)0x00000010)

#define GPIO_ODR_ODR_5   ((uint32_t)0x00000020)

#define GPIO_ODR_ODR_6   ((uint32_t)0x00000040)

#define GPIO_ODR_ODR_7   ((uint32_t)0x00000080)

#define GPIO_ODR_ODR_8   ((uint32_t)0x00000100)

#define GPIO_ODR_ODR_9   ((uint32_t)0x00000200)

#define GPIO_ODR_ODR_10   ((uint32_t)0x00000400)

#define GPIO_ODR_ODR_11   ((uint32_t)0x00000800)

#define GPIO_ODR_ODR_12   ((uint32_t)0x00001000)

#define GPIO_ODR_ODR_13   ((uint32_t)0x00002000)

#define GPIO_ODR_ODR_14   ((uint32_t)0x00004000)

#define GPIO_ODR_ODR_15   ((uint32_t)0x00008000)

#define GPIO_OTYPER_ODR_0   GPIO_ODR_ODR_0

#define GPIO_OTYPER_ODR_1   GPIO_ODR_ODR_1

#define GPIO_OTYPER_ODR_2   GPIO_ODR_ODR_2

#define GPIO_OTYPER_ODR_3   GPIO_ODR_ODR_3

#define GPIO_OTYPER_ODR_4   GPIO_ODR_ODR_4

#define GPIO_OTYPER_ODR_5   GPIO_ODR_ODR_5

#define GPIO_OTYPER_ODR_6   GPIO_ODR_ODR_6

#define GPIO_OTYPER_ODR_7   GPIO_ODR_ODR_7

#define GPIO_OTYPER_ODR_8   GPIO_ODR_ODR_8

#define GPIO_OTYPER_ODR_9   GPIO_ODR_ODR_9

#define GPIO_OTYPER_ODR_10   GPIO_ODR_ODR_10

#define GPIO_OTYPER_ODR_11   GPIO_ODR_ODR_11

#define GPIO_OTYPER_ODR_12   GPIO_ODR_ODR_12

#define GPIO_OTYPER_ODR_13   GPIO_ODR_ODR_13

#define GPIO_OTYPER_ODR_14   GPIO_ODR_ODR_14

#define GPIO_OTYPER_ODR_15   GPIO_ODR_ODR_15

#define GPIO_BSRR_BS_0   ((uint32_t)0x00000001)

#define GPIO_BSRR_BS_1   ((uint32_t)0x00000002)

#define GPIO_BSRR_BS_2   ((uint32_t)0x00000004)

#define GPIO_BSRR_BS_3   ((uint32_t)0x00000008)

#define GPIO_BSRR_BS_4   ((uint32_t)0x00000010)

#define GPIO_BSRR_BS_5   ((uint32_t)0x00000020)

#define GPIO_BSRR_BS_6   ((uint32_t)0x00000040)

#define GPIO_BSRR_BS_7   ((uint32_t)0x00000080)

#define GPIO_BSRR_BS_8   ((uint32_t)0x00000100)

#define GPIO_BSRR_BS_9   ((uint32_t)0x00000200)

#define GPIO_BSRR_BS_10   ((uint32_t)0x00000400)

#define GPIO_BSRR_BS_11   ((uint32_t)0x00000800)

#define GPIO_BSRR_BS_12   ((uint32_t)0x00001000)

#define GPIO_BSRR_BS_13   ((uint32_t)0x00002000)

#define GPIO_BSRR_BS_14   ((uint32_t)0x00004000)

#define GPIO_BSRR_BS_15   ((uint32_t)0x00008000)

#define GPIO_BSRR_BR_0   ((uint32_t)0x00010000)

#define GPIO_BSRR_BR_1   ((uint32_t)0x00020000)

#define GPIO_BSRR_BR_2   ((uint32_t)0x00040000)

#define GPIO_BSRR_BR_3   ((uint32_t)0x00080000)

#define GPIO_BSRR_BR_4   ((uint32_t)0x00100000)

#define GPIO_BSRR_BR_5   ((uint32_t)0x00200000)

#define GPIO_BSRR_BR_6   ((uint32_t)0x00400000)

#define GPIO_BSRR_BR_7   ((uint32_t)0x00800000)

#define GPIO_BSRR_BR_8   ((uint32_t)0x01000000)

#define GPIO_BSRR_BR_9   ((uint32_t)0x02000000)

#define GPIO_BSRR_BR_10   ((uint32_t)0x04000000)

#define GPIO_BSRR_BR_11   ((uint32_t)0x08000000)

#define GPIO_BSRR_BR_12   ((uint32_t)0x10000000)

#define GPIO_BSRR_BR_13   ((uint32_t)0x20000000)

#define GPIO_BSRR_BR_14   ((uint32_t)0x40000000)

#define GPIO_BSRR_BR_15   ((uint32_t)0x80000000)

#define GPIO_LCKR_LCK0   ((uint32_t)0x00000001)

#define GPIO_LCKR_LCK1   ((uint32_t)0x00000002)

#define GPIO_LCKR_LCK2   ((uint32_t)0x00000004)

#define GPIO_LCKR_LCK3   ((uint32_t)0x00000008)

#define GPIO_LCKR_LCK4   ((uint32_t)0x00000010)

#define GPIO_LCKR_LCK5   ((uint32_t)0x00000020)

#define GPIO_LCKR_LCK6   ((uint32_t)0x00000040)

#define GPIO_LCKR_LCK7   ((uint32_t)0x00000080)

#define GPIO_LCKR_LCK8   ((uint32_t)0x00000100)

#define GPIO_LCKR_LCK9   ((uint32_t)0x00000200)

#define GPIO_LCKR_LCK10   ((uint32_t)0x00000400)

#define GPIO_LCKR_LCK11   ((uint32_t)0x00000800)

#define GPIO_LCKR_LCK12   ((uint32_t)0x00001000)

#define GPIO_LCKR_LCK13   ((uint32_t)0x00002000)

#define GPIO_LCKR_LCK14   ((uint32_t)0x00004000)

#define GPIO_LCKR_LCK15   ((uint32_t)0x00008000)

#define GPIO_LCKR_LCKK   ((uint32_t)0x00010000)

#define GPIO_AFRL_AFRL0   ((uint32_t)0x0000000F)

#define GPIO_AFRL_AFRL1   ((uint32_t)0x000000F0)

#define GPIO_AFRL_AFRL2   ((uint32_t)0x00000F00)

#define GPIO_AFRL_AFRL3   ((uint32_t)0x0000F000)

#define GPIO_AFRL_AFRL4   ((uint32_t)0x000F0000)

#define GPIO_AFRL_AFRL5   ((uint32_t)0x00F00000)

#define GPIO_AFRL_AFRL6   ((uint32_t)0x0F000000)

#define GPIO_AFRL_AFRL7   ((uint32_t)0xF0000000)

#define GPIO_AFRH_AFRH8   ((uint32_t)0x0000000F)

#define GPIO_AFRH_AFRH9   ((uint32_t)0x000000F0)

#define GPIO_AFRH_AFRH10   ((uint32_t)0x00000F00)

#define GPIO_AFRH_AFRH11   ((uint32_t)0x0000F000)

#define GPIO_AFRH_AFRH12   ((uint32_t)0x000F0000)

#define GPIO_AFRH_AFRH13   ((uint32_t)0x00F00000)

#define GPIO_AFRH_AFRH14   ((uint32_t)0x0F000000)

#define GPIO_AFRH_AFRH15   ((uint32_t)0xF0000000)

#define I2C_CR1_PE   ((uint16_t)0x0001)

Peripheral Enable

#define I2C_CR1_SMBUS   ((uint16_t)0x0002)

SMBus Mode

#define I2C_CR1_SMBTYPE   ((uint16_t)0x0008)

SMBus Type

#define I2C_CR1_ENARP   ((uint16_t)0x0010)

ARP Enable

#define I2C_CR1_ENPEC   ((uint16_t)0x0020)

PEC Enable

#define I2C_CR1_ENGC   ((uint16_t)0x0040)

General Call Enable

#define I2C_CR1_NOSTRETCH   ((uint16_t)0x0080)

Clock Stretching Disable (Slave mode)

#define I2C_CR1_START   ((uint16_t)0x0100)

Start Generation

#define I2C_CR1_STOP   ((uint16_t)0x0200)

Stop Generation

#define I2C_CR1_ACK   ((uint16_t)0x0400)

Acknowledge Enable

#define I2C_CR1_POS   ((uint16_t)0x0800)

Acknowledge/PEC Position (for data reception)

#define I2C_CR1_PEC   ((uint16_t)0x1000)

Packet Error Checking

#define I2C_CR1_ALERT   ((uint16_t)0x2000)

SMBus Alert

#define I2C_CR1_SWRST   ((uint16_t)0x8000)

Software Reset

#define I2C_CR2_FREQ   ((uint16_t)0x003F)

FREQ[5:0] bits (Peripheral Clock Frequency)

#define I2C_CR2_FREQ_0   ((uint16_t)0x0001)

Bit 0

#define I2C_CR2_FREQ_1   ((uint16_t)0x0002)

Bit 1

#define I2C_CR2_FREQ_2   ((uint16_t)0x0004)

Bit 2

#define I2C_CR2_FREQ_3   ((uint16_t)0x0008)

Bit 3

#define I2C_CR2_FREQ_4   ((uint16_t)0x0010)

Bit 4

#define I2C_CR2_FREQ_5   ((uint16_t)0x0020)

Bit 5

#define I2C_CR2_ITERREN   ((uint16_t)0x0100)

Error Interrupt Enable

#define I2C_CR2_ITEVTEN   ((uint16_t)0x0200)

Event Interrupt Enable

#define I2C_CR2_ITBUFEN   ((uint16_t)0x0400)

Buffer Interrupt Enable

#define I2C_CR2_DMAEN   ((uint16_t)0x0800)

DMA Requests Enable

#define I2C_CR2_LAST   ((uint16_t)0x1000)

DMA Last Transfer

#define I2C_OAR1_ADD1_7   ((uint16_t)0x00FE)

Interface Address

#define I2C_OAR1_ADD8_9   ((uint16_t)0x0300)

Interface Address

#define I2C_OAR1_ADD0   ((uint16_t)0x0001)

Bit 0

#define I2C_OAR1_ADD1   ((uint16_t)0x0002)

Bit 1

#define I2C_OAR1_ADD2   ((uint16_t)0x0004)

Bit 2

#define I2C_OAR1_ADD3   ((uint16_t)0x0008)

Bit 3

#define I2C_OAR1_ADD4   ((uint16_t)0x0010)

Bit 4

#define I2C_OAR1_ADD5   ((uint16_t)0x0020)

Bit 5

#define I2C_OAR1_ADD6   ((uint16_t)0x0040)

Bit 6

#define I2C_OAR1_ADD7   ((uint16_t)0x0080)

Bit 7

#define I2C_OAR1_ADD8   ((uint16_t)0x0100)

Bit 8

#define I2C_OAR1_ADD9   ((uint16_t)0x0200)

Bit 9

#define I2C_OAR1_ADDMODE   ((uint16_t)0x8000)

Addressing Mode (Slave mode)

#define I2C_OAR2_ENDUAL   ((uint8_t)0x01)

Dual addressing mode enable

#define I2C_OAR2_ADD2   ((uint8_t)0xFE)

Interface address

#define I2C_DR_DR   ((uint8_t)0xFF)

8-bit Data Register

#define I2C_SR1_SB   ((uint16_t)0x0001)

Start Bit (Master mode)

#define I2C_SR1_ADDR   ((uint16_t)0x0002)

Address sent (master mode)/matched (slave mode)

#define I2C_SR1_BTF   ((uint16_t)0x0004)

Byte Transfer Finished

#define I2C_SR1_ADD10   ((uint16_t)0x0008)

10-bit header sent (Master mode)

#define I2C_SR1_STOPF   ((uint16_t)0x0010)

Stop detection (Slave mode)

#define I2C_SR1_RXNE   ((uint16_t)0x0040)

Data Register not Empty (receivers)

#define I2C_SR1_TXE   ((uint16_t)0x0080)

Data Register Empty (transmitters)

#define I2C_SR1_BERR   ((uint16_t)0x0100)

Bus Error

#define I2C_SR1_ARLO   ((uint16_t)0x0200)

Arbitration Lost (master mode)

#define I2C_SR1_AF   ((uint16_t)0x0400)

Acknowledge Failure

#define I2C_SR1_OVR   ((uint16_t)0x0800)

Overrun/Underrun

#define I2C_SR1_PECERR   ((uint16_t)0x1000)

PEC Error in reception

#define I2C_SR1_TIMEOUT   ((uint16_t)0x4000)

Timeout or Tlow Error

#define I2C_SR1_SMBALERT   ((uint16_t)0x8000)

SMBus Alert

#define I2C_SR2_MSL   ((uint16_t)0x0001)

Master/Slave

#define I2C_SR2_BUSY   ((uint16_t)0x0002)

Bus Busy

#define I2C_SR2_TRA   ((uint16_t)0x0004)

Transmitter/Receiver

#define I2C_SR2_GENCALL   ((uint16_t)0x0010)

General Call Address (Slave mode)

#define I2C_SR2_SMBDEFAULT   ((uint16_t)0x0020)

SMBus Device Default Address (Slave mode)

#define I2C_SR2_SMBHOST   ((uint16_t)0x0040)

SMBus Host Header (Slave mode)

#define I2C_SR2_DUALF   ((uint16_t)0x0080)

Dual Flag (Slave mode)

#define I2C_SR2_PEC   ((uint16_t)0xFF00)

Packet Error Checking Register

#define I2C_CCR_CCR   ((uint16_t)0x0FFF)

Clock Control Register in Fast/Standard mode (Master mode)

#define I2C_CCR_DUTY   ((uint16_t)0x4000)

Fast Mode Duty Cycle

#define I2C_CCR_FS   ((uint16_t)0x8000)

I2C Master Mode Selection

#define I2C_TRISE_TRISE   ((uint8_t)0x3F)

Maximum Rise Time in Fast/Standard mode (Master mode)

#define IWDG_KR_KEY   ((uint16_t)0xFFFF)

Key value (write only, read 0000h)

#define IWDG_PR_PR   ((uint8_t)0x07)

PR[2:0] (Prescaler divider)

#define IWDG_PR_PR_0   ((uint8_t)0x01)

Bit 0

#define IWDG_PR_PR_1   ((uint8_t)0x02)

Bit 1

#define IWDG_PR_PR_2   ((uint8_t)0x04)

Bit 2

#define IWDG_RLR_RL   ((uint16_t)0x0FFF)

Watchdog counter reload value

#define IWDG_SR_PVU   ((uint8_t)0x01)

Watchdog prescaler value update

#define IWDG_SR_RVU   ((uint8_t)0x02)

Watchdog counter reload value update

#define LCD_CR_LCDEN   ((uint32_t)0x00000001)

LCD Enable Bit

#define LCD_CR_VSEL   ((uint32_t)0x00000002)

Voltage source selector Bit

#define LCD_CR_DUTY   ((uint32_t)0x0000001C)

DUTY[2:0] bits (Duty selector)

#define LCD_CR_DUTY_0   ((uint32_t)0x00000004)

Duty selector Bit 0

#define LCD_CR_DUTY_1   ((uint32_t)0x00000008)

Duty selector Bit 1

#define LCD_CR_DUTY_2   ((uint32_t)0x00000010)

Duty selector Bit 2

#define LCD_CR_BIAS   ((uint32_t)0x00000060)

BIAS[1:0] bits (Bias selector)

#define LCD_CR_BIAS_0   ((uint32_t)0x00000020)

Bias selector Bit 0

#define LCD_CR_BIAS_1   ((uint32_t)0x00000040)

Bias selector Bit 1

#define LCD_CR_MUX_SEG   ((uint32_t)0x00000080)

Mux Segment Enable Bit

#define LCD_FCR_HD   ((uint32_t)0x00000001)

High Drive Enable Bit

#define LCD_FCR_SOFIE   ((uint32_t)0x00000002)

Start of Frame Interrupt Enable Bit

#define LCD_FCR_UDDIE   ((uint32_t)0x00000008)

Update Display Done Interrupt Enable Bit

#define LCD_FCR_PON   ((uint32_t)0x00000070)

PON[2:0] bits (Puls ON Duration)

#define LCD_FCR_PON_0   ((uint32_t)0x00000010)

Bit 0

#define LCD_FCR_PON_1   ((uint32_t)0x00000020)

Bit 1

#define LCD_FCR_PON_2   ((uint32_t)0x00000040)

Bit 2

#define LCD_FCR_DEAD   ((uint32_t)0x00000380)

DEAD[2:0] bits (DEAD Time)

#define LCD_FCR_DEAD_0   ((uint32_t)0x00000080)

Bit 0

#define LCD_FCR_DEAD_1   ((uint32_t)0x00000100)

Bit 1

#define LCD_FCR_DEAD_2   ((uint32_t)0x00000200)

Bit 2

#define LCD_FCR_CC   ((uint32_t)0x00001C00)

CC[2:0] bits (Contrast Control)

#define LCD_FCR_CC_0   ((uint32_t)0x00000400)

Bit 0

#define LCD_FCR_CC_1   ((uint32_t)0x00000800)

Bit 1

#define LCD_FCR_CC_2   ((uint32_t)0x00001000)

Bit 2

#define LCD_FCR_BLINKF   ((uint32_t)0x0000E000)

BLINKF[2:0] bits (Blink Frequency)

#define LCD_FCR_BLINKF_0   ((uint32_t)0x00002000)

Bit 0

#define LCD_FCR_BLINKF_1   ((uint32_t)0x00004000)

Bit 1

#define LCD_FCR_BLINKF_2   ((uint32_t)0x00008000)

Bit 2

#define LCD_FCR_BLINK   ((uint32_t)0x00030000)

BLINK[1:0] bits (Blink Enable)

#define LCD_FCR_BLINK_0   ((uint32_t)0x00010000)

Bit 0

#define LCD_FCR_BLINK_1   ((uint32_t)0x00020000)

Bit 1

#define LCD_FCR_DIV   ((uint32_t)0x003C0000)

DIV[3:0] bits (Divider)

#define LCD_FCR_PS   ((uint32_t)0x03C00000)

PS[3:0] bits (Prescaler)

#define LCD_SR_ENS   ((uint32_t)0x00000001)

LCD Enabled Bit

#define LCD_SR_SOF   ((uint32_t)0x00000002)

Start Of Frame Flag Bit

#define LCD_SR_UDR   ((uint32_t)0x00000004)

Update Display Request Bit

#define LCD_SR_UDD   ((uint32_t)0x00000008)

Update Display Done Flag Bit

#define LCD_SR_RDY   ((uint32_t)0x00000010)

Ready Flag Bit

#define LCD_SR_FCRSR   ((uint32_t)0x00000020)

LCD FCR Register Synchronization Flag Bit

#define LCD_CLR_SOFC   ((uint32_t)0x00000002)

Start Of Frame Flag Clear Bit

#define LCD_CLR_UDDC   ((uint32_t)0x00000008)

Update Display Done Flag Clear Bit

#define LCD_RAM_SEGMENT_DATA   ((uint32_t)0xFFFFFFFF)

Segment Data Bits

#define PWR_CR_LPSDSR   ((uint16_t)0x0001)

Low-power deepsleep/sleep/low power run

#define PWR_CR_PDDS   ((uint16_t)0x0002)

Power Down Deepsleep

#define PWR_CR_CWUF   ((uint16_t)0x0004)

Clear Wakeup Flag

#define PWR_CR_CSBF   ((uint16_t)0x0008)

Clear Standby Flag

#define PWR_CR_PVDE   ((uint16_t)0x0010)

Power Voltage Detector Enable

#define PWR_CR_PLS   ((uint16_t)0x00E0)

PLS[2:0] bits (PVD Level Selection)

#define PWR_CR_PLS_0   ((uint16_t)0x0020)

Bit 0

#define PWR_CR_PLS_1   ((uint16_t)0x0040)

Bit 1

#define PWR_CR_PLS_2   ((uint16_t)0x0080)

Bit 2 PVD level configuration

#define PWR_CR_PLS_LEV0   ((uint16_t)0x0000)

PVD level 0

#define PWR_CR_PLS_LEV1   ((uint16_t)0x0020)

PVD level 1

#define PWR_CR_PLS_LEV2   ((uint16_t)0x0040)

PVD level 2

#define PWR_CR_PLS_LEV3   ((uint16_t)0x0060)

PVD level 3

#define PWR_CR_PLS_LEV4   ((uint16_t)0x0080)

PVD level 4

#define PWR_CR_PLS_LEV5   ((uint16_t)0x00A0)

PVD level 5

#define PWR_CR_PLS_LEV6   ((uint16_t)0x00C0)

PVD level 6

#define PWR_CR_PLS_LEV7   ((uint16_t)0x00E0)

PVD level 7

#define PWR_CR_DBP   ((uint16_t)0x0100)

Disable Backup Domain write protection

#define PWR_CR_ULP   ((uint16_t)0x0200)

Ultra Low Power mode

#define PWR_CR_FWU   ((uint16_t)0x0400)

Fast wakeup

#define PWR_CR_VOS   ((uint16_t)0x1800)

VOS[1:0] bits (Voltage scaling range selection)

#define PWR_CR_VOS_0   ((uint16_t)0x0800)

Bit 0

#define PWR_CR_VOS_1   ((uint16_t)0x1000)

Bit 1

#define PWR_CR_LPRUN   ((uint16_t)0x4000)

Low power run mode

#define PWR_CSR_WUF   ((uint16_t)0x0001)

Wakeup Flag

#define PWR_CSR_SBF   ((uint16_t)0x0002)

Standby Flag

#define PWR_CSR_PVDO   ((uint16_t)0x0004)

PVD Output

#define PWR_CSR_VREFINTRDYF   ((uint16_t)0x0008)

Internal voltage reference (VREFINT) ready flag

#define PWR_CSR_VOSF   ((uint16_t)0x0010)

Voltage Scaling select flag

#define PWR_CSR_REGLPF   ((uint16_t)0x0020)

Regulator LP flag

#define PWR_CSR_EWUP1   ((uint16_t)0x0100)

Enable WKUP pin 1

#define PWR_CSR_EWUP2   ((uint16_t)0x0200)

Enable WKUP pin 2

#define PWR_CSR_EWUP3   ((uint16_t)0x0400)

Enable WKUP pin 3

#define RCC_CR_HSION   ((uint32_t)0x00000001)

Internal High Speed clock enable

#define RCC_CR_HSIRDY   ((uint32_t)0x00000002)

Internal High Speed clock ready flag

#define RCC_CR_MSION   ((uint32_t)0x00000100)

Internal Multi Speed clock enable

#define RCC_CR_MSIRDY   ((uint32_t)0x00000200)

Internal Multi Speed clock ready flag

#define RCC_CR_HSEON   ((uint32_t)0x00010000)

External High Speed clock enable

#define RCC_CR_HSERDY   ((uint32_t)0x00020000)

External High Speed clock ready flag

#define RCC_CR_HSEBYP   ((uint32_t)0x00040000)

External High Speed clock Bypass

#define RCC_CR_PLLON   ((uint32_t)0x01000000)

PLL enable

#define RCC_CR_PLLRDY   ((uint32_t)0x02000000)

PLL clock ready flag

#define RCC_CR_CSSON   ((uint32_t)0x10000000)

Clock Security System enable

#define RCC_CR_RTCPRE   ((uint32_t)0x60000000)

RTC/LCD Prescaler

#define RCC_CR_RTCPRE_0   ((uint32_t)0x20000000)

Bit0

#define RCC_CR_RTCPRE_1   ((uint32_t)0x40000000)

Bit1

#define RCC_ICSCR_HSICAL   ((uint32_t)0x000000FF)

Internal High Speed clock Calibration

#define RCC_ICSCR_HSITRIM   ((uint32_t)0x00001F00)

Internal High Speed clock trimming

#define RCC_ICSCR_MSIRANGE   ((uint32_t)0x0000E000)

Internal Multi Speed clock Range

Referenced by RCC_MSIRangeConfig(), and SystemCoreClockUpdate().

#define RCC_ICSCR_MSIRANGE_0   ((uint32_t)0x00000000)

Internal Multi Speed clock Range 65.536 KHz

#define RCC_ICSCR_MSIRANGE_1   ((uint32_t)0x00002000)

Internal Multi Speed clock Range 131.072 KHz

Referenced by SystemCoreClockUpdate().

#define RCC_ICSCR_MSIRANGE_2   ((uint32_t)0x00004000)

Internal Multi Speed clock Range 262.144 KHz

#define RCC_ICSCR_MSIRANGE_3   ((uint32_t)0x00006000)

Internal Multi Speed clock Range 524.288 KHz

#define RCC_ICSCR_MSIRANGE_4   ((uint32_t)0x00008000)

Internal Multi Speed clock Range 1.048 MHz

#define RCC_ICSCR_MSIRANGE_5   ((uint32_t)0x0000A000)

Internal Multi Speed clock Range 2.097 MHz

#define RCC_ICSCR_MSIRANGE_6   ((uint32_t)0x0000C000)

Internal Multi Speed clock Range 4.194 MHz

#define RCC_ICSCR_MSICAL   ((uint32_t)0x00FF0000)

Internal Multi Speed clock Calibration

#define RCC_ICSCR_MSITRIM   ((uint32_t)0xFF000000)

Internal Multi Speed clock trimming

#define RCC_CFGR_SW   ((uint32_t)0x00000003)

SW[1:0] bits (System clock Switch)

#define RCC_CFGR_SW_0   ((uint32_t)0x00000001)

Bit 0

#define RCC_CFGR_SW_1   ((uint32_t)0x00000002)

Bit 1 SW configuration

#define RCC_CFGR_SW_MSI   ((uint32_t)0x00000000)

MSI selected as system clock

#define RCC_CFGR_SW_HSI   ((uint32_t)0x00000001)

HSI selected as system clock

#define RCC_CFGR_SW_HSE   ((uint32_t)0x00000002)

HSE selected as system clock

#define RCC_CFGR_SW_PLL   ((uint32_t)0x00000003)

PLL selected as system clock

#define RCC_CFGR_SWS   ((uint32_t)0x0000000C)

SWS[1:0] bits (System Clock Switch Status)

#define RCC_CFGR_SWS_0   ((uint32_t)0x00000004)

Bit 0

#define RCC_CFGR_SWS_1   ((uint32_t)0x00000008)

Bit 1 SWS configuration

#define RCC_CFGR_SWS_MSI   ((uint32_t)0x00000000)

MSI oscillator used as system clock

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_SWS_HSI   ((uint32_t)0x00000004)

HSI oscillator used as system clock

#define RCC_CFGR_SWS_HSE   ((uint32_t)0x00000008)

HSE oscillator used as system clock

#define RCC_CFGR_SWS_PLL   ((uint32_t)0x0000000C)

PLL used as system clock

#define RCC_CFGR_HPRE   ((uint32_t)0x000000F0)

HPRE[3:0] bits (AHB prescaler)

#define RCC_CFGR_HPRE_0   ((uint32_t)0x00000010)

Bit 0

#define RCC_CFGR_HPRE_1   ((uint32_t)0x00000020)

Bit 1

#define RCC_CFGR_HPRE_2   ((uint32_t)0x00000040)

Bit 2

#define RCC_CFGR_HPRE_3   ((uint32_t)0x00000080)

Bit 3 HPRE configuration

#define RCC_CFGR_HPRE_DIV1   ((uint32_t)0x00000000)

SYSCLK not divided

#define RCC_CFGR_HPRE_DIV2   ((uint32_t)0x00000080)

SYSCLK divided by 2

#define RCC_CFGR_HPRE_DIV4   ((uint32_t)0x00000090)

SYSCLK divided by 4

#define RCC_CFGR_HPRE_DIV8   ((uint32_t)0x000000A0)

SYSCLK divided by 8

#define RCC_CFGR_HPRE_DIV16   ((uint32_t)0x000000B0)

SYSCLK divided by 16

#define RCC_CFGR_HPRE_DIV64   ((uint32_t)0x000000C0)

SYSCLK divided by 64

#define RCC_CFGR_HPRE_DIV128   ((uint32_t)0x000000D0)

SYSCLK divided by 128

#define RCC_CFGR_HPRE_DIV256   ((uint32_t)0x000000E0)

SYSCLK divided by 256

#define RCC_CFGR_HPRE_DIV512   ((uint32_t)0x000000F0)

SYSCLK divided by 512

#define RCC_CFGR_PPRE1   ((uint32_t)0x00000700)

PRE1[2:0] bits (APB1 prescaler)

#define RCC_CFGR_PPRE1_0   ((uint32_t)0x00000100)

Bit 0

#define RCC_CFGR_PPRE1_1   ((uint32_t)0x00000200)

Bit 1

#define RCC_CFGR_PPRE1_2   ((uint32_t)0x00000400)

Bit 2 PPRE1 configuration

#define RCC_CFGR_PPRE1_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE1_DIV2   ((uint32_t)0x00000400)

HCLK divided by 2

#define RCC_CFGR_PPRE1_DIV4   ((uint32_t)0x00000500)

HCLK divided by 4

#define RCC_CFGR_PPRE1_DIV8   ((uint32_t)0x00000600)

HCLK divided by 8

#define RCC_CFGR_PPRE1_DIV16   ((uint32_t)0x00000700)

HCLK divided by 16

#define RCC_CFGR_PPRE2   ((uint32_t)0x00003800)

PRE2[2:0] bits (APB2 prescaler)

#define RCC_CFGR_PPRE2_0   ((uint32_t)0x00000800)

Bit 0

#define RCC_CFGR_PPRE2_1   ((uint32_t)0x00001000)

Bit 1

#define RCC_CFGR_PPRE2_2   ((uint32_t)0x00002000)

Bit 2 PPRE2 configuration

#define RCC_CFGR_PPRE2_DIV1   ((uint32_t)0x00000000)

HCLK not divided

#define RCC_CFGR_PPRE2_DIV2   ((uint32_t)0x00002000)

HCLK divided by 2

#define RCC_CFGR_PPRE2_DIV4   ((uint32_t)0x00002800)

HCLK divided by 4

#define RCC_CFGR_PPRE2_DIV8   ((uint32_t)0x00003000)

HCLK divided by 8

#define RCC_CFGR_PPRE2_DIV16   ((uint32_t)0x00003800)

HCLK divided by 16 PLL entry clock source

#define RCC_CFGR_PLLSRC   ((uint32_t)0x00010000)

PLL entry clock source

#define RCC_CFGR_PLLSRC_HSI   ((uint32_t)0x00000000)

HSI as PLL entry clock source

#define RCC_CFGR_PLLSRC_HSE   ((uint32_t)0x00010000)

HSE as PLL entry clock source

#define RCC_CFGR_PLLMUL   ((uint32_t)0x003C0000)

PLLMUL[3:0] bits (PLL multiplication factor)

#define RCC_CFGR_PLLMUL_0   ((uint32_t)0x00040000)

Bit 0

#define RCC_CFGR_PLLMUL_1   ((uint32_t)0x00080000)

Bit 1

#define RCC_CFGR_PLLMUL_2   ((uint32_t)0x00100000)

Bit 2

#define RCC_CFGR_PLLMUL_3   ((uint32_t)0x00200000)

Bit 3 PLLMUL configuration

#define RCC_CFGR_PLLMUL3   ((uint32_t)0x00000000)

PLL input clock * 3

#define RCC_CFGR_PLLMUL4   ((uint32_t)0x00040000)

PLL input clock * 4

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL6   ((uint32_t)0x00080000)

PLL input clock * 6

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL8   ((uint32_t)0x000C0000)

PLL input clock * 8

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL12   ((uint32_t)0x00100000)

PLL input clock * 12

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL16   ((uint32_t)0x00140000)

PLL input clock * 16

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL24   ((uint32_t)0x00180000)

PLL input clock * 24

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL32   ((uint32_t)0x001C0000)

PLL input clock * 32

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLMUL48   ((uint32_t)0x00200000)

PLL input clock * 48 PLLDIV configuration

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLDIV   ((uint32_t)0x00C00000)

PLLDIV[1:0] bits (PLL Output Division)

#define RCC_CFGR_PLLDIV_0   ((uint32_t)0x00400000)

Bit0

#define RCC_CFGR_PLLDIV_1   ((uint32_t)0x00800000)

Bit1 PLLDIV configuration

#define RCC_CFGR_PLLDIV1   ((uint32_t)0x00000000)

PLL clock output = CKVCO / 1

#define RCC_CFGR_PLLDIV2   ((uint32_t)0x00400000)

PLL clock output = CKVCO / 2

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLDIV3   ((uint32_t)0x00800000)

PLL clock output = CKVCO / 3

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_PLLDIV4   ((uint32_t)0x00C00000)

PLL clock output = CKVCO / 4

Referenced by SystemCoreClockUpdate().

#define RCC_CFGR_MCOSEL   ((uint32_t)0x07000000)

MCO[2:0] bits (Microcontroller Clock Output)

#define RCC_CFGR_MCOSEL_0   ((uint32_t)0x01000000)

Bit 0

#define RCC_CFGR_MCOSEL_1   ((uint32_t)0x02000000)

Bit 1

#define RCC_CFGR_MCOSEL_2   ((uint32_t)0x04000000)

Bit 2 MCO configuration

#define RCC_CFGR_MCO_NOCLOCK   ((uint32_t)0x00000000)

No clock

#define RCC_CFGR_MCO_SYSCLK   ((uint32_t)0x01000000)

System clock selected

#define RCC_CFGR_MCO_HSI   ((uint32_t)0x02000000)

Internal 16 MHz RC oscillator clock selected

#define RCC_CFGR_MCO_MSI   ((uint32_t)0x03000000)

Internal Medium Speed RC oscillator clock selected

#define RCC_CFGR_MCO_HSE   ((uint32_t)0x04000000)

External 1-25 MHz oscillator clock selected

#define RCC_CFGR_MCO_PLL   ((uint32_t)0x05000000)

PLL clock divided

#define RCC_CFGR_MCO_LSI   ((uint32_t)0x06000000)

LSI selected

#define RCC_CFGR_MCO_LSE   ((uint32_t)0x07000000)

LSE selected

#define RCC_CFGR_MCOPRE   ((uint32_t)0x70000000)

MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler)

#define RCC_CFGR_MCOPRE_0   ((uint32_t)0x10000000)

Bit 0

#define RCC_CFGR_MCOPRE_1   ((uint32_t)0x20000000)

Bit 1

#define RCC_CFGR_MCOPRE_2   ((uint32_t)0x40000000)

Bit 2 MCO Prescaler configuration

#define RCC_CFGR_MCO_DIV1   ((uint32_t)0x00000000)

MCO Clock divided by 1

#define RCC_CFGR_MCO_DIV2   ((uint32_t)0x10000000)

MCO Clock divided by 2

#define RCC_CFGR_MCO_DIV4   ((uint32_t)0x20000000)

MCO Clock divided by 4

#define RCC_CFGR_MCO_DIV8   ((uint32_t)0x30000000)

MCO Clock divided by 8

#define RCC_CFGR_MCO_DIV16   ((uint32_t)0x40000000)

MCO Clock divided by 16 ****************** Bit definition for RCC_CIR register

#define RCC_CIR_LSIRDYF   ((uint32_t)0x00000001)

LSI Ready Interrupt flag

#define RCC_CIR_LSERDYF   ((uint32_t)0x00000002)

LSE Ready Interrupt flag

#define RCC_CIR_HSIRDYF   ((uint32_t)0x00000004)

HSI Ready Interrupt flag

#define RCC_CIR_HSERDYF   ((uint32_t)0x00000008)

HSE Ready Interrupt flag

#define RCC_CIR_PLLRDYF   ((uint32_t)0x00000010)

PLL Ready Interrupt flag

#define RCC_CIR_MSIRDYF   ((uint32_t)0x00000020)

MSI Ready Interrupt flag

#define RCC_CIR_LSECSS   ((uint32_t)0x00000040)

LSE CSS Interrupt flag

#define RCC_CIR_CSSF   ((uint32_t)0x00000080)

Clock Security System Interrupt flag

#define RCC_CIR_LSIRDYIE   ((uint32_t)0x00000100)

LSI Ready Interrupt Enable

#define RCC_CIR_LSERDYIE   ((uint32_t)0x00000200)

LSE Ready Interrupt Enable

#define RCC_CIR_HSIRDYIE   ((uint32_t)0x00000400)

HSI Ready Interrupt Enable

#define RCC_CIR_HSERDYIE   ((uint32_t)0x00000800)

HSE Ready Interrupt Enable

#define RCC_CIR_PLLRDYIE   ((uint32_t)0x00001000)

PLL Ready Interrupt Enable

#define RCC_CIR_MSIRDYIE   ((uint32_t)0x00002000)

MSI Ready Interrupt Enable

#define RCC_CIR_LSECSSIE   ((uint32_t)0x00004000)

LSE CSS Interrupt Enable

#define RCC_CIR_LSIRDYC   ((uint32_t)0x00010000)

LSI Ready Interrupt Clear

#define RCC_CIR_LSERDYC   ((uint32_t)0x00020000)

LSE Ready Interrupt Clear

#define RCC_CIR_HSIRDYC   ((uint32_t)0x00040000)

HSI Ready Interrupt Clear

#define RCC_CIR_HSERDYC   ((uint32_t)0x00080000)

HSE Ready Interrupt Clear

#define RCC_CIR_PLLRDYC   ((uint32_t)0x00100000)

PLL Ready Interrupt Clear

#define RCC_CIR_MSIRDYC   ((uint32_t)0x00200000)

MSI Ready Interrupt Clear

#define RCC_CIR_LSECSSC   ((uint32_t)0x00400000)

LSE CSS Interrupt Clear

#define RCC_CIR_CSSC   ((uint32_t)0x00800000)

Clock Security System Interrupt Clear

#define RCC_AHBRSTR_GPIOARST   ((uint32_t)0x00000001)

GPIO port A reset

#define RCC_AHBRSTR_GPIOBRST   ((uint32_t)0x00000002)

GPIO port B reset

#define RCC_AHBRSTR_GPIOCRST   ((uint32_t)0x00000004)

GPIO port C reset

#define RCC_AHBRSTR_GPIODRST   ((uint32_t)0x00000008)

GPIO port D reset

#define RCC_AHBRSTR_GPIOERST   ((uint32_t)0x00000010)

GPIO port E reset

#define RCC_AHBRSTR_GPIOHRST   ((uint32_t)0x00000020)

GPIO port H reset

#define RCC_AHBRSTR_GPIOFRST   ((uint32_t)0x00000040)

GPIO port F reset

#define RCC_AHBRSTR_GPIOGRST   ((uint32_t)0x00000080)

GPIO port G reset

#define RCC_AHBRSTR_CRCRST   ((uint32_t)0x00001000)

CRC reset

#define RCC_AHBRSTR_FLITFRST   ((uint32_t)0x00008000)

FLITF reset

#define RCC_AHBRSTR_DMA1RST   ((uint32_t)0x01000000)

DMA1 reset

#define RCC_AHBRSTR_DMA2RST   ((uint32_t)0x02000000)

DMA2 reset

#define RCC_AHBRSTR_AESRST   ((uint32_t)0x08000000)

AES reset

#define RCC_AHBRSTR_FSMCRST   ((uint32_t)0x40000000)

FSMC reset

#define RCC_APB2RSTR_SYSCFGRST   ((uint32_t)0x00000001)

System Configuration SYSCFG reset

#define RCC_APB2RSTR_TIM9RST   ((uint32_t)0x00000004)

TIM9 reset

#define RCC_APB2RSTR_TIM10RST   ((uint32_t)0x00000008)

TIM10 reset

#define RCC_APB2RSTR_TIM11RST   ((uint32_t)0x00000010)

TIM11 reset

#define RCC_APB2RSTR_ADC1RST   ((uint32_t)0x00000200)

ADC1 reset

#define RCC_APB2RSTR_SDIORST   ((uint32_t)0x00000800)

SDIO reset

#define RCC_APB2RSTR_SPI1RST   ((uint32_t)0x00001000)

SPI1 reset

#define RCC_APB2RSTR_USART1RST   ((uint32_t)0x00004000)

USART1 reset

#define RCC_APB1RSTR_TIM2RST   ((uint32_t)0x00000001)

Timer 2 reset

#define RCC_APB1RSTR_TIM3RST   ((uint32_t)0x00000002)

Timer 3 reset

#define RCC_APB1RSTR_TIM4RST   ((uint32_t)0x00000004)

Timer 4 reset

#define RCC_APB1RSTR_TIM5RST   ((uint32_t)0x00000008)

Timer 5 reset

#define RCC_APB1RSTR_TIM6RST   ((uint32_t)0x00000010)

Timer 6 reset

#define RCC_APB1RSTR_TIM7RST   ((uint32_t)0x00000020)

Timer 7 reset

#define RCC_APB1RSTR_LCDRST   ((uint32_t)0x00000200)

LCD reset

#define RCC_APB1RSTR_WWDGRST   ((uint32_t)0x00000800)

Window Watchdog reset

#define RCC_APB1RSTR_SPI2RST   ((uint32_t)0x00004000)

SPI 2 reset

#define RCC_APB1RSTR_SPI3RST   ((uint32_t)0x00008000)

SPI 3 reset

#define RCC_APB1RSTR_USART2RST   ((uint32_t)0x00020000)

USART 2 reset

#define RCC_APB1RSTR_USART3RST   ((uint32_t)0x00040000)

USART 3 reset

#define RCC_APB1RSTR_UART4RST   ((uint32_t)0x00080000)

UART 4 reset

#define RCC_APB1RSTR_UART5RST   ((uint32_t)0x00100000)

UART 5 reset

#define RCC_APB1RSTR_I2C1RST   ((uint32_t)0x00200000)

I2C 1 reset

#define RCC_APB1RSTR_I2C2RST   ((uint32_t)0x00400000)

I2C 2 reset

#define RCC_APB1RSTR_USBRST   ((uint32_t)0x00800000)

USB reset

#define RCC_APB1RSTR_PWRRST   ((uint32_t)0x10000000)

Power interface reset

#define RCC_APB1RSTR_DACRST   ((uint32_t)0x20000000)

DAC interface reset

#define RCC_APB1RSTR_COMPRST   ((uint32_t)0x80000000)

Comparator interface reset

#define RCC_AHBENR_GPIOAEN   ((uint32_t)0x00000001)

GPIO port A clock enable

#define RCC_AHBENR_GPIOBEN   ((uint32_t)0x00000002)

GPIO port B clock enable

#define RCC_AHBENR_GPIOCEN   ((uint32_t)0x00000004)

GPIO port C clock enable

#define RCC_AHBENR_GPIODEN   ((uint32_t)0x00000008)

GPIO port D clock enable

#define RCC_AHBENR_GPIOEEN   ((uint32_t)0x00000010)

GPIO port E clock enable

#define RCC_AHBENR_GPIOHEN   ((uint32_t)0x00000020)

GPIO port H clock enable

#define RCC_AHBENR_GPIOFEN   ((uint32_t)0x00000040)

GPIO port F clock enable

#define RCC_AHBENR_GPIOGEN   ((uint32_t)0x00000080)

GPIO port G clock enable

#define RCC_AHBENR_CRCEN   ((uint32_t)0x00001000)

CRC clock enable

#define RCC_AHBENR_FLITFEN   ((uint32_t)0x00008000)

FLITF clock enable (has effect only when the Flash memory is in power down mode)

#define RCC_AHBENR_DMA1EN   ((uint32_t)0x01000000)

DMA1 clock enable

#define RCC_AHBENR_DMA2EN   ((uint32_t)0x02000000)

DMA2 clock enable

Referenced by DMA_Init().

#define RCC_AHBENR_AESEN   ((uint32_t)0x08000000)

AES clock enable

#define RCC_AHBENR_FSMCEN   ((uint32_t)0x40000000)

FSMC clock enable

#define RCC_APB2ENR_SYSCFGEN   ((uint32_t)0x00000001)

System Configuration SYSCFG clock enable

#define RCC_APB2ENR_TIM9EN   ((uint32_t)0x00000004)

TIM9 interface clock enable

#define RCC_APB2ENR_TIM10EN   ((uint32_t)0x00000008)

TIM10 interface clock enable

#define RCC_APB2ENR_TIM11EN   ((uint32_t)0x00000010)

TIM11 Timer clock enable

#define RCC_APB2ENR_ADC1EN   ((uint32_t)0x00000200)

ADC1 clock enable

#define RCC_APB2ENR_SDIOEN   ((uint32_t)0x00000800)

SDIO clock enable

#define RCC_APB2ENR_SPI1EN   ((uint32_t)0x00001000)

SPI1 clock enable

#define RCC_APB2ENR_USART1EN   ((uint32_t)0x00004000)

USART1 clock enable

#define RCC_APB1ENR_TIM2EN   ((uint32_t)0x00000001)

Timer 2 clock enabled

#define RCC_APB1ENR_TIM3EN   ((uint32_t)0x00000002)

Timer 3 clock enable

#define RCC_APB1ENR_TIM4EN   ((uint32_t)0x00000004)

Timer 4 clock enable

#define RCC_APB1ENR_TIM5EN   ((uint32_t)0x00000008)

Timer 5 clock enable

#define RCC_APB1ENR_TIM6EN   ((uint32_t)0x00000010)

Timer 6 clock enable

#define RCC_APB1ENR_TIM7EN   ((uint32_t)0x00000020)

Timer 7 clock enable

#define RCC_APB1ENR_LCDEN   ((uint32_t)0x00000200)

LCD clock enable

#define RCC_APB1ENR_WWDGEN   ((uint32_t)0x00000800)

Window Watchdog clock enable

#define RCC_APB1ENR_SPI2EN   ((uint32_t)0x00004000)

SPI 2 clock enable

#define RCC_APB1ENR_SPI3EN   ((uint32_t)0x00008000)

SPI 3 clock enable

#define RCC_APB1ENR_USART2EN   ((uint32_t)0x00020000)

USART 2 clock enable

#define RCC_APB1ENR_USART3EN   ((uint32_t)0x00040000)

USART 3 clock enable

#define RCC_APB1ENR_UART4EN   ((uint32_t)0x00080000)

UART 4 clock enable

#define RCC_APB1ENR_UART5EN   ((uint32_t)0x00100000)

UART 5 clock enable

#define RCC_APB1ENR_I2C1EN   ((uint32_t)0x00200000)

I2C 1 clock enable

#define RCC_APB1ENR_I2C2EN   ((uint32_t)0x00400000)

I2C 2 clock enable

#define RCC_APB1ENR_USBEN   ((uint32_t)0x00800000)

USB clock enable

#define RCC_APB1ENR_PWREN   ((uint32_t)0x10000000)

Power interface clock enable

#define RCC_APB1ENR_DACEN   ((uint32_t)0x20000000)

DAC interface clock enable

#define RCC_APB1ENR_COMPEN   ((uint32_t)0x80000000)

Comparator interface clock enable

#define RCC_AHBLPENR_GPIOALPEN   ((uint32_t)0x00000001)

GPIO port A clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOBLPEN   ((uint32_t)0x00000002)

GPIO port B clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOCLPEN   ((uint32_t)0x00000004)

GPIO port C clock enabled in sleep mode

#define RCC_AHBLPENR_GPIODLPEN   ((uint32_t)0x00000008)

GPIO port D clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOELPEN   ((uint32_t)0x00000010)

GPIO port E clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOHLPEN   ((uint32_t)0x00000020)

GPIO port H clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOFLPEN   ((uint32_t)0x00000040)

GPIO port F clock enabled in sleep mode

#define RCC_AHBLPENR_GPIOGLPEN   ((uint32_t)0x00000080)

GPIO port G clock enabled in sleep mode

#define RCC_AHBLPENR_CRCLPEN   ((uint32_t)0x00001000)

CRC clock enabled in sleep mode

#define RCC_AHBLPENR_FLITFLPEN   ((uint32_t)0x00008000)

Flash Interface clock enabled in sleep mode (has effect only when the Flash memory is in power down mode)

#define RCC_AHBLPENR_SRAMLPEN   ((uint32_t)0x00010000)

SRAM clock enabled in sleep mode

#define RCC_AHBLPENR_DMA1LPEN   ((uint32_t)0x01000000)

DMA1 clock enabled in sleep mode

#define RCC_AHBLPENR_DMA2LPEN   ((uint32_t)0x02000000)

DMA2 clock enabled in sleep mode

#define RCC_AHBLPENR_AESLPEN   ((uint32_t)0x08000000)

AES clock enabled in sleep mode

#define RCC_AHBLPENR_FSMCLPEN   ((uint32_t)0x40000000)

FSMC clock enabled in sleep mode

#define RCC_APB2LPENR_SYSCFGLPEN   ((uint32_t)0x00000001)

System Configuration SYSCFG clock enabled in sleep mode

#define RCC_APB2LPENR_TIM9LPEN   ((uint32_t)0x00000004)

TIM9 interface clock enabled in sleep mode

#define RCC_APB2LPENR_TIM10LPEN   ((uint32_t)0x00000008)

TIM10 interface clock enabled in sleep mode

#define RCC_APB2LPENR_TIM11LPEN   ((uint32_t)0x00000010)

TIM11 Timer clock enabled in sleep mode

#define RCC_APB2LPENR_ADC1LPEN   ((uint32_t)0x00000200)

ADC1 clock enabled in sleep mode

#define RCC_APB2LPENR_SDIOLPEN   ((uint32_t)0x00000800)

SDIO clock enabled in sleep mode

#define RCC_APB2LPENR_SPI1LPEN   ((uint32_t)0x00001000)

SPI1 clock enabled in sleep mode

#define RCC_APB2LPENR_USART1LPEN   ((uint32_t)0x00004000)

USART1 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM2LPEN   ((uint32_t)0x00000001)

Timer 2 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM3LPEN   ((uint32_t)0x00000002)

Timer 3 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM4LPEN   ((uint32_t)0x00000004)

Timer 4 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM5LPEN   ((uint32_t)0x00000008)

Timer 5 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM6LPEN   ((uint32_t)0x00000010)

Timer 6 clock enabled in sleep mode

#define RCC_APB1LPENR_TIM7LPEN   ((uint32_t)0x00000020)

Timer 7 clock enabled in sleep mode

#define RCC_APB1LPENR_LCDLPEN   ((uint32_t)0x00000200)

LCD clock enabled in sleep mode

#define RCC_APB1LPENR_WWDGLPEN   ((uint32_t)0x00000800)

Window Watchdog clock enabled in sleep mode

#define RCC_APB1LPENR_SPI2LPEN   ((uint32_t)0x00004000)

SPI 2 clock enabled in sleep mode

#define RCC_APB1LPENR_SPI3LPEN   ((uint32_t)0x00008000)

SPI 3 clock enabled in sleep mode

#define RCC_APB1LPENR_USART2LPEN   ((uint32_t)0x00020000)

USART 2 clock enabled in sleep mode

#define RCC_APB1LPENR_USART3LPEN   ((uint32_t)0x00040000)

USART 3 clock enabled in sleep mode

#define RCC_APB1LPENR_UART4LPEN   ((uint32_t)0x00080000)

UART 4 clock enabled in sleep mode

#define RCC_APB1LPENR_UART5LPEN   ((uint32_t)0x00100000)

UART 5 clock enabled in sleep mode

#define RCC_APB1LPENR_I2C1LPEN   ((uint32_t)0x00200000)

I2C 1 clock enabled in sleep mode

#define RCC_APB1LPENR_I2C2LPEN   ((uint32_t)0x00400000)

I2C 2 clock enabled in sleep mode

#define RCC_APB1LPENR_USBLPEN   ((uint32_t)0x00800000)

USB clock enabled in sleep mode

#define RCC_APB1LPENR_PWRLPEN   ((uint32_t)0x10000000)

Power interface clock enabled in sleep mode

#define RCC_APB1LPENR_DACLPEN   ((uint32_t)0x20000000)

DAC interface clock enabled in sleep mode

#define RCC_APB1LPENR_COMPLPEN   ((uint32_t)0x80000000)

Comparator interface clock enabled in sleep mode

#define RCC_CSR_LSION   ((uint32_t)0x00000001)

Internal Low Speed oscillator enable

#define RCC_CSR_LSIRDY   ((uint32_t)0x00000002)

Internal Low Speed oscillator Ready

#define RCC_CSR_LSEON   ((uint32_t)0x00000100)

External Low Speed oscillator enable

#define RCC_CSR_LSERDY   ((uint32_t)0x00000200)

External Low Speed oscillator Ready

#define RCC_CSR_LSEBYP   ((uint32_t)0x00000400)

External Low Speed oscillator Bypass

#define RCC_CSR_LSECSSON   ((uint32_t)0x00000800)

External Low Speed oscillator CSS Enable

#define RCC_CSR_LSECSSD   ((uint32_t)0x00001000)

External Low Speed oscillator CSS Detected

#define RCC_CSR_RTCSEL   ((uint32_t)0x00030000)

RTCSEL[1:0] bits (RTC clock source selection)

#define RCC_CSR_RTCSEL_0   ((uint32_t)0x00010000)

Bit 0

#define RCC_CSR_RTCSEL_1   ((uint32_t)0x00020000)

Bit 1 RTC congiguration

#define RCC_CSR_RTCSEL_NOCLOCK   ((uint32_t)0x00000000)

No clock

#define RCC_CSR_RTCSEL_LSE   ((uint32_t)0x00010000)

LSE oscillator clock used as RTC clock

#define RCC_CSR_RTCSEL_LSI   ((uint32_t)0x00020000)

LSI oscillator clock used as RTC clock

#define RCC_CSR_RTCSEL_HSE   ((uint32_t)0x00030000)

HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock

#define RCC_CSR_RTCEN   ((uint32_t)0x00400000)

RTC clock enable

#define RCC_CSR_RTCRST   ((uint32_t)0x00800000)

RTC reset

#define RCC_CSR_RMVF   ((uint32_t)0x01000000)

Remove reset flag

#define RCC_CSR_OBLRSTF   ((uint32_t)0x02000000)

Option Bytes Loader reset flag

#define RCC_CSR_PINRSTF   ((uint32_t)0x04000000)

PIN reset flag

#define RCC_CSR_PORRSTF   ((uint32_t)0x08000000)

POR/PDR reset flag

#define RCC_CSR_SFTRSTF   ((uint32_t)0x10000000)

Software Reset flag

#define RCC_CSR_IWDGRSTF   ((uint32_t)0x20000000)

Independent Watchdog reset flag

#define RCC_CSR_WWDGRSTF   ((uint32_t)0x40000000)

Window watchdog reset flag

#define RCC_CSR_LPWRRSTF   ((uint32_t)0x80000000)

Low-Power reset flag

#define RTC_TR_PM   ((uint32_t)0x00400000)

#define RTC_TR_HT   ((uint32_t)0x00300000)

#define RTC_TR_HT_0   ((uint32_t)0x00100000)

#define RTC_TR_HT_1   ((uint32_t)0x00200000)

#define RTC_TR_HU   ((uint32_t)0x000F0000)

#define RTC_TR_HU_0   ((uint32_t)0x00010000)

#define RTC_TR_HU_1   ((uint32_t)0x00020000)

#define RTC_TR_HU_2   ((uint32_t)0x00040000)

#define RTC_TR_HU_3   ((uint32_t)0x00080000)

#define RTC_TR_MNT   ((uint32_t)0x00007000)

#define RTC_TR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TR_MNU   ((uint32_t)0x00000F00)

#define RTC_TR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TR_ST   ((uint32_t)0x00000070)

#define RTC_TR_ST_0   ((uint32_t)0x00000010)

#define RTC_TR_ST_1   ((uint32_t)0x00000020)

#define RTC_TR_ST_2   ((uint32_t)0x00000040)

#define RTC_TR_SU   ((uint32_t)0x0000000F)

#define RTC_TR_SU_0   ((uint32_t)0x00000001)

#define RTC_TR_SU_1   ((uint32_t)0x00000002)

#define RTC_TR_SU_2   ((uint32_t)0x00000004)

#define RTC_TR_SU_3   ((uint32_t)0x00000008)

#define RTC_DR_YT   ((uint32_t)0x00F00000)

#define RTC_DR_YT_0   ((uint32_t)0x00100000)

#define RTC_DR_YT_1   ((uint32_t)0x00200000)

#define RTC_DR_YT_2   ((uint32_t)0x00400000)

#define RTC_DR_YT_3   ((uint32_t)0x00800000)

#define RTC_DR_YU   ((uint32_t)0x000F0000)

#define RTC_DR_YU_0   ((uint32_t)0x00010000)

#define RTC_DR_YU_1   ((uint32_t)0x00020000)

#define RTC_DR_YU_2   ((uint32_t)0x00040000)

#define RTC_DR_YU_3   ((uint32_t)0x00080000)

#define RTC_DR_WDU   ((uint32_t)0x0000E000)

#define RTC_DR_WDU_0   ((uint32_t)0x00002000)

#define RTC_DR_WDU_1   ((uint32_t)0x00004000)

#define RTC_DR_WDU_2   ((uint32_t)0x00008000)

#define RTC_DR_MT   ((uint32_t)0x00001000)

#define RTC_DR_MU   ((uint32_t)0x00000F00)

#define RTC_DR_MU_0   ((uint32_t)0x00000100)

#define RTC_DR_MU_1   ((uint32_t)0x00000200)

#define RTC_DR_MU_2   ((uint32_t)0x00000400)

#define RTC_DR_MU_3   ((uint32_t)0x00000800)

#define RTC_DR_DT   ((uint32_t)0x00000030)

#define RTC_DR_DT_0   ((uint32_t)0x00000010)

#define RTC_DR_DT_1   ((uint32_t)0x00000020)

#define RTC_DR_DU   ((uint32_t)0x0000000F)

#define RTC_DR_DU_0   ((uint32_t)0x00000001)

#define RTC_DR_DU_1   ((uint32_t)0x00000002)

#define RTC_DR_DU_2   ((uint32_t)0x00000004)

#define RTC_DR_DU_3   ((uint32_t)0x00000008)

#define RTC_CR_COE   ((uint32_t)0x00800000)

#define RTC_CR_OSEL   ((uint32_t)0x00600000)

#define RTC_CR_OSEL_0   ((uint32_t)0x00200000)

#define RTC_CR_OSEL_1   ((uint32_t)0x00400000)

#define RTC_CR_POL   ((uint32_t)0x00100000)

#define RTC_CR_COSEL   ((uint32_t)0x00080000)

#define RTC_CR_BCK   ((uint32_t)0x00040000)

#define RTC_CR_SUB1H   ((uint32_t)0x00020000)

#define RTC_CR_ADD1H   ((uint32_t)0x00010000)

#define RTC_CR_TSIE   ((uint32_t)0x00008000)

#define RTC_CR_WUTIE   ((uint32_t)0x00004000)

#define RTC_CR_ALRBIE   ((uint32_t)0x00002000)

#define RTC_CR_ALRAIE   ((uint32_t)0x00001000)

#define RTC_CR_TSE   ((uint32_t)0x00000800)

#define RTC_CR_WUTE   ((uint32_t)0x00000400)

#define RTC_CR_ALRBE   ((uint32_t)0x00000200)

#define RTC_CR_ALRAE   ((uint32_t)0x00000100)

#define RTC_CR_DCE   ((uint32_t)0x00000080)

#define RTC_CR_FMT   ((uint32_t)0x00000040)

#define RTC_CR_BYPSHAD   ((uint32_t)0x00000020)

#define RTC_CR_REFCKON   ((uint32_t)0x00000010)

#define RTC_CR_TSEDGE   ((uint32_t)0x00000008)

#define RTC_CR_WUCKSEL   ((uint32_t)0x00000007)

#define RTC_CR_WUCKSEL_0   ((uint32_t)0x00000001)

#define RTC_CR_WUCKSEL_1   ((uint32_t)0x00000002)

#define RTC_CR_WUCKSEL_2   ((uint32_t)0x00000004)

#define RTC_ISR_RECALPF   ((uint32_t)0x00010000)

#define RTC_ISR_TAMP3F   ((uint32_t)0x00008000)

#define RTC_ISR_TAMP2F   ((uint32_t)0x00004000)

#define RTC_ISR_TAMP1F   ((uint32_t)0x00002000)

#define RTC_ISR_TSOVF   ((uint32_t)0x00001000)

#define RTC_ISR_TSF   ((uint32_t)0x00000800)

#define RTC_ISR_WUTF   ((uint32_t)0x00000400)

#define RTC_ISR_ALRBF   ((uint32_t)0x00000200)

#define RTC_ISR_ALRAF   ((uint32_t)0x00000100)

#define RTC_ISR_INIT   ((uint32_t)0x00000080)

#define RTC_ISR_INITF   ((uint32_t)0x00000040)

#define RTC_ISR_RSF   ((uint32_t)0x00000020)

#define RTC_ISR_INITS   ((uint32_t)0x00000010)

#define RTC_ISR_SHPF   ((uint32_t)0x00000008)

#define RTC_ISR_WUTWF   ((uint32_t)0x00000004)

#define RTC_ISR_ALRBWF   ((uint32_t)0x00000002)

#define RTC_ISR_ALRAWF   ((uint32_t)0x00000001)

#define RTC_PRER_PREDIV_A   ((uint32_t)0x007F0000)

#define RTC_PRER_PREDIV_S   ((uint32_t)0x00007FFF)

#define RTC_WUTR_WUT   ((uint32_t)0x0000FFFF)

#define RTC_CALIBR_DCS   ((uint32_t)0x00000080)

#define RTC_CALIBR_DC   ((uint32_t)0x0000001F)

#define RTC_ALRMAR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMAR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMAR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMAR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMAR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMAR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMAR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMAR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMAR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMAR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMAR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMAR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMAR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMAR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMAR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMAR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMAR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMAR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMAR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMAR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMAR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMAR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMAR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMAR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMAR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMAR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMAR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMAR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMAR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMAR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMAR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMAR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMAR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMAR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMAR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMAR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMAR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMAR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMAR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMAR_SU_3   ((uint32_t)0x00000008)

#define RTC_ALRMBR_MSK4   ((uint32_t)0x80000000)

#define RTC_ALRMBR_WDSEL   ((uint32_t)0x40000000)

#define RTC_ALRMBR_DT   ((uint32_t)0x30000000)

#define RTC_ALRMBR_DT_0   ((uint32_t)0x10000000)

#define RTC_ALRMBR_DT_1   ((uint32_t)0x20000000)

#define RTC_ALRMBR_DU   ((uint32_t)0x0F000000)

#define RTC_ALRMBR_DU_0   ((uint32_t)0x01000000)

#define RTC_ALRMBR_DU_1   ((uint32_t)0x02000000)

#define RTC_ALRMBR_DU_2   ((uint32_t)0x04000000)

#define RTC_ALRMBR_DU_3   ((uint32_t)0x08000000)

#define RTC_ALRMBR_MSK3   ((uint32_t)0x00800000)

#define RTC_ALRMBR_PM   ((uint32_t)0x00400000)

#define RTC_ALRMBR_HT   ((uint32_t)0x00300000)

#define RTC_ALRMBR_HT_0   ((uint32_t)0x00100000)

#define RTC_ALRMBR_HT_1   ((uint32_t)0x00200000)

#define RTC_ALRMBR_HU   ((uint32_t)0x000F0000)

#define RTC_ALRMBR_HU_0   ((uint32_t)0x00010000)

#define RTC_ALRMBR_HU_1   ((uint32_t)0x00020000)

#define RTC_ALRMBR_HU_2   ((uint32_t)0x00040000)

#define RTC_ALRMBR_HU_3   ((uint32_t)0x00080000)

#define RTC_ALRMBR_MSK2   ((uint32_t)0x00008000)

#define RTC_ALRMBR_MNT   ((uint32_t)0x00007000)

#define RTC_ALRMBR_MNT_0   ((uint32_t)0x00001000)

#define RTC_ALRMBR_MNT_1   ((uint32_t)0x00002000)

#define RTC_ALRMBR_MNT_2   ((uint32_t)0x00004000)

#define RTC_ALRMBR_MNU   ((uint32_t)0x00000F00)

#define RTC_ALRMBR_MNU_0   ((uint32_t)0x00000100)

#define RTC_ALRMBR_MNU_1   ((uint32_t)0x00000200)

#define RTC_ALRMBR_MNU_2   ((uint32_t)0x00000400)

#define RTC_ALRMBR_MNU_3   ((uint32_t)0x00000800)

#define RTC_ALRMBR_MSK1   ((uint32_t)0x00000080)

#define RTC_ALRMBR_ST   ((uint32_t)0x00000070)

#define RTC_ALRMBR_ST_0   ((uint32_t)0x00000010)

#define RTC_ALRMBR_ST_1   ((uint32_t)0x00000020)

#define RTC_ALRMBR_ST_2   ((uint32_t)0x00000040)

#define RTC_ALRMBR_SU   ((uint32_t)0x0000000F)

#define RTC_ALRMBR_SU_0   ((uint32_t)0x00000001)

#define RTC_ALRMBR_SU_1   ((uint32_t)0x00000002)

#define RTC_ALRMBR_SU_2   ((uint32_t)0x00000004)

#define RTC_ALRMBR_SU_3   ((uint32_t)0x00000008)

#define RTC_WPR_KEY   ((uint32_t)0x000000FF)

#define RTC_SSR_SS   ((uint32_t)0x0000FFFF)

#define RTC_SHIFTR_SUBFS   ((uint32_t)0x00007FFF)

#define RTC_SHIFTR_ADD1S   ((uint32_t)0x80000000)

#define RTC_TSTR_PM   ((uint32_t)0x00400000)

#define RTC_TSTR_HT   ((uint32_t)0x00300000)

#define RTC_TSTR_HT_0   ((uint32_t)0x00100000)

#define RTC_TSTR_HT_1   ((uint32_t)0x00200000)

#define RTC_TSTR_HU   ((uint32_t)0x000F0000)

#define RTC_TSTR_HU_0   ((uint32_t)0x00010000)

#define RTC_TSTR_HU_1   ((uint32_t)0x00020000)

#define RTC_TSTR_HU_2   ((uint32_t)0x00040000)

#define RTC_TSTR_HU_3   ((uint32_t)0x00080000)

#define RTC_TSTR_MNT   ((uint32_t)0x00007000)

#define RTC_TSTR_MNT_0   ((uint32_t)0x00001000)

#define RTC_TSTR_MNT_1   ((uint32_t)0x00002000)

#define RTC_TSTR_MNT_2   ((uint32_t)0x00004000)

#define RTC_TSTR_MNU   ((uint32_t)0x00000F00)

#define RTC_TSTR_MNU_0   ((uint32_t)0x00000100)

#define RTC_TSTR_MNU_1   ((uint32_t)0x00000200)

#define RTC_TSTR_MNU_2   ((uint32_t)0x00000400)

#define RTC_TSTR_MNU_3   ((uint32_t)0x00000800)

#define RTC_TSTR_ST   ((uint32_t)0x00000070)

#define RTC_TSTR_ST_0   ((uint32_t)0x00000010)

#define RTC_TSTR_ST_1   ((uint32_t)0x00000020)

#define RTC_TSTR_ST_2   ((uint32_t)0x00000040)

#define RTC_TSTR_SU   ((uint32_t)0x0000000F)

#define RTC_TSTR_SU_0   ((uint32_t)0x00000001)

#define RTC_TSTR_SU_1   ((uint32_t)0x00000002)

#define RTC_TSTR_SU_2   ((uint32_t)0x00000004)

#define RTC_TSTR_SU_3   ((uint32_t)0x00000008)

#define RTC_TSDR_WDU   ((uint32_t)0x0000E000)

#define RTC_TSDR_WDU_0   ((uint32_t)0x00002000)

#define RTC_TSDR_WDU_1   ((uint32_t)0x00004000)

#define RTC_TSDR_WDU_2   ((uint32_t)0x00008000)

#define RTC_TSDR_MT   ((uint32_t)0x00001000)

#define RTC_TSDR_MU   ((uint32_t)0x00000F00)

#define RTC_TSDR_MU_0   ((uint32_t)0x00000100)

#define RTC_TSDR_MU_1   ((uint32_t)0x00000200)

#define RTC_TSDR_MU_2   ((uint32_t)0x00000400)

#define RTC_TSDR_MU_3   ((uint32_t)0x00000800)

#define RTC_TSDR_DT   ((uint32_t)0x00000030)

#define RTC_TSDR_DT_0   ((uint32_t)0x00000010)

#define RTC_TSDR_DT_1   ((uint32_t)0x00000020)

#define RTC_TSDR_DU   ((uint32_t)0x0000000F)

#define RTC_TSDR_DU_0   ((uint32_t)0x00000001)

#define RTC_TSDR_DU_1   ((uint32_t)0x00000002)

#define RTC_TSDR_DU_2   ((uint32_t)0x00000004)

#define RTC_TSDR_DU_3   ((uint32_t)0x00000008)

#define RTC_TSSSR_SS   ((uint32_t)0x0000FFFF)

#define RTC_CALR_CALP   ((uint32_t)0x00008000)

#define RTC_CALR_CALW8   ((uint32_t)0x00004000)

#define RTC_CALR_CALW16   ((uint32_t)0x00002000)

#define RTC_CALR_CALM   ((uint32_t)0x000001FF)

#define RTC_CALR_CALM_0   ((uint32_t)0x00000001)

#define RTC_CALR_CALM_1   ((uint32_t)0x00000002)

#define RTC_CALR_CALM_2   ((uint32_t)0x00000004)

#define RTC_CALR_CALM_3   ((uint32_t)0x00000008)

#define RTC_CALR_CALM_4   ((uint32_t)0x00000010)

#define RTC_CALR_CALM_5   ((uint32_t)0x00000020)

#define RTC_CALR_CALM_6   ((uint32_t)0x00000040)

#define RTC_CALR_CALM_7   ((uint32_t)0x00000080)

#define RTC_CALR_CALM_8   ((uint32_t)0x00000100)

#define RTC_TAFCR_ALARMOUTTYPE   ((uint32_t)0x00040000)

#define RTC_TAFCR_TAMPPUDIS   ((uint32_t)0x00008000)

#define RTC_TAFCR_TAMPPRCH   ((uint32_t)0x00006000)

#define RTC_TAFCR_TAMPPRCH_0   ((uint32_t)0x00002000)

#define RTC_TAFCR_TAMPPRCH_1   ((uint32_t)0x00004000)

#define RTC_TAFCR_TAMPFLT   ((uint32_t)0x00001800)

#define RTC_TAFCR_TAMPFLT_0   ((uint32_t)0x00000800)

#define RTC_TAFCR_TAMPFLT_1   ((uint32_t)0x00001000)

#define RTC_TAFCR_TAMPFREQ   ((uint32_t)0x00000700)

#define RTC_TAFCR_TAMPFREQ_0   ((uint32_t)0x00000100)

#define RTC_TAFCR_TAMPFREQ_1   ((uint32_t)0x00000200)

#define RTC_TAFCR_TAMPFREQ_2   ((uint32_t)0x00000400)

#define RTC_TAFCR_TAMPTS   ((uint32_t)0x00000080)

#define RTC_TAFCR_TAMP3TRG   ((uint32_t)0x00000040)

#define RTC_TAFCR_TAMP3E   ((uint32_t)0x00000020)

#define RTC_TAFCR_TAMP2TRG   ((uint32_t)0x00000010)

#define RTC_TAFCR_TAMP2E   ((uint32_t)0x00000008)

#define RTC_TAFCR_TAMPIE   ((uint32_t)0x00000004)

#define RTC_TAFCR_TAMP1TRG   ((uint32_t)0x00000002)

#define RTC_TAFCR_TAMP1E   ((uint32_t)0x00000001)

#define RTC_ALRMASSR_MASKSS   ((uint32_t)0x0F000000)

#define RTC_ALRMASSR_MASKSS_0   ((uint32_t)0x01000000)

#define RTC_ALRMASSR_MASKSS_1   ((uint32_t)0x02000000)

#define RTC_ALRMASSR_MASKSS_2   ((uint32_t)0x04000000)

#define RTC_ALRMASSR_MASKSS_3   ((uint32_t)0x08000000)

#define RTC_ALRMASSR_SS   ((uint32_t)0x00007FFF)

#define RTC_ALRMBSSR_MASKSS   ((uint32_t)0x0F000000)

#define RTC_ALRMBSSR_MASKSS_0   ((uint32_t)0x01000000)

#define RTC_ALRMBSSR_MASKSS_1   ((uint32_t)0x02000000)

#define RTC_ALRMBSSR_MASKSS_2   ((uint32_t)0x04000000)

#define RTC_ALRMBSSR_MASKSS_3   ((uint32_t)0x08000000)

#define RTC_ALRMBSSR_SS   ((uint32_t)0x00007FFF)

#define RTC_BKP0R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP1R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP2R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP3R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP4R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP5R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP6R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP7R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP8R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP9R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP10R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP11R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP12R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP13R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP14R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP15R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP16R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP17R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP18R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP19R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP20R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP21R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP22R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP23R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP24R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP25R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP26R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP27R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP28R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP29R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP30R   ((uint32_t)0xFFFFFFFF)

#define RTC_BKP31R   ((uint32_t)0xFFFFFFFF)

#define SDIO_POWER_PWRCTRL   ((uint8_t)0x03)

PWRCTRL[1:0] bits (Power supply control bits)

#define SDIO_POWER_PWRCTRL_0   ((uint8_t)0x01)

Bit 0

#define SDIO_POWER_PWRCTRL_1   ((uint8_t)0x02)

Bit 1

#define SDIO_CLKCR_CLKDIV   ((uint16_t)0x00FF)

Clock divide factor

#define SDIO_CLKCR_CLKEN   ((uint16_t)0x0100)

Clock enable bit

#define SDIO_CLKCR_PWRSAV   ((uint16_t)0x0200)

Power saving configuration bit

#define SDIO_CLKCR_BYPASS   ((uint16_t)0x0400)

Clock divider bypass enable bit

#define SDIO_CLKCR_WIDBUS   ((uint16_t)0x1800)

WIDBUS[1:0] bits (Wide bus mode enable bit)

#define SDIO_CLKCR_WIDBUS_0   ((uint16_t)0x0800)

Bit 0

#define SDIO_CLKCR_WIDBUS_1   ((uint16_t)0x1000)

Bit 1

#define SDIO_CLKCR_NEGEDGE   ((uint16_t)0x2000)

SDIO_CK dephasing selection bit

#define SDIO_CLKCR_HWFC_EN   ((uint16_t)0x4000)

HW Flow Control enable

#define SDIO_ARG_CMDARG   ((uint32_t)0xFFFFFFFF)

Command argument

#define SDIO_CMD_CMDINDEX   ((uint16_t)0x003F)

Command Index

#define SDIO_CMD_WAITRESP   ((uint16_t)0x00C0)

WAITRESP[1:0] bits (Wait for response bits)

#define SDIO_CMD_WAITRESP_0   ((uint16_t)0x0040)

Bit 0

#define SDIO_CMD_WAITRESP_1   ((uint16_t)0x0080)

Bit 1

#define SDIO_CMD_WAITINT   ((uint16_t)0x0100)

CPSM Waits for Interrupt Request

#define SDIO_CMD_WAITPEND   ((uint16_t)0x0200)

CPSM Waits for ends of data transfer (CmdPend internal signal)

#define SDIO_CMD_CPSMEN   ((uint16_t)0x0400)

Command path state machine (CPSM) Enable bit

#define SDIO_CMD_SDIOSUSPEND   ((uint16_t)0x0800)

SD I/O suspend command

#define SDIO_CMD_ENCMDCOMPL   ((uint16_t)0x1000)

Enable CMD completion

#define SDIO_CMD_NIEN   ((uint16_t)0x2000)

Not Interrupt Enable

#define SDIO_CMD_CEATACMD   ((uint16_t)0x4000)

CE-ATA command

#define SDIO_RESPCMD_RESPCMD   ((uint8_t)0x3F)

Response command index

#define SDIO_RESP0_CARDSTATUS0   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP1_CARDSTATUS1   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP2_CARDSTATUS2   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP3_CARDSTATUS3   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_RESP4_CARDSTATUS4   ((uint32_t)0xFFFFFFFF)

Card Status

#define SDIO_DTIMER_DATATIME   ((uint32_t)0xFFFFFFFF)

Data timeout period.

#define SDIO_DLEN_DATALENGTH   ((uint32_t)0x01FFFFFF)

Data length value

#define SDIO_DCTRL_DTEN   ((uint16_t)0x0001)

Data transfer enabled bit

#define SDIO_DCTRL_DTDIR   ((uint16_t)0x0002)

Data transfer direction selection

#define SDIO_DCTRL_DTMODE   ((uint16_t)0x0004)

Data transfer mode selection

#define SDIO_DCTRL_DMAEN   ((uint16_t)0x0008)

DMA enabled bit

#define SDIO_DCTRL_DBLOCKSIZE   ((uint16_t)0x00F0)

DBLOCKSIZE[3:0] bits (Data block size)

#define SDIO_DCTRL_DBLOCKSIZE_0   ((uint16_t)0x0010)

Bit 0

#define SDIO_DCTRL_DBLOCKSIZE_1   ((uint16_t)0x0020)

Bit 1

#define SDIO_DCTRL_DBLOCKSIZE_2   ((uint16_t)0x0040)

Bit 2

#define SDIO_DCTRL_DBLOCKSIZE_3   ((uint16_t)0x0080)

Bit 3

#define SDIO_DCTRL_RWSTART   ((uint16_t)0x0100)

Read wait start

#define SDIO_DCTRL_RWSTOP   ((uint16_t)0x0200)

Read wait stop

#define SDIO_DCTRL_RWMOD   ((uint16_t)0x0400)

Read wait mode

#define SDIO_DCTRL_SDIOEN   ((uint16_t)0x0800)

SD I/O enable functions

#define SDIO_DCOUNT_DATACOUNT   ((uint32_t)0x01FFFFFF)

Data count value

#define SDIO_STA_CCRCFAIL   ((uint32_t)0x00000001)

Command response received (CRC check failed)

#define SDIO_STA_DCRCFAIL   ((uint32_t)0x00000002)

Data block sent/received (CRC check failed)

#define SDIO_STA_CTIMEOUT   ((uint32_t)0x00000004)

Command response timeout

#define SDIO_STA_DTIMEOUT   ((uint32_t)0x00000008)

Data timeout

#define SDIO_STA_TXUNDERR   ((uint32_t)0x00000010)

Transmit FIFO underrun error

#define SDIO_STA_RXOVERR   ((uint32_t)0x00000020)

Received FIFO overrun error

#define SDIO_STA_CMDREND   ((uint32_t)0x00000040)

Command response received (CRC check passed)

#define SDIO_STA_CMDSENT   ((uint32_t)0x00000080)

Command sent (no response required)

#define SDIO_STA_DATAEND   ((uint32_t)0x00000100)

Data end (data counter, SDIDCOUNT, is zero)

#define SDIO_STA_STBITERR   ((uint32_t)0x00000200)

Start bit not detected on all data signals in wide bus mode

#define SDIO_STA_DBCKEND   ((uint32_t)0x00000400)

Data block sent/received (CRC check passed)

#define SDIO_STA_CMDACT   ((uint32_t)0x00000800)

Command transfer in progress

#define SDIO_STA_TXACT   ((uint32_t)0x00001000)

Data transmit in progress

#define SDIO_STA_RXACT   ((uint32_t)0x00002000)

Data receive in progress

#define SDIO_STA_TXFIFOHE   ((uint32_t)0x00004000)

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

#define SDIO_STA_RXFIFOHF   ((uint32_t)0x00008000)

Receive FIFO Half Full: there are at least 8 words in the FIFO

#define SDIO_STA_TXFIFOF   ((uint32_t)0x00010000)

Transmit FIFO full

#define SDIO_STA_RXFIFOF   ((uint32_t)0x00020000)

Receive FIFO full

#define SDIO_STA_TXFIFOE   ((uint32_t)0x00040000)

Transmit FIFO empty

#define SDIO_STA_RXFIFOE   ((uint32_t)0x00080000)

Receive FIFO empty

#define SDIO_STA_TXDAVL   ((uint32_t)0x00100000)

Data available in transmit FIFO

#define SDIO_STA_RXDAVL   ((uint32_t)0x00200000)

Data available in receive FIFO

#define SDIO_STA_SDIOIT   ((uint32_t)0x00400000)

SDIO interrupt received

#define SDIO_STA_CEATAEND   ((uint32_t)0x00800000)

CE-ATA command completion signal received for CMD61

#define SDIO_ICR_CCRCFAILC   ((uint32_t)0x00000001)

CCRCFAIL flag clear bit

#define SDIO_ICR_DCRCFAILC   ((uint32_t)0x00000002)

DCRCFAIL flag clear bit

#define SDIO_ICR_CTIMEOUTC   ((uint32_t)0x00000004)

CTIMEOUT flag clear bit

#define SDIO_ICR_DTIMEOUTC   ((uint32_t)0x00000008)

DTIMEOUT flag clear bit

#define SDIO_ICR_TXUNDERRC   ((uint32_t)0x00000010)

TXUNDERR flag clear bit

#define SDIO_ICR_RXOVERRC   ((uint32_t)0x00000020)

RXOVERR flag clear bit

#define SDIO_ICR_CMDRENDC   ((uint32_t)0x00000040)

CMDREND flag clear bit

#define SDIO_ICR_CMDSENTC   ((uint32_t)0x00000080)

CMDSENT flag clear bit

#define SDIO_ICR_DATAENDC   ((uint32_t)0x00000100)

DATAEND flag clear bit

#define SDIO_ICR_STBITERRC   ((uint32_t)0x00000200)

STBITERR flag clear bit

#define SDIO_ICR_DBCKENDC   ((uint32_t)0x00000400)

DBCKEND flag clear bit

#define SDIO_ICR_SDIOITC   ((uint32_t)0x00400000)

SDIOIT flag clear bit

#define SDIO_ICR_CEATAENDC   ((uint32_t)0x00800000)

CEATAEND flag clear bit

#define SDIO_MASK_CCRCFAILIE   ((uint32_t)0x00000001)

Command CRC Fail Interrupt Enable

#define SDIO_MASK_DCRCFAILIE   ((uint32_t)0x00000002)

Data CRC Fail Interrupt Enable

#define SDIO_MASK_CTIMEOUTIE   ((uint32_t)0x00000004)

Command TimeOut Interrupt Enable

#define SDIO_MASK_DTIMEOUTIE   ((uint32_t)0x00000008)

Data TimeOut Interrupt Enable

#define SDIO_MASK_TXUNDERRIE   ((uint32_t)0x00000010)

Tx FIFO UnderRun Error Interrupt Enable

#define SDIO_MASK_RXOVERRIE   ((uint32_t)0x00000020)

Rx FIFO OverRun Error Interrupt Enable

#define SDIO_MASK_CMDRENDIE   ((uint32_t)0x00000040)

Command Response Received Interrupt Enable

#define SDIO_MASK_CMDSENTIE   ((uint32_t)0x00000080)

Command Sent Interrupt Enable

#define SDIO_MASK_DATAENDIE   ((uint32_t)0x00000100)

Data End Interrupt Enable

#define SDIO_MASK_STBITERRIE   ((uint32_t)0x00000200)

Start Bit Error Interrupt Enable

#define SDIO_MASK_DBCKENDIE   ((uint32_t)0x00000400)

Data Block End Interrupt Enable

#define SDIO_MASK_CMDACTIE   ((uint32_t)0x00000800)

Command Acting Interrupt Enable

#define SDIO_MASK_TXACTIE   ((uint32_t)0x00001000)

Data Transmit Acting Interrupt Enable

#define SDIO_MASK_RXACTIE   ((uint32_t)0x00002000)

Data receive acting interrupt enabled

#define SDIO_MASK_TXFIFOHEIE   ((uint32_t)0x00004000)

Tx FIFO Half Empty interrupt Enable

#define SDIO_MASK_RXFIFOHFIE   ((uint32_t)0x00008000)

Rx FIFO Half Full interrupt Enable

#define SDIO_MASK_TXFIFOFIE   ((uint32_t)0x00010000)

Tx FIFO Full interrupt Enable

#define SDIO_MASK_RXFIFOFIE   ((uint32_t)0x00020000)

Rx FIFO Full interrupt Enable

#define SDIO_MASK_TXFIFOEIE   ((uint32_t)0x00040000)

Tx FIFO Empty interrupt Enable

#define SDIO_MASK_RXFIFOEIE   ((uint32_t)0x00080000)

Rx FIFO Empty interrupt Enable

#define SDIO_MASK_TXDAVLIE   ((uint32_t)0x00100000)

Data available in Tx FIFO interrupt Enable

#define SDIO_MASK_RXDAVLIE   ((uint32_t)0x00200000)

Data available in Rx FIFO interrupt Enable

#define SDIO_MASK_SDIOITIE   ((uint32_t)0x00400000)

SDIO Mode Interrupt Received interrupt Enable

#define SDIO_MASK_CEATAENDIE   ((uint32_t)0x00800000)

CE-ATA command completion signal received Interrupt Enable

#define SDIO_FIFOCNT_FIFOCOUNT   ((uint32_t)0x00FFFFFF)

Remaining number of words to be written to or read from the FIFO

#define SDIO_FIFO_FIFODATA   ((uint32_t)0xFFFFFFFF)

Receive and transmit FIFO data

#define SPI_CR1_CPHA   ((uint16_t)0x0001)

Clock Phase

#define SPI_CR1_CPOL   ((uint16_t)0x0002)

Clock Polarity

#define SPI_CR1_MSTR   ((uint16_t)0x0004)

Master Selection

#define SPI_CR1_BR   ((uint16_t)0x0038)

BR[2:0] bits (Baud Rate Control)

#define SPI_CR1_BR_0   ((uint16_t)0x0008)

Bit 0

#define SPI_CR1_BR_1   ((uint16_t)0x0010)

Bit 1

#define SPI_CR1_BR_2   ((uint16_t)0x0020)

Bit 2

#define SPI_CR1_SPE   ((uint16_t)0x0040)

SPI Enable

#define SPI_CR1_LSBFIRST   ((uint16_t)0x0080)

Frame Format

#define SPI_CR1_SSI   ((uint16_t)0x0100)

Internal slave select

#define SPI_CR1_SSM   ((uint16_t)0x0200)

Software slave management

#define SPI_CR1_RXONLY   ((uint16_t)0x0400)

Receive only

#define SPI_CR1_DFF   ((uint16_t)0x0800)

Data Frame Format

#define SPI_CR1_CRCNEXT   ((uint16_t)0x1000)

Transmit CRC next

#define SPI_CR1_CRCEN   ((uint16_t)0x2000)

Hardware CRC calculation enable

#define SPI_CR1_BIDIOE   ((uint16_t)0x4000)

Output enable in bidirectional mode

#define SPI_CR1_BIDIMODE   ((uint16_t)0x8000)

Bidirectional data mode enable

#define SPI_CR2_RXDMAEN   ((uint8_t)0x01)

Rx Buffer DMA Enable

#define SPI_CR2_TXDMAEN   ((uint8_t)0x02)

Tx Buffer DMA Enable

#define SPI_CR2_SSOE   ((uint8_t)0x04)

SS Output Enable

#define SPI_CR2_FRF   ((uint8_t)0x08)

Frame format

#define SPI_CR2_ERRIE   ((uint8_t)0x20)

Error Interrupt Enable

#define SPI_CR2_RXNEIE   ((uint8_t)0x40)

RX buffer Not Empty Interrupt Enable

#define SPI_CR2_TXEIE   ((uint8_t)0x80)

Tx buffer Empty Interrupt Enable

#define SPI_SR_RXNE   ((uint8_t)0x01)

Receive buffer Not Empty

#define SPI_SR_TXE   ((uint8_t)0x02)

Transmit buffer Empty

#define SPI_SR_CHSIDE   ((uint8_t)0x04)

Channel side

#define SPI_SR_UDR   ((uint8_t)0x08)

Underrun flag

#define SPI_SR_CRCERR   ((uint8_t)0x10)

CRC Error flag

#define SPI_SR_MODF   ((uint8_t)0x20)

Mode fault

#define SPI_SR_OVR   ((uint8_t)0x40)

Overrun flag

#define SPI_SR_BSY   ((uint8_t)0x80)

Busy flag

#define SPI_DR_DR   ((uint16_t)0xFFFF)

Data Register

#define SPI_CRCPR_CRCPOLY   ((uint16_t)0xFFFF)

CRC polynomial register

#define SPI_RXCRCR_RXCRC   ((uint16_t)0xFFFF)

Rx CRC Register

#define SPI_TXCRCR_TXCRC   ((uint16_t)0xFFFF)

Tx CRC Register

#define SPI_I2SCFGR_CHLEN   ((uint16_t)0x0001)

Channel length (number of bits per audio channel)

#define SPI_I2SCFGR_DATLEN   ((uint16_t)0x0006)

DATLEN[1:0] bits (Data length to be transferred)

#define SPI_I2SCFGR_DATLEN_0   ((uint16_t)0x0002)

Bit 0

#define SPI_I2SCFGR_DATLEN_1   ((uint16_t)0x0004)

Bit 1

#define SPI_I2SCFGR_CKPOL   ((uint16_t)0x0008)

steady state clock polarity

#define SPI_I2SCFGR_I2SSTD   ((uint16_t)0x0030)

I2SSTD[1:0] bits (I2S standard selection)

#define SPI_I2SCFGR_I2SSTD_0   ((uint16_t)0x0010)

Bit 0

#define SPI_I2SCFGR_I2SSTD_1   ((uint16_t)0x0020)

Bit 1

#define SPI_I2SCFGR_PCMSYNC   ((uint16_t)0x0080)

PCM frame synchronization

#define SPI_I2SCFGR_I2SCFG   ((uint16_t)0x0300)

I2SCFG[1:0] bits (I2S configuration mode)

#define SPI_I2SCFGR_I2SCFG_0   ((uint16_t)0x0100)

Bit 0

#define SPI_I2SCFGR_I2SCFG_1   ((uint16_t)0x0200)

Bit 1

#define SPI_I2SCFGR_I2SE   ((uint16_t)0x0400)

I2S Enable

#define SPI_I2SCFGR_I2SMOD   ((uint16_t)0x0800)

I2S mode selection

#define SPI_I2SPR_I2SDIV   ((uint16_t)0x00FF)

I2S Linear prescaler

#define SPI_I2SPR_ODD   ((uint16_t)0x0100)

Odd factor for the prescaler

#define SPI_I2SPR_MCKOE   ((uint16_t)0x0200)

Master Clock Output Enable

#define SYSCFG_MEMRMP_MEM_MODE   ((uint32_t)0x00000003)

SYSCFG_Memory Remap Config

#define SYSCFG_MEMRMP_MEM_MODE_0   ((uint32_t)0x00000001)

Bit 0

#define SYSCFG_MEMRMP_MEM_MODE_1   ((uint32_t)0x00000002)

Bit 1

#define SYSCFG_MEMRMP_BOOT_MODE   ((uint32_t)0x00000300)

Boot mode Config

#define SYSCFG_MEMRMP_BOOT_MODE_0   ((uint32_t)0x00000100)

Bit 0

#define SYSCFG_MEMRMP_BOOT_MODE_1   ((uint32_t)0x00000200)

Bit 1

#define SYSCFG_PMC_USB_PU   ((uint32_t)0x00000001)

SYSCFG PMC

#define SYSCFG_EXTICR1_EXTI0   ((uint16_t)0x000F)

EXTI 0 configuration

#define SYSCFG_EXTICR1_EXTI1   ((uint16_t)0x00F0)

EXTI 1 configuration

#define SYSCFG_EXTICR1_EXTI2   ((uint16_t)0x0F00)

EXTI 2 configuration

#define SYSCFG_EXTICR1_EXTI3   ((uint16_t)0xF000)

EXTI 3 configuration

#define SYSCFG_EXTICR1_EXTI0_PA   ((uint16_t)0x0000)

EXTI0 configuration.

PA[0] pin

#define SYSCFG_EXTICR1_EXTI0_PB   ((uint16_t)0x0001)

PB[0] pin

#define SYSCFG_EXTICR1_EXTI0_PC   ((uint16_t)0x0002)

PC[0] pin

#define SYSCFG_EXTICR1_EXTI0_PD   ((uint16_t)0x0003)

PD[0] pin

#define SYSCFG_EXTICR1_EXTI0_PE   ((uint16_t)0x0004)

PE[0] pin

#define SYSCFG_EXTICR1_EXTI0_PH   ((uint16_t)0x0005)

PH[0] pin

#define SYSCFG_EXTICR1_EXTI0_PF   ((uint16_t)0x0006)

PF[0] pin

#define SYSCFG_EXTICR1_EXTI0_PG   ((uint16_t)0x0007)

PG[0] pin

#define SYSCFG_EXTICR1_EXTI1_PA   ((uint16_t)0x0000)

EXTI1 configuration.

PA[1] pin

#define SYSCFG_EXTICR1_EXTI1_PB   ((uint16_t)0x0010)

PB[1] pin

#define SYSCFG_EXTICR1_EXTI1_PC   ((uint16_t)0x0020)

PC[1] pin

#define SYSCFG_EXTICR1_EXTI1_PD   ((uint16_t)0x0030)

PD[1] pin

#define SYSCFG_EXTICR1_EXTI1_PE   ((uint16_t)0x0040)

PE[1] pin

#define SYSCFG_EXTICR1_EXTI1_PH   ((uint16_t)0x0050)

PH[1] pin

#define SYSCFG_EXTICR1_EXTI1_PF   ((uint16_t)0x0060)

PF[1] pin

#define SYSCFG_EXTICR1_EXTI1_PG   ((uint16_t)0x0070)

PG[1] pin

#define SYSCFG_EXTICR1_EXTI2_PA   ((uint16_t)0x0000)

EXTI2 configuration.

PA[2] pin

#define SYSCFG_EXTICR1_EXTI2_PB   ((uint16_t)0x0100)

PB[2] pin

#define SYSCFG_EXTICR1_EXTI2_PC   ((uint16_t)0x0200)

PC[2] pin

#define SYSCFG_EXTICR1_EXTI2_PD   ((uint16_t)0x0300)

PD[2] pin

#define SYSCFG_EXTICR1_EXTI2_PE   ((uint16_t)0x0400)

PE[2] pin

#define SYSCFG_EXTICR1_EXTI2_PH   ((uint16_t)0x0500)

PH[2] pin

#define SYSCFG_EXTICR1_EXTI2_PF   ((uint16_t)0x0600)

PF[2] pin

#define SYSCFG_EXTICR1_EXTI2_PG   ((uint16_t)0x0700)

PG[2] pin

#define SYSCFG_EXTICR1_EXTI3_PA   ((uint16_t)0x0000)

EXTI3 configuration.

PA[3] pin

#define SYSCFG_EXTICR1_EXTI3_PB   ((uint16_t)0x1000)

PB[3] pin

#define SYSCFG_EXTICR1_EXTI3_PC   ((uint16_t)0x2000)

PC[3] pin

#define SYSCFG_EXTICR1_EXTI3_PD   ((uint16_t)0x3000)

PD[3] pin

#define SYSCFG_EXTICR1_EXTI3_PE   ((uint16_t)0x4000)

PE[3] pin

#define SYSCFG_EXTICR1_EXTI3_PF   ((uint16_t)0x3000)

PF[3] pin

#define SYSCFG_EXTICR1_EXTI3_PG   ((uint16_t)0x4000)

PG[3] pin

#define SYSCFG_EXTICR2_EXTI4   ((uint16_t)0x000F)

EXTI 4 configuration

#define SYSCFG_EXTICR2_EXTI5   ((uint16_t)0x00F0)

EXTI 5 configuration

#define SYSCFG_EXTICR2_EXTI6   ((uint16_t)0x0F00)

EXTI 6 configuration

#define SYSCFG_EXTICR2_EXTI7   ((uint16_t)0xF000)

EXTI 7 configuration

#define SYSCFG_EXTICR2_EXTI4_PA   ((uint16_t)0x0000)

EXTI4 configuration.

PA[4] pin

#define SYSCFG_EXTICR2_EXTI4_PB   ((uint16_t)0x0001)

PB[4] pin

#define SYSCFG_EXTICR2_EXTI4_PC   ((uint16_t)0x0002)

PC[4] pin

#define SYSCFG_EXTICR2_EXTI4_PD   ((uint16_t)0x0003)

PD[4] pin

#define SYSCFG_EXTICR2_EXTI4_PE   ((uint16_t)0x0004)

PE[4] pin

#define SYSCFG_EXTICR2_EXTI4_PF   ((uint16_t)0x0006)

PF[4] pin

#define SYSCFG_EXTICR2_EXTI4_PG   ((uint16_t)0x0007)

PG[4] pin

#define SYSCFG_EXTICR2_EXTI5_PA   ((uint16_t)0x0000)

EXTI5 configuration.

PA[5] pin

#define SYSCFG_EXTICR2_EXTI5_PB   ((uint16_t)0x0010)

PB[5] pin

#define SYSCFG_EXTICR2_EXTI5_PC   ((uint16_t)0x0020)

PC[5] pin

#define SYSCFG_EXTICR2_EXTI5_PD   ((uint16_t)0x0030)

PD[5] pin

#define SYSCFG_EXTICR2_EXTI5_PE   ((uint16_t)0x0040)

PE[5] pin

#define SYSCFG_EXTICR2_EXTI5_PF   ((uint16_t)0x0060)

PF[5] pin

#define SYSCFG_EXTICR2_EXTI5_PG   ((uint16_t)0x0070)

PG[5] pin

#define SYSCFG_EXTICR2_EXTI6_PA   ((uint16_t)0x0000)

EXTI6 configuration.

PA[6] pin

#define SYSCFG_EXTICR2_EXTI6_PB   ((uint16_t)0x0100)

PB[6] pin

#define SYSCFG_EXTICR2_EXTI6_PC   ((uint16_t)0x0200)

PC[6] pin

#define SYSCFG_EXTICR2_EXTI6_PD   ((uint16_t)0x0300)

PD[6] pin

#define SYSCFG_EXTICR2_EXTI6_PE   ((uint16_t)0x0400)

PE[6] pin

#define SYSCFG_EXTICR2_EXTI6_PF   ((uint16_t)0x0600)

PF[6] pin

#define SYSCFG_EXTICR2_EXTI6_PG   ((uint16_t)0x0700)

PG[6] pin

#define SYSCFG_EXTICR2_EXTI7_PA   ((uint16_t)0x0000)

EXTI7 configuration.

PA[7] pin

#define SYSCFG_EXTICR2_EXTI7_PB   ((uint16_t)0x1000)

PB[7] pin

#define SYSCFG_EXTICR2_EXTI7_PC   ((uint16_t)0x2000)

PC[7] pin

#define SYSCFG_EXTICR2_EXTI7_PD   ((uint16_t)0x3000)

PD[7] pin

#define SYSCFG_EXTICR2_EXTI7_PE   ((uint16_t)0x4000)

PE[7] pin

#define SYSCFG_EXTICR2_EXTI7_PF   ((uint16_t)0x6000)

PF[7] pin

#define SYSCFG_EXTICR2_EXTI7_PG   ((uint16_t)0x7000)

PG[7] pin

#define SYSCFG_EXTICR3_EXTI8   ((uint16_t)0x000F)

EXTI 8 configuration

#define SYSCFG_EXTICR3_EXTI9   ((uint16_t)0x00F0)

EXTI 9 configuration

#define SYSCFG_EXTICR3_EXTI10   ((uint16_t)0x0F00)

EXTI 10 configuration

#define SYSCFG_EXTICR3_EXTI11   ((uint16_t)0xF000)

EXTI 11 configuration

#define SYSCFG_EXTICR3_EXTI8_PA   ((uint16_t)0x0000)

EXTI8 configuration.

PA[8] pin

#define SYSCFG_EXTICR3_EXTI8_PB   ((uint16_t)0x0001)

PB[8] pin

#define SYSCFG_EXTICR3_EXTI8_PC   ((uint16_t)0x0002)

PC[8] pin

#define SYSCFG_EXTICR3_EXTI8_PD   ((uint16_t)0x0003)

PD[8] pin

#define SYSCFG_EXTICR3_EXTI8_PE   ((uint16_t)0x0004)

PE[8] pin

#define SYSCFG_EXTICR3_EXTI8_PF   ((uint16_t)0x0006)

PF[8] pin

#define SYSCFG_EXTICR3_EXTI8_PG   ((uint16_t)0x0007)

PG[8] pin

#define SYSCFG_EXTICR3_EXTI9_PA   ((uint16_t)0x0000)

EXTI9 configuration.

PA[9] pin

#define SYSCFG_EXTICR3_EXTI9_PB   ((uint16_t)0x0010)

PB[9] pin

#define SYSCFG_EXTICR3_EXTI9_PC   ((uint16_t)0x0020)

PC[9] pin

#define SYSCFG_EXTICR3_EXTI9_PD   ((uint16_t)0x0030)

PD[9] pin

#define SYSCFG_EXTICR3_EXTI9_PE   ((uint16_t)0x0040)

PE[9] pin

#define SYSCFG_EXTICR3_EXTI9_PF   ((uint16_t)0x0060)

PF[9] pin

#define SYSCFG_EXTICR3_EXTI9_PG   ((uint16_t)0x0070)

PG[9] pin

#define SYSCFG_EXTICR3_EXTI10_PA   ((uint16_t)0x0000)

EXTI10 configuration.

PA[10] pin

#define SYSCFG_EXTICR3_EXTI10_PB   ((uint16_t)0x0100)

PB[10] pin

#define SYSCFG_EXTICR3_EXTI10_PC   ((uint16_t)0x0200)

PC[10] pin

#define SYSCFG_EXTICR3_EXTI10_PD   ((uint16_t)0x0300)

PD[10] pin

#define SYSCFG_EXTICR3_EXTI10_PE   ((uint16_t)0x0400)

PE[10] pin

#define SYSCFG_EXTICR3_EXTI10_PF   ((uint16_t)0x0600)

PF[10] pin

#define SYSCFG_EXTICR3_EXTI10_PG   ((uint16_t)0x0700)

PG[10] pin

#define SYSCFG_EXTICR3_EXTI11_PA   ((uint16_t)0x0000)

EXTI11 configuration.

PA[11] pin

#define SYSCFG_EXTICR3_EXTI11_PB   ((uint16_t)0x1000)

PB[11] pin

#define SYSCFG_EXTICR3_EXTI11_PC   ((uint16_t)0x2000)

PC[11] pin

#define SYSCFG_EXTICR3_EXTI11_PD   ((uint16_t)0x3000)

PD[11] pin

#define SYSCFG_EXTICR3_EXTI11_PE   ((uint16_t)0x4000)

PE[11] pin

#define SYSCFG_EXTICR3_EXTI11_PF   ((uint16_t)0x6000)

PF[11] pin

#define SYSCFG_EXTICR3_EXTI11_PG   ((uint16_t)0x7000)

PG[11] pin

#define SYSCFG_EXTICR4_EXTI12   ((uint16_t)0x000F)

EXTI 12 configuration

#define SYSCFG_EXTICR4_EXTI13   ((uint16_t)0x00F0)

EXTI 13 configuration

#define SYSCFG_EXTICR4_EXTI14   ((uint16_t)0x0F00)

EXTI 14 configuration

#define SYSCFG_EXTICR4_EXTI15   ((uint16_t)0xF000)

EXTI 15 configuration

#define SYSCFG_EXTICR4_EXTI12_PA   ((uint16_t)0x0000)

EXTI12 configuration.

PA[12] pin

#define SYSCFG_EXTICR4_EXTI12_PB   ((uint16_t)0x0001)

PB[12] pin

#define SYSCFG_EXTICR4_EXTI12_PC   ((uint16_t)0x0002)

PC[12] pin

#define SYSCFG_EXTICR4_EXTI12_PD   ((uint16_t)0x0003)

PD[12] pin

#define SYSCFG_EXTICR4_EXTI12_PE   ((uint16_t)0x0004)

PE[12] pin

#define SYSCFG_EXTICR4_EXTI12_PF   ((uint16_t)0x0006)

PF[12] pin

#define SYSCFG_EXTICR4_EXTI12_PG   ((uint16_t)0x0007)

PG[12] pin

#define SYSCFG_EXTICR4_EXTI13_PA   ((uint16_t)0x0000)

EXTI13 configuration.

PA[13] pin

#define SYSCFG_EXTICR4_EXTI13_PB   ((uint16_t)0x0010)

PB[13] pin

#define SYSCFG_EXTICR4_EXTI13_PC   ((uint16_t)0x0020)

PC[13] pin

#define SYSCFG_EXTICR4_EXTI13_PD   ((uint16_t)0x0030)

PD[13] pin

#define SYSCFG_EXTICR4_EXTI13_PE   ((uint16_t)0x0040)

PE[13] pin

#define SYSCFG_EXTICR4_EXTI13_PF   ((uint16_t)0x0060)

PF[13] pin

#define SYSCFG_EXTICR4_EXTI13_PG   ((uint16_t)0x0070)

PG[13] pin

#define SYSCFG_EXTICR4_EXTI14_PA   ((uint16_t)0x0000)

EXTI14 configuration.

PA[14] pin

#define SYSCFG_EXTICR4_EXTI14_PB   ((uint16_t)0x0100)

PB[14] pin

#define SYSCFG_EXTICR4_EXTI14_PC   ((uint16_t)0x0200)

PC[14] pin

#define SYSCFG_EXTICR4_EXTI14_PD   ((uint16_t)0x0300)

PD[14] pin

#define SYSCFG_EXTICR4_EXTI14_PE   ((uint16_t)0x0400)

PE[14] pin

#define SYSCFG_EXTICR4_EXTI14_PF   ((uint16_t)0x0600)

PF[14] pin

#define SYSCFG_EXTICR4_EXTI14_PG   ((uint16_t)0x0700)

PG[14] pin

#define SYSCFG_EXTICR4_EXTI15_PA   ((uint16_t)0x0000)

EXTI15 configuration.

PA[15] pin

#define SYSCFG_EXTICR4_EXTI15_PB   ((uint16_t)0x1000)

PB[15] pin

#define SYSCFG_EXTICR4_EXTI15_PC   ((uint16_t)0x2000)

PC[15] pin

#define SYSCFG_EXTICR4_EXTI15_PD   ((uint16_t)0x3000)

PD[15] pin

#define SYSCFG_EXTICR4_EXTI15_PE   ((uint16_t)0x4000)

PE[15] pin

#define SYSCFG_EXTICR4_EXTI15_PF   ((uint16_t)0x6000)

PF[15] pin

#define SYSCFG_EXTICR4_EXTI15_PG   ((uint16_t)0x7000)

PG[15] pin

#define RI_ICR_IC1Z   ((uint32_t)0x0000000F)

IC1Z[3:0] bits (Input Capture 1 select bits)

#define RI_ICR_IC1Z_0   ((uint32_t)0x00000001)

Bit 0

#define RI_ICR_IC1Z_1   ((uint32_t)0x00000002)

Bit 1

#define RI_ICR_IC1Z_2   ((uint32_t)0x00000004)

Bit 2

#define RI_ICR_IC1Z_3   ((uint32_t)0x00000008)

Bit 3

#define RI_ICR_IC2Z   ((uint32_t)0x000000F0)

IC2Z[3:0] bits (Input Capture 2 select bits)

#define RI_ICR_IC2Z_0   ((uint32_t)0x00000010)

Bit 0

#define RI_ICR_IC2Z_1   ((uint32_t)0x00000020)

Bit 1

#define RI_ICR_IC2Z_2   ((uint32_t)0x00000040)

Bit 2

#define RI_ICR_IC2Z_3   ((uint32_t)0x00000080)

Bit 3

#define RI_ICR_IC3Z   ((uint32_t)0x00000F00)

IC3Z[3:0] bits (Input Capture 3 select bits)

#define RI_ICR_IC3Z_0   ((uint32_t)0x00000100)

Bit 0

#define RI_ICR_IC3Z_1   ((uint32_t)0x00000200)

Bit 1

#define RI_ICR_IC3Z_2   ((uint32_t)0x00000400)

Bit 2

#define RI_ICR_IC3Z_3   ((uint32_t)0x00000800)

Bit 3

#define RI_ICR_IC4Z   ((uint32_t)0x0000F000)

IC4Z[3:0] bits (Input Capture 4 select bits)

#define RI_ICR_IC4Z_0   ((uint32_t)0x00001000)

Bit 0

#define RI_ICR_IC4Z_1   ((uint32_t)0x00002000)

Bit 1

#define RI_ICR_IC4Z_2   ((uint32_t)0x00004000)

Bit 2

#define RI_ICR_IC4Z_3   ((uint32_t)0x00008000)

Bit 3

#define RI_ICR_TIM   ((uint32_t)0x00030000)

TIM[3:0] bits (Timers select bits)

#define RI_ICR_TIM_0   ((uint32_t)0x00010000)

Bit 0

#define RI_ICR_TIM_1   ((uint32_t)0x00020000)

Bit 1

#define RI_ICR_IC1   ((uint32_t)0x00040000)

Input capture 1

#define RI_ICR_IC2   ((uint32_t)0x00080000)

Input capture 2

#define RI_ICR_IC3   ((uint32_t)0x00100000)

Input capture 3

#define RI_ICR_IC4   ((uint32_t)0x00200000)

Input capture 4

#define RI_ASCR1_CH   ((uint32_t)0x03FCFFFF)

AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits)

#define RI_ASCR1_CH_0   ((uint32_t)0x00000001)

Bit 0

#define RI_ASCR1_CH_1   ((uint32_t)0x00000002)

Bit 1

#define RI_ASCR1_CH_2   ((uint32_t)0x00000004)

Bit 2

#define RI_ASCR1_CH_3   ((uint32_t)0x00000008)

Bit 3

#define RI_ASCR1_CH_4   ((uint32_t)0x00000010)

Bit 4

#define RI_ASCR1_CH_5   ((uint32_t)0x00000020)

Bit 5

#define RI_ASCR1_CH_6   ((uint32_t)0x00000040)

Bit 6

#define RI_ASCR1_CH_7   ((uint32_t)0x00000080)

Bit 7

#define RI_ASCR1_CH_8   ((uint32_t)0x00000100)

Bit 8

#define RI_ASCR1_CH_9   ((uint32_t)0x00000200)

Bit 9

#define RI_ASCR1_CH_10   ((uint32_t)0x00000400)

Bit 10

#define RI_ASCR1_CH_11   ((uint32_t)0x00000800)

Bit 11

#define RI_ASCR1_CH_12   ((uint32_t)0x00001000)

Bit 12

#define RI_ASCR1_CH_13   ((uint32_t)0x00002000)

Bit 13

#define RI_ASCR1_CH_14   ((uint32_t)0x00004000)

Bit 14

#define RI_ASCR1_CH_15   ((uint32_t)0x00008000)

Bit 15

#define RI_ASCR1_CH_31   ((uint32_t)0x00010000)

Bit 16

#define RI_ASCR1_CH_18   ((uint32_t)0x00040000)

Bit 18

#define RI_ASCR1_CH_19   ((uint32_t)0x00080000)

Bit 19

#define RI_ASCR1_CH_20   ((uint32_t)0x00100000)

Bit 20

#define RI_ASCR1_CH_21   ((uint32_t)0x00200000)

Bit 21

#define RI_ASCR1_CH_22   ((uint32_t)0x00400000)

Bit 22

#define RI_ASCR1_CH_23   ((uint32_t)0x00800000)

Bit 23

#define RI_ASCR1_CH_24   ((uint32_t)0x01000000)

Bit 24

#define RI_ASCR1_CH_25   ((uint32_t)0x02000000)

Bit 25

#define RI_ASCR1_VCOMP   ((uint32_t)0x04000000)

ADC analog switch selection for internal node to COMP1

#define RI_ASCR1_CH_27   ((uint32_t)0x00400000)

Bit 27

#define RI_ASCR1_CH_28   ((uint32_t)0x00800000)

Bit 28

#define RI_ASCR1_CH_29   ((uint32_t)0x01000000)

Bit 29

#define RI_ASCR1_CH_30   ((uint32_t)0x02000000)

Bit 30

#define RI_ASCR1_SCM   ((uint32_t)0x80000000)

I/O Switch control mode

#define RI_ASCR2_GR10_1   ((uint32_t)0x00000001)

GR10-1 selection bit

#define RI_ASCR2_GR10_2   ((uint32_t)0x00000002)

GR10-2 selection bit

#define RI_ASCR2_GR10_3   ((uint32_t)0x00000004)

GR10-3 selection bit

#define RI_ASCR2_GR10_4   ((uint32_t)0x00000008)

GR10-4 selection bit

#define RI_ASCR2_GR6_1   ((uint32_t)0x00000010)

GR6-1 selection bit

#define RI_ASCR2_GR6_2   ((uint32_t)0x00000020)

GR6-2 selection bit

#define RI_ASCR2_GR5_1   ((uint32_t)0x00000040)

GR5-1 selection bit

#define RI_ASCR2_GR5_2   ((uint32_t)0x00000080)

GR5-2 selection bit

#define RI_ASCR2_GR5_3   ((uint32_t)0x00000100)

GR5-3 selection bit

#define RI_ASCR2_GR4_1   ((uint32_t)0x00000200)

GR4-1 selection bit

#define RI_ASCR2_GR4_2   ((uint32_t)0x00000400)

GR4-2 selection bit

#define RI_ASCR2_GR4_3   ((uint32_t)0x00000800)

GR4-3 selection bit

#define RI_ASCR2_GR4_4   ((uint32_t)0x00008000)

GR4-4 selection bit

#define RI_ASCR2_CH0b   ((uint32_t)0x00010000)

CH0b selection bit

#define RI_ASCR2_CH1b   ((uint32_t)0x00020000)

CH1b selection bit

#define RI_ASCR2_CH2b   ((uint32_t)0x00040000)

CH2b selection bit

#define RI_ASCR2_CH3b   ((uint32_t)0x00080000)

CH3b selection bit

#define RI_ASCR2_CH6b   ((uint32_t)0x00100000)

CH6b selection bit

#define RI_ASCR2_CH7b   ((uint32_t)0x00200000)

CH7b selection bit

#define RI_ASCR2_CH8b   ((uint32_t)0x00400000)

CH8b selection bit

#define RI_ASCR2_CH9b   ((uint32_t)0x00800000)

CH9b selection bit

#define RI_ASCR2_CH10b   ((uint32_t)0x01000000)

CH10b selection bit

#define RI_ASCR2_CH11b   ((uint32_t)0x02000000)

CH11b selection bit

#define RI_ASCR2_CH12b   ((uint32_t)0x04000000)

CH12b selection bit

#define RI_ASCR2_GR6_3   ((uint32_t)0x08000000)

GR6-3 selection bit

#define RI_ASCR2_GR6_4   ((uint32_t)0x10000000)

GR6-4 selection bit

#define RI_ASCR2_GR5_4   ((uint32_t)0x20000000)

GR5-4 selection bit

#define RI_HYSCR1_PA   ((uint32_t)0x0000FFFF)

PA[15:0] Port A Hysteresis selection

#define RI_HYSCR1_PA_0   ((uint32_t)0x00000001)

Bit 0

#define RI_HYSCR1_PA_1   ((uint32_t)0x00000002)

Bit 1

#define RI_HYSCR1_PA_2   ((uint32_t)0x00000004)

Bit 2

#define RI_HYSCR1_PA_3   ((uint32_t)0x00000008)

Bit 3

#define RI_HYSCR1_PA_4   ((uint32_t)0x00000010)

Bit 4

#define RI_HYSCR1_PA_5   ((uint32_t)0x00000020)

Bit 5

#define RI_HYSCR1_PA_6   ((uint32_t)0x00000040)

Bit 6

#define RI_HYSCR1_PA_7   ((uint32_t)0x00000080)

Bit 7

#define RI_HYSCR1_PA_8   ((uint32_t)0x00000100)

Bit 8

#define RI_HYSCR1_PA_9   ((uint32_t)0x00000200)

Bit 9

#define RI_HYSCR1_PA_10   ((uint32_t)0x00000400)

Bit 10

#define RI_HYSCR1_PA_11   ((uint32_t)0x00000800)

Bit 11

#define RI_HYSCR1_PA_12   ((uint32_t)0x00001000)

Bit 12

#define RI_HYSCR1_PA_13   ((uint32_t)0x00002000)

Bit 13

#define RI_HYSCR1_PA_14   ((uint32_t)0x00004000)

Bit 14

#define RI_HYSCR1_PA_15   ((uint32_t)0x00008000)

Bit 15

#define RI_HYSCR1_PB   ((uint32_t)0xFFFF0000)

PB[15:0] Port B Hysteresis selection

#define RI_HYSCR1_PB_0   ((uint32_t)0x00010000)

Bit 0

#define RI_HYSCR1_PB_1   ((uint32_t)0x00020000)

Bit 1

#define RI_HYSCR1_PB_2   ((uint32_t)0x00040000)

Bit 2

#define RI_HYSCR1_PB_3   ((uint32_t)0x00080000)

Bit 3

#define RI_HYSCR1_PB_4   ((uint32_t)0x00100000)

Bit 4

#define RI_HYSCR1_PB_5   ((uint32_t)0x00200000)

Bit 5

#define RI_HYSCR1_PB_6   ((uint32_t)0x00400000)

Bit 6

#define RI_HYSCR1_PB_7   ((uint32_t)0x00800000)

Bit 7

#define RI_HYSCR1_PB_8   ((uint32_t)0x01000000)

Bit 8

#define RI_HYSCR1_PB_9   ((uint32_t)0x02000000)

Bit 9

#define RI_HYSCR1_PB_10   ((uint32_t)0x04000000)

Bit 10

#define RI_HYSCR1_PB_11   ((uint32_t)0x08000000)

Bit 11

#define RI_HYSCR1_PB_12   ((uint32_t)0x10000000)

Bit 12

#define RI_HYSCR1_PB_13   ((uint32_t)0x20000000)

Bit 13

#define RI_HYSCR1_PB_14   ((uint32_t)0x40000000)

Bit 14

#define RI_HYSCR1_PB_15   ((uint32_t)0x80000000)

Bit 15

#define RI_HYSCR2_PC   ((uint32_t)0x0000FFFF)

PC[15:0] Port C Hysteresis selection

#define RI_HYSCR2_PC_0   ((uint32_t)0x00000001)

Bit 0

#define RI_HYSCR2_PC_1   ((uint32_t)0x00000002)

Bit 1

#define RI_HYSCR2_PC_2   ((uint32_t)0x00000004)

Bit 2

#define RI_HYSCR2_PC_3   ((uint32_t)0x00000008)

Bit 3

#define RI_HYSCR2_PC_4   ((uint32_t)0x00000010)

Bit 4

#define RI_HYSCR2_PC_5   ((uint32_t)0x00000020)

Bit 5

#define RI_HYSCR2_PC_6   ((uint32_t)0x00000040)

Bit 6

#define RI_HYSCR2_PC_7   ((uint32_t)0x00000080)

Bit 7

#define RI_HYSCR2_PC_8   ((uint32_t)0x00000100)

Bit 8

#define RI_HYSCR2_PC_9   ((uint32_t)0x00000200)

Bit 9

#define RI_HYSCR2_PC_10   ((uint32_t)0x00000400)

Bit 10

#define RI_HYSCR2_PC_11   ((uint32_t)0x00000800)

Bit 11

#define RI_HYSCR2_PC_12   ((uint32_t)0x00001000)

Bit 12

#define RI_HYSCR2_PC_13   ((uint32_t)0x00002000)

Bit 13

#define RI_HYSCR2_PC_14   ((uint32_t)0x00004000)

Bit 14

#define RI_HYSCR2_PC_15   ((uint32_t)0x00008000)

Bit 15

#define RI_HYSCR2_PD   ((uint32_t)0xFFFF0000)

PD[15:0] Port D Hysteresis selection

#define RI_HYSCR2_PD_0   ((uint32_t)0x00010000)

Bit 0

#define RI_HYSCR2_PD_1   ((uint32_t)0x00020000)

Bit 1

#define RI_HYSCR2_PD_2   ((uint32_t)0x00040000)

Bit 2

#define RI_HYSCR2_PD_3   ((uint32_t)0x00080000)

Bit 3

#define RI_HYSCR2_PD_4   ((uint32_t)0x00100000)

Bit 4

#define RI_HYSCR2_PD_5   ((uint32_t)0x00200000)

Bit 5

#define RI_HYSCR2_PD_6   ((uint32_t)0x00400000)

Bit 6

#define RI_HYSCR2_PD_7   ((uint32_t)0x00800000)

Bit 7

#define RI_HYSCR2_PD_8   ((uint32_t)0x01000000)

Bit 8

#define RI_HYSCR2_PD_9   ((uint32_t)0x02000000)

Bit 9

#define RI_HYSCR2_PD_10   ((uint32_t)0x04000000)

Bit 10

#define RI_HYSCR2_PD_11   ((uint32_t)0x08000000)

Bit 11

#define RI_HYSCR2_PD_12   ((uint32_t)0x10000000)

Bit 12

#define RI_HYSCR2_PD_13   ((uint32_t)0x20000000)

Bit 13

#define RI_HYSCR2_PD_14   ((uint32_t)0x40000000)

Bit 14

#define RI_HYSCR2_PD_15   ((uint32_t)0x80000000)

Bit 15

#define RI_HYSCR2_PE   ((uint32_t)0x0000FFFF)

PE[15:0] Port E Hysteresis selection

#define RI_HYSCR2_PE_0   ((uint32_t)0x00000001)

Bit 0

#define RI_HYSCR2_PE_1   ((uint32_t)0x00000002)

Bit 1

#define RI_HYSCR2_PE_2   ((uint32_t)0x00000004)

Bit 2

#define RI_HYSCR2_PE_3   ((uint32_t)0x00000008)

Bit 3

#define RI_HYSCR2_PE_4   ((uint32_t)0x00000010)

Bit 4

#define RI_HYSCR2_PE_5   ((uint32_t)0x00000020)

Bit 5

#define RI_HYSCR2_PE_6   ((uint32_t)0x00000040)

Bit 6

#define RI_HYSCR2_PE_7   ((uint32_t)0x00000080)

Bit 7

#define RI_HYSCR2_PE_8   ((uint32_t)0x00000100)

Bit 8

#define RI_HYSCR2_PE_9   ((uint32_t)0x00000200)

Bit 9

#define RI_HYSCR2_PE_10   ((uint32_t)0x00000400)

Bit 10

#define RI_HYSCR2_PE_11   ((uint32_t)0x00000800)

Bit 11

#define RI_HYSCR2_PE_12   ((uint32_t)0x00001000)

Bit 12

#define RI_HYSCR2_PE_13   ((uint32_t)0x00002000)

Bit 13

#define RI_HYSCR2_PE_14   ((uint32_t)0x00004000)

Bit 14

#define RI_HYSCR2_PE_15   ((uint32_t)0x00008000)

Bit 15

#define RI_HYSCR3_PF   ((uint32_t)0xFFFF0000)

PF[15:0] Port F Hysteresis selection

#define RI_HYSCR3_PF_0   ((uint32_t)0x00010000)

Bit 0

#define RI_HYSCR3_PF_1   ((uint32_t)0x00020000)

Bit 1

#define RI_HYSCR3_PF_2   ((uint32_t)0x00040000)

Bit 2

#define RI_HYSCR3_PF_3   ((uint32_t)0x00080000)

Bit 3

#define RI_HYSCR3_PF_4   ((uint32_t)0x00100000)

Bit 4

#define RI_HYSCR3_PF_5   ((uint32_t)0x00200000)

Bit 5

#define RI_HYSCR3_PF_6   ((uint32_t)0x00400000)

Bit 6

#define RI_HYSCR3_PF_7   ((uint32_t)0x00800000)

Bit 7

#define RI_HYSCR3_PF_8   ((uint32_t)0x01000000)

Bit 8

#define RI_HYSCR3_PF_9   ((uint32_t)0x02000000)

Bit 9

#define RI_HYSCR3_PF_10   ((uint32_t)0x04000000)

Bit 10

#define RI_HYSCR3_PF_11   ((uint32_t)0x08000000)

Bit 11

#define RI_HYSCR3_PF_12   ((uint32_t)0x10000000)

Bit 12

#define RI_HYSCR3_PF_13   ((uint32_t)0x20000000)

Bit 13

#define RI_HYSCR3_PF_14   ((uint32_t)0x40000000)

Bit 14

#define RI_HYSCR3_PF_15   ((uint32_t)0x80000000)

Bit 15

#define RI_HYSCR4_PG   ((uint32_t)0x0000FFFF)

PG[15:0] Port G Hysteresis selection

#define RI_HYSCR4_PG_0   ((uint32_t)0x00000001)

Bit 0

#define RI_HYSCR4_PG_1   ((uint32_t)0x00000002)

Bit 1

#define RI_HYSCR4_PG_2   ((uint32_t)0x00000004)

Bit 2

#define RI_HYSCR4_PG_3   ((uint32_t)0x00000008)

Bit 3

#define RI_HYSCR4_PG_4   ((uint32_t)0x00000010)

Bit 4

#define RI_HYSCR4_PG_5   ((uint32_t)0x00000020)

Bit 5

#define RI_HYSCR4_PG_6   ((uint32_t)0x00000040)

Bit 6

#define RI_HYSCR4_PG_7   ((uint32_t)0x00000080)

Bit 7

#define RI_HYSCR4_PG_8   ((uint32_t)0x00000100)

Bit 8

#define RI_HYSCR4_PG_9   ((uint32_t)0x00000200)

Bit 9

#define RI_HYSCR4_PG_10   ((uint32_t)0x00000400)

Bit 10

#define RI_HYSCR4_PG_11   ((uint32_t)0x00000800)

Bit 11

#define RI_HYSCR4_PG_12   ((uint32_t)0x00001000)

Bit 12

#define RI_HYSCR4_PG_13   ((uint32_t)0x00002000)

Bit 13

#define RI_HYSCR4_PG_14   ((uint32_t)0x00004000)

Bit 14

#define RI_HYSCR4_PG_15   ((uint32_t)0x00008000)

Bit 15

#define TIM_CR1_CEN   ((uint16_t)0x0001)

Counter enable

#define TIM_CR1_UDIS   ((uint16_t)0x0002)

Update disable

#define TIM_CR1_URS   ((uint16_t)0x0004)

Update request source

#define TIM_CR1_OPM   ((uint16_t)0x0008)

One pulse mode

#define TIM_CR1_DIR   ((uint16_t)0x0010)

Direction

#define TIM_CR1_CMS   ((uint16_t)0x0060)

CMS[1:0] bits (Center-aligned mode selection)

#define TIM_CR1_CMS_0   ((uint16_t)0x0020)

Bit 0

#define TIM_CR1_CMS_1   ((uint16_t)0x0040)

Bit 1

#define TIM_CR1_ARPE   ((uint16_t)0x0080)

Auto-reload preload enable

#define TIM_CR1_CKD   ((uint16_t)0x0300)

CKD[1:0] bits (clock division)

#define TIM_CR1_CKD_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CR1_CKD_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CR2_CCDS   ((uint16_t)0x0008)

Capture/Compare DMA Selection

#define TIM_CR2_MMS   ((uint16_t)0x0070)

MMS[2:0] bits (Master Mode Selection)

#define TIM_CR2_MMS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CR2_MMS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CR2_MMS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CR2_TI1S   ((uint16_t)0x0080)

TI1 Selection

#define TIM_SMCR_SMS   ((uint16_t)0x0007)

SMS[2:0] bits (Slave mode selection)

#define TIM_SMCR_SMS_0   ((uint16_t)0x0001)

Bit 0

#define TIM_SMCR_SMS_1   ((uint16_t)0x0002)

Bit 1

#define TIM_SMCR_SMS_2   ((uint16_t)0x0004)

Bit 2

#define TIM_SMCR_OCCS   ((uint16_t)0x0008)

OCCS bits (OCref Clear Selection)

#define TIM_SMCR_TS   ((uint16_t)0x0070)

TS[2:0] bits (Trigger selection)

#define TIM_SMCR_TS_0   ((uint16_t)0x0010)

Bit 0

#define TIM_SMCR_TS_1   ((uint16_t)0x0020)

Bit 1

#define TIM_SMCR_TS_2   ((uint16_t)0x0040)

Bit 2

#define TIM_SMCR_MSM   ((uint16_t)0x0080)

Master/slave mode

#define TIM_SMCR_ETF   ((uint16_t)0x0F00)

ETF[3:0] bits (External trigger filter)

#define TIM_SMCR_ETF_0   ((uint16_t)0x0100)

Bit 0

#define TIM_SMCR_ETF_1   ((uint16_t)0x0200)

Bit 1

#define TIM_SMCR_ETF_2   ((uint16_t)0x0400)

Bit 2

#define TIM_SMCR_ETF_3   ((uint16_t)0x0800)

Bit 3

#define TIM_SMCR_ETPS   ((uint16_t)0x3000)

ETPS[1:0] bits (External trigger prescaler)

#define TIM_SMCR_ETPS_0   ((uint16_t)0x1000)

Bit 0

#define TIM_SMCR_ETPS_1   ((uint16_t)0x2000)

Bit 1

#define TIM_SMCR_ECE   ((uint16_t)0x4000)

External clock enable

#define TIM_SMCR_ETP   ((uint16_t)0x8000)

External trigger polarity

#define TIM_DIER_UIE   ((uint16_t)0x0001)

Update interrupt enable

#define TIM_DIER_CC1IE   ((uint16_t)0x0002)

Capture/Compare 1 interrupt enable

#define TIM_DIER_CC2IE   ((uint16_t)0x0004)

Capture/Compare 2 interrupt enable

#define TIM_DIER_CC3IE   ((uint16_t)0x0008)

Capture/Compare 3 interrupt enable

#define TIM_DIER_CC4IE   ((uint16_t)0x0010)

Capture/Compare 4 interrupt enable

#define TIM_DIER_TIE   ((uint16_t)0x0040)

Trigger interrupt enable

#define TIM_DIER_UDE   ((uint16_t)0x0100)

Update DMA request enable

#define TIM_DIER_CC1DE   ((uint16_t)0x0200)

Capture/Compare 1 DMA request enable

#define TIM_DIER_CC2DE   ((uint16_t)0x0400)

Capture/Compare 2 DMA request enable

#define TIM_DIER_CC3DE   ((uint16_t)0x0800)

Capture/Compare 3 DMA request enable

#define TIM_DIER_CC4DE   ((uint16_t)0x1000)

Capture/Compare 4 DMA request enable

#define TIM_DIER_TDE   ((uint16_t)0x4000)

Trigger DMA request enable

#define TIM_SR_UIF   ((uint16_t)0x0001)

Update interrupt Flag

#define TIM_SR_CC1IF   ((uint16_t)0x0002)

Capture/Compare 1 interrupt Flag

#define TIM_SR_CC2IF   ((uint16_t)0x0004)

Capture/Compare 2 interrupt Flag

#define TIM_SR_CC3IF   ((uint16_t)0x0008)

Capture/Compare 3 interrupt Flag

#define TIM_SR_CC4IF   ((uint16_t)0x0010)

Capture/Compare 4 interrupt Flag

#define TIM_SR_TIF   ((uint16_t)0x0040)

Trigger interrupt Flag

#define TIM_SR_CC1OF   ((uint16_t)0x0200)

Capture/Compare 1 Overcapture Flag

#define TIM_SR_CC2OF   ((uint16_t)0x0400)

Capture/Compare 2 Overcapture Flag

#define TIM_SR_CC3OF   ((uint16_t)0x0800)

Capture/Compare 3 Overcapture Flag

#define TIM_SR_CC4OF   ((uint16_t)0x1000)

Capture/Compare 4 Overcapture Flag

#define TIM_EGR_UG   ((uint8_t)0x01)

Update Generation

#define TIM_EGR_CC1G   ((uint8_t)0x02)

Capture/Compare 1 Generation

#define TIM_EGR_CC2G   ((uint8_t)0x04)

Capture/Compare 2 Generation

#define TIM_EGR_CC3G   ((uint8_t)0x08)

Capture/Compare 3 Generation

#define TIM_EGR_CC4G   ((uint8_t)0x10)

Capture/Compare 4 Generation

#define TIM_EGR_TG   ((uint8_t)0x40)

Trigger Generation

#define TIM_CCMR1_CC1S   ((uint16_t)0x0003)

CC1S[1:0] bits (Capture/Compare 1 Selection)

#define TIM_CCMR1_CC1S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR1_CC1S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR1_OC1FE   ((uint16_t)0x0004)

Output Compare 1 Fast enable

#define TIM_CCMR1_OC1PE   ((uint16_t)0x0008)

Output Compare 1 Preload enable

#define TIM_CCMR1_OC1M   ((uint16_t)0x0070)

OC1M[2:0] bits (Output Compare 1 Mode)

#define TIM_CCMR1_OC1M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_OC1M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_OC1M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_OC1CE   ((uint16_t)0x0080)

Output Compare 1Clear Enable

#define TIM_CCMR1_CC2S   ((uint16_t)0x0300)

CC2S[1:0] bits (Capture/Compare 2 Selection)

#define TIM_CCMR1_CC2S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR1_CC2S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR1_OC2FE   ((uint16_t)0x0400)

Output Compare 2 Fast enable

#define TIM_CCMR1_OC2PE   ((uint16_t)0x0800)

Output Compare 2 Preload enable

#define TIM_CCMR1_OC2M   ((uint16_t)0x7000)

OC2M[2:0] bits (Output Compare 2 Mode)

#define TIM_CCMR1_OC2M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_OC2M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_OC2M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_OC2CE   ((uint16_t)0x8000)

Output Compare 2 Clear Enable

#define TIM_CCMR1_IC1PSC   ((uint16_t)0x000C)

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

#define TIM_CCMR1_IC1PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR1_IC1PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR1_IC1F   ((uint16_t)0x00F0)

IC1F[3:0] bits (Input Capture 1 Filter)

#define TIM_CCMR1_IC1F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR1_IC1F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR1_IC1F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR1_IC1F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR1_IC2PSC   ((uint16_t)0x0C00)

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

#define TIM_CCMR1_IC2PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR1_IC2PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR1_IC2F   ((uint16_t)0xF000)

IC2F[3:0] bits (Input Capture 2 Filter)

#define TIM_CCMR1_IC2F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR1_IC2F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR1_IC2F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR1_IC2F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCMR2_CC3S   ((uint16_t)0x0003)

CC3S[1:0] bits (Capture/Compare 3 Selection)

#define TIM_CCMR2_CC3S_0   ((uint16_t)0x0001)

Bit 0

#define TIM_CCMR2_CC3S_1   ((uint16_t)0x0002)

Bit 1

#define TIM_CCMR2_OC3FE   ((uint16_t)0x0004)

Output Compare 3 Fast enable

#define TIM_CCMR2_OC3PE   ((uint16_t)0x0008)

Output Compare 3 Preload enable

#define TIM_CCMR2_OC3M   ((uint16_t)0x0070)

OC3M[2:0] bits (Output Compare 3 Mode)

#define TIM_CCMR2_OC3M_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_OC3M_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_OC3M_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_OC3CE   ((uint16_t)0x0080)

Output Compare 3 Clear Enable

#define TIM_CCMR2_CC4S   ((uint16_t)0x0300)

CC4S[1:0] bits (Capture/Compare 4 Selection)

#define TIM_CCMR2_CC4S_0   ((uint16_t)0x0100)

Bit 0

#define TIM_CCMR2_CC4S_1   ((uint16_t)0x0200)

Bit 1

#define TIM_CCMR2_OC4FE   ((uint16_t)0x0400)

Output Compare 4 Fast enable

#define TIM_CCMR2_OC4PE   ((uint16_t)0x0800)

Output Compare 4 Preload enable

#define TIM_CCMR2_OC4M   ((uint16_t)0x7000)

OC4M[2:0] bits (Output Compare 4 Mode)

#define TIM_CCMR2_OC4M_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_OC4M_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_OC4M_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_OC4CE   ((uint16_t)0x8000)

Output Compare 4 Clear Enable

#define TIM_CCMR2_IC3PSC   ((uint16_t)0x000C)

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

#define TIM_CCMR2_IC3PSC_0   ((uint16_t)0x0004)

Bit 0

#define TIM_CCMR2_IC3PSC_1   ((uint16_t)0x0008)

Bit 1

#define TIM_CCMR2_IC3F   ((uint16_t)0x00F0)

IC3F[3:0] bits (Input Capture 3 Filter)

#define TIM_CCMR2_IC3F_0   ((uint16_t)0x0010)

Bit 0

#define TIM_CCMR2_IC3F_1   ((uint16_t)0x0020)

Bit 1

#define TIM_CCMR2_IC3F_2   ((uint16_t)0x0040)

Bit 2

#define TIM_CCMR2_IC3F_3   ((uint16_t)0x0080)

Bit 3

#define TIM_CCMR2_IC4PSC   ((uint16_t)0x0C00)

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

#define TIM_CCMR2_IC4PSC_0   ((uint16_t)0x0400)

Bit 0

#define TIM_CCMR2_IC4PSC_1   ((uint16_t)0x0800)

Bit 1

#define TIM_CCMR2_IC4F   ((uint16_t)0xF000)

IC4F[3:0] bits (Input Capture 4 Filter)

#define TIM_CCMR2_IC4F_0   ((uint16_t)0x1000)

Bit 0

#define TIM_CCMR2_IC4F_1   ((uint16_t)0x2000)

Bit 1

#define TIM_CCMR2_IC4F_2   ((uint16_t)0x4000)

Bit 2

#define TIM_CCMR2_IC4F_3   ((uint16_t)0x8000)

Bit 3

#define TIM_CCER_CC1E   ((uint16_t)0x0001)

Capture/Compare 1 output enable

#define TIM_CCER_CC1P   ((uint16_t)0x0002)

Capture/Compare 1 output Polarity

#define TIM_CCER_CC1NP   ((uint16_t)0x0008)

Capture/Compare 1 Complementary output Polarity

#define TIM_CCER_CC2E   ((uint16_t)0x0010)

Capture/Compare 2 output enable

#define TIM_CCER_CC2P   ((uint16_t)0x0020)

Capture/Compare 2 output Polarity

#define TIM_CCER_CC2NP   ((uint16_t)0x0080)

Capture/Compare 2 Complementary output Polarity

#define TIM_CCER_CC3E   ((uint16_t)0x0100)

Capture/Compare 3 output enable

#define TIM_CCER_CC3P   ((uint16_t)0x0200)

Capture/Compare 3 output Polarity

#define TIM_CCER_CC3NP   ((uint16_t)0x0800)

Capture/Compare 3 Complementary output Polarity

#define TIM_CCER_CC4E   ((uint16_t)0x1000)

Capture/Compare 4 output enable

#define TIM_CCER_CC4P   ((uint16_t)0x2000)

Capture/Compare 4 output Polarity

#define TIM_CCER_CC4NP   ((uint16_t)0x8000)

Capture/Compare 4 Complementary output Polarity

#define TIM_CNT_CNT   ((uint16_t)0xFFFF)

Counter Value

#define TIM_PSC_PSC   ((uint16_t)0xFFFF)

Prescaler Value

#define TIM_ARR_ARR   ((uint16_t)0xFFFF)

actual auto-reload Value

#define TIM_CCR1_CCR1   ((uint16_t)0xFFFF)

Capture/Compare 1 Value

#define TIM_CCR2_CCR2   ((uint16_t)0xFFFF)

Capture/Compare 2 Value

#define TIM_CCR3_CCR3   ((uint16_t)0xFFFF)

Capture/Compare 3 Value

#define TIM_CCR4_CCR4   ((uint16_t)0xFFFF)

Capture/Compare 4 Value

#define TIM_DCR_DBA   ((uint16_t)0x001F)

DBA[4:0] bits (DMA Base Address)

#define TIM_DCR_DBA_0   ((uint16_t)0x0001)

Bit 0

#define TIM_DCR_DBA_1   ((uint16_t)0x0002)

Bit 1

#define TIM_DCR_DBA_2   ((uint16_t)0x0004)

Bit 2

#define TIM_DCR_DBA_3   ((uint16_t)0x0008)

Bit 3

#define TIM_DCR_DBA_4   ((uint16_t)0x0010)

Bit 4

#define TIM_DCR_DBL   ((uint16_t)0x1F00)

DBL[4:0] bits (DMA Burst Length)

#define TIM_DCR_DBL_0   ((uint16_t)0x0100)

Bit 0

#define TIM_DCR_DBL_1   ((uint16_t)0x0200)

Bit 1

#define TIM_DCR_DBL_2   ((uint16_t)0x0400)

Bit 2

#define TIM_DCR_DBL_3   ((uint16_t)0x0800)

Bit 3

#define TIM_DCR_DBL_4   ((uint16_t)0x1000)

Bit 4

#define TIM_DMAR_DMAB   ((uint16_t)0xFFFF)

DMA register for burst accesses

#define TIM_OR_TI1RMP   ((uint16_t)0x0003)

Option register for TI1 Remapping

#define TIM_OR_TI1RMP_0   ((uint16_t)0x0001)

Bit 0

#define TIM_OR_TI1RMP_1   ((uint16_t)0x0002)

Bit 1

#define USART_SR_PE   ((uint16_t)0x0001)

Parity Error

#define USART_SR_FE   ((uint16_t)0x0002)

Framing Error

#define USART_SR_NE   ((uint16_t)0x0004)

Noise Error Flag

#define USART_SR_ORE   ((uint16_t)0x0008)

OverRun Error

#define USART_SR_IDLE   ((uint16_t)0x0010)

IDLE line detected

#define USART_SR_RXNE   ((uint16_t)0x0020)

Read Data Register Not Empty

#define USART_SR_TC   ((uint16_t)0x0040)

Transmission Complete

#define USART_SR_TXE   ((uint16_t)0x0080)

Transmit Data Register Empty

#define USART_SR_LBD   ((uint16_t)0x0100)

LIN Break Detection Flag

#define USART_SR_CTS   ((uint16_t)0x0200)

CTS Flag

#define USART_DR_DR   ((uint16_t)0x01FF)

Data value

#define USART_BRR_DIV_FRACTION   ((uint16_t)0x000F)

Fraction of USARTDIV

#define USART_BRR_DIV_MANTISSA   ((uint16_t)0xFFF0)

Mantissa of USARTDIV

#define USART_CR1_SBK   ((uint16_t)0x0001)

Send Break

#define USART_CR1_RWU   ((uint16_t)0x0002)

Receiver wakeup

#define USART_CR1_RE   ((uint16_t)0x0004)

Receiver Enable

#define USART_CR1_TE   ((uint16_t)0x0008)

Transmitter Enable

#define USART_CR1_IDLEIE   ((uint16_t)0x0010)

IDLE Interrupt Enable

#define USART_CR1_RXNEIE   ((uint16_t)0x0020)

RXNE Interrupt Enable

#define USART_CR1_TCIE   ((uint16_t)0x0040)

Transmission Complete Interrupt Enable

#define USART_CR1_TXEIE   ((uint16_t)0x0080)

PE Interrupt Enable

#define USART_CR1_PEIE   ((uint16_t)0x0100)

PE Interrupt Enable

#define USART_CR1_PS   ((uint16_t)0x0200)

Parity Selection

#define USART_CR1_PCE   ((uint16_t)0x0400)

Parity Control Enable

#define USART_CR1_WAKE   ((uint16_t)0x0800)

Wakeup method

#define USART_CR1_M   ((uint16_t)0x1000)

Word length

#define USART_CR1_UE   ((uint16_t)0x2000)

USART Enable

#define USART_CR1_OVER8   ((uint16_t)0x8000)

Oversampling by 8-bit mode

#define USART_CR2_ADD   ((uint16_t)0x000F)

Address of the USART node

#define USART_CR2_LBDL   ((uint16_t)0x0020)

LIN Break Detection Length

#define USART_CR2_LBDIE   ((uint16_t)0x0040)

LIN Break Detection Interrupt Enable

#define USART_CR2_LBCL   ((uint16_t)0x0100)

Last Bit Clock pulse

#define USART_CR2_CPHA   ((uint16_t)0x0200)

Clock Phase

#define USART_CR2_CPOL   ((uint16_t)0x0400)

Clock Polarity

#define USART_CR2_CLKEN   ((uint16_t)0x0800)

Clock Enable

#define USART_CR2_STOP   ((uint16_t)0x3000)

STOP[1:0] bits (STOP bits)

#define USART_CR2_STOP_0   ((uint16_t)0x1000)

Bit 0

#define USART_CR2_STOP_1   ((uint16_t)0x2000)

Bit 1

#define USART_CR2_LINEN   ((uint16_t)0x4000)

LIN mode enable

#define USART_CR3_EIE   ((uint16_t)0x0001)

Error Interrupt Enable

#define USART_CR3_IREN   ((uint16_t)0x0002)

IrDA mode Enable

#define USART_CR3_IRLP   ((uint16_t)0x0004)

IrDA Low-Power

#define USART_CR3_HDSEL   ((uint16_t)0x0008)

Half-Duplex Selection

#define USART_CR3_NACK   ((uint16_t)0x0010)

Smartcard NACK enable

#define USART_CR3_SCEN   ((uint16_t)0x0020)

Smartcard mode enable

#define USART_CR3_DMAR   ((uint16_t)0x0040)

DMA Enable Receiver

#define USART_CR3_DMAT   ((uint16_t)0x0080)

DMA Enable Transmitter

#define USART_CR3_RTSE   ((uint16_t)0x0100)

RTS Enable

#define USART_CR3_CTSE   ((uint16_t)0x0200)

CTS Enable

#define USART_CR3_CTSIE   ((uint16_t)0x0400)

CTS Interrupt Enable

#define USART_CR3_ONEBIT   ((uint16_t)0x0800)

One sample bit method enable

#define USART_GTPR_PSC   ((uint16_t)0x00FF)

PSC[7:0] bits (Prescaler value)

#define USART_GTPR_PSC_0   ((uint16_t)0x0001)

Bit 0

#define USART_GTPR_PSC_1   ((uint16_t)0x0002)

Bit 1

#define USART_GTPR_PSC_2   ((uint16_t)0x0004)

Bit 2

#define USART_GTPR_PSC_3   ((uint16_t)0x0008)

Bit 3

#define USART_GTPR_PSC_4   ((uint16_t)0x0010)

Bit 4

#define USART_GTPR_PSC_5   ((uint16_t)0x0020)

Bit 5

#define USART_GTPR_PSC_6   ((uint16_t)0x0040)

Bit 6

#define USART_GTPR_PSC_7   ((uint16_t)0x0080)

Bit 7

#define USART_GTPR_GT   ((uint16_t)0xFF00)

Guard time value

#define USB_EP0R_EA   ((uint16_t)0x000F)

<Endpoint-specific registers Endpoint Address

#define USB_EP0R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP0R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP0R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP0R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP0R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP0R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP0R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP0R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP0R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP0R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP0R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP0R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP0R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP0R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP0R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP1R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP1R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP1R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP1R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP1R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP1R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP1R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP1R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP1R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP1R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP1R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP1R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP1R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP1R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP1R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP1R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP2R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP2R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP2R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP2R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP2R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP2R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP2R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP2R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP2R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP2R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP2R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP2R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP2R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP2R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP2R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP2R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP3R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP3R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP3R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP3R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP3R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP3R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP3R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP3R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP3R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP3R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP3R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP3R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP3R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP3R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP3R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP3R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP4R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP4R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP4R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP4R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP4R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP4R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP4R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP4R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP4R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP4R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP4R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP4R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP4R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP4R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP4R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP4R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP5R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP5R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP5R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP5R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP5R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP5R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP5R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP5R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP5R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP5R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP5R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP5R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP5R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP5R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP5R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP5R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP6R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP6R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP6R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP6R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP6R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP6R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP6R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP6R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP6R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP6R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP6R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP6R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP6R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP6R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP6R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP6R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception

#define USB_EP7R_EA   ((uint16_t)0x000F)

Endpoint Address

#define USB_EP7R_STAT_TX   ((uint16_t)0x0030)

STAT_TX[1:0] bits (Status bits, for transmission transfers)

#define USB_EP7R_STAT_TX_0   ((uint16_t)0x0010)

Bit 0

#define USB_EP7R_STAT_TX_1   ((uint16_t)0x0020)

Bit 1

#define USB_EP7R_DTOG_TX   ((uint16_t)0x0040)

Data Toggle, for transmission transfers

#define USB_EP7R_CTR_TX   ((uint16_t)0x0080)

Correct Transfer for transmission

#define USB_EP7R_EP_KIND   ((uint16_t)0x0100)

Endpoint Kind

#define USB_EP7R_EP_TYPE   ((uint16_t)0x0600)

EP_TYPE[1:0] bits (Endpoint type)

#define USB_EP7R_EP_TYPE_0   ((uint16_t)0x0200)

Bit 0

#define USB_EP7R_EP_TYPE_1   ((uint16_t)0x0400)

Bit 1

#define USB_EP7R_SETUP   ((uint16_t)0x0800)

Setup transaction completed

#define USB_EP7R_STAT_RX   ((uint16_t)0x3000)

STAT_RX[1:0] bits (Status bits, for reception transfers)

#define USB_EP7R_STAT_RX_0   ((uint16_t)0x1000)

Bit 0

#define USB_EP7R_STAT_RX_1   ((uint16_t)0x2000)

Bit 1

#define USB_EP7R_DTOG_RX   ((uint16_t)0x4000)

Data Toggle, for reception transfers

#define USB_EP7R_CTR_RX   ((uint16_t)0x8000)

Correct Transfer for reception Common registers

#define USB_CNTR_FRES   ((uint16_t)0x0001)

Force USB Reset

#define USB_CNTR_PDWN   ((uint16_t)0x0002)

Power down

#define USB_CNTR_LP_MODE   ((uint16_t)0x0004)

Low-power mode

#define USB_CNTR_FSUSP   ((uint16_t)0x0008)

Force suspend

#define USB_CNTR_RESUME   ((uint16_t)0x0010)

Resume request

#define USB_CNTR_ESOFM   ((uint16_t)0x0100)

Expected Start Of Frame Interrupt Mask

#define USB_CNTR_SOFM   ((uint16_t)0x0200)

Start Of Frame Interrupt Mask

#define USB_CNTR_RESETM   ((uint16_t)0x0400)

RESET Interrupt Mask

#define USB_CNTR_SUSPM   ((uint16_t)0x0800)

Suspend mode Interrupt Mask

#define USB_CNTR_WKUPM   ((uint16_t)0x1000)

Wakeup Interrupt Mask

#define USB_CNTR_ERRM   ((uint16_t)0x2000)

Error Interrupt Mask

#define USB_CNTR_PMAOVRM   ((uint16_t)0x4000)

Packet Memory Area Over / Underrun Interrupt Mask

#define USB_CNTR_CTRM   ((uint16_t)0x8000)

Correct Transfer Interrupt Mask

#define USB_ISTR_EP_ID   ((uint16_t)0x000F)

Endpoint Identifier

#define USB_ISTR_DIR   ((uint16_t)0x0010)

Direction of transaction

#define USB_ISTR_ESOF   ((uint16_t)0x0100)

Expected Start Of Frame

#define USB_ISTR_SOF   ((uint16_t)0x0200)

Start Of Frame

#define USB_ISTR_RESET   ((uint16_t)0x0400)

USB RESET request

#define USB_ISTR_SUSP   ((uint16_t)0x0800)

Suspend mode request

#define USB_ISTR_WKUP   ((uint16_t)0x1000)

Wake up

#define USB_ISTR_ERR   ((uint16_t)0x2000)

Error

#define USB_ISTR_PMAOVR   ((uint16_t)0x4000)

Packet Memory Area Over / Underrun

#define USB_ISTR_CTR   ((uint16_t)0x8000)

Correct Transfer

#define USB_FNR_FN   ((uint16_t)0x07FF)

Frame Number

#define USB_FNR_LSOF   ((uint16_t)0x1800)

Lost SOF

#define USB_FNR_LCK   ((uint16_t)0x2000)

Locked

#define USB_FNR_RXDM   ((uint16_t)0x4000)

Receive Data - Line Status

#define USB_FNR_RXDP   ((uint16_t)0x8000)

Receive Data + Line Status

#define USB_DADDR_ADD   ((uint8_t)0x7F)

ADD[6:0] bits (Device Address)

#define USB_DADDR_ADD0   ((uint8_t)0x01)

Bit 0

#define USB_DADDR_ADD1   ((uint8_t)0x02)

Bit 1

#define USB_DADDR_ADD2   ((uint8_t)0x04)

Bit 2

#define USB_DADDR_ADD3   ((uint8_t)0x08)

Bit 3

#define USB_DADDR_ADD4   ((uint8_t)0x10)

Bit 4

#define USB_DADDR_ADD5   ((uint8_t)0x20)

Bit 5

#define USB_DADDR_ADD6   ((uint8_t)0x40)

Bit 6

#define USB_DADDR_EF   ((uint8_t)0x80)

Enable Function

#define USB_BTABLE_BTABLE   ((uint16_t)0xFFF8)

Buffer Table Buffer descriptor table

#define USB_ADDR0_TX_ADDR0_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 0

#define USB_ADDR1_TX_ADDR1_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 1

#define USB_ADDR2_TX_ADDR2_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 2

#define USB_ADDR3_TX_ADDR3_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 3

#define USB_ADDR4_TX_ADDR4_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 4

#define USB_ADDR5_TX_ADDR5_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 5

#define USB_ADDR6_TX_ADDR6_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 6

#define USB_ADDR7_TX_ADDR7_TX   ((uint16_t)0xFFFE)

Transmission Buffer Address 7

#define USB_COUNT0_TX_COUNT0_TX   ((uint16_t)0x03FF)

Transmission Byte Count 0

#define USB_COUNT1_TX_COUNT1_TX   ((uint16_t)0x03FF)

Transmission Byte Count 1

#define USB_COUNT2_TX_COUNT2_TX   ((uint16_t)0x03FF)

Transmission Byte Count 2

#define USB_COUNT3_TX_COUNT3_TX   ((uint16_t)0x03FF)

Transmission Byte Count 3

#define USB_COUNT4_TX_COUNT4_TX   ((uint16_t)0x03FF)

Transmission Byte Count 4

#define USB_COUNT5_TX_COUNT5_TX   ((uint16_t)0x03FF)

Transmission Byte Count 5

#define USB_COUNT6_TX_COUNT6_TX   ((uint16_t)0x03FF)

Transmission Byte Count 6

#define USB_COUNT7_TX_COUNT7_TX   ((uint16_t)0x03FF)

Transmission Byte Count 7

#define USB_COUNT0_TX_0_COUNT0_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 0 (low)

#define USB_COUNT0_TX_1_COUNT0_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 0 (high)

#define USB_COUNT1_TX_0_COUNT1_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 1 (low)

#define USB_COUNT1_TX_1_COUNT1_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 1 (high)

#define USB_COUNT2_TX_0_COUNT2_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 2 (low)

#define USB_COUNT2_TX_1_COUNT2_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 2 (high)

#define USB_COUNT3_TX_0_COUNT3_TX_0   ((uint16_t)0x000003FF)

Transmission Byte Count 3 (low)

#define USB_COUNT3_TX_1_COUNT3_TX_1   ((uint16_t)0x03FF0000)

Transmission Byte Count 3 (high)

#define USB_COUNT4_TX_0_COUNT4_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 4 (low)

#define USB_COUNT4_TX_1_COUNT4_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 4 (high)

#define USB_COUNT5_TX_0_COUNT5_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 5 (low)

#define USB_COUNT5_TX_1_COUNT5_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 5 (high)

#define USB_COUNT6_TX_0_COUNT6_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 6 (low)

#define USB_COUNT6_TX_1_COUNT6_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 6 (high)

#define USB_COUNT7_TX_0_COUNT7_TX_0   ((uint32_t)0x000003FF)

Transmission Byte Count 7 (low)

#define USB_COUNT7_TX_1_COUNT7_TX_1   ((uint32_t)0x03FF0000)

Transmission Byte Count 7 (high)

#define USB_ADDR0_RX_ADDR0_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 0

#define USB_ADDR1_RX_ADDR1_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 1

#define USB_ADDR2_RX_ADDR2_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 2

#define USB_ADDR3_RX_ADDR3_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 3

#define USB_ADDR4_RX_ADDR4_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 4

#define USB_ADDR5_RX_ADDR5_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 5

#define USB_ADDR6_RX_ADDR6_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 6

#define USB_ADDR7_RX_ADDR7_RX   ((uint16_t)0xFFFE)

Reception Buffer Address 7

#define USB_COUNT0_RX_COUNT0_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT0_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT0_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT0_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT0_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT0_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT0_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT0_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT1_RX_COUNT1_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT1_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT1_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT1_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT1_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT1_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT1_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT1_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT2_RX_COUNT2_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT2_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT2_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT2_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT2_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT2_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT2_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT2_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT3_RX_COUNT3_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT3_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT3_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT3_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT3_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT3_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT3_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT3_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT4_RX_COUNT4_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT4_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT4_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT4_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT4_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT4_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT4_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT4_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT5_RX_COUNT5_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT5_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT5_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT5_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT5_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT5_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT5_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT5_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT6_RX_COUNT6_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT6_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT6_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT6_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT6_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT6_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT6_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT6_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT7_RX_COUNT7_RX   ((uint16_t)0x03FF)

Reception Byte Count

#define USB_COUNT7_RX_NUM_BLOCK   ((uint16_t)0x7C00)

NUM_BLOCK[4:0] bits (Number of blocks)

#define USB_COUNT7_RX_NUM_BLOCK_0   ((uint16_t)0x0400)

Bit 0

#define USB_COUNT7_RX_NUM_BLOCK_1   ((uint16_t)0x0800)

Bit 1

#define USB_COUNT7_RX_NUM_BLOCK_2   ((uint16_t)0x1000)

Bit 2

#define USB_COUNT7_RX_NUM_BLOCK_3   ((uint16_t)0x2000)

Bit 3

#define USB_COUNT7_RX_NUM_BLOCK_4   ((uint16_t)0x4000)

Bit 4

#define USB_COUNT7_RX_BLSIZE   ((uint16_t)0x8000)

BLock SIZE

#define USB_COUNT0_RX_0_COUNT0_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT0_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT0_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT0_RX_1_COUNT0_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT0_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT0_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT1_RX_0_COUNT1_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT1_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT1_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT1_RX_1_COUNT1_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT1_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT1_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT2_RX_0_COUNT2_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT2_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT2_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT2_RX_1_COUNT2_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT2_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT2_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT3_RX_0_COUNT3_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT3_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT3_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT3_RX_1_COUNT3_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT3_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT3_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT4_RX_0_COUNT4_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT4_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT4_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT4_RX_1_COUNT4_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT4_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT4_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT5_RX_0_COUNT5_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT5_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT5_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT5_RX_1_COUNT5_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT5_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT5_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT6_RX_0_COUNT6_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT6_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT6_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT6_RX_1_COUNT6_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT6_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT6_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define USB_COUNT7_RX_0_COUNT7_RX_0   ((uint32_t)0x000003FF)

Reception Byte Count (low)

#define USB_COUNT7_RX_0_NUM_BLOCK_0   ((uint32_t)0x00007C00)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0   ((uint32_t)0x00000400)

Bit 0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1   ((uint32_t)0x00000800)

Bit 1

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2   ((uint32_t)0x00001000)

Bit 2

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3   ((uint32_t)0x00002000)

Bit 3

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4   ((uint32_t)0x00004000)

Bit 4

#define USB_COUNT7_RX_0_BLSIZE_0   ((uint32_t)0x00008000)

BLock SIZE (low)

#define USB_COUNT7_RX_1_COUNT7_RX_1   ((uint32_t)0x03FF0000)

Reception Byte Count (high)

#define USB_COUNT7_RX_1_NUM_BLOCK_1   ((uint32_t)0x7C000000)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0   ((uint32_t)0x04000000)

Bit 0

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1   ((uint32_t)0x08000000)

Bit 1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2   ((uint32_t)0x10000000)

Bit 2

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3   ((uint32_t)0x20000000)

Bit 3

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4   ((uint32_t)0x40000000)

Bit 4

#define USB_COUNT7_RX_1_BLSIZE_1   ((uint32_t)0x80000000)

BLock SIZE (high)

#define WWDG_CR_T   ((uint8_t)0x7F)

T[6:0] bits (7-Bit counter (MSB to LSB))

#define WWDG_CR_T0   ((uint8_t)0x01)

Bit 0

#define WWDG_CR_T1   ((uint8_t)0x02)

Bit 1

#define WWDG_CR_T2   ((uint8_t)0x04)

Bit 2

#define WWDG_CR_T3   ((uint8_t)0x08)

Bit 3

#define WWDG_CR_T4   ((uint8_t)0x10)

Bit 4

#define WWDG_CR_T5   ((uint8_t)0x20)

Bit 5

#define WWDG_CR_T6   ((uint8_t)0x40)

Bit 6

#define WWDG_CR_WDGA   ((uint8_t)0x80)

Activation bit

#define WWDG_CFR_W   ((uint16_t)0x007F)

W[6:0] bits (7-bit window value)

#define WWDG_CFR_W0   ((uint16_t)0x0001)

Bit 0

#define WWDG_CFR_W1   ((uint16_t)0x0002)

Bit 1

#define WWDG_CFR_W2   ((uint16_t)0x0004)

Bit 2

#define WWDG_CFR_W3   ((uint16_t)0x0008)

Bit 3

#define WWDG_CFR_W4   ((uint16_t)0x0010)

Bit 4

#define WWDG_CFR_W5   ((uint16_t)0x0020)

Bit 5

#define WWDG_CFR_W6   ((uint16_t)0x0040)

Bit 6

#define WWDG_CFR_WDGTB   ((uint16_t)0x0180)

WDGTB[1:0] bits (Timer Base)

#define WWDG_CFR_WDGTB0   ((uint16_t)0x0080)

Bit 0

#define WWDG_CFR_WDGTB1   ((uint16_t)0x0100)

Bit 1

#define WWDG_CFR_EWI   ((uint16_t)0x0200)

Early Wakeup Interrupt

#define WWDG_SR_EWIF   ((uint8_t)0x01)

Early Wakeup Interrupt Flag

#define SysTick_CTRL_ENABLE   ((uint32_t)0x00000001)

Counter enable

#define SysTick_CTRL_TICKINT   ((uint32_t)0x00000002)

Counting down to 0 pends the SysTick handler

#define SysTick_CTRL_CLKSOURCE   ((uint32_t)0x00000004)

Clock source

#define SysTick_CTRL_COUNTFLAG   ((uint32_t)0x00010000)

Count Flag

#define SysTick_LOAD_RELOAD   ((uint32_t)0x00FFFFFF)

Value to load into the SysTick Current Value Register when the counter reaches 0

#define SysTick_VAL_CURRENT   ((uint32_t)0x00FFFFFF)

Current value at the time the register is accessed

#define SysTick_CALIB_TENMS   ((uint32_t)0x00FFFFFF)

Reload value to use for 10ms timing

#define SysTick_CALIB_SKEW   ((uint32_t)0x40000000)

Calibration value is not exactly 10 ms

#define SysTick_CALIB_NOREF   ((uint32_t)0x80000000)

The reference clock is not provided

#define NVIC_ISER_SETENA   ((uint32_t)0xFFFFFFFF)

Interrupt set enable bits

#define NVIC_ISER_SETENA_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ISER_SETENA_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ISER_SETENA_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ISER_SETENA_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ISER_SETENA_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ISER_SETENA_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ISER_SETENA_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ISER_SETENA_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ISER_SETENA_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ISER_SETENA_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ISER_SETENA_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ISER_SETENA_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ISER_SETENA_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ISER_SETENA_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ISER_SETENA_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ISER_SETENA_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ISER_SETENA_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ISER_SETENA_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ISER_SETENA_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ISER_SETENA_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ISER_SETENA_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ISER_SETENA_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ISER_SETENA_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ISER_SETENA_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ISER_SETENA_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ISER_SETENA_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ISER_SETENA_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ISER_SETENA_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ISER_SETENA_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ISER_SETENA_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ISER_SETENA_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ISER_SETENA_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ICER_CLRENA   ((uint32_t)0xFFFFFFFF)

Interrupt clear-enable bits

#define NVIC_ICER_CLRENA_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ICER_CLRENA_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ICER_CLRENA_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ICER_CLRENA_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ICER_CLRENA_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ICER_CLRENA_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ICER_CLRENA_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ICER_CLRENA_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ICER_CLRENA_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ICER_CLRENA_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ICER_CLRENA_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ICER_CLRENA_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ICER_CLRENA_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ICER_CLRENA_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ICER_CLRENA_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ICER_CLRENA_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ICER_CLRENA_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ICER_CLRENA_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ICER_CLRENA_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ICER_CLRENA_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ICER_CLRENA_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ICER_CLRENA_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ICER_CLRENA_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ICER_CLRENA_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ICER_CLRENA_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ICER_CLRENA_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ICER_CLRENA_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ICER_CLRENA_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ICER_CLRENA_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ICER_CLRENA_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ICER_CLRENA_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ICER_CLRENA_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ISPR_SETPEND   ((uint32_t)0xFFFFFFFF)

Interrupt set-pending bits

#define NVIC_ISPR_SETPEND_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ISPR_SETPEND_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ISPR_SETPEND_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ISPR_SETPEND_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ISPR_SETPEND_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ISPR_SETPEND_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ISPR_SETPEND_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ISPR_SETPEND_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ISPR_SETPEND_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ISPR_SETPEND_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ISPR_SETPEND_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ISPR_SETPEND_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ISPR_SETPEND_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ISPR_SETPEND_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ISPR_SETPEND_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ISPR_SETPEND_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ISPR_SETPEND_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ISPR_SETPEND_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ISPR_SETPEND_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ISPR_SETPEND_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ISPR_SETPEND_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ISPR_SETPEND_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ISPR_SETPEND_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ISPR_SETPEND_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ISPR_SETPEND_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ISPR_SETPEND_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ISPR_SETPEND_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ISPR_SETPEND_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ISPR_SETPEND_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ISPR_SETPEND_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ISPR_SETPEND_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ISPR_SETPEND_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_ICPR_CLRPEND   ((uint32_t)0xFFFFFFFF)

Interrupt clear-pending bits

#define NVIC_ICPR_CLRPEND_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_ICPR_CLRPEND_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_ICPR_CLRPEND_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_ICPR_CLRPEND_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_ICPR_CLRPEND_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_ICPR_CLRPEND_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_ICPR_CLRPEND_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_ICPR_CLRPEND_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_ICPR_CLRPEND_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_ICPR_CLRPEND_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_ICPR_CLRPEND_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_ICPR_CLRPEND_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_ICPR_CLRPEND_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_ICPR_CLRPEND_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_ICPR_CLRPEND_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_ICPR_CLRPEND_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_ICPR_CLRPEND_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_ICPR_CLRPEND_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_ICPR_CLRPEND_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_ICPR_CLRPEND_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_ICPR_CLRPEND_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_ICPR_CLRPEND_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_ICPR_CLRPEND_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_ICPR_CLRPEND_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_ICPR_CLRPEND_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_ICPR_CLRPEND_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_ICPR_CLRPEND_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_ICPR_CLRPEND_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_ICPR_CLRPEND_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_ICPR_CLRPEND_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_ICPR_CLRPEND_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_ICPR_CLRPEND_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_IABR_ACTIVE   ((uint32_t)0xFFFFFFFF)

Interrupt active flags

#define NVIC_IABR_ACTIVE_0   ((uint32_t)0x00000001)

bit 0

#define NVIC_IABR_ACTIVE_1   ((uint32_t)0x00000002)

bit 1

#define NVIC_IABR_ACTIVE_2   ((uint32_t)0x00000004)

bit 2

#define NVIC_IABR_ACTIVE_3   ((uint32_t)0x00000008)

bit 3

#define NVIC_IABR_ACTIVE_4   ((uint32_t)0x00000010)

bit 4

#define NVIC_IABR_ACTIVE_5   ((uint32_t)0x00000020)

bit 5

#define NVIC_IABR_ACTIVE_6   ((uint32_t)0x00000040)

bit 6

#define NVIC_IABR_ACTIVE_7   ((uint32_t)0x00000080)

bit 7

#define NVIC_IABR_ACTIVE_8   ((uint32_t)0x00000100)

bit 8

#define NVIC_IABR_ACTIVE_9   ((uint32_t)0x00000200)

bit 9

#define NVIC_IABR_ACTIVE_10   ((uint32_t)0x00000400)

bit 10

#define NVIC_IABR_ACTIVE_11   ((uint32_t)0x00000800)

bit 11

#define NVIC_IABR_ACTIVE_12   ((uint32_t)0x00001000)

bit 12

#define NVIC_IABR_ACTIVE_13   ((uint32_t)0x00002000)

bit 13

#define NVIC_IABR_ACTIVE_14   ((uint32_t)0x00004000)

bit 14

#define NVIC_IABR_ACTIVE_15   ((uint32_t)0x00008000)

bit 15

#define NVIC_IABR_ACTIVE_16   ((uint32_t)0x00010000)

bit 16

#define NVIC_IABR_ACTIVE_17   ((uint32_t)0x00020000)

bit 17

#define NVIC_IABR_ACTIVE_18   ((uint32_t)0x00040000)

bit 18

#define NVIC_IABR_ACTIVE_19   ((uint32_t)0x00080000)

bit 19

#define NVIC_IABR_ACTIVE_20   ((uint32_t)0x00100000)

bit 20

#define NVIC_IABR_ACTIVE_21   ((uint32_t)0x00200000)

bit 21

#define NVIC_IABR_ACTIVE_22   ((uint32_t)0x00400000)

bit 22

#define NVIC_IABR_ACTIVE_23   ((uint32_t)0x00800000)

bit 23

#define NVIC_IABR_ACTIVE_24   ((uint32_t)0x01000000)

bit 24

#define NVIC_IABR_ACTIVE_25   ((uint32_t)0x02000000)

bit 25

#define NVIC_IABR_ACTIVE_26   ((uint32_t)0x04000000)

bit 26

#define NVIC_IABR_ACTIVE_27   ((uint32_t)0x08000000)

bit 27

#define NVIC_IABR_ACTIVE_28   ((uint32_t)0x10000000)

bit 28

#define NVIC_IABR_ACTIVE_29   ((uint32_t)0x20000000)

bit 29

#define NVIC_IABR_ACTIVE_30   ((uint32_t)0x40000000)

bit 30

#define NVIC_IABR_ACTIVE_31   ((uint32_t)0x80000000)

bit 31

#define NVIC_IPR0_PRI_0   ((uint32_t)0x000000FF)

Priority of interrupt 0

#define NVIC_IPR0_PRI_1   ((uint32_t)0x0000FF00)

Priority of interrupt 1

#define NVIC_IPR0_PRI_2   ((uint32_t)0x00FF0000)

Priority of interrupt 2

#define NVIC_IPR0_PRI_3   ((uint32_t)0xFF000000)

Priority of interrupt 3

#define NVIC_IPR1_PRI_4   ((uint32_t)0x000000FF)

Priority of interrupt 4

#define NVIC_IPR1_PRI_5   ((uint32_t)0x0000FF00)

Priority of interrupt 5

#define NVIC_IPR1_PRI_6   ((uint32_t)0x00FF0000)

Priority of interrupt 6

#define NVIC_IPR1_PRI_7   ((uint32_t)0xFF000000)

Priority of interrupt 7

#define NVIC_IPR2_PRI_8   ((uint32_t)0x000000FF)

Priority of interrupt 8

#define NVIC_IPR2_PRI_9   ((uint32_t)0x0000FF00)

Priority of interrupt 9

#define NVIC_IPR2_PRI_10   ((uint32_t)0x00FF0000)

Priority of interrupt 10

#define NVIC_IPR2_PRI_11   ((uint32_t)0xFF000000)

Priority of interrupt 11

#define NVIC_IPR3_PRI_12   ((uint32_t)0x000000FF)

Priority of interrupt 12

#define NVIC_IPR3_PRI_13   ((uint32_t)0x0000FF00)

Priority of interrupt 13

#define NVIC_IPR3_PRI_14   ((uint32_t)0x00FF0000)

Priority of interrupt 14

#define NVIC_IPR3_PRI_15   ((uint32_t)0xFF000000)

Priority of interrupt 15

#define NVIC_IPR4_PRI_16   ((uint32_t)0x000000FF)

Priority of interrupt 16

#define NVIC_IPR4_PRI_17   ((uint32_t)0x0000FF00)

Priority of interrupt 17

#define NVIC_IPR4_PRI_18   ((uint32_t)0x00FF0000)

Priority of interrupt 18

#define NVIC_IPR4_PRI_19   ((uint32_t)0xFF000000)

Priority of interrupt 19

#define NVIC_IPR5_PRI_20   ((uint32_t)0x000000FF)

Priority of interrupt 20

#define NVIC_IPR5_PRI_21   ((uint32_t)0x0000FF00)

Priority of interrupt 21

#define NVIC_IPR5_PRI_22   ((uint32_t)0x00FF0000)

Priority of interrupt 22

#define NVIC_IPR5_PRI_23   ((uint32_t)0xFF000000)

Priority of interrupt 23

#define NVIC_IPR6_PRI_24   ((uint32_t)0x000000FF)

Priority of interrupt 24

#define NVIC_IPR6_PRI_25   ((uint32_t)0x0000FF00)

Priority of interrupt 25

#define NVIC_IPR6_PRI_26   ((uint32_t)0x00FF0000)

Priority of interrupt 26

#define NVIC_IPR6_PRI_27   ((uint32_t)0xFF000000)

Priority of interrupt 27

#define NVIC_IPR7_PRI_28   ((uint32_t)0x000000FF)

Priority of interrupt 28

#define NVIC_IPR7_PRI_29   ((uint32_t)0x0000FF00)

Priority of interrupt 29

#define NVIC_IPR7_PRI_30   ((uint32_t)0x00FF0000)

Priority of interrupt 30

#define NVIC_IPR7_PRI_31   ((uint32_t)0xFF000000)

Priority of interrupt 31

#define SCB_CPUID_REVISION   ((uint32_t)0x0000000F)

Implementation defined revision number

#define SCB_CPUID_PARTNO   ((uint32_t)0x0000FFF0)

Number of processor within family

#define SCB_CPUID_Constant   ((uint32_t)0x000F0000)

Reads as 0x0F

#define SCB_CPUID_VARIANT   ((uint32_t)0x00F00000)

Implementation defined variant number

#define SCB_CPUID_IMPLEMENTER   ((uint32_t)0xFF000000)

Implementer code. ARM is 0x41

#define SCB_ICSR_VECTACTIVE   ((uint32_t)0x000001FF)

Active ISR number field

#define SCB_ICSR_RETTOBASE   ((uint32_t)0x00000800)

All active exceptions minus the IPSR_current_exception yields the empty set

#define SCB_ICSR_VECTPENDING   ((uint32_t)0x003FF000)

Pending ISR number field

#define SCB_ICSR_ISRPENDING   ((uint32_t)0x00400000)

Interrupt pending flag

#define SCB_ICSR_ISRPREEMPT   ((uint32_t)0x00800000)

It indicates that a pending interrupt becomes active in the next running cycle

#define SCB_ICSR_PENDSTCLR   ((uint32_t)0x02000000)

Clear pending SysTick bit

#define SCB_ICSR_PENDSTSET   ((uint32_t)0x04000000)

Set pending SysTick bit

#define SCB_ICSR_PENDSVCLR   ((uint32_t)0x08000000)

Clear pending pendSV bit

#define SCB_ICSR_PENDSVSET   ((uint32_t)0x10000000)

Set pending pendSV bit

#define SCB_ICSR_NMIPENDSET   ((uint32_t)0x80000000)

Set pending NMI bit

#define SCB_VTOR_TBLOFF   ((uint32_t)0x1FFFFF80)

Vector table base offset field

#define SCB_VTOR_TBLBASE   ((uint32_t)0x20000000)

Table base in code(0) or RAM(1) ***************** Bit definition for SCB_AIRCR register

#define SCB_AIRCR_VECTRESET   ((uint32_t)0x00000001)

System Reset bit

#define SCB_AIRCR_VECTCLRACTIVE   ((uint32_t)0x00000002)

Clear active vector bit

#define SCB_AIRCR_SYSRESETREQ   ((uint32_t)0x00000004)

Requests chip control logic to generate a reset

#define SCB_AIRCR_PRIGROUP   ((uint32_t)0x00000700)

PRIGROUP[2:0] bits (Priority group)

#define SCB_AIRCR_PRIGROUP_0   ((uint32_t)0x00000100)

Bit 0

#define SCB_AIRCR_PRIGROUP_1   ((uint32_t)0x00000200)

Bit 1

#define SCB_AIRCR_PRIGROUP_2   ((uint32_t)0x00000400)

Bit 2

#define SCB_AIRCR_PRIGROUP0   ((uint32_t)0x00000000)

Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)

#define SCB_AIRCR_PRIGROUP1   ((uint32_t)0x00000100)

Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)

#define SCB_AIRCR_PRIGROUP2   ((uint32_t)0x00000200)

Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)

#define SCB_AIRCR_PRIGROUP3   ((uint32_t)0x00000300)

Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)

#define SCB_AIRCR_PRIGROUP4   ((uint32_t)0x00000400)

Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)

#define SCB_AIRCR_PRIGROUP5   ((uint32_t)0x00000500)

Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)

#define SCB_AIRCR_PRIGROUP6   ((uint32_t)0x00000600)

Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)

#define SCB_AIRCR_PRIGROUP7   ((uint32_t)0x00000700)

Priority group=7 (no pre-emption priority, 8 bits of subpriority)

#define SCB_AIRCR_ENDIANESS   ((uint32_t)0x00008000)

Data endianness bit

#define SCB_AIRCR_VECTKEY   ((uint32_t)0xFFFF0000)

Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)

#define SCB_SCR_SLEEPONEXIT   ((uint8_t)0x02)

Sleep on exit bit

#define SCB_SCR_SLEEPDEEP   ((uint8_t)0x04)

Sleep deep bit

#define SCB_SCR_SEVONPEND   ((uint8_t)0x10)

Wake up from WFE

#define SCB_CCR_NONBASETHRDENA   ((uint16_t)0x0001)

Thread mode can be entered from any level in Handler mode by controlled return value

#define SCB_CCR_USERSETMPEND   ((uint16_t)0x0002)

Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception

#define SCB_CCR_UNALIGN_TRP   ((uint16_t)0x0008)

Trap for unaligned access

#define SCB_CCR_DIV_0_TRP   ((uint16_t)0x0010)

Trap on Divide by 0

#define SCB_CCR_BFHFNMIGN   ((uint16_t)0x0100)

Handlers running at priority -1 and -2

#define SCB_CCR_STKALIGN   ((uint16_t)0x0200)

On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned

#define SCB_SHPR_PRI_N   ((uint32_t)0x000000FF)

Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor

#define SCB_SHPR_PRI_N1   ((uint32_t)0x0000FF00)

Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved

#define SCB_SHPR_PRI_N2   ((uint32_t)0x00FF0000)

Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV

#define SCB_SHPR_PRI_N3   ((uint32_t)0xFF000000)

Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick

#define SCB_SHCSR_MEMFAULTACT   ((uint32_t)0x00000001)

MemManage is active

#define SCB_SHCSR_BUSFAULTACT   ((uint32_t)0x00000002)

BusFault is active

#define SCB_SHCSR_USGFAULTACT   ((uint32_t)0x00000008)

UsageFault is active

#define SCB_SHCSR_SVCALLACT   ((uint32_t)0x00000080)

SVCall is active

#define SCB_SHCSR_MONITORACT   ((uint32_t)0x00000100)

Monitor is active

#define SCB_SHCSR_PENDSVACT   ((uint32_t)0x00000400)

PendSV is active

#define SCB_SHCSR_SYSTICKACT   ((uint32_t)0x00000800)

SysTick is active

#define SCB_SHCSR_USGFAULTPENDED   ((uint32_t)0x00001000)

Usage Fault is pended

#define SCB_SHCSR_MEMFAULTPENDED   ((uint32_t)0x00002000)

MemManage is pended

#define SCB_SHCSR_BUSFAULTPENDED   ((uint32_t)0x00004000)

Bus Fault is pended

#define SCB_SHCSR_SVCALLPENDED   ((uint32_t)0x00008000)

SVCall is pended

#define SCB_SHCSR_MEMFAULTENA   ((uint32_t)0x00010000)

MemManage enable

#define SCB_SHCSR_BUSFAULTENA   ((uint32_t)0x00020000)

Bus Fault enable

#define SCB_SHCSR_USGFAULTENA   ((uint32_t)0x00040000)

UsageFault enable

#define SCB_CFSR_IACCVIOL   ((uint32_t)0x00000001)

< MFSR Instruction access violation

#define SCB_CFSR_DACCVIOL   ((uint32_t)0x00000002)

Data access violation

#define SCB_CFSR_MUNSTKERR   ((uint32_t)0x00000008)

Unstacking error

#define SCB_CFSR_MSTKERR   ((uint32_t)0x00000010)

Stacking error

#define SCB_CFSR_MMARVALID   ((uint32_t)0x00000080)

Memory Manage Address Register address valid flag BFSR

#define SCB_CFSR_IBUSERR   ((uint32_t)0x00000100)

Instruction bus error flag

#define SCB_CFSR_PRECISERR   ((uint32_t)0x00000200)

Precise data bus error

#define SCB_CFSR_IMPRECISERR   ((uint32_t)0x00000400)

Imprecise data bus error

#define SCB_CFSR_UNSTKERR   ((uint32_t)0x00000800)

Unstacking error

#define SCB_CFSR_STKERR   ((uint32_t)0x00001000)

Stacking error

#define SCB_CFSR_BFARVALID   ((uint32_t)0x00008000)

Bus Fault Address Register address valid flag UFSR

#define SCB_CFSR_UNDEFINSTR   ((uint32_t)0x00010000)

The processor attempt to excecute an undefined instruction

#define SCB_CFSR_INVSTATE   ((uint32_t)0x00020000)

Invalid combination of EPSR and instruction

#define SCB_CFSR_INVPC   ((uint32_t)0x00040000)

Attempt to load EXC_RETURN into pc illegally

#define SCB_CFSR_NOCP   ((uint32_t)0x00080000)

Attempt to use a coprocessor instruction

#define SCB_CFSR_UNALIGNED   ((uint32_t)0x01000000)

Fault occurs when there is an attempt to make an unaligned memory access

#define SCB_CFSR_DIVBYZERO   ((uint32_t)0x02000000)

Fault occurs when SDIV or DIV instruction is used with a divisor of 0

#define SCB_HFSR_VECTTBL   ((uint32_t)0x00000002)

Fault occures because of vector table read on exception processing

#define SCB_HFSR_FORCED   ((uint32_t)0x40000000)

Hard Fault activated when a configurable Fault was received and cannot activate

#define SCB_HFSR_DEBUGEVT   ((uint32_t)0x80000000)

Fault related to debug

#define SCB_DFSR_HALTED   ((uint8_t)0x01)

Halt request flag

#define SCB_DFSR_BKPT   ((uint8_t)0x02)

BKPT flag

#define SCB_DFSR_DWTTRAP   ((uint8_t)0x04)

Data Watchpoint and Trace (DWT) flag

#define SCB_DFSR_VCATCH   ((uint8_t)0x08)

Vector catch flag

#define SCB_DFSR_EXTERNAL   ((uint8_t)0x10)

External debug request flag

#define SCB_MMFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)

Mem Manage fault address field

#define SCB_BFAR_ADDRESS   ((uint32_t)0xFFFFFFFF)

Bus fault address field

#define SCB_AFSR_IMPDEF   ((uint32_t)0xFFFFFFFF)

Implementation defined