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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 00047 #ifndef __STM32F2xx_H 00048 #define __STM32F2xx_H 00049 00050 #include <cfg/arch.h> 00051 #include <cfg/clock.h> 00052 00053 #ifdef __cplusplus 00054 extern "C" { 00055 #endif /* __cplusplus */ 00056 00061 /* Uncomment the line below according to the target STM32 device used in your 00062 application 00063 */ 00064 00065 #if !defined (STM32F2XX) 00066 #define STM32F2XX 00067 #endif 00068 00069 /* Tip: To avoid modifying this file each time you need to switch between these 00070 devices, you can define the device in your toolchain compiler preprocessor. 00071 */ 00072 00073 #if !defined (STM32F2XX) 00074 #error "Please select first the target STM32F2XX device used in your application (in stm32f2xx.h file)" 00075 #endif 00076 00077 #if !defined (USE_STDPERIPH_DRIVER) 00078 00083 /*#define USE_STDPERIPH_DRIVER*/ 00084 #endif /* USE_STDPERIPH_DRIVER */ 00085 00093 #if !defined (HSE_VALUE) 00094 #define HSE_VALUE ((uint32_t)25000000) 00095 #endif /* HSE_VALUE */ 00096 00101 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 00102 #define HSI_VALUE ((uint32_t)16000000) 00107 #define __STM32F2XX_STDPERIPH_VERSION_MAIN (0x01) 00108 #define __STM32F2XX_STDPERIPH_VERSION_SUB1 (0x00) 00109 #define __STM32F2XX_STDPERIPH_VERSION_SUB2 (0x00) 00110 #define __STM32F2XX_STDPERIPH_VERSION_RC (0x00) 00111 #define __STM32F2XX_STDPERIPH_VERSION ((__STM32F2XX_STDPERIPH_VERSION_MAIN << 24)\ 00112 |(__STM32F2XX_STDPERIPH_VERSION_SUB1 << 16)\ 00113 |(__STM32F2XX_STDPERIPH_VERSION_SUB2 << 8)\ 00114 |(__STM32F2XX_STDPERIPH_VERSION_RC)) 00115 00127 #define __MPU_PRESENT 1 00128 #define __NVIC_PRIO_BITS 4 00129 #define __Vendor_SysTickConfig 0 00135 typedef enum IRQn 00136 { 00137 /****** Cortex-M3 Processor Exceptions Numbers ****************************************************************/ 00138 NonMaskableInt_IRQn = -14, 00139 MemoryManagement_IRQn = -12, 00140 BusFault_IRQn = -11, 00141 UsageFault_IRQn = -10, 00142 SVCall_IRQn = -5, 00143 DebugMonitor_IRQn = -4, 00144 PendSV_IRQn = -2, 00145 SysTick_IRQn = -1, 00146 /****** STM32 specific Interrupt Numbers **********************************************************************/ 00147 WWDG_IRQn = 0, 00148 PVD_IRQn = 1, 00149 TAMP_STAMP_IRQn = 2, 00150 RTC_WKUP_IRQn = 3, 00151 FLASH_IRQn = 4, 00152 RCC_IRQn = 5, 00153 EXTI0_IRQn = 6, 00154 EXTI1_IRQn = 7, 00155 EXTI2_IRQn = 8, 00156 EXTI3_IRQn = 9, 00157 EXTI4_IRQn = 10, 00158 DMA1_Stream0_IRQn = 11, 00159 DMA1_Stream1_IRQn = 12, 00160 DMA1_Stream2_IRQn = 13, 00161 DMA1_Stream3_IRQn = 14, 00162 DMA1_Stream4_IRQn = 15, 00163 DMA1_Stream5_IRQn = 16, 00164 DMA1_Stream6_IRQn = 17, 00165 ADC_IRQn = 18, 00166 CAN1_TX_IRQn = 19, 00167 CAN1_RX0_IRQn = 20, 00168 CAN1_RX1_IRQn = 21, 00169 CAN1_SCE_IRQn = 22, 00170 EXTI9_5_IRQn = 23, 00171 TIM1_BRK_TIM9_IRQn = 24, 00172 TIM1_UP_TIM10_IRQn = 25, 00173 TIM1_TRG_COM_TIM11_IRQn = 26, 00174 TIM1_CC_IRQn = 27, 00175 TIM2_IRQn = 28, 00176 TIM3_IRQn = 29, 00177 TIM4_IRQn = 30, 00178 I2C1_EV_IRQn = 31, 00179 I2C1_ER_IRQn = 32, 00180 I2C2_EV_IRQn = 33, 00181 I2C2_ER_IRQn = 34, 00182 SPI1_IRQn = 35, 00183 SPI2_IRQn = 36, 00184 USART1_IRQn = 37, 00185 USART2_IRQn = 38, 00186 USART3_IRQn = 39, 00187 EXTI15_10_IRQn = 40, 00188 RTC_Alarm_IRQn = 41, 00189 OTG_FS_WKUP_IRQn = 42, 00190 TIM8_BRK_TIM12_IRQn = 43, 00191 TIM8_UP_TIM13_IRQn = 44, 00192 TIM8_TRG_COM_TIM14_IRQn = 45, 00193 TIM8_CC_IRQn = 46, 00194 DMA1_Stream7_IRQn = 47, 00195 FSMC_IRQn = 48, 00196 SDIO_IRQn = 49, 00197 TIM5_IRQn = 50, 00198 SPI3_IRQn = 51, 00199 UART4_IRQn = 52, 00200 UART5_IRQn = 53, 00201 TIM6_DAC_IRQn = 54, 00202 TIM7_IRQn = 55, 00203 DMA2_Stream0_IRQn = 56, 00204 DMA2_Stream1_IRQn = 57, 00205 DMA2_Stream2_IRQn = 58, 00206 DMA2_Stream3_IRQn = 59, 00207 DMA2_Stream4_IRQn = 60, 00208 ETH_IRQn = 61, 00209 ETH_WKUP_IRQn = 62, 00210 CAN2_TX_IRQn = 63, 00211 CAN2_RX0_IRQn = 64, 00212 CAN2_RX1_IRQn = 65, 00213 CAN2_SCE_IRQn = 66, 00214 OTG_FS_IRQn = 67, 00215 DMA2_Stream5_IRQn = 68, 00216 DMA2_Stream6_IRQn = 69, 00217 DMA2_Stream7_IRQn = 70, 00218 USART6_IRQn = 71, 00219 I2C3_EV_IRQn = 72, 00220 I2C3_ER_IRQn = 73, 00221 OTG_HS_EP1_OUT_IRQn = 74, 00222 OTG_HS_EP1_IN_IRQn = 75, 00223 OTG_HS_WKUP_IRQn = 76, 00224 OTG_HS_IRQn = 77, 00225 DCMI_IRQn = 78, 00226 CRYP_IRQn = 79, 00227 HASH_RNG_IRQn = 80 00228 } IRQn_Type; 00229 00234 #include <arch/cm3/core_cm3.h> 00235 #include <arch/cm3/stm/system_stm32f2xx.h> 00236 #include <stdint.h> 00237 00242 typedef int32_t s32; 00243 typedef int16_t s16; 00244 typedef int8_t s8; 00245 00246 typedef const int32_t sc32; 00247 typedef const int16_t sc16; 00248 typedef const int8_t sc8; 00250 typedef __IO int32_t vs32; 00251 typedef __IO int16_t vs16; 00252 typedef __IO int8_t vs8; 00253 00254 typedef __I int32_t vsc32; 00255 typedef __I int16_t vsc16; 00256 typedef __I int8_t vsc8; 00258 typedef uint32_t u32; 00259 typedef uint16_t u16; 00260 typedef uint8_t u8; 00261 00262 typedef const uint32_t uc32; 00263 typedef const uint16_t uc16; 00264 typedef const uint8_t uc8; 00266 typedef __IO uint32_t vu32; 00267 typedef __IO uint16_t vu16; 00268 typedef __IO uint8_t vu8; 00269 00270 typedef __I uint32_t vuc32; 00271 typedef __I uint16_t vuc16; 00272 typedef __I uint8_t vuc8; 00274 #ifndef __cplusplus 00275 typedef enum 00276 { 00277 FALSE = 0, TRUE = !FALSE 00278 } 00279 bool; 00280 #endif 00281 00282 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 00283 00284 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 00285 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00286 00287 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00288 00301 typedef struct 00302 { 00303 __IO uint32_t SR; 00304 __IO uint32_t CR1; 00305 __IO uint32_t CR2; 00306 __IO uint32_t SMPR1; 00307 __IO uint32_t SMPR2; 00308 __IO uint32_t JOFR1; 00309 __IO uint32_t JOFR2; 00310 __IO uint32_t JOFR3; 00311 __IO uint32_t JOFR4; 00312 __IO uint32_t HTR; 00313 __IO uint32_t LTR; 00314 __IO uint32_t SQR1; 00315 __IO uint32_t SQR2; 00316 __IO uint32_t SQR3; 00317 __IO uint32_t JSQR; 00318 __IO uint32_t JDR1; 00319 __IO uint32_t JDR2; 00320 __IO uint32_t JDR3; 00321 __IO uint32_t JDR4; 00322 __IO uint32_t DR; 00323 } ADC_TypeDef; 00324 00325 typedef struct 00326 { 00327 __IO uint32_t CSR; 00328 __IO uint32_t CCR; 00329 __IO uint32_t CDR; 00331 } ADC_Common_TypeDef; 00332 00333 00338 typedef struct 00339 { 00340 __IO uint32_t TIR; 00341 __IO uint32_t TDTR; 00342 __IO uint32_t TDLR; 00343 __IO uint32_t TDHR; 00344 } CAN_TxMailBox_TypeDef; 00345 00350 typedef struct 00351 { 00352 __IO uint32_t RIR; 00353 __IO uint32_t RDTR; 00354 __IO uint32_t RDLR; 00355 __IO uint32_t RDHR; 00356 } CAN_FIFOMailBox_TypeDef; 00357 00362 typedef struct 00363 { 00364 __IO uint32_t FR1; 00365 __IO uint32_t FR2; 00366 } CAN_FilterRegister_TypeDef; 00367 00372 typedef struct 00373 { 00374 __IO uint32_t MCR; 00375 __IO uint32_t MSR; 00376 __IO uint32_t TSR; 00377 __IO uint32_t RF0R; 00378 __IO uint32_t RF1R; 00379 __IO uint32_t IER; 00380 __IO uint32_t ESR; 00381 __IO uint32_t BTR; 00382 uint32_t RESERVED0[88]; 00383 CAN_TxMailBox_TypeDef sTxMailBox[3]; 00384 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 00385 uint32_t RESERVED1[12]; 00386 __IO uint32_t FMR; 00387 __IO uint32_t FM1R; 00388 uint32_t RESERVED2; 00389 __IO uint32_t FS1R; 00390 uint32_t RESERVED3; 00391 __IO uint32_t FFA1R; 00392 uint32_t RESERVED4; 00393 __IO uint32_t FA1R; 00394 uint32_t RESERVED5[8]; 00395 CAN_FilterRegister_TypeDef sFilterRegister[28]; 00396 } CAN_TypeDef; 00397 00402 typedef struct 00403 { 00404 __IO uint32_t DR; 00405 __IO uint8_t IDR; 00406 uint8_t RESERVED0; 00407 uint16_t RESERVED1; 00408 __IO uint32_t CR; 00409 } CRC_TypeDef; 00410 00415 typedef struct 00416 { 00417 __IO uint32_t CR; 00418 __IO uint32_t SWTRIGR; 00419 __IO uint32_t DHR12R1; 00420 __IO uint32_t DHR12L1; 00421 __IO uint32_t DHR8R1; 00422 __IO uint32_t DHR12R2; 00423 __IO uint32_t DHR12L2; 00424 __IO uint32_t DHR8R2; 00425 __IO uint32_t DHR12RD; 00426 __IO uint32_t DHR12LD; 00427 __IO uint32_t DHR8RD; 00428 __IO uint32_t DOR1; 00429 __IO uint32_t DOR2; 00430 __IO uint32_t SR; 00431 } DAC_TypeDef; 00432 00437 typedef struct 00438 { 00439 __IO uint32_t IDCODE; 00440 __IO uint32_t CR; 00441 __IO uint32_t APB1FZ; 00442 __IO uint32_t APB2FZ; 00443 }DBGMCU_TypeDef; 00444 00449 typedef struct 00450 { 00451 __IO uint32_t CR; 00452 __IO uint32_t SR; 00453 __IO uint32_t RISR; 00454 __IO uint32_t IER; 00455 __IO uint32_t MISR; 00456 __IO uint32_t ICR; 00457 __IO uint32_t ESCR; 00458 __IO uint32_t ESUR; 00459 __IO uint32_t CWSTRTR; 00460 __IO uint32_t CWSIZER; 00461 __IO uint32_t DR; 00462 } DCMI_TypeDef; 00463 00468 typedef struct 00469 { 00470 __IO uint32_t CR; 00471 __IO uint32_t NDTR; 00472 __IO uint32_t PAR; 00473 __IO uint32_t M0AR; 00474 __IO uint32_t M1AR; 00475 __IO uint32_t FCR; 00476 } DMA_Stream_TypeDef; 00477 00478 typedef struct 00479 { 00480 __IO uint32_t LISR; 00481 __IO uint32_t HISR; 00482 __IO uint32_t LIFCR; 00483 __IO uint32_t HIFCR; 00484 } DMA_TypeDef; 00485 00490 typedef struct 00491 { 00492 __IO uint32_t MACCR; 00493 __IO uint32_t MACFFR; 00494 __IO uint32_t MACHTHR; 00495 __IO uint32_t MACHTLR; 00496 __IO uint32_t MACMIIAR; 00497 __IO uint32_t MACMIIDR; 00498 __IO uint32_t MACFCR; 00499 __IO uint32_t MACVLANTR; /* 8 */ 00500 uint32_t RESERVED0[2]; 00501 __IO uint32_t MACRWUFFR; /* 11 */ 00502 __IO uint32_t MACPMTCSR; 00503 uint32_t RESERVED1[2]; 00504 __IO uint32_t MACSR; /* 15 */ 00505 __IO uint32_t MACIMR; 00506 __IO uint32_t MACA0HR; 00507 __IO uint32_t MACA0LR; 00508 __IO uint32_t MACA1HR; 00509 __IO uint32_t MACA1LR; 00510 __IO uint32_t MACA2HR; 00511 __IO uint32_t MACA2LR; 00512 __IO uint32_t MACA3HR; 00513 __IO uint32_t MACA3LR; /* 24 */ 00514 uint32_t RESERVED2[40]; 00515 __IO uint32_t MMCCR; /* 65 */ 00516 __IO uint32_t MMCRIR; 00517 __IO uint32_t MMCTIR; 00518 __IO uint32_t MMCRIMR; 00519 __IO uint32_t MMCTIMR; /* 69 */ 00520 uint32_t RESERVED3[14]; 00521 __IO uint32_t MMCTGFSCCR; /* 84 */ 00522 __IO uint32_t MMCTGFMSCCR; 00523 uint32_t RESERVED4[5]; 00524 __IO uint32_t MMCTGFCR; 00525 uint32_t RESERVED5[10]; 00526 __IO uint32_t MMCRFCECR; 00527 __IO uint32_t MMCRFAECR; 00528 uint32_t RESERVED6[10]; 00529 __IO uint32_t MMCRGUFCR; 00530 uint32_t RESERVED7[334]; 00531 __IO uint32_t PTPTSCR; 00532 __IO uint32_t PTPSSIR; 00533 __IO uint32_t PTPTSHR; 00534 __IO uint32_t PTPTSLR; 00535 __IO uint32_t PTPTSHUR; 00536 __IO uint32_t PTPTSLUR; 00537 __IO uint32_t PTPTSAR; 00538 __IO uint32_t PTPTTHR; 00539 __IO uint32_t PTPTTLR; 00540 __IO uint32_t RESERVED8; 00541 __IO uint32_t PTPTSSR; /* added for STM32F2xx */ 00542 uint32_t RESERVED9[565]; 00543 __IO uint32_t DMABMR; 00544 __IO uint32_t DMATPDR; 00545 __IO uint32_t DMARPDR; 00546 __IO uint32_t DMARDLAR; 00547 __IO uint32_t DMATDLAR; 00548 __IO uint32_t DMASR; 00549 __IO uint32_t DMAOMR; 00550 __IO uint32_t DMAIER; 00551 __IO uint32_t DMAMFBOCR; 00552 __IO uint32_t DMARSWTR; /* added for STM32F2xx */ 00553 uint32_t RESERVED10[8]; 00554 __IO uint32_t DMACHTDR; 00555 __IO uint32_t DMACHRDR; 00556 __IO uint32_t DMACHTBAR; 00557 __IO uint32_t DMACHRBAR; 00558 } ETH_TypeDef; 00559 00564 typedef struct 00565 { 00566 __IO uint32_t IMR; 00567 __IO uint32_t EMR; 00568 __IO uint32_t RTSR; 00569 __IO uint32_t FTSR; 00570 __IO uint32_t SWIER; 00571 __IO uint32_t PR; 00572 } EXTI_TypeDef; 00573 00578 typedef struct 00579 { 00580 __IO uint32_t ACR; 00581 __IO uint32_t KEYR; 00582 __IO uint32_t OPTKEYR; 00583 __IO uint32_t SR; 00584 __IO uint32_t CR; 00585 __IO uint32_t OPTCR; 00586 } FLASH_TypeDef; 00587 00592 typedef struct 00593 { 00594 __IO uint32_t BTCR[8]; 00595 } FSMC_Bank1_TypeDef; 00596 00601 typedef struct 00602 { 00603 __IO uint32_t BWTR[7]; 00604 } FSMC_Bank1E_TypeDef; 00605 00610 typedef struct 00611 { 00612 __IO uint32_t PCR2; 00613 __IO uint32_t SR2; 00614 __IO uint32_t PMEM2; 00615 __IO uint32_t PATT2; 00616 uint32_t RESERVED0; 00617 __IO uint32_t ECCR2; 00618 } FSMC_Bank2_TypeDef; 00619 00624 typedef struct 00625 { 00626 __IO uint32_t PCR3; 00627 __IO uint32_t SR3; 00628 __IO uint32_t PMEM3; 00629 __IO uint32_t PATT3; 00630 uint32_t RESERVED0; 00631 __IO uint32_t ECCR3; 00632 } FSMC_Bank3_TypeDef; 00633 00638 typedef struct 00639 { 00640 __IO uint32_t PCR4; 00641 __IO uint32_t SR4; 00642 __IO uint32_t PMEM4; 00643 __IO uint32_t PATT4; 00644 __IO uint32_t PIO4; 00645 } FSMC_Bank4_TypeDef; 00646 00651 typedef struct 00652 { 00653 __IO uint32_t MODER; 00654 __IO uint32_t OTYPER; 00655 __IO uint32_t OSPEEDR; 00656 __IO uint32_t PUPDR; 00657 __IO uint32_t IDR; 00658 __IO uint32_t ODR; 00659 __IO uint16_t BSRRL; 00660 __IO uint16_t BSRRH; 00661 __IO uint32_t LCKR; 00662 __IO uint32_t AFR[2]; 00663 } GPIO_TypeDef; 00664 00669 typedef struct 00670 { 00671 __IO uint32_t MEMRMP; 00672 __IO uint32_t PMC; 00673 __IO uint32_t EXTICR[4]; 00674 uint32_t RESERVED[2]; 00675 __IO uint32_t CMPCR; 00676 } SYSCFG_TypeDef; 00677 00682 typedef struct 00683 { 00684 __IO uint16_t CR1; 00685 uint16_t RESERVED0; 00686 __IO uint16_t CR2; 00687 uint16_t RESERVED1; 00688 __IO uint16_t OAR1; 00689 uint16_t RESERVED2; 00690 __IO uint16_t OAR2; 00691 uint16_t RESERVED3; 00692 __IO uint16_t DR; 00693 uint16_t RESERVED4; 00694 __IO uint16_t SR1; 00695 uint16_t RESERVED5; 00696 __IO uint16_t SR2; 00697 uint16_t RESERVED6; 00698 __IO uint16_t CCR; 00699 uint16_t RESERVED7; 00700 __IO uint16_t TRISE; 00701 uint16_t RESERVED8; 00702 } I2C_TypeDef; 00703 00708 typedef struct 00709 { 00710 __IO uint32_t KR; 00711 __IO uint32_t PR; 00712 __IO uint32_t RLR; 00713 __IO uint32_t SR; 00714 } IWDG_TypeDef; 00715 00720 typedef struct 00721 { 00722 __IO uint32_t CR; 00723 __IO uint32_t CSR; 00724 } PWR_TypeDef; 00725 00730 typedef struct 00731 { 00732 __IO uint32_t CR; 00733 __IO uint32_t PLLCFGR; 00734 __IO uint32_t CFGR; 00735 __IO uint32_t CIR; 00736 __IO uint32_t AHB1RSTR; 00737 __IO uint32_t AHB2RSTR; 00738 __IO uint32_t AHB3RSTR; 00739 uint32_t RESERVED0; 00740 __IO uint32_t APB1RSTR; 00741 __IO uint32_t APB2RSTR; 00742 uint32_t RESERVED1[2]; 00743 __IO uint32_t AHB1ENR; 00744 __IO uint32_t AHB2ENR; 00745 __IO uint32_t AHB3ENR; 00746 uint32_t RESERVED2; 00747 __IO uint32_t APB1ENR; 00748 __IO uint32_t APB2ENR; 00749 uint32_t RESERVED3[2]; 00750 __IO uint32_t AHB1LPENR; 00751 __IO uint32_t AHB2LPENR; 00752 __IO uint32_t AHB3LPENR; 00753 uint32_t RESERVED4; 00754 __IO uint32_t APB1LPENR; 00755 __IO uint32_t APB2LPENR; 00756 uint32_t RESERVED5[2]; 00757 __IO uint32_t BDCR; 00758 __IO uint32_t CSR; 00759 uint32_t RESERVED6[2]; 00760 __IO uint32_t SSCGR; 00761 __IO uint32_t PLLI2SCFGR; 00762 } RCC_TypeDef; 00763 00768 typedef struct 00769 { 00770 __IO uint32_t TR; 00771 __IO uint32_t DR; 00772 __IO uint32_t CR; 00773 __IO uint32_t ISR; 00774 __IO uint32_t PRER; 00775 __IO uint32_t WUTR; 00776 __IO uint32_t CALIBR; 00777 __IO uint32_t ALRMAR; 00778 __IO uint32_t ALRMBR; 00779 __IO uint32_t WPR; 00780 uint32_t RESERVED1; 00781 uint32_t RESERVED2; 00782 __IO uint32_t TSTR; 00783 __IO uint32_t TSDR; 00784 uint32_t RESERVED3; 00785 uint32_t RESERVED4; 00786 __IO uint32_t TAFCR; 00787 uint32_t RESERVED5; 00788 uint32_t RESERVED6; 00789 uint32_t RESERVED7; 00790 __IO uint32_t BKP0R; 00791 __IO uint32_t BKP1R; 00792 __IO uint32_t BKP2R; 00793 __IO uint32_t BKP3R; 00794 __IO uint32_t BKP4R; 00795 __IO uint32_t BKP5R; 00796 __IO uint32_t BKP6R; 00797 __IO uint32_t BKP7R; 00798 __IO uint32_t BKP8R; 00799 __IO uint32_t BKP9R; 00800 __IO uint32_t BKP10R; 00801 __IO uint32_t BKP11R; 00802 __IO uint32_t BKP12R; 00803 __IO uint32_t BKP13R; 00804 __IO uint32_t BKP14R; 00805 __IO uint32_t BKP15R; 00806 __IO uint32_t BKP16R; 00807 __IO uint32_t BKP17R; 00808 __IO uint32_t BKP18R; 00809 __IO uint32_t BKP19R; 00810 } RTC_TypeDef; 00811 00816 typedef struct 00817 { 00818 __IO uint32_t POWER; 00819 __IO uint32_t CLKCR; 00820 __IO uint32_t ARG; 00821 __IO uint32_t CMD; 00822 __I uint32_t RESPCMD; 00823 __I uint32_t RESP1; 00824 __I uint32_t RESP2; 00825 __I uint32_t RESP3; 00826 __I uint32_t RESP4; 00827 __IO uint32_t DTIMER; 00828 __IO uint32_t DLEN; 00829 __IO uint32_t DCTRL; 00830 __I uint32_t DCOUNT; 00831 __I uint32_t STA; 00832 __IO uint32_t ICR; 00833 __IO uint32_t MASK; 00834 uint32_t RESERVED0[2]; 00835 __I uint32_t FIFOCNT; 00836 uint32_t RESERVED1[13]; 00837 __IO uint32_t FIFO; 00838 } SDIO_TypeDef; 00839 00844 typedef struct 00845 { 00846 __IO uint16_t CR1; 00847 uint16_t RESERVED0; 00848 __IO uint16_t CR2; 00849 uint16_t RESERVED1; 00850 __IO uint16_t SR; 00851 uint16_t RESERVED2; 00852 __IO uint16_t DR; 00853 uint16_t RESERVED3; 00854 __IO uint16_t CRCPR; 00855 uint16_t RESERVED4; 00856 __IO uint16_t RXCRCR; 00857 uint16_t RESERVED5; 00858 __IO uint16_t TXCRCR; 00859 uint16_t RESERVED6; 00860 __IO uint16_t I2SCFGR; 00861 uint16_t RESERVED7; 00862 __IO uint16_t I2SPR; 00863 uint16_t RESERVED8; 00864 } SPI_TypeDef; 00865 00870 typedef struct 00871 { 00872 __IO uint16_t CR1; 00873 uint16_t RESERVED0; 00874 __IO uint16_t CR2; 00875 uint16_t RESERVED1; 00876 __IO uint16_t SMCR; 00877 uint16_t RESERVED2; 00878 __IO uint16_t DIER; 00879 uint16_t RESERVED3; 00880 __IO uint16_t SR; 00881 uint16_t RESERVED4; 00882 __IO uint16_t EGR; 00883 uint16_t RESERVED5; 00884 __IO uint16_t CCMR1; 00885 uint16_t RESERVED6; 00886 __IO uint16_t CCMR2; 00887 uint16_t RESERVED7; 00888 __IO uint16_t CCER; 00889 uint16_t RESERVED8; 00890 __IO uint32_t CNT; 00891 __IO uint16_t PSC; 00892 uint16_t RESERVED9; 00893 __IO uint32_t ARR; 00894 __IO uint16_t RCR; 00895 uint16_t RESERVED10; 00896 __IO uint32_t CCR1; 00897 __IO uint32_t CCR2; 00898 __IO uint32_t CCR3; 00899 __IO uint32_t CCR4; 00900 __IO uint16_t BDTR; 00901 uint16_t RESERVED11; 00902 __IO uint16_t DCR; 00903 uint16_t RESERVED12; 00904 __IO uint16_t DMAR; 00905 uint16_t RESERVED13; 00906 __IO uint16_t OR; 00907 uint16_t RESERVED14; 00908 } TIM_TypeDef; 00909 00914 typedef struct 00915 { 00916 __IO uint16_t SR; 00917 uint16_t RESERVED0; 00918 __IO uint16_t DR; 00919 uint16_t RESERVED1; 00920 __IO uint16_t BRR; 00921 uint16_t RESERVED2; 00922 __IO uint16_t CR1; 00923 uint16_t RESERVED3; 00924 __IO uint16_t CR2; 00925 uint16_t RESERVED4; 00926 __IO uint16_t CR3; 00927 uint16_t RESERVED5; 00928 __IO uint16_t GTPR; 00929 uint16_t RESERVED6; 00930 } USART_TypeDef; 00931 00936 typedef struct 00937 { 00938 __IO uint32_t CR; 00939 __IO uint32_t CFR; 00940 __IO uint32_t SR; 00941 } WWDG_TypeDef; 00942 00947 typedef struct 00948 { 00949 __IO uint32_t CR; 00950 __IO uint32_t SR; 00951 __IO uint32_t DR; 00952 __IO uint32_t DOUT; 00953 __IO uint32_t DMACR; 00954 __IO uint32_t IMSCR; 00955 __IO uint32_t RISR; 00956 __IO uint32_t MISR; 00957 __IO uint32_t K0LR; 00958 __IO uint32_t K0RR; 00959 __IO uint32_t K1LR; 00960 __IO uint32_t K1RR; 00961 __IO uint32_t K2LR; 00962 __IO uint32_t K2RR; 00963 __IO uint32_t K3LR; 00964 __IO uint32_t K3RR; 00965 __IO uint32_t IV0LR; 00966 __IO uint32_t IV0RR; 00967 __IO uint32_t IV1LR; 00968 __IO uint32_t IV1RR; 00969 } CRYP_TypeDef; 00970 00975 typedef struct 00976 { 00977 __IO uint32_t CR; 00978 __IO uint32_t DIN; 00979 __IO uint32_t STR; 00980 __IO uint32_t HR[5]; 00981 __IO uint32_t IMR; 00982 __IO uint32_t SR; 00983 uint32_t RESERVED[52]; 00984 __IO uint32_t CSR[51]; 00985 } HASH_TypeDef; 00986 00991 typedef struct 00992 { 00993 __IO uint32_t CR; 00994 __IO uint32_t SR; 00995 __IO uint32_t DR; 00996 } RNG_TypeDef; 00997 01006 #define FLASH_BASE ((uint32_t)0x08000000) 01007 #define SRAM_BASE ((uint32_t)0x20000000) 01008 #define PERIPH_BASE ((uint32_t)0x40000000) 01010 #define SRAM_BB_BASE ((uint32_t)0x22000000) 01011 #define PERIPH_BB_BASE ((uint32_t)0x42000000) 01013 #define FSMC_R_BASE ((uint32_t)0xA0000000) 01016 #define APB1PERIPH_BASE PERIPH_BASE 01017 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) 01018 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) 01019 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) 01020 01022 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 01023 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 01024 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 01025 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 01026 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 01027 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 01028 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) 01029 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) 01030 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) 01031 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 01032 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 01033 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 01034 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 01035 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 01036 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 01037 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 01038 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 01039 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 01040 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 01041 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 01042 #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) 01043 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 01044 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) 01045 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 01046 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 01047 01049 #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) 01050 #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) 01051 #define USART1_BASE (APB2PERIPH_BASE + 0x1000) 01052 #define USART6_BASE (APB2PERIPH_BASE + 0x1400) 01053 #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) 01054 #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) 01055 #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) 01056 #define ADC_BASE (APB2PERIPH_BASE + 0x2300) 01057 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) 01058 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 01059 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) 01060 #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) 01061 #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) 01062 #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) 01063 #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) 01064 01066 #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) 01067 #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) 01068 #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) 01069 #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) 01070 #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) 01071 #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) 01072 #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) 01073 #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) 01074 #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) 01075 #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) 01076 #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) 01077 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) 01078 #define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) 01079 #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) 01080 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) 01081 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) 01082 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) 01083 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) 01084 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) 01085 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) 01086 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) 01087 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) 01088 #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) 01089 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) 01090 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) 01091 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) 01092 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) 01093 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) 01094 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) 01095 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) 01096 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) 01097 #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) 01098 #define ETH_MAC_BASE (ETH_BASE) 01099 #define ETH_MMC_BASE (ETH_BASE + 0x0100) 01100 #define ETH_PTP_BASE (ETH_BASE + 0x0700) 01101 #define ETH_DMA_BASE (ETH_BASE + 0x1000) 01102 01104 #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) 01105 #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) 01106 #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) 01107 #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) 01108 01110 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) 01111 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) 01112 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) 01113 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) 01114 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) 01115 01116 /* Debug MCU registers base address */ 01117 #define DBGMCU_BASE ((uint32_t )0xE0042000) 01118 01126 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 01127 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 01128 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 01129 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 01130 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 01131 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 01132 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 01133 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 01134 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 01135 #define RTC ((RTC_TypeDef *) RTC_BASE) 01136 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 01137 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 01138 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 01139 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 01140 #define USART2 ((USART_TypeDef *) USART2_BASE) 01141 #define USART3 ((USART_TypeDef *) USART3_BASE) 01142 #define UART4 ((USART_TypeDef *) UART4_BASE) 01143 #define UART5 ((USART_TypeDef *) UART5_BASE) 01144 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 01145 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 01146 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 01147 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 01148 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 01149 #define PWR ((PWR_TypeDef *) PWR_BASE) 01150 #define DAC ((DAC_TypeDef *) DAC_BASE) 01151 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 01152 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 01153 #define USART1 ((USART_TypeDef *) USART1_BASE) 01154 #define USART6 ((USART_TypeDef *) USART6_BASE) 01155 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) 01156 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 01157 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 01158 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 01159 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 01160 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01161 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 01162 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 01163 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 01164 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 01165 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 01166 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01167 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01168 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01169 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01170 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01171 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01172 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01173 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 01174 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) 01175 #define CRC ((CRC_TypeDef *) CRC_BASE) 01176 #define RCC ((RCC_TypeDef *) RCC_BASE) 01177 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01178 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01179 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) 01180 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) 01181 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) 01182 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) 01183 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) 01184 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) 01185 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) 01186 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) 01187 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01188 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) 01189 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) 01190 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) 01191 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) 01192 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) 01193 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) 01194 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) 01195 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) 01196 #define ETH ((ETH_TypeDef *) ETH_BASE) 01197 #define DCMI ((DCMI_TypeDef *) DCMI_BASE) 01198 #define CRYP ((CRYP_TypeDef *) CRYP_BASE) 01199 #define HASH ((HASH_TypeDef *) HASH_BASE) 01200 #define RNG ((RNG_TypeDef *) RNG_BASE) 01201 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 01202 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 01203 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) 01204 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) 01205 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) 01206 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01207 01220 /******************************************************************************/ 01221 /* Peripheral Registers_Bits_Definition */ 01222 /******************************************************************************/ 01223 01224 /******************************************************************************/ 01225 /* */ 01226 /* Analog to Digital Converter */ 01227 /* */ 01228 /******************************************************************************/ 01229 /******************** Bit definition for ADC_SR register ********************/ 01230 #define ADC_SR_AWD ((uint8_t)0x01) 01231 #define ADC_SR_EOC ((uint8_t)0x02) 01232 #define ADC_SR_JEOC ((uint8_t)0x04) 01233 #define ADC_SR_JSTRT ((uint8_t)0x08) 01234 #define ADC_SR_STRT ((uint8_t)0x10) 01235 #define ADC_SR_OVR ((uint8_t)0x20) 01237 /******************* Bit definition for ADC_CR1 register ********************/ 01238 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) 01239 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) 01240 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) 01241 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) 01242 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) 01243 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) 01244 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) 01245 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) 01246 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) 01247 #define ADC_CR1_SCAN ((uint32_t)0x00000100) 01248 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) 01249 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) 01250 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) 01251 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) 01252 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) 01253 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) 01254 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) 01255 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) 01256 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) 01257 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) 01258 #define ADC_CR1_RES ((uint32_t)0x03000000) 01259 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) 01260 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) 01261 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) 01263 /******************* Bit definition for ADC_CR2 register ********************/ 01264 #define ADC_CR2_ADON ((uint32_t)0x00000001) 01265 #define ADC_CR2_CONT ((uint32_t)0x00000002) 01266 #define ADC_CR2_DMA ((uint32_t)0x00000100) 01267 #define ADC_CR2_DDS ((uint32_t)0x00000200) 01268 #define ADC_CR2_EOCS ((uint32_t)0x00000400) 01269 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) 01270 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) 01271 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) 01272 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) 01273 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) 01274 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) 01275 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) 01276 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) 01277 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) 01278 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) 01279 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) 01280 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) 01281 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) 01282 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) 01283 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) 01284 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) 01285 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) 01286 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) 01287 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) 01289 /****************** Bit definition for ADC_SMPR1 register *******************/ 01290 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) 01291 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) 01292 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) 01293 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) 01294 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) 01295 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) 01296 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) 01297 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) 01298 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) 01299 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) 01300 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) 01301 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) 01302 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) 01303 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) 01304 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) 01305 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) 01306 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) 01307 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) 01308 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) 01309 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) 01310 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) 01311 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) 01312 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) 01313 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) 01314 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) 01315 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) 01316 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) 01317 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) 01318 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) 01319 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) 01320 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) 01321 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) 01322 #define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) 01323 #define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) 01324 #define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) 01325 #define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) 01327 /****************** Bit definition for ADC_SMPR2 register *******************/ 01328 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) 01329 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) 01330 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) 01331 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) 01332 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) 01333 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) 01334 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) 01335 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) 01336 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) 01337 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) 01338 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) 01339 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) 01340 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) 01341 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) 01342 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) 01343 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) 01344 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) 01345 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) 01346 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) 01347 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) 01348 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) 01349 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) 01350 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) 01351 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) 01352 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) 01353 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) 01354 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) 01355 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) 01356 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) 01357 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) 01358 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) 01359 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) 01360 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) 01361 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) 01362 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) 01363 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) 01364 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) 01365 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) 01366 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) 01367 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) 01369 /****************** Bit definition for ADC_JOFR1 register *******************/ 01370 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) 01372 /****************** Bit definition for ADC_JOFR2 register *******************/ 01373 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) 01375 /****************** Bit definition for ADC_JOFR3 register *******************/ 01376 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) 01378 /****************** Bit definition for ADC_JOFR4 register *******************/ 01379 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) 01381 /******************* Bit definition for ADC_HTR register ********************/ 01382 #define ADC_HTR_HT ((uint16_t)0x0FFF) 01384 /******************* Bit definition for ADC_LTR register ********************/ 01385 #define ADC_LTR_LT ((uint16_t)0x0FFF) 01387 /******************* Bit definition for ADC_SQR1 register *******************/ 01388 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) 01389 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) 01390 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) 01391 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) 01392 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) 01393 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) 01394 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) 01395 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) 01396 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) 01397 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) 01398 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) 01399 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) 01400 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) 01401 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) 01402 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) 01403 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) 01404 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) 01405 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) 01406 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) 01407 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) 01408 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) 01409 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) 01410 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) 01411 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) 01412 #define ADC_SQR1_L ((uint32_t)0x00F00000) 01413 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) 01414 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) 01415 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) 01416 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) 01418 /******************* Bit definition for ADC_SQR2 register *******************/ 01419 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) 01420 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) 01421 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) 01422 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) 01423 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) 01424 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) 01425 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) 01426 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) 01427 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) 01428 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) 01429 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) 01430 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) 01431 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) 01432 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) 01433 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) 01434 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) 01435 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) 01436 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) 01437 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) 01438 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) 01439 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) 01440 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) 01441 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) 01442 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) 01443 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) 01444 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) 01445 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) 01446 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) 01447 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) 01448 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) 01449 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) 01450 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) 01451 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) 01452 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) 01453 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) 01454 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) 01456 /******************* Bit definition for ADC_SQR3 register *******************/ 01457 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) 01458 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) 01459 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) 01460 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) 01461 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) 01462 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) 01463 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) 01464 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) 01465 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) 01466 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) 01467 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) 01468 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) 01469 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) 01470 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) 01471 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) 01472 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) 01473 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) 01474 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) 01475 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) 01476 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) 01477 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) 01478 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) 01479 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) 01480 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) 01481 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) 01482 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) 01483 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) 01484 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) 01485 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) 01486 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) 01487 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) 01488 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) 01489 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) 01490 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) 01491 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) 01492 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) 01494 /******************* Bit definition for ADC_JSQR register *******************/ 01495 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) 01496 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) 01497 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) 01498 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) 01499 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) 01500 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) 01501 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) 01502 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) 01503 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) 01504 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) 01505 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) 01506 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) 01507 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) 01508 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) 01509 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) 01510 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) 01511 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) 01512 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) 01513 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) 01514 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) 01515 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) 01516 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) 01517 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) 01518 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) 01519 #define ADC_JSQR_JL ((uint32_t)0x00300000) 01520 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) 01521 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) 01523 /******************* Bit definition for ADC_JDR1 register *******************/ 01524 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) 01526 /******************* Bit definition for ADC_JDR2 register *******************/ 01527 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) 01529 /******************* Bit definition for ADC_JDR3 register *******************/ 01530 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) 01532 /******************* Bit definition for ADC_JDR4 register *******************/ 01533 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) 01535 /******************** Bit definition for ADC_DR register ********************/ 01536 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) 01537 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) 01539 /******************* Bit definition for ADC_CSR register ********************/ 01540 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) 01541 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) 01542 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) 01543 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) 01544 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) 01545 #define ADC_CSR_DOVR1 ((uint32_t)0x00000020) 01546 #define ADC_CSR_AWD2 ((uint32_t)0x00000100) 01547 #define ADC_CSR_EOC2 ((uint32_t)0x00000200) 01548 #define ADC_CSR_JEOC2 ((uint32_t)0x00000400) 01549 #define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) 01550 #define ADC_CSR_STRT2 ((uint32_t)0x00001000) 01551 #define ADC_CSR_DOVR2 ((uint32_t)0x00002000) 01552 #define ADC_CSR_AWD3 ((uint32_t)0x00010000) 01553 #define ADC_CSR_EOC3 ((uint32_t)0x00020000) 01554 #define ADC_CSR_JEOC3 ((uint32_t)0x00040000) 01555 #define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) 01556 #define ADC_CSR_STRT3 ((uint32_t)0x00100000) 01557 #define ADC_CSR_DOVR3 ((uint32_t)0x00200000) 01559 /******************* Bit definition for ADC_CCR register ********************/ 01560 #define ADC_CCR_MULTI ((uint32_t)0x0000001F) 01561 #define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) 01562 #define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) 01563 #define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) 01564 #define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) 01565 #define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) 01566 #define ADC_CCR_DELAY ((uint32_t)0x00000F00) 01567 #define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) 01568 #define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) 01569 #define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) 01570 #define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) 01571 #define ADC_CCR_DDS ((uint32_t)0x00002000) 01572 #define ADC_CCR_DMA ((uint32_t)0x0000C000) 01573 #define ADC_CCR_DMA_0 ((uint32_t)0x00004000) 01574 #define ADC_CCR_DMA_1 ((uint32_t)0x00008000) 01575 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) 01576 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) 01577 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) 01578 #define ADC_CCR_VBATE ((uint32_t)0x00400000) 01579 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) 01581 /******************* Bit definition for ADC_CDR register ********************/ 01582 #define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) 01583 #define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) 01585 /******************************************************************************/ 01586 /* */ 01587 /* Controller Area Network */ 01588 /* */ 01589 /******************************************************************************/ 01591 /******************* Bit definition for CAN_MCR register ********************/ 01592 #define CAN_MCR_INRQ ((uint16_t)0x0001) 01593 #define CAN_MCR_SLEEP ((uint16_t)0x0002) 01594 #define CAN_MCR_TXFP ((uint16_t)0x0004) 01595 #define CAN_MCR_RFLM ((uint16_t)0x0008) 01596 #define CAN_MCR_NART ((uint16_t)0x0010) 01597 #define CAN_MCR_AWUM ((uint16_t)0x0020) 01598 #define CAN_MCR_ABOM ((uint16_t)0x0040) 01599 #define CAN_MCR_TTCM ((uint16_t)0x0080) 01600 #define CAN_MCR_RESET ((uint16_t)0x8000) 01602 /******************* Bit definition for CAN_MSR register ********************/ 01603 #define CAN_MSR_INAK ((uint16_t)0x0001) 01604 #define CAN_MSR_SLAK ((uint16_t)0x0002) 01605 #define CAN_MSR_ERRI ((uint16_t)0x0004) 01606 #define CAN_MSR_WKUI ((uint16_t)0x0008) 01607 #define CAN_MSR_SLAKI ((uint16_t)0x0010) 01608 #define CAN_MSR_TXM ((uint16_t)0x0100) 01609 #define CAN_MSR_RXM ((uint16_t)0x0200) 01610 #define CAN_MSR_SAMP ((uint16_t)0x0400) 01611 #define CAN_MSR_RX ((uint16_t)0x0800) 01613 /******************* Bit definition for CAN_TSR register ********************/ 01614 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) 01615 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) 01616 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) 01617 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) 01618 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) 01619 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) 01620 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) 01621 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) 01622 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) 01623 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) 01624 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) 01625 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) 01626 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) 01627 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) 01628 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) 01629 #define CAN_TSR_CODE ((uint32_t)0x03000000) 01631 #define CAN_TSR_TME ((uint32_t)0x1C000000) 01632 #define CAN_TSR_TME0 ((uint32_t)0x04000000) 01633 #define CAN_TSR_TME1 ((uint32_t)0x08000000) 01634 #define CAN_TSR_TME2 ((uint32_t)0x10000000) 01636 #define CAN_TSR_LOW ((uint32_t)0xE0000000) 01637 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) 01638 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) 01639 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) 01641 /******************* Bit definition for CAN_RF0R register *******************/ 01642 #define CAN_RF0R_FMP0 ((uint8_t)0x03) 01643 #define CAN_RF0R_FULL0 ((uint8_t)0x08) 01644 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) 01645 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) 01647 /******************* Bit definition for CAN_RF1R register *******************/ 01648 #define CAN_RF1R_FMP1 ((uint8_t)0x03) 01649 #define CAN_RF1R_FULL1 ((uint8_t)0x08) 01650 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) 01651 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) 01653 /******************** Bit definition for CAN_IER register *******************/ 01654 #define CAN_IER_TMEIE ((uint32_t)0x00000001) 01655 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) 01656 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) 01657 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) 01658 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) 01659 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) 01660 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) 01661 #define CAN_IER_EWGIE ((uint32_t)0x00000100) 01662 #define CAN_IER_EPVIE ((uint32_t)0x00000200) 01663 #define CAN_IER_BOFIE ((uint32_t)0x00000400) 01664 #define CAN_IER_LECIE ((uint32_t)0x00000800) 01665 #define CAN_IER_ERRIE ((uint32_t)0x00008000) 01666 #define CAN_IER_WKUIE ((uint32_t)0x00010000) 01667 #define CAN_IER_SLKIE ((uint32_t)0x00020000) 01669 /******************** Bit definition for CAN_ESR register *******************/ 01670 #define CAN_ESR_EWGF ((uint32_t)0x00000001) 01671 #define CAN_ESR_EPVF ((uint32_t)0x00000002) 01672 #define CAN_ESR_BOFF ((uint32_t)0x00000004) 01674 #define CAN_ESR_LEC ((uint32_t)0x00000070) 01675 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) 01676 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) 01677 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) 01679 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) 01680 #define CAN_ESR_REC ((uint32_t)0xFF000000) 01682 /******************* Bit definition for CAN_BTR register ********************/ 01683 #define CAN_BTR_BRP ((uint32_t)0x000003FF) 01684 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) 01685 #define CAN_BTR_TS2 ((uint32_t)0x00700000) 01686 #define CAN_BTR_SJW ((uint32_t)0x03000000) 01687 #define CAN_BTR_LBKM ((uint32_t)0x40000000) 01688 #define CAN_BTR_SILM ((uint32_t)0x80000000) 01691 /****************** Bit definition for CAN_TI0R register ********************/ 01692 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) 01693 #define CAN_TI0R_RTR ((uint32_t)0x00000002) 01694 #define CAN_TI0R_IDE ((uint32_t)0x00000004) 01695 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) 01696 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) 01698 /****************** Bit definition for CAN_TDT0R register *******************/ 01699 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) 01700 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) 01701 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) 01703 /****************** Bit definition for CAN_TDL0R register *******************/ 01704 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) 01705 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) 01706 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) 01707 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) 01709 /****************** Bit definition for CAN_TDH0R register *******************/ 01710 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) 01711 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) 01712 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) 01713 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) 01715 /******************* Bit definition for CAN_TI1R register *******************/ 01716 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) 01717 #define CAN_TI1R_RTR ((uint32_t)0x00000002) 01718 #define CAN_TI1R_IDE ((uint32_t)0x00000004) 01719 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) 01720 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) 01722 /******************* Bit definition for CAN_TDT1R register ******************/ 01723 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) 01724 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) 01725 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) 01727 /******************* Bit definition for CAN_TDL1R register ******************/ 01728 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) 01729 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) 01730 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) 01731 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) 01733 /******************* Bit definition for CAN_TDH1R register ******************/ 01734 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) 01735 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) 01736 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) 01737 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) 01739 /******************* Bit definition for CAN_TI2R register *******************/ 01740 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) 01741 #define CAN_TI2R_RTR ((uint32_t)0x00000002) 01742 #define CAN_TI2R_IDE ((uint32_t)0x00000004) 01743 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) 01744 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) 01746 /******************* Bit definition for CAN_TDT2R register ******************/ 01747 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) 01748 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) 01749 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) 01751 /******************* Bit definition for CAN_TDL2R register ******************/ 01752 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) 01753 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) 01754 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) 01755 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) 01757 /******************* Bit definition for CAN_TDH2R register ******************/ 01758 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) 01759 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) 01760 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) 01761 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) 01763 /******************* Bit definition for CAN_RI0R register *******************/ 01764 #define CAN_RI0R_RTR ((uint32_t)0x00000002) 01765 #define CAN_RI0R_IDE ((uint32_t)0x00000004) 01766 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) 01767 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) 01769 /******************* Bit definition for CAN_RDT0R register ******************/ 01770 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) 01771 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) 01772 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 01774 /******************* Bit definition for CAN_RDL0R register ******************/ 01775 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 01776 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 01777 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) 01778 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 01780 /******************* Bit definition for CAN_RDH0R register ******************/ 01781 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 01782 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 01783 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 01784 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) 01786 /******************* Bit definition for CAN_RI1R register *******************/ 01787 #define CAN_RI1R_RTR ((uint32_t)0x00000002) 01788 #define CAN_RI1R_IDE ((uint32_t)0x00000004) 01789 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) 01790 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) 01792 /******************* Bit definition for CAN_RDT1R register ******************/ 01793 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) 01794 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) 01795 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) 01797 /******************* Bit definition for CAN_RDL1R register ******************/ 01798 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) 01799 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) 01800 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) 01801 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) 01803 /******************* Bit definition for CAN_RDH1R register ******************/ 01804 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) 01805 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) 01806 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) 01807 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) 01810 /******************* Bit definition for CAN_FMR register ********************/ 01811 #define CAN_FMR_FINIT ((uint8_t)0x01) 01813 /******************* Bit definition for CAN_FM1R register *******************/ 01814 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) 01815 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) 01816 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) 01817 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) 01818 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) 01819 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) 01820 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) 01821 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) 01822 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) 01823 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) 01824 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) 01825 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) 01826 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) 01827 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) 01828 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) 01830 /******************* Bit definition for CAN_FS1R register *******************/ 01831 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) 01832 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) 01833 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) 01834 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) 01835 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) 01836 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) 01837 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) 01838 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) 01839 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) 01840 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) 01841 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) 01842 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) 01843 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) 01844 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) 01845 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) 01847 /****************** Bit definition for CAN_FFA1R register *******************/ 01848 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) 01849 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) 01850 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) 01851 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) 01852 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) 01853 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) 01854 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) 01855 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) 01856 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) 01857 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) 01858 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) 01859 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) 01860 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) 01861 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) 01862 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) 01864 /******************* Bit definition for CAN_FA1R register *******************/ 01865 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) 01866 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) 01867 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) 01868 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) 01869 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) 01870 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) 01871 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) 01872 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) 01873 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) 01874 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) 01875 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) 01876 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) 01877 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) 01878 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) 01879 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) 01881 /******************* Bit definition for CAN_F0R1 register *******************/ 01882 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) 01883 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) 01884 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) 01885 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) 01886 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) 01887 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) 01888 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) 01889 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) 01890 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) 01891 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) 01892 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) 01893 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) 01894 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) 01895 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) 01896 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) 01897 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) 01898 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) 01899 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) 01900 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) 01901 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) 01902 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) 01903 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) 01904 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) 01905 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) 01906 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) 01907 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) 01908 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) 01909 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) 01910 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) 01911 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) 01912 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) 01913 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) 01915 /******************* Bit definition for CAN_F1R1 register *******************/ 01916 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) 01917 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) 01918 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) 01919 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) 01920 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) 01921 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) 01922 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) 01923 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) 01924 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) 01925 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) 01926 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) 01927 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) 01928 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) 01929 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) 01930 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) 01931 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) 01932 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) 01933 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) 01934 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) 01935 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) 01936 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) 01937 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) 01938 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) 01939 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) 01940 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) 01941 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) 01942 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) 01943 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) 01944 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) 01945 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) 01946 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) 01947 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) 01949 /******************* Bit definition for CAN_F2R1 register *******************/ 01950 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) 01951 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) 01952 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) 01953 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) 01954 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) 01955 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) 01956 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) 01957 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) 01958 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) 01959 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) 01960 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) 01961 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) 01962 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) 01963 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) 01964 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) 01965 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) 01966 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) 01967 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) 01968 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) 01969 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) 01970 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) 01971 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) 01972 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) 01973 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) 01974 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) 01975 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) 01976 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) 01977 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) 01978 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) 01979 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) 01980 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) 01981 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) 01983 /******************* Bit definition for CAN_F3R1 register *******************/ 01984 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) 01985 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) 01986 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) 01987 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) 01988 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) 01989 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) 01990 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) 01991 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) 01992 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) 01993 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) 01994 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) 01995 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) 01996 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) 01997 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) 01998 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) 01999 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) 02000 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) 02001 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) 02002 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) 02003 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) 02004 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) 02005 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) 02006 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) 02007 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) 02008 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) 02009 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) 02010 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) 02011 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) 02012 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) 02013 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) 02014 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) 02015 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) 02017 /******************* Bit definition for CAN_F4R1 register *******************/ 02018 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) 02019 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) 02020 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) 02021 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) 02022 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) 02023 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) 02024 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) 02025 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) 02026 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) 02027 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) 02028 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) 02029 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) 02030 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) 02031 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) 02032 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) 02033 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) 02034 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) 02035 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) 02036 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) 02037 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) 02038 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) 02039 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) 02040 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) 02041 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) 02042 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) 02043 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) 02044 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) 02045 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) 02046 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) 02047 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) 02048 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) 02049 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) 02051 /******************* Bit definition for CAN_F5R1 register *******************/ 02052 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) 02053 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) 02054 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) 02055 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) 02056 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) 02057 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) 02058 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) 02059 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) 02060 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) 02061 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) 02062 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) 02063 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) 02064 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) 02065 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) 02066 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) 02067 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) 02068 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) 02069 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) 02070 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) 02071 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) 02072 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) 02073 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) 02074 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) 02075 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) 02076 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) 02077 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) 02078 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) 02079 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) 02080 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) 02081 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) 02082 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) 02083 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) 02085 /******************* Bit definition for CAN_F6R1 register *******************/ 02086 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) 02087 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) 02088 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) 02089 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) 02090 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) 02091 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) 02092 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) 02093 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) 02094 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) 02095 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) 02096 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) 02097 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) 02098 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) 02099 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) 02100 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) 02101 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) 02102 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) 02103 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) 02104 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) 02105 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) 02106 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) 02107 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) 02108 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) 02109 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) 02110 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) 02111 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) 02112 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) 02113 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) 02114 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) 02115 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) 02116 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) 02117 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) 02119 /******************* Bit definition for CAN_F7R1 register *******************/ 02120 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) 02121 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) 02122 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) 02123 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) 02124 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) 02125 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) 02126 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) 02127 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) 02128 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) 02129 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) 02130 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) 02131 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) 02132 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) 02133 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) 02134 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) 02135 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) 02136 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) 02137 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) 02138 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) 02139 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) 02140 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) 02141 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) 02142 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) 02143 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) 02144 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) 02145 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) 02146 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) 02147 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) 02148 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) 02149 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) 02150 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) 02151 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) 02153 /******************* Bit definition for CAN_F8R1 register *******************/ 02154 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) 02155 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) 02156 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) 02157 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) 02158 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) 02159 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) 02160 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) 02161 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) 02162 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) 02163 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) 02164 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) 02165 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) 02166 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) 02167 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) 02168 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) 02169 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) 02170 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) 02171 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) 02172 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) 02173 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) 02174 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) 02175 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) 02176 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) 02177 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) 02178 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) 02179 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) 02180 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) 02181 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) 02182 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) 02183 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) 02184 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) 02185 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) 02187 /******************* Bit definition for CAN_F9R1 register *******************/ 02188 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) 02189 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) 02190 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) 02191 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) 02192 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) 02193 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) 02194 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) 02195 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) 02196 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) 02197 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) 02198 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) 02199 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) 02200 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) 02201 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) 02202 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) 02203 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) 02204 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) 02205 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) 02206 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) 02207 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) 02208 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) 02209 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) 02210 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) 02211 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) 02212 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) 02213 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) 02214 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) 02215 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) 02216 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) 02217 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) 02218 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) 02219 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) 02221 /******************* Bit definition for CAN_F10R1 register ******************/ 02222 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) 02223 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) 02224 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) 02225 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) 02226 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) 02227 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) 02228 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) 02229 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) 02230 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) 02231 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) 02232 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) 02233 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) 02234 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) 02235 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) 02236 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) 02237 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) 02238 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) 02239 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) 02240 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) 02241 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) 02242 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) 02243 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) 02244 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) 02245 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) 02246 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) 02247 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) 02248 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) 02249 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) 02250 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) 02251 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) 02252 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) 02253 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) 02255 /******************* Bit definition for CAN_F11R1 register ******************/ 02256 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) 02257 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) 02258 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) 02259 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) 02260 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) 02261 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) 02262 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) 02263 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) 02264 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) 02265 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) 02266 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) 02267 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) 02268 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) 02269 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) 02270 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) 02271 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) 02272 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) 02273 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) 02274 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) 02275 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) 02276 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) 02277 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) 02278 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) 02279 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) 02280 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) 02281 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) 02282 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) 02283 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) 02284 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) 02285 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) 02286 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) 02287 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) 02289 /******************* Bit definition for CAN_F12R1 register ******************/ 02290 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) 02291 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) 02292 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) 02293 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) 02294 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) 02295 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) 02296 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) 02297 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) 02298 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) 02299 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) 02300 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) 02301 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) 02302 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) 02303 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) 02304 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) 02305 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) 02306 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) 02307 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) 02308 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) 02309 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) 02310 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) 02311 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) 02312 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) 02313 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) 02314 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) 02315 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) 02316 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) 02317 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) 02318 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) 02319 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) 02320 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) 02321 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) 02323 /******************* Bit definition for CAN_F13R1 register ******************/ 02324 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) 02325 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) 02326 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) 02327 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) 02328 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) 02329 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) 02330 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) 02331 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) 02332 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) 02333 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) 02334 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) 02335 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) 02336 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) 02337 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) 02338 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) 02339 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) 02340 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) 02341 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) 02342 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) 02343 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) 02344 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) 02345 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) 02346 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) 02347 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) 02348 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) 02349 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) 02350 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) 02351 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) 02352 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) 02353 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) 02354 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) 02355 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) 02357 /******************* Bit definition for CAN_F0R2 register *******************/ 02358 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) 02359 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) 02360 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) 02361 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) 02362 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) 02363 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) 02364 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) 02365 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) 02366 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) 02367 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) 02368 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) 02369 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) 02370 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) 02371 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) 02372 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) 02373 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) 02374 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) 02375 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) 02376 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) 02377 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) 02378 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) 02379 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) 02380 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) 02381 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) 02382 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) 02383 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) 02384 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) 02385 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) 02386 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) 02387 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) 02388 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) 02389 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) 02391 /******************* Bit definition for CAN_F1R2 register *******************/ 02392 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) 02393 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) 02394 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) 02395 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) 02396 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) 02397 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) 02398 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) 02399 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) 02400 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) 02401 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) 02402 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) 02403 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) 02404 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) 02405 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) 02406 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) 02407 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) 02408 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) 02409 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) 02410 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) 02411 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) 02412 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) 02413 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) 02414 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) 02415 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) 02416 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) 02417 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) 02418 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) 02419 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) 02420 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) 02421 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) 02422 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) 02423 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) 02425 /******************* Bit definition for CAN_F2R2 register *******************/ 02426 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) 02427 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) 02428 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) 02429 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) 02430 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) 02431 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) 02432 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) 02433 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) 02434 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) 02435 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) 02436 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) 02437 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) 02438 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) 02439 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) 02440 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) 02441 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) 02442 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) 02443 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) 02444 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) 02445 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) 02446 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) 02447 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) 02448 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) 02449 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) 02450 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) 02451 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) 02452 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) 02453 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) 02454 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) 02455 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) 02456 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) 02457 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) 02459 /******************* Bit definition for CAN_F3R2 register *******************/ 02460 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) 02461 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) 02462 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) 02463 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) 02464 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) 02465 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) 02466 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) 02467 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) 02468 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) 02469 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) 02470 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) 02471 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) 02472 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) 02473 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) 02474 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) 02475 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) 02476 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) 02477 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) 02478 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) 02479 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) 02480 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) 02481 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) 02482 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) 02483 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) 02484 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) 02485 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) 02486 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) 02487 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) 02488 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) 02489 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) 02490 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) 02491 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) 02493 /******************* Bit definition for CAN_F4R2 register *******************/ 02494 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) 02495 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) 02496 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) 02497 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) 02498 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) 02499 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) 02500 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) 02501 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) 02502 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) 02503 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) 02504 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) 02505 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) 02506 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) 02507 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) 02508 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) 02509 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) 02510 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) 02511 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) 02512 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) 02513 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) 02514 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) 02515 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) 02516 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) 02517 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) 02518 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) 02519 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) 02520 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) 02521 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) 02522 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) 02523 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) 02524 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) 02525 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) 02527 /******************* Bit definition for CAN_F5R2 register *******************/ 02528 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) 02529 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) 02530 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) 02531 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) 02532 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) 02533 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) 02534 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) 02535 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) 02536 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) 02537 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) 02538 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) 02539 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) 02540 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) 02541 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) 02542 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) 02543 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) 02544 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) 02545 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) 02546 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) 02547 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) 02548 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) 02549 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) 02550 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) 02551 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) 02552 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) 02553 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) 02554 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) 02555 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) 02556 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) 02557 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) 02558 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) 02559 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) 02561 /******************* Bit definition for CAN_F6R2 register *******************/ 02562 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) 02563 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) 02564 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) 02565 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) 02566 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) 02567 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) 02568 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) 02569 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) 02570 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) 02571 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) 02572 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) 02573 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) 02574 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) 02575 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) 02576 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) 02577 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) 02578 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) 02579 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) 02580 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) 02581 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) 02582 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) 02583 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) 02584 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) 02585 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) 02586 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) 02587 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) 02588 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) 02589 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) 02590 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) 02591 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) 02592 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) 02593 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) 02595 /******************* Bit definition for CAN_F7R2 register *******************/ 02596 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) 02597 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) 02598 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) 02599 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) 02600 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) 02601 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) 02602 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) 02603 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) 02604 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) 02605 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) 02606 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) 02607 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) 02608 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) 02609 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) 02610 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) 02611 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) 02612 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) 02613 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) 02614 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) 02615 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) 02616 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) 02617 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) 02618 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) 02619 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) 02620 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) 02621 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) 02622 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) 02623 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) 02624 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) 02625 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) 02626 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) 02627 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) 02629 /******************* Bit definition for CAN_F8R2 register *******************/ 02630 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) 02631 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) 02632 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) 02633 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) 02634 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) 02635 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) 02636 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) 02637 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) 02638 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) 02639 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) 02640 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) 02641 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) 02642 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) 02643 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) 02644 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) 02645 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) 02646 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) 02647 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) 02648 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) 02649 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) 02650 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) 02651 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) 02652 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) 02653 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) 02654 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) 02655 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) 02656 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) 02657 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) 02658 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) 02659 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) 02660 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) 02661 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) 02663 /******************* Bit definition for CAN_F9R2 register *******************/ 02664 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) 02665 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) 02666 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) 02667 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) 02668 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) 02669 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) 02670 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) 02671 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) 02672 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) 02673 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) 02674 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) 02675 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) 02676 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) 02677 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) 02678 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) 02679 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) 02680 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) 02681 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) 02682 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) 02683 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) 02684 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) 02685 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) 02686 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) 02687 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) 02688 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) 02689 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) 02690 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) 02691 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) 02692 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) 02693 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) 02694 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) 02695 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) 02697 /******************* Bit definition for CAN_F10R2 register ******************/ 02698 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) 02699 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) 02700 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) 02701 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) 02702 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) 02703 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) 02704 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) 02705 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) 02706 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) 02707 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) 02708 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) 02709 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) 02710 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) 02711 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) 02712 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) 02713 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) 02714 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) 02715 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) 02716 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) 02717 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) 02718 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) 02719 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) 02720 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) 02721 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) 02722 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) 02723 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) 02724 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) 02725 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) 02726 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) 02727 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) 02728 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) 02729 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) 02731 /******************* Bit definition for CAN_F11R2 register ******************/ 02732 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) 02733 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) 02734 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) 02735 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) 02736 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) 02737 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) 02738 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) 02739 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) 02740 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) 02741 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) 02742 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) 02743 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) 02744 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) 02745 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) 02746 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) 02747 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) 02748 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) 02749 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) 02750 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) 02751 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) 02752 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) 02753 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) 02754 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) 02755 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) 02756 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) 02757 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) 02758 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) 02759 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) 02760 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) 02761 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) 02762 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) 02763 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) 02765 /******************* Bit definition for CAN_F12R2 register ******************/ 02766 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) 02767 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) 02768 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) 02769 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) 02770 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) 02771 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) 02772 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) 02773 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) 02774 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) 02775 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) 02776 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) 02777 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) 02778 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) 02779 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) 02780 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) 02781 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) 02782 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) 02783 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) 02784 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) 02785 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) 02786 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) 02787 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) 02788 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) 02789 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) 02790 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) 02791 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) 02792 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) 02793 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) 02794 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) 02795 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) 02796 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) 02797 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) 02799 /******************* Bit definition for CAN_F13R2 register ******************/ 02800 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) 02801 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) 02802 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) 02803 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) 02804 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) 02805 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) 02806 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) 02807 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) 02808 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) 02809 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) 02810 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) 02811 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) 02812 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) 02813 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) 02814 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) 02815 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) 02816 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) 02817 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) 02818 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) 02819 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) 02820 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) 02821 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) 02822 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) 02823 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) 02824 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) 02825 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) 02826 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) 02827 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) 02828 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) 02829 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) 02830 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) 02831 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) 02833 /******************************************************************************/ 02834 /* */ 02835 /* CRC calculation unit */ 02836 /* */ 02837 /******************************************************************************/ 02838 /******************* Bit definition for CRC_DR register *********************/ 02839 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) 02842 /******************* Bit definition for CRC_IDR register ********************/ 02843 #define CRC_IDR_IDR ((uint8_t)0xFF) 02846 /******************** Bit definition for CRC_CR register ********************/ 02847 #define CRC_CR_RESET ((uint8_t)0x01) 02849 /******************************************************************************/ 02850 /* */ 02851 /* Crypto Processor */ 02852 /* */ 02853 /******************************************************************************/ 02854 /******************* Bits definition for CRYP_CR register ********************/ 02855 #define CRYP_CR_ALGODIR ((uint32_t)0x00000004) 02856 02857 #define CRYP_CR_ALGOMODE ((uint32_t)0x00000038) 02858 #define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008) 02859 #define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010) 02860 #define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020) 02861 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000) 02862 #define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008) 02863 #define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010) 02864 #define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018) 02865 #define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020) 02866 #define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028) 02867 #define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030) 02868 #define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038) 02869 02870 #define CRYP_CR_DATATYPE ((uint32_t)0x000000C0) 02871 #define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040) 02872 #define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080) 02873 #define CRYP_CR_KEYSIZE ((uint32_t)0x00000300) 02874 #define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100) 02875 #define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200) 02876 #define CRYP_CR_FFLUSH ((uint32_t)0x00004000) 02877 #define CRYP_CR_CRYPEN ((uint32_t)0x00008000) 02878 /****************** Bits definition for CRYP_SR register *********************/ 02879 #define CRYP_SR_IFEM ((uint32_t)0x00000001) 02880 #define CRYP_SR_IFNF ((uint32_t)0x00000002) 02881 #define CRYP_SR_OFNE ((uint32_t)0x00000004) 02882 #define CRYP_SR_OFFU ((uint32_t)0x00000008) 02883 #define CRYP_SR_BUSY ((uint32_t)0x00000010) 02884 /****************** Bits definition for CRYP_DMACR register ******************/ 02885 #define CRYP_DMACR_DIEN ((uint32_t)0x00000001) 02886 #define CRYP_DMACR_DOEN ((uint32_t)0x00000002) 02887 /***************** Bits definition for CRYP_IMSCR register ******************/ 02888 #define CRYP_IMSCR_INIM ((uint32_t)0x00000001) 02889 #define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002) 02890 /****************** Bits definition for CRYP_RISR register *******************/ 02891 #define CRYP_RISR_OUTRIS ((uint32_t)0x00000001) 02892 #define CRYP_RISR_INRIS ((uint32_t)0x00000002) 02893 /****************** Bits definition for CRYP_MISR register *******************/ 02894 #define CRYP_MISR_INMIS ((uint32_t)0x00000001) 02895 #define CRYP_MISR_OUTMIS ((uint32_t)0x00000002) 02896 02897 /******************************************************************************/ 02898 /* */ 02899 /* Digital to Analog Converter */ 02900 /* */ 02901 /******************************************************************************/ 02902 /******************** Bit definition for DAC_CR register ********************/ 02903 #define DAC_CR_EN1 ((uint32_t)0x00000001) 02904 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) 02905 #define DAC_CR_TEN1 ((uint32_t)0x00000004) 02907 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) 02908 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) 02909 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) 02910 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) 02912 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) 02913 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) 02914 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) 02916 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) 02917 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) 02918 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) 02919 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) 02920 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) 02922 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) 02923 #define DAC_CR_EN2 ((uint32_t)0x00010000) 02924 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) 02925 #define DAC_CR_TEN2 ((uint32_t)0x00040000) 02927 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) 02928 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) 02929 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) 02930 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) 02932 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) 02933 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) 02934 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) 02936 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) 02937 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) 02938 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) 02939 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) 02940 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) 02942 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) 02944 /***************** Bit definition for DAC_SWTRIGR register ******************/ 02945 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) 02946 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) 02948 /***************** Bit definition for DAC_DHR12R1 register ******************/ 02949 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) 02951 /***************** Bit definition for DAC_DHR12L1 register ******************/ 02952 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) 02954 /****************** Bit definition for DAC_DHR8R1 register ******************/ 02955 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) 02957 /***************** Bit definition for DAC_DHR12R2 register ******************/ 02958 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) 02960 /***************** Bit definition for DAC_DHR12L2 register ******************/ 02961 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) 02963 /****************** Bit definition for DAC_DHR8R2 register ******************/ 02964 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) 02966 /***************** Bit definition for DAC_DHR12RD register ******************/ 02967 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) 02968 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) 02970 /***************** Bit definition for DAC_DHR12LD register ******************/ 02971 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) 02972 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) 02974 /****************** Bit definition for DAC_DHR8RD register ******************/ 02975 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) 02976 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) 02978 /******************* Bit definition for DAC_DOR1 register *******************/ 02979 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) 02981 /******************* Bit definition for DAC_DOR2 register *******************/ 02982 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) 02984 /******************** Bit definition for DAC_SR register ********************/ 02985 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) 02986 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) 02988 /******************************************************************************/ 02989 /* */ 02990 /* Debug MCU */ 02991 /* */ 02992 /******************************************************************************/ 02993 02994 /******************************************************************************/ 02995 /* */ 02996 /* DCMI */ 02997 /* */ 02998 /******************************************************************************/ 02999 /******************** Bits definition for DCMI_CR register ******************/ 03000 #define DCMI_CR_CAPTURE ((uint32_t)0x00000001) 03001 #define DCMI_CR_CM ((uint32_t)0x00000002) 03002 #define DCMI_CR_CROP ((uint32_t)0x00000004) 03003 #define DCMI_CR_JPEG ((uint32_t)0x00000008) 03004 #define DCMI_CR_ESS ((uint32_t)0x00000010) 03005 #define DCMI_CR_PCKPOL ((uint32_t)0x00000020) 03006 #define DCMI_CR_HSPOL ((uint32_t)0x00000040) 03007 #define DCMI_CR_VSPOL ((uint32_t)0x00000080) 03008 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100) 03009 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200) 03010 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400) 03011 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800) 03012 #define DCMI_CR_CRE ((uint32_t)0x00001000) 03013 #define DCMI_CR_ENABLE ((uint32_t)0x00004000) 03014 03015 /******************** Bits definition for DCMI_SR register ******************/ 03016 #define DCMI_SR_HSYNC ((uint32_t)0x00000001) 03017 #define DCMI_SR_VSYNC ((uint32_t)0x00000002) 03018 #define DCMI_SR_FNE ((uint32_t)0x00000004) 03019 03020 /******************** Bits definition for DCMI_RISR register ****************/ 03021 #define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001) 03022 #define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002) 03023 #define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004) 03024 #define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008) 03025 #define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010) 03026 03027 /******************** Bits definition for DCMI_IER register *****************/ 03028 #define DCMI_IER_FRAME_IE ((uint32_t)0x00000001) 03029 #define DCMI_IER_OVF_IE ((uint32_t)0x00000002) 03030 #define DCMI_IER_ERR_IE ((uint32_t)0x00000004) 03031 #define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008) 03032 #define DCMI_IER_LINE_IE ((uint32_t)0x00000010) 03033 03034 /******************** Bits definition for DCMI_MISR register ****************/ 03035 #define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001) 03036 #define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002) 03037 #define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004) 03038 #define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008) 03039 #define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010) 03040 03041 /******************** Bits definition for DCMI_ICR register *****************/ 03042 #define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001) 03043 #define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002) 03044 #define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004) 03045 #define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008) 03046 #define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010) 03047 03048 /******************************************************************************/ 03049 /* */ 03050 /* DMA Controller */ 03051 /* */ 03052 /******************************************************************************/ 03053 /******************** Bits definition for DMA_SxCR register *****************/ 03054 #define DMA_SxCR_CHSEL ((uint32_t)0x0E000000) 03055 #define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000) 03056 #define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000) 03057 #define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) 03058 #define DMA_SxCR_MBURST ((uint32_t)0x01800000) 03059 #define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000) 03060 #define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000) 03061 #define DMA_SxCR_PBURST ((uint32_t)0x00600000) 03062 #define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000) 03063 #define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000) 03064 #define DMA_SxCR_ACK ((uint32_t)0x00100000) 03065 #define DMA_SxCR_CT ((uint32_t)0x00080000) 03066 #define DMA_SxCR_DBM ((uint32_t)0x00040000) 03067 #define DMA_SxCR_PL ((uint32_t)0x00030000) 03068 #define DMA_SxCR_PL_0 ((uint32_t)0x00010000) 03069 #define DMA_SxCR_PL_1 ((uint32_t)0x00020000) 03070 #define DMA_SxCR_PINCOS ((uint32_t)0x00008000) 03071 #define DMA_SxCR_MSIZE ((uint32_t)0x00006000) 03072 #define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000) 03073 #define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000) 03074 #define DMA_SxCR_PSIZE ((uint32_t)0x00001800) 03075 #define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800) 03076 #define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000) 03077 #define DMA_SxCR_MINC ((uint32_t)0x00000400) 03078 #define DMA_SxCR_PINC ((uint32_t)0x00000200) 03079 #define DMA_SxCR_CIRC ((uint32_t)0x00000100) 03080 #define DMA_SxCR_DIR ((uint32_t)0x000000C0) 03081 #define DMA_SxCR_DIR_0 ((uint32_t)0x00000040) 03082 #define DMA_SxCR_DIR_1 ((uint32_t)0x00000080) 03083 #define DMA_SxCR_PFCTRL ((uint32_t)0x00000020) 03084 #define DMA_SxCR_TCIE ((uint32_t)0x00000010) 03085 #define DMA_SxCR_HTIE ((uint32_t)0x00000008) 03086 #define DMA_SxCR_TEIE ((uint32_t)0x00000004) 03087 #define DMA_SxCR_DMEIE ((uint32_t)0x00000002) 03088 #define DMA_SxCR_EN ((uint32_t)0x00000001) 03089 03090 /******************** Bits definition for DMA_SxCNDTR register **************/ 03091 #define DMA_SxNDT ((uint32_t)0x0000FFFF) 03092 #define DMA_SxNDT_0 ((uint32_t)0x00000001) 03093 #define DMA_SxNDT_1 ((uint32_t)0x00000002) 03094 #define DMA_SxNDT_2 ((uint32_t)0x00000004) 03095 #define DMA_SxNDT_3 ((uint32_t)0x00000008) 03096 #define DMA_SxNDT_4 ((uint32_t)0x00000010) 03097 #define DMA_SxNDT_5 ((uint32_t)0x00000020) 03098 #define DMA_SxNDT_6 ((uint32_t)0x00000040) 03099 #define DMA_SxNDT_7 ((uint32_t)0x00000080) 03100 #define DMA_SxNDT_8 ((uint32_t)0x00000100) 03101 #define DMA_SxNDT_9 ((uint32_t)0x00000200) 03102 #define DMA_SxNDT_10 ((uint32_t)0x00000400) 03103 #define DMA_SxNDT_11 ((uint32_t)0x00000800) 03104 #define DMA_SxNDT_12 ((uint32_t)0x00001000) 03105 #define DMA_SxNDT_13 ((uint32_t)0x00002000) 03106 #define DMA_SxNDT_14 ((uint32_t)0x00004000) 03107 #define DMA_SxNDT_15 ((uint32_t)0x00008000) 03108 03109 /******************** Bits definition for DMA_SxFCR register ****************/ 03110 #define DMA_SxFCR_FEIE ((uint32_t)0x00000080) 03111 #define DMA_SxFCR_FS ((uint32_t)0x00000038) 03112 #define DMA_SxFCR_FS_0 ((uint32_t)0x00000008) 03113 #define DMA_SxFCR_FS_1 ((uint32_t)0x00000010) 03114 #define DMA_SxFCR_FS_2 ((uint32_t)0x00000020) 03115 #define DMA_SxFCR_DMDIS ((uint32_t)0x00000004) 03116 #define DMA_SxFCR_FTH ((uint32_t)0x00000003) 03117 #define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001) 03118 #define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002) 03119 03120 /******************** Bits definition for DMA_LISR register *****************/ 03121 #define DMA_LISR_TCIF3 ((uint32_t)0x08000000) 03122 #define DMA_LISR_HTIF3 ((uint32_t)0x04000000) 03123 #define DMA_LISR_TEIF3 ((uint32_t)0x02000000) 03124 #define DMA_LISR_DMEIF3 ((uint32_t)0x01000000) 03125 #define DMA_LISR_FEIF3 ((uint32_t)0x00400000) 03126 #define DMA_LISR_TCIF2 ((uint32_t)0x00200000) 03127 #define DMA_LISR_HTIF2 ((uint32_t)0x00100000) 03128 #define DMA_LISR_TEIF2 ((uint32_t)0x00080000) 03129 #define DMA_LISR_DMEIF2 ((uint32_t)0x00040000) 03130 #define DMA_LISR_FEIF2 ((uint32_t)0x00010000) 03131 #define DMA_LISR_TCIF1 ((uint32_t)0x00000800) 03132 #define DMA_LISR_HTIF1 ((uint32_t)0x00000400) 03133 #define DMA_LISR_TEIF1 ((uint32_t)0x00000200) 03134 #define DMA_LISR_DMEIF1 ((uint32_t)0x00000100) 03135 #define DMA_LISR_FEIF1 ((uint32_t)0x00000040) 03136 #define DMA_LISR_TCIF0 ((uint32_t)0x00000020) 03137 #define DMA_LISR_HTIF0 ((uint32_t)0x00000010) 03138 #define DMA_LISR_TEIF0 ((uint32_t)0x00000008) 03139 #define DMA_LISR_DMEIF0 ((uint32_t)0x00000004) 03140 #define DMA_LISR_FEIF0 ((uint32_t)0x00000001) 03141 03142 /******************** Bits definition for DMA_HISR register *****************/ 03143 #define DMA_HISR_TCIF7 ((uint32_t)0x08000000) 03144 #define DMA_HISR_HTIF7 ((uint32_t)0x04000000) 03145 #define DMA_HISR_TEIF7 ((uint32_t)0x02000000) 03146 #define DMA_HISR_DMEIF7 ((uint32_t)0x01000000) 03147 #define DMA_HISR_FEIF7 ((uint32_t)0x00400000) 03148 #define DMA_HISR_TCIF6 ((uint32_t)0x00200000) 03149 #define DMA_HISR_HTIF6 ((uint32_t)0x00100000) 03150 #define DMA_HISR_TEIF6 ((uint32_t)0x00080000) 03151 #define DMA_HISR_DMEIF6 ((uint32_t)0x00040000) 03152 #define DMA_HISR_FEIF6 ((uint32_t)0x00010000) 03153 #define DMA_HISR_TCIF5 ((uint32_t)0x00000800) 03154 #define DMA_HISR_HTIF5 ((uint32_t)0x00000400) 03155 #define DMA_HISR_TEIF5 ((uint32_t)0x00000200) 03156 #define DMA_HISR_DMEIF5 ((uint32_t)0x00000100) 03157 #define DMA_HISR_FEIF5 ((uint32_t)0x00000040) 03158 #define DMA_HISR_TCIF4 ((uint32_t)0x00000020) 03159 #define DMA_HISR_HTIF4 ((uint32_t)0x00000010) 03160 #define DMA_HISR_TEIF4 ((uint32_t)0x00000008) 03161 #define DMA_HISR_DMEIF4 ((uint32_t)0x00000004) 03162 #define DMA_HISR_FEIF4 ((uint32_t)0x00000001) 03163 03164 /******************** Bits definition for DMA_LIFCR register ****************/ 03165 #define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000) 03166 #define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000) 03167 #define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000) 03168 #define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000) 03169 #define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000) 03170 #define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000) 03171 #define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000) 03172 #define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000) 03173 #define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000) 03174 #define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000) 03175 #define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800) 03176 #define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400) 03177 #define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200) 03178 #define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100) 03179 #define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040) 03180 #define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020) 03181 #define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010) 03182 #define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008) 03183 #define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004) 03184 #define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001) 03185 03186 /******************** Bits definition for DMA_HIFCR register ****************/ 03187 #define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000) 03188 #define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000) 03189 #define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000) 03190 #define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000) 03191 #define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000) 03192 #define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000) 03193 #define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000) 03194 #define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000) 03195 #define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000) 03196 #define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000) 03197 #define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800) 03198 #define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400) 03199 #define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200) 03200 #define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100) 03201 #define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040) 03202 #define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020) 03203 #define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010) 03204 #define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008) 03205 #define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004) 03206 #define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001) 03207 03208 /******************************************************************************/ 03209 /* */ 03210 /* External Interrupt/Event Controller */ 03211 /* */ 03212 /******************************************************************************/ 03213 /******************* Bit definition for EXTI_IMR register *******************/ 03214 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) 03215 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) 03216 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) 03217 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) 03218 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) 03219 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) 03220 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) 03221 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) 03222 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) 03223 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) 03224 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) 03225 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) 03226 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) 03227 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) 03228 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) 03229 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) 03230 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) 03231 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) 03232 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) 03233 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) 03235 /******************* Bit definition for EXTI_EMR register *******************/ 03236 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) 03237 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) 03238 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) 03239 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) 03240 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) 03241 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) 03242 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) 03243 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) 03244 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) 03245 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) 03246 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) 03247 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) 03248 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) 03249 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) 03250 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) 03251 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) 03252 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) 03253 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) 03254 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) 03255 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) 03257 /****************** Bit definition for EXTI_RTSR register *******************/ 03258 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) 03259 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) 03260 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) 03261 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) 03262 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) 03263 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) 03264 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) 03265 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) 03266 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) 03267 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) 03268 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) 03269 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) 03270 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) 03271 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) 03272 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) 03273 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) 03274 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) 03275 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) 03276 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) 03277 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) 03279 /****************** Bit definition for EXTI_FTSR register *******************/ 03280 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) 03281 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) 03282 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) 03283 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) 03284 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) 03285 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) 03286 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) 03287 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) 03288 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) 03289 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) 03290 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) 03291 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) 03292 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) 03293 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) 03294 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) 03295 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) 03296 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) 03297 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) 03298 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) 03299 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) 03301 /****************** Bit definition for EXTI_SWIER register ******************/ 03302 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) 03303 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) 03304 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) 03305 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) 03306 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) 03307 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) 03308 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) 03309 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) 03310 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) 03311 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) 03312 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) 03313 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) 03314 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) 03315 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) 03316 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) 03317 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) 03318 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) 03319 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) 03320 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) 03321 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) 03323 /******************* Bit definition for EXTI_PR register ********************/ 03324 #define EXTI_PR_PR0 ((uint32_t)0x00000001) 03325 #define EXTI_PR_PR1 ((uint32_t)0x00000002) 03326 #define EXTI_PR_PR2 ((uint32_t)0x00000004) 03327 #define EXTI_PR_PR3 ((uint32_t)0x00000008) 03328 #define EXTI_PR_PR4 ((uint32_t)0x00000010) 03329 #define EXTI_PR_PR5 ((uint32_t)0x00000020) 03330 #define EXTI_PR_PR6 ((uint32_t)0x00000040) 03331 #define EXTI_PR_PR7 ((uint32_t)0x00000080) 03332 #define EXTI_PR_PR8 ((uint32_t)0x00000100) 03333 #define EXTI_PR_PR9 ((uint32_t)0x00000200) 03334 #define EXTI_PR_PR10 ((uint32_t)0x00000400) 03335 #define EXTI_PR_PR11 ((uint32_t)0x00000800) 03336 #define EXTI_PR_PR12 ((uint32_t)0x00001000) 03337 #define EXTI_PR_PR13 ((uint32_t)0x00002000) 03338 #define EXTI_PR_PR14 ((uint32_t)0x00004000) 03339 #define EXTI_PR_PR15 ((uint32_t)0x00008000) 03340 #define EXTI_PR_PR16 ((uint32_t)0x00010000) 03341 #define EXTI_PR_PR17 ((uint32_t)0x00020000) 03342 #define EXTI_PR_PR18 ((uint32_t)0x00040000) 03343 #define EXTI_PR_PR19 ((uint32_t)0x00080000) 03345 /******************************************************************************/ 03346 /* */ 03347 /* FLASH */ 03348 /* */ 03349 /******************************************************************************/ 03350 /******************* Bits definition for FLASH_ACR register *****************/ 03351 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) 03352 #define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000) 03353 #define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001) 03354 #define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002) 03355 #define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003) 03356 #define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004) 03357 #define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005) 03358 #define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006) 03359 #define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007) 03360 03361 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000100) 03362 #define FLASH_ACR_ICEN ((uint32_t)0x00000200) 03363 #define FLASH_ACR_DCEN ((uint32_t)0x00000400) 03364 #define FLASH_ACR_ICRST ((uint32_t)0x00000800) 03365 #define FLASH_ACR_DCRST ((uint32_t)0x00001000) 03366 #define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00) 03367 #define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03) 03368 03369 /******************* Bits definition for FLASH_SR register ******************/ 03370 #define FLASH_SR_EOP ((uint32_t)0x00000001) 03371 #define FLASH_SR_SOP ((uint32_t)0x00000002) 03372 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) 03373 #define FLASH_SR_PGAERR ((uint32_t)0x00000020) 03374 #define FLASH_SR_PGPERR ((uint32_t)0x00000040) 03375 #define FLASH_SR_PGSERR ((uint32_t)0x00000080) 03376 #define FLASH_SR_BSY ((uint32_t)0x00010000) 03377 03378 /******************* Bits definition for FLASH_CR register ******************/ 03379 #define FLASH_CR_PG ((uint32_t)0x00000001) 03380 #define FLASH_CR_SER ((uint32_t)0x00000002) 03381 #define FLASH_CR_MER ((uint32_t)0x00000004) 03382 #define FLASH_CR_SNB_0 ((uint32_t)0x00000008) 03383 #define FLASH_CR_SNB_1 ((uint32_t)0x00000010) 03384 #define FLASH_CR_SNB_2 ((uint32_t)0x00000020) 03385 #define FLASH_CR_SNB_3 ((uint32_t)0x00000040) 03386 #define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100) 03387 #define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200) 03388 #define FLASH_CR_STRT ((uint32_t)0x00010000) 03389 #define FLASH_CR_EOPIE ((uint32_t)0x01000000) 03390 #define FLASH_CR_LOCK ((uint32_t)0x80000000) 03391 03392 /******************* Bits definition for FLASH_OPTCR register ***************/ 03393 #define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001) 03394 #define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002) 03395 #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) 03396 #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) 03397 #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) 03398 #define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020) 03399 #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) 03400 #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) 03401 #define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100) 03402 #define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200) 03403 #define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400) 03404 #define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800) 03405 #define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000) 03406 #define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000) 03407 #define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000) 03408 #define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000) 03409 #define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000) 03410 #define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000) 03411 #define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000) 03412 #define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000) 03413 #define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000) 03414 #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) 03415 #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) 03416 #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) 03417 #define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000) 03418 #define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000) 03419 #define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000) 03420 #define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000) 03421 03422 /******************************************************************************/ 03423 /* */ 03424 /* Flexible Static Memory Controller */ 03425 /* */ 03426 /******************************************************************************/ 03427 /****************** Bit definition for FSMC_BCR1 register *******************/ 03428 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) 03429 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) 03431 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) 03432 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) 03433 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) 03435 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) 03436 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) 03437 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) 03439 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) 03440 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) 03441 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) 03442 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) 03443 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) 03444 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) 03445 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) 03446 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) 03447 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) 03448 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) 03450 /****************** Bit definition for FSMC_BCR2 register *******************/ 03451 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) 03452 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) 03454 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) 03455 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) 03456 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) 03458 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) 03459 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) 03460 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) 03462 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) 03463 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) 03464 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) 03465 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) 03466 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) 03467 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) 03468 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) 03469 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) 03470 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) 03471 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) 03473 /****************** Bit definition for FSMC_BCR3 register *******************/ 03474 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) 03475 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) 03477 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) 03478 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) 03479 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) 03481 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) 03482 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) 03483 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) 03485 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) 03486 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) 03487 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) 03488 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) 03489 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) 03490 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) 03491 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) 03492 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) 03493 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) 03494 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) 03496 /****************** Bit definition for FSMC_BCR4 register *******************/ 03497 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) 03498 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) 03500 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) 03501 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) 03502 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) 03504 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) 03505 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) 03506 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) 03508 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) 03509 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) 03510 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) 03511 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) 03512 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) 03513 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) 03514 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) 03515 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) 03516 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) 03517 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) 03519 /****************** Bit definition for FSMC_BTR1 register ******************/ 03520 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) 03521 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) 03522 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) 03523 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) 03524 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) 03526 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) 03527 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) 03528 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) 03529 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) 03530 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) 03532 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) 03533 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) 03534 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) 03535 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) 03536 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) 03538 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) 03539 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) 03540 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) 03541 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) 03542 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) 03544 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) 03545 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) 03546 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) 03547 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) 03548 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) 03550 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) 03551 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) 03552 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) 03553 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) 03554 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) 03556 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) 03557 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) 03558 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) 03560 /****************** Bit definition for FSMC_BTR2 register *******************/ 03561 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) 03562 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) 03563 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) 03564 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) 03565 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) 03567 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) 03568 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) 03569 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) 03570 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) 03571 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) 03573 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) 03574 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) 03575 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) 03576 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) 03577 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) 03579 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) 03580 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) 03581 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) 03582 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) 03583 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) 03585 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) 03586 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) 03587 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) 03588 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) 03589 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) 03591 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) 03592 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) 03593 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) 03594 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) 03595 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) 03597 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) 03598 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) 03599 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) 03601 /******************* Bit definition for FSMC_BTR3 register *******************/ 03602 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) 03603 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) 03604 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) 03605 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) 03606 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) 03608 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) 03609 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) 03610 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) 03611 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) 03612 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) 03614 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) 03615 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) 03616 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) 03617 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) 03618 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) 03620 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) 03621 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) 03622 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) 03623 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) 03624 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) 03626 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) 03627 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) 03628 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) 03629 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) 03630 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) 03632 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) 03633 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) 03634 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) 03635 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) 03636 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) 03638 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) 03639 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) 03640 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) 03642 /****************** Bit definition for FSMC_BTR4 register *******************/ 03643 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) 03644 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) 03645 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) 03646 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) 03647 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) 03649 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) 03650 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) 03651 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) 03652 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) 03653 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) 03655 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) 03656 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) 03657 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) 03658 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) 03659 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) 03661 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) 03662 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) 03663 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) 03664 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) 03665 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) 03667 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) 03668 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) 03669 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) 03670 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) 03671 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) 03673 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) 03674 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) 03675 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) 03676 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) 03677 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) 03679 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) 03680 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) 03681 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) 03683 /****************** Bit definition for FSMC_BWTR1 register ******************/ 03684 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) 03685 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) 03686 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) 03687 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) 03688 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) 03690 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) 03691 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) 03692 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) 03693 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) 03694 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) 03696 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) 03697 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) 03698 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) 03699 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) 03700 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) 03702 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) 03703 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) 03704 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) 03705 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) 03706 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) 03708 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) 03709 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) 03710 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) 03711 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) 03712 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) 03714 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) 03715 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) 03716 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) 03718 /****************** Bit definition for FSMC_BWTR2 register ******************/ 03719 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) 03720 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) 03721 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) 03722 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) 03723 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) 03725 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) 03726 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) 03727 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) 03728 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) 03729 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) 03731 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) 03732 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) 03733 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) 03734 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) 03735 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) 03737 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) 03738 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) 03739 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) 03740 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) 03741 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) 03743 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) 03744 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) 03745 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) 03746 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) 03747 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) 03749 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) 03750 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) 03751 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) 03753 /****************** Bit definition for FSMC_BWTR3 register ******************/ 03754 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) 03755 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) 03756 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) 03757 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) 03758 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) 03760 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) 03761 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) 03762 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) 03763 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) 03764 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) 03766 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) 03767 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) 03768 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) 03769 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) 03770 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) 03772 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) 03773 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) 03774 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) 03775 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) 03776 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) 03778 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) 03779 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) 03780 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) 03781 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) 03782 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) 03784 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) 03785 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) 03786 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) 03788 /****************** Bit definition for FSMC_BWTR4 register ******************/ 03789 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) 03790 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) 03791 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) 03792 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) 03793 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) 03795 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) 03796 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) 03797 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) 03798 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) 03799 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) 03801 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) 03802 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) 03803 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) 03804 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) 03805 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) 03807 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) 03808 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) 03809 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) 03810 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) 03811 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) 03813 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 03814 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 03815 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 03816 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 03817 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) 03819 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 03820 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 03821 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 03823 /****************** Bit definition for FSMC_PCR2 register *******************/ 03824 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) 03825 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) 03826 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) 03828 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) 03829 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) 03830 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) 03832 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) 03834 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 03835 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 03836 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 03837 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 03838 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) 03840 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) 03841 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 03842 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 03843 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 03844 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 03846 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) 03847 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) 03848 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) 03849 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) 03851 /****************** Bit definition for FSMC_PCR3 register *******************/ 03852 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) 03853 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) 03854 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) 03856 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) 03857 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) 03858 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) 03860 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) 03862 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) 03863 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) 03864 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) 03865 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) 03866 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) 03868 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) 03869 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) 03870 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) 03871 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) 03872 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) 03874 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) 03875 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) 03876 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) 03877 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) 03879 /****************** Bit definition for FSMC_PCR4 register *******************/ 03880 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) 03881 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) 03882 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) 03884 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) 03885 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) 03886 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) 03888 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) 03890 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) 03891 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) 03892 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) 03893 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) 03894 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) 03896 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) 03897 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) 03898 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) 03899 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) 03900 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) 03902 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) 03903 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) 03904 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) 03905 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) 03907 /******************* Bit definition for FSMC_SR2 register *******************/ 03908 #define FSMC_SR2_IRS ((uint8_t)0x01) 03909 #define FSMC_SR2_ILS ((uint8_t)0x02) 03910 #define FSMC_SR2_IFS ((uint8_t)0x04) 03911 #define FSMC_SR2_IREN ((uint8_t)0x08) 03912 #define FSMC_SR2_ILEN ((uint8_t)0x10) 03913 #define FSMC_SR2_IFEN ((uint8_t)0x20) 03914 #define FSMC_SR2_FEMPT ((uint8_t)0x40) 03916 /******************* Bit definition for FSMC_SR3 register *******************/ 03917 #define FSMC_SR3_IRS ((uint8_t)0x01) 03918 #define FSMC_SR3_ILS ((uint8_t)0x02) 03919 #define FSMC_SR3_IFS ((uint8_t)0x04) 03920 #define FSMC_SR3_IREN ((uint8_t)0x08) 03921 #define FSMC_SR3_ILEN ((uint8_t)0x10) 03922 #define FSMC_SR3_IFEN ((uint8_t)0x20) 03923 #define FSMC_SR3_FEMPT ((uint8_t)0x40) 03925 /******************* Bit definition for FSMC_SR4 register *******************/ 03926 #define FSMC_SR4_IRS ((uint8_t)0x01) 03927 #define FSMC_SR4_ILS ((uint8_t)0x02) 03928 #define FSMC_SR4_IFS ((uint8_t)0x04) 03929 #define FSMC_SR4_IREN ((uint8_t)0x08) 03930 #define FSMC_SR4_ILEN ((uint8_t)0x10) 03931 #define FSMC_SR4_IFEN ((uint8_t)0x20) 03932 #define FSMC_SR4_FEMPT ((uint8_t)0x40) 03934 /****************** Bit definition for FSMC_PMEM2 register ******************/ 03935 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) 03936 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) 03937 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) 03938 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) 03939 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) 03940 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) 03941 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) 03942 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) 03943 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) 03945 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) 03946 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) 03947 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) 03948 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) 03949 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) 03950 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) 03951 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) 03952 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) 03953 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) 03955 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) 03956 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) 03957 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) 03958 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) 03959 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) 03960 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) 03961 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) 03962 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) 03963 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) 03965 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) 03966 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) 03967 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) 03968 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) 03969 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) 03970 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) 03971 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) 03972 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) 03973 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) 03975 /****************** Bit definition for FSMC_PMEM3 register ******************/ 03976 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) 03977 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) 03978 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) 03979 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) 03980 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) 03981 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) 03982 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) 03983 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) 03984 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) 03986 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) 03987 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) 03988 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) 03989 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) 03990 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) 03991 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) 03992 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) 03993 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) 03994 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) 03996 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) 03997 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) 03998 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) 03999 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) 04000 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) 04001 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) 04002 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) 04003 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) 04004 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) 04006 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) 04007 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) 04008 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) 04009 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) 04010 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) 04011 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) 04012 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) 04013 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) 04014 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) 04016 /****************** Bit definition for FSMC_PMEM4 register ******************/ 04017 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) 04018 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) 04019 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) 04020 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) 04021 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) 04022 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) 04023 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) 04024 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) 04025 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) 04027 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) 04028 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) 04029 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) 04030 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) 04031 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) 04032 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) 04033 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) 04034 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) 04035 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) 04037 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) 04038 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) 04039 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) 04040 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) 04041 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) 04042 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) 04043 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) 04044 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) 04045 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) 04047 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) 04048 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) 04049 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) 04050 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) 04051 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) 04052 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) 04053 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) 04054 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) 04055 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) 04057 /****************** Bit definition for FSMC_PATT2 register ******************/ 04058 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) 04059 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) 04060 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) 04061 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) 04062 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) 04063 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) 04064 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) 04065 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) 04066 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) 04068 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) 04069 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) 04070 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) 04071 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) 04072 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) 04073 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) 04074 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) 04075 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) 04076 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) 04078 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) 04079 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) 04080 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) 04081 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) 04082 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) 04083 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) 04084 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) 04085 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) 04086 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) 04088 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) 04089 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) 04090 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) 04091 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) 04092 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) 04093 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) 04094 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) 04095 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) 04096 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) 04098 /****************** Bit definition for FSMC_PATT3 register ******************/ 04099 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) 04100 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) 04101 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) 04102 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) 04103 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) 04104 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) 04105 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) 04106 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) 04107 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) 04109 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) 04110 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) 04111 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) 04112 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) 04113 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) 04114 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) 04115 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) 04116 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) 04117 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) 04119 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) 04120 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) 04121 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) 04122 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) 04123 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) 04124 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) 04125 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) 04126 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) 04127 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) 04129 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) 04130 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) 04131 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) 04132 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) 04133 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) 04134 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) 04135 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) 04136 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) 04137 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) 04139 /****************** Bit definition for FSMC_PATT4 register ******************/ 04140 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) 04141 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) 04142 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) 04143 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) 04144 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) 04145 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) 04146 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) 04147 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) 04148 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) 04150 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) 04151 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) 04152 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) 04153 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) 04154 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) 04155 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) 04156 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) 04157 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) 04158 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) 04160 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) 04161 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) 04162 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) 04163 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) 04164 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) 04165 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) 04166 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) 04167 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) 04168 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) 04170 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) 04171 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) 04172 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) 04173 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) 04174 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) 04175 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) 04176 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) 04177 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) 04178 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) 04180 /****************** Bit definition for FSMC_PIO4 register *******************/ 04181 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) 04182 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) 04183 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) 04184 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) 04185 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) 04186 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) 04187 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) 04188 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) 04189 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) 04191 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) 04192 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) 04193 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) 04194 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) 04195 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) 04196 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) 04197 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) 04198 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) 04199 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) 04201 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) 04202 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) 04203 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) 04204 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) 04205 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) 04206 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) 04207 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) 04208 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) 04209 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) 04211 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) 04212 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) 04213 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) 04214 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) 04215 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) 04216 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) 04217 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) 04218 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) 04219 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) 04221 /****************** Bit definition for FSMC_ECCR2 register ******************/ 04222 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) 04224 /****************** Bit definition for FSMC_ECCR3 register ******************/ 04225 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) 04227 /******************************************************************************/ 04228 /* */ 04229 /* General Purpose I/O */ 04230 /* */ 04231 /******************************************************************************/ 04232 /****************** Bits definition for GPIO_MODER register *****************/ 04233 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003) 04234 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001) 04235 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002) 04236 04237 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C) 04238 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004) 04239 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008) 04240 04241 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030) 04242 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010) 04243 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020) 04244 04245 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0) 04246 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040) 04247 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080) 04248 04249 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300) 04250 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100) 04251 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200) 04252 04253 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00) 04254 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400) 04255 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800) 04256 04257 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000) 04258 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000) 04259 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000) 04260 04261 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000) 04262 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000) 04263 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000) 04264 04265 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000) 04266 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000) 04267 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000) 04268 04269 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000) 04270 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000) 04271 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000) 04272 04273 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000) 04274 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000) 04275 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000) 04276 04277 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000) 04278 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000) 04279 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000) 04280 04281 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000) 04282 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000) 04283 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000) 04284 04285 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000) 04286 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000) 04287 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000) 04288 04289 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000) 04290 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000) 04291 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000) 04292 04293 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000) 04294 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000) 04295 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000) 04296 04297 /****************** Bits definition for GPIO_OTYPER register ****************/ 04298 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001) 04299 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002) 04300 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004) 04301 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008) 04302 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010) 04303 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020) 04304 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040) 04305 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080) 04306 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100) 04307 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200) 04308 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400) 04309 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800) 04310 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000) 04311 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000) 04312 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000) 04313 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000) 04314 04315 /****************** Bits definition for GPIO_OSPEEDR register ***************/ 04316 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003) 04317 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001) 04318 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002) 04319 04320 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C) 04321 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004) 04322 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008) 04323 04324 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030) 04325 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010) 04326 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020) 04327 04328 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0) 04329 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040) 04330 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080) 04331 04332 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300) 04333 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100) 04334 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200) 04335 04336 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00) 04337 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400) 04338 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800) 04339 04340 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000) 04341 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000) 04342 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000) 04343 04344 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000) 04345 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000) 04346 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000) 04347 04348 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000) 04349 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000) 04350 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000) 04351 04352 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000) 04353 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000) 04354 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000) 04355 04356 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000) 04357 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000) 04358 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000) 04359 04360 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000) 04361 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000) 04362 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000) 04363 04364 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000) 04365 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000) 04366 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000) 04367 04368 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000) 04369 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000) 04370 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000) 04371 04372 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000) 04373 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000) 04374 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000) 04375 04376 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000) 04377 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000) 04378 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000) 04379 04380 /****************** Bits definition for GPIO_PUPDR register *****************/ 04381 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003) 04382 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001) 04383 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002) 04384 04385 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C) 04386 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004) 04387 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008) 04388 04389 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030) 04390 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010) 04391 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020) 04392 04393 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0) 04394 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040) 04395 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080) 04396 04397 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300) 04398 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100) 04399 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200) 04400 04401 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00) 04402 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400) 04403 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800) 04404 04405 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000) 04406 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000) 04407 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000) 04408 04409 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000) 04410 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000) 04411 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000) 04412 04413 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000) 04414 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000) 04415 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000) 04416 04417 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000) 04418 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000) 04419 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000) 04420 04421 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000) 04422 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000) 04423 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000) 04424 04425 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000) 04426 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000) 04427 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000) 04428 04429 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000) 04430 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000) 04431 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000) 04432 04433 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000) 04434 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000) 04435 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000) 04436 04437 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000) 04438 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000) 04439 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000) 04440 04441 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000) 04442 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000) 04443 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000) 04444 04445 /****************** Bits definition for GPIO_IDR register *******************/ 04446 #define GPIO_OTYPER_IDR_0 ((uint32_t)0x00000001) 04447 #define GPIO_OTYPER_IDR_1 ((uint32_t)0x00000002) 04448 #define GPIO_OTYPER_IDR_2 ((uint32_t)0x00000004) 04449 #define GPIO_OTYPER_IDR_3 ((uint32_t)0x00000008) 04450 #define GPIO_OTYPER_IDR_4 ((uint32_t)0x00000010) 04451 #define GPIO_OTYPER_IDR_5 ((uint32_t)0x00000020) 04452 #define GPIO_OTYPER_IDR_6 ((uint32_t)0x00000040) 04453 #define GPIO_OTYPER_IDR_7 ((uint32_t)0x00000080) 04454 #define GPIO_OTYPER_IDR_8 ((uint32_t)0x00000100) 04455 #define GPIO_OTYPER_IDR_9 ((uint32_t)0x00000200) 04456 #define GPIO_OTYPER_IDR_10 ((uint32_t)0x00000400) 04457 #define GPIO_OTYPER_IDR_11 ((uint32_t)0x00000800) 04458 #define GPIO_OTYPER_IDR_12 ((uint32_t)0x00001000) 04459 #define GPIO_OTYPER_IDR_13 ((uint32_t)0x00002000) 04460 #define GPIO_OTYPER_IDR_14 ((uint32_t)0x00004000) 04461 #define GPIO_OTYPER_IDR_15 ((uint32_t)0x00008000) 04462 04463 /****************** Bits definition for GPIO_ODR register *******************/ 04464 #define GPIO_OTYPER_ODR_0 ((uint32_t)0x00000001) 04465 #define GPIO_OTYPER_ODR_1 ((uint32_t)0x00000002) 04466 #define GPIO_OTYPER_ODR_2 ((uint32_t)0x00000004) 04467 #define GPIO_OTYPER_ODR_3 ((uint32_t)0x00000008) 04468 #define GPIO_OTYPER_ODR_4 ((uint32_t)0x00000010) 04469 #define GPIO_OTYPER_ODR_5 ((uint32_t)0x00000020) 04470 #define GPIO_OTYPER_ODR_6 ((uint32_t)0x00000040) 04471 #define GPIO_OTYPER_ODR_7 ((uint32_t)0x00000080) 04472 #define GPIO_OTYPER_ODR_8 ((uint32_t)0x00000100) 04473 #define GPIO_OTYPER_ODR_9 ((uint32_t)0x00000200) 04474 #define GPIO_OTYPER_ODR_10 ((uint32_t)0x00000400) 04475 #define GPIO_OTYPER_ODR_11 ((uint32_t)0x00000800) 04476 #define GPIO_OTYPER_ODR_12 ((uint32_t)0x00001000) 04477 #define GPIO_OTYPER_ODR_13 ((uint32_t)0x00002000) 04478 #define GPIO_OTYPER_ODR_14 ((uint32_t)0x00004000) 04479 #define GPIO_OTYPER_ODR_15 ((uint32_t)0x00008000) 04480 04481 /****************** Bits definition for GPIO_BSRR register ******************/ 04482 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001) 04483 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002) 04484 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004) 04485 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008) 04486 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010) 04487 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020) 04488 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040) 04489 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080) 04490 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100) 04491 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200) 04492 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400) 04493 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800) 04494 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000) 04495 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000) 04496 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000) 04497 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000) 04498 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000) 04499 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000) 04500 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000) 04501 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000) 04502 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000) 04503 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000) 04504 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000) 04505 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000) 04506 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000) 04507 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000) 04508 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000) 04509 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000) 04510 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000) 04511 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000) 04512 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000) 04513 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000) 04514 04515 /******************************************************************************/ 04516 /* */ 04517 /* HASH */ 04518 /* */ 04519 /******************************************************************************/ 04520 /****************** Bits definition for HASH_CR register ********************/ 04521 #define HASH_CR_INIT ((uint32_t)0x00000004) 04522 #define HASH_CR_DMAE ((uint32_t)0x00000008) 04523 #define HASH_CR_DATATYPE ((uint32_t)0x00000030) 04524 #define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010) 04525 #define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020) 04526 #define HASH_CR_MODE ((uint32_t)0x00000040) 04527 #define HASH_CR_ALGO ((uint32_t)0x00000080) 04528 #define HASH_CR_NBW ((uint32_t)0x00000F00) 04529 #define HASH_CR_NBW_0 ((uint32_t)0x00000100) 04530 #define HASH_CR_NBW_1 ((uint32_t)0x00000200) 04531 #define HASH_CR_NBW_2 ((uint32_t)0x00000400) 04532 #define HASH_CR_NBW_3 ((uint32_t)0x00000800) 04533 #define HASH_CR_DINNE ((uint32_t)0x00001000) 04534 #define HASH_CR_LKEY ((uint32_t)0x00010000) 04535 04536 /****************** Bits definition for HASH_STR register *******************/ 04537 #define HASH_STR_NBW ((uint32_t)0x0000001F) 04538 #define HASH_STR_NBW_0 ((uint32_t)0x00000001) 04539 #define HASH_STR_NBW_1 ((uint32_t)0x00000002) 04540 #define HASH_STR_NBW_2 ((uint32_t)0x00000004) 04541 #define HASH_STR_NBW_3 ((uint32_t)0x00000008) 04542 #define HASH_STR_NBW_4 ((uint32_t)0x00000010) 04543 #define HASH_STR_DCAL ((uint32_t)0x00000100) 04544 04545 /****************** Bits definition for HASH_IMR register *******************/ 04546 #define HASH_IMR_DINIM ((uint32_t)0x00000001) 04547 #define HASH_IMR_DCIM ((uint32_t)0x00000002) 04548 04549 /****************** Bits definition for HASH_SR register ********************/ 04550 #define HASH_SR_DINIS ((uint32_t)0x00000001) 04551 #define HASH_SR_DCIS ((uint32_t)0x00000002) 04552 #define HASH_SR_DMAS ((uint32_t)0x00000004) 04553 #define HASH_SR_BUSY ((uint32_t)0x00000008) 04554 04555 /******************************************************************************/ 04556 /* */ 04557 /* Inter-integrated Circuit Interface */ 04558 /* */ 04559 /******************************************************************************/ 04560 /******************* Bit definition for I2C_CR1 register ********************/ 04561 #define I2C_CR1_PE ((uint16_t)0x0001) 04562 #define I2C_CR1_SMBUS ((uint16_t)0x0002) 04563 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) 04564 #define I2C_CR1_ENARP ((uint16_t)0x0010) 04565 #define I2C_CR1_ENPEC ((uint16_t)0x0020) 04566 #define I2C_CR1_ENGC ((uint16_t)0x0040) 04567 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) 04568 #define I2C_CR1_START ((uint16_t)0x0100) 04569 #define I2C_CR1_STOP ((uint16_t)0x0200) 04570 #define I2C_CR1_ACK ((uint16_t)0x0400) 04571 #define I2C_CR1_POS ((uint16_t)0x0800) 04572 #define I2C_CR1_PEC ((uint16_t)0x1000) 04573 #define I2C_CR1_ALERT ((uint16_t)0x2000) 04574 #define I2C_CR1_SWRST ((uint16_t)0x8000) 04576 /******************* Bit definition for I2C_CR2 register ********************/ 04577 #define I2C_CR2_FREQ ((uint16_t)0x003F) 04578 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) 04579 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) 04580 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) 04581 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) 04582 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) 04583 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) 04585 #define I2C_CR2_ITERREN ((uint16_t)0x0100) 04586 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) 04587 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) 04588 #define I2C_CR2_DMAEN ((uint16_t)0x0800) 04589 #define I2C_CR2_LAST ((uint16_t)0x1000) 04591 /******************* Bit definition for I2C_OAR1 register *******************/ 04592 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) 04593 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) 04595 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) 04596 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) 04597 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) 04598 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) 04599 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) 04600 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) 04601 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) 04602 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) 04603 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) 04604 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) 04606 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) 04608 /******************* Bit definition for I2C_OAR2 register *******************/ 04609 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) 04610 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) 04612 /******************** Bit definition for I2C_DR register ********************/ 04613 #define I2C_DR_DR ((uint8_t)0xFF) 04615 /******************* Bit definition for I2C_SR1 register ********************/ 04616 #define I2C_SR1_SB ((uint16_t)0x0001) 04617 #define I2C_SR1_ADDR ((uint16_t)0x0002) 04618 #define I2C_SR1_BTF ((uint16_t)0x0004) 04619 #define I2C_SR1_ADD10 ((uint16_t)0x0008) 04620 #define I2C_SR1_STOPF ((uint16_t)0x0010) 04621 #define I2C_SR1_RXNE ((uint16_t)0x0040) 04622 #define I2C_SR1_TXE ((uint16_t)0x0080) 04623 #define I2C_SR1_BERR ((uint16_t)0x0100) 04624 #define I2C_SR1_ARLO ((uint16_t)0x0200) 04625 #define I2C_SR1_AF ((uint16_t)0x0400) 04626 #define I2C_SR1_OVR ((uint16_t)0x0800) 04627 #define I2C_SR1_PECERR ((uint16_t)0x1000) 04628 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) 04629 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) 04631 /******************* Bit definition for I2C_SR2 register ********************/ 04632 #define I2C_SR2_MSL ((uint16_t)0x0001) 04633 #define I2C_SR2_BUSY ((uint16_t)0x0002) 04634 #define I2C_SR2_TRA ((uint16_t)0x0004) 04635 #define I2C_SR2_GENCALL ((uint16_t)0x0010) 04636 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) 04637 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) 04638 #define I2C_SR2_DUALF ((uint16_t)0x0080) 04639 #define I2C_SR2_PEC ((uint16_t)0xFF00) 04641 /******************* Bit definition for I2C_CCR register ********************/ 04642 #define I2C_CCR_CCR ((uint16_t)0x0FFF) 04643 #define I2C_CCR_DUTY ((uint16_t)0x4000) 04644 #define I2C_CCR_FS ((uint16_t)0x8000) 04646 /****************** Bit definition for I2C_TRISE register *******************/ 04647 #define I2C_TRISE_TRISE ((uint8_t)0x3F) 04649 /******************************************************************************/ 04650 /* */ 04651 /* Independent WATCHDOG */ 04652 /* */ 04653 /******************************************************************************/ 04654 /******************* Bit definition for IWDG_KR register ********************/ 04655 #define IWDG_KR_KEY ((uint16_t)0xFFFF) 04657 /******************* Bit definition for IWDG_PR register ********************/ 04658 #define IWDG_PR_PR ((uint8_t)0x07) 04659 #define IWDG_PR_PR_0 ((uint8_t)0x01) 04660 #define IWDG_PR_PR_1 ((uint8_t)0x02) 04661 #define IWDG_PR_PR_2 ((uint8_t)0x04) 04663 /******************* Bit definition for IWDG_RLR register *******************/ 04664 #define IWDG_RLR_RL ((uint16_t)0x0FFF) 04666 /******************* Bit definition for IWDG_SR register ********************/ 04667 #define IWDG_SR_PVU ((uint8_t)0x01) 04668 #define IWDG_SR_RVU ((uint8_t)0x02) 04670 /******************************************************************************/ 04671 /* */ 04672 /* Power Control */ 04673 /* */ 04674 /******************************************************************************/ 04675 /******************** Bit definition for PWR_CR register ********************/ 04676 #define PWR_CR_LPDS ((uint16_t)0x0001) 04677 #define PWR_CR_PDDS ((uint16_t)0x0002) 04678 #define PWR_CR_CWUF ((uint16_t)0x0004) 04679 #define PWR_CR_CSBF ((uint16_t)0x0008) 04680 #define PWR_CR_PVDE ((uint16_t)0x0010) 04682 #define PWR_CR_PLS ((uint16_t)0x00E0) 04683 #define PWR_CR_PLS_0 ((uint16_t)0x0020) 04684 #define PWR_CR_PLS_1 ((uint16_t)0x0040) 04685 #define PWR_CR_PLS_2 ((uint16_t)0x0080) 04688 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) 04689 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) 04690 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) 04691 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) 04692 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) 04693 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) 04694 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) 04695 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) 04697 #define PWR_CR_DBP ((uint16_t)0x0100) 04698 #define PWR_CR_FPDS ((uint16_t)0x0200) 04701 /******************* Bit definition for PWR_CSR register ********************/ 04702 #define PWR_CSR_WUF ((uint16_t)0x0001) 04703 #define PWR_CSR_SBF ((uint16_t)0x0002) 04704 #define PWR_CSR_PVDO ((uint16_t)0x0004) 04705 #define PWR_CSR_BRR ((uint16_t)0x0008) 04706 #define PWR_CSR_EWUP ((uint16_t)0x0100) 04707 #define PWR_CSR_BRE ((uint16_t)0x0200) 04709 /******************************************************************************/ 04710 /* */ 04711 /* Reset and Clock Control */ 04712 /* */ 04713 /******************************************************************************/ 04714 /******************** Bit definition for RCC_CR register ********************/ 04715 #define RCC_CR_HSION ((uint32_t)0x00000001) 04716 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 04717 04718 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 04719 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) 04720 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) 04721 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) 04722 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) 04723 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) 04725 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) 04726 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) 04727 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) 04728 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) 04729 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) 04730 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) 04731 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) 04732 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) 04733 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) 04735 #define RCC_CR_HSEON ((uint32_t)0x00010000) 04736 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 04737 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 04738 #define RCC_CR_CSSON ((uint32_t)0x00080000) 04739 #define RCC_CR_PLLON ((uint32_t)0x01000000) 04740 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 04741 #define RCC_CR_PLLI2SON ((uint32_t)0x04000000) 04742 #define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000) 04743 04744 /******************** Bit definition for RCC_PLLCFGR register ***************/ 04745 #define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F) 04746 #define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001) 04747 #define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002) 04748 #define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004) 04749 #define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008) 04750 #define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010) 04751 #define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020) 04752 04753 #define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0) 04754 #define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040) 04755 #define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080) 04756 #define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100) 04757 #define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200) 04758 #define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400) 04759 #define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800) 04760 #define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000) 04761 #define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000) 04762 #define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000) 04763 04764 #define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000) 04765 #define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000) 04766 #define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000) 04767 04768 #define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000) 04769 #define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000) 04770 #define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000) 04771 04772 #define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000) 04773 #define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000) 04774 #define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000) 04775 #define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000) 04776 #define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000) 04777 04778 /******************** Bit definition for RCC_CFGR register ******************/ 04780 #define RCC_CFGR_SW ((uint32_t)0x00000003) 04781 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) 04782 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) 04784 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) 04785 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) 04786 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) 04789 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) 04790 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) 04791 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) 04793 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) 04794 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) 04795 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) 04798 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) 04799 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) 04800 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) 04801 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) 04802 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) 04804 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) 04805 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) 04806 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) 04807 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) 04808 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) 04809 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) 04810 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) 04811 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) 04812 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) 04815 #define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) 04816 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) 04817 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) 04818 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) 04820 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) 04821 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) 04822 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) 04823 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) 04824 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) 04827 #define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) 04828 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) 04829 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) 04830 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) 04832 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) 04833 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) 04834 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) 04835 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) 04836 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E00) 04839 #define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000) 04840 #define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000) 04841 #define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000) 04842 #define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000) 04843 #define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000) 04844 #define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000) 04845 04847 #define RCC_CFGR_MCO1 ((uint32_t)0x00600000) 04848 #define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000) 04849 #define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000) 04850 04851 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) 04852 04853 #define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000) 04854 #define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000) 04855 #define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000) 04856 #define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000) 04857 04858 #define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000) 04859 #define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000) 04860 #define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000) 04861 #define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000) 04862 04863 #define RCC_CFGR_MCO2 ((uint32_t)0xC0000000) 04864 #define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000) 04865 #define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000) 04866 04867 /******************** Bit definition for RCC_CIR register *******************/ 04868 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 04869 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) 04870 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 04871 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) 04872 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 04873 #define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020) 04874 #define RCC_CIR_CSSF ((uint32_t)0x00000080) 04875 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) 04876 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) 04877 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) 04878 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) 04879 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) 04880 #define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000) 04881 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) 04882 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 04883 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 04884 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 04885 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) 04886 #define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000) 04887 #define RCC_CIR_CSSC ((uint32_t)0x00800000) 04888 04889 /******************** Bit definition for RCC_AHB1RSTR register **************/ 04890 #define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001) 04891 #define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002) 04892 #define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004) 04893 #define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008) 04894 #define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010) 04895 #define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020) 04896 #define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040) 04897 #define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080) 04898 #define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100) 04899 #define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000) 04900 #define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000) 04901 #define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000) 04902 #define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000) 04903 #define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000) 04904 04905 /******************** Bit definition for RCC_AHB2RSTR register **************/ 04906 #define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001) 04907 #define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010) 04908 #define RCC_AHB2RSTR_HSAHRST ((uint32_t)0x00000020) 04909 #define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040) 04910 #define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080) 04911 04912 /******************** Bit definition for RCC_AHB3RSTR register **************/ 04913 #define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001) 04914 04915 /******************** Bit definition for RCC_APB1RSTR register **************/ 04916 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) 04917 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 04918 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) 04919 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 04920 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 04921 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 04922 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) 04923 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) 04924 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) 04925 #define RCC_APB1RSTR_WWDGEN ((uint32_t)0x00000800) 04926 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00008000) 04927 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00010000) 04928 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 04929 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) 04930 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 04931 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 04932 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) 04933 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 04934 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000) 04935 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) 04936 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) 04937 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 04938 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 04939 04940 /******************** Bit definition for RCC_APB2RSTR register **************/ 04941 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001) 04942 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002) 04943 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010) 04944 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) 04945 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100) 04946 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) 04947 #define RCC_APB2RSTR_SPI1 ((uint32_t)0x00001000) 04948 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000) 04949 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000) 04950 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000) 04951 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000) 04952 04953 /******************** Bit definition for RCC_AHB1ENR register ***************/ 04954 #define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001) 04955 #define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002) 04956 #define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004) 04957 #define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008) 04958 #define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010) 04959 #define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020) 04960 #define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040) 04961 #define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080) 04962 #define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100) 04963 #define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000) 04964 #define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000) 04965 #define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000) 04966 #define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000) 04967 #define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000) 04968 #define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000) 04969 #define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000) 04970 #define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000) 04971 #define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000) 04972 #define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000) 04973 04974 /******************** Bit definition for RCC_AHB2ENR register ***************/ 04975 #define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001) 04976 #define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010) 04977 #define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020) 04978 #define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040) 04979 #define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080) 04980 04981 /******************** Bit definition for RCC_AHB3ENR register ***************/ 04982 #define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001) 04983 04984 /******************** Bit definition for RCC_APB1ENR register ***************/ 04985 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 04986 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) 04987 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) 04988 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 04989 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 04990 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 04991 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) 04992 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) 04993 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) 04994 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 04995 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) 04996 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 04997 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 04998 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) 04999 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 05000 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 05001 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) 05002 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 05003 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000) 05004 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 05005 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) 05006 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) 05007 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 05008 05009 /******************** Bit definition for RCC_APB2ENR register ***************/ 05010 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001) 05011 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002) 05012 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010) 05013 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) 05014 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100) 05015 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200) 05016 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400) 05017 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) 05018 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) 05019 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000) 05020 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000) 05021 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000) 05022 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000) 05023 05024 /******************** Bit definition for RCC_AHB1LPENR register *************/ 05025 #define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001) 05026 #define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002) 05027 #define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004) 05028 #define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008) 05029 #define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010) 05030 #define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020) 05031 #define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040) 05032 #define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080) 05033 #define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100) 05034 #define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000) 05035 #define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000) 05036 #define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000) 05037 #define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000) 05038 #define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000) 05039 #define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000) 05040 #define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000) 05041 #define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000) 05042 #define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000) 05043 #define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000) 05044 #define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000) 05045 #define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000) 05046 #define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000) 05047 05048 /******************** Bit definition for RCC_AHB2LPENR register *************/ 05049 #define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001) 05050 #define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010) 05051 #define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020) 05052 #define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040) 05053 #define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080) 05054 05055 /******************** Bit definition for RCC_AHB3LPENR register *************/ 05056 #define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001) 05057 05058 /******************** Bit definition for RCC_APB1LPENR register *************/ 05059 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) 05060 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) 05061 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) 05062 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) 05063 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) 05064 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) 05065 #define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040) 05066 #define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080) 05067 #define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100) 05068 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) 05069 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) 05070 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) 05071 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) 05072 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) 05073 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) 05074 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) 05075 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) 05076 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) 05077 #define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000) 05078 #define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000) 05079 #define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000) 05080 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) 05081 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) 05082 05083 /******************** Bit definition for RCC_APB2LPENR register *************/ 05084 #define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001) 05085 #define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002) 05086 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010) 05087 #define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020) 05088 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100) 05089 #define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200) 05090 #define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400) 05091 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) 05092 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) 05093 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000) 05094 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000) 05095 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000) 05096 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000) 05097 05098 /******************** Bit definition for RCC_BDCR register ******************/ 05099 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) 05100 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) 05101 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) 05102 05103 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) 05104 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) 05105 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) 05106 05107 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) 05108 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) 05109 05110 /******************** Bit definition for RCC_CSR register *******************/ 05111 #define RCC_CSR_LSION ((uint32_t)0x00000001) 05112 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) 05113 #define RCC_CSR_RMVF ((uint32_t)0x01000000) 05114 #define RCC_CSR_BORRSTF ((uint32_t)0x02000000) 05115 #define RCC_CSR_PADRSTF ((uint32_t)0x04000000) 05116 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) 05117 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 05118 #define RCC_CSR_WDGRSTF ((uint32_t)0x20000000) 05119 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) 05120 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) 05121 05122 /******************** Bit definition for RCC_SSCGR register *****************/ 05123 #define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF) 05124 #define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000) 05125 #define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000) 05126 #define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000) 05127 05128 /******************** Bit definition for RCC_PLLI2SCFGR register ************/ 05129 #define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0) 05130 #define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000) 05131 05132 /******************************************************************************/ 05133 /* */ 05134 /* RNG */ 05135 /* */ 05136 /******************************************************************************/ 05137 /******************** Bits definition for RNG_CR register *******************/ 05138 #define RNG_CR_RNGEN ((uint32_t)0x00000004) 05139 #define RNG_CR_IE ((uint32_t)0x00000008) 05140 05141 /******************** Bits definition for RNG_SR register *******************/ 05142 #define RNG_SR_DRDY ((uint32_t)0x00000001) 05143 #define RNG_SR_CECS ((uint32_t)0x00000002) 05144 #define RNG_SR_SECS ((uint32_t)0x00000004) 05145 #define RNG_SR_CEIS ((uint32_t)0x00000020) 05146 #define RNG_SR_SEIS ((uint32_t)0x00000040) 05147 05148 /******************************************************************************/ 05149 /* */ 05150 /* Real-Time Clock (RTC) */ 05151 /* */ 05152 /******************************************************************************/ 05153 /******************** Bits definition for RTC_TR register *******************/ 05154 #define RTC_TR_PM ((uint32_t)0x00400000) 05155 #define RTC_TR_HT ((uint32_t)0x00300000) 05156 #define RTC_TR_HT_0 ((uint32_t)0x00100000) 05157 #define RTC_TR_HT_1 ((uint32_t)0x00200000) 05158 #define RTC_TR_HU ((uint32_t)0x000F0000) 05159 #define RTC_TR_HU_0 ((uint32_t)0x00010000) 05160 #define RTC_TR_HU_1 ((uint32_t)0x00020000) 05161 #define RTC_TR_HU_2 ((uint32_t)0x00040000) 05162 #define RTC_TR_HU_3 ((uint32_t)0x00080000) 05163 #define RTC_TR_MNT ((uint32_t)0x00007000) 05164 #define RTC_TR_MNT_0 ((uint32_t)0x00001000) 05165 #define RTC_TR_MNT_1 ((uint32_t)0x00002000) 05166 #define RTC_TR_MNT_2 ((uint32_t)0x00004000) 05167 #define RTC_TR_MNU ((uint32_t)0x00000F00) 05168 #define RTC_TR_MNU_0 ((uint32_t)0x00000100) 05169 #define RTC_TR_MNU_1 ((uint32_t)0x00000200) 05170 #define RTC_TR_MNU_2 ((uint32_t)0x00000400) 05171 #define RTC_TR_MNU_3 ((uint32_t)0x00000800) 05172 #define RTC_TR_ST ((uint32_t)0x00000070) 05173 #define RTC_TR_ST_0 ((uint32_t)0x00000010) 05174 #define RTC_TR_ST_1 ((uint32_t)0x00000020) 05175 #define RTC_TR_ST_2 ((uint32_t)0x00000040) 05176 #define RTC_TR_SU ((uint32_t)0x0000000F) 05177 #define RTC_TR_SU_0 ((uint32_t)0x00000001) 05178 #define RTC_TR_SU_1 ((uint32_t)0x00000002) 05179 #define RTC_TR_SU_2 ((uint32_t)0x00000004) 05180 #define RTC_TR_SU_3 ((uint32_t)0x00000008) 05181 05182 /******************** Bits definition for RTC_DR register *******************/ 05183 #define RTC_DR_YT ((uint32_t)0x00F00000) 05184 #define RTC_DR_YT_0 ((uint32_t)0x00100000) 05185 #define RTC_DR_YT_1 ((uint32_t)0x00200000) 05186 #define RTC_DR_YT_2 ((uint32_t)0x00400000) 05187 #define RTC_DR_YT_3 ((uint32_t)0x00800000) 05188 #define RTC_DR_YU ((uint32_t)0x000F0000) 05189 #define RTC_DR_YU_0 ((uint32_t)0x00010000) 05190 #define RTC_DR_YU_1 ((uint32_t)0x00020000) 05191 #define RTC_DR_YU_2 ((uint32_t)0x00040000) 05192 #define RTC_DR_YU_3 ((uint32_t)0x00080000) 05193 #define RTC_DR_WDU ((uint32_t)0x0000E000) 05194 #define RTC_DR_WDU_0 ((uint32_t)0x00002000) 05195 #define RTC_DR_WDU_1 ((uint32_t)0x00004000) 05196 #define RTC_DR_WDU_2 ((uint32_t)0x00008000) 05197 #define RTC_DR_MT ((uint32_t)0x00001000) 05198 #define RTC_DR_MU ((uint32_t)0x00000F00) 05199 #define RTC_DR_MU_0 ((uint32_t)0x00000100) 05200 #define RTC_DR_MU_1 ((uint32_t)0x00000200) 05201 #define RTC_DR_MU_2 ((uint32_t)0x00000400) 05202 #define RTC_DR_MU_3 ((uint32_t)0x00000800) 05203 #define RTC_DR_DT ((uint32_t)0x00000030) 05204 #define RTC_DR_DT_0 ((uint32_t)0x00000010) 05205 #define RTC_DR_DT_1 ((uint32_t)0x00000020) 05206 #define RTC_DR_DU ((uint32_t)0x0000000F) 05207 #define RTC_DR_DU_0 ((uint32_t)0x00000001) 05208 #define RTC_DR_DU_1 ((uint32_t)0x00000002) 05209 #define RTC_DR_DU_2 ((uint32_t)0x00000004) 05210 #define RTC_DR_DU_3 ((uint32_t)0x00000008) 05211 05212 /******************** Bits definition for RTC_CR register *******************/ 05213 #define RTC_CR_COE ((uint32_t)0x00800000) 05214 #define RTC_CR_OSEL ((uint32_t)0x00600000) 05215 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000) 05216 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000) 05217 #define RTC_CR_POL ((uint32_t)0x00100000) 05218 #define RTC_CR_BCK ((uint32_t)0x00040000) 05219 #define RTC_CR_SUB1H ((uint32_t)0x00020000) 05220 #define RTC_CR_ADD1H ((uint32_t)0x00010000) 05221 #define RTC_CR_TSIE ((uint32_t)0x00008000) 05222 #define RTC_CR_WUTIE ((uint32_t)0x00004000) 05223 #define RTC_CR_ALRBIE ((uint32_t)0x00002000) 05224 #define RTC_CR_ALRAIE ((uint32_t)0x00001000) 05225 #define RTC_CR_TSE ((uint32_t)0x00000800) 05226 #define RTC_CR_WUTE ((uint32_t)0x00000400) 05227 #define RTC_CR_ALRBE ((uint32_t)0x00000200) 05228 #define RTC_CR_ALRAE ((uint32_t)0x00000100) 05229 #define RTC_CR_DCE ((uint32_t)0x00000080) 05230 #define RTC_CR_FMT ((uint32_t)0x00000040) 05231 #define RTC_CR_REFCKON ((uint32_t)0x00000010) 05232 #define RTC_CR_TSEDGE ((uint32_t)0x00000008) 05233 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007) 05234 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001) 05235 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002) 05236 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004) 05237 05238 /******************** Bits definition for RTC_ISR register ******************/ 05239 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000) 05240 #define RTC_ISR_TSOVF ((uint32_t)0x00001000) 05241 #define RTC_ISR_TSF ((uint32_t)0x00000800) 05242 #define RTC_ISR_WUTF ((uint32_t)0x00000400) 05243 #define RTC_ISR_ALRBF ((uint32_t)0x00000200) 05244 #define RTC_ISR_ALRAF ((uint32_t)0x00000100) 05245 #define RTC_ISR_INIT ((uint32_t)0x00000080) 05246 #define RTC_ISR_INITF ((uint32_t)0x00000040) 05247 #define RTC_ISR_RSF ((uint32_t)0x00000020) 05248 #define RTC_ISR_INITS ((uint32_t)0x00000010) 05249 #define RTC_ISR_WUTWF ((uint32_t)0x00000004) 05250 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002) 05251 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001) 05252 05253 /******************** Bits definition for RTC_PRER register *****************/ 05254 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000) 05255 #define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF) 05256 05257 /******************** Bits definition for RTC_WUTR register *****************/ 05258 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF) 05259 05260 /******************** Bits definition for RTC_CALIBR register ***************/ 05261 #define RTC_CALIBR_DCS ((uint32_t)0x00000080) 05262 #define RTC_CALIBR_DC ((uint32_t)0x0000001F) 05263 05264 /******************** Bits definition for RTC_ALRMAR register ***************/ 05265 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000) 05266 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000) 05267 #define RTC_ALRMAR_DT ((uint32_t)0x30000000) 05268 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000) 05269 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000) 05270 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000) 05271 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000) 05272 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000) 05273 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000) 05274 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000) 05275 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000) 05276 #define RTC_ALRMAR_PM ((uint32_t)0x00400000) 05277 #define RTC_ALRMAR_HT ((uint32_t)0x00300000) 05278 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000) 05279 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000) 05280 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000) 05281 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000) 05282 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000) 05283 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000) 05284 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000) 05285 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000) 05286 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000) 05287 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000) 05288 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000) 05289 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000) 05290 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00) 05291 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100) 05292 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200) 05293 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400) 05294 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800) 05295 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080) 05296 #define RTC_ALRMAR_ST ((uint32_t)0x00000070) 05297 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010) 05298 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020) 05299 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040) 05300 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F) 05301 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001) 05302 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002) 05303 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004) 05304 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008) 05305 05306 /******************** Bits definition for RTC_ALRMBR register ***************/ 05307 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000) 05308 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000) 05309 #define RTC_ALRMBR_DT ((uint32_t)0x30000000) 05310 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000) 05311 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000) 05312 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000) 05313 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000) 05314 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000) 05315 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000) 05316 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000) 05317 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000) 05318 #define RTC_ALRMBR_PM ((uint32_t)0x00400000) 05319 #define RTC_ALRMBR_HT ((uint32_t)0x00300000) 05320 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000) 05321 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000) 05322 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000) 05323 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000) 05324 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000) 05325 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000) 05326 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000) 05327 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000) 05328 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000) 05329 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000) 05330 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000) 05331 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000) 05332 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00) 05333 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100) 05334 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200) 05335 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400) 05336 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800) 05337 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080) 05338 #define RTC_ALRMBR_ST ((uint32_t)0x00000070) 05339 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010) 05340 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020) 05341 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040) 05342 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F) 05343 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001) 05344 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002) 05345 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004) 05346 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008) 05347 05348 /******************** Bits definition for RTC_WPR register ******************/ 05349 #define RTC_WPR_KEY ((uint32_t)0x000000FF) 05350 05351 /******************** Bits definition for RTC_TSTR register *****************/ 05352 #define RTC_TSTR_PM ((uint32_t)0x00400000) 05353 #define RTC_TSTR_HT ((uint32_t)0x00300000) 05354 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000) 05355 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000) 05356 #define RTC_TSTR_HU ((uint32_t)0x000F0000) 05357 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000) 05358 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000) 05359 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000) 05360 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000) 05361 #define RTC_TSTR_MNT ((uint32_t)0x00007000) 05362 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000) 05363 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000) 05364 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000) 05365 #define RTC_TSTR_MNU ((uint32_t)0x00000F00) 05366 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100) 05367 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200) 05368 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400) 05369 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800) 05370 #define RTC_TSTR_ST ((uint32_t)0x00000070) 05371 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010) 05372 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020) 05373 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040) 05374 #define RTC_TSTR_SU ((uint32_t)0x0000000F) 05375 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001) 05376 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002) 05377 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004) 05378 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008) 05379 05380 /******************** Bits definition for RTC_TSDR register *****************/ 05381 #define RTC_TSDR_WDU ((uint32_t)0x0000E000) 05382 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000) 05383 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000) 05384 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000) 05385 #define RTC_TSDR_MT ((uint32_t)0x00001000) 05386 #define RTC_TSDR_MU ((uint32_t)0x00000F00) 05387 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100) 05388 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200) 05389 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400) 05390 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800) 05391 #define RTC_TSDR_DT ((uint32_t)0x00000030) 05392 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010) 05393 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020) 05394 #define RTC_TSDR_DU ((uint32_t)0x0000000F) 05395 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001) 05396 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002) 05397 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004) 05398 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008) 05399 05400 /******************** Bits definition for RTC_TAFCR register ****************/ 05401 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000) 05402 #define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000) 05403 #define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000) 05404 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004) 05405 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002) 05406 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001) 05407 05408 /******************** Bits definition for RTC_BKP0R register ****************/ 05409 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF) 05410 05411 /******************** Bits definition for RTC_BKP1R register ****************/ 05412 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF) 05413 05414 /******************** Bits definition for RTC_BKP2R register ****************/ 05415 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF) 05416 05417 /******************** Bits definition for RTC_BKP3R register ****************/ 05418 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF) 05419 05420 /******************** Bits definition for RTC_BKP4R register ****************/ 05421 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF) 05422 05423 /******************** Bits definition for RTC_BKP5R register ****************/ 05424 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF) 05425 05426 /******************** Bits definition for RTC_BKP6R register ****************/ 05427 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF) 05428 05429 /******************** Bits definition for RTC_BKP7R register ****************/ 05430 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF) 05431 05432 /******************** Bits definition for RTC_BKP8R register ****************/ 05433 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF) 05434 05435 /******************** Bits definition for RTC_BKP9R register ****************/ 05436 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF) 05437 05438 /******************** Bits definition for RTC_BKP10R register ***************/ 05439 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF) 05440 05441 /******************** Bits definition for RTC_BKP11R register ***************/ 05442 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF) 05443 05444 /******************** Bits definition for RTC_BKP12R register ***************/ 05445 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF) 05446 05447 /******************** Bits definition for RTC_BKP13R register ***************/ 05448 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF) 05449 05450 /******************** Bits definition for RTC_BKP14R register ***************/ 05451 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF) 05452 05453 /******************** Bits definition for RTC_BKP15R register ***************/ 05454 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF) 05455 05456 /******************** Bits definition for RTC_BKP16R register ***************/ 05457 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF) 05458 05459 /******************** Bits definition for RTC_BKP17R register ***************/ 05460 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF) 05461 05462 /******************** Bits definition for RTC_BKP18R register ***************/ 05463 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF) 05464 05465 /******************** Bits definition for RTC_BKP19R register ***************/ 05466 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF) 05467 05468 /******************************************************************************/ 05469 /* */ 05470 /* SD host Interface */ 05471 /* */ 05472 /******************************************************************************/ 05473 /****************** Bit definition for SDIO_POWER register ******************/ 05474 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) 05475 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) 05476 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) 05478 /****************** Bit definition for SDIO_CLKCR register ******************/ 05479 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) 05480 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) 05481 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) 05482 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) 05484 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) 05485 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) 05486 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) 05488 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) 05489 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) 05491 /******************* Bit definition for SDIO_ARG register *******************/ 05492 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) 05494 /******************* Bit definition for SDIO_CMD register *******************/ 05495 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) 05497 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) 05498 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) 05499 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) 05501 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) 05502 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) 05503 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) 05504 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) 05505 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) 05506 #define SDIO_CMD_NIEN ((uint16_t)0x2000) 05507 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) 05509 /***************** Bit definition for SDIO_RESPCMD register *****************/ 05510 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) 05512 /****************** Bit definition for SDIO_RESP0 register ******************/ 05513 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) 05515 /****************** Bit definition for SDIO_RESP1 register ******************/ 05516 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) 05518 /****************** Bit definition for SDIO_RESP2 register ******************/ 05519 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) 05521 /****************** Bit definition for SDIO_RESP3 register ******************/ 05522 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) 05524 /****************** Bit definition for SDIO_RESP4 register ******************/ 05525 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) 05527 /****************** Bit definition for SDIO_DTIMER register *****************/ 05528 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) 05530 /****************** Bit definition for SDIO_DLEN register *******************/ 05531 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) 05533 /****************** Bit definition for SDIO_DCTRL register ******************/ 05534 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) 05535 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) 05536 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) 05537 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) 05539 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) 05540 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) 05541 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) 05542 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) 05543 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) 05545 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) 05546 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) 05547 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) 05548 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) 05550 /****************** Bit definition for SDIO_DCOUNT register *****************/ 05551 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) 05553 /****************** Bit definition for SDIO_STA register ********************/ 05554 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) 05555 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) 05556 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) 05557 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) 05558 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) 05559 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) 05560 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) 05561 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) 05562 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) 05563 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) 05564 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) 05565 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) 05566 #define SDIO_STA_TXACT ((uint32_t)0x00001000) 05567 #define SDIO_STA_RXACT ((uint32_t)0x00002000) 05568 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) 05569 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) 05570 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) 05571 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) 05572 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) 05573 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) 05574 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) 05575 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) 05576 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) 05577 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) 05579 /******************* Bit definition for SDIO_ICR register *******************/ 05580 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) 05581 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) 05582 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) 05583 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) 05584 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) 05585 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) 05586 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) 05587 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) 05588 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) 05589 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) 05590 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) 05591 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) 05592 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) 05594 /****************** Bit definition for SDIO_MASK register *******************/ 05595 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) 05596 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) 05597 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) 05598 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) 05599 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) 05600 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) 05601 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) 05602 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) 05603 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) 05604 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) 05605 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) 05606 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) 05607 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) 05608 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) 05609 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) 05610 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) 05611 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) 05612 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) 05613 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) 05614 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) 05615 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) 05616 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) 05617 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) 05618 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) 05620 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 05621 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) 05623 /****************** Bit definition for SDIO_FIFO register *******************/ 05624 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) 05626 /******************************************************************************/ 05627 /* */ 05628 /* Serial Peripheral Interface */ 05629 /* */ 05630 /******************************************************************************/ 05631 /******************* Bit definition for SPI_CR1 register ********************/ 05632 #define SPI_CR1_CPHA ((uint16_t)0x0001) 05633 #define SPI_CR1_CPOL ((uint16_t)0x0002) 05634 #define SPI_CR1_MSTR ((uint16_t)0x0004) 05636 #define SPI_CR1_BR ((uint16_t)0x0038) 05637 #define SPI_CR1_BR_0 ((uint16_t)0x0008) 05638 #define SPI_CR1_BR_1 ((uint16_t)0x0010) 05639 #define SPI_CR1_BR_2 ((uint16_t)0x0020) 05641 #define SPI_CR1_SPE ((uint16_t)0x0040) 05642 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) 05643 #define SPI_CR1_SSI ((uint16_t)0x0100) 05644 #define SPI_CR1_SSM ((uint16_t)0x0200) 05645 #define SPI_CR1_RXONLY ((uint16_t)0x0400) 05646 #define SPI_CR1_DFF ((uint16_t)0x0800) 05647 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) 05648 #define SPI_CR1_CRCEN ((uint16_t)0x2000) 05649 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) 05650 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) 05652 /******************* Bit definition for SPI_CR2 register ********************/ 05653 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) 05654 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) 05655 #define SPI_CR2_SSOE ((uint8_t)0x04) 05656 #define SPI_CR2_ERRIE ((uint8_t)0x20) 05657 #define SPI_CR2_RXNEIE ((uint8_t)0x40) 05658 #define SPI_CR2_TXEIE ((uint8_t)0x80) 05660 /******************** Bit definition for SPI_SR register ********************/ 05661 #define SPI_SR_RXNE ((uint8_t)0x01) 05662 #define SPI_SR_TXE ((uint8_t)0x02) 05663 #define SPI_SR_CHSIDE ((uint8_t)0x04) 05664 #define SPI_SR_UDR ((uint8_t)0x08) 05665 #define SPI_SR_CRCERR ((uint8_t)0x10) 05666 #define SPI_SR_MODF ((uint8_t)0x20) 05667 #define SPI_SR_OVR ((uint8_t)0x40) 05668 #define SPI_SR_BSY ((uint8_t)0x80) 05670 /******************** Bit definition for SPI_DR register ********************/ 05671 #define SPI_DR_DR ((uint16_t)0xFFFF) 05673 /******************* Bit definition for SPI_CRCPR register ******************/ 05674 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) 05676 /****************** Bit definition for SPI_RXCRCR register ******************/ 05677 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) 05679 /****************** Bit definition for SPI_TXCRCR register ******************/ 05680 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) 05682 /****************** Bit definition for SPI_I2SCFGR register *****************/ 05683 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) 05685 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) 05686 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) 05687 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) 05689 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) 05691 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) 05692 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) 05693 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) 05695 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) 05697 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) 05698 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) 05699 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) 05701 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) 05702 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) 05704 /****************** Bit definition for SPI_I2SPR register *******************/ 05705 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) 05706 #define SPI_I2SPR_ODD ((uint16_t)0x0100) 05707 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) 05709 /******************************************************************************/ 05710 /* */ 05711 /* SYSCFG */ 05712 /* */ 05713 /******************************************************************************/ 05714 /****************** Bit definition for SYSCFG_MEMRMP register ***************/ 05715 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) 05716 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) 05717 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) 05718 05719 /****************** Bit definition for SYSCFG_PMC register ******************/ 05720 #define SYSCFG_PMC_MII_RMII ((uint16_t)0x0080) 05722 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 05723 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) 05724 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) 05725 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) 05726 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) 05730 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) 05731 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) 05732 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) 05733 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) 05734 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) 05735 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) 05736 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) 05737 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) 05738 #define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) 05742 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) 05743 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) 05744 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) 05745 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) 05746 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) 05747 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) 05748 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) 05749 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) 05750 #define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) 05754 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) 05755 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) 05756 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) 05757 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) 05758 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) 05759 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) 05760 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) 05761 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) 05762 #define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) 05766 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) 05767 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) 05768 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) 05769 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) 05770 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) 05771 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) 05772 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) 05773 #define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) 05774 #define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) 05776 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/ 05777 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) 05778 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) 05779 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) 05780 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) 05784 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) 05785 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) 05786 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) 05787 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) 05788 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) 05789 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) 05790 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) 05791 #define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) 05792 #define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) 05796 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) 05797 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) 05798 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) 05799 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) 05800 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) 05801 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) 05802 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) 05803 #define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) 05804 #define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) 05808 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) 05809 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) 05810 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) 05811 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) 05812 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) 05813 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) 05814 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) 05815 #define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) 05816 #define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) 05820 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) 05821 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) 05822 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) 05823 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) 05824 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) 05825 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) 05826 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) 05827 #define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) 05828 #define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) 05830 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/ 05831 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) 05832 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) 05833 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) 05834 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) 05839 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) 05840 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) 05841 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) 05842 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) 05843 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) 05844 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) 05845 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) 05846 #define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) 05847 #define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) 05851 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) 05852 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) 05853 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) 05854 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) 05855 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) 05856 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) 05857 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) 05858 #define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) 05859 #define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) 05863 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) 05864 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) 05865 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) 05866 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) 05867 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) 05868 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) 05869 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) 05870 #define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) 05871 #define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) 05875 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) 05876 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) 05877 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) 05878 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) 05879 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) 05880 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) 05881 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) 05882 #define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) 05883 #define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) 05885 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/ 05886 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) 05887 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) 05888 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) 05889 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) 05893 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) 05894 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) 05895 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) 05896 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) 05897 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) 05898 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) 05899 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) 05900 #define SYSCFG_EXTICR3_EXTI12_PH ((uint16_t)0x0007) 05904 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) 05905 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) 05906 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) 05907 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) 05908 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) 05909 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) 05910 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) 05911 #define SYSCFG_EXTICR3_EXTI13_PH ((uint16_t)0x0070) 05915 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) 05916 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) 05917 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) 05918 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) 05919 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) 05920 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) 05921 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) 05922 #define SYSCFG_EXTICR3_EXTI14_PH ((uint16_t)0x0700) 05926 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) 05927 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) 05928 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) 05929 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) 05930 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) 05931 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) 05932 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) 05933 #define SYSCFG_EXTICR3_EXTI15_PH ((uint16_t)0x7000) 05935 /****************** Bit definition for SYSCFG_CMPCR register ****************/ 05936 #define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) 05937 #define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) 05939 /******************************************************************************/ 05940 /* */ 05941 /* TIM */ 05942 /* */ 05943 /******************************************************************************/ 05944 /******************* Bit definition for TIM_CR1 register ********************/ 05945 #define TIM_CR1_CEN ((uint16_t)0x0001) 05946 #define TIM_CR1_UDIS ((uint16_t)0x0002) 05947 #define TIM_CR1_URS ((uint16_t)0x0004) 05948 #define TIM_CR1_OPM ((uint16_t)0x0008) 05949 #define TIM_CR1_DIR ((uint16_t)0x0010) 05951 #define TIM_CR1_CMS ((uint16_t)0x0060) 05952 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) 05953 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) 05955 #define TIM_CR1_ARPE ((uint16_t)0x0080) 05957 #define TIM_CR1_CKD ((uint16_t)0x0300) 05958 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) 05959 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) 05961 /******************* Bit definition for TIM_CR2 register ********************/ 05962 #define TIM_CR2_CCPC ((uint16_t)0x0001) 05963 #define TIM_CR2_CCUS ((uint16_t)0x0004) 05964 #define TIM_CR2_CCDS ((uint16_t)0x0008) 05966 #define TIM_CR2_MMS ((uint16_t)0x0070) 05967 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) 05968 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) 05969 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) 05971 #define TIM_CR2_TI1S ((uint16_t)0x0080) 05972 #define TIM_CR2_OIS1 ((uint16_t)0x0100) 05973 #define TIM_CR2_OIS1N ((uint16_t)0x0200) 05974 #define TIM_CR2_OIS2 ((uint16_t)0x0400) 05975 #define TIM_CR2_OIS2N ((uint16_t)0x0800) 05976 #define TIM_CR2_OIS3 ((uint16_t)0x1000) 05977 #define TIM_CR2_OIS3N ((uint16_t)0x2000) 05978 #define TIM_CR2_OIS4 ((uint16_t)0x4000) 05980 /******************* Bit definition for TIM_SMCR register *******************/ 05981 #define TIM_SMCR_SMS ((uint16_t)0x0007) 05982 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) 05983 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) 05984 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) 05986 #define TIM_SMCR_TS ((uint16_t)0x0070) 05987 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) 05988 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) 05989 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) 05991 #define TIM_SMCR_MSM ((uint16_t)0x0080) 05993 #define TIM_SMCR_ETF ((uint16_t)0x0F00) 05994 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) 05995 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) 05996 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) 05997 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) 05999 #define TIM_SMCR_ETPS ((uint16_t)0x3000) 06000 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) 06001 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) 06003 #define TIM_SMCR_ECE ((uint16_t)0x4000) 06004 #define TIM_SMCR_ETP ((uint16_t)0x8000) 06006 /******************* Bit definition for TIM_DIER register *******************/ 06007 #define TIM_DIER_UIE ((uint16_t)0x0001) 06008 #define TIM_DIER_CC1IE ((uint16_t)0x0002) 06009 #define TIM_DIER_CC2IE ((uint16_t)0x0004) 06010 #define TIM_DIER_CC3IE ((uint16_t)0x0008) 06011 #define TIM_DIER_CC4IE ((uint16_t)0x0010) 06012 #define TIM_DIER_COMIE ((uint16_t)0x0020) 06013 #define TIM_DIER_TIE ((uint16_t)0x0040) 06014 #define TIM_DIER_BIE ((uint16_t)0x0080) 06015 #define TIM_DIER_UDE ((uint16_t)0x0100) 06016 #define TIM_DIER_CC1DE ((uint16_t)0x0200) 06017 #define TIM_DIER_CC2DE ((uint16_t)0x0400) 06018 #define TIM_DIER_CC3DE ((uint16_t)0x0800) 06019 #define TIM_DIER_CC4DE ((uint16_t)0x1000) 06020 #define TIM_DIER_COMDE ((uint16_t)0x2000) 06021 #define TIM_DIER_TDE ((uint16_t)0x4000) 06023 /******************** Bit definition for TIM_SR register ********************/ 06024 #define TIM_SR_UIF ((uint16_t)0x0001) 06025 #define TIM_SR_CC1IF ((uint16_t)0x0002) 06026 #define TIM_SR_CC2IF ((uint16_t)0x0004) 06027 #define TIM_SR_CC3IF ((uint16_t)0x0008) 06028 #define TIM_SR_CC4IF ((uint16_t)0x0010) 06029 #define TIM_SR_COMIF ((uint16_t)0x0020) 06030 #define TIM_SR_TIF ((uint16_t)0x0040) 06031 #define TIM_SR_BIF ((uint16_t)0x0080) 06032 #define TIM_SR_CC1OF ((uint16_t)0x0200) 06033 #define TIM_SR_CC2OF ((uint16_t)0x0400) 06034 #define TIM_SR_CC3OF ((uint16_t)0x0800) 06035 #define TIM_SR_CC4OF ((uint16_t)0x1000) 06037 /******************* Bit definition for TIM_EGR register ********************/ 06038 #define TIM_EGR_UG ((uint8_t)0x01) 06039 #define TIM_EGR_CC1G ((uint8_t)0x02) 06040 #define TIM_EGR_CC2G ((uint8_t)0x04) 06041 #define TIM_EGR_CC3G ((uint8_t)0x08) 06042 #define TIM_EGR_CC4G ((uint8_t)0x10) 06043 #define TIM_EGR_COMG ((uint8_t)0x20) 06044 #define TIM_EGR_TG ((uint8_t)0x40) 06045 #define TIM_EGR_BG ((uint8_t)0x80) 06047 /****************** Bit definition for TIM_CCMR1 register *******************/ 06048 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) 06049 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) 06050 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) 06052 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) 06053 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) 06055 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) 06056 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 06057 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 06058 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 06060 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) 06062 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) 06063 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 06064 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 06066 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) 06067 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) 06069 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) 06070 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 06071 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 06072 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 06074 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) 06076 /*----------------------------------------------------------------------------*/ 06077 06078 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 06079 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 06080 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 06082 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) 06083 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 06084 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 06085 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 06086 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 06088 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 06089 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) 06090 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) 06092 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) 06093 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) 06094 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) 06095 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) 06096 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) 06098 /****************** Bit definition for TIM_CCMR2 register *******************/ 06099 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) 06100 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) 06101 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) 06103 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) 06104 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) 06106 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) 06107 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) 06108 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) 06109 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) 06111 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) 06113 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) 06114 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) 06115 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) 06117 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) 06118 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) 06120 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) 06121 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) 06122 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) 06123 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) 06125 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) 06127 /*----------------------------------------------------------------------------*/ 06128 06129 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) 06130 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) 06131 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) 06133 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) 06134 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) 06135 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) 06136 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) 06137 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) 06139 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) 06140 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) 06141 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) 06143 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) 06144 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) 06145 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) 06146 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) 06147 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) 06149 /******************* Bit definition for TIM_CCER register *******************/ 06150 #define TIM_CCER_CC1E ((uint16_t)0x0001) 06151 #define TIM_CCER_CC1P ((uint16_t)0x0002) 06152 #define TIM_CCER_CC1NE ((uint16_t)0x0004) 06153 #define TIM_CCER_CC1NP ((uint16_t)0x0008) 06154 #define TIM_CCER_CC2E ((uint16_t)0x0010) 06155 #define TIM_CCER_CC2P ((uint16_t)0x0020) 06156 #define TIM_CCER_CC2NE ((uint16_t)0x0040) 06157 #define TIM_CCER_CC2NP ((uint16_t)0x0080) 06158 #define TIM_CCER_CC3E ((uint16_t)0x0100) 06159 #define TIM_CCER_CC3P ((uint16_t)0x0200) 06160 #define TIM_CCER_CC3NE ((uint16_t)0x0400) 06161 #define TIM_CCER_CC3NP ((uint16_t)0x0800) 06162 #define TIM_CCER_CC4E ((uint16_t)0x1000) 06163 #define TIM_CCER_CC4P ((uint16_t)0x2000) 06164 #define TIM_CCER_CC4NP ((uint16_t)0x8000) 06166 /******************* Bit definition for TIM_CNT register ********************/ 06167 #define TIM_CNT_CNT ((uint16_t)0xFFFF) 06169 /******************* Bit definition for TIM_PSC register ********************/ 06170 #define TIM_PSC_PSC ((uint16_t)0xFFFF) 06172 /******************* Bit definition for TIM_ARR register ********************/ 06173 #define TIM_ARR_ARR ((uint16_t)0xFFFF) 06175 /******************* Bit definition for TIM_RCR register ********************/ 06176 #define TIM_RCR_REP ((uint8_t)0xFF) 06178 /******************* Bit definition for TIM_CCR1 register *******************/ 06179 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) 06181 /******************* Bit definition for TIM_CCR2 register *******************/ 06182 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) 06184 /******************* Bit definition for TIM_CCR3 register *******************/ 06185 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) 06187 /******************* Bit definition for TIM_CCR4 register *******************/ 06188 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) 06190 /******************* Bit definition for TIM_BDTR register *******************/ 06191 #define TIM_BDTR_DTG ((uint16_t)0x00FF) 06192 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) 06193 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) 06194 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) 06195 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) 06196 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) 06197 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) 06198 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) 06199 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) 06201 #define TIM_BDTR_LOCK ((uint16_t)0x0300) 06202 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) 06203 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) 06205 #define TIM_BDTR_OSSI ((uint16_t)0x0400) 06206 #define TIM_BDTR_OSSR ((uint16_t)0x0800) 06207 #define TIM_BDTR_BKE ((uint16_t)0x1000) 06208 #define TIM_BDTR_BKP ((uint16_t)0x2000) 06209 #define TIM_BDTR_AOE ((uint16_t)0x4000) 06210 #define TIM_BDTR_MOE ((uint16_t)0x8000) 06212 /******************* Bit definition for TIM_DCR register ********************/ 06213 #define TIM_DCR_DBA ((uint16_t)0x001F) 06214 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) 06215 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) 06216 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) 06217 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) 06218 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) 06220 #define TIM_DCR_DBL ((uint16_t)0x1F00) 06221 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) 06222 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) 06223 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) 06224 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) 06225 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) 06227 /******************* Bit definition for TIM_DMAR register *******************/ 06228 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) 06230 /******************* Bit definition for TIM_OR register *********************/ 06231 #define TIM_OR_TI4_RMP ((uint16_t)0x00C0) 06232 #define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) 06233 #define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) 06234 #define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) 06235 #define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) 06236 #define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) 06239 /******************************************************************************/ 06240 /* */ 06241 /* Universal Synchronous Asynchronous Receiver Transmitter */ 06242 /* */ 06243 /******************************************************************************/ 06244 /******************* Bit definition for USART_SR register *******************/ 06245 #define USART_SR_PE ((uint16_t)0x0001) 06246 #define USART_SR_FE ((uint16_t)0x0002) 06247 #define USART_SR_NE ((uint16_t)0x0004) 06248 #define USART_SR_ORE ((uint16_t)0x0008) 06249 #define USART_SR_IDLE ((uint16_t)0x0010) 06250 #define USART_SR_RXNE ((uint16_t)0x0020) 06251 #define USART_SR_TC ((uint16_t)0x0040) 06252 #define USART_SR_TXE ((uint16_t)0x0080) 06253 #define USART_SR_LBD ((uint16_t)0x0100) 06254 #define USART_SR_CTS ((uint16_t)0x0200) 06256 /******************* Bit definition for USART_DR register *******************/ 06257 #define USART_DR_DR ((uint16_t)0x01FF) 06259 /****************** Bit definition for USART_BRR register *******************/ 06260 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) 06261 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) 06263 /****************** Bit definition for USART_CR1 register *******************/ 06264 #define USART_CR1_SBK ((uint16_t)0x0001) 06265 #define USART_CR1_RWU ((uint16_t)0x0002) 06266 #define USART_CR1_RE ((uint16_t)0x0004) 06267 #define USART_CR1_TE ((uint16_t)0x0008) 06268 #define USART_CR1_IDLEIE ((uint16_t)0x0010) 06269 #define USART_CR1_RXNEIE ((uint16_t)0x0020) 06270 #define USART_CR1_TCIE ((uint16_t)0x0040) 06271 #define USART_CR1_TXEIE ((uint16_t)0x0080) 06272 #define USART_CR1_PEIE ((uint16_t)0x0100) 06273 #define USART_CR1_PS ((uint16_t)0x0200) 06274 #define USART_CR1_PCE ((uint16_t)0x0400) 06275 #define USART_CR1_WAKE ((uint16_t)0x0800) 06276 #define USART_CR1_M ((uint16_t)0x1000) 06277 #define USART_CR1_UE ((uint16_t)0x2000) 06278 #define USART_CR1_OVER8 ((uint16_t)0x8000) 06280 /****************** Bit definition for USART_CR2 register *******************/ 06281 #define USART_CR2_ADD ((uint16_t)0x000F) 06282 #define USART_CR2_LBDL ((uint16_t)0x0020) 06283 #define USART_CR2_LBDIE ((uint16_t)0x0040) 06284 #define USART_CR2_LBCL ((uint16_t)0x0100) 06285 #define USART_CR2_CPHA ((uint16_t)0x0200) 06286 #define USART_CR2_CPOL ((uint16_t)0x0400) 06287 #define USART_CR2_CLKEN ((uint16_t)0x0800) 06289 #define USART_CR2_STOP ((uint16_t)0x3000) 06290 #define USART_CR2_STOP_0 ((uint16_t)0x1000) 06291 #define USART_CR2_STOP_1 ((uint16_t)0x2000) 06293 #define USART_CR2_LINEN ((uint16_t)0x4000) 06295 /****************** Bit definition for USART_CR3 register *******************/ 06296 #define USART_CR3_EIE ((uint16_t)0x0001) 06297 #define USART_CR3_IREN ((uint16_t)0x0002) 06298 #define USART_CR3_IRLP ((uint16_t)0x0004) 06299 #define USART_CR3_HDSEL ((uint16_t)0x0008) 06300 #define USART_CR3_NACK ((uint16_t)0x0010) 06301 #define USART_CR3_SCEN ((uint16_t)0x0020) 06302 #define USART_CR3_DMAR ((uint16_t)0x0040) 06303 #define USART_CR3_DMAT ((uint16_t)0x0080) 06304 #define USART_CR3_RTSE ((uint16_t)0x0100) 06305 #define USART_CR3_CTSE ((uint16_t)0x0200) 06306 #define USART_CR3_CTSIE ((uint16_t)0x0400) 06307 #define USART_CR3_ONEBIT ((uint16_t)0x0800) 06309 /****************** Bit definition for USART_GTPR register ******************/ 06310 #define USART_GTPR_PSC ((uint16_t)0x00FF) 06311 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) 06312 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) 06313 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) 06314 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) 06315 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) 06316 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) 06317 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) 06318 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) 06320 #define USART_GTPR_GT ((uint16_t)0xFF00) 06322 /******************************************************************************/ 06323 /* */ 06324 /* Window WATCHDOG */ 06325 /* */ 06326 /******************************************************************************/ 06327 /******************* Bit definition for WWDG_CR register ********************/ 06328 #define WWDG_CR_T ((uint8_t)0x7F) 06329 #define WWDG_CR_T0 ((uint8_t)0x01) 06330 #define WWDG_CR_T1 ((uint8_t)0x02) 06331 #define WWDG_CR_T2 ((uint8_t)0x04) 06332 #define WWDG_CR_T3 ((uint8_t)0x08) 06333 #define WWDG_CR_T4 ((uint8_t)0x10) 06334 #define WWDG_CR_T5 ((uint8_t)0x20) 06335 #define WWDG_CR_T6 ((uint8_t)0x40) 06337 #define WWDG_CR_WDGA ((uint8_t)0x80) 06339 /******************* Bit definition for WWDG_CFR register *******************/ 06340 #define WWDG_CFR_W ((uint16_t)0x007F) 06341 #define WWDG_CFR_W0 ((uint16_t)0x0001) 06342 #define WWDG_CFR_W1 ((uint16_t)0x0002) 06343 #define WWDG_CFR_W2 ((uint16_t)0x0004) 06344 #define WWDG_CFR_W3 ((uint16_t)0x0008) 06345 #define WWDG_CFR_W4 ((uint16_t)0x0010) 06346 #define WWDG_CFR_W5 ((uint16_t)0x0020) 06347 #define WWDG_CFR_W6 ((uint16_t)0x0040) 06349 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) 06350 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) 06351 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) 06353 #define WWDG_CFR_EWI ((uint16_t)0x0200) 06355 /******************* Bit definition for WWDG_SR register ********************/ 06356 #define WWDG_SR_EWIF ((uint8_t)0x01) 06359 /******************************************************************************/ 06360 /* */ 06361 /* DBG */ 06362 /* */ 06363 /******************************************************************************/ 06364 /******************** Bit definition for DBGMCU_IDCODE register *************/ 06365 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 06366 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 06367 06368 /******************** Bit definition for DBGMCU_CR register *****************/ 06369 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 06370 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 06371 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 06372 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 06373 06374 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 06375 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) 06376 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) 06378 /******************** Bit definition for DBGMCU_APB1_FZ register ************/ 06379 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) 06380 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) 06381 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) 06382 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) 06383 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) 06384 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) 06385 #define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040) 06386 #define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080) 06387 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) 06388 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) 06389 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) 06390 #define DBGMCU_APB1_FZ_DBG_IWDEG_STOP ((uint32_t)0x00001000) 06391 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) 06392 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) 06393 #define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000) 06394 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000) 06395 #define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000) 06396 06397 /******************** Bit definition for DBGMCU_APB2_FZ register ************/ 06398 #define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001) 06399 #define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002) 06400 #define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000) 06401 #define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000) 06402 #define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000) 06403 06404 /******************************************************************************/ 06405 /* */ 06406 /* Ethernet MAC Registers bits definitions */ 06407 /* */ 06408 /******************************************************************************/ 06409 /* Bit definition for Ethernet MAC Control Register register */ 06410 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ 06411 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ 06412 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ 06413 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ 06414 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ 06415 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ 06416 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ 06417 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ 06418 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ 06419 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ 06420 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ 06421 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ 06422 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ 06423 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ 06424 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ 06425 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ 06426 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ 06427 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ 06428 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ 06429 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling 06430 a transmission attempt during retries after a collision: 0 =< r <2^k */ 06431 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ 06432 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ 06433 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ 06434 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ 06435 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ 06436 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ 06437 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ 06438 06439 /* Bit definition for Ethernet MAC Frame Filter Register */ 06440 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ 06441 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ 06442 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ 06443 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ 06444 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ 06445 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ 06446 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ 06447 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ 06448 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ 06449 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ 06450 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ 06451 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ 06452 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ 06453 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ 06454 06455 /* Bit definition for Ethernet MAC Hash Table High Register */ 06456 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ 06457 06458 /* Bit definition for Ethernet MAC Hash Table Low Register */ 06459 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ 06460 06461 /* Bit definition for Ethernet MAC MII Address Register */ 06462 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ 06463 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ 06464 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ 06465 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ 06466 #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-120 MHz; MDC clock= HCLK/62 */ 06467 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ 06468 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/42 */ 06469 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ 06470 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ 06471 06472 /* Bit definition for Ethernet MAC MII Data Register */ 06473 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ 06474 06475 /* Bit definition for Ethernet MAC Flow Control Register */ 06476 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ 06477 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ 06478 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ 06479 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ 06480 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ 06481 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ 06482 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ 06483 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ 06484 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ 06485 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ 06486 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ 06487 06488 /* Bit definition for Ethernet MAC VLAN Tag Register */ 06489 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ 06490 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ 06491 06492 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 06493 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ 06494 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. 06495 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ 06496 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask 06497 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask 06498 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask 06499 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask 06500 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 06501 RSVD - Filter1 Command - RSVD - Filter0 Command 06502 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset 06503 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 06504 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ 06505 06506 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 06507 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ 06508 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ 06509 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ 06510 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ 06511 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ 06512 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ 06513 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ 06514 06515 /* Bit definition for Ethernet MAC Status Register */ 06516 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ 06517 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ 06518 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ 06519 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ 06520 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ 06521 06522 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 06523 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ 06524 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ 06525 06526 /* Bit definition for Ethernet MAC Address0 High Register */ 06527 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ 06528 06529 /* Bit definition for Ethernet MAC Address0 Low Register */ 06530 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ 06531 06532 /* Bit definition for Ethernet MAC Address1 High Register */ 06533 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ 06534 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ 06535 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ 06536 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06537 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06538 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06539 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06540 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06541 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ 06542 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 06543 06544 /* Bit definition for Ethernet MAC Address1 Low Register */ 06545 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ 06546 06547 /* Bit definition for Ethernet MAC Address2 High Register */ 06548 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ 06549 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ 06550 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 06551 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06552 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06553 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06554 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06555 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06556 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 06557 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 06558 06559 /* Bit definition for Ethernet MAC Address2 Low Register */ 06560 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ 06561 06562 /* Bit definition for Ethernet MAC Address3 High Register */ 06563 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ 06564 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ 06565 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 06566 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 06567 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 06568 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 06569 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 06570 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 06571 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 06572 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ 06573 06574 /* Bit definition for Ethernet MAC Address3 Low Register */ 06575 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ 06576 06577 /******************************************************************************/ 06578 /* Ethernet MMC Registers bits definition */ 06579 /******************************************************************************/ 06580 06581 /* Bit definition for Ethernet MMC Contol Register */ 06582 #define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset (Only in STM32F2xx) */ 06583 #define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset (Only in STM32F2xx) */ 06584 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ 06585 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ 06586 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ 06587 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ 06588 06589 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 06590 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ 06591 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ 06592 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ 06593 06594 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 06595 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ 06596 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ 06597 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ 06598 06599 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 06600 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ 06601 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ 06602 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ 06603 06604 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 06605 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ 06606 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ 06607 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ 06608 06609 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ 06610 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ 06611 06612 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ 06613 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ 06614 06615 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ 06616 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ 06617 06618 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ 06619 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ 06620 06621 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ 06622 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ 06623 06624 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ 06625 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ 06626 06627 /******************************************************************************/ 06628 /* Ethernet PTP Registers bits definition */ 06629 /******************************************************************************/ 06630 06631 /* Bit definition for Ethernet PTP Time Stamp Contol Register */ 06632 #define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */ 06633 #define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */ 06634 #define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */ 06635 #define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ 06636 #define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ 06637 #define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ 06638 #define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ 06639 #define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */ 06640 #define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */ 06641 06642 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ 06643 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ 06644 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ 06645 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ 06646 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ 06647 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ 06648 06649 /* Bit definition for Ethernet PTP Sub-Second Increment Register */ 06650 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ 06651 06652 /* Bit definition for Ethernet PTP Time Stamp High Register */ 06653 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ 06654 06655 /* Bit definition for Ethernet PTP Time Stamp Low Register */ 06656 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ 06657 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ 06658 06659 /* Bit definition for Ethernet PTP Time Stamp High Update Register */ 06660 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ 06661 06662 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ 06663 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ 06664 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ 06665 06666 /* Bit definition for Ethernet PTP Time Stamp Addend Register */ 06667 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ 06668 06669 /* Bit definition for Ethernet PTP Target Time High Register */ 06670 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ 06671 06672 /* Bit definition for Ethernet PTP Target Time Low Register */ 06673 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ 06674 06675 /* Bit definition for Ethernet PTP Time Stamp Status Register */ 06676 #define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */ 06677 #define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */ 06678 06679 /******************************************************************************/ 06680 /* Ethernet DMA Registers bits definition */ 06681 /******************************************************************************/ 06682 06683 /* Bit definition for Ethernet DMA Bus Mode Register */ 06684 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ 06685 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ 06686 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ 06687 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ 06688 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ 06689 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ 06690 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 06691 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 06692 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 06693 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 06694 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 06695 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 06696 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 06697 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 06698 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ 06699 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ 06700 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ 06701 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 06702 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ 06703 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ 06704 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ 06705 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 06706 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ 06707 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 06708 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 06709 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 06710 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 06711 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 06712 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 06713 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 06714 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 06715 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 06716 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 06717 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 06718 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 06719 #define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */ 06720 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ 06721 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ 06722 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ 06723 06724 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ 06725 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ 06726 06727 /* Bit definition for Ethernet DMA Receive Poll Demand Register */ 06728 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ 06729 06730 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ 06731 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ 06732 06733 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ 06734 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ 06735 06736 /* Bit definition for Ethernet DMA Status Register */ 06737 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ 06738 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ 06739 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ 06740 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ 06741 /* combination with EBS[2:0] for GetFlagStatus function */ 06742 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ 06743 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ 06744 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ 06745 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ 06746 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ 06747 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ 06748 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ 06749 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ 06750 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ 06751 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ 06752 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ 06753 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ 06754 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ 06755 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ 06756 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ 06757 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ 06758 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ 06759 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ 06760 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ 06761 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ 06762 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ 06763 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ 06764 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ 06765 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ 06766 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ 06767 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ 06768 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ 06769 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ 06770 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ 06771 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ 06772 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ 06773 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ 06774 06775 /* Bit definition for Ethernet DMA Operation Mode Register */ 06776 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ 06777 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ 06778 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ 06779 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ 06780 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ 06781 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ 06782 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ 06783 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ 06784 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ 06785 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ 06786 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ 06787 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ 06788 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ 06789 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ 06790 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ 06791 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ 06792 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ 06793 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ 06794 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ 06795 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ 06796 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ 06797 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ 06798 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ 06799 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ 06800 06801 /* Bit definition for Ethernet DMA Interrupt Enable Register */ 06802 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ 06803 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ 06804 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ 06805 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ 06806 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ 06807 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ 06808 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ 06809 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ 06810 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ 06811 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ 06812 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ 06813 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ 06814 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ 06815 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ 06816 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ 06817 06818 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ 06819 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ 06820 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ 06821 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ 06822 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ 06823 06824 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ 06825 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ 06826 06827 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ 06828 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ 06829 06830 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ 06831 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ 06832 06833 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ 06834 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ 06835 06844 #ifdef USE_STDPERIPH_DRIVER 06845 #include "stm32f2xx_conf.h " 06846 #endif /* USE_STDPERIPH_DRIVER */ 06847 06852 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 06853 06854 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 06855 06856 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 06857 06858 #define CLEAR_REG(REG) ((REG) = (0x0)) 06859 06860 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 06861 06862 #define READ_REG(REG) ((REG)) 06863 06864 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 06865 06870 #ifdef __cplusplus 06871 } 06872 #endif /* __cplusplus */ 06873 06874 #endif /* __STM32F2xx_H */ 06875 06884 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/