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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 00032 #include <cfg/arch.h> 00033 #include <cfg/clock.h> 00034 00035 #ifndef __STM32F10x_H 00036 #define __STM32F10x_H 00037 00038 #ifdef __cplusplus 00039 extern "C" { 00040 #endif 00041 00046 #if !defined(HSE_VALUE) 00047 #ifdef STM32F10X_CL 00048 #define HSE_VALUE ((uint32_t)25000000) 00049 #else 00050 #define HSE_VALUE ((uint32_t)8000000) 00051 #endif /* STM32F10X_CL */ 00052 #endif /* HSE_VALUE */ 00053 00057 #define HSI_VALUE ((uint32_t)8000000) 00062 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) 00068 #define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) 00069 #define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) 00070 #define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) 00071 #define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\ 00072 | (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\ 00073 | __STM32F10X_STDPERIPH_VERSION_SUB2) 00074 00078 #ifdef STM32F10X_XL 00079 #define __MPU_PRESENT 1 00080 #else 00081 #define __MPU_PRESENT 0 00082 #endif /* STM32F10X_XL */ 00083 #define __NVIC_PRIO_BITS 4 00084 #define __Vendor_SysTickConfig 0 00090 typedef enum IRQn 00091 { 00092 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00093 NonMaskableInt_IRQn = -14, 00094 HardFault_IRQn = -13, 00095 MemoryManagement_IRQn = -12, 00096 BusFault_IRQn = -11, 00097 UsageFault_IRQn = -10, 00098 SVCall_IRQn = -5, 00099 DebugMonitor_IRQn = -4, 00100 PendSV_IRQn = -2, 00101 SysTick_IRQn = -1, 00103 /****** STM32 specific Interrupt Numbers *********************************************************/ 00104 WWDG_IRQn = 0, 00105 PVD_IRQn = 1, 00106 TAMPER_IRQn = 2, 00107 RTC_IRQn = 3, 00108 FLASH_IRQn = 4, 00109 RCC_IRQn = 5, 00110 EXTI0_IRQn = 6, 00111 EXTI1_IRQn = 7, 00112 EXTI2_IRQn = 8, 00113 EXTI3_IRQn = 9, 00114 EXTI4_IRQn = 10, 00115 DMA1_Channel1_IRQn = 11, 00116 DMA1_Channel2_IRQn = 12, 00117 DMA1_Channel3_IRQn = 13, 00118 DMA1_Channel4_IRQn = 14, 00119 DMA1_Channel5_IRQn = 15, 00120 DMA1_Channel6_IRQn = 16, 00121 DMA1_Channel7_IRQn = 17, 00123 #ifdef STM32F10X_LD 00124 ADC1_2_IRQn = 18, 00125 USB_HP_CAN1_TX_IRQn = 19, 00126 USB_LP_CAN1_RX0_IRQn = 20, 00127 CAN1_RX1_IRQn = 21, 00128 CAN1_SCE_IRQn = 22, 00129 EXTI9_5_IRQn = 23, 00130 TIM1_BRK_IRQn = 24, 00131 TIM1_UP_IRQn = 25, 00132 TIM1_TRG_COM_IRQn = 26, 00133 TIM1_CC_IRQn = 27, 00134 TIM2_IRQn = 28, 00135 TIM3_IRQn = 29, 00136 I2C1_EV_IRQn = 31, 00137 I2C1_ER_IRQn = 32, 00138 SPI1_IRQn = 35, 00139 USART1_IRQn = 37, 00140 USART2_IRQn = 38, 00141 EXTI15_10_IRQn = 40, 00142 RTCAlarm_IRQn = 41, 00143 USBWakeUp_IRQn = 42 00144 #endif /* STM32F10X_LD */ 00145 00146 #ifdef STM32F10X_LD_VL 00147 ADC1_IRQn = 18, 00148 EXTI9_5_IRQn = 23, 00149 TIM1_BRK_TIM15_IRQn = 24, 00150 TIM1_UP_TIM16_IRQn = 25, 00151 TIM1_TRG_COM_TIM17_IRQn = 26, 00152 TIM1_CC_IRQn = 27, 00153 TIM2_IRQn = 28, 00154 TIM3_IRQn = 29, 00155 I2C1_EV_IRQn = 31, 00156 I2C1_ER_IRQn = 32, 00157 SPI1_IRQn = 35, 00158 USART1_IRQn = 37, 00159 USART2_IRQn = 38, 00160 EXTI15_10_IRQn = 40, 00161 RTCAlarm_IRQn = 41, 00162 CEC_IRQn = 42, 00163 TIM6_DAC_IRQn = 54, 00164 TIM7_IRQn = 55 00165 #endif /* STM32F10X_LD_VL */ 00166 00167 #ifdef STM32F10X_MD 00168 ADC1_2_IRQn = 18, 00169 USB_HP_CAN1_TX_IRQn = 19, 00170 USB_LP_CAN1_RX0_IRQn = 20, 00171 CAN1_RX1_IRQn = 21, 00172 CAN1_SCE_IRQn = 22, 00173 EXTI9_5_IRQn = 23, 00174 TIM1_BRK_IRQn = 24, 00175 TIM1_UP_IRQn = 25, 00176 TIM1_TRG_COM_IRQn = 26, 00177 TIM1_CC_IRQn = 27, 00178 TIM2_IRQn = 28, 00179 TIM3_IRQn = 29, 00180 TIM4_IRQn = 30, 00181 I2C1_EV_IRQn = 31, 00182 I2C1_ER_IRQn = 32, 00183 I2C2_EV_IRQn = 33, 00184 I2C2_ER_IRQn = 34, 00185 SPI1_IRQn = 35, 00186 SPI2_IRQn = 36, 00187 USART1_IRQn = 37, 00188 USART2_IRQn = 38, 00189 USART3_IRQn = 39, 00190 EXTI15_10_IRQn = 40, 00191 RTCAlarm_IRQn = 41, 00192 USBWakeUp_IRQn = 42 00193 #endif /* STM32F10X_MD */ 00194 00195 #ifdef STM32F10X_MD_VL 00196 ADC1_IRQn = 18, 00197 EXTI9_5_IRQn = 23, 00198 TIM1_BRK_TIM15_IRQn = 24, 00199 TIM1_UP_TIM16_IRQn = 25, 00200 TIM1_TRG_COM_TIM17_IRQn = 26, 00201 TIM1_CC_IRQn = 27, 00202 TIM2_IRQn = 28, 00203 TIM3_IRQn = 29, 00204 TIM4_IRQn = 30, 00205 I2C1_EV_IRQn = 31, 00206 I2C1_ER_IRQn = 32, 00207 I2C2_EV_IRQn = 33, 00208 I2C2_ER_IRQn = 34, 00209 SPI1_IRQn = 35, 00210 SPI2_IRQn = 36, 00211 USART1_IRQn = 37, 00212 USART2_IRQn = 38, 00213 USART3_IRQn = 39, 00214 EXTI15_10_IRQn = 40, 00215 RTCAlarm_IRQn = 41, 00216 CEC_IRQn = 42, 00217 TIM6_DAC_IRQn = 54, 00218 TIM7_IRQn = 55 00219 #endif /* STM32F10X_MD_VL */ 00220 00221 #ifdef STM32F10X_HD 00222 ADC1_2_IRQn = 18, 00223 USB_HP_CAN1_TX_IRQn = 19, 00224 USB_LP_CAN1_RX0_IRQn = 20, 00225 CAN1_RX1_IRQn = 21, 00226 CAN1_SCE_IRQn = 22, 00227 EXTI9_5_IRQn = 23, 00228 TIM1_BRK_IRQn = 24, 00229 TIM1_UP_IRQn = 25, 00230 TIM1_TRG_COM_IRQn = 26, 00231 TIM1_CC_IRQn = 27, 00232 TIM2_IRQn = 28, 00233 TIM3_IRQn = 29, 00234 TIM4_IRQn = 30, 00235 I2C1_EV_IRQn = 31, 00236 I2C1_ER_IRQn = 32, 00237 I2C2_EV_IRQn = 33, 00238 I2C2_ER_IRQn = 34, 00239 SPI1_IRQn = 35, 00240 SPI2_IRQn = 36, 00241 USART1_IRQn = 37, 00242 USART2_IRQn = 38, 00243 USART3_IRQn = 39, 00244 EXTI15_10_IRQn = 40, 00245 RTCAlarm_IRQn = 41, 00246 USBWakeUp_IRQn = 42, 00247 TIM8_BRK_IRQn = 43, 00248 TIM8_UP_IRQn = 44, 00249 TIM8_TRG_COM_IRQn = 45, 00250 TIM8_CC_IRQn = 46, 00251 ADC3_IRQn = 47, 00252 FSMC_IRQn = 48, 00253 SDIO_IRQn = 49, 00254 TIM5_IRQn = 50, 00255 SPI3_IRQn = 51, 00256 UART4_IRQn = 52, 00257 UART5_IRQn = 53, 00258 TIM6_IRQn = 54, 00259 TIM7_IRQn = 55, 00260 DMA2_Channel1_IRQn = 56, 00261 DMA2_Channel2_IRQn = 57, 00262 DMA2_Channel3_IRQn = 58, 00263 DMA2_Channel4_5_IRQn = 59 00264 #endif /* STM32F10X_HD */ 00265 00266 #ifdef STM32F10X_XL 00267 ADC1_2_IRQn = 18, 00268 USB_HP_CAN1_TX_IRQn = 19, 00269 USB_LP_CAN1_RX0_IRQn = 20, 00270 CAN1_RX1_IRQn = 21, 00271 CAN1_SCE_IRQn = 22, 00272 EXTI9_5_IRQn = 23, 00273 TIM1_BRK_TIM9_IRQn = 24, 00274 TIM1_UP_TIM10_IRQn = 25, 00275 TIM1_TRG_COM_TIM11_IRQn = 26, 00276 TIM1_CC_IRQn = 27, 00277 TIM2_IRQn = 28, 00278 TIM3_IRQn = 29, 00279 TIM4_IRQn = 30, 00280 I2C1_EV_IRQn = 31, 00281 I2C1_ER_IRQn = 32, 00282 I2C2_EV_IRQn = 33, 00283 I2C2_ER_IRQn = 34, 00284 SPI1_IRQn = 35, 00285 SPI2_IRQn = 36, 00286 USART1_IRQn = 37, 00287 USART2_IRQn = 38, 00288 USART3_IRQn = 39, 00289 EXTI15_10_IRQn = 40, 00290 RTCAlarm_IRQn = 41, 00291 USBWakeUp_IRQn = 42, 00292 TIM8_BRK_TIM12_IRQn = 43, 00293 TIM8_UP_TIM13_IRQn = 44, 00294 TIM8_TRG_COM_TIM14_IRQn = 45, 00295 TIM8_CC_IRQn = 46, 00296 ADC3_IRQn = 47, 00297 FSMC_IRQn = 48, 00298 SDIO_IRQn = 49, 00299 TIM5_IRQn = 50, 00300 SPI3_IRQn = 51, 00301 UART4_IRQn = 52, 00302 UART5_IRQn = 53, 00303 TIM6_IRQn = 54, 00304 TIM7_IRQn = 55, 00305 DMA2_Channel1_IRQn = 56, 00306 DMA2_Channel2_IRQn = 57, 00307 DMA2_Channel3_IRQn = 58, 00308 DMA2_Channel4_5_IRQn = 59 00309 #endif /* STM32F10X_XL */ 00310 00311 #ifdef STM32F10X_CL 00312 ADC1_2_IRQn = 18, 00313 CAN1_TX_IRQn = 19, 00314 CAN1_RX0_IRQn = 20, 00315 CAN1_RX1_IRQn = 21, 00316 CAN1_SCE_IRQn = 22, 00317 EXTI9_5_IRQn = 23, 00318 TIM1_BRK_IRQn = 24, 00319 TIM1_UP_IRQn = 25, 00320 TIM1_TRG_COM_IRQn = 26, 00321 TIM1_CC_IRQn = 27, 00322 TIM2_IRQn = 28, 00323 TIM3_IRQn = 29, 00324 TIM4_IRQn = 30, 00325 I2C1_EV_IRQn = 31, 00326 I2C1_ER_IRQn = 32, 00327 I2C2_EV_IRQn = 33, 00328 I2C2_ER_IRQn = 34, 00329 SPI1_IRQn = 35, 00330 SPI2_IRQn = 36, 00331 USART1_IRQn = 37, 00332 USART2_IRQn = 38, 00333 USART3_IRQn = 39, 00334 EXTI15_10_IRQn = 40, 00335 RTCAlarm_IRQn = 41, 00336 OTG_FS_WKUP_IRQn = 42, 00337 TIM5_IRQn = 50, 00338 SPI3_IRQn = 51, 00339 UART4_IRQn = 52, 00340 UART5_IRQn = 53, 00341 TIM6_IRQn = 54, 00342 TIM7_IRQn = 55, 00343 DMA2_Channel1_IRQn = 56, 00344 DMA2_Channel2_IRQn = 57, 00345 DMA2_Channel3_IRQn = 58, 00346 DMA2_Channel4_IRQn = 59, 00347 DMA2_Channel5_IRQn = 60, 00348 ETH_IRQn = 61, 00349 ETH_WKUP_IRQn = 62, 00350 CAN2_TX_IRQn = 63, 00351 CAN2_RX0_IRQn = 64, 00352 CAN2_RX1_IRQn = 65, 00353 CAN2_SCE_IRQn = 66, 00354 OTG_FS_IRQn = 67 00355 #endif /* STM32F10X_CL */ 00356 } IRQn_Type; 00357 00362 #include <arch/cm3/core_cm3.h> 00363 #include <arch/cm3/stm/system_stm32f10x.h> 00364 #include <stdint.h> 00365 00371 typedef int32_t s32; 00372 typedef int16_t s16; 00373 typedef int8_t s8; 00374 00375 typedef const int32_t sc32; 00376 typedef const int16_t sc16; 00377 typedef const int8_t sc8; 00379 typedef __IO int32_t vs32; 00380 typedef __IO int16_t vs16; 00381 typedef __IO int8_t vs8; 00382 00383 typedef __I int32_t vsc32; 00384 typedef __I int16_t vsc16; 00385 typedef __I int8_t vsc8; 00387 typedef uint32_t u32; 00388 typedef uint16_t u16; 00389 typedef uint8_t u8; 00390 00391 typedef const uint32_t uc32; 00392 typedef const uint16_t uc16; 00393 typedef const uint8_t uc8; 00395 typedef __IO uint32_t vu32; 00396 typedef __IO uint16_t vu16; 00397 typedef __IO uint8_t vu8; 00398 00399 typedef __I uint32_t vuc32; 00400 typedef __I uint16_t vuc16; 00401 typedef __I uint8_t vuc8; 00404 #ifndef __cplusplus 00405 typedef enum {FALSE = 0, TRUE = !FALSE} bool; 00406 #endif 00407 00408 typedef enum { 00409 RESET = 0, 00410 SET = !RESET 00411 } FlagStatus, ITStatus; 00412 00413 typedef enum { 00414 DISABLE = 0, 00415 ENABLE = !DISABLE 00416 } FunctionalState; 00417 00418 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) 00419 00420 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; 00433 typedef struct 00434 { 00435 __IO uint32_t SR; 00436 __IO uint32_t CR1; 00437 __IO uint32_t CR2; 00438 __IO uint32_t SMPR1; 00439 __IO uint32_t SMPR2; 00440 __IO uint32_t JOFR1; 00441 __IO uint32_t JOFR2; 00442 __IO uint32_t JOFR3; 00443 __IO uint32_t JOFR4; 00444 __IO uint32_t HTR; 00445 __IO uint32_t LTR; 00446 __IO uint32_t SQR1; 00447 __IO uint32_t SQR2; 00448 __IO uint32_t SQR3; 00449 __IO uint32_t JSQR; 00450 __IO uint32_t JDR1; 00451 __IO uint32_t JDR2; 00452 __IO uint32_t JDR3; 00453 __IO uint32_t JDR4; 00454 __IO uint32_t DR; 00455 } ADC_TypeDef; 00456 00461 typedef struct 00462 { 00463 uint32_t RESERVED0; 00464 __IO uint16_t DR1; 00465 uint16_t RESERVED1; 00466 __IO uint16_t DR2; 00467 uint16_t RESERVED2; 00468 __IO uint16_t DR3; 00469 uint16_t RESERVED3; 00470 __IO uint16_t DR4; 00471 uint16_t RESERVED4; 00472 __IO uint16_t DR5; 00473 uint16_t RESERVED5; 00474 __IO uint16_t DR6; 00475 uint16_t RESERVED6; 00476 __IO uint16_t DR7; 00477 uint16_t RESERVED7; 00478 __IO uint16_t DR8; 00479 uint16_t RESERVED8; 00480 __IO uint16_t DR9; 00481 uint16_t RESERVED9; 00482 __IO uint16_t DR10; 00483 uint16_t RESERVED10; 00484 __IO uint16_t RTCCR; 00485 uint16_t RESERVED11; 00486 __IO uint16_t CR; 00487 uint16_t RESERVED12; 00488 __IO uint16_t CSR; 00489 uint16_t RESERVED13[5]; 00490 __IO uint16_t DR11; 00491 uint16_t RESERVED14; 00492 __IO uint16_t DR12; 00493 uint16_t RESERVED15; 00494 __IO uint16_t DR13; 00495 uint16_t RESERVED16; 00496 __IO uint16_t DR14; 00497 uint16_t RESERVED17; 00498 __IO uint16_t DR15; 00499 uint16_t RESERVED18; 00500 __IO uint16_t DR16; 00501 uint16_t RESERVED19; 00502 __IO uint16_t DR17; 00503 uint16_t RESERVED20; 00504 __IO uint16_t DR18; 00505 uint16_t RESERVED21; 00506 __IO uint16_t DR19; 00507 uint16_t RESERVED22; 00508 __IO uint16_t DR20; 00509 uint16_t RESERVED23; 00510 __IO uint16_t DR21; 00511 uint16_t RESERVED24; 00512 __IO uint16_t DR22; 00513 uint16_t RESERVED25; 00514 __IO uint16_t DR23; 00515 uint16_t RESERVED26; 00516 __IO uint16_t DR24; 00517 uint16_t RESERVED27; 00518 __IO uint16_t DR25; 00519 uint16_t RESERVED28; 00520 __IO uint16_t DR26; 00521 uint16_t RESERVED29; 00522 __IO uint16_t DR27; 00523 uint16_t RESERVED30; 00524 __IO uint16_t DR28; 00525 uint16_t RESERVED31; 00526 __IO uint16_t DR29; 00527 uint16_t RESERVED32; 00528 __IO uint16_t DR30; 00529 uint16_t RESERVED33; 00530 __IO uint16_t DR31; 00531 uint16_t RESERVED34; 00532 __IO uint16_t DR32; 00533 uint16_t RESERVED35; 00534 __IO uint16_t DR33; 00535 uint16_t RESERVED36; 00536 __IO uint16_t DR34; 00537 uint16_t RESERVED37; 00538 __IO uint16_t DR35; 00539 uint16_t RESERVED38; 00540 __IO uint16_t DR36; 00541 uint16_t RESERVED39; 00542 __IO uint16_t DR37; 00543 uint16_t RESERVED40; 00544 __IO uint16_t DR38; 00545 uint16_t RESERVED41; 00546 __IO uint16_t DR39; 00547 uint16_t RESERVED42; 00548 __IO uint16_t DR40; 00549 uint16_t RESERVED43; 00550 __IO uint16_t DR41; 00551 uint16_t RESERVED44; 00552 __IO uint16_t DR42; 00553 uint16_t RESERVED45; 00554 } BKP_TypeDef; 00555 00560 typedef struct 00561 { 00562 __IO uint32_t TIR; 00563 __IO uint32_t TDTR; 00564 __IO uint32_t TDLR; 00565 __IO uint32_t TDHR; 00566 } CAN_TxMailBox_TypeDef; 00567 00572 typedef struct 00573 { 00574 __IO uint32_t RIR; 00575 __IO uint32_t RDTR; 00576 __IO uint32_t RDLR; 00577 __IO uint32_t RDHR; 00578 } CAN_FIFOMailBox_TypeDef; 00579 00584 typedef struct 00585 { 00586 __IO uint32_t FR1; 00587 __IO uint32_t FR2; 00588 } CAN_FilterRegister_TypeDef; 00589 00594 typedef struct 00595 { 00596 __IO uint32_t MCR; 00597 __IO uint32_t MSR; 00598 __IO uint32_t TSR; 00599 __IO uint32_t RF0R; 00600 __IO uint32_t RF1R; 00601 __IO uint32_t IER; 00602 __IO uint32_t ESR; 00603 __IO uint32_t BTR; 00604 uint32_t RESERVED0[88]; 00605 CAN_TxMailBox_TypeDef sTxMailBox[3]; 00606 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; 00607 uint32_t RESERVED1[12]; 00608 __IO uint32_t FMR; 00609 __IO uint32_t FM1R; 00610 uint32_t RESERVED2; 00611 __IO uint32_t FS1R; 00612 uint32_t RESERVED3; 00613 __IO uint32_t FFA1R; 00614 uint32_t RESERVED4; 00615 __IO uint32_t FA1R; 00616 uint32_t RESERVED5[8]; 00617 #ifndef STM32F10X_CL 00618 CAN_FilterRegister_TypeDef sFilterRegister[14]; 00619 #else 00620 CAN_FilterRegister_TypeDef sFilterRegister[28]; 00621 #endif /* STM32F10X_CL */ 00622 } CAN_TypeDef; 00623 00627 typedef struct 00628 { 00629 __IO uint32_t CFGR; 00630 __IO uint32_t OAR; 00631 __IO uint32_t PRES; 00632 __IO uint32_t ESR; 00633 __IO uint32_t CSR; 00634 __IO uint32_t TXD; 00635 __IO uint32_t RXD; 00636 } CEC_TypeDef; 00637 00642 typedef struct 00643 { 00644 __IO uint32_t DR; 00645 __IO uint8_t IDR; 00646 uint8_t RESERVED0; 00647 uint16_t RESERVED1; 00648 __IO uint32_t CR; 00649 } CRC_TypeDef; 00650 00655 typedef struct 00656 { 00657 __IO uint32_t CR; 00658 __IO uint32_t SWTRIGR; 00659 __IO uint32_t DHR12R1; 00660 __IO uint32_t DHR12L1; 00661 __IO uint32_t DHR8R1; 00662 __IO uint32_t DHR12R2; 00663 __IO uint32_t DHR12L2; 00664 __IO uint32_t DHR8R2; 00665 __IO uint32_t DHR12RD; 00666 __IO uint32_t DHR12LD; 00667 __IO uint32_t DHR8RD; 00668 __IO uint32_t DOR1; 00669 __IO uint32_t DOR2; 00670 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 00671 __IO uint32_t SR; 00672 #endif 00673 } DAC_TypeDef; 00674 00679 typedef struct 00680 { 00681 __IO uint32_t IDCODE; 00682 __IO uint32_t CR; 00683 }DBGMCU_TypeDef; 00684 00689 typedef struct 00690 { 00691 __IO uint32_t CCR; 00692 __IO uint32_t CNDTR; 00693 __IO uint32_t CPAR; 00694 __IO uint32_t CMAR; 00695 } DMA_Channel_TypeDef; 00696 00697 typedef struct 00698 { 00699 __IO uint32_t ISR; 00700 __IO uint32_t IFCR; 00701 } DMA_TypeDef; 00702 00707 typedef struct 00708 { 00709 __IO uint32_t MACCR; 00710 __IO uint32_t MACFFR; 00711 __IO uint32_t MACHTHR; 00712 __IO uint32_t MACHTLR; 00713 __IO uint32_t MACMIIAR; 00714 __IO uint32_t MACMIIDR; 00715 __IO uint32_t MACFCR; 00716 __IO uint32_t MACVLANTR; /* 8 */ 00717 uint32_t RESERVED0[2]; 00718 __IO uint32_t MACRWUFFR; /* 11 */ 00719 __IO uint32_t MACPMTCSR; 00720 uint32_t RESERVED1[2]; 00721 __IO uint32_t MACSR; /* 15 */ 00722 __IO uint32_t MACIMR; 00723 __IO uint32_t MACA0HR; 00724 __IO uint32_t MACA0LR; 00725 __IO uint32_t MACA1HR; 00726 __IO uint32_t MACA1LR; 00727 __IO uint32_t MACA2HR; 00728 __IO uint32_t MACA2LR; 00729 __IO uint32_t MACA3HR; 00730 __IO uint32_t MACA3LR; /* 24 */ 00731 uint32_t RESERVED2[40]; 00732 __IO uint32_t MMCCR; /* 65 */ 00733 __IO uint32_t MMCRIR; 00734 __IO uint32_t MMCTIR; 00735 __IO uint32_t MMCRIMR; 00736 __IO uint32_t MMCTIMR; /* 69 */ 00737 uint32_t RESERVED3[14]; 00738 __IO uint32_t MMCTGFSCCR; /* 84 */ 00739 __IO uint32_t MMCTGFMSCCR; 00740 uint32_t RESERVED4[5]; 00741 __IO uint32_t MMCTGFCR; 00742 uint32_t RESERVED5[10]; 00743 __IO uint32_t MMCRFCECR; 00744 __IO uint32_t MMCRFAECR; 00745 uint32_t RESERVED6[10]; 00746 __IO uint32_t MMCRGUFCR; 00747 uint32_t RESERVED7[334]; 00748 __IO uint32_t PTPTSCR; 00749 __IO uint32_t PTPSSIR; 00750 __IO uint32_t PTPTSHR; 00751 __IO uint32_t PTPTSLR; 00752 __IO uint32_t PTPTSHUR; 00753 __IO uint32_t PTPTSLUR; 00754 __IO uint32_t PTPTSAR; 00755 __IO uint32_t PTPTTHR; 00756 __IO uint32_t PTPTTLR; 00757 uint32_t RESERVED8[567]; 00758 __IO uint32_t DMABMR; 00759 __IO uint32_t DMATPDR; 00760 __IO uint32_t DMARPDR; 00761 __IO uint32_t DMARDLAR; 00762 __IO uint32_t DMATDLAR; 00763 __IO uint32_t DMASR; 00764 __IO uint32_t DMAOMR; 00765 __IO uint32_t DMAIER; 00766 __IO uint32_t DMAMFBOCR; 00767 uint32_t RESERVED9[9]; 00768 __IO uint32_t DMACHTDR; 00769 __IO uint32_t DMACHRDR; 00770 __IO uint32_t DMACHTBAR; 00771 __IO uint32_t DMACHRBAR; 00772 } ETH_TypeDef; 00773 00778 typedef struct 00779 { 00780 __IO uint32_t IMR; 00781 __IO uint32_t EMR; 00782 __IO uint32_t RTSR; 00783 __IO uint32_t FTSR; 00784 __IO uint32_t SWIER; 00785 __IO uint32_t PR; 00786 } EXTI_TypeDef; 00787 00792 typedef struct 00793 { 00794 __IO uint32_t ACR; 00795 __IO uint32_t KEYR; 00796 __IO uint32_t OPTKEYR; 00797 __IO uint32_t SR; 00798 __IO uint32_t CR; 00799 __IO uint32_t AR; 00800 __IO uint32_t RESERVED; 00801 __IO uint32_t OBR; 00802 __IO uint32_t WRPR; 00803 #ifdef STM32F10X_XL 00804 uint32_t RESERVED1[8]; 00805 __IO uint32_t KEYR2; 00806 uint32_t RESERVED2; 00807 __IO uint32_t SR2; 00808 __IO uint32_t CR2; 00809 __IO uint32_t AR2; 00810 #endif /* STM32F10X_XL */ 00811 } FLASH_TypeDef; 00812 00817 typedef struct 00818 { 00819 __IO uint16_t RDP; 00820 __IO uint16_t USER; 00821 __IO uint16_t Data0; 00822 __IO uint16_t Data1; 00823 __IO uint16_t WRP0; 00824 __IO uint16_t WRP1; 00825 __IO uint16_t WRP2; 00826 __IO uint16_t WRP3; 00827 } OB_TypeDef; 00828 00833 typedef struct 00834 { 00835 __IO uint32_t BTCR[8]; 00836 } FSMC_Bank1_TypeDef; 00837 00842 typedef struct 00843 { 00844 __IO uint32_t BWTR[7]; 00845 } FSMC_Bank1E_TypeDef; 00846 00851 typedef struct 00852 { 00853 __IO uint32_t PCR2; 00854 __IO uint32_t SR2; 00855 __IO uint32_t PMEM2; 00856 __IO uint32_t PATT2; 00857 uint32_t RESERVED0; 00858 __IO uint32_t ECCR2; 00859 } FSMC_Bank2_TypeDef; 00860 00865 typedef struct 00866 { 00867 __IO uint32_t PCR3; 00868 __IO uint32_t SR3; 00869 __IO uint32_t PMEM3; 00870 __IO uint32_t PATT3; 00871 uint32_t RESERVED0; 00872 __IO uint32_t ECCR3; 00873 } FSMC_Bank3_TypeDef; 00874 00879 typedef struct 00880 { 00881 __IO uint32_t PCR4; 00882 __IO uint32_t SR4; 00883 __IO uint32_t PMEM4; 00884 __IO uint32_t PATT4; 00885 __IO uint32_t PIO4; 00886 } FSMC_Bank4_TypeDef; 00887 00892 typedef struct 00893 { 00894 __IO uint32_t CRL; 00895 __IO uint32_t CRH; 00896 __IO uint32_t IDR; 00897 __IO uint32_t ODR; 00898 __IO uint32_t BSRR; 00899 __IO uint32_t BRR; 00900 __IO uint32_t LCKR; 00901 } GPIO_TypeDef; 00902 00907 typedef struct 00908 { 00909 __IO uint32_t EVCR; 00910 __IO uint32_t MAPR; 00911 __IO uint32_t EXTICR[4]; 00912 uint32_t RESERVED0; 00913 __IO uint32_t MAPR2; 00914 } AFIO_TypeDef; 00919 typedef struct 00920 { 00921 __IO uint16_t CR1; 00922 uint16_t RESERVED0; 00923 __IO uint16_t CR2; 00924 uint16_t RESERVED1; 00925 __IO uint16_t OAR1; 00926 uint16_t RESERVED2; 00927 __IO uint16_t OAR2; 00928 uint16_t RESERVED3; 00929 __IO uint16_t DR; 00930 uint16_t RESERVED4; 00931 __IO uint16_t SR1; 00932 uint16_t RESERVED5; 00933 __IO uint16_t SR2; 00934 uint16_t RESERVED6; 00935 __IO uint16_t CCR; 00936 uint16_t RESERVED7; 00937 __IO uint16_t TRISE; 00938 uint16_t RESERVED8; 00939 } I2C_TypeDef; 00940 00945 typedef struct 00946 { 00947 __IO uint32_t KR; 00948 __IO uint32_t PR; 00949 __IO uint32_t RLR; 00950 __IO uint32_t SR; 00951 } IWDG_TypeDef; 00952 00957 typedef struct 00958 { 00959 __IO uint32_t CR; 00960 __IO uint32_t CSR; 00961 } PWR_TypeDef; 00962 00967 typedef struct 00968 { 00969 __IO uint32_t CR; 00970 __IO uint32_t CFGR; 00971 __IO uint32_t CIR; 00972 __IO uint32_t APB2RSTR; 00973 __IO uint32_t APB1RSTR; 00974 __IO uint32_t AHBENR; 00975 __IO uint32_t APB2ENR; 00976 __IO uint32_t APB1ENR; 00977 __IO uint32_t BDCR; 00978 __IO uint32_t CSR; 00979 00980 #ifdef STM32F10X_CL 00981 __IO uint32_t AHBRSTR; 00982 __IO uint32_t CFGR2; 00983 #endif /* STM32F10X_CL */ 00984 00985 #if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL 00986 uint32_t RESERVED0; 00987 __IO uint32_t CFGR2; 00988 #endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */ 00989 } RCC_TypeDef; 00990 00995 typedef struct 00996 { 00997 __IO uint16_t CRH; 00998 uint16_t RESERVED0; 00999 __IO uint16_t CRL; 01000 uint16_t RESERVED1; 01001 __IO uint16_t PRLH; 01002 uint16_t RESERVED2; 01003 __IO uint16_t PRLL; 01004 uint16_t RESERVED3; 01005 __IO uint16_t DIVH; 01006 uint16_t RESERVED4; 01007 __IO uint16_t DIVL; 01008 uint16_t RESERVED5; 01009 __IO uint16_t CNTH; 01010 uint16_t RESERVED6; 01011 __IO uint16_t CNTL; 01012 uint16_t RESERVED7; 01013 __IO uint16_t ALRH; 01014 uint16_t RESERVED8; 01015 __IO uint16_t ALRL; 01016 uint16_t RESERVED9; 01017 } RTC_TypeDef; 01018 01023 typedef struct 01024 { 01025 __IO uint32_t POWER; 01026 __IO uint32_t CLKCR; 01027 __IO uint32_t ARG; 01028 __IO uint32_t CMD; 01029 __I uint32_t RESPCMD; 01030 __I uint32_t RESP1; 01031 __I uint32_t RESP2; 01032 __I uint32_t RESP3; 01033 __I uint32_t RESP4; 01034 __IO uint32_t DTIMER; 01035 __IO uint32_t DLEN; 01036 __IO uint32_t DCTRL; 01037 __I uint32_t DCOUNT; 01038 __I uint32_t STA; 01039 __IO uint32_t ICR; 01040 __IO uint32_t MASK; 01041 uint32_t RESERVED0[2]; 01042 __I uint32_t FIFOCNT; 01043 uint32_t RESERVED1[13]; 01044 __IO uint32_t FIFO; 01045 } SDIO_TypeDef; 01046 01051 typedef struct 01052 { 01053 __IO uint16_t CR1; 01054 uint16_t RESERVED0; 01055 __IO uint16_t CR2; 01056 uint16_t RESERVED1; 01057 __IO uint16_t SR; 01058 uint16_t RESERVED2; 01059 __IO uint16_t DR; 01060 uint16_t RESERVED3; 01061 __IO uint16_t CRCPR; 01062 uint16_t RESERVED4; 01063 __IO uint16_t RXCRCR; 01064 uint16_t RESERVED5; 01065 __IO uint16_t TXCRCR; 01066 uint16_t RESERVED6; 01067 __IO uint16_t I2SCFGR; 01068 uint16_t RESERVED7; 01069 __IO uint16_t I2SPR; 01070 uint16_t RESERVED8; 01071 } SPI_TypeDef; 01072 01077 typedef struct 01078 { 01079 __IO uint16_t CR1; 01080 uint16_t RESERVED0; 01081 __IO uint16_t CR2; 01082 uint16_t RESERVED1; 01083 __IO uint16_t SMCR; 01084 uint16_t RESERVED2; 01085 __IO uint16_t DIER; 01086 uint16_t RESERVED3; 01087 __IO uint16_t SR; 01088 uint16_t RESERVED4; 01089 __IO uint16_t EGR; 01090 uint16_t RESERVED5; 01091 __IO uint16_t CCMR1; 01092 uint16_t RESERVED6; 01093 __IO uint16_t CCMR2; 01094 uint16_t RESERVED7; 01095 __IO uint16_t CCER; 01096 uint16_t RESERVED8; 01097 __IO uint16_t CNT; 01098 uint16_t RESERVED9; 01099 __IO uint16_t PSC; 01100 uint16_t RESERVED10; 01101 __IO uint16_t ARR; 01102 uint16_t RESERVED11; 01103 __IO uint16_t RCR; 01104 uint16_t RESERVED12; 01105 __IO uint16_t CCR1; 01106 uint16_t RESERVED13; 01107 __IO uint16_t CCR2; 01108 uint16_t RESERVED14; 01109 __IO uint16_t CCR3; 01110 uint16_t RESERVED15; 01111 __IO uint16_t CCR4; 01112 uint16_t RESERVED16; 01113 __IO uint16_t BDTR; 01114 uint16_t RESERVED17; 01115 __IO uint16_t DCR; 01116 uint16_t RESERVED18; 01117 __IO uint16_t DMAR; 01118 uint16_t RESERVED19; 01119 } TIM_TypeDef; 01120 01125 typedef struct 01126 { 01127 __IO uint16_t SR; 01128 uint16_t RESERVED0; 01129 __IO uint16_t DR; 01130 uint16_t RESERVED1; 01131 __IO uint16_t BRR; 01132 uint16_t RESERVED2; 01133 __IO uint16_t CR1; 01134 uint16_t RESERVED3; 01135 __IO uint16_t CR2; 01136 uint16_t RESERVED4; 01137 __IO uint16_t CR3; 01138 uint16_t RESERVED5; 01139 __IO uint16_t GTPR; 01140 uint16_t RESERVED6; 01141 } USART_TypeDef; 01142 01147 typedef struct 01148 { 01149 __IO uint32_t CR; 01150 __IO uint32_t CFR; 01151 __IO uint32_t SR; 01152 } WWDG_TypeDef; 01153 01158 typedef struct 01159 { 01160 __I uint16_t FLASH_SIZE; 01161 uint16_t RESERVED0; 01162 uint32_t RESERVED1; 01163 __I uint16_t U_ID0; 01164 __I uint16_t U_ID1; 01165 __I uint32_t U_ID2; 01166 __I uint32_t U_ID3; 01167 } ESIG_TypeDef; 01168 01177 #define PERIPH_BB_BASE ((uint32_t)0x42000000) 01178 #define SRAM_BB_BASE ((uint32_t)0x22000000) 01180 #define SRAM_BASE ((uint32_t)0x20000000) 01181 #define PERIPH_BASE ((uint32_t)0x40000000) 01183 #define FSMC_R_BASE ((uint32_t)0xA0000000) 01186 #define APB1PERIPH_BASE PERIPH_BASE 01187 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 01188 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 01189 01190 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 01191 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 01192 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 01193 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 01194 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 01195 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 01196 #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) 01197 #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) 01198 #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) 01199 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 01200 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 01201 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 01202 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 01203 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 01204 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 01205 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 01206 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 01207 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 01208 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 01209 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 01210 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 01211 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) 01212 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) 01213 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 01214 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 01215 #define CEC_BASE (APB1PERIPH_BASE + 0x7800) 01216 01217 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) 01218 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 01219 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) 01220 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) 01221 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) 01222 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) 01223 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) 01224 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) 01225 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) 01226 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 01227 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) 01228 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) 01229 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 01230 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) 01231 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 01232 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) 01233 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) 01234 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) 01235 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) 01236 #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) 01237 #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) 01238 #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) 01239 01240 #define SDIO_BASE (PERIPH_BASE + 0x18000) 01241 01242 #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) 01243 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) 01244 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) 01245 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) 01246 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) 01247 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) 01248 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) 01249 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) 01250 #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) 01251 #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) 01252 #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) 01253 #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) 01254 #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) 01255 #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) 01256 #define RCC_BASE (AHBPERIPH_BASE + 0x1000) 01257 #define CRC_BASE (AHBPERIPH_BASE + 0x3000) 01258 01259 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) 01260 #define OB_BASE ((uint32_t)0x1FFFF800) 01262 #define DEV_ESIG_BASE ((uint32_t)0x1FFFF7E0) 01263 #define ESIG ((ESIG_TypeDef *) DEV_ESIG_BASE) 01264 01265 #define ETH_BASE (AHBPERIPH_BASE + 0x8000) 01266 #define ETH_MAC_BASE (ETH_BASE) 01267 #define ETH_MMC_BASE (ETH_BASE + 0x0100) 01268 #define ETH_PTP_BASE (ETH_BASE + 0x0700) 01269 #define ETH_DMA_BASE (ETH_BASE + 0x1000) 01270 01271 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) 01272 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) 01273 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) 01274 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) 01275 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) 01277 #define DBGMCU_BASE ((uint32_t)0xE0042000) 01287 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 01288 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 01289 #define TIM4 ((TIM_TypeDef *) TIM4_BASE) 01290 #define TIM5 ((TIM_TypeDef *) TIM5_BASE) 01291 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 01292 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 01293 #define TIM12 ((TIM_TypeDef *) TIM12_BASE) 01294 #define TIM13 ((TIM_TypeDef *) TIM13_BASE) 01295 #define TIM14 ((TIM_TypeDef *) TIM14_BASE) 01296 #define RTC ((RTC_TypeDef *) RTC_BASE) 01297 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 01298 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 01299 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 01300 #define SPI3 ((SPI_TypeDef *) SPI3_BASE) 01301 #define USART2 ((USART_TypeDef *) USART2_BASE) 01302 #define USART3 ((USART_TypeDef *) USART3_BASE) 01303 #define UART4 ((USART_TypeDef *) UART4_BASE) 01304 #define UART5 ((USART_TypeDef *) UART5_BASE) 01305 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 01306 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 01307 #define CAN1 ((CAN_TypeDef *) CAN1_BASE) 01308 #define CAN2 ((CAN_TypeDef *) CAN2_BASE) 01309 #define BKP ((BKP_TypeDef *) BKP_BASE) 01310 #define PWR ((PWR_TypeDef *) PWR_BASE) 01311 #define DAC ((DAC_TypeDef *) DAC_BASE) 01312 #define CEC ((CEC_TypeDef *) CEC_BASE) 01313 #define AFIO ((AFIO_TypeDef *) AFIO_BASE) 01314 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 01315 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 01316 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 01317 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 01318 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 01319 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 01320 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) 01321 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) 01322 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 01323 #define ADC2 ((ADC_TypeDef *) ADC2_BASE) 01324 #define TIM1 ((TIM_TypeDef *) TIM1_BASE) 01325 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 01326 #define TIM8 ((TIM_TypeDef *) TIM8_BASE) 01327 #define USART1 ((USART_TypeDef *) USART1_BASE) 01328 #define ADC3 ((ADC_TypeDef *) ADC3_BASE) 01329 #define TIM15 ((TIM_TypeDef *) TIM15_BASE) 01330 #define TIM16 ((TIM_TypeDef *) TIM16_BASE) 01331 #define TIM17 ((TIM_TypeDef *) TIM17_BASE) 01332 #define TIM9 ((TIM_TypeDef *) TIM9_BASE) 01333 #define TIM10 ((TIM_TypeDef *) TIM10_BASE) 01334 #define TIM11 ((TIM_TypeDef *) TIM11_BASE) 01335 #define SDIO ((SDIO_TypeDef *) SDIO_BASE) 01336 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 01337 #define DMA2 ((DMA_TypeDef *) DMA2_BASE) 01338 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 01339 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 01340 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 01341 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 01342 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 01343 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 01344 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 01345 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) 01346 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) 01347 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) 01348 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) 01349 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) 01350 #define RCC ((RCC_TypeDef *) RCC_BASE) 01351 #define CRC ((CRC_TypeDef *) CRC_BASE) 01352 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 01353 #define OB ((OB_TypeDef *) OB_BASE) 01354 #define ETH ((ETH_TypeDef *) ETH_BASE) 01355 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) 01356 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) 01357 #define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) 01358 #define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE) 01359 #define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE) 01360 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 01361 01374 /******************************************************************************/ 01375 /* Peripheral Registers_Bits_Definition */ 01376 /******************************************************************************/ 01377 01378 /******************************************************************************/ 01379 /* */ 01380 /* CRC calculation unit */ 01381 /* */ 01382 /******************************************************************************/ 01383 01384 /******************* Bit definition for CRC_DR register *********************/ 01385 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) 01388 /******************* Bit definition for CRC_IDR register ********************/ 01389 #define CRC_IDR_IDR ((uint8_t)0xFF) 01392 /******************** Bit definition for CRC_CR register ********************/ 01393 #define CRC_CR_RESET ((uint8_t)0x01) 01395 /******************************************************************************/ 01396 /* */ 01397 /* Power Control */ 01398 /* */ 01399 /******************************************************************************/ 01400 01401 /******************** Bit definition for PWR_CR register ********************/ 01402 #define PWR_CR_LPDS ((uint16_t)0x0001) 01403 #define PWR_CR_PDDS ((uint16_t)0x0002) 01404 #define PWR_CR_CWUF ((uint16_t)0x0004) 01405 #define PWR_CR_CSBF ((uint16_t)0x0008) 01406 #define PWR_CR_PVDE ((uint16_t)0x0010) 01408 #define PWR_CR_PLS ((uint16_t)0x00E0) 01409 #define PWR_CR_PLS_0 ((uint16_t)0x0020) 01410 #define PWR_CR_PLS_1 ((uint16_t)0x0040) 01411 #define PWR_CR_PLS_2 ((uint16_t)0x0080) 01414 #define PWR_CR_PLS_2V2 ((uint16_t)0x0000) 01415 #define PWR_CR_PLS_2V3 ((uint16_t)0x0020) 01416 #define PWR_CR_PLS_2V4 ((uint16_t)0x0040) 01417 #define PWR_CR_PLS_2V5 ((uint16_t)0x0060) 01418 #define PWR_CR_PLS_2V6 ((uint16_t)0x0080) 01419 #define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) 01420 #define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) 01421 #define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) 01423 #define PWR_CR_DBP ((uint16_t)0x0100) 01426 /******************* Bit definition for PWR_CSR register ********************/ 01427 #define PWR_CSR_WUF ((uint16_t)0x0001) 01428 #define PWR_CSR_SBF ((uint16_t)0x0002) 01429 #define PWR_CSR_PVDO ((uint16_t)0x0004) 01430 #define PWR_CSR_EWUP ((uint16_t)0x0100) 01432 /******************************************************************************/ 01433 /* */ 01434 /* Backup registers */ 01435 /* */ 01436 /******************************************************************************/ 01437 01438 /******************* Bit definition for BKP_DR1 register ********************/ 01439 #define BKP_DR1_D ((uint16_t)0xFFFF) 01441 /******************* Bit definition for BKP_DR2 register ********************/ 01442 #define BKP_DR2_D ((uint16_t)0xFFFF) 01444 /******************* Bit definition for BKP_DR3 register ********************/ 01445 #define BKP_DR3_D ((uint16_t)0xFFFF) 01447 /******************* Bit definition for BKP_DR4 register ********************/ 01448 #define BKP_DR4_D ((uint16_t)0xFFFF) 01450 /******************* Bit definition for BKP_DR5 register ********************/ 01451 #define BKP_DR5_D ((uint16_t)0xFFFF) 01453 /******************* Bit definition for BKP_DR6 register ********************/ 01454 #define BKP_DR6_D ((uint16_t)0xFFFF) 01456 /******************* Bit definition for BKP_DR7 register ********************/ 01457 #define BKP_DR7_D ((uint16_t)0xFFFF) 01459 /******************* Bit definition for BKP_DR8 register ********************/ 01460 #define BKP_DR8_D ((uint16_t)0xFFFF) 01462 /******************* Bit definition for BKP_DR9 register ********************/ 01463 #define BKP_DR9_D ((uint16_t)0xFFFF) 01465 /******************* Bit definition for BKP_DR10 register *******************/ 01466 #define BKP_DR10_D ((uint16_t)0xFFFF) 01468 /******************* Bit definition for BKP_DR11 register *******************/ 01469 #define BKP_DR11_D ((uint16_t)0xFFFF) 01471 /******************* Bit definition for BKP_DR12 register *******************/ 01472 #define BKP_DR12_D ((uint16_t)0xFFFF) 01474 /******************* Bit definition for BKP_DR13 register *******************/ 01475 #define BKP_DR13_D ((uint16_t)0xFFFF) 01477 /******************* Bit definition for BKP_DR14 register *******************/ 01478 #define BKP_DR14_D ((uint16_t)0xFFFF) 01480 /******************* Bit definition for BKP_DR15 register *******************/ 01481 #define BKP_DR15_D ((uint16_t)0xFFFF) 01483 /******************* Bit definition for BKP_DR16 register *******************/ 01484 #define BKP_DR16_D ((uint16_t)0xFFFF) 01486 /******************* Bit definition for BKP_DR17 register *******************/ 01487 #define BKP_DR17_D ((uint16_t)0xFFFF) 01489 /****************** Bit definition for BKP_DR18 register ********************/ 01490 #define BKP_DR18_D ((uint16_t)0xFFFF) 01492 /******************* Bit definition for BKP_DR19 register *******************/ 01493 #define BKP_DR19_D ((uint16_t)0xFFFF) 01495 /******************* Bit definition for BKP_DR20 register *******************/ 01496 #define BKP_DR20_D ((uint16_t)0xFFFF) 01498 /******************* Bit definition for BKP_DR21 register *******************/ 01499 #define BKP_DR21_D ((uint16_t)0xFFFF) 01501 /******************* Bit definition for BKP_DR22 register *******************/ 01502 #define BKP_DR22_D ((uint16_t)0xFFFF) 01504 /******************* Bit definition for BKP_DR23 register *******************/ 01505 #define BKP_DR23_D ((uint16_t)0xFFFF) 01507 /******************* Bit definition for BKP_DR24 register *******************/ 01508 #define BKP_DR24_D ((uint16_t)0xFFFF) 01510 /******************* Bit definition for BKP_DR25 register *******************/ 01511 #define BKP_DR25_D ((uint16_t)0xFFFF) 01513 /******************* Bit definition for BKP_DR26 register *******************/ 01514 #define BKP_DR26_D ((uint16_t)0xFFFF) 01516 /******************* Bit definition for BKP_DR27 register *******************/ 01517 #define BKP_DR27_D ((uint16_t)0xFFFF) 01519 /******************* Bit definition for BKP_DR28 register *******************/ 01520 #define BKP_DR28_D ((uint16_t)0xFFFF) 01522 /******************* Bit definition for BKP_DR29 register *******************/ 01523 #define BKP_DR29_D ((uint16_t)0xFFFF) 01525 /******************* Bit definition for BKP_DR30 register *******************/ 01526 #define BKP_DR30_D ((uint16_t)0xFFFF) 01528 /******************* Bit definition for BKP_DR31 register *******************/ 01529 #define BKP_DR31_D ((uint16_t)0xFFFF) 01531 /******************* Bit definition for BKP_DR32 register *******************/ 01532 #define BKP_DR32_D ((uint16_t)0xFFFF) 01534 /******************* Bit definition for BKP_DR33 register *******************/ 01535 #define BKP_DR33_D ((uint16_t)0xFFFF) 01537 /******************* Bit definition for BKP_DR34 register *******************/ 01538 #define BKP_DR34_D ((uint16_t)0xFFFF) 01540 /******************* Bit definition for BKP_DR35 register *******************/ 01541 #define BKP_DR35_D ((uint16_t)0xFFFF) 01543 /******************* Bit definition for BKP_DR36 register *******************/ 01544 #define BKP_DR36_D ((uint16_t)0xFFFF) 01546 /******************* Bit definition for BKP_DR37 register *******************/ 01547 #define BKP_DR37_D ((uint16_t)0xFFFF) 01549 /******************* Bit definition for BKP_DR38 register *******************/ 01550 #define BKP_DR38_D ((uint16_t)0xFFFF) 01552 /******************* Bit definition for BKP_DR39 register *******************/ 01553 #define BKP_DR39_D ((uint16_t)0xFFFF) 01555 /******************* Bit definition for BKP_DR40 register *******************/ 01556 #define BKP_DR40_D ((uint16_t)0xFFFF) 01558 /******************* Bit definition for BKP_DR41 register *******************/ 01559 #define BKP_DR41_D ((uint16_t)0xFFFF) 01561 /******************* Bit definition for BKP_DR42 register *******************/ 01562 #define BKP_DR42_D ((uint16_t)0xFFFF) 01564 /****************** Bit definition for BKP_RTCCR register *******************/ 01565 #define BKP_RTCCR_CAL ((uint16_t)0x007F) 01566 #define BKP_RTCCR_CCO ((uint16_t)0x0080) 01567 #define BKP_RTCCR_ASOE ((uint16_t)0x0100) 01568 #define BKP_RTCCR_ASOS ((uint16_t)0x0200) 01570 /******************** Bit definition for BKP_CR register ********************/ 01571 #define BKP_CR_TPE ((uint8_t)0x01) 01572 #define BKP_CR_TPAL ((uint8_t)0x02) 01574 /******************* Bit definition for BKP_CSR register ********************/ 01575 #define BKP_CSR_CTE ((uint16_t)0x0001) 01576 #define BKP_CSR_CTI ((uint16_t)0x0002) 01577 #define BKP_CSR_TPIE ((uint16_t)0x0004) 01578 #define BKP_CSR_TEF ((uint16_t)0x0100) 01579 #define BKP_CSR_TIF ((uint16_t)0x0200) 01581 /******************************************************************************/ 01582 /* */ 01583 /* Reset and Clock Control */ 01584 /* */ 01585 /******************************************************************************/ 01586 01587 /******************** Bit definition for RCC_CR register ********************/ 01588 #define RCC_CR_HSION ((uint32_t)0x00000001) 01589 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) 01590 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) 01591 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) 01592 #define RCC_CR_HSEON ((uint32_t)0x00010000) 01593 #define RCC_CR_HSERDY ((uint32_t)0x00020000) 01594 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) 01595 #define RCC_CR_CSSON ((uint32_t)0x00080000) 01596 #define RCC_CR_PLLON ((uint32_t)0x01000000) 01597 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) 01599 #ifdef STM32F10X_CL 01600 #define RCC_CR_PLL2ON ((uint32_t)0x04000000) 01601 #define RCC_CR_PLL2RDY ((uint32_t)0x08000000) 01602 #define RCC_CR_PLL3ON ((uint32_t)0x10000000) 01603 #define RCC_CR_PLL3RDY ((uint32_t)0x20000000) 01604 #endif /* STM32F10X_CL */ 01605 01606 /******************* Bit definition for RCC_CFGR register *******************/ 01608 #define RCC_CFGR_SW ((uint32_t)0x00000003) 01609 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) 01610 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) 01612 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) 01613 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) 01614 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) 01617 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) 01618 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) 01619 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) 01621 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) 01622 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) 01623 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) 01626 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) 01627 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) 01628 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) 01629 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) 01630 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) 01632 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) 01633 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) 01634 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) 01635 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) 01636 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) 01637 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) 01638 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) 01639 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) 01640 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) 01643 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) 01644 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) 01645 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) 01646 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) 01648 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) 01649 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) 01650 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) 01651 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) 01652 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) 01655 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) 01656 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) 01657 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) 01658 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) 01660 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) 01661 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) 01662 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) 01663 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) 01664 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) 01667 #define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) 01668 #define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) 01669 #define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) 01671 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) 01672 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) 01673 #define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) 01674 #define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) 01676 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) 01678 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) 01681 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) 01682 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) 01683 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) 01684 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) 01685 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) 01687 #ifdef STM32F10X_CL 01688 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01689 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) 01691 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) 01692 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) 01694 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01695 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01696 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01697 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01698 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01699 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01700 #define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) 01702 #define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) 01705 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) 01706 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01707 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01708 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01709 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) 01711 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01712 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01713 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01714 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01715 #define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) 01716 #define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) 01717 #define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) 01718 #define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) 01719 #define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) 01720 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 01721 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01722 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) 01724 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) 01725 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) 01727 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) 01728 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) 01729 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01730 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01731 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01732 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01733 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01734 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01735 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) 01736 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) 01737 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) 01738 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) 01739 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) 01740 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) 01741 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) 01744 #define RCC_CFGR_MCO ((uint32_t)0x07000000) 01745 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01746 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01747 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01749 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01750 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01751 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01752 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01753 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) 01754 #else 01755 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) 01756 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) 01758 #define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) 01759 #define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) 01761 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) 01762 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) 01763 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) 01764 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) 01765 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) 01766 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) 01767 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) 01768 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) 01769 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) 01770 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) 01771 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) 01772 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) 01773 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) 01774 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) 01775 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) 01776 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) 01779 #define RCC_CFGR_MCO ((uint32_t)0x07000000) 01780 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) 01781 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) 01782 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) 01784 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) 01785 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) 01786 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) 01787 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) 01788 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) 01789 #endif /* STM32F10X_CL */ 01790 01792 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) 01793 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) 01794 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) 01795 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) 01796 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) 01797 #define RCC_CIR_CSSF ((uint32_t)0x00000080) 01798 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) 01799 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) 01800 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) 01801 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) 01802 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) 01803 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) 01804 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) 01805 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) 01806 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) 01807 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) 01808 #define RCC_CIR_CSSC ((uint32_t)0x00800000) 01810 #ifdef STM32F10X_CL 01811 #define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) 01812 #define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) 01813 #define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) 01814 #define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) 01815 #define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) 01816 #define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) 01817 #endif /* STM32F10X_CL */ 01818 01819 /***************** Bit definition for RCC_APB2RSTR register *****************/ 01820 #define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) 01821 #define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) 01822 #define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) 01823 #define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) 01824 #define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) 01825 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) 01827 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) 01828 #define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) 01829 #endif 01830 01831 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) 01832 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) 01833 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) 01835 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 01836 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) 01837 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) 01838 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) 01839 #endif 01840 01841 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01842 #define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) 01843 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01844 01845 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 01846 #define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) 01847 #define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) 01848 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) 01849 #define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) 01850 #endif 01851 01852 #ifdef STM32F10X_XL 01853 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) 01854 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) 01855 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) 01856 #endif /* STM32F10X_XL */ 01857 01858 /***************** Bit definition for RCC_APB1RSTR register *****************/ 01859 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) 01860 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) 01861 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) 01862 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) 01863 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) 01865 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) 01866 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) 01867 #endif 01868 01869 #define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) 01870 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) 01872 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01873 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) 01874 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) 01875 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) 01876 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) 01877 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01878 01879 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL) 01880 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) 01881 #endif 01882 01883 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) 01884 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) 01885 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 01886 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 01887 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) 01888 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) 01889 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) 01890 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 01891 #endif 01892 01893 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 01894 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) 01895 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) 01896 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) 01897 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) 01898 #endif 01899 01900 #ifdef STM32F10X_CL 01901 #define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) 01902 #endif /* STM32F10X_CL */ 01903 01904 #ifdef STM32F10X_XL 01905 #define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) 01906 #define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) 01907 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) 01908 #endif /* STM32F10X_XL */ 01909 01910 /****************** Bit definition for RCC_AHBENR register ******************/ 01911 #define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) 01912 #define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) 01913 #define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) 01914 #define RCC_AHBENR_CRCEN ((uint16_t)0x0040) 01916 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL) 01917 #define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) 01918 #endif 01919 01920 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 01921 #define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) 01922 #define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) 01923 #endif 01924 01925 #ifdef STM32F10X_CL 01926 #define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) 01927 #define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) 01928 #define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) 01929 #define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) 01930 #endif /* STM32F10X_CL */ 01931 01932 /****************** Bit definition for RCC_APB2ENR register *****************/ 01933 #define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) 01934 #define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) 01935 #define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) 01936 #define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) 01937 #define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) 01938 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) 01940 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) 01941 #define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) 01942 #endif 01943 01944 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) 01945 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) 01946 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) 01948 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 01949 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) 01950 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) 01951 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) 01952 #endif 01953 01954 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01955 #define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) 01956 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01957 01958 #if defined (STM32F10X_HD) || defined (STM32F10X_XL) 01959 #define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) 01960 #define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) 01961 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) 01962 #define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) 01963 #endif 01964 01965 #ifdef STM32F10X_XL 01966 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) 01967 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) 01968 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) 01969 #endif 01970 01971 /***************** Bit definition for RCC_APB1ENR register ******************/ 01972 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) 01973 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) 01974 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) 01975 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) 01976 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) 01978 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) 01979 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) 01980 #endif 01981 01982 #define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) 01983 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) 01985 #if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) 01986 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) 01987 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) 01988 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) 01989 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) 01990 #endif /* STM32F10X_LD && STM32F10X_LD_VL */ 01991 01992 #if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) 01993 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) 01994 #endif 01995 01996 #if defined (STM32F10X_HD) || defined (STM32F10X_CL) 01997 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) 01998 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 01999 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 02000 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) 02001 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) 02002 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) 02003 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 02004 #endif 02005 02006 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 02007 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) 02008 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) 02009 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) 02010 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) 02011 #endif 02012 02013 #ifdef STM32F10X_CL 02014 #define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) 02015 #endif /* STM32F10X_CL */ 02016 02017 #ifdef STM32F10X_XL 02018 #define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) 02019 #define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) 02020 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) 02021 #endif /* STM32F10X_XL */ 02022 02023 /******************* Bit definition for RCC_BDCR register *******************/ 02024 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) 02025 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) 02026 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) 02028 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) 02029 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) 02030 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) 02033 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) 02034 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) 02035 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) 02036 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) 02038 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) 02039 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) 02041 /******************* Bit definition for RCC_CSR register ********************/ 02042 #define RCC_CSR_LSION ((uint32_t)0x00000001) 02043 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) 02044 #define RCC_CSR_RMVF ((uint32_t)0x01000000) 02045 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) 02046 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) 02047 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) 02048 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) 02049 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) 02050 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) 02052 #ifdef STM32F10X_CL 02053 /******************* Bit definition for RCC_AHBRSTR register ****************/ 02054 #define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) 02055 #define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) 02057 /******************* Bit definition for RCC_CFGR2 register ******************/ 02058 02059 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) 02060 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) 02061 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) 02062 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) 02063 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) 02065 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) 02066 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) 02067 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) 02068 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) 02069 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) 02070 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) 02071 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) 02072 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) 02073 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) 02074 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) 02075 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) 02076 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) 02077 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) 02078 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) 02079 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) 02080 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) 02083 #define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) 02084 #define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) 02085 #define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) 02086 #define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) 02087 #define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) 02089 #define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) 02090 #define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) 02091 #define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) 02092 #define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) 02093 #define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) 02094 #define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) 02095 #define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) 02096 #define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) 02097 #define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) 02098 #define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) 02099 #define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) 02100 #define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) 02101 #define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) 02102 #define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) 02103 #define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) 02104 #define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) 02107 #define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) 02108 #define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) 02109 #define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) 02110 #define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) 02111 #define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) 02113 #define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) 02114 #define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) 02115 #define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) 02116 #define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) 02117 #define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) 02118 #define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) 02119 #define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) 02120 #define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) 02121 #define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) 02124 #define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) 02125 #define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) 02126 #define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) 02127 #define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) 02128 #define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) 02130 #define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) 02131 #define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) 02132 #define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) 02133 #define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) 02134 #define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) 02135 #define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) 02136 #define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) 02137 #define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) 02138 #define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) 02140 #define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) 02141 #define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) 02142 #define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) 02143 #define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) 02144 #define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) 02145 #endif /* STM32F10X_CL */ 02146 02147 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 02148 /******************* Bit definition for RCC_CFGR2 register ******************/ 02150 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) 02151 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) 02152 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) 02153 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) 02154 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) 02156 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) 02157 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) 02158 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) 02159 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) 02160 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) 02161 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) 02162 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) 02163 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) 02164 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) 02165 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) 02166 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) 02167 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) 02168 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) 02169 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) 02170 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) 02171 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) 02172 #endif 02173 02174 /******************************************************************************/ 02175 /* */ 02176 /* General Purpose and Alternate Function I/O */ 02177 /* */ 02178 /******************************************************************************/ 02179 02180 /******************* Bit definition for GPIO_CRL register *******************/ 02181 #define GPIO_CRL_MODE ((uint32_t)0x33333333) 02183 #define GPIO_CRL_MODE0 ((uint32_t)0x00000003) 02184 #define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) 02185 #define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) 02187 #define GPIO_CRL_MODE1 ((uint32_t)0x00000030) 02188 #define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) 02189 #define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) 02191 #define GPIO_CRL_MODE2 ((uint32_t)0x00000300) 02192 #define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) 02193 #define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) 02195 #define GPIO_CRL_MODE3 ((uint32_t)0x00003000) 02196 #define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) 02197 #define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) 02199 #define GPIO_CRL_MODE4 ((uint32_t)0x00030000) 02200 #define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) 02201 #define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) 02203 #define GPIO_CRL_MODE5 ((uint32_t)0x00300000) 02204 #define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) 02205 #define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) 02207 #define GPIO_CRL_MODE6 ((uint32_t)0x03000000) 02208 #define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) 02209 #define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) 02211 #define GPIO_CRL_MODE7 ((uint32_t)0x30000000) 02212 #define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) 02213 #define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) 02215 #define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) 02217 #define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) 02218 #define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) 02219 #define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) 02221 #define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) 02222 #define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) 02223 #define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) 02225 #define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) 02226 #define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) 02227 #define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) 02229 #define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) 02230 #define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) 02231 #define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) 02233 #define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) 02234 #define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) 02235 #define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) 02237 #define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) 02238 #define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) 02239 #define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) 02241 #define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) 02242 #define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) 02243 #define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) 02245 #define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) 02246 #define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) 02247 #define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) 02249 /******************* Bit definition for GPIO_CRH register *******************/ 02250 #define GPIO_CRH_MODE ((uint32_t)0x33333333) 02252 #define GPIO_CRH_MODE8 ((uint32_t)0x00000003) 02253 #define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) 02254 #define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) 02256 #define GPIO_CRH_MODE9 ((uint32_t)0x00000030) 02257 #define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) 02258 #define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) 02260 #define GPIO_CRH_MODE10 ((uint32_t)0x00000300) 02261 #define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) 02262 #define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) 02264 #define GPIO_CRH_MODE11 ((uint32_t)0x00003000) 02265 #define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) 02266 #define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) 02268 #define GPIO_CRH_MODE12 ((uint32_t)0x00030000) 02269 #define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) 02270 #define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) 02272 #define GPIO_CRH_MODE13 ((uint32_t)0x00300000) 02273 #define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) 02274 #define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) 02276 #define GPIO_CRH_MODE14 ((uint32_t)0x03000000) 02277 #define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) 02278 #define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) 02280 #define GPIO_CRH_MODE15 ((uint32_t)0x30000000) 02281 #define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) 02282 #define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) 02284 #define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) 02286 #define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) 02287 #define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) 02288 #define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) 02290 #define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) 02291 #define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) 02292 #define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) 02294 #define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) 02295 #define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) 02296 #define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) 02298 #define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) 02299 #define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) 02300 #define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) 02302 #define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) 02303 #define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) 02304 #define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) 02306 #define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) 02307 #define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) 02308 #define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) 02310 #define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) 02311 #define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) 02312 #define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) 02314 #define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) 02315 #define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) 02316 #define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) 02319 #define GPIO_IDR_IDR0 ((uint16_t)0x0001) 02320 #define GPIO_IDR_IDR1 ((uint16_t)0x0002) 02321 #define GPIO_IDR_IDR2 ((uint16_t)0x0004) 02322 #define GPIO_IDR_IDR3 ((uint16_t)0x0008) 02323 #define GPIO_IDR_IDR4 ((uint16_t)0x0010) 02324 #define GPIO_IDR_IDR5 ((uint16_t)0x0020) 02325 #define GPIO_IDR_IDR6 ((uint16_t)0x0040) 02326 #define GPIO_IDR_IDR7 ((uint16_t)0x0080) 02327 #define GPIO_IDR_IDR8 ((uint16_t)0x0100) 02328 #define GPIO_IDR_IDR9 ((uint16_t)0x0200) 02329 #define GPIO_IDR_IDR10 ((uint16_t)0x0400) 02330 #define GPIO_IDR_IDR11 ((uint16_t)0x0800) 02331 #define GPIO_IDR_IDR12 ((uint16_t)0x1000) 02332 #define GPIO_IDR_IDR13 ((uint16_t)0x2000) 02333 #define GPIO_IDR_IDR14 ((uint16_t)0x4000) 02334 #define GPIO_IDR_IDR15 ((uint16_t)0x8000) 02336 /******************* Bit definition for GPIO_ODR register *******************/ 02337 #define GPIO_ODR_ODR0 ((uint16_t)0x0001) 02338 #define GPIO_ODR_ODR1 ((uint16_t)0x0002) 02339 #define GPIO_ODR_ODR2 ((uint16_t)0x0004) 02340 #define GPIO_ODR_ODR3 ((uint16_t)0x0008) 02341 #define GPIO_ODR_ODR4 ((uint16_t)0x0010) 02342 #define GPIO_ODR_ODR5 ((uint16_t)0x0020) 02343 #define GPIO_ODR_ODR6 ((uint16_t)0x0040) 02344 #define GPIO_ODR_ODR7 ((uint16_t)0x0080) 02345 #define GPIO_ODR_ODR8 ((uint16_t)0x0100) 02346 #define GPIO_ODR_ODR9 ((uint16_t)0x0200) 02347 #define GPIO_ODR_ODR10 ((uint16_t)0x0400) 02348 #define GPIO_ODR_ODR11 ((uint16_t)0x0800) 02349 #define GPIO_ODR_ODR12 ((uint16_t)0x1000) 02350 #define GPIO_ODR_ODR13 ((uint16_t)0x2000) 02351 #define GPIO_ODR_ODR14 ((uint16_t)0x4000) 02352 #define GPIO_ODR_ODR15 ((uint16_t)0x8000) 02354 /****************** Bit definition for GPIO_BSRR register *******************/ 02355 #define GPIO_BSRR_BS0 ((uint32_t)0x00000001) 02356 #define GPIO_BSRR_BS1 ((uint32_t)0x00000002) 02357 #define GPIO_BSRR_BS2 ((uint32_t)0x00000004) 02358 #define GPIO_BSRR_BS3 ((uint32_t)0x00000008) 02359 #define GPIO_BSRR_BS4 ((uint32_t)0x00000010) 02360 #define GPIO_BSRR_BS5 ((uint32_t)0x00000020) 02361 #define GPIO_BSRR_BS6 ((uint32_t)0x00000040) 02362 #define GPIO_BSRR_BS7 ((uint32_t)0x00000080) 02363 #define GPIO_BSRR_BS8 ((uint32_t)0x00000100) 02364 #define GPIO_BSRR_BS9 ((uint32_t)0x00000200) 02365 #define GPIO_BSRR_BS10 ((uint32_t)0x00000400) 02366 #define GPIO_BSRR_BS11 ((uint32_t)0x00000800) 02367 #define GPIO_BSRR_BS12 ((uint32_t)0x00001000) 02368 #define GPIO_BSRR_BS13 ((uint32_t)0x00002000) 02369 #define GPIO_BSRR_BS14 ((uint32_t)0x00004000) 02370 #define GPIO_BSRR_BS15 ((uint32_t)0x00008000) 02372 #define GPIO_BSRR_BR0 ((uint32_t)0x00010000) 02373 #define GPIO_BSRR_BR1 ((uint32_t)0x00020000) 02374 #define GPIO_BSRR_BR2 ((uint32_t)0x00040000) 02375 #define GPIO_BSRR_BR3 ((uint32_t)0x00080000) 02376 #define GPIO_BSRR_BR4 ((uint32_t)0x00100000) 02377 #define GPIO_BSRR_BR5 ((uint32_t)0x00200000) 02378 #define GPIO_BSRR_BR6 ((uint32_t)0x00400000) 02379 #define GPIO_BSRR_BR7 ((uint32_t)0x00800000) 02380 #define GPIO_BSRR_BR8 ((uint32_t)0x01000000) 02381 #define GPIO_BSRR_BR9 ((uint32_t)0x02000000) 02382 #define GPIO_BSRR_BR10 ((uint32_t)0x04000000) 02383 #define GPIO_BSRR_BR11 ((uint32_t)0x08000000) 02384 #define GPIO_BSRR_BR12 ((uint32_t)0x10000000) 02385 #define GPIO_BSRR_BR13 ((uint32_t)0x20000000) 02386 #define GPIO_BSRR_BR14 ((uint32_t)0x40000000) 02387 #define GPIO_BSRR_BR15 ((uint32_t)0x80000000) 02389 /******************* Bit definition for GPIO_BRR register *******************/ 02390 #define GPIO_BRR_BR0 ((uint16_t)0x0001) 02391 #define GPIO_BRR_BR1 ((uint16_t)0x0002) 02392 #define GPIO_BRR_BR2 ((uint16_t)0x0004) 02393 #define GPIO_BRR_BR3 ((uint16_t)0x0008) 02394 #define GPIO_BRR_BR4 ((uint16_t)0x0010) 02395 #define GPIO_BRR_BR5 ((uint16_t)0x0020) 02396 #define GPIO_BRR_BR6 ((uint16_t)0x0040) 02397 #define GPIO_BRR_BR7 ((uint16_t)0x0080) 02398 #define GPIO_BRR_BR8 ((uint16_t)0x0100) 02399 #define GPIO_BRR_BR9 ((uint16_t)0x0200) 02400 #define GPIO_BRR_BR10 ((uint16_t)0x0400) 02401 #define GPIO_BRR_BR11 ((uint16_t)0x0800) 02402 #define GPIO_BRR_BR12 ((uint16_t)0x1000) 02403 #define GPIO_BRR_BR13 ((uint16_t)0x2000) 02404 #define GPIO_BRR_BR14 ((uint16_t)0x4000) 02405 #define GPIO_BRR_BR15 ((uint16_t)0x8000) 02407 /****************** Bit definition for GPIO_LCKR register *******************/ 02408 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) 02409 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) 02410 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) 02411 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) 02412 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) 02413 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) 02414 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) 02415 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) 02416 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) 02417 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) 02418 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) 02419 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) 02420 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) 02421 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) 02422 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) 02423 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) 02424 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000) 02426 /*----------------------------------------------------------------------------*/ 02427 02428 /****************** Bit definition for AFIO_EVCR register *******************/ 02429 #define AFIO_EVCR_PIN ((uint8_t)0x0F) 02430 #define AFIO_EVCR_PIN_0 ((uint8_t)0x01) 02431 #define AFIO_EVCR_PIN_1 ((uint8_t)0x02) 02432 #define AFIO_EVCR_PIN_2 ((uint8_t)0x04) 02433 #define AFIO_EVCR_PIN_3 ((uint8_t)0x08) 02436 #define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) 02437 #define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) 02438 #define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) 02439 #define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) 02440 #define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) 02441 #define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) 02442 #define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) 02443 #define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) 02444 #define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) 02445 #define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) 02446 #define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) 02447 #define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) 02448 #define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) 02449 #define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) 02450 #define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) 02451 #define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) 02453 #define AFIO_EVCR_PORT ((uint8_t)0x70) 02454 #define AFIO_EVCR_PORT_0 ((uint8_t)0x10) 02455 #define AFIO_EVCR_PORT_1 ((uint8_t)0x20) 02456 #define AFIO_EVCR_PORT_2 ((uint8_t)0x40) 02459 #define AFIO_EVCR_PORT_PA ((uint8_t)0x00) 02460 #define AFIO_EVCR_PORT_PB ((uint8_t)0x10) 02461 #define AFIO_EVCR_PORT_PC ((uint8_t)0x20) 02462 #define AFIO_EVCR_PORT_PD ((uint8_t)0x30) 02463 #define AFIO_EVCR_PORT_PE ((uint8_t)0x40) 02465 #define AFIO_EVCR_EVOE ((uint8_t)0x80) 02467 /****************** Bit definition for AFIO_MAPR register *******************/ 02468 #define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) 02469 #define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) 02470 #define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) 02471 #define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) 02473 #define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) 02474 #define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) 02475 #define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) 02477 /* USART3_REMAP configuration */ 02478 #define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) 02479 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) 02480 #define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) 02482 #define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) 02483 #define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) 02484 #define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) 02487 #define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) 02488 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) 02489 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) 02491 #define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) 02492 #define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) 02493 #define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) 02496 #define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) 02497 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) 02498 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) 02499 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) 02501 #define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) 02502 #define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) 02503 #define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) 02506 #define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) 02507 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) 02508 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) 02510 #define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) 02512 #define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) 02513 #define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) 02514 #define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) 02517 #define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) 02518 #define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) 02519 #define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) 02521 #define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) 02522 #define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) 02523 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) 02524 #define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) 02525 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) 02526 #define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) 02529 #define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) 02530 #define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) 02531 #define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) 02532 #define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) 02534 #define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) 02535 #define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) 02536 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) 02537 #define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) 02539 #ifdef STM32F10X_CL 02540 02541 #define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) 02544 #define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) 02547 #define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) 02550 #define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) 02553 #define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) 02556 #define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x20000000) 02557 #endif 02558 02559 /***************** Bit definition for AFIO_EXTICR1 register *****************/ 02560 #define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) 02561 #define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) 02562 #define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) 02563 #define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) 02566 #define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) 02567 #define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) 02568 #define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) 02569 #define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) 02570 #define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) 02571 #define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) 02572 #define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) 02575 #define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) 02576 #define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) 02577 #define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) 02578 #define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) 02579 #define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) 02580 #define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) 02581 #define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) 02584 #define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) 02585 #define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) 02586 #define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) 02587 #define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) 02588 #define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) 02589 #define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) 02590 #define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) 02593 #define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) 02594 #define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) 02595 #define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) 02596 #define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) 02597 #define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) 02598 #define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) 02599 #define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) 02601 /***************** Bit definition for AFIO_EXTICR2 register *****************/ 02602 #define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) 02603 #define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) 02604 #define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) 02605 #define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) 02608 #define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) 02609 #define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) 02610 #define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) 02611 #define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) 02612 #define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) 02613 #define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) 02614 #define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) 02616 /* EXTI5 configuration */ 02617 #define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) 02618 #define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) 02619 #define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) 02620 #define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) 02621 #define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) 02622 #define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) 02623 #define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) 02626 #define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) 02627 #define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) 02628 #define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) 02629 #define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) 02630 #define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) 02631 #define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) 02632 #define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) 02635 #define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) 02636 #define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) 02637 #define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) 02638 #define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) 02639 #define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) 02640 #define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) 02641 #define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) 02643 /***************** Bit definition for AFIO_EXTICR3 register *****************/ 02644 #define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) 02645 #define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) 02646 #define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) 02647 #define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) 02650 #define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) 02651 #define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) 02652 #define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) 02653 #define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) 02654 #define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) 02655 #define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) 02656 #define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) 02659 #define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) 02660 #define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) 02661 #define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) 02662 #define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) 02663 #define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) 02664 #define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) 02665 #define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) 02668 #define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) 02669 #define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) 02670 #define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) 02671 #define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) 02672 #define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) 02673 #define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) 02674 #define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) 02677 #define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) 02678 #define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) 02679 #define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) 02680 #define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) 02681 #define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) 02682 #define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) 02683 #define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) 02685 /***************** Bit definition for AFIO_EXTICR4 register *****************/ 02686 #define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) 02687 #define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) 02688 #define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) 02689 #define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) 02691 /* EXTI12 configuration */ 02692 #define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) 02693 #define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) 02694 #define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) 02695 #define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) 02696 #define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) 02697 #define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) 02698 #define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) 02700 /* EXTI13 configuration */ 02701 #define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) 02702 #define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) 02703 #define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) 02704 #define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) 02705 #define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) 02706 #define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) 02707 #define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) 02710 #define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) 02711 #define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) 02712 #define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) 02713 #define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) 02714 #define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) 02715 #define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) 02716 #define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) 02719 #define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) 02720 #define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) 02721 #define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) 02722 #define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) 02723 #define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) 02724 #define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) 02725 #define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) 02727 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 02728 /****************** Bit definition for AFIO_MAPR2 register ******************/ 02729 #define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) 02730 #define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) 02731 #define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) 02732 #define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) 02733 #define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) 02734 #endif 02735 02736 #ifdef STM32F10X_XL 02737 /****************** Bit definition for AFIO_MAPR2 register ******************/ 02738 #define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) 02739 #define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) 02740 #define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) 02741 #define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) 02742 #define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) 02743 #define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) 02744 #endif 02745 02746 /******************************************************************************/ 02747 /* */ 02748 /* SystemTick */ 02749 /* */ 02750 /******************************************************************************/ 02751 02752 /***************** Bit definition for SysTick_CTRL register *****************/ 02753 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) 02754 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) 02755 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) 02756 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) 02758 /***************** Bit definition for SysTick_LOAD register *****************/ 02759 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) 02761 /***************** Bit definition for SysTick_VAL register ******************/ 02762 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) 02764 /***************** Bit definition for SysTick_CALIB register ****************/ 02765 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) 02766 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) 02767 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) 02769 /******************************************************************************/ 02770 /* */ 02771 /* Nested Vectored Interrupt Controller */ 02772 /* */ 02773 /******************************************************************************/ 02774 02775 /****************** Bit definition for NVIC_ISER register *******************/ 02776 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) 02777 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) 02778 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) 02779 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) 02780 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) 02781 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) 02782 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) 02783 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) 02784 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) 02785 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) 02786 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) 02787 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) 02788 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) 02789 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) 02790 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) 02791 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) 02792 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) 02793 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) 02794 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) 02795 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) 02796 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) 02797 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) 02798 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) 02799 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) 02800 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) 02801 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) 02802 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) 02803 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) 02804 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) 02805 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) 02806 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) 02807 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) 02808 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) 02810 /****************** Bit definition for NVIC_ICER register *******************/ 02811 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) 02812 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) 02813 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) 02814 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) 02815 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) 02816 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) 02817 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) 02818 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) 02819 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) 02820 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) 02821 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) 02822 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) 02823 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) 02824 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) 02825 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) 02826 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) 02827 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) 02828 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) 02829 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) 02830 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) 02831 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) 02832 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) 02833 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) 02834 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) 02835 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) 02836 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) 02837 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) 02838 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) 02839 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) 02840 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) 02841 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) 02842 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) 02843 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) 02845 /****************** Bit definition for NVIC_ISPR register *******************/ 02846 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) 02847 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) 02848 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) 02849 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) 02850 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) 02851 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) 02852 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) 02853 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) 02854 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) 02855 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) 02856 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) 02857 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) 02858 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) 02859 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) 02860 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) 02861 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) 02862 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) 02863 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) 02864 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) 02865 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) 02866 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) 02867 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) 02868 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) 02869 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) 02870 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) 02871 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) 02872 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) 02873 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) 02874 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) 02875 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) 02876 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) 02877 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) 02878 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) 02880 /****************** Bit definition for NVIC_ICPR register *******************/ 02881 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) 02882 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) 02883 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) 02884 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) 02885 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) 02886 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) 02887 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) 02888 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) 02889 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) 02890 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) 02891 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) 02892 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) 02893 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) 02894 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) 02895 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) 02896 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) 02897 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) 02898 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) 02899 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) 02900 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) 02901 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) 02902 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) 02903 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) 02904 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) 02905 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) 02906 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) 02907 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) 02908 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) 02909 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) 02910 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) 02911 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) 02912 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) 02913 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) 02915 /****************** Bit definition for NVIC_IABR register *******************/ 02916 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) 02917 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) 02918 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) 02919 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) 02920 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) 02921 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) 02922 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) 02923 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) 02924 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) 02925 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) 02926 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) 02927 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) 02928 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) 02929 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) 02930 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) 02931 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) 02932 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) 02933 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) 02934 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) 02935 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) 02936 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) 02937 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) 02938 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) 02939 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) 02940 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) 02941 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) 02942 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) 02943 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) 02944 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) 02945 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) 02946 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) 02947 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) 02948 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) 02950 /****************** Bit definition for NVIC_PRI0 register *******************/ 02951 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) 02952 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) 02953 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) 02954 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) 02956 /****************** Bit definition for NVIC_PRI1 register *******************/ 02957 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) 02958 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) 02959 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) 02960 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) 02962 /****************** Bit definition for NVIC_PRI2 register *******************/ 02963 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) 02964 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) 02965 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) 02966 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) 02968 /****************** Bit definition for NVIC_PRI3 register *******************/ 02969 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) 02970 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) 02971 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) 02972 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) 02974 /****************** Bit definition for NVIC_PRI4 register *******************/ 02975 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) 02976 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) 02977 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) 02978 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) 02980 /****************** Bit definition for NVIC_PRI5 register *******************/ 02981 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) 02982 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) 02983 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) 02984 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) 02986 /****************** Bit definition for NVIC_PRI6 register *******************/ 02987 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) 02988 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) 02989 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) 02990 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) 02992 /****************** Bit definition for NVIC_PRI7 register *******************/ 02993 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) 02994 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) 02995 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) 02996 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) 02998 /****************** Bit definition for SCB_CPUID register *******************/ 02999 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) 03000 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) 03001 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) 03002 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) 03003 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) 03005 /******************* Bit definition for SCB_ICSR register *******************/ 03006 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) 03007 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) 03008 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) 03009 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) 03010 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) 03011 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) 03012 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) 03013 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) 03014 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) 03015 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) 03017 /******************* Bit definition for SCB_VTOR register *******************/ 03018 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) 03019 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) 03022 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) 03023 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) 03024 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) 03026 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) 03027 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) 03028 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) 03029 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) 03031 /* prority group configuration */ 03032 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) 03033 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) 03034 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) 03035 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) 03036 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) 03037 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) 03038 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) 03039 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) 03041 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) 03042 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) 03044 /******************* Bit definition for SCB_SCR register ********************/ 03045 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) 03046 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) 03047 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) 03049 /******************** Bit definition for SCB_CCR register *******************/ 03050 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) 03051 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) 03052 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) 03053 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) 03054 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) 03055 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) 03057 /******************* Bit definition for SCB_SHPR register ********************/ 03058 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) 03059 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) 03060 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) 03061 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) 03063 /****************** Bit definition for SCB_SHCSR register *******************/ 03064 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) 03065 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) 03066 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) 03067 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) 03068 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) 03069 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) 03070 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) 03071 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) 03072 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) 03073 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) 03074 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) 03075 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) 03076 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) 03077 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) 03079 /******************* Bit definition for SCB_CFSR register *******************/ 03080 03081 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) 03082 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) 03083 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) 03084 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) 03085 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) 03087 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) 03088 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) 03089 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) 03090 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) 03091 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) 03092 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) 03094 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) 03095 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) 03096 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) 03097 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) 03098 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) 03099 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) 03101 /******************* Bit definition for SCB_HFSR register *******************/ 03102 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) 03103 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) 03104 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) 03106 /******************* Bit definition for SCB_DFSR register *******************/ 03107 #define SCB_DFSR_HALTED ((uint8_t)0x01) 03108 #define SCB_DFSR_BKPT ((uint8_t)0x02) 03109 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) 03110 #define SCB_DFSR_VCATCH ((uint8_t)0x08) 03111 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) 03113 /******************* Bit definition for SCB_MMFAR register ******************/ 03114 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 03116 /******************* Bit definition for SCB_BFAR register *******************/ 03117 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) 03119 /******************* Bit definition for SCB_afsr register *******************/ 03120 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) 03122 /******************************************************************************/ 03123 /* */ 03124 /* External Interrupt/Event Controller */ 03125 /* */ 03126 /******************************************************************************/ 03127 03128 /******************* Bit definition for EXTI_IMR register *******************/ 03129 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) 03130 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) 03131 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) 03132 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) 03133 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) 03134 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) 03135 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) 03136 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) 03137 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) 03138 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) 03139 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) 03140 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) 03141 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) 03142 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) 03143 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) 03144 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) 03145 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) 03146 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) 03147 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) 03148 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) 03150 /******************* Bit definition for EXTI_EMR register *******************/ 03151 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) 03152 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) 03153 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) 03154 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) 03155 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) 03156 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) 03157 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) 03158 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) 03159 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) 03160 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) 03161 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) 03162 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) 03163 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) 03164 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) 03165 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) 03166 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) 03167 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) 03168 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) 03169 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) 03170 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) 03172 /****************** Bit definition for EXTI_RTSR register *******************/ 03173 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) 03174 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) 03175 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) 03176 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) 03177 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) 03178 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) 03179 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) 03180 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) 03181 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) 03182 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) 03183 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) 03184 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) 03185 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) 03186 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) 03187 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) 03188 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) 03189 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) 03190 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) 03191 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) 03192 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) 03194 /****************** Bit definition for EXTI_FTSR register *******************/ 03195 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) 03196 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) 03197 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) 03198 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) 03199 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) 03200 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) 03201 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) 03202 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) 03203 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) 03204 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) 03205 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) 03206 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) 03207 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) 03208 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) 03209 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) 03210 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) 03211 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) 03212 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) 03213 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) 03214 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) 03216 /****************** Bit definition for EXTI_SWIER register ******************/ 03217 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) 03218 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) 03219 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) 03220 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) 03221 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) 03222 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) 03223 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) 03224 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) 03225 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) 03226 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) 03227 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) 03228 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) 03229 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) 03230 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) 03231 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) 03232 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) 03233 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) 03234 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) 03235 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) 03236 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) 03238 /******************* Bit definition for EXTI_PR register ********************/ 03239 #define EXTI_PR_PR0 ((uint32_t)0x00000001) 03240 #define EXTI_PR_PR1 ((uint32_t)0x00000002) 03241 #define EXTI_PR_PR2 ((uint32_t)0x00000004) 03242 #define EXTI_PR_PR3 ((uint32_t)0x00000008) 03243 #define EXTI_PR_PR4 ((uint32_t)0x00000010) 03244 #define EXTI_PR_PR5 ((uint32_t)0x00000020) 03245 #define EXTI_PR_PR6 ((uint32_t)0x00000040) 03246 #define EXTI_PR_PR7 ((uint32_t)0x00000080) 03247 #define EXTI_PR_PR8 ((uint32_t)0x00000100) 03248 #define EXTI_PR_PR9 ((uint32_t)0x00000200) 03249 #define EXTI_PR_PR10 ((uint32_t)0x00000400) 03250 #define EXTI_PR_PR11 ((uint32_t)0x00000800) 03251 #define EXTI_PR_PR12 ((uint32_t)0x00001000) 03252 #define EXTI_PR_PR13 ((uint32_t)0x00002000) 03253 #define EXTI_PR_PR14 ((uint32_t)0x00004000) 03254 #define EXTI_PR_PR15 ((uint32_t)0x00008000) 03255 #define EXTI_PR_PR16 ((uint32_t)0x00010000) 03256 #define EXTI_PR_PR17 ((uint32_t)0x00020000) 03257 #define EXTI_PR_PR18 ((uint32_t)0x00040000) 03258 #define EXTI_PR_PR19 ((uint32_t)0x00080000) 03260 /******************************************************************************/ 03261 /* */ 03262 /* DMA Controller */ 03263 /* */ 03264 /******************************************************************************/ 03265 03266 /******************* Bit definition for DMA_ISR register ********************/ 03267 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) 03268 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) 03269 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) 03270 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) 03271 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) 03272 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) 03273 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) 03274 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) 03275 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) 03276 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) 03277 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) 03278 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) 03279 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) 03280 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) 03281 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) 03282 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) 03283 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) 03284 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) 03285 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) 03286 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) 03287 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) 03288 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) 03289 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) 03290 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) 03291 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) 03292 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) 03293 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) 03294 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) 03296 /******************* Bit definition for DMA_IFCR register *******************/ 03297 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) 03298 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) 03299 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) 03300 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) 03301 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) 03302 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) 03303 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) 03304 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) 03305 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) 03306 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) 03307 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) 03308 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) 03309 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) 03310 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) 03311 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) 03312 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) 03313 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) 03314 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) 03315 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) 03316 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) 03317 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) 03318 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) 03319 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) 03320 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) 03321 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) 03322 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) 03323 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) 03324 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) 03326 /******************* Bit definition for DMA_CCR1 register *******************/ 03327 #define DMA_CCR1_EN ((uint16_t)0x0001) 03328 #define DMA_CCR1_TCIE ((uint16_t)0x0002) 03329 #define DMA_CCR1_HTIE ((uint16_t)0x0004) 03330 #define DMA_CCR1_TEIE ((uint16_t)0x0008) 03331 #define DMA_CCR1_DIR ((uint16_t)0x0010) 03332 #define DMA_CCR1_CIRC ((uint16_t)0x0020) 03333 #define DMA_CCR1_PINC ((uint16_t)0x0040) 03334 #define DMA_CCR1_MINC ((uint16_t)0x0080) 03336 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) 03337 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) 03338 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) 03340 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) 03341 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) 03342 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) 03344 #define DMA_CCR1_PL ((uint16_t)0x3000) 03345 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) 03346 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) 03348 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) 03350 /******************* Bit definition for DMA_CCR2 register *******************/ 03351 #define DMA_CCR2_EN ((uint16_t)0x0001) 03352 #define DMA_CCR2_TCIE ((uint16_t)0x0002) 03353 #define DMA_CCR2_HTIE ((uint16_t)0x0004) 03354 #define DMA_CCR2_TEIE ((uint16_t)0x0008) 03355 #define DMA_CCR2_DIR ((uint16_t)0x0010) 03356 #define DMA_CCR2_CIRC ((uint16_t)0x0020) 03357 #define DMA_CCR2_PINC ((uint16_t)0x0040) 03358 #define DMA_CCR2_MINC ((uint16_t)0x0080) 03360 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) 03361 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) 03362 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) 03364 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) 03365 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) 03366 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) 03368 #define DMA_CCR2_PL ((uint16_t)0x3000) 03369 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) 03370 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) 03372 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) 03374 /******************* Bit definition for DMA_CCR3 register *******************/ 03375 #define DMA_CCR3_EN ((uint16_t)0x0001) 03376 #define DMA_CCR3_TCIE ((uint16_t)0x0002) 03377 #define DMA_CCR3_HTIE ((uint16_t)0x0004) 03378 #define DMA_CCR3_TEIE ((uint16_t)0x0008) 03379 #define DMA_CCR3_DIR ((uint16_t)0x0010) 03380 #define DMA_CCR3_CIRC ((uint16_t)0x0020) 03381 #define DMA_CCR3_PINC ((uint16_t)0x0040) 03382 #define DMA_CCR3_MINC ((uint16_t)0x0080) 03384 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) 03385 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) 03386 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) 03388 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) 03389 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) 03390 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) 03392 #define DMA_CCR3_PL ((uint16_t)0x3000) 03393 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) 03394 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) 03396 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) 03399 #define DMA_CCR4_EN ((uint16_t)0x0001) 03400 #define DMA_CCR4_TCIE ((uint16_t)0x0002) 03401 #define DMA_CCR4_HTIE ((uint16_t)0x0004) 03402 #define DMA_CCR4_TEIE ((uint16_t)0x0008) 03403 #define DMA_CCR4_DIR ((uint16_t)0x0010) 03404 #define DMA_CCR4_CIRC ((uint16_t)0x0020) 03405 #define DMA_CCR4_PINC ((uint16_t)0x0040) 03406 #define DMA_CCR4_MINC ((uint16_t)0x0080) 03408 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) 03409 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) 03410 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) 03412 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) 03413 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) 03414 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) 03416 #define DMA_CCR4_PL ((uint16_t)0x3000) 03417 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) 03418 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) 03420 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) 03422 /****************** Bit definition for DMA_CCR5 register *******************/ 03423 #define DMA_CCR5_EN ((uint16_t)0x0001) 03424 #define DMA_CCR5_TCIE ((uint16_t)0x0002) 03425 #define DMA_CCR5_HTIE ((uint16_t)0x0004) 03426 #define DMA_CCR5_TEIE ((uint16_t)0x0008) 03427 #define DMA_CCR5_DIR ((uint16_t)0x0010) 03428 #define DMA_CCR5_CIRC ((uint16_t)0x0020) 03429 #define DMA_CCR5_PINC ((uint16_t)0x0040) 03430 #define DMA_CCR5_MINC ((uint16_t)0x0080) 03432 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) 03433 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) 03434 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) 03436 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) 03437 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) 03438 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) 03440 #define DMA_CCR5_PL ((uint16_t)0x3000) 03441 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) 03442 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) 03444 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) 03446 /******************* Bit definition for DMA_CCR6 register *******************/ 03447 #define DMA_CCR6_EN ((uint16_t)0x0001) 03448 #define DMA_CCR6_TCIE ((uint16_t)0x0002) 03449 #define DMA_CCR6_HTIE ((uint16_t)0x0004) 03450 #define DMA_CCR6_TEIE ((uint16_t)0x0008) 03451 #define DMA_CCR6_DIR ((uint16_t)0x0010) 03452 #define DMA_CCR6_CIRC ((uint16_t)0x0020) 03453 #define DMA_CCR6_PINC ((uint16_t)0x0040) 03454 #define DMA_CCR6_MINC ((uint16_t)0x0080) 03456 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) 03457 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) 03458 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) 03460 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) 03461 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) 03462 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) 03464 #define DMA_CCR6_PL ((uint16_t)0x3000) 03465 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) 03466 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) 03468 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) 03470 /******************* Bit definition for DMA_CCR7 register *******************/ 03471 #define DMA_CCR7_EN ((uint16_t)0x0001) 03472 #define DMA_CCR7_TCIE ((uint16_t)0x0002) 03473 #define DMA_CCR7_HTIE ((uint16_t)0x0004) 03474 #define DMA_CCR7_TEIE ((uint16_t)0x0008) 03475 #define DMA_CCR7_DIR ((uint16_t)0x0010) 03476 #define DMA_CCR7_CIRC ((uint16_t)0x0020) 03477 #define DMA_CCR7_PINC ((uint16_t)0x0040) 03478 #define DMA_CCR7_MINC ((uint16_t)0x0080) 03480 #define DMA_CCR7_PSIZE , ((uint16_t)0x0300) 03481 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) 03482 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) 03484 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) 03485 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) 03486 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) 03488 #define DMA_CCR7_PL ((uint16_t)0x3000) 03489 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) 03490 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) 03492 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) 03494 /****************** Bit definition for DMA_CNDTR1 register ******************/ 03495 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) 03497 /****************** Bit definition for DMA_CNDTR2 register ******************/ 03498 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) 03500 /****************** Bit definition for DMA_CNDTR3 register ******************/ 03501 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) 03503 /****************** Bit definition for DMA_CNDTR4 register ******************/ 03504 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) 03506 /****************** Bit definition for DMA_CNDTR5 register ******************/ 03507 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) 03509 /****************** Bit definition for DMA_CNDTR6 register ******************/ 03510 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) 03512 /****************** Bit definition for DMA_CNDTR7 register ******************/ 03513 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) 03515 /****************** Bit definition for DMA_CPAR1 register *******************/ 03516 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) 03518 /****************** Bit definition for DMA_CPAR2 register *******************/ 03519 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) 03521 /****************** Bit definition for DMA_CPAR3 register *******************/ 03522 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) 03525 /****************** Bit definition for DMA_CPAR4 register *******************/ 03526 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) 03528 /****************** Bit definition for DMA_CPAR5 register *******************/ 03529 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) 03531 /****************** Bit definition for DMA_CPAR6 register *******************/ 03532 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) 03535 /****************** Bit definition for DMA_CPAR7 register *******************/ 03536 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) 03538 /****************** Bit definition for DMA_CMAR1 register *******************/ 03539 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) 03541 /****************** Bit definition for DMA_CMAR2 register *******************/ 03542 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) 03544 /****************** Bit definition for DMA_CMAR3 register *******************/ 03545 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) 03548 /****************** Bit definition for DMA_CMAR4 register *******************/ 03549 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) 03551 /****************** Bit definition for DMA_CMAR5 register *******************/ 03552 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) 03554 /****************** Bit definition for DMA_CMAR6 register *******************/ 03555 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) 03557 /****************** Bit definition for DMA_CMAR7 register *******************/ 03558 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) 03560 /******************************************************************************/ 03561 /* */ 03562 /* Analog to Digital Converter */ 03563 /* */ 03564 /******************************************************************************/ 03565 03566 /******************** Bit definition for ADC_SR register ********************/ 03567 #define ADC_SR_AWD ((uint8_t)0x01) 03568 #define ADC_SR_EOC ((uint8_t)0x02) 03569 #define ADC_SR_JEOC ((uint8_t)0x04) 03570 #define ADC_SR_JSTRT ((uint8_t)0x08) 03571 #define ADC_SR_STRT ((uint8_t)0x10) 03573 /******************* Bit definition for ADC_CR1 register ********************/ 03574 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) 03575 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) 03576 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) 03577 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) 03578 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) 03579 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) 03581 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) 03582 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) 03583 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) 03584 #define ADC_CR1_SCAN ((uint32_t)0x00000100) 03585 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) 03586 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) 03587 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) 03588 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) 03590 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) 03591 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) 03592 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) 03593 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) 03595 #define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) 03596 #define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) 03597 #define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) 03598 #define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) 03599 #define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) 03601 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) 03602 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) 03605 /******************* Bit definition for ADC_CR2 register ********************/ 03606 #define ADC_CR2_ADON ((uint32_t)0x00000001) 03607 #define ADC_CR2_CONT ((uint32_t)0x00000002) 03608 #define ADC_CR2_CAL ((uint32_t)0x00000004) 03609 #define ADC_CR2_RSTCAL ((uint32_t)0x00000008) 03610 #define ADC_CR2_DMA ((uint32_t)0x00000100) 03611 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) 03613 #define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) 03614 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) 03615 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) 03616 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) 03618 #define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) 03620 #define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) 03621 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) 03622 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) 03623 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) 03625 #define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) 03626 #define ADC_CR2_JSWSTART ((uint32_t)0x00200000) 03627 #define ADC_CR2_SWSTART ((uint32_t)0x00400000) 03628 #define ADC_CR2_TSVREFE ((uint32_t)0x00800000) 03630 /****************** Bit definition for ADC_SMPR1 register *******************/ 03631 #define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) 03632 #define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) 03633 #define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) 03634 #define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) 03636 #define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) 03637 #define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) 03638 #define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) 03639 #define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) 03641 #define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) 03642 #define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) 03643 #define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) 03644 #define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) 03646 #define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) 03647 #define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) 03648 #define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) 03649 #define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) 03651 #define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) 03652 #define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) 03653 #define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) 03654 #define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) 03656 #define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) 03657 #define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) 03658 #define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) 03659 #define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) 03661 #define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) 03662 #define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) 03663 #define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) 03664 #define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) 03666 #define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) 03667 #define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) 03668 #define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) 03669 #define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) 03671 /****************** Bit definition for ADC_SMPR2 register *******************/ 03672 #define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) 03673 #define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) 03674 #define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) 03675 #define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) 03677 #define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) 03678 #define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) 03679 #define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) 03680 #define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) 03682 #define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) 03683 #define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) 03684 #define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) 03685 #define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) 03687 #define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) 03688 #define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) 03689 #define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) 03690 #define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) 03692 #define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) 03693 #define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) 03694 #define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) 03695 #define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) 03697 #define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) 03698 #define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) 03699 #define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) 03700 #define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) 03702 #define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) 03703 #define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) 03704 #define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) 03705 #define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) 03707 #define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) 03708 #define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) 03709 #define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) 03710 #define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) 03712 #define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) 03713 #define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) 03714 #define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) 03715 #define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) 03717 #define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) 03718 #define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) 03719 #define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) 03720 #define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) 03722 /****************** Bit definition for ADC_JOFR1 register *******************/ 03723 #define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) 03725 /****************** Bit definition for ADC_JOFR2 register *******************/ 03726 #define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) 03728 /****************** Bit definition for ADC_JOFR3 register *******************/ 03729 #define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) 03731 /****************** Bit definition for ADC_JOFR4 register *******************/ 03732 #define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) 03734 /******************* Bit definition for ADC_HTR register ********************/ 03735 #define ADC_HTR_HT ((uint16_t)0x0FFF) 03737 /******************* Bit definition for ADC_LTR register ********************/ 03738 #define ADC_LTR_LT ((uint16_t)0x0FFF) 03740 /******************* Bit definition for ADC_SQR1 register *******************/ 03741 #define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) 03742 #define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) 03743 #define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) 03744 #define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) 03745 #define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) 03746 #define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) 03748 #define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) 03749 #define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) 03750 #define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) 03751 #define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) 03752 #define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) 03753 #define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) 03755 #define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) 03756 #define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) 03757 #define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) 03758 #define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) 03759 #define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) 03760 #define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) 03762 #define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) 03763 #define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) 03764 #define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) 03765 #define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) 03766 #define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) 03767 #define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) 03769 #define ADC_SQR1_L ((uint32_t)0x00F00000) 03770 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) 03771 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) 03772 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) 03773 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) 03775 /******************* Bit definition for ADC_SQR2 register *******************/ 03776 #define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) 03777 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) 03778 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) 03779 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) 03780 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) 03781 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) 03783 #define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) 03784 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) 03785 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) 03786 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) 03787 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) 03788 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) 03790 #define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) 03791 #define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) 03792 #define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) 03793 #define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) 03794 #define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) 03795 #define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) 03797 #define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) 03798 #define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) 03799 #define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) 03800 #define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) 03801 #define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) 03802 #define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) 03804 #define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) 03805 #define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) 03806 #define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) 03807 #define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) 03808 #define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) 03809 #define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) 03811 #define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) 03812 #define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) 03813 #define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) 03814 #define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) 03815 #define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) 03816 #define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) 03818 /******************* Bit definition for ADC_SQR3 register *******************/ 03819 #define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) 03820 #define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) 03821 #define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) 03822 #define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) 03823 #define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) 03824 #define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) 03826 #define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) 03827 #define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) 03828 #define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) 03829 #define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) 03830 #define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) 03831 #define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) 03833 #define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) 03834 #define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) 03835 #define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) 03836 #define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) 03837 #define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) 03838 #define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) 03840 #define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) 03841 #define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) 03842 #define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) 03843 #define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) 03844 #define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) 03845 #define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) 03847 #define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) 03848 #define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) 03849 #define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) 03850 #define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) 03851 #define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) 03852 #define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) 03854 #define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) 03855 #define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) 03856 #define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) 03857 #define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) 03858 #define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) 03859 #define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) 03861 /******************* Bit definition for ADC_JSQR register *******************/ 03862 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) 03863 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) 03864 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) 03865 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) 03866 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) 03867 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) 03869 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) 03870 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) 03871 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) 03872 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) 03873 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) 03874 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) 03876 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) 03877 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) 03878 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) 03879 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) 03880 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) 03881 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) 03883 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) 03884 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) 03885 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) 03886 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) 03887 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) 03888 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) 03890 #define ADC_JSQR_JL ((uint32_t)0x00300000) 03891 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) 03892 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) 03894 /******************* Bit definition for ADC_JDR1 register *******************/ 03895 #define ADC_JDR1_JDATA ((uint16_t)0xFFFF) 03897 /******************* Bit definition for ADC_JDR2 register *******************/ 03898 #define ADC_JDR2_JDATA ((uint16_t)0xFFFF) 03900 /******************* Bit definition for ADC_JDR3 register *******************/ 03901 #define ADC_JDR3_JDATA ((uint16_t)0xFFFF) 03903 /******************* Bit definition for ADC_JDR4 register *******************/ 03904 #define ADC_JDR4_JDATA ((uint16_t)0xFFFF) 03906 /******************** Bit definition for ADC_DR register ********************/ 03907 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) 03908 #define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) 03910 /******************************************************************************/ 03911 /* */ 03912 /* Digital to Analog Converter */ 03913 /* */ 03914 /******************************************************************************/ 03915 03916 /******************** Bit definition for DAC_CR register ********************/ 03917 #define DAC_CR_EN1 ((uint32_t)0x00000001) 03918 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) 03919 #define DAC_CR_TEN1 ((uint32_t)0x00000004) 03921 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) 03922 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) 03923 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) 03924 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) 03926 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) 03927 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) 03928 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) 03930 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) 03931 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) 03932 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) 03933 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) 03934 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) 03936 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) 03937 #define DAC_CR_EN2 ((uint32_t)0x00010000) 03938 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) 03939 #define DAC_CR_TEN2 ((uint32_t)0x00040000) 03941 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) 03942 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) 03943 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) 03944 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) 03946 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) 03947 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) 03948 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) 03950 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) 03951 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) 03952 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) 03953 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) 03954 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) 03956 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) 03958 /***************** Bit definition for DAC_SWTRIGR register ******************/ 03959 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) 03960 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) 03962 /***************** Bit definition for DAC_DHR12R1 register ******************/ 03963 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) 03965 /***************** Bit definition for DAC_DHR12L1 register ******************/ 03966 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) 03968 /****************** Bit definition for DAC_DHR8R1 register ******************/ 03969 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) 03971 /***************** Bit definition for DAC_DHR12R2 register ******************/ 03972 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) 03974 /***************** Bit definition for DAC_DHR12L2 register ******************/ 03975 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) 03977 /****************** Bit definition for DAC_DHR8R2 register ******************/ 03978 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) 03980 /***************** Bit definition for DAC_DHR12RD register ******************/ 03981 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) 03982 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) 03984 /***************** Bit definition for DAC_DHR12LD register ******************/ 03985 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) 03986 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) 03988 /****************** Bit definition for DAC_DHR8RD register ******************/ 03989 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) 03990 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) 03992 /******************* Bit definition for DAC_DOR1 register *******************/ 03993 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) 03995 /******************* Bit definition for DAC_DOR2 register *******************/ 03996 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) 03998 /******************** Bit definition for DAC_SR register ********************/ 03999 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) 04000 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) 04002 /******************************************************************************/ 04003 /* */ 04004 /* CEC */ 04005 /* */ 04006 /******************************************************************************/ 04007 /******************** Bit definition for CEC_CFGR register ******************/ 04008 #define CEC_CFGR_PE ((uint16_t)0x0001) 04009 #define CEC_CFGR_IE ((uint16_t)0x0002) 04010 #define CEC_CFGR_BTEM ((uint16_t)0x0004) 04011 #define CEC_CFGR_BPEM ((uint16_t)0x0008) 04013 /******************** Bit definition for CEC_OAR register ******************/ 04014 #define CEC_OAR_OA ((uint16_t)0x000F) 04015 #define CEC_OAR_OA_0 ((uint16_t)0x0001) 04016 #define CEC_OAR_OA_1 ((uint16_t)0x0002) 04017 #define CEC_OAR_OA_2 ((uint16_t)0x0004) 04018 #define CEC_OAR_OA_3 ((uint16_t)0x0008) 04020 /******************** Bit definition for CEC_PRES register ******************/ 04021 #define CEC_PRES_PRES ((uint16_t)0x3FFF) 04023 /******************** Bit definition for CEC_ESR register ******************/ 04024 #define CEC_ESR_BTE ((uint16_t)0x0001) 04025 #define CEC_ESR_BPE ((uint16_t)0x0002) 04026 #define CEC_ESR_RBTFE ((uint16_t)0x0004) 04027 #define CEC_ESR_SBE ((uint16_t)0x0008) 04028 #define CEC_ESR_ACKE ((uint16_t)0x0010) 04029 #define CEC_ESR_LINE ((uint16_t)0x0020) 04030 #define CEC_ESR_TBTFE ((uint16_t)0x0040) 04032 /******************** Bit definition for CEC_CSR register ******************/ 04033 #define CEC_CSR_TSOM ((uint16_t)0x0001) 04034 #define CEC_CSR_TEOM ((uint16_t)0x0002) 04035 #define CEC_CSR_TERR ((uint16_t)0x0004) 04036 #define CEC_CSR_TBTRF ((uint16_t)0x0008) 04037 #define CEC_CSR_RSOM ((uint16_t)0x0010) 04038 #define CEC_CSR_REOM ((uint16_t)0x0020) 04039 #define CEC_CSR_RERR ((uint16_t)0x0040) 04040 #define CEC_CSR_RBTF ((uint16_t)0x0080) 04042 /******************** Bit definition for CEC_TXD register ******************/ 04043 #define CEC_TXD_TXD ((uint16_t)0x00FF) 04045 /******************** Bit definition for CEC_RXD register ******************/ 04046 #define CEC_RXD_RXD ((uint16_t)0x00FF) 04048 /******************************************************************************/ 04049 /* */ 04050 /* TIM */ 04051 /* */ 04052 /******************************************************************************/ 04053 04054 /******************* Bit definition for TIM_CR1 register ********************/ 04055 #define TIM_CR1_CEN ((uint16_t)0x0001) 04056 #define TIM_CR1_UDIS ((uint16_t)0x0002) 04057 #define TIM_CR1_URS ((uint16_t)0x0004) 04058 #define TIM_CR1_OPM ((uint16_t)0x0008) 04059 #define TIM_CR1_DIR ((uint16_t)0x0010) 04061 #define TIM_CR1_CMS ((uint16_t)0x0060) 04062 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) 04063 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) 04065 #define TIM_CR1_ARPE ((uint16_t)0x0080) 04067 #define TIM_CR1_CKD ((uint16_t)0x0300) 04068 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) 04069 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) 04071 /******************* Bit definition for TIM_CR2 register ********************/ 04072 #define TIM_CR2_CCPC ((uint16_t)0x0001) 04073 #define TIM_CR2_CCUS ((uint16_t)0x0004) 04074 #define TIM_CR2_CCDS ((uint16_t)0x0008) 04076 #define TIM_CR2_MMS ((uint16_t)0x0070) 04077 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) 04078 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) 04079 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) 04081 #define TIM_CR2_TI1S ((uint16_t)0x0080) 04082 #define TIM_CR2_OIS1 ((uint16_t)0x0100) 04083 #define TIM_CR2_OIS1N ((uint16_t)0x0200) 04084 #define TIM_CR2_OIS2 ((uint16_t)0x0400) 04085 #define TIM_CR2_OIS2N ((uint16_t)0x0800) 04086 #define TIM_CR2_OIS3 ((uint16_t)0x1000) 04087 #define TIM_CR2_OIS3N ((uint16_t)0x2000) 04088 #define TIM_CR2_OIS4 ((uint16_t)0x4000) 04090 /******************* Bit definition for TIM_SMCR register *******************/ 04091 #define TIM_SMCR_SMS ((uint16_t)0x0007) 04092 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) 04093 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) 04094 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) 04096 #define TIM_SMCR_TS ((uint16_t)0x0070) 04097 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) 04098 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) 04099 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) 04101 #define TIM_SMCR_MSM ((uint16_t)0x0080) 04103 #define TIM_SMCR_ETF ((uint16_t)0x0F00) 04104 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) 04105 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) 04106 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) 04107 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) 04109 #define TIM_SMCR_ETPS ((uint16_t)0x3000) 04110 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) 04111 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) 04113 #define TIM_SMCR_ECE ((uint16_t)0x4000) 04114 #define TIM_SMCR_ETP ((uint16_t)0x8000) 04116 /******************* Bit definition for TIM_DIER register *******************/ 04117 #define TIM_DIER_UIE ((uint16_t)0x0001) 04118 #define TIM_DIER_CC1IE ((uint16_t)0x0002) 04119 #define TIM_DIER_CC2IE ((uint16_t)0x0004) 04120 #define TIM_DIER_CC3IE ((uint16_t)0x0008) 04121 #define TIM_DIER_CC4IE ((uint16_t)0x0010) 04122 #define TIM_DIER_COMIE ((uint16_t)0x0020) 04123 #define TIM_DIER_TIE ((uint16_t)0x0040) 04124 #define TIM_DIER_BIE ((uint16_t)0x0080) 04125 #define TIM_DIER_UDE ((uint16_t)0x0100) 04126 #define TIM_DIER_CC1DE ((uint16_t)0x0200) 04127 #define TIM_DIER_CC2DE ((uint16_t)0x0400) 04128 #define TIM_DIER_CC3DE ((uint16_t)0x0800) 04129 #define TIM_DIER_CC4DE ((uint16_t)0x1000) 04130 #define TIM_DIER_COMDE ((uint16_t)0x2000) 04131 #define TIM_DIER_TDE ((uint16_t)0x4000) 04133 /******************** Bit definition for TIM_SR register ********************/ 04134 #define TIM_SR_UIF ((uint16_t)0x0001) 04135 #define TIM_SR_CC1IF ((uint16_t)0x0002) 04136 #define TIM_SR_CC2IF ((uint16_t)0x0004) 04137 #define TIM_SR_CC3IF ((uint16_t)0x0008) 04138 #define TIM_SR_CC4IF ((uint16_t)0x0010) 04139 #define TIM_SR_COMIF ((uint16_t)0x0020) 04140 #define TIM_SR_TIF ((uint16_t)0x0040) 04141 #define TIM_SR_BIF ((uint16_t)0x0080) 04142 #define TIM_SR_CC1OF ((uint16_t)0x0200) 04143 #define TIM_SR_CC2OF ((uint16_t)0x0400) 04144 #define TIM_SR_CC3OF ((uint16_t)0x0800) 04145 #define TIM_SR_CC4OF ((uint16_t)0x1000) 04147 /******************* Bit definition for TIM_EGR register ********************/ 04148 #define TIM_EGR_UG ((uint8_t)0x01) 04149 #define TIM_EGR_CC1G ((uint8_t)0x02) 04150 #define TIM_EGR_CC2G ((uint8_t)0x04) 04151 #define TIM_EGR_CC3G ((uint8_t)0x08) 04152 #define TIM_EGR_CC4G ((uint8_t)0x10) 04153 #define TIM_EGR_COMG ((uint8_t)0x20) 04154 #define TIM_EGR_TG ((uint8_t)0x40) 04155 #define TIM_EGR_BG ((uint8_t)0x80) 04157 /****************** Bit definition for TIM_CCMR1 register *******************/ 04158 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) 04159 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) 04160 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) 04162 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) 04163 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) 04165 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) 04166 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) 04167 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) 04168 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) 04170 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) 04172 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) 04173 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) 04174 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) 04176 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) 04177 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) 04179 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) 04180 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) 04181 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) 04182 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) 04184 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) 04186 /*----------------------------------------------------------------------------*/ 04187 04188 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) 04189 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) 04190 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) 04192 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) 04193 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) 04194 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) 04195 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) 04196 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) 04198 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) 04199 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) 04200 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) 04202 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) 04203 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) 04204 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) 04205 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) 04206 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) 04208 /****************** Bit definition for TIM_CCMR2 register *******************/ 04209 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) 04210 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) 04211 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) 04213 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) 04214 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) 04216 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) 04217 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) 04218 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) 04219 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) 04221 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) 04223 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) 04224 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) 04225 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) 04227 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) 04228 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) 04230 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) 04231 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) 04232 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) 04233 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) 04235 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) 04237 /*----------------------------------------------------------------------------*/ 04238 04239 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) 04240 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) 04241 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) 04243 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) 04244 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) 04245 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) 04246 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) 04247 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) 04249 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) 04250 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) 04251 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) 04253 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) 04254 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) 04255 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) 04256 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) 04257 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) 04259 /******************* Bit definition for TIM_CCER register *******************/ 04260 #define TIM_CCER_CC1E ((uint16_t)0x0001) 04261 #define TIM_CCER_CC1P ((uint16_t)0x0002) 04262 #define TIM_CCER_CC1NE ((uint16_t)0x0004) 04263 #define TIM_CCER_CC1NP ((uint16_t)0x0008) 04264 #define TIM_CCER_CC2E ((uint16_t)0x0010) 04265 #define TIM_CCER_CC2P ((uint16_t)0x0020) 04266 #define TIM_CCER_CC2NE ((uint16_t)0x0040) 04267 #define TIM_CCER_CC2NP ((uint16_t)0x0080) 04268 #define TIM_CCER_CC3E ((uint16_t)0x0100) 04269 #define TIM_CCER_CC3P ((uint16_t)0x0200) 04270 #define TIM_CCER_CC3NE ((uint16_t)0x0400) 04271 #define TIM_CCER_CC3NP ((uint16_t)0x0800) 04272 #define TIM_CCER_CC4E ((uint16_t)0x1000) 04273 #define TIM_CCER_CC4P ((uint16_t)0x2000) 04275 /******************* Bit definition for TIM_CNT register ********************/ 04276 #define TIM_CNT_CNT ((uint16_t)0xFFFF) 04278 /******************* Bit definition for TIM_PSC register ********************/ 04279 #define TIM_PSC_PSC ((uint16_t)0xFFFF) 04281 /******************* Bit definition for TIM_ARR register ********************/ 04282 #define TIM_ARR_ARR ((uint16_t)0xFFFF) 04284 /******************* Bit definition for TIM_RCR register ********************/ 04285 #define TIM_RCR_REP ((uint8_t)0xFF) 04287 /******************* Bit definition for TIM_CCR1 register *******************/ 04288 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) 04290 /******************* Bit definition for TIM_CCR2 register *******************/ 04291 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) 04293 /******************* Bit definition for TIM_CCR3 register *******************/ 04294 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) 04296 /******************* Bit definition for TIM_CCR4 register *******************/ 04297 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) 04299 /******************* Bit definition for TIM_BDTR register *******************/ 04300 #define TIM_BDTR_DTG ((uint16_t)0x00FF) 04301 #define TIM_BDTR_DTG_0 ((uint16_t)0x0001) 04302 #define TIM_BDTR_DTG_1 ((uint16_t)0x0002) 04303 #define TIM_BDTR_DTG_2 ((uint16_t)0x0004) 04304 #define TIM_BDTR_DTG_3 ((uint16_t)0x0008) 04305 #define TIM_BDTR_DTG_4 ((uint16_t)0x0010) 04306 #define TIM_BDTR_DTG_5 ((uint16_t)0x0020) 04307 #define TIM_BDTR_DTG_6 ((uint16_t)0x0040) 04308 #define TIM_BDTR_DTG_7 ((uint16_t)0x0080) 04310 #define TIM_BDTR_LOCK ((uint16_t)0x0300) 04311 #define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) 04312 #define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) 04314 #define TIM_BDTR_OSSI ((uint16_t)0x0400) 04315 #define TIM_BDTR_OSSR ((uint16_t)0x0800) 04316 #define TIM_BDTR_BKE ((uint16_t)0x1000) 04317 #define TIM_BDTR_BKP ((uint16_t)0x2000) 04318 #define TIM_BDTR_AOE ((uint16_t)0x4000) 04319 #define TIM_BDTR_MOE ((uint16_t)0x8000) 04321 /******************* Bit definition for TIM_DCR register ********************/ 04322 #define TIM_DCR_DBA ((uint16_t)0x001F) 04323 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) 04324 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) 04325 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) 04326 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) 04327 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) 04329 #define TIM_DCR_DBL ((uint16_t)0x1F00) 04330 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) 04331 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) 04332 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) 04333 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) 04334 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) 04336 /******************* Bit definition for TIM_DMAR register *******************/ 04337 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) 04339 /******************************************************************************/ 04340 /* */ 04341 /* Real-Time Clock */ 04342 /* */ 04343 /******************************************************************************/ 04344 04345 /******************* Bit definition for RTC_CRH register ********************/ 04346 #define RTC_CRH_SECIE ((uint8_t)0x01) 04347 #define RTC_CRH_ALRIE ((uint8_t)0x02) 04348 #define RTC_CRH_OWIE ((uint8_t)0x04) 04350 /******************* Bit definition for RTC_CRL register ********************/ 04351 #define RTC_CRL_SECF ((uint8_t)0x01) 04352 #define RTC_CRL_ALRF ((uint8_t)0x02) 04353 #define RTC_CRL_OWF ((uint8_t)0x04) 04354 #define RTC_CRL_RSF ((uint8_t)0x08) 04355 #define RTC_CRL_CNF ((uint8_t)0x10) 04356 #define RTC_CRL_RTOFF ((uint8_t)0x20) 04358 /******************* Bit definition for RTC_PRLH register *******************/ 04359 #define RTC_PRLH_PRL ((uint16_t)0x000F) 04361 /******************* Bit definition for RTC_PRLL register *******************/ 04362 #define RTC_PRLL_PRL ((uint16_t)0xFFFF) 04364 /******************* Bit definition for RTC_DIVH register *******************/ 04365 #define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) 04367 /******************* Bit definition for RTC_DIVL register *******************/ 04368 #define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) 04370 /******************* Bit definition for RTC_CNTH register *******************/ 04371 #define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) 04373 /******************* Bit definition for RTC_CNTL register *******************/ 04374 #define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) 04376 /******************* Bit definition for RTC_ALRH register *******************/ 04377 #define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) 04379 /******************* Bit definition for RTC_ALRL register *******************/ 04380 #define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) 04382 /******************************************************************************/ 04383 /* */ 04384 /* Independent WATCHDOG */ 04385 /* */ 04386 /******************************************************************************/ 04387 04388 /******************* Bit definition for IWDG_KR register ********************/ 04389 #define IWDG_KR_KEY ((uint16_t)0xFFFF) 04391 /******************* Bit definition for IWDG_PR register ********************/ 04392 #define IWDG_PR_PR ((uint8_t)0x07) 04393 #define IWDG_PR_PR_0 ((uint8_t)0x01) 04394 #define IWDG_PR_PR_1 ((uint8_t)0x02) 04395 #define IWDG_PR_PR_2 ((uint8_t)0x04) 04397 /******************* Bit definition for IWDG_RLR register *******************/ 04398 #define IWDG_RLR_RL ((uint16_t)0x0FFF) 04400 /******************* Bit definition for IWDG_SR register ********************/ 04401 #define IWDG_SR_PVU ((uint8_t)0x01) 04402 #define IWDG_SR_RVU ((uint8_t)0x02) 04404 /******************************************************************************/ 04405 /* */ 04406 /* Window WATCHDOG */ 04407 /* */ 04408 /******************************************************************************/ 04409 04410 /******************* Bit definition for WWDG_CR register ********************/ 04411 #define WWDG_CR_T ((uint8_t)0x7F) 04412 #define WWDG_CR_T0 ((uint8_t)0x01) 04413 #define WWDG_CR_T1 ((uint8_t)0x02) 04414 #define WWDG_CR_T2 ((uint8_t)0x04) 04415 #define WWDG_CR_T3 ((uint8_t)0x08) 04416 #define WWDG_CR_T4 ((uint8_t)0x10) 04417 #define WWDG_CR_T5 ((uint8_t)0x20) 04418 #define WWDG_CR_T6 ((uint8_t)0x40) 04420 #define WWDG_CR_WDGA ((uint8_t)0x80) 04422 /******************* Bit definition for WWDG_CFR register *******************/ 04423 #define WWDG_CFR_W ((uint16_t)0x007F) 04424 #define WWDG_CFR_W0 ((uint16_t)0x0001) 04425 #define WWDG_CFR_W1 ((uint16_t)0x0002) 04426 #define WWDG_CFR_W2 ((uint16_t)0x0004) 04427 #define WWDG_CFR_W3 ((uint16_t)0x0008) 04428 #define WWDG_CFR_W4 ((uint16_t)0x0010) 04429 #define WWDG_CFR_W5 ((uint16_t)0x0020) 04430 #define WWDG_CFR_W6 ((uint16_t)0x0040) 04432 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) 04433 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) 04434 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) 04436 #define WWDG_CFR_EWI ((uint16_t)0x0200) 04438 /******************* Bit definition for WWDG_SR register ********************/ 04439 #define WWDG_SR_EWIF ((uint8_t)0x01) 04441 /******************************************************************************/ 04442 /* */ 04443 /* Flexible Static Memory Controller */ 04444 /* */ 04445 /******************************************************************************/ 04446 04447 /****************** Bit definition for FSMC_BCR1 register *******************/ 04448 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) 04449 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) 04451 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) 04452 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) 04453 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) 04455 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) 04456 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) 04457 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) 04459 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) 04460 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) 04461 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) 04462 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) 04463 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) 04464 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) 04465 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) 04466 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) 04467 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) 04469 /****************** Bit definition for FSMC_BCR2 register *******************/ 04470 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) 04471 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) 04473 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) 04474 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) 04475 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) 04477 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) 04478 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) 04479 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) 04481 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) 04482 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) 04483 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) 04484 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) 04485 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) 04486 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) 04487 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) 04488 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) 04489 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) 04491 /****************** Bit definition for FSMC_BCR3 register *******************/ 04492 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) 04493 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) 04495 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) 04496 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) 04497 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) 04499 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) 04500 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) 04501 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) 04503 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) 04504 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) 04505 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) 04506 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) 04507 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) 04508 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) 04509 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) 04510 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) 04511 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) 04513 /****************** Bit definition for FSMC_BCR4 register *******************/ 04514 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) 04515 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) 04517 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) 04518 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) 04519 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) 04521 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) 04522 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) 04523 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) 04525 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) 04526 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) 04527 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) 04528 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) 04529 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) 04530 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) 04531 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) 04532 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) 04533 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) 04535 /****************** Bit definition for FSMC_BTR1 register ******************/ 04536 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) 04537 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) 04538 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) 04539 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) 04540 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) 04542 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) 04543 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) 04544 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) 04545 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) 04546 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) 04548 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) 04549 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) 04550 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) 04551 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) 04552 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) 04554 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) 04555 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) 04556 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) 04557 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) 04558 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) 04560 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) 04561 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) 04562 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) 04563 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) 04564 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) 04566 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) 04567 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) 04568 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) 04569 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) 04570 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) 04572 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) 04573 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) 04574 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) 04576 /****************** Bit definition for FSMC_BTR2 register *******************/ 04577 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) 04578 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) 04579 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) 04580 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) 04581 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) 04583 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) 04584 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) 04585 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) 04586 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) 04587 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) 04589 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) 04590 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) 04591 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) 04592 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) 04593 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) 04595 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) 04596 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) 04597 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) 04598 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) 04599 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) 04601 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) 04602 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) 04603 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) 04604 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) 04605 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) 04607 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) 04608 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) 04609 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) 04610 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) 04611 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) 04613 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) 04614 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) 04615 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) 04617 /******************* Bit definition for FSMC_BTR3 register *******************/ 04618 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) 04619 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) 04620 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) 04621 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) 04622 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) 04624 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) 04625 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) 04626 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) 04627 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) 04628 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) 04630 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) 04631 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) 04632 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) 04633 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) 04634 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) 04636 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) 04637 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) 04638 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) 04639 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) 04640 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) 04642 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) 04643 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) 04644 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) 04645 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) 04646 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) 04648 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) 04649 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) 04650 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) 04651 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) 04652 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) 04654 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) 04655 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) 04656 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) 04658 /****************** Bit definition for FSMC_BTR4 register *******************/ 04659 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) 04660 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) 04661 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) 04662 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) 04663 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) 04665 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) 04666 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) 04667 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) 04668 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) 04669 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) 04671 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) 04672 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) 04673 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) 04674 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) 04675 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) 04677 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) 04678 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) 04679 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) 04680 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) 04681 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) 04683 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) 04684 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) 04685 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) 04686 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) 04687 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) 04689 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) 04690 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) 04691 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) 04692 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) 04693 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) 04695 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) 04696 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) 04697 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) 04699 /****************** Bit definition for FSMC_BWTR1 register ******************/ 04700 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) 04701 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) 04702 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) 04703 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) 04704 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) 04706 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) 04707 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) 04708 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) 04709 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) 04710 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) 04712 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) 04713 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) 04714 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) 04715 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) 04716 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) 04718 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) 04719 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) 04720 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) 04721 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) 04722 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) 04724 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) 04725 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) 04726 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) 04727 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) 04728 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) 04730 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) 04731 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) 04732 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) 04734 /****************** Bit definition for FSMC_BWTR2 register ******************/ 04735 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) 04736 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) 04737 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) 04738 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) 04739 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) 04741 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) 04742 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) 04743 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) 04744 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) 04745 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) 04747 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) 04748 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) 04749 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) 04750 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) 04751 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) 04753 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) 04754 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) 04755 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) 04756 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) 04757 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) 04759 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) 04760 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) 04761 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) 04762 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) 04763 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) 04765 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) 04766 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) 04767 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) 04769 /****************** Bit definition for FSMC_BWTR3 register ******************/ 04770 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) 04771 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) 04772 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) 04773 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) 04774 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) 04776 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) 04777 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) 04778 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) 04779 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) 04780 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) 04782 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) 04783 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) 04784 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) 04785 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) 04786 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) 04788 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) 04789 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) 04790 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) 04791 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) 04792 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) 04794 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) 04795 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) 04796 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) 04797 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) 04798 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) 04800 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) 04801 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) 04802 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) 04804 /****************** Bit definition for FSMC_BWTR4 register ******************/ 04805 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) 04806 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) 04807 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) 04808 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) 04809 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) 04811 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) 04812 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) 04813 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) 04814 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) 04815 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) 04817 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) 04818 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) 04819 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) 04820 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) 04821 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) 04823 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) 04824 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) 04825 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) 04826 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) 04827 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) 04829 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) 04830 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) 04831 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) 04832 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) 04833 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) 04835 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) 04836 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) 04837 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) 04839 /****************** Bit definition for FSMC_PCR2 register *******************/ 04840 #define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) 04841 #define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) 04842 #define FSMC_PCR2_PTYP ((uint32_t)0x00000008) 04844 #define FSMC_PCR2_PWID ((uint32_t)0x00000030) 04845 #define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) 04846 #define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) 04848 #define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) 04850 #define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) 04851 #define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) 04852 #define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) 04853 #define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) 04854 #define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) 04856 #define FSMC_PCR2_TAR ((uint32_t)0x0001E000) 04857 #define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) 04858 #define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) 04859 #define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) 04860 #define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) 04862 #define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) 04863 #define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) 04864 #define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) 04865 #define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) 04867 /****************** Bit definition for FSMC_PCR3 register *******************/ 04868 #define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) 04869 #define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) 04870 #define FSMC_PCR3_PTYP ((uint32_t)0x00000008) 04872 #define FSMC_PCR3_PWID ((uint32_t)0x00000030) 04873 #define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) 04874 #define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) 04876 #define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) 04878 #define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) 04879 #define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) 04880 #define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) 04881 #define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) 04882 #define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) 04884 #define FSMC_PCR3_TAR ((uint32_t)0x0001E000) 04885 #define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) 04886 #define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) 04887 #define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) 04888 #define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) 04890 #define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) 04891 #define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) 04892 #define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) 04893 #define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) 04895 /****************** Bit definition for FSMC_PCR4 register *******************/ 04896 #define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) 04897 #define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) 04898 #define FSMC_PCR4_PTYP ((uint32_t)0x00000008) 04900 #define FSMC_PCR4_PWID ((uint32_t)0x00000030) 04901 #define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) 04902 #define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) 04904 #define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) 04906 #define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) 04907 #define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) 04908 #define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) 04909 #define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) 04910 #define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) 04912 #define FSMC_PCR4_TAR ((uint32_t)0x0001E000) 04913 #define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) 04914 #define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) 04915 #define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) 04916 #define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) 04918 #define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) 04919 #define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) 04920 #define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) 04921 #define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) 04923 /******************* Bit definition for FSMC_SR2 register *******************/ 04924 #define FSMC_SR2_IRS ((uint8_t)0x01) 04925 #define FSMC_SR2_ILS ((uint8_t)0x02) 04926 #define FSMC_SR2_IFS ((uint8_t)0x04) 04927 #define FSMC_SR2_IREN ((uint8_t)0x08) 04928 #define FSMC_SR2_ILEN ((uint8_t)0x10) 04929 #define FSMC_SR2_IFEN ((uint8_t)0x20) 04930 #define FSMC_SR2_FEMPT ((uint8_t)0x40) 04932 /******************* Bit definition for FSMC_SR3 register *******************/ 04933 #define FSMC_SR3_IRS ((uint8_t)0x01) 04934 #define FSMC_SR3_ILS ((uint8_t)0x02) 04935 #define FSMC_SR3_IFS ((uint8_t)0x04) 04936 #define FSMC_SR3_IREN ((uint8_t)0x08) 04937 #define FSMC_SR3_ILEN ((uint8_t)0x10) 04938 #define FSMC_SR3_IFEN ((uint8_t)0x20) 04939 #define FSMC_SR3_FEMPT ((uint8_t)0x40) 04941 /******************* Bit definition for FSMC_SR4 register *******************/ 04942 #define FSMC_SR4_IRS ((uint8_t)0x01) 04943 #define FSMC_SR4_ILS ((uint8_t)0x02) 04944 #define FSMC_SR4_IFS ((uint8_t)0x04) 04945 #define FSMC_SR4_IREN ((uint8_t)0x08) 04946 #define FSMC_SR4_ILEN ((uint8_t)0x10) 04947 #define FSMC_SR4_IFEN ((uint8_t)0x20) 04948 #define FSMC_SR4_FEMPT ((uint8_t)0x40) 04950 /****************** Bit definition for FSMC_PMEM2 register ******************/ 04951 #define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) 04952 #define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) 04953 #define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) 04954 #define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) 04955 #define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) 04956 #define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) 04957 #define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) 04958 #define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) 04959 #define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) 04961 #define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) 04962 #define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) 04963 #define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) 04964 #define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) 04965 #define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) 04966 #define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) 04967 #define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) 04968 #define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) 04969 #define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) 04971 #define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) 04972 #define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) 04973 #define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) 04974 #define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) 04975 #define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) 04976 #define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) 04977 #define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) 04978 #define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) 04979 #define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) 04981 #define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) 04982 #define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) 04983 #define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) 04984 #define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) 04985 #define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) 04986 #define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) 04987 #define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) 04988 #define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) 04989 #define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) 04991 /****************** Bit definition for FSMC_PMEM3 register ******************/ 04992 #define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) 04993 #define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) 04994 #define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) 04995 #define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) 04996 #define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) 04997 #define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) 04998 #define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) 04999 #define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) 05000 #define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) 05002 #define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) 05003 #define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) 05004 #define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) 05005 #define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) 05006 #define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) 05007 #define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) 05008 #define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) 05009 #define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) 05010 #define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) 05012 #define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) 05013 #define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) 05014 #define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) 05015 #define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) 05016 #define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) 05017 #define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) 05018 #define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) 05019 #define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) 05020 #define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) 05022 #define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) 05023 #define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) 05024 #define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) 05025 #define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) 05026 #define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) 05027 #define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) 05028 #define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) 05029 #define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) 05030 #define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) 05032 /****************** Bit definition for FSMC_PMEM4 register ******************/ 05033 #define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) 05034 #define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) 05035 #define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) 05036 #define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) 05037 #define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) 05038 #define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) 05039 #define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) 05040 #define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) 05041 #define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) 05043 #define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) 05044 #define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) 05045 #define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) 05046 #define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) 05047 #define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) 05048 #define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) 05049 #define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) 05050 #define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) 05051 #define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) 05053 #define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) 05054 #define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) 05055 #define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) 05056 #define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) 05057 #define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) 05058 #define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) 05059 #define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) 05060 #define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) 05061 #define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) 05063 #define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) 05064 #define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) 05065 #define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) 05066 #define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) 05067 #define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) 05068 #define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) 05069 #define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) 05070 #define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) 05071 #define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) 05073 /****************** Bit definition for FSMC_PATT2 register ******************/ 05074 #define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) 05075 #define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) 05076 #define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) 05077 #define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) 05078 #define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) 05079 #define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) 05080 #define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) 05081 #define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) 05082 #define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) 05084 #define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) 05085 #define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) 05086 #define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) 05087 #define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) 05088 #define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) 05089 #define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) 05090 #define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) 05091 #define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) 05092 #define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) 05094 #define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) 05095 #define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) 05096 #define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) 05097 #define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) 05098 #define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) 05099 #define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) 05100 #define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) 05101 #define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) 05102 #define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) 05104 #define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) 05105 #define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) 05106 #define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) 05107 #define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) 05108 #define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) 05109 #define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) 05110 #define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) 05111 #define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) 05112 #define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) 05114 /****************** Bit definition for FSMC_PATT3 register ******************/ 05115 #define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) 05116 #define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) 05117 #define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) 05118 #define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) 05119 #define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) 05120 #define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) 05121 #define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) 05122 #define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) 05123 #define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) 05125 #define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) 05126 #define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) 05127 #define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) 05128 #define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) 05129 #define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) 05130 #define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) 05131 #define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) 05132 #define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) 05133 #define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) 05135 #define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) 05136 #define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) 05137 #define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) 05138 #define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) 05139 #define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) 05140 #define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) 05141 #define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) 05142 #define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) 05143 #define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) 05145 #define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) 05146 #define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) 05147 #define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) 05148 #define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) 05149 #define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) 05150 #define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) 05151 #define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) 05152 #define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) 05153 #define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) 05155 /****************** Bit definition for FSMC_PATT4 register ******************/ 05156 #define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) 05157 #define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) 05158 #define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) 05159 #define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) 05160 #define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) 05161 #define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) 05162 #define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) 05163 #define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) 05164 #define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) 05166 #define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) 05167 #define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) 05168 #define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) 05169 #define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) 05170 #define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) 05171 #define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) 05172 #define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) 05173 #define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) 05174 #define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) 05176 #define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) 05177 #define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) 05178 #define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) 05179 #define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) 05180 #define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) 05181 #define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) 05182 #define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) 05183 #define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) 05184 #define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) 05186 #define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) 05187 #define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) 05188 #define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) 05189 #define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) 05190 #define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) 05191 #define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) 05192 #define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) 05193 #define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) 05194 #define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) 05196 /****************** Bit definition for FSMC_PIO4 register *******************/ 05197 #define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) 05198 #define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) 05199 #define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) 05200 #define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) 05201 #define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) 05202 #define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) 05203 #define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) 05204 #define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) 05205 #define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) 05207 #define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) 05208 #define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) 05209 #define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) 05210 #define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) 05211 #define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) 05212 #define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) 05213 #define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) 05214 #define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) 05215 #define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) 05217 #define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) 05218 #define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) 05219 #define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) 05220 #define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) 05221 #define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) 05222 #define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) 05223 #define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) 05224 #define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) 05225 #define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) 05227 #define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) 05228 #define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) 05229 #define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) 05230 #define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) 05231 #define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) 05232 #define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) 05233 #define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) 05234 #define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) 05235 #define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) 05237 /****************** Bit definition for FSMC_ECCR2 register ******************/ 05238 #define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) 05240 /****************** Bit definition for FSMC_ECCR3 register ******************/ 05241 #define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) 05243 /******************************************************************************/ 05244 /* */ 05245 /* SD host Interface */ 05246 /* */ 05247 /******************************************************************************/ 05248 05249 /****************** Bit definition for SDIO_POWER register ******************/ 05250 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) 05251 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) 05252 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) 05254 /****************** Bit definition for SDIO_CLKCR register ******************/ 05255 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) 05256 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) 05257 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) 05258 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) 05260 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) 05261 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) 05262 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) 05264 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) 05265 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) 05267 /******************* Bit definition for SDIO_ARG register *******************/ 05268 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) 05270 /******************* Bit definition for SDIO_CMD register *******************/ 05271 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) 05273 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) 05274 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) 05275 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) 05277 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) 05278 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) 05279 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) 05280 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) 05281 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) 05282 #define SDIO_CMD_NIEN ((uint16_t)0x2000) 05283 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) 05285 /***************** Bit definition for SDIO_RESPCMD register *****************/ 05286 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) 05288 /****************** Bit definition for SDIO_RESP0 register ******************/ 05289 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) 05291 /****************** Bit definition for SDIO_RESP1 register ******************/ 05292 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) 05294 /****************** Bit definition for SDIO_RESP2 register ******************/ 05295 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) 05297 /****************** Bit definition for SDIO_RESP3 register ******************/ 05298 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) 05300 /****************** Bit definition for SDIO_RESP4 register ******************/ 05301 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) 05303 /****************** Bit definition for SDIO_DTIMER register *****************/ 05304 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) 05306 /****************** Bit definition for SDIO_DLEN register *******************/ 05307 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) 05309 /****************** Bit definition for SDIO_DCTRL register ******************/ 05310 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) 05311 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) 05312 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) 05313 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) 05315 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) 05316 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) 05317 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) 05318 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) 05319 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) 05321 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) 05322 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) 05323 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) 05324 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) 05326 /****************** Bit definition for SDIO_DCOUNT register *****************/ 05327 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) 05329 /****************** Bit definition for SDIO_STA register ********************/ 05330 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) 05331 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) 05332 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) 05333 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) 05334 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) 05335 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) 05336 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) 05337 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) 05338 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) 05339 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) 05340 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) 05341 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) 05342 #define SDIO_STA_TXACT ((uint32_t)0x00001000) 05343 #define SDIO_STA_RXACT ((uint32_t)0x00002000) 05344 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) 05345 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) 05346 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) 05347 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) 05348 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) 05349 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) 05350 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) 05351 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) 05352 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) 05353 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) 05355 /******************* Bit definition for SDIO_ICR register *******************/ 05356 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) 05357 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) 05358 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) 05359 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) 05360 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) 05361 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) 05362 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) 05363 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) 05364 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) 05365 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) 05366 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) 05367 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) 05368 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) 05370 /****************** Bit definition for SDIO_MASK register *******************/ 05371 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) 05372 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) 05373 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) 05374 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) 05375 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) 05376 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) 05377 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) 05378 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) 05379 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) 05380 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) 05381 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) 05382 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) 05383 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) 05384 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) 05385 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) 05386 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) 05387 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) 05388 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) 05389 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) 05390 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) 05391 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) 05392 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) 05393 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) 05394 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) 05396 /***************** Bit definition for SDIO_FIFOCNT register *****************/ 05397 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) 05399 /****************** Bit definition for SDIO_FIFO register *******************/ 05400 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) 05402 /******************************************************************************/ 05403 /* */ 05404 /* USB Device FS */ 05405 /* */ 05406 /******************************************************************************/ 05407 05409 /******************* Bit definition for USB_EP0R register *******************/ 05410 #define USB_EP0R_EA ((uint16_t)0x000F) 05412 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) 05413 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) 05414 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) 05416 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) 05417 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) 05418 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) 05420 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) 05421 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) 05422 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) 05424 #define USB_EP0R_SETUP ((uint16_t)0x0800) 05426 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) 05427 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) 05428 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) 05430 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) 05431 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) 05433 /******************* Bit definition for USB_EP1R register *******************/ 05434 #define USB_EP1R_EA ((uint16_t)0x000F) 05436 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) 05437 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) 05438 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) 05440 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) 05441 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) 05442 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) 05444 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) 05445 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) 05446 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) 05448 #define USB_EP1R_SETUP ((uint16_t)0x0800) 05450 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) 05451 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) 05452 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) 05454 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) 05455 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) 05457 /******************* Bit definition for USB_EP2R register *******************/ 05458 #define USB_EP2R_EA ((uint16_t)0x000F) 05460 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) 05461 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) 05462 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) 05464 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) 05465 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) 05466 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) 05468 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) 05469 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) 05470 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) 05472 #define USB_EP2R_SETUP ((uint16_t)0x0800) 05474 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) 05475 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) 05476 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) 05478 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) 05479 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) 05481 /******************* Bit definition for USB_EP3R register *******************/ 05482 #define USB_EP3R_EA ((uint16_t)0x000F) 05484 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) 05485 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) 05486 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) 05488 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) 05489 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) 05490 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) 05492 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) 05493 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) 05494 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) 05496 #define USB_EP3R_SETUP ((uint16_t)0x0800) 05498 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) 05499 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) 05500 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) 05502 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) 05503 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) 05505 /******************* Bit definition for USB_EP4R register *******************/ 05506 #define USB_EP4R_EA ((uint16_t)0x000F) 05508 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) 05509 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) 05510 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) 05512 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) 05513 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) 05514 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) 05516 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) 05517 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) 05518 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) 05520 #define USB_EP4R_SETUP ((uint16_t)0x0800) 05522 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) 05523 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) 05524 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) 05526 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) 05527 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) 05529 /******************* Bit definition for USB_EP5R register *******************/ 05530 #define USB_EP5R_EA ((uint16_t)0x000F) 05532 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) 05533 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) 05534 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) 05536 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) 05537 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) 05538 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) 05540 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) 05541 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) 05542 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) 05544 #define USB_EP5R_SETUP ((uint16_t)0x0800) 05546 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) 05547 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) 05548 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) 05550 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) 05551 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) 05553 /******************* Bit definition for USB_EP6R register *******************/ 05554 #define USB_EP6R_EA ((uint16_t)0x000F) 05556 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) 05557 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) 05558 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) 05560 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) 05561 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) 05562 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) 05564 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) 05565 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) 05566 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) 05568 #define USB_EP6R_SETUP ((uint16_t)0x0800) 05570 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) 05571 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) 05572 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) 05574 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) 05575 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) 05577 /******************* Bit definition for USB_EP7R register *******************/ 05578 #define USB_EP7R_EA ((uint16_t)0x000F) 05580 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) 05581 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) 05582 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) 05584 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) 05585 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) 05586 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) 05588 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) 05589 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) 05590 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) 05592 #define USB_EP7R_SETUP ((uint16_t)0x0800) 05594 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) 05595 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) 05596 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) 05598 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) 05599 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) 05602 /******************* Bit definition for USB_CNTR register *******************/ 05603 #define USB_CNTR_FRES ((uint16_t)0x0001) 05604 #define USB_CNTR_PDWN ((uint16_t)0x0002) 05605 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) 05606 #define USB_CNTR_FSUSP ((uint16_t)0x0008) 05607 #define USB_CNTR_RESUME ((uint16_t)0x0010) 05608 #define USB_CNTR_ESOFM ((uint16_t)0x0100) 05609 #define USB_CNTR_SOFM ((uint16_t)0x0200) 05610 #define USB_CNTR_RESETM ((uint16_t)0x0400) 05611 #define USB_CNTR_SUSPM ((uint16_t)0x0800) 05612 #define USB_CNTR_WKUPM ((uint16_t)0x1000) 05613 #define USB_CNTR_ERRM ((uint16_t)0x2000) 05614 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) 05615 #define USB_CNTR_CTRM ((uint16_t)0x8000) 05617 /******************* Bit definition for USB_ISTR register *******************/ 05618 #define USB_ISTR_EP_ID ((uint16_t)0x000F) 05619 #define USB_ISTR_DIR ((uint16_t)0x0010) 05620 #define USB_ISTR_ESOF ((uint16_t)0x0100) 05621 #define USB_ISTR_SOF ((uint16_t)0x0200) 05622 #define USB_ISTR_RESET ((uint16_t)0x0400) 05623 #define USB_ISTR_SUSP ((uint16_t)0x0800) 05624 #define USB_ISTR_WKUP ((uint16_t)0x1000) 05625 #define USB_ISTR_ERR ((uint16_t)0x2000) 05626 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) 05627 #define USB_ISTR_CTR ((uint16_t)0x8000) 05629 /******************* Bit definition for USB_FNR register ********************/ 05630 #define USB_FNR_FN ((uint16_t)0x07FF) 05631 #define USB_FNR_LSOF ((uint16_t)0x1800) 05632 #define USB_FNR_LCK ((uint16_t)0x2000) 05633 #define USB_FNR_RXDM ((uint16_t)0x4000) 05634 #define USB_FNR_RXDP ((uint16_t)0x8000) 05636 /****************** Bit definition for USB_DADDR register *******************/ 05637 #define USB_DADDR_ADD ((uint8_t)0x7F) 05638 #define USB_DADDR_ADD0 ((uint8_t)0x01) 05639 #define USB_DADDR_ADD1 ((uint8_t)0x02) 05640 #define USB_DADDR_ADD2 ((uint8_t)0x04) 05641 #define USB_DADDR_ADD3 ((uint8_t)0x08) 05642 #define USB_DADDR_ADD4 ((uint8_t)0x10) 05643 #define USB_DADDR_ADD5 ((uint8_t)0x20) 05644 #define USB_DADDR_ADD6 ((uint8_t)0x40) 05646 #define USB_DADDR_EF ((uint8_t)0x80) 05648 /****************** Bit definition for USB_BTABLE register ******************/ 05649 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) 05652 /***************** Bit definition for USB_ADDR0_TX register *****************/ 05653 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) 05655 /***************** Bit definition for USB_ADDR1_TX register *****************/ 05656 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) 05658 /***************** Bit definition for USB_ADDR2_TX register *****************/ 05659 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) 05661 /***************** Bit definition for USB_ADDR3_TX register *****************/ 05662 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) 05664 /***************** Bit definition for USB_ADDR4_TX register *****************/ 05665 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) 05667 /***************** Bit definition for USB_ADDR5_TX register *****************/ 05668 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) 05670 /***************** Bit definition for USB_ADDR6_TX register *****************/ 05671 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) 05673 /***************** Bit definition for USB_ADDR7_TX register *****************/ 05674 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) 05676 /*----------------------------------------------------------------------------*/ 05677 05678 /***************** Bit definition for USB_COUNT0_TX register ****************/ 05679 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) 05681 /***************** Bit definition for USB_COUNT1_TX register ****************/ 05682 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) 05684 /***************** Bit definition for USB_COUNT2_TX register ****************/ 05685 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) 05687 /***************** Bit definition for USB_COUNT3_TX register ****************/ 05688 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) 05690 /***************** Bit definition for USB_COUNT4_TX register ****************/ 05691 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) 05693 /***************** Bit definition for USB_COUNT5_TX register ****************/ 05694 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) 05696 /***************** Bit definition for USB_COUNT6_TX register ****************/ 05697 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) 05699 /***************** Bit definition for USB_COUNT7_TX register ****************/ 05700 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) 05702 /*----------------------------------------------------------------------------*/ 05703 05704 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/ 05705 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) 05707 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/ 05708 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) 05710 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/ 05711 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) 05713 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/ 05714 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) 05716 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/ 05717 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) 05719 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/ 05720 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) 05722 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/ 05723 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) 05725 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/ 05726 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) 05728 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/ 05729 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) 05731 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/ 05732 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) 05734 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/ 05735 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) 05737 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/ 05738 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) 05740 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/ 05741 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) 05743 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/ 05744 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) 05746 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/ 05747 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) 05749 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/ 05750 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) 05752 /*----------------------------------------------------------------------------*/ 05753 05754 /***************** Bit definition for USB_ADDR0_RX register *****************/ 05755 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) 05757 /***************** Bit definition for USB_ADDR1_RX register *****************/ 05758 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) 05760 /***************** Bit definition for USB_ADDR2_RX register *****************/ 05761 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) 05763 /***************** Bit definition for USB_ADDR3_RX register *****************/ 05764 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) 05766 /***************** Bit definition for USB_ADDR4_RX register *****************/ 05767 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) 05769 /***************** Bit definition for USB_ADDR5_RX register *****************/ 05770 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) 05772 /***************** Bit definition for USB_ADDR6_RX register *****************/ 05773 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) 05775 /***************** Bit definition for USB_ADDR7_RX register *****************/ 05776 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) 05778 /*----------------------------------------------------------------------------*/ 05779 05780 /***************** Bit definition for USB_COUNT0_RX register ****************/ 05781 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) 05783 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) 05784 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05785 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05786 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05787 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05788 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05790 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) 05792 /***************** Bit definition for USB_COUNT1_RX register ****************/ 05793 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) 05795 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) 05796 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05797 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05798 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05799 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05800 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05802 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) 05804 /***************** Bit definition for USB_COUNT2_RX register ****************/ 05805 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) 05807 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) 05808 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05809 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05810 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05811 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05812 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05814 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) 05816 /***************** Bit definition for USB_COUNT3_RX register ****************/ 05817 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) 05819 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) 05820 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05821 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05822 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05823 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05824 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05826 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) 05828 /***************** Bit definition for USB_COUNT4_RX register ****************/ 05829 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) 05831 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) 05832 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05833 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05834 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05835 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05836 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05838 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) 05840 /***************** Bit definition for USB_COUNT5_RX register ****************/ 05841 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) 05843 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) 05844 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05845 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05846 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05847 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05848 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05850 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) 05852 /***************** Bit definition for USB_COUNT6_RX register ****************/ 05853 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) 05855 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) 05856 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05857 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05858 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05859 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05860 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05862 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) 05864 /***************** Bit definition for USB_COUNT7_RX register ****************/ 05865 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) 05867 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) 05868 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) 05869 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) 05870 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) 05871 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) 05872 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) 05874 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) 05876 /*----------------------------------------------------------------------------*/ 05877 05878 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/ 05879 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) 05881 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05882 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05883 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05884 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05885 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05886 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05888 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05890 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/ 05891 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) 05893 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05894 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05895 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05896 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05897 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05898 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05900 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05902 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/ 05903 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) 05905 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05906 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05907 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05908 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05909 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05910 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05912 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05914 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/ 05915 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) 05917 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05918 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05919 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05920 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05921 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05922 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05924 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05926 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/ 05927 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) 05929 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05930 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05931 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05932 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05933 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05934 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05936 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05938 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/ 05939 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) 05941 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05942 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05943 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05944 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05945 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05946 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05948 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05950 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/ 05951 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) 05953 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05954 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05955 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05956 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05957 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05958 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05960 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05962 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/ 05963 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) 05965 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05966 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05967 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05968 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05969 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05970 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05972 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05974 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/ 05975 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) 05977 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 05978 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 05979 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 05980 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 05981 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 05982 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 05984 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 05986 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/ 05987 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) 05989 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 05990 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 05991 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 05992 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 05993 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 05994 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 05996 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 05998 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/ 05999 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) 06001 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06002 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06003 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06004 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06005 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06006 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06008 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06010 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/ 06011 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) 06013 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06014 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06015 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06016 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06017 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06018 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06020 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06022 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/ 06023 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) 06025 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06026 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06027 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06028 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06029 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06030 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06032 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06034 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/ 06035 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) 06037 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06038 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06039 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06040 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06041 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06042 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06044 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06046 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/ 06047 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) 06049 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) 06050 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) 06051 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) 06052 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) 06053 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) 06054 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) 06056 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) 06058 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/ 06059 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) 06061 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) 06062 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) 06063 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) 06064 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) 06065 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) 06066 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) 06068 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) 06070 /******************************************************************************/ 06071 /* */ 06072 /* Controller Area Network */ 06073 /* */ 06074 /******************************************************************************/ 06075 06077 /******************* Bit definition for CAN_MCR register ********************/ 06078 #define CAN_MCR_INRQ ((uint16_t)0x0001) 06079 #define CAN_MCR_SLEEP ((uint16_t)0x0002) 06080 #define CAN_MCR_TXFP ((uint16_t)0x0004) 06081 #define CAN_MCR_RFLM ((uint16_t)0x0008) 06082 #define CAN_MCR_NART ((uint16_t)0x0010) 06083 #define CAN_MCR_AWUM ((uint16_t)0x0020) 06084 #define CAN_MCR_ABOM ((uint16_t)0x0040) 06085 #define CAN_MCR_TTCM ((uint16_t)0x0080) 06086 #define CAN_MCR_RESET ((uint16_t)0x8000) 06088 /******************* Bit definition for CAN_MSR register ********************/ 06089 #define CAN_MSR_INAK ((uint16_t)0x0001) 06090 #define CAN_MSR_SLAK ((uint16_t)0x0002) 06091 #define CAN_MSR_ERRI ((uint16_t)0x0004) 06092 #define CAN_MSR_WKUI ((uint16_t)0x0008) 06093 #define CAN_MSR_SLAKI ((uint16_t)0x0010) 06094 #define CAN_MSR_TXM ((uint16_t)0x0100) 06095 #define CAN_MSR_RXM ((uint16_t)0x0200) 06096 #define CAN_MSR_SAMP ((uint16_t)0x0400) 06097 #define CAN_MSR_RX ((uint16_t)0x0800) 06099 /******************* Bit definition for CAN_TSR register ********************/ 06100 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) 06101 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) 06102 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) 06103 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) 06104 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) 06105 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) 06106 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) 06107 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) 06108 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) 06109 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) 06110 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) 06111 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) 06112 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) 06113 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) 06114 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) 06115 #define CAN_TSR_CODE ((uint32_t)0x03000000) 06117 #define CAN_TSR_TME ((uint32_t)0x1C000000) 06118 #define CAN_TSR_TME0 ((uint32_t)0x04000000) 06119 #define CAN_TSR_TME1 ((uint32_t)0x08000000) 06120 #define CAN_TSR_TME2 ((uint32_t)0x10000000) 06122 #define CAN_TSR_LOW ((uint32_t)0xE0000000) 06123 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) 06124 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) 06125 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) 06127 /******************* Bit definition for CAN_RF0R register *******************/ 06128 #define CAN_RF0R_FMP0 ((uint8_t)0x03) 06129 #define CAN_RF0R_FULL0 ((uint8_t)0x08) 06130 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) 06131 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) 06133 /******************* Bit definition for CAN_RF1R register *******************/ 06134 #define CAN_RF1R_FMP1 ((uint8_t)0x03) 06135 #define CAN_RF1R_FULL1 ((uint8_t)0x08) 06136 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) 06137 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) 06139 /******************** Bit definition for CAN_IER register *******************/ 06140 #define CAN_IER_TMEIE ((uint32_t)0x00000001) 06141 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) 06142 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) 06143 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) 06144 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) 06145 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) 06146 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) 06147 #define CAN_IER_EWGIE ((uint32_t)0x00000100) 06148 #define CAN_IER_EPVIE ((uint32_t)0x00000200) 06149 #define CAN_IER_BOFIE ((uint32_t)0x00000400) 06150 #define CAN_IER_LECIE ((uint32_t)0x00000800) 06151 #define CAN_IER_ERRIE ((uint32_t)0x00008000) 06152 #define CAN_IER_WKUIE ((uint32_t)0x00010000) 06153 #define CAN_IER_SLKIE ((uint32_t)0x00020000) 06155 /******************** Bit definition for CAN_ESR register *******************/ 06156 #define CAN_ESR_EWGF ((uint32_t)0x00000001) 06157 #define CAN_ESR_EPVF ((uint32_t)0x00000002) 06158 #define CAN_ESR_BOFF ((uint32_t)0x00000004) 06160 #define CAN_ESR_LEC ((uint32_t)0x00000070) 06161 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) 06162 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) 06163 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) 06165 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) 06166 #define CAN_ESR_REC ((uint32_t)0xFF000000) 06168 /******************* Bit definition for CAN_BTR register ********************/ 06169 #define CAN_BTR_BRP ((uint32_t)0x000003FF) 06170 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) 06171 #define CAN_BTR_TS2 ((uint32_t)0x00700000) 06172 #define CAN_BTR_SJW ((uint32_t)0x03000000) 06173 #define CAN_BTR_LBKM ((uint32_t)0x40000000) 06174 #define CAN_BTR_SILM ((uint32_t)0x80000000) 06177 /****************** Bit definition for CAN_TI0R register ********************/ 06178 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) 06179 #define CAN_TI0R_RTR ((uint32_t)0x00000002) 06180 #define CAN_TI0R_IDE ((uint32_t)0x00000004) 06181 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) 06182 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) 06184 /****************** Bit definition for CAN_TDT0R register *******************/ 06185 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) 06186 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) 06187 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) 06189 /****************** Bit definition for CAN_TDL0R register *******************/ 06190 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) 06191 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) 06192 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) 06193 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) 06195 /****************** Bit definition for CAN_TDH0R register *******************/ 06196 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) 06197 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) 06198 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) 06199 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) 06201 /******************* Bit definition for CAN_TI1R register *******************/ 06202 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) 06203 #define CAN_TI1R_RTR ((uint32_t)0x00000002) 06204 #define CAN_TI1R_IDE ((uint32_t)0x00000004) 06205 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) 06206 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) 06208 /******************* Bit definition for CAN_TDT1R register ******************/ 06209 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) 06210 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) 06211 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) 06213 /******************* Bit definition for CAN_TDL1R register ******************/ 06214 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) 06215 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) 06216 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) 06217 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) 06219 /******************* Bit definition for CAN_TDH1R register ******************/ 06220 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) 06221 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) 06222 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) 06223 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) 06225 /******************* Bit definition for CAN_TI2R register *******************/ 06226 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) 06227 #define CAN_TI2R_RTR ((uint32_t)0x00000002) 06228 #define CAN_TI2R_IDE ((uint32_t)0x00000004) 06229 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) 06230 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) 06232 /******************* Bit definition for CAN_TDT2R register ******************/ 06233 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) 06234 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) 06235 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) 06237 /******************* Bit definition for CAN_TDL2R register ******************/ 06238 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) 06239 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) 06240 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) 06241 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) 06243 /******************* Bit definition for CAN_TDH2R register ******************/ 06244 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) 06245 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) 06246 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) 06247 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) 06249 /******************* Bit definition for CAN_RI0R register *******************/ 06250 #define CAN_RI0R_RTR ((uint32_t)0x00000002) 06251 #define CAN_RI0R_IDE ((uint32_t)0x00000004) 06252 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) 06253 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) 06255 /******************* Bit definition for CAN_RDT0R register ******************/ 06256 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) 06257 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) 06258 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) 06260 /******************* Bit definition for CAN_RDL0R register ******************/ 06261 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) 06262 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) 06263 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) 06264 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) 06266 /******************* Bit definition for CAN_RDH0R register ******************/ 06267 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) 06268 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) 06269 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) 06270 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) 06272 /******************* Bit definition for CAN_RI1R register *******************/ 06273 #define CAN_RI1R_RTR ((uint32_t)0x00000002) 06274 #define CAN_RI1R_IDE ((uint32_t)0x00000004) 06275 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) 06276 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) 06278 /******************* Bit definition for CAN_RDT1R register ******************/ 06279 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) 06280 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) 06281 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) 06283 /******************* Bit definition for CAN_RDL1R register ******************/ 06284 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) 06285 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) 06286 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) 06287 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) 06289 /******************* Bit definition for CAN_RDH1R register ******************/ 06290 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) 06291 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) 06292 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) 06293 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) 06296 /******************* Bit definition for CAN_FMR register ********************/ 06297 #define CAN_FMR_FINIT ((uint8_t)0x01) 06299 /******************* Bit definition for CAN_FM1R register *******************/ 06300 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) 06301 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) 06302 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) 06303 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) 06304 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) 06305 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) 06306 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) 06307 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) 06308 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) 06309 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) 06310 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) 06311 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) 06312 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) 06313 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) 06314 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) 06316 /******************* Bit definition for CAN_FS1R register *******************/ 06317 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) 06318 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) 06319 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) 06320 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) 06321 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) 06322 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) 06323 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) 06324 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) 06325 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) 06326 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) 06327 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) 06328 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) 06329 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) 06330 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) 06331 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) 06333 /****************** Bit definition for CAN_FFA1R register *******************/ 06334 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) 06335 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) 06336 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) 06337 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) 06338 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) 06339 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) 06340 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) 06341 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) 06342 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) 06343 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) 06344 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) 06345 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) 06346 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) 06347 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) 06348 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) 06350 /******************* Bit definition for CAN_FA1R register *******************/ 06351 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) 06352 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) 06353 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) 06354 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) 06355 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) 06356 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) 06357 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) 06358 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) 06359 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) 06360 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) 06361 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) 06362 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) 06363 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) 06364 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) 06365 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) 06367 /******************* Bit definition for CAN_F0R1 register *******************/ 06368 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) 06369 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) 06370 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) 06371 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) 06372 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) 06373 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) 06374 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) 06375 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) 06376 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) 06377 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) 06378 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) 06379 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) 06380 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) 06381 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) 06382 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) 06383 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) 06384 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) 06385 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) 06386 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) 06387 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) 06388 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) 06389 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) 06390 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) 06391 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) 06392 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) 06393 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) 06394 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) 06395 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) 06396 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) 06397 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) 06398 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) 06399 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) 06401 /******************* Bit definition for CAN_F1R1 register *******************/ 06402 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) 06403 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) 06404 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) 06405 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) 06406 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) 06407 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) 06408 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) 06409 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) 06410 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) 06411 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) 06412 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) 06413 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) 06414 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) 06415 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) 06416 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) 06417 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) 06418 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) 06419 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) 06420 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) 06421 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) 06422 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) 06423 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) 06424 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) 06425 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) 06426 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) 06427 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) 06428 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) 06429 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) 06430 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) 06431 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) 06432 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) 06433 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) 06435 /******************* Bit definition for CAN_F2R1 register *******************/ 06436 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) 06437 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) 06438 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) 06439 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) 06440 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) 06441 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) 06442 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) 06443 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) 06444 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) 06445 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) 06446 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) 06447 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) 06448 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) 06449 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) 06450 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) 06451 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) 06452 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) 06453 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) 06454 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) 06455 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) 06456 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) 06457 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) 06458 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) 06459 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) 06460 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) 06461 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) 06462 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) 06463 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) 06464 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) 06465 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) 06466 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) 06467 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) 06469 /******************* Bit definition for CAN_F3R1 register *******************/ 06470 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) 06471 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) 06472 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) 06473 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) 06474 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) 06475 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) 06476 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) 06477 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) 06478 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) 06479 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) 06480 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) 06481 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) 06482 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) 06483 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) 06484 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) 06485 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) 06486 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) 06487 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) 06488 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) 06489 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) 06490 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) 06491 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) 06492 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) 06493 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) 06494 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) 06495 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) 06496 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) 06497 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) 06498 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) 06499 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) 06500 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) 06501 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) 06503 /******************* Bit definition for CAN_F4R1 register *******************/ 06504 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) 06505 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) 06506 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) 06507 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) 06508 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) 06509 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) 06510 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) 06511 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) 06512 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) 06513 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) 06514 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) 06515 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) 06516 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) 06517 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) 06518 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) 06519 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) 06520 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) 06521 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) 06522 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) 06523 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) 06524 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) 06525 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) 06526 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) 06527 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) 06528 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) 06529 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) 06530 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) 06531 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) 06532 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) 06533 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) 06534 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) 06535 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) 06537 /******************* Bit definition for CAN_F5R1 register *******************/ 06538 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) 06539 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) 06540 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) 06541 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) 06542 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) 06543 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) 06544 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) 06545 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) 06546 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) 06547 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) 06548 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) 06549 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) 06550 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) 06551 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) 06552 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) 06553 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) 06554 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) 06555 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) 06556 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) 06557 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) 06558 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) 06559 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) 06560 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) 06561 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) 06562 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) 06563 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) 06564 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) 06565 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) 06566 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) 06567 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) 06568 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) 06569 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) 06571 /******************* Bit definition for CAN_F6R1 register *******************/ 06572 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) 06573 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) 06574 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) 06575 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) 06576 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) 06577 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) 06578 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) 06579 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) 06580 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) 06581 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) 06582 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) 06583 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) 06584 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) 06585 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) 06586 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) 06587 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) 06588 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) 06589 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) 06590 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) 06591 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) 06592 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) 06593 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) 06594 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) 06595 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) 06596 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) 06597 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) 06598 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) 06599 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) 06600 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) 06601 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) 06602 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) 06603 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) 06605 /******************* Bit definition for CAN_F7R1 register *******************/ 06606 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) 06607 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) 06608 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) 06609 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) 06610 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) 06611 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) 06612 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) 06613 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) 06614 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) 06615 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) 06616 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) 06617 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) 06618 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) 06619 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) 06620 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) 06621 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) 06622 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) 06623 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) 06624 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) 06625 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) 06626 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) 06627 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) 06628 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) 06629 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) 06630 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) 06631 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) 06632 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) 06633 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) 06634 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) 06635 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) 06636 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) 06637 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) 06639 /******************* Bit definition for CAN_F8R1 register *******************/ 06640 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) 06641 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) 06642 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) 06643 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) 06644 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) 06645 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) 06646 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) 06647 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) 06648 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) 06649 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) 06650 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) 06651 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) 06652 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) 06653 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) 06654 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) 06655 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) 06656 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) 06657 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) 06658 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) 06659 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) 06660 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) 06661 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) 06662 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) 06663 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) 06664 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) 06665 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) 06666 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) 06667 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) 06668 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) 06669 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) 06670 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) 06671 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) 06673 /******************* Bit definition for CAN_F9R1 register *******************/ 06674 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) 06675 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) 06676 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) 06677 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) 06678 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) 06679 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) 06680 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) 06681 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) 06682 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) 06683 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) 06684 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) 06685 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) 06686 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) 06687 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) 06688 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) 06689 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) 06690 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) 06691 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) 06692 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) 06693 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) 06694 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) 06695 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) 06696 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) 06697 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) 06698 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) 06699 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) 06700 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) 06701 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) 06702 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) 06703 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) 06704 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) 06705 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) 06707 /******************* Bit definition for CAN_F10R1 register ******************/ 06708 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) 06709 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) 06710 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) 06711 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) 06712 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) 06713 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) 06714 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) 06715 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) 06716 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) 06717 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) 06718 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) 06719 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) 06720 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) 06721 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) 06722 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) 06723 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) 06724 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) 06725 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) 06726 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) 06727 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) 06728 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) 06729 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) 06730 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) 06731 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) 06732 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) 06733 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) 06734 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) 06735 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) 06736 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) 06737 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) 06738 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) 06739 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) 06741 /******************* Bit definition for CAN_F11R1 register ******************/ 06742 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) 06743 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) 06744 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) 06745 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) 06746 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) 06747 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) 06748 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) 06749 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) 06750 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) 06751 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) 06752 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) 06753 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) 06754 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) 06755 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) 06756 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) 06757 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) 06758 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) 06759 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) 06760 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) 06761 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) 06762 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) 06763 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) 06764 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) 06765 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) 06766 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) 06767 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) 06768 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) 06769 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) 06770 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) 06771 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) 06772 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) 06773 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) 06775 /******************* Bit definition for CAN_F12R1 register ******************/ 06776 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) 06777 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) 06778 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) 06779 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) 06780 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) 06781 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) 06782 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) 06783 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) 06784 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) 06785 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) 06786 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) 06787 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) 06788 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) 06789 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) 06790 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) 06791 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) 06792 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) 06793 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) 06794 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) 06795 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) 06796 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) 06797 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) 06798 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) 06799 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) 06800 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) 06801 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) 06802 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) 06803 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) 06804 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) 06805 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) 06806 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) 06807 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) 06809 /******************* Bit definition for CAN_F13R1 register ******************/ 06810 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) 06811 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) 06812 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) 06813 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) 06814 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) 06815 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) 06816 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) 06817 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) 06818 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) 06819 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) 06820 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) 06821 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) 06822 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) 06823 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) 06824 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) 06825 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) 06826 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) 06827 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) 06828 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) 06829 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) 06830 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) 06831 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) 06832 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) 06833 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) 06834 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) 06835 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) 06836 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) 06837 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) 06838 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) 06839 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) 06840 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) 06841 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) 06843 /******************* Bit definition for CAN_F0R2 register *******************/ 06844 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) 06845 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) 06846 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) 06847 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) 06848 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) 06849 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) 06850 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) 06851 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) 06852 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) 06853 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) 06854 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) 06855 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) 06856 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) 06857 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) 06858 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) 06859 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) 06860 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) 06861 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) 06862 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) 06863 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) 06864 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) 06865 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) 06866 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) 06867 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) 06868 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) 06869 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) 06870 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) 06871 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) 06872 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) 06873 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) 06874 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) 06875 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) 06877 /******************* Bit definition for CAN_F1R2 register *******************/ 06878 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) 06879 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) 06880 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) 06881 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) 06882 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) 06883 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) 06884 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) 06885 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) 06886 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) 06887 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) 06888 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) 06889 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) 06890 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) 06891 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) 06892 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) 06893 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) 06894 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) 06895 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) 06896 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) 06897 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) 06898 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) 06899 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) 06900 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) 06901 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) 06902 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) 06903 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) 06904 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) 06905 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) 06906 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) 06907 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) 06908 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) 06909 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) 06911 /******************* Bit definition for CAN_F2R2 register *******************/ 06912 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) 06913 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) 06914 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) 06915 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) 06916 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) 06917 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) 06918 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) 06919 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) 06920 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) 06921 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) 06922 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) 06923 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) 06924 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) 06925 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) 06926 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) 06927 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) 06928 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) 06929 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) 06930 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) 06931 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) 06932 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) 06933 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) 06934 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) 06935 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) 06936 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) 06937 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) 06938 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) 06939 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) 06940 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) 06941 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) 06942 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) 06943 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) 06945 /******************* Bit definition for CAN_F3R2 register *******************/ 06946 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) 06947 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) 06948 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) 06949 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) 06950 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) 06951 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) 06952 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) 06953 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) 06954 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) 06955 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) 06956 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) 06957 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) 06958 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) 06959 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) 06960 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) 06961 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) 06962 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) 06963 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) 06964 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) 06965 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) 06966 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) 06967 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) 06968 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) 06969 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) 06970 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) 06971 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) 06972 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) 06973 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) 06974 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) 06975 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) 06976 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) 06977 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) 06979 /******************* Bit definition for CAN_F4R2 register *******************/ 06980 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) 06981 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) 06982 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) 06983 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) 06984 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) 06985 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) 06986 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) 06987 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) 06988 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) 06989 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) 06990 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) 06991 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) 06992 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) 06993 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) 06994 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) 06995 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) 06996 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) 06997 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) 06998 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) 06999 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) 07000 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) 07001 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) 07002 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) 07003 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) 07004 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) 07005 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) 07006 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) 07007 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) 07008 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) 07009 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) 07010 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) 07011 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) 07013 /******************* Bit definition for CAN_F5R2 register *******************/ 07014 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) 07015 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) 07016 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) 07017 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) 07018 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) 07019 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) 07020 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) 07021 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) 07022 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) 07023 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) 07024 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) 07025 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) 07026 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) 07027 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) 07028 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) 07029 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) 07030 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) 07031 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) 07032 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) 07033 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) 07034 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) 07035 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) 07036 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) 07037 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) 07038 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) 07039 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) 07040 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) 07041 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) 07042 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) 07043 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) 07044 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) 07045 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) 07047 /******************* Bit definition for CAN_F6R2 register *******************/ 07048 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) 07049 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) 07050 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) 07051 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) 07052 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) 07053 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) 07054 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) 07055 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) 07056 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) 07057 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) 07058 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) 07059 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) 07060 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) 07061 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) 07062 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) 07063 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) 07064 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) 07065 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) 07066 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) 07067 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) 07068 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) 07069 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) 07070 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) 07071 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) 07072 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) 07073 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) 07074 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) 07075 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) 07076 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) 07077 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) 07078 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) 07079 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) 07081 /******************* Bit definition for CAN_F7R2 register *******************/ 07082 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) 07083 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) 07084 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) 07085 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) 07086 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) 07087 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) 07088 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) 07089 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) 07090 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) 07091 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) 07092 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) 07093 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) 07094 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) 07095 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) 07096 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) 07097 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) 07098 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) 07099 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) 07100 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) 07101 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) 07102 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) 07103 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) 07104 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) 07105 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) 07106 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) 07107 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) 07108 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) 07109 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) 07110 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) 07111 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) 07112 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) 07113 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) 07115 /******************* Bit definition for CAN_F8R2 register *******************/ 07116 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) 07117 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) 07118 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) 07119 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) 07120 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) 07121 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) 07122 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) 07123 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) 07124 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) 07125 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) 07126 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) 07127 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) 07128 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) 07129 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) 07130 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) 07131 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) 07132 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) 07133 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) 07134 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) 07135 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) 07136 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) 07137 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) 07138 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) 07139 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) 07140 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) 07141 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) 07142 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) 07143 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) 07144 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) 07145 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) 07146 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) 07147 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) 07149 /******************* Bit definition for CAN_F9R2 register *******************/ 07150 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) 07151 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) 07152 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) 07153 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) 07154 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) 07155 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) 07156 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) 07157 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) 07158 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) 07159 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) 07160 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) 07161 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) 07162 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) 07163 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) 07164 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) 07165 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) 07166 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) 07167 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) 07168 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) 07169 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) 07170 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) 07171 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) 07172 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) 07173 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) 07174 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) 07175 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) 07176 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) 07177 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) 07178 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) 07179 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) 07180 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) 07181 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) 07183 /******************* Bit definition for CAN_F10R2 register ******************/ 07184 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) 07185 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) 07186 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) 07187 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) 07188 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) 07189 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) 07190 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) 07191 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) 07192 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) 07193 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) 07194 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) 07195 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) 07196 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) 07197 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) 07198 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) 07199 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) 07200 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) 07201 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) 07202 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) 07203 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) 07204 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) 07205 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) 07206 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) 07207 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) 07208 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) 07209 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) 07210 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) 07211 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) 07212 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) 07213 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) 07214 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) 07215 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) 07217 /******************* Bit definition for CAN_F11R2 register ******************/ 07218 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) 07219 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) 07220 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) 07221 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) 07222 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) 07223 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) 07224 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) 07225 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) 07226 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) 07227 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) 07228 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) 07229 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) 07230 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) 07231 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) 07232 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) 07233 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) 07234 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) 07235 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) 07236 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) 07237 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) 07238 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) 07239 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) 07240 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) 07241 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) 07242 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) 07243 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) 07244 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) 07245 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) 07246 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) 07247 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) 07248 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) 07249 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) 07251 /******************* Bit definition for CAN_F12R2 register ******************/ 07252 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) 07253 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) 07254 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) 07255 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) 07256 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) 07257 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) 07258 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) 07259 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) 07260 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) 07261 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) 07262 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) 07263 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) 07264 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) 07265 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) 07266 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) 07267 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) 07268 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) 07269 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) 07270 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) 07271 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) 07272 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) 07273 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) 07274 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) 07275 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) 07276 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) 07277 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) 07278 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) 07279 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) 07280 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) 07281 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) 07282 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) 07283 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) 07285 /******************* Bit definition for CAN_F13R2 register ******************/ 07286 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) 07287 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) 07288 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) 07289 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) 07290 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) 07291 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) 07292 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) 07293 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) 07294 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) 07295 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) 07296 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) 07297 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) 07298 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) 07299 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) 07300 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) 07301 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) 07302 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) 07303 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) 07304 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) 07305 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) 07306 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) 07307 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) 07308 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) 07309 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) 07310 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) 07311 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) 07312 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) 07313 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) 07314 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) 07315 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) 07316 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) 07317 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) 07319 /******************************************************************************/ 07320 /* */ 07321 /* Serial Peripheral Interface */ 07322 /* */ 07323 /******************************************************************************/ 07324 07325 /******************* Bit definition for SPI_CR1 register ********************/ 07326 #define SPI_CR1_CPHA ((uint16_t)0x0001) 07327 #define SPI_CR1_CPOL ((uint16_t)0x0002) 07328 #define SPI_CR1_MSTR ((uint16_t)0x0004) 07330 #define SPI_CR1_BR ((uint16_t)0x0038) 07331 #define SPI_CR1_BR_0 ((uint16_t)0x0008) 07332 #define SPI_CR1_BR_1 ((uint16_t)0x0010) 07333 #define SPI_CR1_BR_2 ((uint16_t)0x0020) 07335 #define SPI_CR1_SPE ((uint16_t)0x0040) 07336 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) 07337 #define SPI_CR1_SSI ((uint16_t)0x0100) 07338 #define SPI_CR1_SSM ((uint16_t)0x0200) 07339 #define SPI_CR1_RXONLY ((uint16_t)0x0400) 07340 #define SPI_CR1_DFF ((uint16_t)0x0800) 07341 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) 07342 #define SPI_CR1_CRCEN ((uint16_t)0x2000) 07343 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) 07344 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) 07346 /******************* Bit definition for SPI_CR2 register ********************/ 07347 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) 07348 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) 07349 #define SPI_CR2_SSOE ((uint8_t)0x04) 07350 #define SPI_CR2_ERRIE ((uint8_t)0x20) 07351 #define SPI_CR2_RXNEIE ((uint8_t)0x40) 07352 #define SPI_CR2_TXEIE ((uint8_t)0x80) 07354 /******************** Bit definition for SPI_SR register ********************/ 07355 #define SPI_SR_RXNE ((uint8_t)0x01) 07356 #define SPI_SR_TXE ((uint8_t)0x02) 07357 #define SPI_SR_CHSIDE ((uint8_t)0x04) 07358 #define SPI_SR_UDR ((uint8_t)0x08) 07359 #define SPI_SR_CRCERR ((uint8_t)0x10) 07360 #define SPI_SR_MODF ((uint8_t)0x20) 07361 #define SPI_SR_OVR ((uint8_t)0x40) 07362 #define SPI_SR_BSY ((uint8_t)0x80) 07364 /******************** Bit definition for SPI_DR register ********************/ 07365 #define SPI_DR_DR ((uint16_t)0xFFFF) 07367 /******************* Bit definition for SPI_CRCPR register ******************/ 07368 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) 07370 /****************** Bit definition for SPI_RXCRCR register ******************/ 07371 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) 07373 /****************** Bit definition for SPI_TXCRCR register ******************/ 07374 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) 07376 /****************** Bit definition for SPI_I2SCFGR register *****************/ 07377 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) 07379 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) 07380 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) 07381 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) 07383 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) 07385 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) 07386 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) 07387 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) 07389 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) 07391 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) 07392 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) 07393 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) 07395 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) 07396 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) 07398 /****************** Bit definition for SPI_I2SPR register *******************/ 07399 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) 07400 #define SPI_I2SPR_ODD ((uint16_t)0x0100) 07401 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) 07403 /******************************************************************************/ 07404 /* */ 07405 /* Inter-integrated Circuit Interface */ 07406 /* */ 07407 /******************************************************************************/ 07408 07409 /******************* Bit definition for I2C_CR1 register ********************/ 07410 #define I2C_CR1_PE ((uint16_t)0x0001) 07411 #define I2C_CR1_SMBUS ((uint16_t)0x0002) 07412 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) 07413 #define I2C_CR1_ENARP ((uint16_t)0x0010) 07414 #define I2C_CR1_ENPEC ((uint16_t)0x0020) 07415 #define I2C_CR1_ENGC ((uint16_t)0x0040) 07416 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) 07417 #define I2C_CR1_START ((uint16_t)0x0100) 07418 #define I2C_CR1_STOP ((uint16_t)0x0200) 07419 #define I2C_CR1_ACK ((uint16_t)0x0400) 07420 #define I2C_CR1_POS ((uint16_t)0x0800) 07421 #define I2C_CR1_PEC ((uint16_t)0x1000) 07422 #define I2C_CR1_ALERT ((uint16_t)0x2000) 07423 #define I2C_CR1_SWRST ((uint16_t)0x8000) 07425 /******************* Bit definition for I2C_CR2 register ********************/ 07426 #define I2C_CR2_FREQ ((uint16_t)0x003F) 07427 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) 07428 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) 07429 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) 07430 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) 07431 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) 07432 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) 07434 #define I2C_CR2_ITERREN ((uint16_t)0x0100) 07435 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) 07436 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) 07437 #define I2C_CR2_DMAEN ((uint16_t)0x0800) 07438 #define I2C_CR2_LAST ((uint16_t)0x1000) 07440 /******************* Bit definition for I2C_OAR1 register *******************/ 07441 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) 07442 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) 07444 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) 07445 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) 07446 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) 07447 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) 07448 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) 07449 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) 07450 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) 07451 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) 07452 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) 07453 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) 07455 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) 07457 /******************* Bit definition for I2C_OAR2 register *******************/ 07458 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) 07459 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) 07461 /******************** Bit definition for I2C_DR register ********************/ 07462 #define I2C_DR_DR ((uint8_t)0xFF) 07464 /******************* Bit definition for I2C_SR1 register ********************/ 07465 #define I2C_SR1_SB ((uint16_t)0x0001) 07466 #define I2C_SR1_ADDR ((uint16_t)0x0002) 07467 #define I2C_SR1_BTF ((uint16_t)0x0004) 07468 #define I2C_SR1_ADD10 ((uint16_t)0x0008) 07469 #define I2C_SR1_STOPF ((uint16_t)0x0010) 07470 #define I2C_SR1_RXNE ((uint16_t)0x0040) 07471 #define I2C_SR1_TXE ((uint16_t)0x0080) 07472 #define I2C_SR1_BERR ((uint16_t)0x0100) 07473 #define I2C_SR1_ARLO ((uint16_t)0x0200) 07474 #define I2C_SR1_AF ((uint16_t)0x0400) 07475 #define I2C_SR1_OVR ((uint16_t)0x0800) 07476 #define I2C_SR1_PECERR ((uint16_t)0x1000) 07477 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) 07478 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) 07480 /******************* Bit definition for I2C_SR2 register ********************/ 07481 #define I2C_SR2_MSL ((uint16_t)0x0001) 07482 #define I2C_SR2_BUSY ((uint16_t)0x0002) 07483 #define I2C_SR2_TRA ((uint16_t)0x0004) 07484 #define I2C_SR2_GENCALL ((uint16_t)0x0010) 07485 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) 07486 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) 07487 #define I2C_SR2_DUALF ((uint16_t)0x0080) 07488 #define I2C_SR2_PEC ((uint16_t)0xFF00) 07490 /******************* Bit definition for I2C_CCR register ********************/ 07491 #define I2C_CCR_CCR ((uint16_t)0x0FFF) 07492 #define I2C_CCR_DUTY ((uint16_t)0x4000) 07493 #define I2C_CCR_FS ((uint16_t)0x8000) 07495 /****************** Bit definition for I2C_TRISE register *******************/ 07496 #define I2C_TRISE_TRISE ((uint8_t)0x3F) 07498 /******************************************************************************/ 07499 /* */ 07500 /* Universal Synchronous Asynchronous Receiver Transmitter */ 07501 /* */ 07502 /******************************************************************************/ 07503 07504 /******************* Bit definition for USART_SR register *******************/ 07505 #define USART_SR_PE ((uint16_t)0x0001) 07506 #define USART_SR_FE ((uint16_t)0x0002) 07507 #define USART_SR_NE ((uint16_t)0x0004) 07508 #define USART_SR_ORE ((uint16_t)0x0008) 07509 #define USART_SR_IDLE ((uint16_t)0x0010) 07510 #define USART_SR_RXNE ((uint16_t)0x0020) 07511 #define USART_SR_TC ((uint16_t)0x0040) 07512 #define USART_SR_TXE ((uint16_t)0x0080) 07513 #define USART_SR_LBD ((uint16_t)0x0100) 07514 #define USART_SR_CTS ((uint16_t)0x0200) 07516 /******************* Bit definition for USART_DR register *******************/ 07517 #define USART_DR_DR ((uint16_t)0x01FF) 07519 /****************** Bit definition for USART_BRR register *******************/ 07520 #define USART_BRR_DIV_Fraction ((uint16_t)0x000F) 07521 #define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) 07523 /****************** Bit definition for USART_CR1 register *******************/ 07524 #define USART_CR1_SBK ((uint16_t)0x0001) 07525 #define USART_CR1_RWU ((uint16_t)0x0002) 07526 #define USART_CR1_RE ((uint16_t)0x0004) 07527 #define USART_CR1_TE ((uint16_t)0x0008) 07528 #define USART_CR1_IDLEIE ((uint16_t)0x0010) 07529 #define USART_CR1_RXNEIE ((uint16_t)0x0020) 07530 #define USART_CR1_TCIE ((uint16_t)0x0040) 07531 #define USART_CR1_TXEIE ((uint16_t)0x0080) 07532 #define USART_CR1_PEIE ((uint16_t)0x0100) 07533 #define USART_CR1_PS ((uint16_t)0x0200) 07534 #define USART_CR1_PCE ((uint16_t)0x0400) 07535 #define USART_CR1_WAKE ((uint16_t)0x0800) 07536 #define USART_CR1_M ((uint16_t)0x1000) 07537 #define USART_CR1_UE ((uint16_t)0x2000) 07538 #define USART_CR1_OVER8 ((uint16_t)0x8000) 07540 /****************** Bit definition for USART_CR2 register *******************/ 07541 #define USART_CR2_ADD ((uint16_t)0x000F) 07542 #define USART_CR2_LBDL ((uint16_t)0x0020) 07543 #define USART_CR2_LBDIE ((uint16_t)0x0040) 07544 #define USART_CR2_LBCL ((uint16_t)0x0100) 07545 #define USART_CR2_CPHA ((uint16_t)0x0200) 07546 #define USART_CR2_CPOL ((uint16_t)0x0400) 07547 #define USART_CR2_CLKEN ((uint16_t)0x0800) 07549 #define USART_CR2_STOP ((uint16_t)0x3000) 07550 #define USART_CR2_STOP_0 ((uint16_t)0x1000) 07551 #define USART_CR2_STOP_1 ((uint16_t)0x2000) 07553 #define USART_CR2_LINEN ((uint16_t)0x4000) 07555 /****************** Bit definition for USART_CR3 register *******************/ 07556 #define USART_CR3_EIE ((uint16_t)0x0001) 07557 #define USART_CR3_IREN ((uint16_t)0x0002) 07558 #define USART_CR3_IRLP ((uint16_t)0x0004) 07559 #define USART_CR3_HDSEL ((uint16_t)0x0008) 07560 #define USART_CR3_NACK ((uint16_t)0x0010) 07561 #define USART_CR3_SCEN ((uint16_t)0x0020) 07562 #define USART_CR3_DMAR ((uint16_t)0x0040) 07563 #define USART_CR3_DMAT ((uint16_t)0x0080) 07564 #define USART_CR3_RTSE ((uint16_t)0x0100) 07565 #define USART_CR3_CTSE ((uint16_t)0x0200) 07566 #define USART_CR3_CTSIE ((uint16_t)0x0400) 07567 #define USART_CR3_ONEBIT ((uint16_t)0x0800) 07569 /****************** Bit definition for USART_GTPR register ******************/ 07570 #define USART_GTPR_PSC ((uint16_t)0x00FF) 07571 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) 07572 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) 07573 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) 07574 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) 07575 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) 07576 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) 07577 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) 07578 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) 07580 #define USART_GTPR_GT ((uint16_t)0xFF00) 07582 /******************************************************************************/ 07583 /* */ 07584 /* Debug MCU */ 07585 /* */ 07586 /******************************************************************************/ 07587 07588 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 07589 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) 07591 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) 07592 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) 07593 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) 07594 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) 07595 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) 07596 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) 07597 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) 07598 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) 07599 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) 07600 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) 07601 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) 07602 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) 07603 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) 07604 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) 07605 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) 07606 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) 07607 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) 07609 /****************** Bit definition for DBGMCU_CR register *******************/ 07610 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) 07611 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) 07612 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) 07613 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) 07615 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) 07616 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) 07617 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) 07619 #define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) 07620 #define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) 07621 #define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) 07622 #define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) 07623 #define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) 07624 #define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) 07625 #define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) 07626 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 07627 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 07628 #define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) 07629 #define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) 07630 #define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) 07631 #define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) 07632 #define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) 07633 #define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) 07634 #define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) 07635 #define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) 07636 #define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) 07637 #define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) 07638 #define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) 07639 #define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) 07640 #define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) 07641 #define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) 07643 /******************************************************************************/ 07644 /* */ 07645 /* FLASH and Option Bytes Registers */ 07646 /* */ 07647 /******************************************************************************/ 07648 07649 /******************* Bit definition for FLASH_ACR register ******************/ 07650 #define FLASH_ACR_LATENCY ((uint8_t)0x03) 07651 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) 07652 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) 07653 #define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) 07655 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) 07656 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) 07657 #define FLASH_ACR_PRFTBS ((uint8_t)0x20) 07659 /****************** Bit definition for FLASH_KEYR register ******************/ 07660 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) 07662 /***************** Bit definition for FLASH_OPTKEYR register ****************/ 07663 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) 07665 /****************** Bit definition for FLASH_SR register *******************/ 07666 #define FLASH_SR_BSY ((uint8_t)0x01) 07667 #define FLASH_SR_PGERR ((uint8_t)0x04) 07668 #define FLASH_SR_WRPRTERR ((uint8_t)0x10) 07669 #define FLASH_SR_EOP ((uint8_t)0x20) 07671 /******************* Bit definition for FLASH_CR register *******************/ 07672 #define FLASH_CR_PG ((uint16_t)0x0001) 07673 #define FLASH_CR_PER ((uint16_t)0x0002) 07674 #define FLASH_CR_MER ((uint16_t)0x0004) 07675 #define FLASH_CR_OPTPG ((uint16_t)0x0010) 07676 #define FLASH_CR_OPTER ((uint16_t)0x0020) 07677 #define FLASH_CR_STRT ((uint16_t)0x0040) 07678 #define FLASH_CR_LOCK ((uint16_t)0x0080) 07679 #define FLASH_CR_OPTWRE ((uint16_t)0x0200) 07680 #define FLASH_CR_ERRIE ((uint16_t)0x0400) 07681 #define FLASH_CR_EOPIE ((uint16_t)0x1000) 07683 /******************* Bit definition for FLASH_AR register *******************/ 07684 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) 07686 /****************** Bit definition for FLASH_OBR register *******************/ 07687 #define FLASH_OBR_OPTERR ((uint16_t)0x0001) 07688 #define FLASH_OBR_RDPRT ((uint16_t)0x0002) 07690 #define FLASH_OBR_USER ((uint16_t)0x03FC) 07691 #define FLASH_OBR_WDG_SW ((uint16_t)0x0004) 07692 #define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) 07693 #define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) 07694 #define FLASH_OBR_BFB2 ((uint16_t)0x0020) 07696 /****************** Bit definition for FLASH_WRPR register ******************/ 07697 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) 07699 /*----------------------------------------------------------------------------*/ 07700 07701 /****************** Bit definition for FLASH_RDP register *******************/ 07702 #define FLASH_RDP_RDP ((uint32_t)0x000000FF) 07703 #define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) 07705 /****************** Bit definition for FLASH_USER register ******************/ 07706 #define FLASH_USER_USER ((uint32_t)0x00FF0000) 07707 #define FLASH_USER_nUSER ((uint32_t)0xFF000000) 07709 /****************** Bit definition for FLASH_Data0 register *****************/ 07710 #define FLASH_Data0_Data0 ((uint32_t)0x000000FF) 07711 #define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) 07713 /****************** Bit definition for FLASH_Data1 register *****************/ 07714 #define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) 07715 #define FLASH_Data1_nData1 ((uint32_t)0xFF000000) 07717 /****************** Bit definition for FLASH_WRP0 register ******************/ 07718 #define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) 07719 #define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) 07721 /****************** Bit definition for FLASH_WRP1 register ******************/ 07722 #define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) 07723 #define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) 07725 /****************** Bit definition for FLASH_WRP2 register ******************/ 07726 #define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) 07727 #define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) 07729 /****************** Bit definition for FLASH_WRP3 register ******************/ 07730 #define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) 07731 #define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) 07733 #ifdef STM32F10X_CL 07734 /******************************************************************************/ 07735 /* Ethernet MAC Registers bits definitions */ 07736 /******************************************************************************/ 07737 /* Bit definition for Ethernet MAC Control Register register */ 07738 #define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */ 07739 #define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */ 07740 #define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */ 07741 #define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ 07742 #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ 07743 #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ 07744 #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ 07745 #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ 07746 #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ 07747 #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ 07748 #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ 07749 #define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */ 07750 #define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */ 07751 #define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */ 07752 #define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */ 07753 #define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */ 07754 #define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */ 07755 #define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */ 07756 #define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */ 07757 #define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling 07758 a transmission attempt during retries after a collision: 0 =< r <2^k */ 07759 #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */ 07760 #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */ 07761 #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */ 07762 #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ 07763 #define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */ 07764 #define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */ 07765 #define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */ 07766 07767 /* Bit definition for Ethernet MAC Frame Filter Register */ 07768 #define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ 07769 #define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ 07770 #define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ 07771 #define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ 07772 #define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */ 07773 #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ 07774 #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ 07775 #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ 07776 #define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ 07777 #define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ 07778 #define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ 07779 #define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ 07780 #define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */ 07781 #define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */ 07782 07783 /* Bit definition for Ethernet MAC Hash Table High Register */ 07784 #define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */ 07785 07786 /* Bit definition for Ethernet MAC Hash Table Low Register */ 07787 #define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */ 07788 07789 /* Bit definition for Ethernet MAC MII Address Register */ 07790 #define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ 07791 #define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ 07792 #define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ 07793 #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ 07794 #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ 07795 #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ 07796 #define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ 07797 #define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ 07798 07799 /* Bit definition for Ethernet MAC MII Data Register */ 07800 #define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */ 07801 07802 /* Bit definition for Ethernet MAC Flow Control Register */ 07803 #define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */ 07804 #define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */ 07805 #define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */ 07806 #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ 07807 #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ 07808 #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ 07809 #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ 07810 #define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */ 07811 #define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */ 07812 #define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */ 07813 #define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */ 07814 07815 /* Bit definition for Ethernet MAC VLAN Tag Register */ 07816 #define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */ 07817 #define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ 07818 07819 /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 07820 #define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */ 07821 /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. 07822 Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ 07823 /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask 07824 Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask 07825 Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask 07826 Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask 07827 Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 07828 RSVD - Filter1 Command - RSVD - Filter0 Command 07829 Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset 07830 Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 07831 Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ 07832 07833 /* Bit definition for Ethernet MAC PMT Control and Status Register */ 07834 #define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ 07835 #define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */ 07836 #define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ 07837 #define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ 07838 #define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */ 07839 #define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */ 07840 #define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */ 07841 07842 /* Bit definition for Ethernet MAC Status Register */ 07843 #define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */ 07844 #define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */ 07845 #define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */ 07846 #define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */ 07847 #define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */ 07848 07849 /* Bit definition for Ethernet MAC Interrupt Mask Register */ 07850 #define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */ 07851 #define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */ 07852 07853 /* Bit definition for Ethernet MAC Address0 High Register */ 07854 #define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */ 07855 07856 /* Bit definition for Ethernet MAC Address0 Low Register */ 07857 #define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */ 07858 07859 /* Bit definition for Ethernet MAC Address1 High Register */ 07860 #define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */ 07861 #define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */ 07862 #define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ 07863 #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 07864 #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 07865 #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 07866 #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 07867 #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 07868 #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ 07869 #define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 07870 07871 /* Bit definition for Ethernet MAC Address1 Low Register */ 07872 #define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */ 07873 07874 /* Bit definition for Ethernet MAC Address2 High Register */ 07875 #define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */ 07876 #define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */ 07877 #define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 07878 #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 07879 #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 07880 #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 07881 #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 07882 #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 07883 #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 07884 #define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */ 07885 07886 /* Bit definition for Ethernet MAC Address2 Low Register */ 07887 #define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */ 07888 07889 /* Bit definition for Ethernet MAC Address3 High Register */ 07890 #define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */ 07891 #define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */ 07892 #define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */ 07893 #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ 07894 #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ 07895 #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ 07896 #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ 07897 #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ 07898 #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ 07899 #define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */ 07900 07901 /* Bit definition for Ethernet MAC Address3 Low Register */ 07902 #define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */ 07903 07904 /******************************************************************************/ 07905 /* Ethernet MMC Registers bits definition */ 07906 /******************************************************************************/ 07907 07908 /* Bit definition for Ethernet MMC Contol Register */ 07909 #define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */ 07910 #define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */ 07911 #define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */ 07912 #define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */ 07913 07914 /* Bit definition for Ethernet MMC Receive Interrupt Register */ 07915 #define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ 07916 #define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ 07917 #define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ 07918 07919 /* Bit definition for Ethernet MMC Transmit Interrupt Register */ 07920 #define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ 07921 #define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ 07922 #define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ 07923 07924 /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ 07925 #define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ 07926 #define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ 07927 #define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ 07928 07929 /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ 07930 #define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ 07931 #define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ 07932 #define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ 07933 07934 /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ 07935 #define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ 07936 07937 /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ 07938 #define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ 07939 07940 /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ 07941 #define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */ 07942 07943 /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ 07944 #define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */ 07945 07946 /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ 07947 #define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ 07948 07949 /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ 07950 #define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */ 07951 07952 /******************************************************************************/ 07953 /* Ethernet PTP Registers bits definition */ 07954 /******************************************************************************/ 07955 07956 /* Bit definition for Ethernet PTP Time Stamp Contol Register */ 07957 #define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */ 07958 #define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */ 07959 #define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */ 07960 #define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */ 07961 #define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */ 07962 #define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */ 07963 07964 /* Bit definition for Ethernet PTP Sub-Second Increment Register */ 07965 #define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */ 07966 07967 /* Bit definition for Ethernet PTP Time Stamp High Register */ 07968 #define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */ 07969 07970 /* Bit definition for Ethernet PTP Time Stamp Low Register */ 07971 #define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */ 07972 #define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */ 07973 07974 /* Bit definition for Ethernet PTP Time Stamp High Update Register */ 07975 #define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */ 07976 07977 /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ 07978 #define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */ 07979 #define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */ 07980 07981 /* Bit definition for Ethernet PTP Time Stamp Addend Register */ 07982 #define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */ 07983 07984 /* Bit definition for Ethernet PTP Target Time High Register */ 07985 #define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */ 07986 07987 /* Bit definition for Ethernet PTP Target Time Low Register */ 07988 #define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */ 07989 07990 /******************************************************************************/ 07991 /* Ethernet DMA Registers bits definition */ 07992 /******************************************************************************/ 07993 07994 /* Bit definition for Ethernet DMA Bus Mode Register */ 07995 #define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */ 07996 #define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */ 07997 #define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */ 07998 #define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */ 07999 #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ 08000 #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ 08001 #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 08002 #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 08003 #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 08004 #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 08005 #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ 08006 #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ 08007 #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ 08008 #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ 08009 #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ 08010 #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ 08011 #define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */ 08012 #define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 08013 #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */ 08014 #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */ 08015 #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */ 08016 #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ 08017 #define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */ 08018 #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 08019 #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 08020 #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 08021 #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 08022 #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 08023 #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 08024 #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 08025 #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 08026 #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 08027 #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 08028 #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 08029 #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 08030 #define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */ 08031 #define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */ 08032 #define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */ 08033 08034 /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ 08035 #define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */ 08036 08037 /* Bit definition for Ethernet DMA Receive Poll Demand Register */ 08038 #define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */ 08039 08040 /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ 08041 #define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */ 08042 08043 /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ 08044 #define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */ 08045 08046 /* Bit definition for Ethernet DMA Status Register */ 08047 #define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */ 08048 #define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */ 08049 #define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */ 08050 #define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */ 08051 /* combination with EBS[2:0] for GetFlagStatus function */ 08052 #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ 08053 #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ 08054 #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ 08055 #define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */ 08056 #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ 08057 #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ 08058 #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ 08059 #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ 08060 #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */ 08061 #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ 08062 #define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */ 08063 #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ 08064 #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ 08065 #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ 08066 #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */ 08067 #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ 08068 #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ 08069 #define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ 08070 #define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ 08071 #define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */ 08072 #define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */ 08073 #define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */ 08074 #define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */ 08075 #define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */ 08076 #define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */ 08077 #define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */ 08078 #define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */ 08079 #define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */ 08080 #define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */ 08081 #define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */ 08082 #define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */ 08083 #define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */ 08084 08085 /* Bit definition for Ethernet DMA Operation Mode Register */ 08086 #define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ 08087 #define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */ 08088 #define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */ 08089 #define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */ 08090 #define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */ 08091 #define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */ 08092 #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ 08093 #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ 08094 #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ 08095 #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ 08096 #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ 08097 #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ 08098 #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ 08099 #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ 08100 #define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */ 08101 #define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */ 08102 #define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */ 08103 #define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */ 08104 #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ 08105 #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ 08106 #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ 08107 #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ 08108 #define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */ 08109 #define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */ 08110 08111 /* Bit definition for Ethernet DMA Interrupt Enable Register */ 08112 #define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */ 08113 #define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */ 08114 #define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */ 08115 #define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */ 08116 #define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */ 08117 #define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */ 08118 #define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */ 08119 #define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */ 08120 #define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */ 08121 #define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */ 08122 #define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */ 08123 #define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */ 08124 #define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */ 08125 #define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */ 08126 #define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */ 08127 08128 /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ 08129 #define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ 08130 #define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */ 08131 #define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ 08132 #define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */ 08133 08134 /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ 08135 #define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */ 08136 08137 /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ 08138 #define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */ 08139 08140 /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ 08141 #define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */ 08142 08143 /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ 08144 #define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */ 08145 #endif /* STM32F10X_CL */ 08146 08155 #ifdef USE_STDPERIPH_DRIVER 08156 #include "stm32f10x_conf.h" 08157 #endif 08158 08163 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) 08164 08165 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) 08166 08167 #define READ_BIT(REG, BIT) ((REG) & (BIT)) 08168 08169 #define CLEAR_REG(REG) ((REG) = (0x0)) 08170 08171 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) 08172 08173 #define READ_REG(REG) ((REG)) 08174 08175 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) 08176 08181 #ifdef __cplusplus 08182 } 08183 #endif 08184 08185 #endif /* __STM32F10x_H */ 08186 08195 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/