AES_TypeDef Struct Reference

AES hardware accelerator. More...

#include <stm32l1xx.h>

Collaboration diagram for AES_TypeDef:

Data Fields
__IO uint32_t	CR
__IO uint32_t	SR
__IO uint32_t	DINR
__IO uint32_t	DOUTR
__IO uint32_t	KEYR0
__IO uint32_t	KEYR1
__IO uint32_t	KEYR2
__IO uint32_t	KEYR3
__IO uint32_t	IVR0
__IO uint32_t	IVR1
__IO uint32_t	IVR2
__IO uint32_t	IVR3

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Detailed Description

AES hardware accelerator.

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Field Documentation

__IO uint32_t AES_TypeDef::CR

AES control register, Address offset: 0x00

__IO uint32_t AES_TypeDef::SR

AES status register, Address offset: 0x04

__IO uint32_t AES_TypeDef::DINR

AES data input register, Address offset: 0x08

__IO uint32_t AES_TypeDef::DOUTR

AES data output register, Address offset: 0x0C

__IO uint32_t AES_TypeDef::KEYR0

AES key register 0, Address offset: 0x10

__IO uint32_t AES_TypeDef::KEYR1

AES key register 1, Address offset: 0x14

__IO uint32_t AES_TypeDef::KEYR2

AES key register 2, Address offset: 0x18

__IO uint32_t AES_TypeDef::KEYR3

AES key register 3, Address offset: 0x1C

__IO uint32_t AES_TypeDef::IVR0

AES initialization vector register 0, Address offset: 0x20

__IO uint32_t AES_TypeDef::IVR1

AES initialization vector register 1, Address offset: 0x24

__IO uint32_t AES_TypeDef::IVR2

AES initialization vector register 2, Address offset: 0x28

__IO uint32_t AES_TypeDef::IVR3

AES initialization vector register 3, Address offset: 0x2C

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The documentation for this struct was generated from the following file:

• include/arch/cm3/stm/stm32l1xx.h