lpc177x_8x_clk.h File Reference

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Defines
#define	XTAL   (12000000UL)
#define	OSC_CLK   ( XTAL)
#define	RTC_CLK   ( 32768UL)
#define	IRC_OSC   (12000000UL)
#define	WDT_OSC   ( 500000UL)
#define	CLKPWR_PCONP_PCLCD   0
#define	CLKPWR_PCONP_PCTIM0   1
#define	CLKPWR_PCONP_PCTIM1   2
#define	CLKPWR_PCONP_PCUART0   3
#define	CLKPWR_PCONP_PCUART1   4
#define	CLKPWR_PCONP_PCPWM0   5
#define	CLKPWR_PCONP_PCPWM1   6
#define	CLKPWR_PCONP_PCI2C0   7
#define	CLKPWR_PCONP_PCUART4   8
#define	CLKPWR_PCONP_PCRTC   9
#define	CLKPWR_PCONP_PCSSP1   10
#define	CLKPWR_PCONP_PCEMC   11
#define	CLKPWR_PCONP_PCADC   12
#define	CLKPWR_PCONP_PCAN1   13
#define	CLKPWR_PCONP_PCAN2   14
#define	CLKPWR_PCONP_PCGPIO   15
#define	CLKPWR_PCONP_PCMCPWM   17
#define	CLKPWR_PCONP_PCQEI   18
#define	CLKPWR_PCONP_PCI2C1   19
#define	CLKPWR_PCONP_PCSSP2   20
#define	CLKPWR_PCONP_PCSSP0   21
#define	CLKPWR_PCONP_PCTIM2   22
#define	CLKPWR_PCONP_PCTIM3   23
#define	CLKPWR_PCONP_PCUART2   24
#define	CLKPWR_PCONP_PCUART3   25
#define	CLKPWR_PCONP_PCI2C2   26
#define	CLKPWR_PCONP_PCI2S   27
#define	CLKPWR_PCONP_PCSDC   28
#define	CLKPWR_PCONP_PCGPDMA   29
#define	CLKPWR_PCONP_PCENET   30
#define	CLKPWR_PCONP_PCUSB   31
#define	CLKPWR_RSTCON0_LCD   0
#define	CLKPWR_RSTCON0_TIM0   1
#define	CLKPWR_RSTCON0_TIM1   2
#define	CLKPWR_RSTCON0_UART0   3
#define	CLKPWR_RSTCON0_UART1   4
#define	CLKPWR_RSTCON0_PWM0   5
#define	CLKPWR_RSTCON0_PWM1   6
#define	CLKPWR_RSTCON0_I2C0   7
#define	CLKPWR_RSTCON0_UART4   8
#define	CLKPWR_RSTCON0_RTC   9
#define	CLKPWR_RSTCON0_SSP1   10
#define	CLKPWR_RSTCON0_EMC   11
#define	CLKPWR_RSTCON0_ADC   12
#define	CLKPWR_RSTCON0_CAN1   13
#define	CLKPWR_RSTCON0_CAN2   14
#define	CLKPWR_RSTCON0_GPIO   15
#define	CLKPWR_RSTCON0_MCPWM   17
#define	CLKPWR_RSTCON0_QEI   18
#define	CLKPWR_RSTCON0_I2C1   19
#define	CLKPWR_RSTCON0_SSP2   20
#define	CLKPWR_RSTCON0_SSP0   21
#define	CLKPWR_RSTCON0_TIM2   22
#define	CLKPWR_RSTCON0_TIM3   23
#define	CLKPWR_RSTCON0_UART2   24
#define	CLKPWR_RSTCON0_UART3   25
#define	CLKPWR_RSTCON0_I2C2   26
#define	CLKPWR_RSTCON0_I2S   27
#define	CLKPWR_RSTCON0_SDC   28
#define	CLKPWR_RSTCON0_GPDMA   29
#define	CLKPWR_RSTCON0_ENET   30
#define	CLKPWR_RSTCON0_USB   31
#define	CLKPWR_RSTCON1_IOCON   32
#define	CLKPWR_RSTCON1_DAC   33
#define	CLKPWR_RSTCON1_CANACC   34
#define	SysCtlPeripheralClkEnable(bit)   CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 1
#define	SysCtlPeripheralClkDisable(bit)   CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 0
#define	SysCtlPeripheralClkGet(bit)   CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit))
#define	SysCtlPeripheralResetEnable(bit)
#define	SysCtlPeripheralResetDisable(bit)
#define	NS_2_CLKS(clock, ns)   (((((((clock) >> 4)*69) >> 20)*(ns))>>12)+1)
Functions
uint32_t	Lpc17xx_ClockGet (int idx)
	requests frequency of the given clock
uint32_t	SysCtlClockGet (void)
	requests System clock frequency
int	SetSysClock (void)
	Update SystemCoreClock according to Clock Register Values.

---

Define Documentation

#define XTAL   (12000000UL)

#define OSC_CLK   ( XTAL)

#define RTC_CLK   ( 32768UL)

#define IRC_OSC   (12000000UL)

#define WDT_OSC   ( 500000UL)

#define CLKPWR_PCONP_PCLCD   0

#define CLKPWR_PCONP_PCTIM0   1

#define CLKPWR_PCONP_PCTIM1   2

#define CLKPWR_PCONP_PCUART0   3

#define CLKPWR_PCONP_PCUART1   4

#define CLKPWR_PCONP_PCPWM0   5

#define CLKPWR_PCONP_PCPWM1   6

#define CLKPWR_PCONP_PCI2C0   7

#define CLKPWR_PCONP_PCUART4   8

#define CLKPWR_PCONP_PCRTC   9

#define CLKPWR_PCONP_PCSSP1   10

#define CLKPWR_PCONP_PCEMC   11

Referenced by Lpc177x_8x_EmcInit().

#define CLKPWR_PCONP_PCADC   12

#define CLKPWR_PCONP_PCAN1   13

#define CLKPWR_PCONP_PCAN2   14

#define CLKPWR_PCONP_PCGPIO   15

#define CLKPWR_PCONP_PCMCPWM   17

#define CLKPWR_PCONP_PCQEI   18

#define CLKPWR_PCONP_PCI2C1   19

#define CLKPWR_PCONP_PCSSP2   20

#define CLKPWR_PCONP_PCSSP0   21

#define CLKPWR_PCONP_PCTIM2   22

#define CLKPWR_PCONP_PCTIM3   23

#define CLKPWR_PCONP_PCUART2   24

#define CLKPWR_PCONP_PCUART3   25

#define CLKPWR_PCONP_PCI2C2   26

#define CLKPWR_PCONP_PCI2S   27

#define CLKPWR_PCONP_PCSDC   28

Referenced by Lpc177x_8x_MciInit().

#define CLKPWR_PCONP_PCGPDMA   29

#define CLKPWR_PCONP_PCENET   30

#define CLKPWR_PCONP_PCUSB   31

#define CLKPWR_RSTCON0_LCD   0

#define CLKPWR_RSTCON0_TIM0   1

#define CLKPWR_RSTCON0_TIM1   2

#define CLKPWR_RSTCON0_UART0   3

#define CLKPWR_RSTCON0_UART1   4

#define CLKPWR_RSTCON0_PWM0   5

#define CLKPWR_RSTCON0_PWM1   6

#define CLKPWR_RSTCON0_I2C0   7

#define CLKPWR_RSTCON0_UART4   8

#define CLKPWR_RSTCON0_RTC   9

#define CLKPWR_RSTCON0_SSP1   10

#define CLKPWR_RSTCON0_EMC   11

#define CLKPWR_RSTCON0_ADC   12

#define CLKPWR_RSTCON0_CAN1   13

#define CLKPWR_RSTCON0_CAN2   14

#define CLKPWR_RSTCON0_GPIO   15

#define CLKPWR_RSTCON0_MCPWM   17

#define CLKPWR_RSTCON0_QEI   18

#define CLKPWR_RSTCON0_I2C1   19

#define CLKPWR_RSTCON0_SSP2   20

#define CLKPWR_RSTCON0_SSP0   21

#define CLKPWR_RSTCON0_TIM2   22

#define CLKPWR_RSTCON0_TIM3   23

#define CLKPWR_RSTCON0_UART2   24

#define CLKPWR_RSTCON0_UART3   25

#define CLKPWR_RSTCON0_I2C2   26

#define CLKPWR_RSTCON0_I2S   27

#define CLKPWR_RSTCON0_SDC   28

#define CLKPWR_RSTCON0_GPDMA   29

#define CLKPWR_RSTCON0_ENET   30

#define CLKPWR_RSTCON0_USB   31

#define CLKPWR_RSTCON1_IOCON   32

#define CLKPWR_RSTCON1_DAC   33

#define CLKPWR_RSTCON1_CANACC   34

#define SysCtlPeripheralClkEnable

(

bit

)

CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 1

#define SysCtlPeripheralClkDisable

(

bit

)

CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit)) = 0

#define SysCtlPeripheralClkGet

(

bit

)

CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, PCONP, (bit))

#define SysCtlPeripheralResetEnable

(

bit

)

Value:

if ((bit) < 32) \
                                          CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, RSTCON0, (bit)) = 1; else \
                                          CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, RSTCON1, (bit - 32)) = 1;

#define SysCtlPeripheralResetDisable

(

bit

)

Value:

if ((bit) < 32) \
                                          CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, RSTCON0, (bit)) = 0; else \
                                          CM3BBREG(LPC_SC_BASE, LPC_SC_TypeDef, RSTCON1, (bit - 32)) = 0;

#define NS_2_CLKS	(		clock,
			ns
	)		(((((((clock) >> 4)*69) >> 20)*(ns))>>12)+1)

---

Function Documentation

uint32_t Lpc17xx_ClockGet

(

int

idx

)

requests frequency of the given clock

Parameters:

idx	NUT_HWCLK Index

Return values:

clock

or 0 if idx points to an invalid clock

References EMCClock, NUT_HWCLK_CPU, PeripheralClock, SystemCoreClock, SystemCoreClockUpdate(), and USBClock.

Here is the call graph for this function:

uint32_t SysCtlClockGet

(

void

)

requests System clock frequency

Note:

This function should be used only after reset.

Parameters:

None

Return values:

None

int SetSysClock

(

void

)

Update SystemCoreClock according to Clock Register Values.

This function reads out the CPUs clock and PLL registers and assembles the actual clock speed values into the SystemCoreClock global variable. Sets System clock frequency to the configured defaults.

Note:

This function should be used only after reset.

Parameters:

None

Return values:

None	Update SystemCoreClock according to Clock Register Values.

Note:

This function should be used only after reset.

Parameters:

None

Return values:

None	Update SystemCoreClock according to Clock Register Values.

Enable HSI/HSE clock and setup HCLK, PCLK2 and PCLK1 prescalers.

Parameters:

None.

Returns:

0 on success, -1 on fault of HSE.