Universal synchronous / asynchronous receiver / transmitter registers. More...

Collaboration diagram for USART:

Defines
#define	ASCII_XON 0x11
#define	ASCII_XOFF 0x13
#define	XON_PENDING 0x10
#define	XOFF_PENDING 0x20
#define	XOFF_SENT 0x40
#define	XOFF_RCVD 0x80
#define	US_OVRE 0x00000020
	Overrun error.
#define	ASCII_XON 0x11
#define	ASCII_XOFF 0x13
#define	XON_PENDING 0x10
#define	XOFF_PENDING 0x20
#define	XOFF_SENT 0x40
#define	XOFF_RCVD 0x80
Functions
int	Sc16is752RegWrite (uint8_t dev, uint8_t ch, uint8_t reg, uint8_t val)
int	Sc16is752RegRead (uint8_t dev, uint8_t ch, uint8_t reg, uint8_t *val)
int	selectRegisterSet (uint8_t dev, uint8_t ch, uint8_t reg)
void	Sc16is752UsartProcessChannelInterrupt (uint8_t dev, uint8_t ch, uint8_t iir)
void	Sc16is752UsartInterruptProcessing (void *arg)
void	Sc16is752UsartEnable (uint8_t dev, uint8_t ch)
	Carefully enable USART hardware functions.
void	Sc16is752UsartDisable (uint8_t dev, uint8_t ch)
	Carefully disable USART hardware functions.
uint32_t	Sc16is752UsartGetSpeed (uint8_t dev, uint8_t ch)
	Query the USART hardware for the selected speed.
int	Sc16is752UsartSetSpeed (uint32_t rate, uint8_t dev, uint8_t ch)
	Set the USART hardware bit rate.
uint8_t	Sc16is752UsartGetDataBits (uint8_t dev, uint8_t ch)
	Query the USART hardware for the number of data bits.
int	Sc16is752UsartSetDataBits (uint8_t bits, uint8_t dev, uint8_t ch)
	Set the USART hardware to the number of data bits.
uint8_t	Sc16is752UsartGetParity (uint8_t dev, uint8_t ch)
	Query the USART hardware for the parity mode.
int	Sc16is752UsartSetParity (uint8_t mode, uint8_t dev, uint8_t ch)
	Set the USART hardware to the specified parity mode.
uint8_t	Sc16is752UsartGetStopBits (uint8_t dev, uint8_t ch)
	Query the USART hardware for the number of stop bits.
int	Sc16is752UsartSetStopBits (uint8_t bits, uint8_t dev, uint8_t ch)
	Set the USART hardware to the number of stop bits.
uint32_t	Sc16is752UsartGetStatus (uint8_t dev, uint8_t ch)
	Query the USART hardware status.
int	Sc16is752UsartSetStatus (uint32_t flags, uint8_t dev, uint8_t ch)
	Set the USART hardware status.
uint8_t	Sc16is752UsartGetClockMode (uint8_t dev, uint8_t ch)
	Query the USART hardware for synchronous mode.
int	Sc16is752UsartSetClockMode (uint8_t mode, uint8_t dev, uint8_t ch)
	Set asynchronous or synchronous mode.
uint32_t	Sc16is752UsartGetFlowControl (uint8_t dev, uint8_t ch)
	Query flow control mode.
int	Sc16is752UsartSetFlowControl (uint32_t flags, uint8_t dev, uint8_t ch)
	Set flow control mode.
void	Sc16is752UsartTxStart (uint8_t dev, uint8_t ch)
	Start the USART transmitter hardware.
void	Sc16is752UsartRxStart (uint8_t dev, uint8_t ch)
	Start the USART receiver hardware.
int	Sc16is752UsartInit (uint8_t dev, uint8_t ch, NUTDEVICE nutDev, IRQ_HANDLER irq)
	Initialize the USART hardware driver.
int	Sc16is752UsartDeinit (uint8_t dev, uint8_t ch, IRQ_HANDLER *irq)
	Deinitialize the USART hardware driver.
USART Control Register
#define	US_CR_OFF 0x00000000
	USART control register offset.
#define	US0_CR (USART0_BASE + US_CR_OFF)
	Channel 0 control register address.
#define	US1_CR (USART1_BASE + US_CR_OFF)
	Channel 1 control register address.
#define	US_RSTRX 0x00000004
	Reset receiver.
#define	US_RSTTX 0x00000008
	Reset transmitter.
#define	US_RXEN 0x00000010
	Receiver enable.
#define	US_RXDIS 0x00000020
	Receiver disable.
#define	US_TXEN 0x00000040
	Transmitter enable.
#define	US_TXDIS 0x00000080
	Transmitter disable.
#define	US_RSTSTA 0x00000100
	Reset status bits.
#define	US_STTBRK 0x00000200
	Start break.
#define	US_STPBRK 0x00000400
	Stop break.
#define	US_STTTO 0x00000800
	Start timeout.
#define	US_SENDA 0x00001000
	Send next byte with address bit set.
Mode Register
#define	US_MR_OFF 0x00000004
	USART mode register offset.
#define	US0_MR (USART0_BASE + US_MR_OFF)
	Channel 0 mode register address.
#define	US1_MR (USART1_BASE + US_MR_OFF)
	Channel 1 mode register address.
#define	US_CLKS 0x00000030
	Clock selection mask.
#define	US_CLKS_MCK 0x00000000
	Master clock.
#define	US_CLKS_MCK8 0x00000010
	Master clock divided by 8.
#define	US_CLKS_SCK 0x00000020
	External clock.
#define	US_CLKS_SLCK 0x00000030
	Slow clock.
#define	US_CHRL 0x000000C0
	Masks data length.
#define	US_CHRL_5 0x00000000
	5 data bits.
#define	US_CHRL_6 0x00000040
	6 data bits.
#define	US_CHRL_7 0x00000080
	7 data bits.
#define	US_CHRL_8 0x000000C0
	8 data bits.
#define	US_SYNC 0x00000100
	Synchronous mode enable.
#define	US_PAR 0x00000E00
	Parity mode mask.
#define	US_PAR_EVEN 0x00000000
	Even parity.
#define	US_PAR_ODD 0x00000200
	Odd parity.
#define	US_PAR_SPACE 0x00000400
	Space parity.
#define	US_PAR_MARK 0x00000600
	Marked parity.
#define	US_PAR_NO 0x00000800
	No parity.
#define	US_PAR_MULTIDROP 0x00000C00
	Multi-drop mode.
#define	US_NBSTOP 0x00003000
	Masks stop bit length.
#define	US_NBSTOP_1 0x00000000
	1 stop bit.
#define	US_NBSTOP_1_5 0x00001000
	1.5 stop bits.
#define	US_NBSTOP_2 0x00002000
	2 stop bits.
#define	US_CHMODE 0x0000C000
	Channel mode mask.
#define	US_CHMODE_NORMAL 0x00000000
	Normal mode.
#define	US_CHMODE_AUTOMATIC_ECHO 0x00004000
	Automatic echo.
#define	US_CHMODE_LOCAL_LOOPBACK 0x00008000
	Local loopback.
#define	US_CHMODE_REMOTE_LOOPBACK 0x0000C000
	Remote loopback.
#define	US_MODE9 0x00020000
	9 bit mode.
#define	US_CLKO 0x00040000
	Baud rate output enable.
Status and Interrupt Register
#define	US_CSR_OFF 0x00000014
	USART status register offset.
#define	US0_CSR (USART0_BASE + US_CSR_OFF)
	Channel 0 status register address.
#define	US1_CSR (USART1_BASE + US_CSR_OFF)
	Channel 1 status register address.
#define	US_IER_OFF 0x00000008
	USART interrupt enable register offset.
#define	US0_IER (USART0_BASE + US_IER_OFF)
	Channel 0 interrupt enable register address.
#define	US1_IER (USART1_BASE + US_IER_OFF)
	Channel 1 interrupt enable register address.
#define	US_IDR_OFF 0x0000000C
	USART interrupt disable register offset.
#define	US0_IDR (USART0_BASE + US_IDR_OFF)
	Channel 0 interrupt disable register address.
#define	US1_IDR (USART1_BASE + US_IDR_OFF)
	Channel 1 interrupt disable register address.
#define	US_IMR_OFF 0x00000010
	USART interrupt mask register offset.
#define	US0_IMR (USART0_BASE + US_IMR_OFF)
	Channel 0 interrupt mask register address.
#define	US1_IMR (USART1_BASE + US_IMR_OFF)
	Channel 1 interrupt mask register address.
#define	US_RXRDY 0x00000001
	Receiver ready.
#define	US_TXRDY 0x00000002
	Transmitter ready.
#define	US_RXBRK 0x00000004
	Receiver break.
#define	US_ENDRX 0x00000008
	End of receiver PDC transfer.
#define	US_ENDTX 0x00000010
	End of transmitter PDC transfer.
#define	US_OVRE 0x00000020
	Overrun error.
#define	US_FRAME 0x00000040
	Framing error.
#define	US_PARE 0x00000080
	Parity error.
#define	US_TIMEOUT 0x00000100
	Receiver timeout.
#define	US_TXEMPTY 0x00000200
	Transmitter empty.
#define	US_RXBUFF 0x00001000
	Receive buffer full.
#define	AT91_US_BAUD(baud) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)
	Baud rate calculation helper macro.
Receiver Holding Register
#define	US_RHR_OFF 0x00000018
	USART receiver holding register offset.
#define	US0_RHR (USART0_BASE + US_RHR_OFF)
	Channel 0 receiver holding register address.
#define	US1_RHR (USART1_BASE + US_RHR_OFF)
	Channel 1 receiver holding register address.
Transmitter Holding Register
#define	US_THR_OFF 0x0000001C
	USART transmitter holding register offset.
#define	US0_THR (USART0_BASE + US_THR_OFF)
	Channel 0 transmitter holding register address.
#define	US1_THR (USART1_BASE + US_THR_OFF)
	Channel 1 transmitter holding register address.
Baud Rate Generator Register
#define	US_BRGR_OFF 0x00000020
	USART baud rate register offset.
#define	US0_BRGR (USART0_BASE + US_BRGR_OFF)
	Channel 0 baud rate register address.
#define	US1_BRGR (USART1_BASE + US_BRGR_OFF)
	Channel 1 baud rate register address.
Receiver Timeout Register
#define	US_RTOR_OFF 0x00000024
	USART receiver timeout register offset.
#define	US0_RTOR (USART0_BASE + US_RTOR_OFF)
	Channel 0 receiver timeout register address.
#define	US1_RTOR (USART1_BASE + US_RTOR_OFF)
	Channel 1 receiver timeout register address.
Transmitter Time Guard Register
#define	US_TTGR_OFF 0x00000028
	USART transmitter time guard register offset.
#define	US0_TTGR (USART0_BASE + US_TTGR_OFF)
	Channel 0 transmitter time guard register address.
#define	US1_TTGR (USART1_BASE + US_TTGR_OFF)
	Channel 1 transmitter time guard register address.
FI DI Ratio Register
#define	US_FIDI_OFF 0x00000040
	USART FI DI ratio register offset.
#define	US0_FIDI (USART0_BASE + US_FIDI_OFF)
	Channel 0 FI DI ratio register address.
#define	US1_FIDI (USART1_BASE + US_FIDI_OFF)
	Channel 1 FI DI ratio register address.
Error Counter Register
#define	US_NER_OFF 0x00000044
	USART error counter register offset.
#define	US0_NER (USART0_BASE + US_NER_OFF)
	Channel 0 error counter register address.
#define	US1_NER (USART1_BASE + US_NER_OFF)
	Channel 1 error counter register address.
IrDA Filter Register
#define	US_IF_OFF 0x0000004C
	USART IrDA filter register offset.
#define	US0_IF (USART0_BASE + US_IF_OFF)
	Channel 0 IrDA filter register address.
#define	US1_IF (USART1_BASE + US_IF_OFF)
	Channel 1 IrDA filter register address.
AT91 USART0 Device
NUTDEVICE	devUsartAt910
	USART0 device information structure.
AT91 USART1 Device
NUTDEVICE	devUsartAt911
	USART1 device information structure.
AT91 DBGU Device
NUTDEVICE	devDbguAt91
	USART0 device information structure.
SC16IS752 USARTa Device
NUTDEVICE	devUsartsc16is752a
	USART0 device information structure.
SC16IS752 USARTa Device
NUTDEVICE	devUsartsc16is752b
	USART0 device information structure.
SC16IS752 USARTc Device
NUTDEVICE	devUsartsc16is752c
	USART2 device information structure.
SC16IS752 USARTd Device
NUTDEVICE	devUsartsc16is752d
	USART3 device information structure.

Detailed Description

Universal synchronous / asynchronous receiver / transmitter registers.

Define Documentation

#define US_CR_OFF 0x00000000

USART control register offset.

Definition at line 69 of file at91_us.h.

#define US0_CR (USART0_BASE + US_CR_OFF)

Channel 0 control register address.

Definition at line 70 of file at91_us.h.

#define US1_CR (USART1_BASE + US_CR_OFF)

Channel 1 control register address.

Definition at line 71 of file at91_us.h.

Referenced by AhdlcAt91Init(), and AhdlcAt91Open().

#define US_RSTRX 0x00000004

Reset receiver.

Definition at line 72 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_RSTTX 0x00000008

Reset transmitter.

Definition at line 73 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_RXEN 0x00000010

Receiver enable.

Definition at line 74 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_RXDIS 0x00000020

Receiver disable.

Definition at line 75 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_TXEN 0x00000040

Transmitter enable.

Definition at line 76 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_TXDIS 0x00000080

Transmitter disable.

Definition at line 77 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_RSTSTA 0x00000100

Reset status bits.

Definition at line 78 of file at91_us.h.

#define US_STTBRK 0x00000200

Start break.

Definition at line 79 of file at91_us.h.

#define US_STPBRK 0x00000400

Stop break.

Definition at line 80 of file at91_us.h.

#define US_STTTO 0x00000800

Start timeout.

Definition at line 81 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_SENDA 0x00001000

Send next byte with address bit set.

Definition at line 82 of file at91_us.h.

#define US_MR_OFF 0x00000004

USART mode register offset.

Definition at line 97 of file at91_us.h.

Referenced by AhdlcAt91IOCtl().

#define US0_MR (USART0_BASE + US_MR_OFF)

Channel 0 mode register address.

Definition at line 98 of file at91_us.h.

#define US1_MR (USART1_BASE + US_MR_OFF)

Channel 1 mode register address.

Definition at line 99 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_CLKS 0x00000030

Clock selection mask.

Definition at line 111 of file at91_us.h.

Referenced by AhdlcAt91IOCtl().

#define US_CLKS_MCK 0x00000000

Master clock.

Definition at line 112 of file at91_us.h.

Referenced by AhdlcAt91IOCtl().

#define US_CLKS_MCK8 0x00000010

Master clock divided by 8.

Definition at line 113 of file at91_us.h.

Referenced by AhdlcAt91IOCtl().

#define US_CLKS_SCK 0x00000020

External clock.

Definition at line 114 of file at91_us.h.

#define US_CLKS_SLCK 0x00000030

Slow clock.

Definition at line 115 of file at91_us.h.

#define US_CHRL 0x000000C0

Masks data length.

Definition at line 117 of file at91_us.h.

#define US_CHRL_5 0x00000000

5 data bits.

Definition at line 118 of file at91_us.h.

#define US_CHRL_6 0x00000040

6 data bits.

Definition at line 119 of file at91_us.h.

#define US_CHRL_7 0x00000080

7 data bits.

Definition at line 120 of file at91_us.h.

#define US_CHRL_8 0x000000C0

8 data bits.

Definition at line 121 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_SYNC 0x00000100

Synchronous mode enable.

Definition at line 123 of file at91_us.h.

#define US_PAR 0x00000E00

Parity mode mask.

Definition at line 125 of file at91_us.h.

#define US_PAR_EVEN 0x00000000

Even parity.

Definition at line 126 of file at91_us.h.

#define US_PAR_ODD 0x00000200

Odd parity.

Definition at line 127 of file at91_us.h.

#define US_PAR_SPACE 0x00000400

Space parity.

Definition at line 128 of file at91_us.h.

#define US_PAR_MARK 0x00000600

Marked parity.

Definition at line 129 of file at91_us.h.

#define US_PAR_NO 0x00000800

No parity.

Definition at line 130 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_PAR_MULTIDROP 0x00000C00

Multi-drop mode.

Definition at line 131 of file at91_us.h.

#define US_NBSTOP 0x00003000

Masks stop bit length.

Definition at line 133 of file at91_us.h.

#define US_NBSTOP_1 0x00000000

1 stop bit.

Definition at line 134 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_NBSTOP_1_5 0x00001000

1.5 stop bits.

Definition at line 135 of file at91_us.h.

#define US_NBSTOP_2 0x00002000

2 stop bits.

Definition at line 136 of file at91_us.h.

#define US_CHMODE 0x0000C000

Channel mode mask.

Definition at line 138 of file at91_us.h.

#define US_CHMODE_NORMAL 0x00000000

Normal mode.

Definition at line 139 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_CHMODE_AUTOMATIC_ECHO 0x00004000

Automatic echo.

Definition at line 140 of file at91_us.h.

#define US_CHMODE_LOCAL_LOOPBACK 0x00008000

Local loopback.

Definition at line 141 of file at91_us.h.

#define US_CHMODE_REMOTE_LOOPBACK 0x0000C000

Remote loopback.

Definition at line 142 of file at91_us.h.

#define US_MODE9 0x00020000

9 bit mode.

Definition at line 144 of file at91_us.h.

#define US_CLKO 0x00040000

Baud rate output enable.

Definition at line 146 of file at91_us.h.

#define US_CSR_OFF 0x00000014

USART status register offset.

Definition at line 151 of file at91_us.h.

#define US0_CSR (USART0_BASE + US_CSR_OFF)

Channel 0 status register address.

Definition at line 152 of file at91_us.h.

#define US1_CSR (USART1_BASE + US_CSR_OFF)

Channel 1 status register address.

Definition at line 153 of file at91_us.h.

#define US_IER_OFF 0x00000008

USART interrupt enable register offset.

Definition at line 155 of file at91_us.h.

#define US0_IER (USART0_BASE + US_IER_OFF)

Channel 0 interrupt enable register address.

Definition at line 156 of file at91_us.h.

#define US1_IER (USART1_BASE + US_IER_OFF)

Channel 1 interrupt enable register address.

Definition at line 157 of file at91_us.h.

Referenced by AhdlcAt91Open(), and AhdlcAt91Put().

#define US_IDR_OFF 0x0000000C

USART interrupt disable register offset.

Definition at line 159 of file at91_us.h.

#define US0_IDR (USART0_BASE + US_IDR_OFF)

Channel 0 interrupt disable register address.

Definition at line 160 of file at91_us.h.

#define US1_IDR (USART1_BASE + US_IDR_OFF)

Channel 1 interrupt disable register address.

Definition at line 161 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_IMR_OFF 0x00000010

USART interrupt mask register offset.

Definition at line 163 of file at91_us.h.

#define US0_IMR (USART0_BASE + US_IMR_OFF)

Channel 0 interrupt mask register address.

Definition at line 164 of file at91_us.h.

#define US1_IMR (USART1_BASE + US_IMR_OFF)

Channel 1 interrupt mask register address.

Definition at line 165 of file at91_us.h.

#define US_RXRDY 0x00000001

Receiver ready.

Definition at line 167 of file at91_us.h.

#define US_TXRDY 0x00000002

Transmitter ready.

Definition at line 168 of file at91_us.h.

Referenced by AhdlcAt91Put().

#define US_RXBRK 0x00000004

Receiver break.

Definition at line 169 of file at91_us.h.

#define US_ENDRX 0x00000008

End of receiver PDC transfer.

Definition at line 170 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_ENDTX 0x00000010

End of transmitter PDC transfer.

Definition at line 171 of file at91_us.h.

#define US_OVRE 0x00000020

Overrun error.

Definition at line 172 of file at91_us.h.

#define US_FRAME 0x00000040

Framing error.

Definition at line 173 of file at91_us.h.

#define US_PARE 0x00000080

Parity error.

Definition at line 174 of file at91_us.h.

#define US_TIMEOUT 0x00000100

Receiver timeout.

Definition at line 175 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_TXEMPTY 0x00000200

Transmitter empty.

Definition at line 176 of file at91_us.h.

#define US_RXBUFF 0x00001000

Receive buffer full.

Definition at line 177 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define AT91_US_BAUD ( baud ) ((NUT_CPU_FREQ / (8 * (baud)) + 1) / 2)

Baud rate calculation helper macro.

Deprecated:: Use NutGetCpuClock() and calculate the divider value locally.

Definition at line 196 of file at91_us.h.

#define US_RHR_OFF 0x00000018

USART receiver holding register offset.

Definition at line 201 of file at91_us.h.

#define US0_RHR (USART0_BASE + US_RHR_OFF)

Channel 0 receiver holding register address.

Definition at line 202 of file at91_us.h.

#define US1_RHR (USART1_BASE + US_RHR_OFF)

Channel 1 receiver holding register address.

Definition at line 203 of file at91_us.h.

#define US_THR_OFF 0x0000001C

USART transmitter holding register offset.

Definition at line 208 of file at91_us.h.

#define US0_THR (USART0_BASE + US_THR_OFF)

Channel 0 transmitter holding register address.

Definition at line 209 of file at91_us.h.

#define US1_THR (USART1_BASE + US_THR_OFF)

Channel 1 transmitter holding register address.

Definition at line 210 of file at91_us.h.

#define US_BRGR_OFF 0x00000020

USART baud rate register offset.

Definition at line 215 of file at91_us.h.

Referenced by AhdlcAt91IOCtl(), and At91DevDebugIOCtl().

#define US0_BRGR (USART0_BASE + US_BRGR_OFF)

Channel 0 baud rate register address.

Definition at line 216 of file at91_us.h.

#define US1_BRGR (USART1_BASE + US_BRGR_OFF)

Channel 1 baud rate register address.

Definition at line 217 of file at91_us.h.

Referenced by AhdlcAt91Init().

#define US_RTOR_OFF 0x00000024

USART receiver timeout register offset.

Definition at line 222 of file at91_us.h.

#define US0_RTOR (USART0_BASE + US_RTOR_OFF)

Channel 0 receiver timeout register address.

Definition at line 223 of file at91_us.h.

#define US1_RTOR (USART1_BASE + US_RTOR_OFF)

Channel 1 receiver timeout register address.

Definition at line 224 of file at91_us.h.

Referenced by AhdlcAt91Open().

#define US_TTGR_OFF 0x00000028

USART transmitter time guard register offset.

Definition at line 229 of file at91_us.h.

#define US0_TTGR (USART0_BASE + US_TTGR_OFF)

Channel 0 transmitter time guard register address.

Definition at line 230 of file at91_us.h.

#define US1_TTGR (USART1_BASE + US_TTGR_OFF)

Channel 1 transmitter time guard register address.

Definition at line 231 of file at91_us.h.

#define US_FIDI_OFF 0x00000040

USART FI DI ratio register offset.

Definition at line 236 of file at91_us.h.

#define US0_FIDI (USART0_BASE + US_FIDI_OFF)

Channel 0 FI DI ratio register address.

Definition at line 237 of file at91_us.h.

#define US1_FIDI (USART1_BASE + US_FIDI_OFF)

Channel 1 FI DI ratio register address.

Definition at line 238 of file at91_us.h.

#define US_NER_OFF 0x00000044

USART error counter register offset.

Definition at line 243 of file at91_us.h.

#define US0_NER (USART0_BASE + US_NER_OFF)

Channel 0 error counter register address.

Definition at line 244 of file at91_us.h.

#define US1_NER (USART1_BASE + US_NER_OFF)

Channel 1 error counter register address.

Definition at line 245 of file at91_us.h.

#define US_IF_OFF 0x0000004C

USART IrDA filter register offset.

Definition at line 250 of file at91_us.h.

#define US0_IF (USART0_BASE + US_IF_OFF)

Channel 0 IrDA filter register address.

Definition at line 251 of file at91_us.h.

#define US1_IF (USART1_BASE + US_IF_OFF)

Channel 1 IrDA filter register address.

Definition at line 252 of file at91_us.h.

#define ASCII_XON 0x11

Definition at line 254 of file usartat91.c.

#define ASCII_XOFF 0x13

Definition at line 256 of file usartat91.c.

#define XON_PENDING 0x10

Definition at line 259 of file usartat91.c.

#define XOFF_PENDING 0x20

Definition at line 261 of file usartat91.c.

#define XOFF_SENT 0x40

Definition at line 263 of file usartat91.c.

#define XOFF_RCVD 0x80

Definition at line 265 of file usartat91.c.

#define US_OVRE 0x00000020

Overrun error.

Definition at line 83 of file usartsc16is752.c.

#define ASCII_XON 0x11

Definition at line 87 of file usartsc16is752.c.

#define ASCII_XOFF 0x13

Definition at line 89 of file usartsc16is752.c.

#define XON_PENDING 0x10

Definition at line 92 of file usartsc16is752.c.

#define XOFF_PENDING 0x20

Definition at line 94 of file usartsc16is752.c.

#define XOFF_SENT 0x40

Definition at line 96 of file usartsc16is752.c.

#define XOFF_RCVD 0x80

Definition at line 98 of file usartsc16is752.c.

Function Documentation

int Sc16is752RegWrite	(	uint8_t	dev,
		uint8_t	ch,
		uint8_t	reg,
		uint8_t	val
	)

Definition at line 1222 of file usartsc16is752.c.

Referenced by Sc16is752UsartInit(), and Sc16is752UsartTxStart().

int Sc16is752RegRead	(	uint8_t	dev,
		uint8_t	ch,
		uint8_t	reg,
		uint8_t *	val
	)

Definition at line 1233 of file usartsc16is752.c.

Referenced by Sc16is752UsartInit(), Sc16is752UsartInterruptProcessing(), and Sc16is752UsartTxStart().

int selectRegisterSet	(	uint8_t	dev,
		uint8_t	ch,
		uint8_t	reg
	)

Select the register set depending on the register address The device can only address 16 registers directly. The other registers are accessible indirectly only.

Definition at line 1256 of file usartsc16is752.c.

References DEFSEL, ERSSEL, MSR, MYPRINT, REGSEL_MASK, SPR, SRSSEL, TCRBIT, and TCRSEL.

void Sc16is752UsartProcessChannelInterrupt	(	uint8_t	dev,
		uint8_t	ch,
		uint8_t	iir
	)

Definition at line 341 of file usartsc16is752.c.

References _USARTDCB::dcb_rx_rbf, _USARTDCB::dcb_tx_rbf, and _NUTDEVICE::dev_dcb.

Referenced by Sc16is752UsartInterruptProcessing().

void Sc16is752UsartInterruptProcessing ( void * arg )

UART Interrupt Processing Thread

Definition at line 374 of file usartsc16is752.c.

References IIR, MYPRINT, NUT_WAIT_INFINITE, NutEventWait(), NutThreadSetPriority(), Sc16is752RegRead(), and Sc16is752UsartProcessChannelInterrupt().

Referenced by Sc16is752UsartInit().

Here is the call graph for this function:

void Sc16is752UsartEnable	(	uint8_t	dev,
		uint8_t	ch
	)

Carefully enable USART hardware functions.

Always enabale transmitter and receiver, even on read-only or write-only mode. So we can support software flow control.

Definition at line 424 of file usartsc16is752.c.

References printf.

Referenced by Sc16is752UsartSetSpeed().

void Sc16is752UsartDisable	(	uint8_t	dev,
		uint8_t	ch
	)

Carefully disable USART hardware functions.

Definition at line 445 of file usartsc16is752.c.

References printf.

Referenced by Sc16is752UsartSetSpeed().

uint32_t Sc16is752UsartGetSpeed	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware for the selected speed.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: The currently selected baudrate.

Definition at line 476 of file usartsc16is752.c.

References printf.

int Sc16is752UsartSetSpeed	(	uint32_t	rate,
		uint8_t	dev,
		uint8_t	ch
	)

Set the USART hardware bit rate.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Parameters:

rate	Number of bits per second.

Returns:: 0 on success, -1 otherwise.

Definition at line 505 of file usartsc16is752.c.

References printf, Sc16is752UsartDisable(), and Sc16is752UsartEnable().

Here is the call graph for this function:

uint8_t Sc16is752UsartGetDataBits	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware for the number of data bits.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: The number of data bits set.

Definition at line 525 of file usartsc16is752.c.

References printf.

int Sc16is752UsartSetDataBits	(	uint8_t	bits,
		uint8_t	dev,
		uint8_t	ch
	)

Set the USART hardware to the number of data bits.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: 0 on success, -1 otherwise.

Definition at line 562 of file usartsc16is752.c.

References printf.

uint8_t Sc16is752UsartGetParity	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware for the parity mode.

This routine is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: Parity mode, either 0 (disabled), 1 (odd), 2 (even) or 9 (multidrop).

Definition at line 610 of file usartsc16is752.c.

References printf.

int Sc16is752UsartSetParity	(	uint8_t	mode,
		uint8_t	dev,
		uint8_t	ch
	)

Set the USART hardware to the specified parity mode.

This routine is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Parameters:

mode	0 (disabled), 1 (odd) or 2 (even)

Returns:: 0 on success, -1 otherwise.

Definition at line 645 of file usartsc16is752.c.

References printf.

uint8_t Sc16is752UsartGetStopBits	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware for the number of stop bits.

This routine is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: The number of stop bits set, either 1, 2 or 3 (1.5 bits).

Definition at line 684 of file usartsc16is752.c.

References printf.

int Sc16is752UsartSetStopBits	(	uint8_t	bits,
		uint8_t	dev,
		uint8_t	ch
	)

Set the USART hardware to the number of stop bits.

This routine is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: 0 on success, -1 otherwise.

Definition at line 711 of file usartsc16is752.c.

References printf.

uint32_t Sc16is752UsartGetStatus	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware status.

Returns:: Status flags.

Definition at line 747 of file usartsc16is752.c.

References printf.

int Sc16is752UsartSetStatus	(	uint32_t	flags,
		uint8_t	dev,
		uint8_t	ch
	)

Set the USART hardware status.

Parameters:

flags Status flags.

Returns:: 0 on success, -1 otherwise.

Definition at line 820 of file usartsc16is752.c.

References printf.

uint8_t Sc16is752UsartGetClockMode	(	uint8_t	dev,
		uint8_t	ch
	)

Query the USART hardware for synchronous mode.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: Or-ed combination of UART_SYNC, UART_MASTER, UART_NCLOCK and UART_HIGHSPEED.

Definition at line 898 of file usartsc16is752.c.

References printf.

Referenced by Sc16is752UsartSetClockMode().

int Sc16is752UsartSetClockMode	(	uint8_t	mode,
		uint8_t	dev,
		uint8_t	ch
	)

Set asynchronous or synchronous mode.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Parameters:

mode	Must be an or-ed combination of USART_SYNC, USART_MASTER, USART_NCLOCK and USART_HIGHSPEED.

Returns:: 0 on success, -1 otherwise.

Definition at line 919 of file usartsc16is752.c.

References printf, and Sc16is752UsartGetClockMode().

Here is the call graph for this function:

uint32_t Sc16is752UsartGetFlowControl	(	uint8_t	dev,
		uint8_t	ch
	)

Query flow control mode.

This routine is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Returns:: See UsartIOCtl().

Definition at line 941 of file usartsc16is752.c.

References printf, and USART_MF_XONXOFF.

Referenced by Sc16is752UsartSetFlowControl().

int Sc16is752UsartSetFlowControl	(	uint32_t	flags,
		uint8_t	dev,
		uint8_t	ch
	)

Set flow control mode.

This function is called by ioctl function of the upper level USART driver through the USARTDCB jump table.

Parameters:

flags See UsartIOCtl().

Returns:: 0 on success, -1 otherwise.

Definition at line 968 of file usartsc16is752.c.

References printf, and Sc16is752UsartGetFlowControl().

Here is the call graph for this function:

void Sc16is752UsartTxStart	(	uint8_t	dev,
		uint8_t	ch
	)

Start the USART transmitter hardware.

The upper level USART driver will call this function through the USARTDCB jump table each time it added one or more bytes to the transmit buffer.

TODO Check if Tx interrupt is generated immediately or if a first char needs to sent

Definition at line 999 of file usartsc16is752.c.

References IER, printf, Sc16is752RegRead(), and Sc16is752RegWrite().

Here is the call graph for this function:

void Sc16is752UsartRxStart	(	uint8_t	dev,
		uint8_t	ch
	)

Start the USART receiver hardware.

The upper level USART driver will call this function through the USARTDCB jump table each time it removed enough bytes from the receive buffer. Enough means, that the number of bytes left in the buffer is below the low watermark.

Definition at line 1021 of file usartsc16is752.c.

References printf.

int Sc16is752UsartInit	(	uint8_t	dev,
		uint8_t	ch,
		NUTDEVICE *	nutDev,
		IRQ_HANDLER *	irq
	)

Initialize the USART hardware driver.

This function is called during device registration by the upper level USART driver through the USARTDCB jump table.

Returns:: 0 on success, -1 otherwise.

TODO Check if Rx interrupt is generated immediately or if a first char needs to sent

Definition at line 1052 of file usartsc16is752.c.

References DLH, DLL, FCR, IER, INIT_BAUDRATE, LCR, MYPRINT, NUT_IRQMODE_FALLINGEDGE, NutIrqEnable(), NutIrqSetMode(), NutRegisterIrqHandler(), NutThreadCreate(), printf, Sc16is752RegRead(), Sc16is752RegWrite(), and Sc16is752UsartInterruptProcessing().

Here is the call graph for this function:

int Sc16is752UsartDeinit	(	uint8_t	dev,
		uint8_t	ch,
		IRQ_HANDLER *	irq
	)

Deinitialize the USART hardware driver.

This function is called during device deregistration by the upper level USART driver through the USARTDCB jump table.

Returns:: 0 on success, -1 otherwise.

Definition at line 1160 of file usartsc16is752.c.

References NutRegisterIrqHandler(), and printf.

Here is the call graph for this function:

Variable Documentation

NUTDEVICE devUsartAt910

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '0', 0, 0, 0, 0},    
    IFTYP_CHAR,                 
    0,                          
    0,                          
    0,                          
    &dcb_usart0,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 
    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART0 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART0.

The device is named uart0.

Definition at line 137 of file usart0at91.c.

Referenced by AhdlcAt91IOCtl().

NUTDEVICE devUsartAt911

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '1', 0, 0, 0, 0},    
    IFTYP_CHAR,                 
    1,                          
    0,                          
    0,                          
    &dcb_usart1,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 
    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART1 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART1.

The device is named uart1.

Definition at line 137 of file usart1at91.c.

NUTDEVICE devDbguAt91

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', 'd', 0, 0, 0, 0},    
    IFTYP_CHAR,                 
    DBGU_BASE,                  
    0,                          
    0,                          
    &dcb_dbgu,                  
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 
    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART0 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART0.

The device is named uart0.

Definition at line 144 of file usartDat91.c.

NUTDEVICE devUsartsc16is752a

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '_', 'a', 0, 0, 0},    
    IFTYP_CHAR,                 
    (SCDEV<<8)|CH_,              
    0,                          
    0,                          
    &dcb_usarta,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 

    UsartWrite_P,               

    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART0 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART0.

The device is named uarta.

Definition at line 226 of file usart0sc16is752.c.

NUTDEVICE devUsartsc16is752b

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '_', 'b', 0, 0, 0},    
    IFTYP_CHAR,                 
    0,                          
    0,                          
    0,                          
    &dcb_usartb,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 

    UsartWrite_P,               

    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART0 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART0.

The device is named uarta.

Definition at line 234 of file usart1sc16is752.c.

NUTDEVICE devUsartsc16is752c

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '_', 'c', 0, 0, 0},    
    IFTYP_CHAR,                 
    (SCDEV<<8)|CH_,              
    0,                          
    0,                          
    &dcb_usartc,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 

    UsartWrite_P,               

    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART2 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART2.

The device is named uartc.

Definition at line 234 of file usart2sc16is752.c.

NUTDEVICE devUsartsc16is752d

Initial value:

 {
    0,                          
    {'u', 'a', 'r', 't', '_', 'd', 0, 0, 0},    
    IFTYP_CHAR,                 
    (SCDEV<<8)|CH_,              
    0,                          
    0,                          
    &dcb_usartd,                
    UsartInit,                  
    UsartIOCtl,                 
    UsartRead,                  
    UsartWrite,                 

    UsartWrite_P,               

    UsartOpen,                  
    UsartClose,                 
    UsartSize                   
}

USART3 device information structure.

An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the AT91's on-chip USART3.

The device is named uartd.

Definition at line 80 of file usart3sc16is752.c.

Defines

Functions

USART Control Register

Mode Register

Status and Interrupt Register

Receiver Holding Register

Transmitter Holding Register

Baud Rate Generator Register

Receiver Timeout Register

Transmitter Time Guard Register

FI DI Ratio Register

Error Counter Register

IrDA Filter Register

AT91 USART0 Device

AT91 USART1 Device

AT91 DBGU Device

SC16IS752 USARTa Device

SC16IS752 USARTa Device

SC16IS752 USARTc Device

SC16IS752 USARTd Device

Detailed Description

Define Documentation

Function Documentation

Variable Documentation