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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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Static memory controller registers. More...
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SMC Setup Register | |
| #define | SMC_SETUP(cs) (SMC_BASE + 0x10 * cs + 0x00) |
| SMC setup register address. | |
| #define | SMC_NWE_SETUP 0x0000003F |
| NWE setup length mask. | |
| #define | SMC_NWE_SETUP_LSB 0 |
| NWE setup length LSB. | |
| #define | SMC_NCS_WR_SETUP 0x00003F00 |
| NCS setup length in write access mask. | |
| #define | SMC_NCS_WR_SETUP_LSB 8 |
| NCS setup length in write access LSB. | |
| #define | SMC_NRD_SETUP 0x003F0000 |
| NRD setup length mask. | |
| #define | SMC_NRD_SETUP_LSB 16 |
| NRD setup length LSB. | |
| #define | SMC_NCS_RD_SETUP 0x3F000000 |
| NCS setup length in read access mask. | |
| #define | SMC_NCS_RD_SETUP_LSB 24 |
| NCS setup length in read access LSB. | |
SMC Pulse Register | |
| #define | SMC_PULSE(cs) (SMC_BASE + 0x10 * cs + 0x04) |
| SMC pulse register address. | |
| #define | SMC_NWE_PULSE 0x0000003F |
| NWE pulse length mask. | |
| #define | SMC_NWE_PULSE_LSB 0 |
| NWE pulse length LSB. | |
| #define | SMC_NCS_WR_PULSE 0x00003F00 |
| NCS pulse length in write access mask. | |
| #define | SMC_NCS_WR_PULSE_LSB 8 |
| NCS pulse length in write access LSB. | |
| #define | SMC_NRD_PULSE 0x003F0000 |
| NRD pulse length mask. | |
| #define | SMC_NRD_PULSE_LSB 16 |
| NRD pulse length LSB. | |
| #define | SMC_NCS_RD_PULSE 0x3F000000 |
| NCS pulse length in read access mask. | |
| #define | SMC_NCS_RD_PULSE_LSB 24 |
| NCS pulse length in read access LSB. | |
SMC Cycle Register | |
| #define | SMC_CYCLE(cs) (SMC_BASE + 0x10 * cs + 0x08) |
| SMC cycle register address. | |
| #define | SMC_NWE_CYCLE 0x000001FF |
| Total write cycle length mask. | |
| #define | SMC_NWE_CYCLE_LSB 0 |
| Total write cycle length LSB. | |
| #define | SMC_NRD_CYCLE 0x01FF0000 |
| Total read cycle length mask. | |
| #define | SMC_NRD_CYCLE_LSB 16 |
| Total read cycle length LSB. | |
SMC Mode Register | |
| #define | SMC_MODE(cs) (SMC_BASE + 0x10 * cs + 0x0C) |
| SMC mode register address. | |
| #define | SMC_READ_MODE 0x00000001 |
| Read operation mode. | |
| #define | SMC_WRITE_MODE 0x00000002 |
| Write operation mode. | |
| #define | SMC_EXNW_MODE 0x00000030 |
| NWAIT mode mask. | |
| #define | SMC_EXNW_MODE_DISABLED 0x00000000 |
| NWAIT mode mask. | |
| #define | SMC_EXNW_MODE_FROZEN 0x00000020 |
| NWAIT mode mask. | |
| #define | SMC_EXNW_MODE_READY 0x00000030 |
| NWAIT mode mask. | |
| #define | SMC_BAT 0x00000100 |
| Byte access mode. | |
| #define | SMC_DBW 0x00003000 |
| Data bus width. | |
| #define | SMC_DBW_8 0x00000000 |
| 8-bit data bus. | |
| #define | SMC_DBW_16 0x00001000 |
| 16-bit data bus. | |
| #define | SMC_DBW_32 0x00002000 |
| 32-bit data bus. | |
| #define | SMC_TDF_CYCLES 0x000F0000 |
| Data float time mask. | |
| #define | SMC_TDF_CYCLES_LSB 16 |
| Data float time LSB. | |
| #define | SMC_TDF_MODE 0x00100000 |
| TDF optimization. | |
| #define | SMC_PMEN 0x01000000 |
| Page mode enable. | |
| #define | SMC_PS 0x30000000 |
| Page size mask. | |
| #define | SMC_PS_4 0x00000000 |
| 4-byte page. | |
| #define | SMC_PS_8 0x10000000 |
| 8-byte page. | |
| #define | SMC_PS_16 0x20000000 |
| 16-byte page. | |
| #define | SMC_PS_32 0x30000000 |
| 32-byte page. | |
Static memory controller registers.
| #define SMC_SETUP | ( | cs | ) | (SMC_BASE + 0x10 * cs + 0x00) |
SMC setup register address.
Definition at line 87 of file at91_smc.h.
| #define SMC_NWE_SETUP 0x0000003F |
NWE setup length mask.
Definition at line 88 of file at91_smc.h.
| #define SMC_NWE_SETUP_LSB 0 |
NWE setup length LSB.
Definition at line 89 of file at91_smc.h.
| #define SMC_NCS_WR_SETUP 0x00003F00 |
NCS setup length in write access mask.
Definition at line 90 of file at91_smc.h.
| #define SMC_NCS_WR_SETUP_LSB 8 |
NCS setup length in write access LSB.
Definition at line 91 of file at91_smc.h.
| #define SMC_NRD_SETUP 0x003F0000 |
NRD setup length mask.
Definition at line 92 of file at91_smc.h.
| #define SMC_NRD_SETUP_LSB 16 |
NRD setup length LSB.
Definition at line 93 of file at91_smc.h.
| #define SMC_NCS_RD_SETUP 0x3F000000 |
NCS setup length in read access mask.
Definition at line 94 of file at91_smc.h.
| #define SMC_NCS_RD_SETUP_LSB 24 |
NCS setup length in read access LSB.
Definition at line 95 of file at91_smc.h.
| #define SMC_PULSE | ( | cs | ) | (SMC_BASE + 0x10 * cs + 0x04) |
SMC pulse register address.
Definition at line 100 of file at91_smc.h.
| #define SMC_NWE_PULSE 0x0000003F |
NWE pulse length mask.
Definition at line 101 of file at91_smc.h.
| #define SMC_NWE_PULSE_LSB 0 |
NWE pulse length LSB.
Definition at line 102 of file at91_smc.h.
| #define SMC_NCS_WR_PULSE 0x00003F00 |
NCS pulse length in write access mask.
Definition at line 103 of file at91_smc.h.
| #define SMC_NCS_WR_PULSE_LSB 8 |
NCS pulse length in write access LSB.
Definition at line 104 of file at91_smc.h.
| #define SMC_NRD_PULSE 0x003F0000 |
NRD pulse length mask.
Definition at line 105 of file at91_smc.h.
| #define SMC_NRD_PULSE_LSB 16 |
NRD pulse length LSB.
Definition at line 106 of file at91_smc.h.
| #define SMC_NCS_RD_PULSE 0x3F000000 |
NCS pulse length in read access mask.
Definition at line 107 of file at91_smc.h.
| #define SMC_NCS_RD_PULSE_LSB 24 |
NCS pulse length in read access LSB.
Definition at line 108 of file at91_smc.h.
| #define SMC_CYCLE | ( | cs | ) | (SMC_BASE + 0x10 * cs + 0x08) |
SMC cycle register address.
Definition at line 113 of file at91_smc.h.
| #define SMC_NWE_CYCLE 0x000001FF |
Total write cycle length mask.
Definition at line 114 of file at91_smc.h.
| #define SMC_NWE_CYCLE_LSB 0 |
Total write cycle length LSB.
Definition at line 115 of file at91_smc.h.
| #define SMC_NRD_CYCLE 0x01FF0000 |
Total read cycle length mask.
Definition at line 116 of file at91_smc.h.
| #define SMC_NRD_CYCLE_LSB 16 |
Total read cycle length LSB.
Definition at line 117 of file at91_smc.h.
| #define SMC_MODE | ( | cs | ) | (SMC_BASE + 0x10 * cs + 0x0C) |
SMC mode register address.
Definition at line 122 of file at91_smc.h.
| #define SMC_READ_MODE 0x00000001 |
Read operation mode.
Definition at line 123 of file at91_smc.h.
| #define SMC_WRITE_MODE 0x00000002 |
Write operation mode.
Definition at line 124 of file at91_smc.h.
| #define SMC_EXNW_MODE 0x00000030 |
NWAIT mode mask.
Definition at line 125 of file at91_smc.h.
| #define SMC_EXNW_MODE_DISABLED 0x00000000 |
NWAIT mode mask.
Definition at line 126 of file at91_smc.h.
| #define SMC_EXNW_MODE_FROZEN 0x00000020 |
NWAIT mode mask.
Definition at line 127 of file at91_smc.h.
| #define SMC_EXNW_MODE_READY 0x00000030 |
NWAIT mode mask.
Definition at line 128 of file at91_smc.h.
| #define SMC_BAT 0x00000100 |
| #define SMC_DBW 0x00003000 |
Data bus width.
Definition at line 130 of file at91_smc.h.
| #define SMC_DBW_8 0x00000000 |
8-bit data bus.
Definition at line 131 of file at91_smc.h.
| #define SMC_DBW_16 0x00001000 |
| #define SMC_DBW_32 0x00002000 |
32-bit data bus.
Definition at line 133 of file at91_smc.h.
| #define SMC_TDF_CYCLES 0x000F0000 |
Data float time mask.
Definition at line 134 of file at91_smc.h.
| #define SMC_TDF_CYCLES_LSB 16 |
Data float time LSB.
Definition at line 135 of file at91_smc.h.
| #define SMC_TDF_MODE 0x00100000 |
TDF optimization.
Definition at line 136 of file at91_smc.h.
| #define SMC_PMEN 0x01000000 |
Page mode enable.
Definition at line 137 of file at91_smc.h.
| #define SMC_PS 0x30000000 |
Page size mask.
Definition at line 138 of file at91_smc.h.
| #define SMC_PS_4 0x00000000 |
4-byte page.
Definition at line 139 of file at91_smc.h.
| #define SMC_PS_8 0x10000000 |
8-byte page.
Definition at line 140 of file at91_smc.h.
| #define SMC_PS_16 0x20000000 |
16-byte page.
Definition at line 141 of file at91_smc.h.
| #define SMC_PS_32 0x30000000 |
32-byte page.
Definition at line 142 of file at91_smc.h.