Go to the documentation of this file.00001 #ifndef _ARCH_ARM_AT91_SMC_H_
00002 #define _ARCH_ARM_AT91_SMC_H_
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00057
00058 #if defined(SMC_HAS_CSR)
00059
00060 #define SMC_CSR(cs) (SMC_BASE + cs * 0x04)
00062 #define SMC_NWS 0x0000007F
00063 #define SMC_NWS_LSB 0
00064 #define SMC_WSEN 0x00000080
00065 #define SMC_TDF 0x00000F00
00066 #define SMC_TDF_LSB 8
00067 #define SMC_BAT 0x00001000
00068 #define SMC_DBW 0x00006000
00069 #define SMC_DBW_16 0x00002000
00070 #define SMC_DBW_8 0x00004000
00071 #define SMC_DRP 0x00008000
00072 #define SMC_ACSS 0x00030000
00073 #define SMC_ACSS_LSB 16
00074 #define SMC_ACSS_STANDARD 0x00000000
00075 #define SMC_ACSS_1_CYCLE 0x00010000
00076 #define SMC_ACSS_2_CYCLES 0x00020000
00077 #define SMC_ACSS_3_CYCLES 0x00030000
00078 #define SMC_RWSETUP 0x07000000
00079 #define SMC_RWSETUP_LSB 24
00080 #define SMC_RWHOLD 0x70000000
00081 #define SMC_RWHOLD_LSB 28
00083 #else
00084
00087 #define SMC_SETUP(cs) (SMC_BASE + 0x10 * cs + 0x00)
00088 #define SMC_NWE_SETUP 0x0000003F
00089 #define SMC_NWE_SETUP_LSB 0
00090 #define SMC_NCS_WR_SETUP 0x00003F00
00091 #define SMC_NCS_WR_SETUP_LSB 8
00092 #define SMC_NRD_SETUP 0x003F0000
00093 #define SMC_NRD_SETUP_LSB 16
00094 #define SMC_NCS_RD_SETUP 0x3F000000
00095 #define SMC_NCS_RD_SETUP_LSB 24
00097
00098
00100 #define SMC_PULSE(cs) (SMC_BASE + 0x10 * cs + 0x04)
00101 #define SMC_NWE_PULSE 0x0000003F
00102 #define SMC_NWE_PULSE_LSB 0
00103 #define SMC_NCS_WR_PULSE 0x00003F00
00104 #define SMC_NCS_WR_PULSE_LSB 8
00105 #define SMC_NRD_PULSE 0x003F0000
00106 #define SMC_NRD_PULSE_LSB 16
00107 #define SMC_NCS_RD_PULSE 0x3F000000
00108 #define SMC_NCS_RD_PULSE_LSB 24
00110
00111
00113 #define SMC_CYCLE(cs) (SMC_BASE + 0x10 * cs + 0x08)
00114 #define SMC_NWE_CYCLE 0x000001FF
00115 #define SMC_NWE_CYCLE_LSB 0
00116 #define SMC_NRD_CYCLE 0x01FF0000
00117 #define SMC_NRD_CYCLE_LSB 16
00119
00120
00122 #define SMC_MODE(cs) (SMC_BASE + 0x10 * cs + 0x0C)
00123 #define SMC_READ_MODE 0x00000001
00124 #define SMC_WRITE_MODE 0x00000002
00125 #define SMC_EXNW_MODE 0x00000030
00126 #define SMC_EXNW_MODE_DISABLED 0x00000000
00127 #define SMC_EXNW_MODE_FROZEN 0x00000020
00128 #define SMC_EXNW_MODE_READY 0x00000030
00129 #define SMC_BAT 0x00000100
00130 #define SMC_DBW 0x00003000
00131 #define SMC_DBW_8 0x00000000
00132 #define SMC_DBW_16 0x00001000
00133 #define SMC_DBW_32 0x00002000
00134 #define SMC_TDF_CYCLES 0x000F0000
00135 #define SMC_TDF_CYCLES_LSB 16
00136 #define SMC_TDF_MODE 0x00100000
00137 #define SMC_PMEN 0x01000000
00138 #define SMC_PS 0x30000000
00139 #define SMC_PS_4 0x00000000
00140 #define SMC_PS_8 0x10000000
00141 #define SMC_PS_16 0x20000000
00142 #define SMC_PS_32 0x30000000
00144
00145 #endif
00146
00150 #endif