at91_sdramc.h File Reference

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SDRAM Controller Mode Register
#define	SDRAMC_MR_OFF   0x00000000
	Mode register offset.
#define	SDRAMC_MR   (SDRAMC_BASE + SDRAMC_MR_OFF)
	Mode register address.
#define	SDRAMC_MODE   0x00000007
	Command mode mask.
#define	SDRAMC_MODE_NORMAL   0x00000000
	Normal mode.
#define	SDRAMC_MODE_NOP   0x00000001
	Issues a NOP command when accessed.
#define	SDRAMC_MODE_PRCGALL   0x00000002
	Issues an "All Banks Precharge" command when accessed.
#define	SDRAMC_MODE_LMR   0x00000003
	Issues a "Load Mode Register" command when accessed.
#define	SDRAMC_MODE_RFSH   0x00000004
	Issues a "Auto Refresh" command when accessed.
#define	SDRAMC_MODE_EXT_LMR   0x00000005
	Issues a "Extended Load Mode Register" command when accessed.
#define	SDRAMC_MODE_DEEP   0x00000006
	Enters deep power down mode.
SDRAM Controller Refresh Timer Register
#define	SDRAMC_TR_OFF   0x00000004
	Refresh timer register offset.
#define	SDRAMC_TR   (SDRAMC_BASE + SDRAMC_TR_OFF)
	Refresh timer register address.
#define	SDRAMC_COUNT   0x00000FFF
	Refresh timer count mask.
SDRAM Controller Configuration Register
#define	SDRAMC_CR_OFF   0x00000008
	Configuration register offset.
#define	SDRAMC_CR   (SDRAMC_BASE + SDRAMC_CR_OFF)
	Configuration register address.
#define	SDRAMC_NC   0x00000003
	Number of column bits.
#define	SDRAMC_NC_8   0x00000000
	8 column bits.
#define	SDRAMC_NC_9   0x00000001
	9 column bits.
#define	SDRAMC_NC_10   0x00000002
	10 column bits.
#define	SDRAMC_NC_11   0x00000003
	11 column bits.
#define	SDRAMC_NR   0x0000000C
	Number of row bits.
#define	SDRAMC_NR_11   0x00000000
	11 row bits.
#define	SDRAMC_NR_12   0x00000004
	12 row bits.
#define	SDRAMC_NR_13   0x00000008
	13 row bits.
#define	SDRAMC_NB   0x00000010
	4 banks.
#define	SDRAMC_CAS   0x00000060
	CAS latency.
#define	SDRAMC_CAS_1   0x00000020
	CAS latency of 1 cycle.
#define	SDRAMC_CAS_2   0x00000040
	CAS latency of 2 cycles.
#define	SDRAMC_CAS_3   0x00000060
	CAS latency of 3 cycles.
#define	SDRAMC_DBW   0x00000080
	16-bit data bus.
#define	SDRAMC_TWR   0x00000F00
	Write recovery delay.
#define	SDRAMC_TWR_LSB   8
	Write recovery delay.
#define	SDRAMC_TRC   0x0000F000
	Row cycle delay.
#define	SDRAMC_TRC_LSB   12
	Row cycle delay.
#define	SDRAMC_TRP   0x000F0000
	Row precharge delay.
#define	SDRAMC_TRP_LSB   16
	Row precharge delay.
#define	SDRAMC_TRCD   0x00F00000
	Row to column delay.
#define	SDRAMC_TRCD_LSB   20
	Row to column delay.
#define	SDRAMC_TRAS   0x0F000000
	Active to precharge delay.
#define	SDRAMC_TRAS_LSB   24
	Active to precharge delay.
#define	SDRAMC_TXSR   0xF0000000
	Exit self refresh to active delay.
#define	SDRAMC_TXSR_LSB   28
	Exit self refresh to active delay.
SDRAM Controller Low Power Register
#define	SDRAMC_SRR_OFF   0x0000000C
	Self refresh register offset.
#define	SDRAMC_SRR   (SDRAMC_BASE + SDRAMC_SRR_OFF)
	Self refresh register address.
#define	SDRAMC_SRCB   0x00000001
	Self refresh command bit.
#define	SDRAMC_LPR_OFF   0x00000010
	Low power register offset.
#define	SDRAMC_LPR   (SDRAMC_BASE + SDRAMC_LPR_OFF)
	Low power register address.
#define	SDRAMC_LPCB   0x00000003
	Low power configuration mask.
#define	SDRAMC_LPCB_DISABLE   0x00000000
	Low power feature disabled.
#define	SDRAMC_LPCB_SELF_REFRESH   0x00000001
	Enable self refresh.
#define	SDRAMC_LPCB_POWER_DOWN   0x00000002
	Issues a "Power Down" command when accessed..
#define	SDRAMC_LPCB_DEEP_POWER_DOWN   0x00000003
	Enters deep power down mode.
#define	SDRAMC_PASR   0x00000070
	Partial array self-refresh mask.
#define	SDRAMC_PASR_LSB   4
	Partial array self-refresh LSB.
#define	SDRAMC_TCSR   0x00000300
	Temperature compensated self-refresh mask.
#define	SDRAMC_TCSR_LSB   8
	Temperature compensated self-refresh LSB.
#define	SDRAMC_DS   0x00000C00
	Drive strength mask.
#define	SDRAMC_DS_LSB   10
	Drive strength LSB.
#define	SDRAMC_TIMEOUT   0x00003000
	Mask of time to define when low-power mode is enabled.
#define	SDRAMC_TIMEOUT_0   0x00000000
	Activate immediately.
#define	SDRAMC_TIMEOUT_64   0x00001000
	Activate after 64 clock cycles after the end of the last transfer.
#define	SDRAMC_TIMEOUT_128   0x00002000
	Activate after 64 clock cycles after the end of the last transfer.
SDRAM Controller Interrupt Registers
#define	SDRAMC_IER_OFF   0x00000014
	Interrupt enable register offset.
#define	SDRAMC_IER   (SDRAMC_BASE + SDRAMC_IER_OFF)
	Interrupt enable register address.
#define	SDRAMC_IDR_OFF   0x00000018
	Interrupt disable register offset.
#define	SDRAMC_IDR   (SDRAMC_BASE + SDRAMC_IDR_OFF)
	Interrupt disable register address.
#define	SDRAMC_IMR_OFF   0x0000001C
	Interrupt mask register offset.
#define	SDRAMC_IMR   (SDRAMC_BASE + SDRAMC_IMR_OFF)
	Interrupt mask register address.
#define	SDRAMC_ISR_OFF   0x00000020
	Interrupt status register offset.
#define	SDRAMC_ISR   (SDRAMC_BASE + SDRAMC_ISR_OFF)
	Interrupt status register address.
#define	SDRAMC_RES   0x00000001
	Refresh error status.
SDRAM Controller Memory Device Register
#define	SDRAMC_MDR_OFF   0x00000024
	Memory device register offset.
#define	SDRAMC_MDR   (SDRAMC_BASE + SDRAMC_MDR_OFF)
	Memory device register address.
#define	SDRAMC_MD   0x00000003
	Memory device type mask.
#define	SDRAMC_MD   0x00000003
	Memory device type mask.
#define	SDRAMC_MD_SDRAM   0x00000000
	SDRAM.
#define	SDRAMC_MD_LPSDRAM   0x00000001
	Low power SDRAM.