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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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SDRAM controller registers. More...
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SDRAM Controller Mode Register | |
| #define | SDRAMC_MR_OFF 0x00000000 |
| Mode register offset. | |
| #define | SDRAMC_MR (SDRAMC_BASE + SDRAMC_MR_OFF) |
| Mode register address. | |
| #define | SDRAMC_MODE 0x00000007 |
| Command mode mask. | |
| #define | SDRAMC_MODE_NORMAL 0x00000000 |
| Normal mode. | |
| #define | SDRAMC_MODE_NOP 0x00000001 |
| Issues a NOP command when accessed. | |
| #define | SDRAMC_MODE_PRCGALL 0x00000002 |
| Issues an "All Banks Precharge" command when accessed. | |
| #define | SDRAMC_MODE_LMR 0x00000003 |
| Issues a "Load Mode Register" command when accessed. | |
| #define | SDRAMC_MODE_RFSH 0x00000004 |
| Issues a "Auto Refresh" command when accessed. | |
| #define | SDRAMC_MODE_EXT_LMR 0x00000005 |
| Issues a "Extended Load Mode Register" command when accessed. | |
| #define | SDRAMC_MODE_DEEP 0x00000006 |
| Enters deep power down mode. | |
SDRAM Controller Refresh Timer Register | |
| #define | SDRAMC_TR_OFF 0x00000004 |
| Refresh timer register offset. | |
| #define | SDRAMC_TR (SDRAMC_BASE + SDRAMC_TR_OFF) |
| Refresh timer register address. | |
| #define | SDRAMC_COUNT 0x00000FFF |
| Refresh timer count mask. | |
SDRAM Controller Configuration Register | |
| #define | SDRAMC_CR_OFF 0x00000008 |
| Configuration register offset. | |
| #define | SDRAMC_CR (SDRAMC_BASE + SDRAMC_CR_OFF) |
| Configuration register address. | |
| #define | SDRAMC_NC 0x00000003 |
| Number of column bits. | |
| #define | SDRAMC_NC_8 0x00000000 |
| 8 column bits. | |
| #define | SDRAMC_NC_9 0x00000001 |
| 9 column bits. | |
| #define | SDRAMC_NC_10 0x00000002 |
| 10 column bits. | |
| #define | SDRAMC_NC_11 0x00000003 |
| 11 column bits. | |
| #define | SDRAMC_NR 0x0000000C |
| Number of row bits. | |
| #define | SDRAMC_NR_11 0x00000000 |
| 11 row bits. | |
| #define | SDRAMC_NR_12 0x00000004 |
| 12 row bits. | |
| #define | SDRAMC_NR_13 0x00000008 |
| 13 row bits. | |
| #define | SDRAMC_NB 0x00000010 |
| 4 banks. | |
| #define | SDRAMC_CAS 0x00000060 |
| CAS latency. | |
| #define | SDRAMC_CAS_1 0x00000020 |
| CAS latency of 1 cycle. | |
| #define | SDRAMC_CAS_2 0x00000040 |
| CAS latency of 2 cycles. | |
| #define | SDRAMC_CAS_3 0x00000060 |
| CAS latency of 3 cycles. | |
| #define | SDRAMC_DBW 0x00000080 |
| 16-bit data bus. | |
| #define | SDRAMC_TWR 0x00000F00 |
| Write recovery delay. | |
| #define | SDRAMC_TWR_LSB 8 |
| Write recovery delay. | |
| #define | SDRAMC_TRC 0x0000F000 |
| Row cycle delay. | |
| #define | SDRAMC_TRC_LSB 12 |
| Row cycle delay. | |
| #define | SDRAMC_TRP 0x000F0000 |
| Row precharge delay. | |
| #define | SDRAMC_TRP_LSB 16 |
| Row precharge delay. | |
| #define | SDRAMC_TRCD 0x00F00000 |
| Row to column delay. | |
| #define | SDRAMC_TRCD_LSB 20 |
| Row to column delay. | |
| #define | SDRAMC_TRAS 0x0F000000 |
| Active to precharge delay. | |
| #define | SDRAMC_TRAS_LSB 24 |
| Active to precharge delay. | |
| #define | SDRAMC_TXSR 0xF0000000 |
| Exit self refresh to active delay. | |
| #define | SDRAMC_TXSR_LSB 28 |
| Exit self refresh to active delay. | |
SDRAM Controller Low Power Register | |
| #define | SDRAMC_SRR_OFF 0x0000000C |
| Self refresh register offset. | |
| #define | SDRAMC_SRR (SDRAMC_BASE + SDRAMC_SRR_OFF) |
| Self refresh register address. | |
| #define | SDRAMC_SRCB 0x00000001 |
| Self refresh command bit. | |
| #define | SDRAMC_LPR_OFF 0x00000010 |
| Low power register offset. | |
| #define | SDRAMC_LPR (SDRAMC_BASE + SDRAMC_LPR_OFF) |
| Low power register address. | |
| #define | SDRAMC_LPCB 0x00000003 |
| Low power configuration mask. | |
| #define | SDRAMC_LPCB_DISABLE 0x00000000 |
| Low power feature disabled. | |
| #define | SDRAMC_LPCB_SELF_REFRESH 0x00000001 |
| Enable self refresh. | |
| #define | SDRAMC_LPCB_POWER_DOWN 0x00000002 |
| Issues a "Power Down" command when accessed.. | |
| #define | SDRAMC_LPCB_DEEP_POWER_DOWN 0x00000003 |
| Enters deep power down mode. | |
| #define | SDRAMC_PASR 0x00000070 |
| Partial array self-refresh mask. | |
| #define | SDRAMC_PASR_LSB 4 |
| Partial array self-refresh LSB. | |
| #define | SDRAMC_TCSR 0x00000300 |
| Temperature compensated self-refresh mask. | |
| #define | SDRAMC_TCSR_LSB 8 |
| Temperature compensated self-refresh LSB. | |
| #define | SDRAMC_DS 0x00000C00 |
| Drive strength mask. | |
| #define | SDRAMC_DS_LSB 10 |
| Drive strength LSB. | |
| #define | SDRAMC_TIMEOUT 0x00003000 |
| Mask of time to define when low-power mode is enabled. | |
| #define | SDRAMC_TIMEOUT_0 0x00000000 |
| Activate immediately. | |
| #define | SDRAMC_TIMEOUT_64 0x00001000 |
| Activate after 64 clock cycles after the end of the last transfer. | |
| #define | SDRAMC_TIMEOUT_128 0x00002000 |
| Activate after 64 clock cycles after the end of the last transfer. | |
SDRAM Controller Interrupt Registers | |
| #define | SDRAMC_IER_OFF 0x00000014 |
| Interrupt enable register offset. | |
| #define | SDRAMC_IER (SDRAMC_BASE + SDRAMC_IER_OFF) |
| Interrupt enable register address. | |
| #define | SDRAMC_IDR_OFF 0x00000018 |
| Interrupt disable register offset. | |
| #define | SDRAMC_IDR (SDRAMC_BASE + SDRAMC_IDR_OFF) |
| Interrupt disable register address. | |
| #define | SDRAMC_IMR_OFF 0x0000001C |
| Interrupt mask register offset. | |
| #define | SDRAMC_IMR (SDRAMC_BASE + SDRAMC_IMR_OFF) |
| Interrupt mask register address. | |
| #define | SDRAMC_ISR_OFF 0x00000020 |
| Interrupt status register offset. | |
| #define | SDRAMC_ISR (SDRAMC_BASE + SDRAMC_ISR_OFF) |
| Interrupt status register address. | |
| #define | SDRAMC_RES 0x00000001 |
| Refresh error status. | |
SDRAM Controller Memory Device Register | |
| #define | SDRAMC_MDR_OFF 0x00000024 |
| Memory device register offset. | |
| #define | SDRAMC_MDR (SDRAMC_BASE + SDRAMC_MDR_OFF) |
| Memory device register address. | |
| #define | SDRAMC_MD 0x00000003 |
| Memory device type mask. | |
| #define | SDRAMC_MD 0x00000003 |
| Memory device type mask. | |
| #define | SDRAMC_MD_SDRAM 0x00000000 |
| SDRAM. | |
| #define | SDRAMC_MD_LPSDRAM 0x00000001 |
| Low power SDRAM. | |
SDRAM controller registers.
| #define SDRAMC_MR_OFF 0x00000000 |
Mode register offset.
Definition at line 60 of file at91_sdramc.h.
| #define SDRAMC_MR (SDRAMC_BASE + SDRAMC_MR_OFF) |
Mode register address.
Definition at line 61 of file at91_sdramc.h.
| #define SDRAMC_MODE 0x00000007 |
Command mode mask.
Definition at line 62 of file at91_sdramc.h.
| #define SDRAMC_MODE_NORMAL 0x00000000 |
Normal mode.
Definition at line 63 of file at91_sdramc.h.
| #define SDRAMC_MODE_NOP 0x00000001 |
Issues a NOP command when accessed.
Definition at line 64 of file at91_sdramc.h.
| #define SDRAMC_MODE_PRCGALL 0x00000002 |
Issues an "All Banks Precharge" command when accessed.
Definition at line 65 of file at91_sdramc.h.
| #define SDRAMC_MODE_LMR 0x00000003 |
Issues a "Load Mode Register" command when accessed.
Definition at line 66 of file at91_sdramc.h.
| #define SDRAMC_MODE_RFSH 0x00000004 |
Issues a "Auto Refresh" command when accessed.
Definition at line 67 of file at91_sdramc.h.
| #define SDRAMC_MODE_EXT_LMR 0x00000005 |
Issues a "Extended Load Mode Register" command when accessed.
Definition at line 68 of file at91_sdramc.h.
| #define SDRAMC_MODE_DEEP 0x00000006 |
Enters deep power down mode.
Definition at line 69 of file at91_sdramc.h.
| #define SDRAMC_TR_OFF 0x00000004 |
Refresh timer register offset.
Definition at line 77 of file at91_sdramc.h.
| #define SDRAMC_TR (SDRAMC_BASE + SDRAMC_TR_OFF) |
Refresh timer register address.
Definition at line 78 of file at91_sdramc.h.
| #define SDRAMC_COUNT 0x00000FFF |
Refresh timer count mask.
Definition at line 79 of file at91_sdramc.h.
| #define SDRAMC_CR_OFF 0x00000008 |
Configuration register offset.
Definition at line 84 of file at91_sdramc.h.
| #define SDRAMC_CR (SDRAMC_BASE + SDRAMC_CR_OFF) |
Configuration register address.
Definition at line 85 of file at91_sdramc.h.
| #define SDRAMC_NC 0x00000003 |
Number of column bits.
Definition at line 86 of file at91_sdramc.h.
| #define SDRAMC_NC_8 0x00000000 |
8 column bits.
Definition at line 87 of file at91_sdramc.h.
| #define SDRAMC_NC_9 0x00000001 |
9 column bits.
Definition at line 88 of file at91_sdramc.h.
| #define SDRAMC_NC_10 0x00000002 |
10 column bits.
Definition at line 89 of file at91_sdramc.h.
| #define SDRAMC_NC_11 0x00000003 |
11 column bits.
Definition at line 90 of file at91_sdramc.h.
| #define SDRAMC_NR 0x0000000C |
Number of row bits.
Definition at line 91 of file at91_sdramc.h.
| #define SDRAMC_NR_11 0x00000000 |
11 row bits.
Definition at line 92 of file at91_sdramc.h.
| #define SDRAMC_NR_12 0x00000004 |
12 row bits.
Definition at line 93 of file at91_sdramc.h.
| #define SDRAMC_NR_13 0x00000008 |
13 row bits.
Definition at line 94 of file at91_sdramc.h.
| #define SDRAMC_NB 0x00000010 |
4 banks.
Definition at line 95 of file at91_sdramc.h.
| #define SDRAMC_CAS 0x00000060 |
CAS latency.
Definition at line 96 of file at91_sdramc.h.
| #define SDRAMC_CAS_1 0x00000020 |
CAS latency of 1 cycle.
Definition at line 97 of file at91_sdramc.h.
| #define SDRAMC_CAS_2 0x00000040 |
CAS latency of 2 cycles.
Definition at line 98 of file at91_sdramc.h.
| #define SDRAMC_CAS_3 0x00000060 |
CAS latency of 3 cycles.
Definition at line 99 of file at91_sdramc.h.
| #define SDRAMC_DBW 0x00000080 |
16-bit data bus.
Definition at line 114 of file at91_sdramc.h.
| #define SDRAMC_TWR 0x00000F00 |
Write recovery delay.
Definition at line 115 of file at91_sdramc.h.
| #define SDRAMC_TWR_LSB 8 |
Write recovery delay.
Definition at line 116 of file at91_sdramc.h.
| #define SDRAMC_TRC 0x0000F000 |
Row cycle delay.
Definition at line 117 of file at91_sdramc.h.
| #define SDRAMC_TRC_LSB 12 |
Row cycle delay.
Definition at line 118 of file at91_sdramc.h.
| #define SDRAMC_TRP 0x000F0000 |
Row precharge delay.
Definition at line 119 of file at91_sdramc.h.
| #define SDRAMC_TRP_LSB 16 |
Row precharge delay.
Definition at line 120 of file at91_sdramc.h.
| #define SDRAMC_TRCD 0x00F00000 |
Row to column delay.
Definition at line 121 of file at91_sdramc.h.
| #define SDRAMC_TRCD_LSB 20 |
Row to column delay.
Definition at line 122 of file at91_sdramc.h.
| #define SDRAMC_TRAS 0x0F000000 |
Active to precharge delay.
Definition at line 123 of file at91_sdramc.h.
| #define SDRAMC_TRAS_LSB 24 |
Active to precharge delay.
Definition at line 124 of file at91_sdramc.h.
| #define SDRAMC_TXSR 0xF0000000 |
Exit self refresh to active delay.
Definition at line 125 of file at91_sdramc.h.
| #define SDRAMC_TXSR_LSB 28 |
Exit self refresh to active delay.
Definition at line 126 of file at91_sdramc.h.
| #define SDRAMC_SRR_OFF 0x0000000C |
Self refresh register offset.
Definition at line 132 of file at91_sdramc.h.
| #define SDRAMC_SRR (SDRAMC_BASE + SDRAMC_SRR_OFF) |
Self refresh register address.
Definition at line 133 of file at91_sdramc.h.
| #define SDRAMC_SRCB 0x00000001 |
Self refresh command bit.
Definition at line 134 of file at91_sdramc.h.
| #define SDRAMC_LPR_OFF 0x00000010 |
Low power register offset.
Definition at line 139 of file at91_sdramc.h.
| #define SDRAMC_LPR (SDRAMC_BASE + SDRAMC_LPR_OFF) |
Low power register address.
Definition at line 140 of file at91_sdramc.h.
| #define SDRAMC_LPCB 0x00000003 |
Low power configuration mask.
Definition at line 141 of file at91_sdramc.h.
| #define SDRAMC_LPCB_DISABLE 0x00000000 |
Low power feature disabled.
Definition at line 142 of file at91_sdramc.h.
| #define SDRAMC_LPCB_SELF_REFRESH 0x00000001 |
Enable self refresh.
Definition at line 143 of file at91_sdramc.h.
| #define SDRAMC_LPCB_POWER_DOWN 0x00000002 |
Issues a "Power Down" command when accessed..
Definition at line 144 of file at91_sdramc.h.
| #define SDRAMC_LPCB_DEEP_POWER_DOWN 0x00000003 |
Enters deep power down mode.
Definition at line 145 of file at91_sdramc.h.
| #define SDRAMC_PASR 0x00000070 |
Partial array self-refresh mask.
Definition at line 146 of file at91_sdramc.h.
| #define SDRAMC_PASR_LSB 4 |
Partial array self-refresh LSB.
Definition at line 147 of file at91_sdramc.h.
| #define SDRAMC_TCSR 0x00000300 |
Temperature compensated self-refresh mask.
Definition at line 148 of file at91_sdramc.h.
| #define SDRAMC_TCSR_LSB 8 |
Temperature compensated self-refresh LSB.
Definition at line 149 of file at91_sdramc.h.
| #define SDRAMC_DS 0x00000C00 |
Drive strength mask.
Definition at line 150 of file at91_sdramc.h.
| #define SDRAMC_DS_LSB 10 |
Drive strength LSB.
Definition at line 151 of file at91_sdramc.h.
| #define SDRAMC_TIMEOUT 0x00003000 |
Mask of time to define when low-power mode is enabled.
Definition at line 152 of file at91_sdramc.h.
| #define SDRAMC_TIMEOUT_0 0x00000000 |
Activate immediately.
Definition at line 153 of file at91_sdramc.h.
| #define SDRAMC_TIMEOUT_64 0x00001000 |
Activate after 64 clock cycles after the end of the last transfer.
Definition at line 154 of file at91_sdramc.h.
| #define SDRAMC_TIMEOUT_128 0x00002000 |
Activate after 64 clock cycles after the end of the last transfer.
Definition at line 155 of file at91_sdramc.h.
| #define SDRAMC_IER_OFF 0x00000014 |
Interrupt enable register offset.
Definition at line 160 of file at91_sdramc.h.
| #define SDRAMC_IER (SDRAMC_BASE + SDRAMC_IER_OFF) |
Interrupt enable register address.
Definition at line 161 of file at91_sdramc.h.
| #define SDRAMC_IDR_OFF 0x00000018 |
Interrupt disable register offset.
Definition at line 162 of file at91_sdramc.h.
| #define SDRAMC_IDR (SDRAMC_BASE + SDRAMC_IDR_OFF) |
Interrupt disable register address.
Definition at line 163 of file at91_sdramc.h.
| #define SDRAMC_IMR_OFF 0x0000001C |
Interrupt mask register offset.
Definition at line 164 of file at91_sdramc.h.
| #define SDRAMC_IMR (SDRAMC_BASE + SDRAMC_IMR_OFF) |
Interrupt mask register address.
Definition at line 165 of file at91_sdramc.h.
| #define SDRAMC_ISR_OFF 0x00000020 |
Interrupt status register offset.
Definition at line 166 of file at91_sdramc.h.
| #define SDRAMC_ISR (SDRAMC_BASE + SDRAMC_ISR_OFF) |
Interrupt status register address.
Definition at line 167 of file at91_sdramc.h.
| #define SDRAMC_RES 0x00000001 |
Refresh error status.
Definition at line 168 of file at91_sdramc.h.
| #define SDRAMC_MDR_OFF 0x00000024 |
Memory device register offset.
Definition at line 173 of file at91_sdramc.h.
| #define SDRAMC_MDR (SDRAMC_BASE + SDRAMC_MDR_OFF) |
Memory device register address.
Definition at line 174 of file at91_sdramc.h.
| #define SDRAMC_MD 0x00000003 |
Memory device type mask.
Definition at line 176 of file at91_sdramc.h.
| #define SDRAMC_MD 0x00000003 |
Memory device type mask.
Definition at line 176 of file at91_sdramc.h.
| #define SDRAMC_MD_SDRAM 0x00000000 |
SDRAM.
Definition at line 177 of file at91_sdramc.h.
| #define SDRAMC_MD_LPSDRAM 0x00000001 |
Low power SDRAM.
Definition at line 178 of file at91_sdramc.h.