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ADC Control Register | |
#define | ADC_CR_OFF 0x00000000 |
Control register offset. | |
#define | ADC_CR (ADC_BASE + ADC_CR_OFF) |
Control register address. | |
#define | ADC_SWRST 0x00000001 |
Software reset. | |
#define | ADC_START 0x00000002 |
Start a conversion. | |
ADC Mode Register | |
#define | ADC_MR_OFF 0x00000004 |
Mode register offset. | |
#define | ADC_MR (ADC_BASE + ADC_MR_OFF) |
Mode register address. | |
#define | ADC_TRGEN 0x00000001 |
Hardware trigger enable. | |
#define | ADC_TRGSEL 0x0000000E |
Trigger select mask. | |
#define | ADC_TRGSEL_TIOA0 0x00000000 |
Trigger select timer counter 0 output. | |
#define | ADC_TRGSEL_TIOA1 0x00000002 |
Trigger select timer counter 1 output. | |
#define | ADC_TRGSEL_TIOA2 0x00000004 |
Trigger select timer counter 2 output. | |
#define | ADC_TRGSEL_EXT 0x0000000C |
Single trigger. | |
#define | ADC_LOWRES 0x00000010 |
10bit / 8bit selection | |
#define | ADC_SLEEP 0x00000020 |
Enter sleep mode. | |
#define | ADC_PRESCAL 0x00003F00 |
Prescaler mask. | |
#define | ADC_PRESCAL_LSB 8 |
Prescaler LSB. | |
#define | ADC_STARTUP 0x001F0000 |
Startup time mask. | |
#define | ADC_STARTUP_LSB 16 |
Startup time LSB. | |
#define | ADC_SHTIM 0x0F000000 |
Sample hold time mask. | |
#define | ADC_SHTIM_LSB 24 |
Sample hold time LSB. | |
ADC Channel Enable Register | |
#define | ADC_CHER_OFF 0x00000010 |
Channel enable register offset. | |
#define | ADC_CHER (ADC_BASE + ADC_CHER_OFF) |
Channel enable register address. | |
#define | ADC_CH(x) ((unsigned long)BV(x)) |
macro to access channel by numer | |
#define | ADC_CH0 0x00000001 |
ADC Channel 0. | |
#define | ADC_CH1 0x00000002 |
ADC Channel 1. | |
#define | ADC_CH2 0x00000004 |
ADC Channel 2. | |
#define | ADC_CH3 0x00000008 |
ADC Channel 3. | |
#define | ADC_CH4 0x00000010 |
ADC Channel 4. | |
#define | ADC_CH5 0x00000020 |
ADC Channel 5. | |
#define | ADC_CH6 0x00000040 |
ADC Channel 6. | |
#define | ADC_CH7 0x00000080 |
ADC Channel 7. | |
ADC Channel Disable Register | |
#define | ADC_CHDR_OFF 0x00000014 |
Channel disable register offset. | |
#define | ADC_CHDR (ADC_BASE + ADC_CHDR_OFF) |
Channel disable register address. | |
ADC Channel Status Register | |
#define | ADC_CHSR_OFF 0x00000018 |
Channel status register offset. | |
#define | ADC_CHSR (ADC_BASE + ADC_CHSR_OFF) |
Channel status register address. | |
ADC Status Register | |
#define | ADC_SR_OFF 0x0000001C |
ADC status register offset. | |
#define | ADC_SR (ADC_BASE + ADC_SR_OFF) |
ADC status register address. | |
#define | ADC_EOC(x) ((unsigned long)BV(x)) |
Macro to access EOC flag by channel number. | |
#define | ADC_EOC0 0x00000001 |
End of conversion channel 0. | |
#define | ADC_EOC1 0x00000002 |
End of conversion channel 1. | |
#define | ADC_EOC2 0x00000004 |
End of conversion channel 2. | |
#define | ADC_EOC3 0x00000008 |
End of conversion channel 3. | |
#define | ADC_EOC4 0x00000010 |
End of conversion channel 4. | |
#define | ADC_EOC5 0x00000020 |
End of conversion channel 5. | |
#define | ADC_EOC6 0x00000040 |
End of conversion channel 6. | |
#define | ADC_EOC7 0x00000080 |
End of conversion channel 7. | |
#define | ADC_OVRE(x) ((unsigned long)BV(x+8)) |
Macto to acces overrun error flag by channel number. | |
#define | ADC_OVRE0 0x00000100 |
Overrun error flag channel 0. | |
#define | ADC_OVRE1 0x00000200 |
Overrun error flag channel 1. | |
#define | ADC_OVRE2 0x00000400 |
Overrun error flag channel 2. | |
#define | ADC_OVRE3 0x00000800 |
Overrun error flag channel 3. | |
#define | ADC_OVRE4 0x00001000 |
Overrun error flag channel 4. | |
#define | ADC_OVRE5 0x00002000 |
Overrun error flag channel 5. | |
#define | ADC_OVRE6 0x00004000 |
Overrun error flag channel 6. | |
#define | ADC_OVRE7 0x00008000 |
Overrun error flag channel 7. | |
#define | ADC_DRDY 0x00010000 |
Data ready flag. | |
#define | ADC_GOVRE 0x00020000 |
General data overrun error flag. | |
#define | ADC_ENDRX 0x00040000 |
End of rx buffer flag. | |
#define | ADC_RXBUF 0x00080000 |
Rx buffer full flag. | |
ADC Last Converted Data Register | |
#define | ADC_LCDR_OFF 0x00000020 |
Last converted data register offset. | |
#define | ADC_LCDR (ADC_BASE + ADC_LCDR_OFF) |
Last converted data register. | |
#define | ADC_LCDR_MASK 0x000003FF |
Last converted data mask (10bit) | |
ADC Interrupt Enable Register | |
#define | ADC_IER_OFF 0x00000024 |
Interrupt enable register offset. | |
#define | ADC_IER (ADC_BASE + ADC_IER_OFF) |
Last converted data register. | |
ADC Interrupt Disable Register | |
#define | ADC_IDR_OFF 0x00000028 |
Interrupt disable register offset. | |
#define | ADC_IDR (ADC_BASE + ADC_IDR_OFF) |
Interrupt disable register. | |
ADC Interrupt Mask Register | |
#define | ADC_IMR_OFF 0x0000002C |
Interrupt mask register offset. | |
#define | ADC_IMR (ADC_BASE + ADC_IMR_OFF) |
Interrupt mask register. | |
ADC Channel Data Register | |
#define | ADC_CDR_OFF 0x00000030 |
Channel data register offset. | |
#define | ADC_CDR(x) (ADC_BASE + ADC_CDR_OFF + ((x) << 2)) |
Channel data register. | |
#define | ADC_CDR_MASK 0x000003FF |
Channel data mask (10bit) |