at91_adc.h

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/*
 * Copyright (C) 2004 by Ole Reinhardt <ole.reinhardt@embedded-it.de>,
 *                       Kernelconcepts http://www.embedded-it.de
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the copyright holders nor the names of
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 *
 * For additional information see http://www.ethernut.de/
 *
 */

/*
 * $Log$
 * Revision 1.2  2007/12/09 22:12:49  olereinhardt
 * Added cvs log tag
 *
 */

#ifndef _ARCH_ARM_AT91_ADC_H_
#define _ARCH_ARM_AT91_ADC_H_


#define ADC_CR_OFF              0x00000000      
#define ADC_CR      (ADC_BASE + ADC_CR_OFF)     
#define ADC_SWRST               0x00000001      
#define ADC_START               0x00000002      


#define ADC_MR_OFF              0x00000004      
#define ADC_MR      (ADC_BASE + ADC_MR_OFF)     
#define ADC_TRGEN               0x00000001      
#define ADC_TRGSEL              0x0000000E      
#define   ADC_TRGSEL_TIOA0      0x00000000      
#define   ADC_TRGSEL_TIOA1      0x00000002      
#define   ADC_TRGSEL_TIOA2      0x00000004      
#define   ADC_TRGSEL_EXT        0x0000000C      
#define ADC_LOWRES              0x00000010      
#define ADC_SLEEP               0x00000020      
#define ADC_PRESCAL             0x00003F00      
#define ADC_PRESCAL_LSB         8               
#define ADC_STARTUP             0x001F0000      
#define ADC_STARTUP_LSB         16              
#define ADC_SHTIM               0x0F000000      
#define ADC_SHTIM_LSB           24              


#define ADC_CHER_OFF            0x00000010      
#define ADC_CHER    (ADC_BASE + ADC_CHER_OFF)   
#define ADC_CH(x) ((unsigned long)BV(x))        
#define ADC_CH0                 0x00000001      
#define ADC_CH1                 0x00000002      
#define ADC_CH2                 0x00000004      
#define ADC_CH3                 0x00000008      
#define ADC_CH4                 0x00000010      
#define ADC_CH5                 0x00000020      
#define ADC_CH6                 0x00000040      
#define ADC_CH7                 0x00000080      


#define ADC_CHDR_OFF            0x00000014      
#define ADC_CHDR    (ADC_BASE + ADC_CHDR_OFF)   


#define ADC_CHSR_OFF            0x00000018      
#define ADC_CHSR    (ADC_BASE + ADC_CHSR_OFF)   


#define ADC_SR_OFF              0x0000001C      
#define ADC_SR      (ADC_BASE + ADC_SR_OFF)     
#define ADC_EOC(x)((unsigned long)BV(x))        
#define ADC_EOC0                0x00000001      
#define ADC_EOC1                0x00000002      
#define ADC_EOC2                0x00000004      
#define ADC_EOC3                0x00000008      
#define ADC_EOC4                0x00000010      
#define ADC_EOC5                0x00000020      
#define ADC_EOC6                0x00000040      
#define ADC_EOC7                0x00000080      
#define ADC_OVRE(x)((unsigned long)BV(x+8))     
#define ADC_OVRE0               0x00000100      
#define ADC_OVRE1               0x00000200      
#define ADC_OVRE2               0x00000400      
#define ADC_OVRE3               0x00000800      
#define ADC_OVRE4               0x00001000      
#define ADC_OVRE5               0x00002000      
#define ADC_OVRE6               0x00004000      
#define ADC_OVRE7               0x00008000      
#define ADC_DRDY                0x00010000      
#define ADC_GOVRE               0x00020000      
#define ADC_ENDRX               0x00040000      
#define ADC_RXBUF               0x00080000      


#define ADC_LCDR_OFF            0x00000020      
#define ADC_LCDR    (ADC_BASE + ADC_LCDR_OFF)   
#define ADC_LCDR_MASK           0x000003FF      


#define ADC_IER_OFF             0x00000024      
#define ADC_IER     (ADC_BASE + ADC_IER_OFF)    


#define ADC_IDR_OFF             0x00000028      
#define ADC_IDR     (ADC_BASE + ADC_IDR_OFF)    


#define ADC_IMR_OFF             0x0000002C      
#define ADC_IMR     (ADC_BASE + ADC_IMR_OFF)    


#define ADC_CDR_OFF             0x00000030      
#define ADC_CDR(x) (ADC_BASE + ADC_CDR_OFF + ((x) << 2))    
#define ADC_CDR_MASK           0x000003FF       

#if defined(ADC_HAS_PDC)

#define ADC_RPR    (ADC_BASE + PERIPH_RPR_OFF)  


#define ADC_RCR    (ADC_BASE + PERIPH_RCR_OFF)  


#define ADC_TPR    (ADC_BASE + PERIPH_TPR_OFF)  


#define ADC_TCR    (ADC_BASE + PERIPH_TCR_OFF)  


#define ADC_RNPR   (ADC_BASE + PERIPH_RNPR_OFF) 


#define ADC_RNCR   (ADC_BASE + PERIPH_RNCR_OFF) 


#define ADC_TNPR   (ADC_BASE + PERIPH_TNPR_OFF) 


#define ADC_TNCR   (ADC_BASE + PERIPH_TNCR_OFF) 


#define ADC_PTCR   (ADC_BASE + PERIPH_PTCR_OFF) 


#define ADC_PTSR   (ADC_BASE + PERIPH_PTSR_OFF) 

#endif


#endif