System Control InterFace(SCIF) driver. More...

#include "compiler.h"
#include "scif_uc3l.h"

Include dependency graph for scif_uc3l.c:

Data Structures
union	u_avr32_scif_oscctrl0_t
union	u_avr32_scif_oscctrl32_t
union	u_avr32_scif_dfll0conf_t
union	u_avr32_scif_dfll0ssg_t
Defines
#define	SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
#define	SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)
#define	SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))
Enumerations
enum	scif_dfll_mode_t { SCIF_DFLL0_MODE_OPENLOOP = 0, SCIF_DFLL0_MODE_CLOSEDLOOP }
	The different DFLL0 modes. More...
Functions
long int	scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
	Configure and start an OSC0/OSC1 oscillator.
bool	scif_is_osc_ready (scif_osc_t osc)
	Is an oscillator stable and ready to be used as clock source?
long int	scif_stop_osc (scif_osc_t osc)
	Stop an oscillator.
long int	scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal)
	Configure an oscillator in crystal mode.
long int	scif_configure_osc_extmode (scif_osc_t osc)
	Configure an external clock as input clock.
long int	scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready)
	Enable an oscillator with a given startup time.
long int	scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready)
	Configure and start the OSC32 oscillator.
long	scif_stop_osc32 ()
	Stop the OSC32 oscillator.
long int	scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig)
	Configure and start the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz)
	Automatic configuration and start of the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig)
	Update the frequency of the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_stop (void)
	Stop the DFLL0 in open loop mode.
long int	scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf)
	Configure and enable the SSG.
long int	scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig)
	Configure and start the DFLL0 in closed loop mode.
long int	scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg)
	Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
void	scif_start_rc120M (void)
	Start the 120MHz internal RCosc (RC120M) clock.
void	scif_stop_rc120M (void)
	Stop the 120MHz internal RCosc (RC120M) clock.
void	scif_start_rc32k (void)
	Start the 32kHz internal RCosc (RC32K) clock.
void	scif_stop_rc32k (void)
	Stop the 32kHz internal RCosc (RC32K) clock.
void	scif_disable_rc32out (void)
	Unforce the RC32 signal from being output on the dedicated pin (PA20)
long int	scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt)
	Setup and start a generic clock.
long int	scif_stop_gclk (unsigned int gclk)
	Stop a generic clock.
long int	scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
	Setup a generic clock.
long int	scif_gc_enable (unsigned int gclk)
	Enable a generic clock.
long int	scif_pclksr_statushigh_wait (unsigned long statusMask)
	Wait for a status high in the Power and Clocks status register.

Detailed Description

System Control InterFace(SCIF) driver.

Compiler: IAR EWAVR32 and GNU GCC for AVR32
Supported devices: All AVR32 UC3L devices.
AppNote:

Author:: Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Define Documentation

#define SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))

Referenced by scif_dfll0_openloop_start_auto().

Enumeration Type Documentation

enum scif_dfll_mode_t

The different DFLL0 modes.

DFLL Control Functions

Enumerator:

SCIF_DFLL0_MODE_OPENLOOP
SCIF_DFLL0_MODE_CLOSEDLOOP

Function Documentation

long int scif_start_osc	(	scif_osc_t	osc,
		const scif_osc_opt_t *	opt,
		bool	wait_for_ready
	)

Configure and start an OSC0/OSC1 oscillator.

Interrupt Functions Power and Clocks Status Functions OSC0/OSC1 Functions

References ENABLE, scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.

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bool scif_is_osc_ready ( scif_osc_t osc )

Is an oscillator stable and ready to be used as clock source?

Parameters:

osc	The oscillator [INPUT]

Returns:: Status.

Return values:

true	oscillator stable and ready
false	oscillator not enabled or not ready.

long int scif_stop_osc ( scif_osc_t osc )

Stop an oscillator.

Parameters:

osc	The oscillator to stop

Returns:: Status.

Return values:

0	Oscillator successfully stopped.
<0	An error occured when stopping the oscillator.

References SCIF_UNLOCK.

long int scif_configure_osc_crystalmode	(	scif_osc_t	osc,
		unsigned int	fcrystal
	)

Configure an oscillator in crystal mode.

Parameters:

osc	The oscillator to configure [INPUT]
fcrystal	Crystal frequency (Hz) [INPUT]

Returns:: Status.

Return values:

0	Oscillator successfully configured.
<0	Error configuring the oscillator.

References u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.

long int scif_configure_osc_extmode ( scif_osc_t osc )

Configure an external clock as input clock.

Parameters:

osc	The external clock to configure [INPUT]

Returns:: Status.

Return values:

0	External clock successfully configured.
<0	Error configuring the external clock.

References u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC_MODE_EXT_CLK, and SCIF_UNLOCK.

long int scif_enable_osc	(	scif_osc_t	osc,
		unsigned int	startup,
		bool	wait_for_ready
	)

Enable an oscillator with a given startup time.

Parameters:

osc	The oscillator to configure [INPUT]
startup	Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT]
wait_for_ready	Wait for the oscillator to be stable before return [INPUT]

Returns:: Status.

Return values:

0	Oscillator successfully started
<0	Error starting the oscillator.

References ENABLE, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_start_osc32	(	const scif_osc32_opt_t *	opt,
		bool	wait_for_ready
	)

Configure and start the OSC32 oscillator.

OSC32 Functions

References scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, ENABLE, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::oscctrl32, u_avr32_scif_oscctrl32_t::OSCCTRL32, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.

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long scif_stop_osc32 ( void )

Stop the OSC32 oscillator.

Returns:: Status.

Return values:

0	Oscillator successfully stopped.
<0	An error occured when stopping the oscillator.

References SCIF_UNLOCK.

long int scif_dfll0_openloop_start ( const scif_dfll_openloop_conf_t * pdfllconfig )

Configure and start the DFLL0 in open loop mode.

Parameters:

pdfllconfig The DFLL parameters in open loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_openloop_conf_t::fine, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_openloop_start_auto().

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long int scif_dfll0_openloop_start_auto ( unsigned long TargetFreqkHz )

Automatic configuration and start of the DFLL0 in open loop mode.

Parameters:

TargetFreqkHz The DFLL target frequency (in kHz) [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.

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long int scif_dfll0_openloop_updatefreq ( const scif_dfll_openloop_conf_t * pdfllconfig )

Update the frequency of the DFLL0 in open loop mode.

Parameters:

pdfllconfig The DFLL parameters in open loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 frequency updated successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_dfll0_openloop_stop ( void )

Stop the DFLL0 in open loop mode.

Returns:: Status.

Return values:

0	DFLL0 successfully stopped.
<0	Error.

References u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_dfll0_ssg_enable ( scif_dfll_ssg_conf_t * pssg_conf )

Configure and enable the SSG.

Note:: The SSG reference generic clock must have previously been enabled.

Parameters:

pssg_conf The settings for the SCIF.DFLL0SSG register [INPUT]

Returns:: Status.

Return values:

0	SSG Generic clock configured and started successfully.
<0	Error.

References scif_dfll_ssg_conf_t::amplitude, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, ENABLE, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.

long int scif_dfll0_closedloop_start ( const scif_dfll_closedloop_conf_t * pdfllconfig )

Configure and start the DFLL0 in closed loop mode.

Note:: The main reference generic clock must have previously been started.

Parameters:

pdfllconfig The DFLL parameters in closed loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_closedloop_configure_and_start().

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long int scif_dfll0_closedloop_configure_and_start	(	const scif_gclk_opt_t *	gc_dfllif_ref_opt,
		unsigned long long	target_freq_hz,
		bool	enable_ssg
	)

Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.

Note:: Configures and enables the generic clock CLK_DFLLIF_REF to serve as the main reference.; This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.

Parameters:

gc_dfllif_ref_opt	The settings for the CLK_DFLLIF_REF generic clock [INPUT]
target_freq_hz	The target frequency (in Hz) [INPUT]
enable_ssg	Enable/disable the SSG feature [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.

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void scif_start_rc120M ( void )

Start the 120MHz internal RCosc (RC120M) clock.

Calibration Functions Critical Path Oscillator Functions 120MHz RCosc Functions

References SCIF_UNLOCK.

void scif_stop_rc120M ( void )

Stop the 120MHz internal RCosc (RC120M) clock.

References SCIF_UNLOCK.

void scif_start_rc32k ( void )

Start the 32kHz internal RCosc (RC32K) clock.

32kHz internal RCosc (RC32K) Functions

References SCIF_UNLOCK.

void scif_stop_rc32k ( void )

Stop the 32kHz internal RCosc (RC32K) clock.

References SCIF_UNLOCK.

void scif_disable_rc32out ( void )

Unforce the RC32 signal from being output on the dedicated pin (PA20)

Referenced by scif_start_osc32().

long int scif_start_gclk	(	unsigned int	gclk,
		const scif_gclk_opt_t *	opt
	)

Setup and start a generic clock.

Generic Clock Functions

References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, and SCIF_GCCTRL_OSCSEL_INVALID.

long int scif_stop_gclk ( unsigned int gclk )

Stop a generic clock.

Parameters:

gclk	The generic clock number to stop.

Note:: To avoid an infinite loop, this function checks the Clock enable flag SCIF_POLL_TIMEOUT times.

Returns:: Status.

Return values:

0	Success.
<0	Unable to stop generic clock.

References SCIF_POLL_TIMEOUT.

Referenced by scif_gc_setup().

long int scif_gc_setup	(	unsigned int	gclk,
		scif_gcctrl_oscsel_t	clk_src,
		unsigned int	diven,
		unsigned int	divfactor
	)

Setup a generic clock.

Parameters:

gclk	generic clock number (0 for gc0...)
clk_src	The input clock source to use for the generic clock
diven	Generic clock divisor enable
divfactor	Generic clock divisor

Note:: If the generic clock is already enabled, this function will disable it, apply the configuration then restart the generic clock.

Returns:: Status.

Return values:

0	Success.
<0	An error occured.

References SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().

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long int scif_gc_enable ( unsigned int gclk )

Enable a generic clock.

Parameters:

gclk	generic clock number (0 for gc0...)

Returns:: Status.

Return values:

0	Success.
<0	An error occured.

long int scif_pclksr_statushigh_wait ( unsigned long statusMask )

Wait for a status high in the Power and Clocks status register.

Backup Registers Functions Misc

Parameters:

statusMask Mask field of the status to poll [INPUT]

Returns:: Status.

Return values:

0	Status is high.
<0	SCIF_POLL_TIMEOUT Timeout expired before the status was high.

References SCIF_POLL_TIMEOUT.

Referenced by scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_enable_osc(), scif_start_osc(), and scif_start_osc32().

Data Structures

Defines

Enumerations

Functions

Detailed Description

Define Documentation

Enumeration Type Documentation

Function Documentation