scif_uc3l.h

Go to the documentation of this file.

/*This file has been prepared for Doxygen automatic documentation generation.*/
/* Copyright (C) 2009 - 2011 Atmel Corporation. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. The name of Atmel may not be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * 4. This software may only be redistributed and used in connection with an Atmel
 * AVR product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
 *
 */
#ifndef _SCIF_UC3L_H_
#define _SCIF_UC3L_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "compiler.h"

//  These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h
#if defined(AVR32_SCIF_100_H_INCLUDED) || defined(AVR32_SCIF_102_H_INCLUDED)
// Optionnal #undef AVR32_SCIF_GC_NO_DIV_CLOCK if the define values is wrong.
#define AVR32_SCIF_GC_NO_DIV_CLOCK       AVR32_GC_NO_DIV_CLOCK
#endif

#define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE      0x00000001  //! Enable value for OSCCTRL0.OSCEN
#define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE     0x00000000  //! Disable value for OSCCTRL0.OSCEN
#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE   0x00000001  //! Enable value for OSCCTRL32.OSC32EN
#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE  0x00000000  //! Disable value for OSCCTRL32.OSC32EN



#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ  4000000UL

#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ  20000000UL

typedef enum
{
  SCIF_GCCTRL_SLOWCLOCK  = AVR32_SCIF_GC_USES_CLK_SLOW,
  SCIF_GCCTRL_OSC32K  = AVR32_SCIF_GC_USES_CLK_32,
  SCIF_GCCTRL_DFLL0  = AVR32_SCIF_GC_USES_DFLL0,
  SCIF_GCCTRL_OSC0  = AVR32_SCIF_GC_USES_OSC0,
  SCIF_GCCTRL_RC120M  = AVR32_SCIF_GC_USES_RC120M,
  SCIF_GCCTRL_CPUCLOCK  = AVR32_SCIF_GC_USES_CLK_CPU,
  SCIF_GCCTRL_HSBCLOCK  = AVR32_SCIF_GC_USES_CLK_HSB,
  SCIF_GCCTRL_PBACLOCK  = AVR32_SCIF_GC_USES_CLK_PBA,
  SCIF_GCCTRL_PBBCLOCK  = AVR32_SCIF_GC_USES_CLK_PBB,
  SCIF_GCCTRL_RC32K  = AVR32_SCIF_GC_USES_RC32K,
  SCIF_GCCTRL_CLK1K  = AVR32_SCIF_GC_USES_CLK_1K,
#if (UC3L0128 || UC3L0256)
  SCIF_GCCTRL_PLL0  = AVR32_SCIF_GC_USES_PLL0,
#endif
  SCIF_GCCTRL_OSCSEL_INVALID
} scif_gcctrl_oscsel_t;

#if (UC3L0128 || UC3L0256)
#define SCIF_DFLL_MINFREQ_KHZ         20000
#define SCIF_DFLL_MINFREQ_HZ          20000000UL
#else
#define SCIF_DFLL_MINFREQ_KHZ         40000
#define SCIF_DFLL_MINFREQ_HZ          40000000UL
#endif

#define SCIF_DFLL_MAXFREQ_KHZ         150000
#define SCIF_DFLL_MAXFREQ_HZ          150000000UL

#define SCIF_SLOWCLOCK_FREQ_HZ        AVR32_SCIF_RCOSC_FREQUENCY
#define SCIF_SLOWCLOCK_FREQ_KHZ       (SCIF_SLOWCLOCK_FREQ_HZ/1000)

#define SCIF_RC32K_FREQ_HZ            32768
#define SCIF_RC32K_FREQ_KHZ           (SCIF_RC32K_FREQ_HZ/1000)

#define SCIF_RC120M_FREQ_HZ           120000000UL
#define SCIF_RC120M_FREQ_KHZ          120000

#define SCIF_OSC32_FREQ_HZ            32768

#define SCIF_POLL_TIMEOUT             100000

#define SCIF_NOT_SUPPORTED            (-10000)


typedef enum
{
  SCIF_OSC0  = 0,
  SCIF_OSC1  = 1
} scif_osc_t;

typedef enum
{
  SCIF_OSC_MODE_EXT_CLK = 0,            // For both OSC0 & OSC32
  SCIF_OSC_MODE_2PIN_CRYSTAL = 1,       // For both OSC0 and OSC32
  SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2,
  SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3,
  SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, // For OSC32 only
  SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5,
  SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6,
  SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7
} scif_osc_mode_t;

typedef struct
{
  unsigned long   freq_hz;
  scif_osc_mode_t mode;
  unsigned char   startup;
  unsigned char   gain;
} scif_osc_opt_t;

#if (UC3L0128 || UC3L0256)

typedef struct
{
  unsigned char   pll_freq;
  unsigned char   pll_wbwdisable;
  unsigned char   pll_div2;
  unsigned int    mul;
  unsigned int    div;
  unsigned int    lockcount;
  unsigned char   osc;
} scif_pll_opt_t;
#endif

typedef struct
{
  scif_osc_mode_t mode;
  unsigned char   startup;
  bool            pinsel;
  bool            en1k;
  bool            en32k;
} scif_osc32_opt_t;


typedef struct
{
  scif_gcctrl_oscsel_t clock_source;
  unsigned int divider;
  unsigned int diven;
  // (to fill-in if the clock_source is set to OSCn).
  unsigned long extosc_f;
} scif_gclk_opt_t;


typedef struct
{
  unsigned int  fine;
  unsigned int  coarse;
} scif_dfll_openloop_conf_t;

typedef struct
{
  unsigned int    coarse;
  unsigned int    fmul;
  unsigned int    imul;
  unsigned int    finemaxstep;
  unsigned int    coarsemaxstep;
} scif_dfll_closedloop_conf_t;

typedef struct
{
  unsigned int    use_random;
  unsigned int    amplitude;
  unsigned int    step_size;
} scif_dfll_ssg_conf_t;


#define SCIF_UNLOCK(reg)  (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))



#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_enable_interrupts(unsigned long mask)
{
  AVR32_SCIF.ier = mask;
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_disable_interrupts(unsigned long mask)
{
  AVR32_SCIF.idr = mask;
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline unsigned long scif_get_enabled_interrupts(void)
{
  return(AVR32_SCIF.imr);
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline unsigned long scif_get_interrupts_status(void)
{
  return(AVR32_SCIF.isr);
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_clear_interrupts_status(unsigned long mask)
{
  AVR32_SCIF.icr = mask;
}





#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline unsigned long scif_get_pclk_status(void)
{
  return(AVR32_SCIF.pclksr);
}





extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);

extern bool scif_is_osc_ready(scif_osc_t osc);

extern long int scif_stop_osc(scif_osc_t osc);

extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);

extern long int scif_configure_osc_extmode(scif_osc_t osc);

extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);

#if (UC3L0128 || UC3L0256)





extern long int scif_pll0_setup(const scif_pll_opt_t *opt);

extern long int scif_pll0_enable(void);

extern long int scif_pll0_disable(void);


extern long int scif_wait_for_pll0_locked(void);


#endif



extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline bool scif_is_osc32_ready(void)
{
  return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_osc32_1kout_ena(void)
{
  AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_osc32_1kout_dis(void)
{
  AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_osc32_32kout_ena(void)
{
  AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
}

#ifdef __GNUC__
__attribute__((__always_inline__))
#endif
static inline void scif_osc32_32kout_dis(void)
{
  AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
}

extern long int scif_stop_osc32(void);





extern long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig);

extern long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz);

extern long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig);

extern long int scif_dfll0_openloop_updatefreq_auto(unsigned long TargetFreq);

extern long int scif_dfll0_openloop_stop(void);

#define scif_dfll0_ssg_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)

extern long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf);

#define scif_dfll0_closedloop_mainref_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)

extern long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig);

extern long int scif_dfll0_closedloop_configure_and_start( const scif_gclk_opt_t *gc_dfllif_ref_opt,
                                                    unsigned long long target_freq_hz,
                                                    bool enable_ssg);

#define scif_dfll0_closedloop_dither_gc_enable(pgc_conf)  scif_dfll0_ssg_gc_enable(pgc_conf)












extern void scif_start_rc120M(void);

extern void scif_stop_rc120M(void);





extern void scif_start_rc32k(void);

extern void scif_stop_rc32k(void);

extern void scif_disable_rc32out(void);





extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);

extern long int scif_stop_gclk(unsigned int gclk);

extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);

extern long int scif_gc_enable(unsigned int gclk);










long int scif_pclksr_statushigh_wait(unsigned long statusMask);


#ifdef __cplusplus
}
#endif

#endif  // _SCIF_UC3L_H_