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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 /********************************************************************** 00002 * $Id$ LPC177x_8x.h 2011-06-02 00003 */ 00033 #ifndef __LPC177x_8x_H__ 00034 #define __LPC177x_8x_H__ 00035 00036 /* 00037 * ========================================================================== 00038 * ---------- Interrupt Number Definition ----------------------------------- 00039 * ========================================================================== 00040 */ 00041 00042 typedef enum IRQn 00043 { 00044 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ 00045 NonMaskableInt_IRQn = -14, 00046 HardFault_IRQn = -13, 00047 MemoryManagement_IRQn = -12, 00048 BusFault_IRQn = -11, 00049 UsageFault_IRQn = -10, 00050 SVCall_IRQn = -5, 00051 DebugMonitor_IRQn = -4, 00052 PendSV_IRQn = -2, 00053 SysTick_IRQn = -1, 00055 /****** LPC177x_8x Specific Interrupt Numbers *******************************************************/ 00056 WDT_IRQn = 0, 00057 TIMER0_IRQn = 1, 00058 TIMER1_IRQn = 2, 00059 TIMER2_IRQn = 3, 00060 TIMER3_IRQn = 4, 00061 UART0_IRQn = 5, 00062 UART1_IRQn = 6, 00063 UART2_IRQn = 7, 00064 UART3_IRQn = 8, 00065 PWM1_IRQn = 9, 00066 I2C0_IRQn = 10, 00067 I2C1_IRQn = 11, 00068 I2C2_IRQn = 12, 00069 Reserved0_IRQn = 13, 00070 SSP0_IRQn = 14, 00071 SSP1_IRQn = 15, 00072 PLL0_IRQn = 16, 00073 RTC_IRQn = 17, 00074 EINT0_IRQn = 18, 00075 EINT1_IRQn = 19, 00076 EINT2_IRQn = 20, 00077 EINT3_IRQn = 21, 00078 ADC_IRQn = 22, 00079 BOD_IRQn = 23, 00080 USB_IRQn = 24, 00081 CAN_IRQn = 25, 00082 DMA_IRQn = 26, 00083 I2S_IRQn = 27, 00084 ENET_IRQn = 28, 00085 MCI_IRQn = 29, 00086 MCPWM_IRQn = 30, 00087 QEI_IRQn = 31, 00088 PLL1_IRQn = 32, 00089 USBActivity_IRQn = 33, 00090 CANActivity_IRQn = 34, 00091 UART4_IRQn = 35, 00092 SSP2_IRQn = 36, 00093 LCD_IRQn = 37, 00094 GPIO_IRQn = 38, 00095 PWM0_IRQn = 39, 00096 EEPROM_IRQn = 40, 00097 } IRQn_Type; 00098 00099 00100 /* 00101 * ========================================================================== 00102 * ----------- Processor and Core Peripheral Section ------------------------ 00103 * ========================================================================== 00104 */ 00105 00106 /* Configuration of the Cortex-M3 Processor and Core Peripherals */ 00107 #define __MPU_PRESENT 1 00108 #define __NVIC_PRIO_BITS 5 00109 #define __Vendor_SysTickConfig 0 00112 #include <arch/cm3/core_cm3.h> /* Cortex-M3 processor and core peripherals */ 00113 #include "system_lpc177x_8x.h" /* System Header */ 00114 00115 00116 /******************************************************************************/ 00117 /* Device Specific Peripheral registers structures */ 00118 /******************************************************************************/ 00119 00120 #if defined ( __CC_ARM ) 00121 #pragma anon_unions 00122 #endif 00123 00124 /*------------- System Control (SC) ------------------------------------------*/ 00125 typedef struct 00126 { 00127 __IO uint32_t FLASHCFG; 00128 uint32_t RESERVED0[31]; 00129 __IO uint32_t PLL0CON; 00130 __IO uint32_t PLL0CFG; 00131 __I uint32_t PLL0STAT; 00132 __O uint32_t PLL0FEED; 00133 uint32_t RESERVED1[4]; 00134 __IO uint32_t PLL1CON; 00135 __IO uint32_t PLL1CFG; 00136 __I uint32_t PLL1STAT; 00137 __O uint32_t PLL1FEED; 00138 uint32_t RESERVED2[4]; 00139 __IO uint32_t PCON; 00140 __IO uint32_t PCONP; 00141 uint32_t RESERVED3[14]; 00142 __IO uint32_t EMCCLKSEL; 00143 __IO uint32_t CCLKSEL; 00144 __IO uint32_t USBCLKSEL; 00145 __IO uint32_t CLKSRCSEL; 00146 __IO uint32_t CANSLEEPCLR; 00147 __IO uint32_t CANWAKEFLAGS; 00148 uint32_t RESERVED4[10]; 00149 __IO uint32_t EXTINT; 00150 uint32_t RESERVED5[1]; 00151 __IO uint32_t EXTMODE; 00152 __IO uint32_t EXTPOLAR; 00153 uint32_t RESERVED6[12]; 00154 __IO uint32_t RSID; 00155 uint32_t RESERVED7[7]; 00156 __IO uint32_t SCS; 00157 __IO uint32_t IRCTRIM; 00158 __IO uint32_t PCLKSEL; 00159 uint32_t RESERVED8; 00160 __IO uint32_t PBOOST; 00161 uint32_t RESERVED9; 00162 __IO uint32_t LCD_CFG; 00163 uint32_t RESERVED10[1]; 00164 __IO uint32_t USBIntSt; 00165 __IO uint32_t DMAREQSEL; 00166 __IO uint32_t CLKOUTCFG; 00167 __IO uint32_t RSTCON0; 00168 __IO uint32_t RSTCON1; 00169 uint32_t RESERVED11[2]; 00170 __IO uint32_t EMCDLYCTL; 00171 __IO uint32_t EMCCAL; 00172 } LPC_SC_TypeDef; 00173 00174 /*------------- Pin Connect Block (PINCON) -----------------------------------*/ 00175 typedef struct 00176 { 00177 __IO uint32_t P0_0; /* 0x000 */ 00178 __IO uint32_t P0_1; 00179 __IO uint32_t P0_2; 00180 __IO uint32_t P0_3; 00181 __IO uint32_t P0_4; 00182 __IO uint32_t P0_5; 00183 __IO uint32_t P0_6; 00184 __IO uint32_t P0_7; 00185 00186 __IO uint32_t P0_8; /* 0x020 */ 00187 __IO uint32_t P0_9; 00188 __IO uint32_t P0_10; 00189 __IO uint32_t P0_11; 00190 __IO uint32_t P0_12; 00191 __IO uint32_t P0_13; 00192 __IO uint32_t P0_14; 00193 __IO uint32_t P0_15; 00194 00195 __IO uint32_t P0_16; /* 0x040 */ 00196 __IO uint32_t P0_17; 00197 __IO uint32_t P0_18; 00198 __IO uint32_t P0_19; 00199 __IO uint32_t P0_20; 00200 __IO uint32_t P0_21; 00201 __IO uint32_t P0_22; 00202 __IO uint32_t P0_23; 00203 00204 __IO uint32_t P0_24; /* 0x060 */ 00205 __IO uint32_t P0_25; 00206 __IO uint32_t P0_26; 00207 __IO uint32_t P0_27; 00208 __IO uint32_t P0_28; 00209 __IO uint32_t P0_29; 00210 __IO uint32_t P0_30; 00211 __IO uint32_t P0_31; 00212 00213 __IO uint32_t P1_0; /* 0x080 */ 00214 __IO uint32_t P1_1; 00215 __IO uint32_t P1_2; 00216 __IO uint32_t P1_3; 00217 __IO uint32_t P1_4; 00218 __IO uint32_t P1_5; 00219 __IO uint32_t P1_6; 00220 __IO uint32_t P1_7; 00221 00222 __IO uint32_t P1_8; /* 0x0A0 */ 00223 __IO uint32_t P1_9; 00224 __IO uint32_t P1_10; 00225 __IO uint32_t P1_11; 00226 __IO uint32_t P1_12; 00227 __IO uint32_t P1_13; 00228 __IO uint32_t P1_14; 00229 __IO uint32_t P1_15; 00230 00231 __IO uint32_t P1_16; /* 0x0C0 */ 00232 __IO uint32_t P1_17; 00233 __IO uint32_t P1_18; 00234 __IO uint32_t P1_19; 00235 __IO uint32_t P1_20; 00236 __IO uint32_t P1_21; 00237 __IO uint32_t P1_22; 00238 __IO uint32_t P1_23; 00239 00240 __IO uint32_t P1_24; /* 0x0E0 */ 00241 __IO uint32_t P1_25; 00242 __IO uint32_t P1_26; 00243 __IO uint32_t P1_27; 00244 __IO uint32_t P1_28; 00245 __IO uint32_t P1_29; 00246 __IO uint32_t P1_30; 00247 __IO uint32_t P1_31; 00248 00249 __IO uint32_t P2_0; /* 0x100 */ 00250 __IO uint32_t P2_1; 00251 __IO uint32_t P2_2; 00252 __IO uint32_t P2_3; 00253 __IO uint32_t P2_4; 00254 __IO uint32_t P2_5; 00255 __IO uint32_t P2_6; 00256 __IO uint32_t P2_7; 00257 00258 __IO uint32_t P2_8; /* 0x120 */ 00259 __IO uint32_t P2_9; 00260 __IO uint32_t P2_10; 00261 __IO uint32_t P2_11; 00262 __IO uint32_t P2_12; 00263 __IO uint32_t P2_13; 00264 __IO uint32_t P2_14; 00265 __IO uint32_t P2_15; 00266 00267 __IO uint32_t P2_16; /* 0x140 */ 00268 __IO uint32_t P2_17; 00269 __IO uint32_t P2_18; 00270 __IO uint32_t P2_19; 00271 __IO uint32_t P2_20; 00272 __IO uint32_t P2_21; 00273 __IO uint32_t P2_22; 00274 __IO uint32_t P2_23; 00275 00276 __IO uint32_t P2_24; /* 0x160 */ 00277 __IO uint32_t P2_25; 00278 __IO uint32_t P2_26; 00279 __IO uint32_t P2_27; 00280 __IO uint32_t P2_28; 00281 __IO uint32_t P2_29; 00282 __IO uint32_t P2_30; 00283 __IO uint32_t P2_31; 00284 00285 __IO uint32_t P3_0; /* 0x180 */ 00286 __IO uint32_t P3_1; 00287 __IO uint32_t P3_2; 00288 __IO uint32_t P3_3; 00289 __IO uint32_t P3_4; 00290 __IO uint32_t P3_5; 00291 __IO uint32_t P3_6; 00292 __IO uint32_t P3_7; 00293 00294 __IO uint32_t P3_8; /* 0x1A0 */ 00295 __IO uint32_t P3_9; 00296 __IO uint32_t P3_10; 00297 __IO uint32_t P3_11; 00298 __IO uint32_t P3_12; 00299 __IO uint32_t P3_13; 00300 __IO uint32_t P3_14; 00301 __IO uint32_t P3_15; 00302 00303 __IO uint32_t P3_16; /* 0x1C0 */ 00304 __IO uint32_t P3_17; 00305 __IO uint32_t P3_18; 00306 __IO uint32_t P3_19; 00307 __IO uint32_t P3_20; 00308 __IO uint32_t P3_21; 00309 __IO uint32_t P3_22; 00310 __IO uint32_t P3_23; 00311 00312 __IO uint32_t P3_24; /* 0x1E0 */ 00313 __IO uint32_t P3_25; 00314 __IO uint32_t P3_26; 00315 __IO uint32_t P3_27; 00316 __IO uint32_t P3_28; 00317 __IO uint32_t P3_29; 00318 __IO uint32_t P3_30; 00319 __IO uint32_t P3_31; 00320 00321 __IO uint32_t P4_0; /* 0x200 */ 00322 __IO uint32_t P4_1; 00323 __IO uint32_t P4_2; 00324 __IO uint32_t P4_3; 00325 __IO uint32_t P4_4; 00326 __IO uint32_t P4_5; 00327 __IO uint32_t P4_6; 00328 __IO uint32_t P4_7; 00329 00330 __IO uint32_t P4_8; /* 0x220 */ 00331 __IO uint32_t P4_9; 00332 __IO uint32_t P4_10; 00333 __IO uint32_t P4_11; 00334 __IO uint32_t P4_12; 00335 __IO uint32_t P4_13; 00336 __IO uint32_t P4_14; 00337 __IO uint32_t P4_15; 00338 00339 __IO uint32_t P4_16; /* 0x240 */ 00340 __IO uint32_t P4_17; 00341 __IO uint32_t P4_18; 00342 __IO uint32_t P4_19; 00343 __IO uint32_t P4_20; 00344 __IO uint32_t P4_21; 00345 __IO uint32_t P4_22; 00346 __IO uint32_t P4_23; 00347 00348 __IO uint32_t P4_24; /* 0x260 */ 00349 __IO uint32_t P4_25; 00350 __IO uint32_t P4_26; 00351 __IO uint32_t P4_27; 00352 __IO uint32_t P4_28; 00353 __IO uint32_t P4_29; 00354 __IO uint32_t P4_30; 00355 __IO uint32_t P4_31; 00356 00357 __IO uint32_t P5_0; /* 0x280 */ 00358 __IO uint32_t P5_1; 00359 __IO uint32_t P5_2; 00360 __IO uint32_t P5_3; 00361 __IO uint32_t P5_4; /* 0x290 */ 00362 } LPC_IOCON_TypeDef; 00363 00364 /*------------- General Purpose Input/Output (GPIO) --------------------------*/ 00365 typedef struct 00366 { 00367 __IO uint32_t FIODIR; 00368 uint32_t RESERVED0[3]; 00369 __IO uint32_t FIOMASK; 00370 __IO uint32_t FIOPIN; 00371 __IO uint32_t FIOSET; 00372 __O uint32_t FIOCLR; 00373 } LPC_GPIO_TypeDef; 00374 00375 typedef struct 00376 { 00377 __I uint32_t IntStatus; 00378 __I uint32_t IO0IntStatR; 00379 __I uint32_t IO0IntStatF; 00380 __O uint32_t IO0IntClr; 00381 __IO uint32_t IO0IntEnR; 00382 __IO uint32_t IO0IntEnF; 00383 uint32_t RESERVED0[3]; 00384 __I uint32_t IO2IntStatR; 00385 __I uint32_t IO2IntStatF; 00386 __O uint32_t IO2IntClr; 00387 __IO uint32_t IO2IntEnR; 00388 __IO uint32_t IO2IntEnF; 00389 } LPC_GPIOINT_TypeDef; 00390 00391 /*------------- Timer (TIM) --------------------------------------------------*/ 00392 typedef struct 00393 { 00394 __IO uint32_t IR; 00395 __IO uint32_t TCR; 00396 __IO uint32_t TC; 00397 __IO uint32_t PR; 00398 __IO uint32_t PC; 00399 __IO uint32_t MCR; 00400 __IO uint32_t MR0; 00401 __IO uint32_t MR1; 00402 __IO uint32_t MR2; 00403 __IO uint32_t MR3; 00404 __IO uint32_t CCR; 00405 __I uint32_t CR0; 00406 __I uint32_t CR1; 00407 uint32_t RESERVED0[2]; 00408 __IO uint32_t EMR; 00409 uint32_t RESERVED1[12]; 00410 __IO uint32_t CTCR; 00411 } LPC_TIM_TypeDef; 00412 00413 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/ 00414 typedef struct 00415 { 00416 __IO uint32_t IR; 00417 __IO uint32_t TCR; 00418 __IO uint32_t TC; 00419 __IO uint32_t PR; 00420 __IO uint32_t PC; 00421 __IO uint32_t MCR; 00422 __IO uint32_t MR0; 00423 __IO uint32_t MR1; 00424 __IO uint32_t MR2; 00425 __IO uint32_t MR3; 00426 __IO uint32_t CCR; 00427 __I uint32_t CR0; 00428 __I uint32_t CR1; 00429 __I uint32_t CR2; 00430 __I uint32_t CR3; 00431 uint32_t RESERVED0; 00432 __IO uint32_t MR4; 00433 __IO uint32_t MR5; 00434 __IO uint32_t MR6; 00435 __IO uint32_t PCR; 00436 __IO uint32_t LER; 00437 uint32_t RESERVED1[7]; 00438 __IO uint32_t CTCR; 00439 } LPC_PWM_TypeDef; 00440 00441 /*------------- Universal Asynchronous Receiver Transmitter (UARTx) -----------*/ 00442 /* There are three types of UARTs on the chip: 00443 (1) UART0,UART2, and UART3 are the standard UART. 00444 (2) UART1 is the standard with modem capability. 00445 (3) USART(UART4) is the sync/async UART with smart card capability. 00446 More details can be found on the Users Manual. */ 00447 00448 #if 0 00449 typedef struct 00450 { 00451 union { 00452 __I uint8_t RBR; 00453 __O uint8_t THR; 00454 __IO uint8_t DLL; 00455 uint32_t RESERVED0; 00456 }; 00457 union { 00458 __IO uint8_t DLM; 00459 __IO uint32_t IER; 00460 }; 00461 union { 00462 __I uint32_t IIR; 00463 __O uint8_t FCR; 00464 }; 00465 __IO uint8_t LCR; 00466 uint8_t RESERVED1[7]; 00467 __I uint8_t LSR; 00468 uint8_t RESERVED2[7]; 00469 __IO uint8_t SCR; 00470 uint8_t RESERVED3[3]; 00471 __IO uint32_t ACR; 00472 __IO uint8_t ICR; 00473 uint8_t RESERVED4[3]; 00474 __IO uint8_t FDR; 00475 uint8_t RESERVED5[7]; 00476 __IO uint8_t TER; 00477 uint8_t RESERVED6[39]; 00478 __I uint8_t FIFOLVL; 00479 } LPC_UART_TypeDef; 00480 #else 00481 typedef struct 00482 { 00483 union 00484 { 00485 __I uint8_t RBR; 00486 __O uint8_t THR; 00487 __IO uint8_t DLL; 00488 uint32_t RESERVED0; 00489 }; 00490 union 00491 { 00492 __IO uint8_t DLM; 00493 __IO uint32_t IER; 00494 }; 00495 union 00496 { 00497 __I uint32_t IIR; 00498 __O uint8_t FCR; 00499 }; 00500 __IO uint8_t LCR; 00501 uint8_t RESERVED1[7];//Reserved 00502 __I uint8_t LSR; 00503 uint8_t RESERVED2[7];//Reserved 00504 __IO uint8_t SCR; 00505 uint8_t RESERVED3[3];//Reserved 00506 __IO uint32_t ACR; 00507 uint8_t RESERVED4[4];//Reserved 00508 __IO uint8_t FDR; 00509 uint8_t RESERVED5[7];//Reserved 00510 __IO uint8_t TER; 00511 uint8_t RESERVED8[27];//Reserved 00512 __IO uint8_t RS485CTRL; 00513 uint8_t RESERVED9[3];//Reserved 00514 __IO uint8_t ADRMATCH; 00515 uint8_t RESERVED10[3];//Reserved 00516 __IO uint8_t RS485DLY; 00517 uint8_t RESERVED11[3];//Reserved 00518 }LPC_UART_TypeDef; 00519 #endif 00520 00521 00522 typedef struct 00523 { 00524 union { 00525 __I uint8_t RBR; 00526 __O uint8_t THR; 00527 __IO uint8_t DLL; 00528 uint32_t RESERVED0; 00529 }; 00530 union { 00531 __IO uint8_t DLM; 00532 __IO uint32_t IER; 00533 }; 00534 union { 00535 __I uint32_t IIR; 00536 __O uint8_t FCR; 00537 }; 00538 __IO uint8_t LCR; 00539 uint8_t RESERVED1[3]; 00540 __IO uint8_t MCR; 00541 uint8_t RESERVED2[3]; 00542 __I uint8_t LSR; 00543 uint8_t RESERVED3[3]; 00544 __I uint8_t MSR; 00545 uint8_t RESERVED4[3]; 00546 __IO uint8_t SCR; 00547 uint8_t RESERVED5[3]; 00548 __IO uint32_t ACR; 00549 uint32_t RESERVED6; 00550 __IO uint32_t FDR; 00551 uint32_t RESERVED7; 00552 __IO uint8_t TER; 00553 uint8_t RESERVED8[27]; 00554 __IO uint8_t RS485CTRL; 00555 uint8_t RESERVED9[3]; 00556 __IO uint8_t ADRMATCH; 00557 uint8_t RESERVED10[3]; 00558 __IO uint8_t RS485DLY; 00559 uint8_t RESERVED11[3]; 00560 } LPC_UART1_TypeDef; 00561 00562 typedef struct 00563 { 00564 union { 00565 __I uint32_t RBR; 00566 __O uint32_t THR; 00567 __IO uint32_t DLL; 00568 }; 00569 union { 00570 __IO uint32_t DLM; 00571 __IO uint32_t IER; 00572 }; 00573 union { 00574 __I uint32_t IIR; 00575 __O uint32_t FCR; 00576 }; 00577 __IO uint32_t LCR; 00578 __IO uint32_t MCR; 00579 __I uint32_t LSR; 00580 __I uint32_t MSR; 00581 __IO uint32_t SCR; 00582 __IO uint32_t ACR; 00583 __IO uint32_t ICR; 00584 __IO uint32_t FDR; 00585 __IO uint32_t OSR; 00586 uint32_t RESERVED0[6]; 00587 __IO uint32_t SCI_CTRL; 00588 __IO uint32_t RS485CTRL; 00589 __IO uint32_t ADRMATCH; 00590 __IO uint32_t RS485DLY; 00591 __IO uint32_t SYNCCTRL; 00592 __IO uint32_t TER; 00593 } LPC_UART4_TypeDef; 00594 00595 /*------------- Synchronous Serial Communication (SSP) -----------------------*/ 00596 typedef struct 00597 { 00598 __IO uint32_t CR0; 00599 __IO uint32_t CR1; 00600 __IO uint32_t DR; 00601 __I uint32_t SR; 00602 __IO uint32_t CPSR; 00603 __IO uint32_t IMSC; 00604 __IO uint32_t RIS; 00605 __IO uint32_t MIS; 00606 __IO uint32_t ICR; 00607 __IO uint32_t DMACR; 00608 } LPC_SSP_TypeDef; 00609 00610 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ 00611 typedef struct 00612 { 00613 __IO uint32_t CONSET; 00614 __I uint32_t STAT; 00615 __IO uint32_t DAT; 00616 __IO uint32_t ADR0; 00617 __IO uint32_t SCLH; 00618 __IO uint32_t SCLL; 00619 __O uint32_t CONCLR; 00620 __IO uint32_t MMCTRL; 00621 __IO uint32_t ADR1; 00622 __IO uint32_t ADR2; 00623 __IO uint32_t ADR3; 00624 __I uint32_t DATA_BUFFER; 00625 __IO uint32_t MASK0; 00626 __IO uint32_t MASK1; 00627 __IO uint32_t MASK2; 00628 __IO uint32_t MASK3; 00629 } LPC_I2C_TypeDef; 00630 00631 /*------------- Inter IC Sound (I2S) -----------------------------------------*/ 00632 typedef struct 00633 { 00634 __IO uint32_t DAO; 00635 __IO uint32_t DAI; 00636 __O uint32_t TXFIFO; 00637 __I uint32_t RXFIFO; 00638 __I uint32_t STATE; 00639 __IO uint32_t DMA1; 00640 __IO uint32_t DMA2; 00641 __IO uint32_t IRQ; 00642 __IO uint32_t TXRATE; 00643 __IO uint32_t RXRATE; 00644 __IO uint32_t TXBITRATE; 00645 __IO uint32_t RXBITRATE; 00646 __IO uint32_t TXMODE; 00647 __IO uint32_t RXMODE; 00648 } LPC_I2S_TypeDef; 00649 00650 /*------------- Real-Time Clock (RTC) ----------------------------------------*/ 00651 typedef struct 00652 { 00653 __IO uint8_t ILR; 00654 uint8_t RESERVED0[7]; 00655 __IO uint8_t CCR; 00656 uint8_t RESERVED1[3]; 00657 __IO uint8_t CIIR; 00658 uint8_t RESERVED2[3]; 00659 __IO uint8_t AMR; 00660 uint8_t RESERVED3[3]; 00661 __I uint32_t CTIME0; 00662 __I uint32_t CTIME1; 00663 __I uint32_t CTIME2; 00664 __IO uint8_t SEC; 00665 uint8_t RESERVED4[3]; 00666 __IO uint8_t MIN; 00667 uint8_t RESERVED5[3]; 00668 __IO uint8_t HOUR; 00669 uint8_t RESERVED6[3]; 00670 __IO uint8_t DOM; 00671 uint8_t RESERVED7[3]; 00672 __IO uint8_t DOW; 00673 uint8_t RESERVED8[3]; 00674 __IO uint16_t DOY; 00675 uint16_t RESERVED9; 00676 __IO uint8_t MONTH; 00677 uint8_t RESERVED10[3]; 00678 __IO uint16_t YEAR; 00679 uint16_t RESERVED11; 00680 __IO uint32_t CALIBRATION; 00681 __IO uint32_t GPREG0; 00682 __IO uint32_t GPREG1; 00683 __IO uint32_t GPREG2; 00684 __IO uint32_t GPREG3; 00685 __IO uint32_t GPREG4; 00686 __IO uint8_t RTC_AUXEN; 00687 uint8_t RESERVED12[3]; 00688 __IO uint8_t RTC_AUX; 00689 uint8_t RESERVED13[3]; 00690 __IO uint8_t ALSEC; 00691 uint8_t RESERVED14[3]; 00692 __IO uint8_t ALMIN; 00693 uint8_t RESERVED15[3]; 00694 __IO uint8_t ALHOUR; 00695 uint8_t RESERVED16[3]; 00696 __IO uint8_t ALDOM; 00697 uint8_t RESERVED17[3]; 00698 __IO uint8_t ALDOW; 00699 uint8_t RESERVED18[3]; 00700 __IO uint16_t ALDOY; 00701 uint16_t RESERVED19; 00702 __IO uint8_t ALMON; 00703 uint8_t RESERVED20[3]; 00704 __IO uint16_t ALYEAR; 00705 uint16_t RESERVED21; 00706 __IO uint32_t ERSTATUS; 00707 __IO uint32_t ERCONTROL; 00708 __IO uint32_t ERCOUNTERS; 00709 uint32_t RESERVED22; 00710 __IO uint32_t ERFIRSTSTAMP0; 00711 __IO uint32_t ERFIRSTSTAMP1; 00712 __IO uint32_t ERFIRSTSTAMP2; 00713 uint32_t RESERVED23; 00714 __IO uint32_t ERLASTSTAMP0; 00715 __IO uint32_t ERLASTSTAMP1; 00716 __IO uint32_t ERLASTSTAMP2; 00717 } LPC_RTC_TypeDef; 00718 00719 /*------------- Watchdog Timer (WDT) -----------------------------------------*/ 00720 typedef struct 00721 { 00722 __IO uint8_t MOD; 00723 uint8_t RESERVED0[3]; 00724 __IO uint32_t TC; 00725 __O uint8_t FEED; 00726 uint8_t RESERVED1[3]; 00727 __I uint32_t TV; 00728 uint32_t RESERVED2; 00729 __IO uint32_t WARNINT; 00730 __IO uint32_t WINDOW; 00731 } LPC_WDT_TypeDef; 00732 00733 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/ 00734 typedef struct 00735 { 00736 __IO uint32_t CR; 00737 __IO uint32_t GDR; 00738 uint32_t RESERVED0; 00739 __IO uint32_t INTEN; 00740 __IO uint32_t DR[8]; 00741 __I uint32_t STAT; 00742 __IO uint32_t ADTRM; 00743 } LPC_ADC_TypeDef; 00744 00745 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/ 00746 typedef struct 00747 { 00748 __IO uint32_t CR; 00749 __IO uint32_t CTRL; 00750 __IO uint32_t CNTVAL; 00751 } LPC_DAC_TypeDef; 00752 00753 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/ 00754 typedef struct 00755 { 00756 __I uint32_t CON; 00757 __O uint32_t CON_SET; 00758 __O uint32_t CON_CLR; 00759 __I uint32_t CAPCON; 00760 __O uint32_t CAPCON_SET; 00761 __O uint32_t CAPCON_CLR; 00762 __IO uint32_t TC0; 00763 __IO uint32_t TC1; 00764 __IO uint32_t TC2; 00765 __IO uint32_t LIM0; 00766 __IO uint32_t LIM1; 00767 __IO uint32_t LIM2; 00768 __IO uint32_t MAT0; 00769 __IO uint32_t MAT1; 00770 __IO uint32_t MAT2; 00771 __IO uint32_t DT; 00772 __IO uint32_t CP; 00773 __IO uint32_t CAP0; 00774 __IO uint32_t CAP1; 00775 __IO uint32_t CAP2; 00776 __I uint32_t INTEN; 00777 __O uint32_t INTEN_SET; 00778 __O uint32_t INTEN_CLR; 00779 __I uint32_t CNTCON; 00780 __O uint32_t CNTCON_SET; 00781 __O uint32_t CNTCON_CLR; 00782 __I uint32_t INTF; 00783 __O uint32_t INTF_SET; 00784 __O uint32_t INTF_CLR; 00785 __O uint32_t CAP_CLR; 00786 } LPC_MCPWM_TypeDef; 00787 00788 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/ 00789 typedef struct 00790 { 00791 __O uint32_t CON; 00792 __I uint32_t STAT; 00793 __IO uint32_t CONF; 00794 __I uint32_t POS; 00795 __IO uint32_t MAXPOS; 00796 __IO uint32_t CMPOS0; 00797 __IO uint32_t CMPOS1; 00798 __IO uint32_t CMPOS2; 00799 __I uint32_t INXCNT; 00800 __IO uint32_t INXCMP0; 00801 __IO uint32_t LOAD; 00802 __I uint32_t TIME; 00803 __I uint32_t VEL; 00804 __I uint32_t CAP; 00805 __IO uint32_t VELCOMP; 00806 __IO uint32_t FILTERPHA; 00807 __IO uint32_t FILTERPHB; 00808 __IO uint32_t FILTERINX; 00809 __IO uint32_t WINDOW; 00810 __IO uint32_t INXCMP1; 00811 __IO uint32_t INXCMP2; 00812 uint32_t RESERVED0[993]; 00813 __O uint32_t IEC; 00814 __O uint32_t IES; 00815 __I uint32_t INTSTAT; 00816 __I uint32_t IE; 00817 __O uint32_t CLR; 00818 __O uint32_t SET; 00819 } LPC_QEI_TypeDef; 00820 00821 /*------------- SD/MMC card Interface (MCI)-----------------------------------*/ 00822 typedef struct 00823 { 00824 __IO uint32_t POWER; 00825 __IO uint32_t CLOCK; 00826 __IO uint32_t ARGUMENT; 00827 __IO uint32_t COMMAND; 00828 __I uint32_t RESP_CMD; 00829 __I uint32_t RESP0; 00830 __I uint32_t RESP1; 00831 __I uint32_t RESP2; 00832 __I uint32_t RESP3; 00833 __IO uint32_t DATATMR; 00834 __IO uint32_t DATALEN; 00835 __IO uint32_t DATACTRL; 00836 __I uint32_t DATACNT; 00837 __I uint32_t STATUS; 00838 __O uint32_t CLEAR; 00839 __IO uint32_t MASK0; 00840 uint32_t RESERVED0[2]; 00841 __I uint32_t FIFOCNT; 00842 uint32_t RESERVED1[13]; 00843 __IO uint32_t FIFO[16]; 00844 } LPC_MCI_TypeDef; 00845 00846 /*------------- Controller Area Network (CAN) --------------------------------*/ 00847 typedef struct 00848 { 00849 __IO uint32_t mask[512]; /* ID Masks */ 00850 } LPC_CANAF_RAM_TypeDef; 00851 00852 typedef struct /* Acceptance Filter Registers */ 00853 { 00855 __IO uint32_t AFMR; 00856 00858 __IO uint32_t SFF_sa; 00859 00861 __IO uint32_t SFF_GRP_sa; 00862 00864 __IO uint32_t EFF_sa; 00865 00867 __IO uint32_t EFF_GRP_sa; 00868 00870 __IO uint32_t ENDofTable; 00871 00873 __I uint32_t LUTerrAd; 00874 00876 __I uint32_t LUTerr; 00877 00879 __IO uint32_t FCANIE; 00880 00882 __IO uint32_t FCANIC0; 00883 00885 __IO uint32_t FCANIC1; 00886 } LPC_CANAF_TypeDef; 00887 00888 typedef struct /* Central Registers */ 00889 { 00890 __I uint32_t TxSR; 00891 __I uint32_t RxSR; 00892 __I uint32_t MSR; 00893 } LPC_CANCR_TypeDef; 00894 00895 typedef struct /* Controller Registers */ 00896 { 00898 __IO uint32_t MOD; 00899 00901 __O uint32_t CMR; 00902 00904 __IO uint32_t GSR; 00905 00907 __I uint32_t ICR; 00908 00910 __IO uint32_t IER; 00911 00913 __IO uint32_t BTR; 00914 00916 __IO uint32_t EWL; 00917 00919 __I uint32_t SR; 00920 00922 __IO uint32_t RFS; 00923 00925 __IO uint32_t RID; 00926 00928 __IO uint32_t RDA; 00929 00931 __IO uint32_t RDB; 00932 00934 __IO uint32_t TFI1; 00935 00937 __IO uint32_t TID1; 00938 00940 __IO uint32_t TDA1; 00941 00943 __IO uint32_t TDB1; 00944 00946 __IO uint32_t TFI2; 00947 00949 __IO uint32_t TID2; 00950 00952 __IO uint32_t TDA2; 00953 00955 __IO uint32_t TDB2; 00956 00958 __IO uint32_t TFI3; 00959 00961 __IO uint32_t TID3; 00962 00964 __IO uint32_t TDA3; 00965 00967 __IO uint32_t TDB3; 00968 } LPC_CAN_TypeDef; 00969 00970 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/ 00971 typedef struct /* Common Registers */ 00972 { 00973 __I uint32_t IntStat; 00974 __I uint32_t IntTCStat; 00975 __O uint32_t IntTCClear; 00976 __I uint32_t IntErrStat; 00977 __O uint32_t IntErrClr; 00978 __I uint32_t RawIntTCStat; 00979 __I uint32_t RawIntErrStat; 00980 __I uint32_t EnbldChns; 00981 __IO uint32_t SoftBReq; 00982 __IO uint32_t SoftSReq; 00983 __IO uint32_t SoftLBReq; 00984 __IO uint32_t SoftLSReq; 00985 __IO uint32_t Config; 00986 __IO uint32_t Sync; 00987 } LPC_GPDMA_TypeDef; 00988 00989 typedef struct /* Channel Registers */ 00990 { 00991 __IO uint32_t CSrcAddr; 00992 __IO uint32_t CDestAddr; 00993 __IO uint32_t CLLI; 00994 __IO uint32_t CControl; 00995 __IO uint32_t CConfig; 00996 } LPC_GPDMACH_TypeDef; 00997 00998 /*------------- Universal Serial Bus (USB) -----------------------------------*/ 00999 typedef struct 01000 { 01001 __I uint32_t Revision; /* USB Host Registers */ 01002 __IO uint32_t Control; 01003 __IO uint32_t CommandStatus; 01004 __IO uint32_t InterruptStatus; 01005 __IO uint32_t InterruptEnable; 01006 __IO uint32_t InterruptDisable; 01007 __IO uint32_t HCCA; 01008 __I uint32_t PeriodCurrentED; 01009 __IO uint32_t ControlHeadED; 01010 __IO uint32_t ControlCurrentED; 01011 __IO uint32_t BulkHeadED; 01012 __IO uint32_t BulkCurrentED; 01013 __I uint32_t DoneHead; 01014 __IO uint32_t FmInterval; 01015 __I uint32_t FmRemaining; 01016 __I uint32_t FmNumber; 01017 __IO uint32_t PeriodicStart; 01018 __IO uint32_t LSTreshold; 01019 __IO uint32_t RhDescriptorA; 01020 __IO uint32_t RhDescriptorB; 01021 __IO uint32_t RhStatus; 01022 __IO uint32_t RhPortStatus1; 01023 __IO uint32_t RhPortStatus2; 01024 uint32_t RESERVED0[40]; 01025 __I uint32_t Module_ID; 01026 01027 __I uint32_t IntSt; /* USB On-The-Go Registers */ 01028 __IO uint32_t IntEn; 01029 __O uint32_t IntSet; 01030 __O uint32_t IntClr; 01031 __IO uint32_t StCtrl; 01032 __IO uint32_t Tmr; 01033 uint32_t RESERVED1[58]; 01034 01035 __I uint32_t DevIntSt; /* USB Device Interrupt Registers */ 01036 __IO uint32_t DevIntEn; 01037 __O uint32_t DevIntClr; 01038 __O uint32_t DevIntSet; 01039 01040 __O uint32_t CmdCode; /* USB Device SIE Command Registers */ 01041 __I uint32_t CmdData; 01042 01043 __I uint32_t RxData; /* USB Device Transfer Registers */ 01044 __O uint32_t TxData; 01045 __I uint32_t RxPLen; 01046 __O uint32_t TxPLen; 01047 __IO uint32_t Ctrl; 01048 __O uint32_t DevIntPri; 01049 01050 __I uint32_t EpIntSt; /* USB Device Endpoint Interrupt Regs */ 01051 __IO uint32_t EpIntEn; 01052 __O uint32_t EpIntClr; 01053 __O uint32_t EpIntSet; 01054 __O uint32_t EpIntPri; 01055 01056 __IO uint32_t ReEp; /* USB Device Endpoint Realization Reg*/ 01057 __O uint32_t EpInd; 01058 __IO uint32_t MaxPSize; 01059 01060 __I uint32_t DMARSt; /* USB Device DMA Registers */ 01061 __O uint32_t DMARClr; 01062 __O uint32_t DMARSet; 01063 uint32_t RESERVED2[9]; 01064 __IO uint32_t UDCAH; 01065 __I uint32_t EpDMASt; 01066 __O uint32_t EpDMAEn; 01067 __O uint32_t EpDMADis; 01068 __I uint32_t DMAIntSt; 01069 __IO uint32_t DMAIntEn; 01070 uint32_t RESERVED3[2]; 01071 __I uint32_t EoTIntSt; 01072 __O uint32_t EoTIntClr; 01073 __O uint32_t EoTIntSet; 01074 __I uint32_t NDDRIntSt; 01075 __O uint32_t NDDRIntClr; 01076 __O uint32_t NDDRIntSet; 01077 __I uint32_t SysErrIntSt; 01078 __O uint32_t SysErrIntClr; 01079 __O uint32_t SysErrIntSet; 01080 uint32_t RESERVED4[15]; 01081 01082 union { 01083 __I uint32_t I2C_RX; /* USB OTG I2C Registers */ 01084 __O uint32_t I2C_TX; 01085 }; 01086 __IO uint32_t I2C_STS; 01087 __IO uint32_t I2C_CTL; 01088 __IO uint32_t I2C_CLKHI; 01089 __O uint32_t I2C_CLKLO; 01090 uint32_t RESERVED5[824]; 01091 01092 union { 01093 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */ 01094 __IO uint32_t OTGClkCtrl; 01095 }; 01096 union { 01097 __I uint32_t USBClkSt; 01098 __I uint32_t OTGClkSt; 01099 }; 01100 } LPC_USB_TypeDef; 01101 01102 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/ 01103 typedef struct 01104 { 01105 __IO uint32_t MAC1; /* MAC Registers */ 01106 __IO uint32_t MAC2; 01107 __IO uint32_t IPGT; 01108 __IO uint32_t IPGR; 01109 __IO uint32_t CLRT; 01110 __IO uint32_t MAXF; 01111 __IO uint32_t SUPP; 01112 __IO uint32_t TEST; 01113 __IO uint32_t MCFG; 01114 __IO uint32_t MCMD; 01115 __IO uint32_t MADR; 01116 __O uint32_t MWTD; 01117 __I uint32_t MRDD; 01118 __I uint32_t MIND; 01119 uint32_t RESERVED0[2]; 01120 __IO uint32_t SA0; 01121 __IO uint32_t SA1; 01122 __IO uint32_t SA2; 01123 uint32_t RESERVED1[45]; 01124 __IO uint32_t Command; /* Control Registers */ 01125 __I uint32_t Status; 01126 __IO uint32_t RxDescriptor; 01127 __IO uint32_t RxStatus; 01128 __IO uint32_t RxDescriptorNumber; 01129 __I uint32_t RxProduceIndex; 01130 __IO uint32_t RxConsumeIndex; 01131 __IO uint32_t TxDescriptor; 01132 __IO uint32_t TxStatus; 01133 __IO uint32_t TxDescriptorNumber; 01134 __IO uint32_t TxProduceIndex; 01135 __I uint32_t TxConsumeIndex; 01136 uint32_t RESERVED2[10]; 01137 __I uint32_t TSV0; 01138 __I uint32_t TSV1; 01139 __I uint32_t RSV; 01140 uint32_t RESERVED3[3]; 01141 __IO uint32_t FlowControlCounter; 01142 __I uint32_t FlowControlStatus; 01143 uint32_t RESERVED4[34]; 01144 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */ 01145 __I uint32_t RxFilterWoLStatus; 01146 __O uint32_t RxFilterWoLClear; 01147 uint32_t RESERVED5; 01148 __IO uint32_t HashFilterL; 01149 __IO uint32_t HashFilterH; 01150 uint32_t RESERVED6[882]; 01151 __I uint32_t IntStatus; /* Module Control Registers */ 01152 __IO uint32_t IntEnable; 01153 __O uint32_t IntClear; 01154 __O uint32_t IntSet; 01155 uint32_t RESERVED7; 01156 __IO uint32_t PowerDown; 01157 uint32_t RESERVED8; 01158 __IO uint32_t Module_ID; 01159 } LPC_EMAC_TypeDef; 01160 01161 /*------------- LCD controller (LCD) -----------------------------------------*/ 01162 typedef struct 01163 { 01164 __IO uint32_t TIMH; /* LCD Registers */ 01165 __IO uint32_t TIMV; 01166 __IO uint32_t POL; 01167 __IO uint32_t LE; 01168 __IO uint32_t UPBASE; 01169 __IO uint32_t LPBASE; 01170 __IO uint32_t CTRL; 01171 __IO uint32_t INTMSK; 01172 __I uint32_t INTRAW; 01173 __I uint32_t INTSTAT; 01174 __O uint32_t INTCLR; 01175 __I uint32_t UPCURR; 01176 __I uint32_t LPCURR; 01177 uint32_t RESERVED0[115]; 01178 __IO uint32_t PAL[128]; 01179 uint32_t RESERVED1[256]; 01180 __IO uint32_t CRSR_IMG[256]; 01181 __IO uint32_t CRSR_CTRL; 01182 __IO uint32_t CRSR_CFG; 01183 __IO uint32_t CRSR_PAL0; 01184 __IO uint32_t CRSR_PAL1; 01185 __IO uint32_t CRSR_XY; 01186 __IO uint32_t CRSR_CLIP; 01187 uint32_t RESERVED2[2]; 01188 __IO uint32_t CRSR_INTMSK; 01189 __O uint32_t CRSR_INTCLR; 01190 __I uint32_t CRSR_INTRAW; 01191 __I uint32_t CRSR_INTSTAT; 01192 } LPC_LCD_TypeDef; 01193 01194 /*------------- External Memory Controller (EMC) -----------------------------*/ 01195 typedef struct 01196 { 01197 __IO uint32_t Control; 01198 __I uint32_t Status; 01199 __IO uint32_t Config; 01200 uint32_t RESERVED0[5]; 01201 __IO uint32_t DynamicControl; 01202 __IO uint32_t DynamicRefresh; 01203 __IO uint32_t DynamicReadConfig; 01204 uint32_t RESERVED1[1]; 01205 __IO uint32_t DynamicRP; 01206 __IO uint32_t DynamicRAS; 01207 __IO uint32_t DynamicSREX; 01208 __IO uint32_t DynamicAPR; 01209 __IO uint32_t DynamicDAL; 01210 __IO uint32_t DynamicWR; 01211 __IO uint32_t DynamicRC; 01212 __IO uint32_t DynamicRFC; 01213 __IO uint32_t DynamicXSR; 01214 __IO uint32_t DynamicRRD; 01215 __IO uint32_t DynamicMRD; 01216 uint32_t RESERVED2[9]; 01217 __IO uint32_t StaticExtendedWait; 01218 uint32_t RESERVED3[31]; 01219 __IO uint32_t DynamicConfig0; 01220 __IO uint32_t DynamicRasCas0; 01221 uint32_t RESERVED4[6]; 01222 __IO uint32_t DynamicConfig1; 01223 __IO uint32_t DynamicRasCas1; 01224 uint32_t RESERVED5[6]; 01225 __IO uint32_t DynamicConfig2; 01226 __IO uint32_t DynamicRasCas2; 01227 uint32_t RESERVED6[6]; 01228 __IO uint32_t DynamicConfig3; 01229 __IO uint32_t DynamicRasCas3; 01230 uint32_t RESERVED7[38]; 01231 __IO uint32_t StaticConfig0; 01232 __IO uint32_t StaticWaitWen0; 01233 __IO uint32_t StaticWaitOen0; 01234 __IO uint32_t StaticWaitRd0; 01235 __IO uint32_t StaticWaitPage0; 01236 __IO uint32_t StaticWaitWr0; 01237 __IO uint32_t StaticWaitTurn0; 01238 uint32_t RESERVED8[1]; 01239 __IO uint32_t StaticConfig1; 01240 __IO uint32_t StaticWaitWen1; 01241 __IO uint32_t StaticWaitOen1; 01242 __IO uint32_t StaticWaitRd1; 01243 __IO uint32_t StaticWaitPage1; 01244 __IO uint32_t StaticWaitWr1; 01245 __IO uint32_t StaticWaitTurn1; 01246 uint32_t RESERVED9[1]; 01247 __IO uint32_t StaticConfig2; 01248 __IO uint32_t StaticWaitWen2; 01249 __IO uint32_t StaticWaitOen2; 01250 __IO uint32_t StaticWaitRd2; 01251 __IO uint32_t StaticWaitPage2; 01252 __IO uint32_t StaticWaitWr2; 01253 __IO uint32_t StaticWaitTurn2; 01254 uint32_t RESERVED10[1]; 01255 __IO uint32_t StaticConfig3; 01256 __IO uint32_t StaticWaitWen3; 01257 __IO uint32_t StaticWaitOen3; 01258 __IO uint32_t StaticWaitRd3; 01259 __IO uint32_t StaticWaitPage3; 01260 __IO uint32_t StaticWaitWr3; 01261 __IO uint32_t StaticWaitTurn3; 01262 } LPC_EMC_TypeDef; 01263 01264 /*------------- CRC Engine (CRC) -----------------------------------------*/ 01265 typedef struct 01266 { 01267 __IO uint32_t MODE; 01268 __IO uint32_t SEED; 01269 union { 01270 __I uint32_t SUM; 01271 struct { 01272 __O uint32_t DATA; 01273 } WR_DATA_DWORD; 01274 01275 struct { 01276 __O uint16_t DATA; 01277 uint16_t RESERVED; 01278 }WR_DATA_WORD; 01279 01280 struct { 01281 __O uint8_t DATA; 01282 uint8_t RESERVED[3]; 01283 }WR_DATA_BYTE; 01284 }; 01285 } LPC_CRC_TypeDef; 01286 01287 /*------------- EEPROM Controller (EEPROM) -----------------------------------*/ 01288 typedef struct 01289 { 01290 __IO uint32_t CMD; /* 0x0080 */ 01291 __IO uint32_t ADDR; 01292 __IO uint32_t WDATA; 01293 __IO uint32_t RDATA; 01294 __IO uint32_t WSTATE; /* 0x0090 */ 01295 __IO uint32_t CLKDIV; 01296 __IO uint32_t PWRDWN; /* 0x0098 */ 01297 uint32_t RESERVED0[975]; 01298 __IO uint32_t INT_CLR_ENABLE; /* 0x0FD8 */ 01299 __IO uint32_t INT_SET_ENABLE; 01300 __IO uint32_t INT_STATUS; /* 0x0FE0 */ 01301 __IO uint32_t INT_ENABLE; 01302 __IO uint32_t INT_CLR_STATUS; 01303 __IO uint32_t INT_SET_STATUS; 01304 } LPC_EEPROM_TypeDef; 01305 01306 #if defined ( __CC_ARM ) 01307 #pragma no_anon_unions 01308 #endif 01309 01310 /******************************************************************************/ 01311 /* Peripheral memory map */ 01312 /******************************************************************************/ 01313 /* Base addresses */ 01314 #define LPC_FLASH_BASE (0x00000000UL) 01315 #define LPC_RAM_BASE (0x10000000UL) 01316 #define LPC_PERI_RAM_BASE (0x20000000UL) 01317 #define LPC_APB0_BASE (0x40000000UL) 01318 #define LPC_APB1_BASE (0x40080000UL) 01319 #define LPC_AHBRAM1_BASE (0x20004000UL) 01320 #define LPC_AHB_BASE (0x20080000UL) 01321 #define LPC_CM3_BASE (0xE0000000UL) 01322 01323 /* APB0 peripherals */ 01324 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) 01325 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) 01326 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) 01327 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) 01328 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) 01329 #define LPC_PWM0_BASE (LPC_APB0_BASE + 0x14000) 01330 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) 01331 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) 01332 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) 01333 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) 01334 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x2C000) 01335 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) 01336 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) 01337 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) 01338 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) 01339 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) 01340 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) 01341 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) 01342 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) 01343 01344 /* APB1 peripherals */ 01345 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) 01346 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) 01347 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) 01348 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) 01349 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) 01350 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) 01351 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) 01352 #define LPC_UART4_BASE (LPC_APB1_BASE + 0x24000) 01353 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) 01354 #define LPC_SSP2_BASE (LPC_APB1_BASE + 0x2C000) 01355 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) 01356 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) 01357 #define LPC_MCI_BASE (LPC_APB1_BASE + 0x40000) 01358 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) 01359 01360 /* AHB peripherals */ 01361 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x00000) 01362 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x00100) 01363 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x00120) 01364 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x00140) 01365 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x00160) 01366 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x00180) 01367 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x001A0) 01368 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x001C0) 01369 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x001E0) 01370 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x04000) 01371 #define LPC_LCD_BASE (LPC_AHB_BASE + 0x08000) 01372 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) 01373 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x10000) 01374 #define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x18000) 01375 #define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x18020) 01376 #define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x18040) 01377 #define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x18060) 01378 #define LPC_GPIO4_BASE (LPC_AHB_BASE + 0x18080) 01379 #define LPC_GPIO5_BASE (LPC_AHB_BASE + 0x180A0) 01380 #define LPC_EMC_BASE (LPC_AHB_BASE + 0x1C000) 01381 01382 #define LPC_EEPROM_BASE (LPC_FLASH_BASE+ 0x200080) 01383 01384 01385 /******************************************************************************/ 01386 /* Peripheral declaration */ 01387 /******************************************************************************/ 01388 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) 01389 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) 01390 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) 01391 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) 01392 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) 01393 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) 01394 #define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) 01395 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) 01396 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) 01397 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) 01398 #define LPC_UART4 ((LPC_UART4_TypeDef *) LPC_UART4_BASE ) 01399 #define LPC_PWM0 ((LPC_PWM_TypeDef *) LPC_PWM0_BASE ) 01400 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) 01401 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) 01402 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) 01403 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) 01404 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) 01405 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) 01406 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) 01407 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) 01408 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) 01409 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) 01410 #define LPC_SSP2 ((LPC_SSP_TypeDef *) LPC_SSP2_BASE ) 01411 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) 01412 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) 01413 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) 01414 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) 01415 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) 01416 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) 01417 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) 01418 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) 01419 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) 01420 #define LPC_MCI ((LPC_MCI_TypeDef *) LPC_MCI_BASE ) 01421 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) 01422 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) 01423 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) 01424 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) 01425 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) 01426 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) 01427 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) 01428 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) 01429 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) 01430 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) 01431 #define LPC_LCD ((LPC_LCD_TypeDef *) LPC_LCD_BASE ) 01432 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) 01433 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) 01434 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) 01435 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) 01436 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) 01437 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) 01438 #define LPC_GPIO5 ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE ) 01439 #define LPC_EMC ((LPC_EMC_TypeDef *) LPC_EMC_BASE ) 01440 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) 01441 #define LPC_EEPROM ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE ) 01442 01443 #endif // __LPC177x_8x_H__