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Medianut 2 Connectors

Connector J1
Headphone Output

2.5 mm stereo audio jack.

Pin	Signal	Usage
1	GBUF	Ground buffer.
2	RIGHT	Right channel output.
3	LEFT	Left channel output.
4	N/C
5

Connector J2
Microphone Input

2.5 mm mono audio jack.

Pin	Signal	Usage
1	MICN	Negative differential microphone input, self-biasing.
2	MICP	Positive differential microphone input, self-biasing.
3	N/C
4
5

Connector J3
Audio Extension

2 x 7 position box pin header, 2.54 mm (0.1") grid.

Pin	Signal	Usage
1	RJ1	To right channel at J1.
2	RIGHT	Right channel audio output from decoder, if JP1 pins 3 and 5 are shortened.
3	LEFT	Left channel audio output from decoder, if JP1 pins 4 and 6 are shortened.
4	LJ1	To left channel at J1.
5	GBUF	Ground buffer used as common voltage for headphones. This will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from the decoder may be connected directly to the headphones.
6
7	AGND	Analog ground.
8	LINEIN	Line input.
9	GND	Digital ground.
10
11	LROUT GPIO4	Not available with the VS1011E board version. Indicates the channel transmitted on the I2S bus. Low for left and high for right channel.
12	DIN GPIO1	Not available with the VS1011E board version. I2S serial data input.
13	MCLK GPIO5	Not available with the VS1011E board version. I2S master clock.
14	BCLK GPIO0	Not available with the VS1011E board version. I2S bit rate clock.

Connector J4
Keyboard

2 x 5 position box pin header, 2.54 mm (0.1") grid.

Pin	ATmega168	Signal	Usage
1	PC4 ADC4 SDA PCINT12	KEY3	Push button 3.
2		+5V	Power supply.
3	PB1 OC1A PCINT1	KEY1	Push button 1.
4	PB7 TOSC2 XTAL2 PCINT7	CS	Keyboard chip select.
5		GND	Digital ground.
6	PB3 MOSI OC2A PCINT3	MOSI	Serial keyboard data output.
7	PB0 ICP1 CLKO PCINT0	KEY2	Push button 2.
8	PB4 MISO PCINT4	MISO	Serial keyboard data input.
9	PC5 ADC5 SCL PCINT13	KEY4	Push button 4.
10	PB5 SCK PCINT5	CLOCK	Serial keyboard clock.

Connector J5
Display

2 x 10 position box pin header, 2.54 mm (0.1") grid.

Pin	ATmega168	LCD Signal	Usage
1		GND	Digital ground
2		+5V	Power supply
3		VLC
4	PC6 RESET PCINT14	RESET
5	PC1 ADC1 PCINT9	E	Display enable output. Driven low before read/write starts.
6	PC2 ADC2 PCINT10	R/W	Read/write output. Driven high during read and low during write.
7	PD0 RXD PCINT16	DB0	Low order bidirectional data bus pins. Not used if the display is configured for 4-bit operation.
8	PD1 TXD PCINT17	DB1
9	PD2 INT0 PCINT18	DB2
10	PD3 INT1 OC2B PCINT19	DB3
11	PD4 T0 XCK PCINT20	DB4	High order bidirectional data bus pins.
12	PD5 T1 OC0B PCINT21	DB5
13	PD6 AIN0 OC0A PCINT22	DB6
14	PD7 AIN1 PCINT23	DB7
15	PC3 ADC3 PCINT11	RS	Register select. Set to low for instructions and high for data.
16	-(PB6+PB7) TOSC1/2 XTAL1/2 PCINT6/7	NCS2	Negated chip select. Driven low, when PB6 and PB7 are both high.
17	PB6 TOSC1 XTAL1 PCINT6	CS1	Chip select.
18		VOUT
19		ANODE
20		CATHODE

Connector J6
Ethernut Expansion Port

2 x 32 position socket, 2.54 mm (0.1") grid.

Pin	Ethernut 1/2	Ethernut 3	Medianut 2	Usage
1	N/C	+3.3V	N/C
2	N/C	+3.3V	N/C
3	+5V	N/C	N/C
4	+5V	N/C	N/C
5	GND	GND	GND	Digital ground.
6	GND	GND	GND	Digital ground.
7	GND	GND	GND	Digital ground.
8	GND	GND	GND	Digital ground.
9	MR\	NMR	N/C
10	DC	DC	DC	Medianut power supply, +6V..+24V.
11	+5V	N/C	N/C
12	+5V	N/C	N/C
13	RD\ PG1	NCRD	N/C
14	WR\ PG0	NCWR	N/C
15	D0	CDR0	N/C
16	D1	CDR1	N/C
17	D2	CDR2	N/C
18	D3	CDR3	N/C
19	D4	CDR4	N/C
20	D5	CDR5	N/C
21	D6	CDR6	N/C
22	D7	CDR7	N/C
23	A0 PA0	CAR0	N/C
24	A1 PA1	CAR1	N/C
25	A2 PA2	CAR2	N/C
26	A3 PA3	CAR3	N/C
27	A4 PA4	CAR4	N/C
28	A5 PA5	CAR5	N/C
29	A6 PA6	CAR6	N/C
30	A7 PA7	CAR7	N/C
31	A8 PC0	CAR8	N/C
32	A9 PC1	CAR9	N/C
33	A10 PC2	CAR10	N/C
34	A11 PC3	CAR11	N/C
35	A12 PC4	CAR12	N/C
36	A13 PC5	CAR13	N/C
37	A14 PC6	CAR14	N/C
38	A15 PC7	CAR15	N/C
39	PE0 RXD0 PDI PCINT8	P15 RXD0	N/C
40	PE1 TXD0 PDO	P14 TXD0	N/C
41	PE2 XCK0 AIN0	P13 SCK0	N/C
42	PE3 OC3A AIN1	P8 TIOB2	N/C
43	PE4 INT4 OC3B	P9 IRQ0	N/C
44	PE5 INT5 OC3C	P27 NCS3	N/C
45	PE6 INT6 T3	P11 IRQ2	DREQ	Data request output. If high, the decoder can take at least 32 bytes of SDI data or a single SCI command.
46	PE7 INT7 ICP3 CLKO	P12 FIQ	N/C
47	PB0 -SS PCINT0	P0 TCLK0	XOE	Decoder buffer output enable. If low, XCS, SCK, SI and SO are routed to the decoder. Must be high, while Ethernut uses the serial bus for communication with other devices.
48	PB1 SCK PCINT1	P1 TIOA0	SCK	Serial bus clock input. Data is shifted out on the falling edge and sampled on the rising edge.
49	PB2 MOSI PCINT2	P2 TIOB0	SI	Serial bus data input. Reads SDI data when XDCS is low and XCS is high, or commands when XCS is low and XDCS is high.
50	PB3 MISO PCINT3	P3 TCLK1	SO	Serial bus data output. Sends command responses when XCS is low.
51	PB4 OC0/OC2A PCINT0	P4 TIOA1	N/C
52	PB5 OC1A PCINT5	P5 TIOB1	XDCS BSYNC	Data chip select input. XDCS must be low and XCS must be high when sending SDI data to the decoder.
53	PB6 OC1B PCINT6	P6 TCLK2	XRESET	Decoder hardware reset. When driven low, the decoder sets all internal registers to initial values and enters full power down mode.
54	PB7 OC1C OC2/OC0A PCINT7	P7 TIOA2	LED	LED backlit control. Set high to switch backlit on.
55	PD0 INT0 SCL	P17 SW-SCL	N/C
56	PD1 INT1 SDA	P16 SW-SDA XTMS(JP9)	N/C
57	PD2 INT2 RXD1	P22 RXD1	TX	Not available with the VS1011E board version. If R51 is mounted, this pin is connected to the UART transmit line of the decoder.
58	PD3 INT3 TXD1	P21 TXD1 NTRI	RX	Not available with the VS1011E board version. If R52 is mounted, this pin is connected to the UART receive line of the decoder.
59	PD4 ICP1	P23 XTDI(JP9)	ARESET	ATmega168 hardware reset.
60	PD5 XCK1	P20 SCK1	AINT	ATmega168 interrupt request output.
61	PD6 T1	P19 XTDO(JP9)	XCS	Command chip select input. XCS must be low and XDCS must be high when sending SCI commands to the decoder.
62	PD7 T2/T0	P18 XTCK(JP9)	AOE	ATmega168 buffer output enable. If low, SCK, SI and SO are routed to the Medianut Slave CPU. Additionally the ATmega168 SS pin is driven low. Must be high, while Ethernut uses the serial bus for communication with other devices.
63	N/C	N/C	N/C
64	N/C ALE PG2	N/C	N/C