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Ethernut 3 CPLD

The Ethernut 3 design includes a Complex Programmable Logic Device (CPLD). Through re-programming, it allows to implement application specific hardware functions. By default, the CPLD offers the following features:

CPLD Registers

The chip is accessed through the CPU's memory bus interface. Its internal functions can be controlled by the firmware through 7 memory-mapped registers, located at base address 0x21000000:

Offset Register Symbol Access Reset State
0x00 NPL RS-232 Command Register NPL_RSCR Read/Write 0x20
0x04 NPL Interrupt Mask Register NPL_IMR Read/Write 0x0000
0x0C NPL Signal Latch Register NPL_SLR Read Only 0x0000
0x10 NPL Signal Clear Register NPL_SCR Write Only  
0x14 NPL MMC Data Register NPL_MMCDR Read/Write 0x00
0x18 NPL External Enable Register NPL_XER Read/Write 0x07
0x1C NPL Version ID Register NPL_VIDR Read Only 0x02

Application programmers should use the symbols defined in dev/npl.h to access the CPLD registers. For example, the version ID register can be used by the firmware to adapt to different logic implementations. The following code fragment prints out the CPLD version: 

#include <dev/npl.h>
uint8_t npl_version;
...
npl_version = inb(NPL_VIDR);
printf("CPLD Version %u\n", npl_version);
Warning Do not apply CPLD versions above
15 (0x0F) to Ethernut 3.0.

There are significant differences between the logic of Ethernut 3.0 and Ethernut 3.1. Most notably, pin 19 is used on Ethernut 3.0 to monitor the wake-up signal from the Ethernet controller. While running in 16-bit mode, the Ethernet controller on Ethernut 3.1 doesn't provide this feature and the pin is used as a chip select output for the new serial flash chip. Enabling this output on Ethernut 3.0 would result in a short circuit and may damage the CPLD or the Ethernet controller or both.

NPL RS-232 Command Register

Symbol: NPL_RSCR
Memory Address: 0x21000000

This 8-bit register controls the RS-232 handshake outputs and routes the specified USARTs to the RS-232 transceiver. Two additional bits can be used to permanently switch the RS-232 transceiver on or off.

In most cases this register will be controlled by a device driver of the operating system. But not all drivers may offer the full set of available functions.

7
6
5
4
3
2
1
0
RSUSP
 RSUS1 RSUS0 0 RSRTS RSDTR RSFOFF RSFON

NPL Interrupt Mask Register

Symbol: NPL_IMR
Memory Address: 0x21000004

This 16-bit register is used to enable interrupts on specific events. If a signal becomes active and the related bit is set to 1, then the IRQ0 line is pulled low and the firmware will execute the interrupt handler that had been registered for this signal.

Nut/OS provides an API to simplify NPL interrupt handling. It is quite similar to the API used for CPU interrupts. Thus, applications typically do not directly access this register.

15
14
13
12
11
10
9
8
        NMMCD MMCD NRSINVAL RSINVAL

7
6
5
4
3
2
1
0
MMCREADY FMBUSY LANWAKEUP RTCALARM RSRI RSDCD RSDSR RSCTS

NPL Signal Latch Register

Symbol: NPL_SLR
Memory Address: 0x2100000C

This 16-bit read-only register latches active signal states. If a signal becomes active, the corresponding bit will be set to 1 and remain 1 until explicitly cleared. To clear any latched bit, 1 must be written to the corresponding bit in the signal clear register (NPL_SCR) after the signal became inactive again. However, the MMCREADY bit is cleared automatically after reading the MMC data register (NPL_MMCDR).

If corresponding bits in this register and in the interrupt mask register are both 1, then the IRQ0 line will be pulled low.

15
14
13
12
11
10
9
8
        NMMCD MMCD NRSINVAL RSINVAL

7
6
5
4
3
2
1
0
MMCREADY FMBUSY LANWAKEUP MMCWP RTCALARM RSRI RSDCD RSDSR RSCTS

NPL Signal Clear Register

Symbol: NPL_SCR
Memory Address: 0x21000010

Writing a 1 to any bit after the related signal became inactive clears the corresponding bit in the signal latch register (NPL_SLR).

15
14
13
12
11
10
9
8
        NMMCD MMCD NRSINVAL RSINVAL

7
6
5
4
3
2
1
0
  FMBUSY LANWAKEUP MMCWP RTCALARM RSRI RSDCD RSDSR RSCTS

See the NPL Signal Latch Register (NPL_SLR) for a description of the individual bits.

NPL MMC Data Register

Symbol: NPL_MMCDR
Memory Address: 0x21000014

This 8-bit register is used to receive a data byte from and send a data byte to the serial peripheral interface that is connected to the MMC/SD-Card socket and the serial DataFlash chip. The latter is not available on Ethernut 3.0.

Reading the register must be done first. After writing, the data byte will be shifted out and a new data byte will be shifted in.

7
6
5
4
3
2
1
0
DATA

NPL External Enable Register

Symbol: NPL_XER
Memory Address: 0x21000018

This 8-bit register is used to enable SPI devices and to control the panel select line and the green user LED.

7
6
5
4
3
2
1
0
          USRLED PANCS MMCS

NPL Version ID Register

Symbol: NPL_VIDR
Memory Address: 0x2100001C

This register contains the Version ID of the CPLD configuration.

7
6
5
4
3
2
1
0
Version Identifier

Version identifiers 0 to 15 are used for Ethernut 3.0.

Version identifiers including and above 16 are used for Ethernut 3.1 and shall never be applied to Ethernut 3.0.

Bit 7 is always 0 in standard implementations and may be set to 1 for custom configurations.

It is important to note, that not all CPLD configurations may work on every board revision. In some cases you may damage the hardware by using the wrong CPLD contents.

CPLD Programming

The XC95144XL CPLD used on Ethernut 3 can be re-programmed either by using a JTAG adapter or by running the XSVF Executor application. The CPLD configuration is defined by a high level language, either Verilog or VHDL. It is then converted to a Jedec or SVF file, which in turn is used by a special tool for CPLD programming.

Access to the CPLD JTAG port is configured by jumper block JP3. Routing the JTAG connector to the CPLD is provided by shortening pins 2 and 4, 7 and 9, 12 and 14 as well as pins 15 and 17. A special Xilinx compatible adapter is needed for programming the CPLD. So far this is not supported by the Turtelizer adapter.

The alternative method, using the XSVF Executor, is quite convenient and doesn't require any JTAG adapter at all. The Verilog or VHDL code is converted to an XSVF file (compressed SVF) and linked to the XSVF Executor application in one go. The resulting binary can be uploaded to the Ethernut board using the boot loader. As soon as the XSVF Executor starts running, it will program the CPLD via GPIO pins. The required jumper configuration is shown below.

The problem with this method is, that a badly programmed CPLD may disable the boot loader or other essential functions. To recover from such situations, you can upload the XSVF Executor binary into the CPU's internal RAM using the Turtelizer JTAG adapter and still use GPIO lines for CPLD programming.

In any case you'll need to install the Xilinx ISE WebPACK, which is available free of charge from the Xilinx download page for Windows and Linux PCs. For Mac OS a virtual machine may to the job.

Since Nut/OS beta 4.9.7 the Makefiles had been updated for VHDL support. Thus, if you want to modify the Ethernut 3.1 CPLD or if you want to write new VHDL code, you need at least this version. Note, that you still can continue using older version for your application development. Nut/OS installations allow to keep several versions concurrently on your PC.

The Ethernut 3.1 Rev-D Support Package contains a ready to use XSVF Executor setup. Copy the whole directory named npl-vhdl4-31 into the application tree that has been created by the Nut/OS Configurator for the Ethernut 3.1 D Board. Open a command line shell, change to this directory and simply run 'make clean all install'. Note, that all tools must be accessible via the PATH environment. On Windows you may use 

SET PATH=C:\ethernut-4.9.7\nut\tools\win32;C:\Programme\yagarto\bin;
  C:\Xilinx\10.1\ISE\bin\nt;C:\Xilinx\10.1\ISE\lib\nt;
  C:\Xilinx\10.1\ISE\smartmodel\nt\installed_nt\lib\pcnt.lib;%PATH%
entered in one single line. Of course your installation directories may differ and must be properly adjusted.

Latest distributions of Nut/OS allow to run 'make clean all burn', in which case the binary is uploaded via OpenOCD and the Turtelizer. This is even faster than the Ethernet boot loader and quite useful if your CPLD code disables the boot loader.

The CPLD configuration for Ethernut 3.1 is programmed in VHDL (many thanks to Michael Fischer btw.), while Verilog was used for the Ethernut 3.0 CPLD. The Verilog sources together with the XSVF Executor are available in npl30e-v6.zip. This is an older package, using a local copy of the XSVF Executor. If you want to stay up-to-date with Ethernut 3.0, install the npl-vhdl4-31 directory from the Ethernut 3.1 support package explained above. Better rename this directory to npl30e and run make clean to remove all built files. Further remove all npl31d.* files and copy npl30d.v and npl30d.ucf from the npl30e-v6.zip archive (located in subdirectory npl) to the previously renamed directory npl30e. In a last step change 

PROJ = npl31d
HDL  = VHDL
in Makedefs to 
PROJ = npl30d
HDL  = Verilog



Have fun,

Castrop-Rauxel, 24th of November 2009