Register definitions.
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Defines |
#define | EBI_BASE 0xFFE00000 |
| EBI base address.
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#define | SF_BASE 0xFFF00000 |
| Special function register base address.
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#define | USART1_BASE 0xFFFCC000 |
| USART 1 base address.
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#define | USART0_BASE 0xFFFD0000 |
| USART 0 base address.
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#define | TC_BASE 0xFFFE0000 |
| TC base address.
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#define | PIO_BASE 0xFFFF0000 |
| PIO base address.
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#define | PS_BASE 0xFFFF4000 |
| PS base address.
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#define | WD_BASE 0xFFFF8000 |
| Watch Dog register base address.
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#define | AIC_BASE 0xFFFFF000 |
#define | PERIPH_RPR_OFF 0x00000030 |
| Receive pointer register offset.
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#define | PERIPH_RCR_OFF 0x00000034 |
| Receive counter register offset.
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#define | PERIPH_TPR_OFF 0x00000038 |
| Transmit pointer register offset.
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#define | PERIPH_TCR_OFF 0x0000003C |
| Transmit counter register offset.
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#define | USART_HAS_PDC |
Peripheral Identifiers and Interrupts |
#define | FIQ_ID 0 |
| Fast interrupt ID.
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#define | SWIRQ_ID 1 |
| Software interrupt ID.
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#define | US0_ID 2 |
| USART 0 ID.
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#define | US1_ID 3 |
| USART 1 ID.
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#define | TC0_ID 4 |
| Timer 0 ID.
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#define | TC1_ID 5 |
| Timer 1 ID.
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#define | TC2_ID 6 |
| Timer 2 ID.
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#define | WDI_ID 7 |
| Watchdog interrupt ID.
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#define | PIO_ID 8 |
| Parallel I/O controller ID.
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#define | IRQ0_ID 16 |
| External interrupt 0 ID.
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#define | IRQ1_ID 17 |
| External interrupt 1 ID.
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#define | IRQ2_ID 18 |
| External interrupt 2 ID.
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USART Peripheral Multiplexing |
#define | P15_RXD0 15 |
#define | P14_TXD0 14 |
#define | P13_SCK0 13 |
#define | P22_RXD1 22 |
#define | P21_TXD1 21 |
#define | P20_SCK1 20 |
Detailed Description
Register definitions.
Define Documentation
Fast interrupt ID.
Definition at line 92 of file at91x40.h.
Software interrupt ID.
Definition at line 93 of file at91x40.h.
Watchdog interrupt ID.
Definition at line 99 of file at91x40.h.
External interrupt 0 ID.
Definition at line 101 of file at91x40.h.
External interrupt 1 ID.
Definition at line 102 of file at91x40.h.
External interrupt 2 ID.
Definition at line 103 of file at91x40.h.
#define EBI_BASE 0xFFE00000 |
#define SF_BASE 0xFFF00000 |
Special function register base address.
Definition at line 107 of file at91x40.h.
#define USART1_BASE 0xFFFCC000 |
USART 1 base address.
Definition at line 108 of file at91x40.h.
#define USART0_BASE 0xFFFD0000 |
USART 0 base address.
Definition at line 109 of file at91x40.h.
#define TC_BASE 0xFFFE0000 |
#define PIO_BASE 0xFFFF0000 |
#define PS_BASE 0xFFFF4000 |
#define WD_BASE 0xFFFF8000 |
Watch Dog register base address.
Definition at line 113 of file at91x40.h.
#define AIC_BASE 0xFFFFF000 |
#define PERIPH_RPR_OFF 0x00000030 |
Receive pointer register offset.
Definition at line 116 of file at91x40.h.
#define PERIPH_RCR_OFF 0x00000034 |
Receive counter register offset.
Definition at line 117 of file at91x40.h.
#define PERIPH_TPR_OFF 0x00000038 |
Transmit pointer register offset.
Definition at line 118 of file at91x40.h.
#define PERIPH_TCR_OFF 0x0000003C |
Transmit counter register offset.
Definition at line 119 of file at91x40.h.