at91_tc.h File Reference

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Timer Counter Base Addresses
#define	TC0_BASE   (TC_BASE + 0x00)
	Channel 0 base address.
#define	TC1_BASE   (TC_BASE + 0x40)
	Channel 1 base address.
#define	TC2_BASE   (TC_BASE + 0x80)
	Channel 2 base address.
#define	TC3_BASE   (TC_BLK1_BASE + 0x00)
	Channel 3 base address.
#define	TC4_BASE   (TC_BLK1_BASE + 0x40)
	Channel 4 base address.
#define	TC5_BASE   (TC_BLK1_BASE + 0x80)
	Channel 5 base address.
Timer Counter Control Register
#define	TC_CCR_OFF   0x00
	Control register offset.
#define	TC0_CCR   (TC0_BASE + TC_CCR_OFF)
	Channel 0 control register address.
#define	TC1_CCR   (TC1_BASE + TC_CCR_OFF)
	Channel 1 control register address.
#define	TC2_CCR   (TC2_BASE + TC_CCR_OFF)
	Channel 2 control register address.
#define	TC3_CCR   (TC3_BASE + TC_CCR_OFF)
	Channel 3 control register address.
#define	TC4_CCR   (TC4_BASE + TC_CCR_OFF)
	Channel 4 control register address.
#define	TC5_CCR   (TC5_BASE + TC_CCR_OFF)
	Channel 5 control register address.
#define	TC_CLKEN   0x00000001
	Clock enable command.
#define	TC_CLKDIS   0x00000002
	Clock disable command.
#define	TC_SWTRG   0x00000004
	Software trigger command.
Timer Counter Channel Mode Register
#define	TC_CMR_OFF   0x04
	Mode register offset.
#define	TC0_CMR   (TC0_BASE + TC_CMR_OFF)
	Channel 0 mode register address.
#define	TC1_CMR   (TC1_BASE + TC_CMR_OFF)
	Channel 1 mode register address.
#define	TC2_CMR   (TC2_BASE + TC_CMR_OFF)
	Channel 2 mode register address.
#define	TC3_CMR   (TC3_BASE + TC_CMR_OFF)
	Channel 3 mode register address.
#define	TC4_CMR   (TC4_BASE + TC_CMR_OFF)
	Channel 4 mode register address.
#define	TC5_CMR   (TC5_BASE + TC_CMR_OFF)
	Channel 5 mode register address.
#define	TC_CLKS   0x00000007
	Clock selection mask.
#define	TC_CLKS_TIMER_CLOCK1   0x00000000
	Selects timer clock 1.
#define	TC_CLKS_MCK2   TC_CLKS_TIMER_CLOCK1
	Selects MCK / 2.
#define	TC_CLKS_TIMER_CLOCK2   0x00000001
	Selects timer clock 2.
#define	TC_CLKS_MCK8   TC_CLKS_TIMER_CLOCK2
	Selects MCK / 8.
#define	TC_CLKS_TIMER_CLOCK3   0x00000002
	Selects timer clock 3.
#define	TC_CLKS_MCK32   TC_CLKS_TIMER_CLOCK3
	Selects MCK / 32.
#define	TC_CLKS_TIMER_CLOCK4   0x00000003
	Selects timer clock 4.
#define	TC_CLKS_MCK128   TC_CLKS_TIMER_CLOCK4
	Selects MCK / 128.
#define	TC_CLKS_TIMER_CLOCK5   0x00000004
	Selects timer clock 5.
#define	TC_CLKS_MCK1024   TC_CLKS_TIMER_CLOCK5
	Selects MCK / 1024 on older CPUs.
#define	TC_CLKS_SLCK   TC_CLKS_TIMER_CLOCK5
	Selects slow clock on newer CPUs.
#define	TC_CLKS_XC0   0x00000005
	Selects external clock 0.
#define	TC_CLKS_XC1   0x00000006
	Selects external clock 1.
#define	TC_CLKS_XC2   0x00000007
	Selects external clock 2.
#define	TC_CLKI   0x00000008
	Increments on falling edge.
#define	TC_BURST   0x00000030
	Burst signal selection mask.
#define	TC_BURST_NONE   0x00000000
	Clock is not gated by an external signal.
#define	TC_BUSRT_XC0   0x00000010
	ANDed with external clock 0.
#define	TC_BURST_XC1   0x00000020
	ANDed with external clock 1.
#define	TC_BURST_XC2   0x00000030
	ANDed with external clock 2.
#define	TC_CPCTRG   0x00004000
	RC Compare Enable Trigger Enable.
#define	TC_WAVE   0x00008000
	Selects waveform mode.
#define	TC_CAPT   0x00000000
	Selects capture mode.
Capture Mode
#define	TC_LDBSTOP   0x00000040
	Counter clock stopped on RB loading.
#define	TC_LDBDIS   0x00000080
	Counter clock disabled on RB loading.
#define	TC_ETRGEDG   0x00000300
	External trigger edge selection mask.
#define	TC_ETRGEDG_RISING_EDGE   0x00000100
	Trigger on external rising edge.
#define	TC_ETRGEDG_FALLING_EDGE   0x00000200
	Trigger on external falling edge.
#define	TC_ETRGEDG_BOTH_EDGE   0x00000300
	Trigger on both external edges.
#define	TC_ABETRG   0x00000400
	TIOA or TIOB external trigger selection mask.
#define	TC_ABETRG_TIOB   0x00000000
	TIOB used as an external trigger.
#define	TC_ABETRG_TIOA   0x00000400
	TIOA used as an external trigger.
#define	TC_LDRA   0x00030000
	RA loading selection mask.
#define	TC_LDRA_RISING_EDGE   0x00010000
	Load RA on rising edge of TIOA.
#define	TC_LDRA_FALLING_EDGE   0x00020000
	Load RA on falling edge of TIOA.
#define	TC_LDRA_BOTH_EDGE   0x00030000
	Load RA on any edge of TIOA.
#define	TC_LDRB   0x000C0000
	RB loading selection mask.
#define	TC_LDRB_RISING_EDGE   0x00040000
	Load RB on rising edge of TIOA.
#define	TC_LDRB_FALLING_EDGE   0x00080000
	Load RB on falling edge of TIOA.
#define	TC_LDRB_BOTH_EDGE   0x000C0000
	Load RB on any edge of TIOA.
Waveform Mode
#define	TC_CPCSTOP   0x00000040
	Counter clock stopped on RC compare.
#define	TC_CPCDIS   0x00000080
	Counter clock disabled on RC compare.
#define	TC_EEVTEDG   0x00000300
	External event edge selection mask.
#define	TC_EEVTEDG_RISING_EDGE   0x00000100
	External event on rising edge..
#define	TC_EEVTEDG_FALLING_EDGE   0x00000200
	External event on falling edge..
#define	TC_EEVTEDG_BOTH_EDGE   0x00000300
	External event on any edge..
#define	TC_EEVT   0x00000C00
	External event selection mask.
#define	TC_EEVT_TIOB   0x00000000
	TIOB selected as external event.
#define	TC_EEVT_XC0   0x00000400
	XC0 selected as external event.
#define	TC_EEVT_XC1   0x00000800
	XC1 selected as external event.
#define	TC_EEVT_XC2   0x00000C00
	XC2 selected as external event.
#define	TC_ENETRG   0x00001000
	External event trigger enable.
#define	TC_WAVSEL_UPDOWN   0x00002000
	Count up and down.
#define	TC_WAVSEL_RCTRIG   0x00004000
	Automatic trigger on RC compare.
#define	TC_ACPA   0x00030000
	Masks RA compare effect on TIOA.
#define	TC_ACPA_SET_OUTPUT   0x00010000
	RA compare sets TIOA.
#define	TC_ACPA_CLEAR_OUTPUT   0x00020000
	RA compare clears TIOA.
#define	TC_ACPA_TOGGLE_OUTPUT   0x00030000
	RA compare toggles TIOA.
#define	TC_ACPC   0x000C0000
	Masks RC compare effect on TIOA.
#define	TC_ACPC_SET_OUTPUT   0x00040000
	RC compare sets TIOA.
#define	TC_ACPC_CLEAR_OUTPUT   0x00080000
	RC compare clears TIOA.
#define	TC_ACPC_TOGGLE_OUTPUT   0x000C0000
	RC compare toggles TIOA.
#define	TC_AEEVT   0x00300000
	Masks external event effect on TIOA.
#define	TC_AEEVT_SET_OUTPUT   0x00100000
	External event sets TIOA.
#define	TC_AEEVT_CLEAR_OUTPUT   0x00200000
	External event clears TIOA.
#define	TC_AEEVT_TOGGLE_OUTPUT   0x00300000
	External event toggles TIOA.
#define	TC_ASWTRG   0x00C00000
	Masks software trigger effect on TIOA.
#define	TC_ASWTRG_SET_OUTPUT   0x00400000
	Software trigger sets TIOA.
#define	TC_ASWTRG_CLEAR_OUTPUT   0x00800000
	Software trigger clears TIOA.
#define	TC_ASWTRG_TOGGLE_OUTPUT   0x00C00000
	Software trigger toggles TIOA.
#define	TC_BCPB   0x03000000
	Masks RB compare effect on TIOB.
#define	TC_BCPB_SET_OUTPUT   0x01000000
	RB compare sets TIOB.
#define	TC_BCPB_CLEAR_OUTPUT   0x02000000
	RB compare clears TIOB.
#define	TC_BCPB_TOGGLE_OUTPUT   0x03000000
	RB compare toggles TIOB.
#define	TC_BCPC   0x0C000000
	Masks RC compare effect on TIOB.
#define	TC_BCPC_SET_OUTPUT   0x04000000
	RC compare sets TIOB.
#define	TC_BCPC_CLEAR_OUTPUT   0x08000000
	RC compare clears TIOB.
#define	TC_BCPC_TOGGLE_OUTPUT   0x0C000000
	RC compare toggles TIOB.
#define	TC_BEEVT   0x30000000
	Masks external event effect on TIOB.
#define	TC_BEEVT_SET_OUTPUT   0x10000000
	External event sets TIOB.
#define	TC_BEEVT_CLEAR_OUTPUT   0x20000000
	External event clears TIOB.
#define	TC_BEEVT_TOGGLE_OUTPUT   0x30000000
	External event toggles TIOB.
#define	TC_BSWTRG   0xC0000000
	Masks software trigger effect on TIOB.
#define	TC_BSWTRG_SET_OUTPUT   0x40000000
	Software trigger sets TIOB.
#define	TC_BSWTRG_CLEAR_OUTPUT   0x80000000
	Software trigger clears TIOB.
#define	TC_BSWTRG_TOGGLE_OUTPUT   0xC0000000
	Software trigger toggles TIOB.
Counter Value Register
#define	TC_CV_OFF   0x10
	Counter value register offset.
#define	TC0_CV   (TC0_BASE + TC_CV_OFF)
	Counter 0 value.
#define	TC1_CV   (TC1_BASE + TC_CV_OFF)
	Counter 1 value.
#define	TC2_CV   (TC2_BASE + TC_CV_OFF)
	Counter 2 value.
#define	TC3_CV   (TC3_BASE + TC_CV_OFF)
	Counter 3 value.
#define	TC4_CV   (TC4_BASE + TC_CV_OFF)
	Counter 4 value.
#define	TC5_CV   (TC5_BASE + TC_CV_OFF)
	Counter 5 value.
Timer Counter Register A
#define	TC_RA_OFF   0x14
	Register A offset.
#define	TC0_RA   (TC0_BASE + TC_RA_OFF)
	Channel 0 register A.
#define	TC1_RA   (TC1_BASE + TC_RA_OFF)
	Channel 1 register A.
#define	TC2_RA   (TC2_BASE + TC_RA_OFF)
	Channel 2 register A.
#define	TC3_RA   (TC3_BASE + TC_RA_OFF)
	Channel 3 register A.
#define	TC4_RA   (TC4_BASE + TC_RA_OFF)
	Channel 4 register A.
#define	TC5_RA   (TC5_BASE + TC_RA_OFF)
	Channel 5 register A.
Timer Counter Register B
#define	TC_RB_OFF   0x18
	Register B offset.
#define	TC0_RB   (TC0_BASE + TC_RB_OFF)
	Channel 0 register B.
#define	TC1_RB   (TC1_BASE + TC_RB_OFF)
	Channel 1 register B.
#define	TC2_RB   (TC2_BASE + TC_RB_OFF)
	Channel 2 register B.
#define	TC3_RB   (TC3_BASE + TC_RB_OFF)
	Channel 3 register B.
#define	TC4_RB   (TC4_BASE + TC_RB_OFF)
	Channel 4 register B.
#define	TC5_RB   (TC5_BASE + TC_RB_OFF)
	Channel 5 register B.
Timer Counter Register C
#define	TC_RC_OFF   0x1C
	Register C offset.
#define	TC0_RC   (TC0_BASE + TC_RC_OFF)
	Channel 0 register C.
#define	TC1_RC   (TC1_BASE + TC_RC_OFF)
	Channel 1 register C.
#define	TC2_RC   (TC2_BASE + TC_RC_OFF)
	Channel 2 register C.
#define	TC3_RC   (TC3_BASE + TC_RC_OFF)
	Channel 3 register C.
#define	TC4_RC   (TC4_BASE + TC_RC_OFF)
	Channel 4 register C.
#define	TC5_RC   (TC5_BASE + TC_RC_OFF)
	Channel 5 register C.
Timer Counter Status and Interrupt Registers
#define	TC_SR_OFF   0x20
	Status register offset.
#define	TC0_SR   (TC0_BASE + TC_SR_OFF)
	Channel 0 status register address.
#define	TC1_SR   (TC1_BASE + TC_SR_OFF)
	Channel 1 status register address.
#define	TC2_SR   (TC2_BASE + TC_SR_OFF)
	Channel 2 status register address.
#define	TC3_SR   (TC3_BASE + TC_SR_OFF)
	Channel 3 status register address.
#define	TC4_SR   (TC4_BASE + TC_SR_OFF)
	Channel 4 status register address.
#define	TC5_SR   (TC5_BASE + TC_SR_OFF)
	Channel 5 status register address.
#define	TC_IER_OFF   0x24
	Interrupt enable register offset.
#define	TC0_IER   (TC0_BASE + TC_IER_OFF)
	Channel 0 interrupt enable register address.
#define	TC1_IER   (TC1_BASE + TC_IER_OFF)
	Channel 1 interrupt enable register address.
#define	TC2_IER   (TC2_BASE + TC_IER_OFF)
	Channel 2 interrupt enable register address.
#define	TC3_IER   (TC3_BASE + TC_IER_OFF)
	Channel 3 interrupt enable register address.
#define	TC4_IER   (TC4_BASE + TC_IER_OFF)
	Channel 4 interrupt enable register address.
#define	TC5_IER   (TC5_BASE + TC_IER_OFF)
	Channel 5 interrupt enable register address.
#define	TC_IDR_OFF   0x28
	Interrupt disable register offset.
#define	TC0_IDR   (TC0_BASE + TC_IDR_OFF)
	Channel 0 interrupt disable register address.
#define	TC1_IDR   (TC1_BASE + TC_IDR_OFF)
	Channel 1 interrupt disable register address.
#define	TC2_IDR   (TC2_BASE + TC_IDR_OFF)
	Channel 2 interrupt disable register address.
#define	TC3_IDR   (TC3_BASE + TC_IDR_OFF)
	Channel 3 interrupt disable register address.
#define	TC4_IDR   (TC4_BASE + TC_IDR_OFF)
	Channel 4 interrupt disable register address.
#define	TC5_IDR   (TC5_BASE + TC_IDR_OFF)
	Channel 5 interrupt disable register address.
#define	TC_IMR_OFF   0x2C
	Interrupt mask register offset.
#define	TC0_IMR   (TC0_BASE + TC_IMR_OFF)
	Channel 0 interrupt mask register address.
#define	TC1_IMR   (TC1_BASE + TC_IMR_OFF)
	Channel 1 interrupt mask register address.
#define	TC2_IMR   (TC2_BASE + TC_IMR_OFF)
	Channel 2 interrupt mask register address.
#define	TC3_IMR   (TC3_BASE + TC_IMR_OFF)
	Channel 3 interrupt mask register address.
#define	TC4_IMR   (TC4_BASE + TC_IMR_OFF)
	Channel 4 interrupt mask register address.
#define	TC5_IMR   (TC5_BASE + TC_IMR_OFF)
	Channel 5 interrupt mask register address.
#define	TC_COVFS   0x00000001
	Counter overflow flag.
#define	TC_LOVRS   0x00000002
	Load overrun flag.
#define	TC_CPAS   0x00000004
	RA compare flag.
#define	TC_CPBS   0x00000008
	RB compare flag.
#define	TC_CPCS   0x00000010
	RC compare flag.
#define	TC_LDRAS   0x00000020
	RA loading flag.
#define	TC_LDRBS   0x00000040
	RB loading flag.
#define	TC_ETRGS   0x00000080
	External trigger flag.
#define	TC_CLKSTA   0x00010000
	Clock enable flag.
#define	TC_MTIOA   0x00020000
	TIOA flag.
#define	TC_MTIOB   0x00040000
	TIOB flag.
Timer Counter Block Control Register
#define	TC_BCR_OFF   0xC0
	Block control register offset.
#define	TC_BKL0_CR   (TC_BASE + TC_BCR_OFF)
	Block 0 control register address.
#define	TC_BCR   TC_BKL0_CR
	Block control register address.
#define	TC_BKL1_CR   (TC_BLK1_BASE + TC_BCR_OFF)
	Block 1 control register address.
#define	TC_SYNC   0x00000001
	Synchronisation trigger.
Timer Counter Block Mode Register
#define	TC_BMR_OFF   0xC4
	Block mode register offset.
#define	TC_BLK0_MR   (TC_BASE + TC_BMR_OFF)
	Block 0 mode register address.
#define	TC_BMR   TC_BKL0_MR
	Block control register address.
#define	TC_BLK1_MR   (TC_BLK1_BASE + TC_BMR_OFF)
	Block 1 mode register address.
#define	TC_TC0XC0S   0x00000003
	External clock signal 0 selection mask.
#define	TC_TCLK0XC0   0x00000000
	Selects TCLK0.
#define	TC_NONEXC0   0x00000001
	None selected.
#define	TC_TIOA1XC0   0x00000002
	Selects TIOA1.
#define	TC_TIOA2XC0   0x00000003
	Selects TIOA2.
#define	TC_TC1XC1S   0x0000000C
	External clock signal 1 selection mask.
#define	TC_TCLK1XC1   0x00000000
	Selects TCLK1.
#define	TC_NONEXC1   0x00000004
	None selected.
#define	TC_TIOA0XC1   0x00000008
	Selects TIOA0.
#define	TC_TIOA2XC1   0x0000000C
	Selects TIOA2.
#define	TC_TC2XC2S   0x00000030
	External clock signal 2 selection mask.
#define	TC_TCLK2XC2   0x00000000
	Selects TCLK2.
#define	TC_NONEXC2   0x00000010
	None selected.
#define	TC_TIOA0XC2   0x00000020
	Selects TIOA0.
#define	TC_TIOA1XC2   0x00000030
	Selects TIOA1.