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00022
00023 #ifndef __STM32F10x_ADC_H
00024 #define __STM32F10x_ADC_H
00025
00026
00027 #include "stm32f10x.h"
00028
00045 typedef struct
00046 {
00047 uint32_t ADC_Mode;
00048 FunctionalState ADC_ScanConvMode;
00049 FunctionalState ADC_ContinuousConvMode;
00050 uint32_t ADC_ExternalTrigConv;
00051 uint32_t ADC_DataAlign;
00052 uint8_t ADC_NbrOfChannel;
00053 }ADC_InitTypeDef;
00062 #define IS_ADC_ALL_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
00063 ((*(uint32_t*)&(PERIPH)) == ADC2_BASE) || \
00064 ((*(uint32_t*)&(PERIPH)) == ADC3_BASE))
00065
00066 #define IS_ADC_DMA_PERIPH(PERIPH) (((*(uint32_t*)&(PERIPH)) == ADC1_BASE) || \
00067 ((*(uint32_t*)&(PERIPH)) == ADC3_BASE))
00068
00073 #define ADC_Mode_Independent ((uint32_t)0x00000000)
00074 #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
00075 #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
00076 #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
00077 #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
00078 #define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
00079 #define ADC_Mode_RegSimult ((uint32_t)0x00060000)
00080 #define ADC_Mode_FastInterl ((uint32_t)0x00070000)
00081 #define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
00082 #define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
00083
00084 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
00085 ((MODE) == ADC_Mode_RegInjecSimult) || \
00086 ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
00087 ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
00088 ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
00089 ((MODE) == ADC_Mode_InjecSimult) || \
00090 ((MODE) == ADC_Mode_RegSimult) || \
00091 ((MODE) == ADC_Mode_FastInterl) || \
00092 ((MODE) == ADC_Mode_SlowInterl) || \
00093 ((MODE) == ADC_Mode_AlterTrig))
00094
00106 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
00107 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
00108 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
00109 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
00110 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
00111 #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
00112
00117 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
00118 #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
00119
00124 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
00125 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
00126 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
00127 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
00128 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
00129 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
00130
00131 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
00132 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
00133 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
00134 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
00135 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
00136 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
00137 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
00138 ((REGTRIG) == ADC_ExternalTrigConv_None) || \
00139 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
00140 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
00141 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
00142 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
00143 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
00144 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
00145
00153 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
00154 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
00155 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
00156 ((ALIGN) == ADC_DataAlign_Left))
00157
00165 #define ADC_Channel_0 ((uint8_t)0x00)
00166 #define ADC_Channel_1 ((uint8_t)0x01)
00167 #define ADC_Channel_2 ((uint8_t)0x02)
00168 #define ADC_Channel_3 ((uint8_t)0x03)
00169 #define ADC_Channel_4 ((uint8_t)0x04)
00170 #define ADC_Channel_5 ((uint8_t)0x05)
00171 #define ADC_Channel_6 ((uint8_t)0x06)
00172 #define ADC_Channel_7 ((uint8_t)0x07)
00173 #define ADC_Channel_8 ((uint8_t)0x08)
00174 #define ADC_Channel_9 ((uint8_t)0x09)
00175 #define ADC_Channel_10 ((uint8_t)0x0A)
00176 #define ADC_Channel_11 ((uint8_t)0x0B)
00177 #define ADC_Channel_12 ((uint8_t)0x0C)
00178 #define ADC_Channel_13 ((uint8_t)0x0D)
00179 #define ADC_Channel_14 ((uint8_t)0x0E)
00180 #define ADC_Channel_15 ((uint8_t)0x0F)
00181 #define ADC_Channel_16 ((uint8_t)0x10)
00182 #define ADC_Channel_17 ((uint8_t)0x11)
00183
00184 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
00185 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
00186 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
00187 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
00188 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
00189 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
00190 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
00191 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
00192 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
00193
00201 #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
00202 #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
00203 #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
00204 #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
00205 #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
00206 #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
00207 #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
00208 #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
00209 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
00210 ((TIME) == ADC_SampleTime_7Cycles5) || \
00211 ((TIME) == ADC_SampleTime_13Cycles5) || \
00212 ((TIME) == ADC_SampleTime_28Cycles5) || \
00213 ((TIME) == ADC_SampleTime_41Cycles5) || \
00214 ((TIME) == ADC_SampleTime_55Cycles5) || \
00215 ((TIME) == ADC_SampleTime_71Cycles5) || \
00216 ((TIME) == ADC_SampleTime_239Cycles5))
00217
00229 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
00230 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
00231 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
00232 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
00233 #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
00234
00239 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
00240 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
00241 #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
00242
00247 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
00248 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
00249 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
00250 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
00251 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
00252
00253 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
00254 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
00255 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
00256 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
00257 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
00258 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
00259 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
00260 ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
00261 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
00262 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
00263 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
00264 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
00265 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
00266
00274 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
00275 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
00276 #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
00277 #define ADC_InjectedChannel_4 ((uint8_t)0x20)
00278 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
00279 ((CHANNEL) == ADC_InjectedChannel_2) || \
00280 ((CHANNEL) == ADC_InjectedChannel_3) || \
00281 ((CHANNEL) == ADC_InjectedChannel_4))
00282
00290 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
00291 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
00292 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
00293 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
00294 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
00295 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
00296 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
00297
00298 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
00299 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
00300 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
00301 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
00302 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
00303 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
00304 ((WATCHDOG) == ADC_AnalogWatchdog_None))
00305
00313 #define ADC_IT_EOC ((uint16_t)0x0220)
00314 #define ADC_IT_AWD ((uint16_t)0x0140)
00315 #define ADC_IT_JEOC ((uint16_t)0x0480)
00316
00317 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
00318
00319 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
00320 ((IT) == ADC_IT_JEOC))
00321
00329 #define ADC_FLAG_AWD ((uint8_t)0x01)
00330 #define ADC_FLAG_EOC ((uint8_t)0x02)
00331 #define ADC_FLAG_JEOC ((uint8_t)0x04)
00332 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
00333 #define ADC_FLAG_STRT ((uint8_t)0x10)
00334 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
00335 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
00336 ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
00337 ((FLAG) == ADC_FLAG_STRT))
00338
00346 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
00347
00356 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
00357
00366 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
00367
00376 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
00377
00387 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
00388
00396 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
00397
00406 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
00407
00428 typedef struct
00429 {
00430 __IO uint32_t SR;
00431 __IO uint32_t CR1;
00432 __IO uint32_t CR2;
00433 __IO uint32_t SMPR1;
00434 __IO uint32_t SMPR2;
00435 __IO uint32_t JOFR1;
00436 __IO uint32_t JOFR2;
00437 __IO uint32_t JOFR3;
00438 __IO uint32_t JOFR4;
00439 __IO uint32_t HTR;
00440 __IO uint32_t LTR;
00441 __IO uint32_t SQR1;
00442 __IO uint32_t SQR2;
00443 __IO uint32_t SQR3;
00444 __IO uint32_t JSQR;
00445 __IO uint32_t JDR1;
00446 __IO uint32_t JDR2;
00447 __IO uint32_t JDR3;
00448 __IO uint32_t JDR4;
00449 __IO uint32_t DR;
00450 } ADC_TypeDef;
00451
00452
00453 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
00454 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
00455 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
00456 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
00457 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
00458 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
00459
00460
00461 #endif
00462
00475