MP3 Decoder. More...
Data Structures | |
struct | VS_HEADERINFO |
Defines | |
#define | VS_OPCODE_READ 3 |
#define | VS_OPCODE_WRITE 2 |
#define | VS_MODE_REG 0 |
#define | VS_STATUS_REG 1 |
#define | VS_INT_FCTLH_REG 2 |
#define | VS_CLOCKF_REG 3 |
#define | VS_DECODE_TIME_REG 4 |
#define | VS_AUDATA_REG 5 |
#define | VS_WRAM_REG 6 |
#define | VS_WRAMADDR_REG 7 |
#define | VS_HDAT0_REG 8 |
#define | VS_HDAT1_REG 9 |
#define | VS_A1ADDR_REG 10 |
#define | VS_VOL_REG 11 |
#define | VS_A1CTRL_REG 13 |
#define | VS_SM_DIFF 0x0001 |
#define | VS_SM_FFWD 0x0002 |
#define | VS_SM_RESET 0x0004 |
#define | VS_SM_MP12 0x0008 |
#define | VS_SM_PDOWN 0x0010 |
#define | VS_SM_DAC 0x0020 |
#define | VS_SM_DACMONO 0x0040 |
#define | VS_SM_BASS 0x0080 |
#define | VS_SM_DACT 0x0100 |
#define | VS_SM_BYTEORD 0x0200 |
#define | VS_SM_IBMODE 0x0400 |
#define | VS_SM_IBCLK 0x0800 |
#define | VS_CF_DOUBLER 0x8000 |
#define | VS_FLUSH_BYTES 2048 |
#define | VS_STATUS_STOPPED 0 |
#define | VS_STATUS_RUNNING 1 |
#define | VS_STATUS_EOF 2 |
#define | VS_STATUS_EMPTY 4 |
#define | VS_SCK_BIT 0 |
VS1001 serial control interface clock input bit. | |
#define | VS_SCK_PORT PORTB |
#define | VS_SCK_DDR DDRB |
#define | VS_SS_BIT 1 |
VS1001 serial data interface clock input bit. | |
#define | VS_SS_PORT PORTB |
#define | VS_SS_DDR DDRB |
#define | VS_SI_BIT 2 |
VS1001 serial control interface data input. | |
#define | VS_SI_PORT PORTB |
#define | VS_SI_DDR DDRB |
#define | VS_SO_BIT 3 |
VS1001 serial control interface data output. | |
#define | VS_SO_PIN PINB |
#define | VS_SO_DDR DDRB |
#define | VS_XCS_BIT 4 |
VS1001 active low chip select input. | |
#define | VS_XCS_PORT PORTB |
#define | VS_XCS_DDR DDRB |
#define | VS_BSYNC_BIT 5 |
VS1001 serial data interface bit sync. | |
#define | VS_BSYNC_PORT PORTB |
#define | VS_BSYNC_DDR DDRB |
#define | VS_RESET_BIT 7 |
VS1001 hardware reset input. | |
#define | VS_RESET_PORT PORTB |
#define | VS_RESET_DDR DDRB |
#define | VS_SIGNAL sig_INTERRUPT6 |
VS1001 data request interrupt. | |
#define | VS_DREQ_BIT 6 |
#define | VS_DREQ_PORT PORTE |
#define | VS_DREQ_PIN PINE |
#define | VS_DREQ_DDR DDRE |
Functions | |
uint8_t | VsPlayerInterrupts (uint8_t enable) |
Enable or disable player interrupts. | |
uint8_t * | VsBufferInit (uint16_t size) |
uint8_t * | VsBufferReset (void) |
uint8_t * | VsBufferRequest (uint16_t *sizep) |
uint8_t * | VsBufferAcknowledge (uint16_t nbytes) |
uint16_t | VsBufferAvailable (void) |
int | VsSetVolume (uint8_t left, uint8_t right) |
Set volume. |
MP3 Decoder.
#define VS_OPCODE_READ 3 |
Referenced by FeederThread(), and VsCodecMode().
#define VS_OPCODE_WRITE 2 |
Referenced by FeederThread(), VsCodecMode(), VsDecoderSetBass(), and VsDecoderSetVolume().
#define VS_MODE_REG 0 |
Referenced by VsCodecMode(), VsPlayerReset(), and VsPlayerSetMode().
#define VS_STATUS_REG 1 |
#define VS_INT_FCTLH_REG 2 |
Referenced by VsPlayerInit(), and VsPlayerReset().
#define VS_CLOCKF_REG 3 |
Referenced by VsPlayerInit(), and VsPlayerReset().
#define VS_DECODE_TIME_REG 4 |
Referenced by VsPlayTime().
#define VS_AUDATA_REG 5 |
#define VS_WRAM_REG 6 |
#define VS_WRAMADDR_REG 7 |
#define VS_HDAT0_REG 8 |
Referenced by VsGetHeaderInfo(), and VsMemoryTest().
#define VS_HDAT1_REG 9 |
Referenced by FeederThread(), and VsGetHeaderInfo().
#define VS_A1ADDR_REG 10 |
#define VS_VOL_REG 11 |
Referenced by FeederThread(), VsDecoderSetVolume(), and VsSetVolume().
#define VS_A1CTRL_REG 13 |
#define VS_SM_DIFF 0x0001 |
#define VS_SM_FFWD 0x0002 |
#define VS_SM_RESET 0x0004 |
Referenced by VsCodecBeep(), VsCodecMode(), VsCodecOpen(), and VsPlayerReset().
#define VS_SM_MP12 0x0008 |
#define VS_SM_PDOWN 0x0010 |
#define VS_SM_DAC 0x0020 |
#define VS_SM_DACMONO 0x0040 |
#define VS_SM_BASS 0x0080 |
#define VS_SM_DACT 0x0100 |
#define VS_SM_BYTEORD 0x0200 |
#define VS_SM_IBMODE 0x0400 |
#define VS_SM_IBCLK 0x0800 |
#define VS_CF_DOUBLER 0x8000 |
#define VS_FLUSH_BYTES 2048 |
#define VS_STATUS_STOPPED 0 |
Referenced by VsPlayerReset(), and VsPlayerStop().
#define VS_STATUS_RUNNING 1 |
Referenced by VsPlayerFlush(), VsPlayerKick(), and VsPlayerStop().
#define VS_STATUS_EOF 2 |
#define VS_STATUS_EMPTY 4 |
Referenced by VsPlayerFlush().
#define VS_SCK_BIT 0 |
VS1001 serial control interface clock input bit.
The first rising clock edge after XCS has gone low marks the first bit to be written to the decoder.
Referenced by VsPlayerInit().
#define VS_SCK_PORT PORTB |
Port register of VS_SCK_BIT.
Referenced by VsPlayerInit().
#define VS_SCK_DDR DDRB |
Data direction register of VS_SCK_BIT.
Referenced by VsPlayerInit().
#define VS_SS_BIT 1 |
VS1001 serial data interface clock input bit.
Referenced by VsPlayerInit().
#define VS_SS_PORT PORTB |
Port output register of VS_SS_BIT.
#define VS_SS_DDR DDRB |
Data direction register of VS_SS_BIT.
Referenced by VsPlayerInit().
#define VS_SI_BIT 2 |
VS1001 serial control interface data input.
The decoder samples this input on the rising edge of SCK if XCS is low.
Referenced by VsPlayerInit().
#define VS_SI_PORT PORTB |
Port output register of VS_SI_BIT.
#define VS_SI_DDR DDRB |
Data direction register of VS_SI_BIT.
Referenced by VsPlayerInit().
#define VS_SO_BIT 3 |
VS1001 serial control interface data output.
If data is transfered from the decoder, bits are shifted out on the falling SCK edge. If data is transfered to the decoder, SO is at a high impedance state.
Referenced by VsPlayerInit().
#define VS_SO_PIN PINB |
Port input register of VS_SO_BIT.
#define VS_SO_DDR DDRB |
Data direction register of VS_SO_BIT.
Referenced by VsPlayerInit().
#define VS_XCS_BIT 4 |
VS1001 active low chip select input.
A high level forces the serial interface into standby mode, ending the current operation. A high level also forces serial output (SO) to high impedance state.
Referenced by VsPlayerInit().
#define VS_XCS_PORT PORTB |
Port output register of VS_XCS_BIT.
Referenced by VsPlayerInit().
#define VS_XCS_DDR DDRB |
Data direction register of VS_XCS_BIT.
Referenced by VsPlayerInit().
#define VS_BSYNC_BIT 5 |
VS1001 serial data interface bit sync.
The first DCLK sampling edge, during which BSYNC is high, marks the first bit of a data byte.
Referenced by VsPlayerInit().
#define VS_BSYNC_PORT PORTB |
Port output register of VS_BSYNC_BIT.
Referenced by VsPlayerInit().
#define VS_BSYNC_DDR DDRB |
Data direction register of VS_BSYNC_BIT.
Referenced by VsPlayerInit().
#define VS_RESET_BIT 7 |
VS1001 hardware reset input.
Referenced by VsPlayerInit(), and VsPlayerReset().
#define VS_RESET_PORT PORTB |
Port output register of VS_RESET_BIT.
Referenced by VsPlayerInit(), and VsPlayerReset().
#define VS_RESET_DDR DDRB |
Data direction register of VS_RESET_BIT.
Referenced by VsPlayerInit().
#define VS_SIGNAL sig_INTERRUPT6 |
VS1001 data request interrupt.
Referenced by VsPlayerInit(), and VsPlayerInterrupts().
#define VS_DREQ_BIT 6 |
Referenced by VsPlayerInit(), and VsPlayerReset().
#define VS_DREQ_PORT PORTE |
Port output register of VS_DREQ_BIT.
Referenced by VsPlayerInit().
#define VS_DREQ_PIN PINE |
Port input register of VS_DREQ_BIT.
Referenced by VsPlayerReset().
#define VS_DREQ_DDR DDRE |
Data direction register of VS_DREQ_BIT.
Referenced by VsPlayerInit().
Enable or disable player interrupts.
This routine is typically used by applications when dealing with unprotected buffers.
enable | Disables interrupts when zero. Otherwise interrupts are enabled. |
References NutIrqDisable(), NutIrqEnable(), rc, and VS_SIGNAL.
Referenced by VsBeep(), VsGetHeaderInfo(), VsMemoryTest(), VsPlayerFlush(), VsPlayerInit(), VsPlayerKick(), VsPlayerReset(), VsPlayerSetMode(), VsPlayerStop(), VsPlayTime(), and VsSetVolume().
uint8_t* VsBufferReset | ( | void | ) |
uint16_t VsBufferAvailable | ( | void | ) |
Set volume.
left | Left channel volume. |
right | Right channel volume. |
References VS_VOL_REG, and VsPlayerInterrupts().