ADC Control Register | |
#define | ADC_CR_OFF 0x00000000 |
#define | ADC_CR_CH_SEL(x) _BV(x) |
#define | ADC_CR_CLKDIV(d) ((n) << 8) |
#define | ADC_CR_BURST _BV(16) |
#define | ADC_CR_PDN _BV(21) |
#define | ADC_CR_START_MODE_SEL(x) ((x) << 24) |
#define | ADC_CR_START_MASK ADC_CR_START_MODE_SEL(7) |
#define | ADC_CR_START_NOW (1UL<<24)) |
#define | ADC_CR_START_EINT0 (2 << 24) |
#define | ADC_CR_START_CAP01 (3 << 24) |
#define | ADC_CR_START_MAT01 (4 << 24) |
#define | ADC_CR_START_MAT03 (5 << 24) |
#define | ADC_CR_START_MAT10 (6 << 24) |
#define | ADC_CR_START_MAT11 (7 << 24) |
#define | ADC_CR_EDGE _BV(27) |
ADC Global Data Register | |
#define | ADC_GDR_OFF 0x00000004 |
#define | ADC_GDR_RESULT(x) (((x) >> 4) & 0xFFF) |
#define | ADC_GDR_CH(x) (((x) >> 24) & 7) |
#define | ADC_GDR_CH_MASK (7 << 24) |
#define | ADC_GDR_OVERRUN_FLAG _BV(30) |
#define | ADC_GDR_DONE_FLAG _BV(31) |
ADC Interrupt Register | |
#define | ADC_INTEN_OFF 0x0000000C |
#define | ADC_INTEN_CH(x) _BV(x) |
#define | ADC_INTEN_GLOBAL _BV(8) |
ADC Data Registers | |
#define | ADC_DR_OFF(x) ((x) * 4 + 0x00000010) |
#define | ADC_DR_OVERRUN_FLAG _BV(30) |
#define | ADC_DR_DONE_FLAG _BV(31) |
ADC Status Register | |
#define | ADC_STAT_OFF 0x00000030 |
#define | ADC_STAT_CH_DONE_FLAG(x) _BV(x) |
#define | ADC_STAT_CH_OVERRUN_FLAG(x) _BV((x) + 8) |
#define | ADC_STAT_INT_FLAG _BV(16) |
ADC Trim Register | |
#define | ADC_TRIM_OFF 0x00000034 |
#define ADC_CR_OFF 0x00000000 |
#define ADC_CR_CH_SEL | ( | x | ) | _BV(x) |
#define ADC_CR_CLKDIV | ( | d | ) | ((n) << 8) |
#define ADC_CR_BURST _BV(16) |
#define ADC_CR_PDN _BV(21) |
#define ADC_CR_START_MODE_SEL | ( | x | ) | ((x) << 24) |
#define ADC_CR_START_MASK ADC_CR_START_MODE_SEL(7) |
#define ADC_CR_START_NOW (1UL<<24)) |
#define ADC_CR_START_EINT0 (2 << 24) |
#define ADC_CR_START_CAP01 (3 << 24) |
#define ADC_CR_START_MAT01 (4 << 24) |
#define ADC_CR_START_MAT03 (5 << 24) |
#define ADC_CR_START_MAT10 (6 << 24) |
#define ADC_CR_START_MAT11 (7 << 24) |
#define ADC_CR_EDGE _BV(27) |
#define ADC_GDR_OFF 0x00000004 |
#define ADC_GDR_RESULT | ( | x | ) | (((x) >> 4) & 0xFFF) |
#define ADC_GDR_CH | ( | x | ) | (((x) >> 24) & 7) |
#define ADC_GDR_CH_MASK (7 << 24) |
#define ADC_GDR_OVERRUN_FLAG _BV(30) |
#define ADC_GDR_DONE_FLAG _BV(31) |
#define ADC_INTEN_OFF 0x0000000C |
#define ADC_INTEN_CH | ( | x | ) | _BV(x) |
#define ADC_INTEN_GLOBAL _BV(8) |
#define ADC_DR_OFF | ( | x | ) | ((x) * 4 + 0x00000010) |
#define ADC_DR_OVERRUN_FLAG _BV(30) |
#define ADC_DR_DONE_FLAG _BV(31) |
#define ADC_STAT_OFF 0x00000030 |
#define ADC_STAT_CH_DONE_FLAG | ( | x | ) | _BV(x) |
#define ADC_STAT_CH_OVERRUN_FLAG | ( | x | ) | _BV((x) + 8) |
#define ADC_STAT_INT_FLAG _BV(16) |
#define ADC_TRIM_OFF 0x00000034 |