XgNutArchArmLpcTim

Timer Interrupt Register
#define	TIM_IR_OFF   0x00000000
#define	TIM_IR_MR0   0x00000001
#define	TIM_IR_MR1   0x00000002
#define	TIM_IR_MR2   0x00000004
#define	TIM_IR_MR3   0x00000008
#define	TIM_IR_MR(x)   _BV(x)
#define	TIM_IR_CR0   0x00000010
#define	TIM_IR_CR1   0x00000020
#define	TIM_IR_CR(x)   _BV((x) + 4)
Timer Control Register
#define	TIM_TCR_OFF   0x00000004
#define	TIM_TCR_ENA   0x00000001
#define	TIM_ENABLE   TIM_TCR_ENA
#define	TIM_TCR_RST   0x00000002
#define	TIM_RESET   TIM_TCR_RST
Timer Counter Register
#define	TIM_TC_OFF   0x00000008
Timer Prescale Register
#define	TIM_PR_OFF   0x0000000C
Timer Prescale Counter Register
#define	TIM_PC_OFF   0x00000010
Timer Match Control Register
#define	TIM_MCR_OFF   0x00000014
#define	TIM_MCR_MR0I   0x00000001
#define	TIM_MCR_MR0R   0x00000002
#define	TIM_MCR_MR0S   0x00000004
#define	TIM_MCR_MR1I   0x00000008
#define	TIM_MCR_MR1R   0x00000010
#define	TIM_MCR_MR1S   0x00000020
#define	TIM_MCR_MR2I   0x00000040
#define	TIM_MCR_MR2R   0x00000080
#define	TIM_MCR_MR2S   0x00000100
#define	TIM_MCR_MR3I   0x00000200
#define	TIM_MCR_MR3R   0x00000400
#define	TIM_MCR_MR3S   0x00000800
#define	TIM_INT_ON_MATCH(x)   _BV((x) * 3)
#define	TIM_RESET_ON_MATCH(x)   _BV((x) * 3 + 1)
#define	TIM_STOP_ON_MATCH(x)   _BV((x) * 3 + 2)
#define	TIM_MCR_CHANNEL_MASK(x)   (7 << ((x) * 3))
Timer Match Registers
#define	TIM_MR_OFF(x)   (0x00000018 + ((x) * 4))
Timer Capture Control Register
#define	TIM_CCR_OFF   0x00000028
#define	TIM_CAP_RISING(x)   _BV((x) * 3)
#define	TIM_CAP_FALLING(x)   _BV((x) * 3 + 1)
#define	TIM_INT_ON_CAP(x)   _BV((x) * 3 + 2)
#define	TIM_EDGE_MASK(x)   (3 << ((x) * 3))
#define	TIM_CCR_CHANNEL_MASK(x)   (7 << ((x) * 3))
Timer Capture Registers
#define	TIM_CR_OFF(x)   (0x0000002C + ((x) * 4)
Timer External Match Register
#define	TIM_EMR_OFF   0x0000003C
#define	TIM_EM(x)   _BV(x)
#define	TIM_EM_NOTHING   0x0
#define	TIM_EM_LOW   0x1
#define	TIM_EM_HIGH   0x2
#define	TIM_EM_TOGGLE   0x3
#define	TIM_EM_SET(x, f)   ((f) << ((x) + 4))
#define	TIM_EM_MASK(x)   (3 << ((x) + 4))
Timer Count Control Register
#define	TIM_CTCR_OFF   0x00000070
#define	TIM_TIMER_MODE   0
#define	TIM_COUNTER_RISING_MODE   1
#define	TIM_COUNTER_FALLING_MODE   2
#define	TIM_COUNTER_ANY_MODE   3
#define	TIM_CTCR_MODE_LSB   0
#define	TIM_CTCR_MODE_MSK   0x3
#define	TIM_CTCR_INPUT_LSB   2
#define	TIM_CTCR_INPUT_MSK   0xC

---

Define Documentation

#define TIM_IR_OFF   0x00000000

#define TIM_IR_MR0   0x00000001

#define TIM_IR_MR1   0x00000002

#define TIM_IR_MR2   0x00000004

#define TIM_IR_MR3   0x00000008

#define TIM_IR_MR

(

x

)

_BV(x)

#define TIM_IR_CR0   0x00000010

#define TIM_IR_CR1   0x00000020

#define TIM_IR_CR

(

x

)

_BV((x) + 4)

#define TIM_TCR_OFF   0x00000004

#define TIM_TCR_ENA   0x00000001

#define TIM_ENABLE   TIM_TCR_ENA

#define TIM_TCR_RST   0x00000002

#define TIM_RESET   TIM_TCR_RST

#define TIM_TC_OFF   0x00000008

#define TIM_PR_OFF   0x0000000C

#define TIM_PC_OFF   0x00000010

#define TIM_MCR_OFF   0x00000014

#define TIM_MCR_MR0I   0x00000001

#define TIM_MCR_MR0R   0x00000002

#define TIM_MCR_MR0S   0x00000004

#define TIM_MCR_MR1I   0x00000008

#define TIM_MCR_MR1R   0x00000010

#define TIM_MCR_MR1S   0x00000020

#define TIM_MCR_MR2I   0x00000040

#define TIM_MCR_MR2R   0x00000080

#define TIM_MCR_MR2S   0x00000100

#define TIM_MCR_MR3I   0x00000200

#define TIM_MCR_MR3R   0x00000400

#define TIM_MCR_MR3S   0x00000800

#define TIM_INT_ON_MATCH

(

x

)

_BV((x) * 3)

#define TIM_RESET_ON_MATCH

(

x

)

_BV((x) * 3 + 1)

#define TIM_STOP_ON_MATCH

(

x

)

_BV((x) * 3 + 2)

#define TIM_MCR_CHANNEL_MASK

(

x

)

(7 << ((x) * 3))

#define TIM_MR_OFF

(

x

)

(0x00000018 + ((x) * 4))

#define TIM_CCR_OFF   0x00000028

#define TIM_CAP_RISING

(

x

)

_BV((x) * 3)

#define TIM_CAP_FALLING

(

x

)

_BV((x) * 3 + 1)

#define TIM_INT_ON_CAP

(

x

)

_BV((x) * 3 + 2)

#define TIM_EDGE_MASK

(

x

)

(3 << ((x) * 3))

#define TIM_CCR_CHANNEL_MASK

(

x

)

(7 << ((x) * 3))

#define TIM_CR_OFF

(

x

)

(0x0000002C + ((x) * 4)

#define TIM_EMR_OFF   0x0000003C

#define TIM_EM

(

x

)

_BV(x)

#define TIM_EM_NOTHING   0x0

#define TIM_EM_LOW   0x1

#define TIM_EM_HIGH   0x2

#define TIM_EM_TOGGLE   0x3

#define TIM_EM_SET	(		x,
			f
	)		((f) << ((x) + 4))

#define TIM_EM_MASK

(

x

)

(3 << ((x) + 4))

#define TIM_CTCR_OFF   0x00000070

#define TIM_TIMER_MODE   0

#define TIM_COUNTER_RISING_MODE   1

#define TIM_COUNTER_FALLING_MODE   2

#define TIM_COUNTER_ANY_MODE   3

#define TIM_CTCR_MODE_LSB   0

#define TIM_CTCR_MODE_MSK   0x3

#define TIM_CTCR_INPUT_LSB   2

#define TIM_CTCR_INPUT_MSK   0xC