Nut/OS  5.0.5
API Reference
Serial Peripheral Interface
AT91 Support

Serial peripheral interface registers. More...

Collaboration diagram for Serial Peripheral Interface:

SPI Control Register

#define SPI_CR_OFF   0x00000000
 Control register offset.
#define SPI_SPIEN   0x00000001
 SPI enable.
#define SPI_SPIDIS   0x00000002
 SPI disable.
#define SPI_SWRST   0x00000080
 Software reset.
#define SPI_LASTXFER   0x01000000
 Last transfer.

SPI Mode Register

#define SPI_MR_OFF   0x00000004
 Mode register offset.
#define SPI_MSTR   0x00000001
 Master mode.
#define SPI_PS   0x00000002
 Peripheral select.
#define SPI_PCSDEC   0x00000004
 Chip select decode.
#define SPI_FDIV   0x00000008
 Clock selection.
#define SPI_MODFDIS   0x00000010
 Mode fault detection.
#define SPI_LLB   0x00000080
 Local loopback enable.
#define SPI_PCS   0x000F0000
 Peripheral chip select mask.
#define SPI_PCS_0   0x000E0000
 Peripheral chip select 0.
#define SPI_PCS_1   0x000D0000
 Peripheral chip select 1.
#define SPI_PCS_2   0x000B0000
 Peripheral chip select 2.
#define SPI_PCS_3   0x00070000
 Peripheral chip select 3.
#define SPI_PCS_LSB   16
 Least significant bit of peripheral chip select.
#define SPI_DLYBCS   0xFF000000
 Mask for delay between chip selects.
#define SPI_DLYBCS_LSB   24
 Least significant bit of delay between chip selects.

SPI Receive Data Register

#define SPI_RDR_OFF   0x00000008
 Receive data register offset.
#define SPI_RD   0x0000FFFF
 Receive data mask.
#define SPI_RD_LSB   0
 Least significant bit of receive data.

SPI Transmit Data Register

#define SPI_TDR_OFF   0x0000000C
 Transmit data register offset.
#define SPI_TD   0x0000FFFF
 Transmit data mask.
#define SPI_TD_LSB   0
 Least significant bit of transmit data.

SPI Status and Interrupt Register

#define SPI_SR_OFF   0x00000010
 Status register offset.
#define SPI_IER_OFF   0x00000014
 Interrupt enable register offset.
#define SPI_IDR_OFF   0x00000018
 Interrupt disable register offset.
#define SPI_IMR_OFF   0x0000001C
 Interrupt mask register offset.
#define SPI_RDRF   0x00000001
 Receive data register full.
#define SPI_TDRE   0x00000002
 Transmit data register empty.
#define SPI_MODF   0x00000004
 Mode fault error.
#define SPI_OVRES   0x00000008
 Overrun error status.
#define SPI_ENDRX   0x00000010
 End of RX buffer.
#define SPI_ENDTX   0x00000020
 End of TX buffer.
#define SPI_RXBUFF   0x00000040
 RX buffer full.
#define SPI_TXBUFE   0x00000080
 TX buffer empty.
#define SPI_NSSR   0x00000100
 NSS rising.
#define SPI_TXEMPTY   0x00000200
 Transmission register empty.
#define SPI_SPIENS   0x00010000
 SPI enable status.

SPI Chip Select Registers

#define SPI_CSR0_OFF   0x00000030
 Chip select register 0 offset.
#define SPI_CSR1_OFF   0x00000034
 Chip select register 1 offset.
#define SPI_CSR2_OFF   0x00000038
 Chip select register 2 offset.
#define SPI_CSR3_OFF   0x0000003C
 Chip select register 3 offset.
#define SPI_CPOL   0x00000001
 Clock polarity.
#define SPI_NCPHA   0x00000002
 Clock phase.
#define SPI_CSAAT   0x00000008
 Chip select active after transfer.
#define SPI_BITS   0x000000F0
 Bits per transfer mask.
#define SPI_BITS_8   0x00000000
 8 bits per transfer.
#define SPI_BITS_9   0x00000010
 9 bits per transfer.
#define SPI_BITS_10   0x00000020
 10 bits per transfer.
#define SPI_BITS_11   0x00000030
 11 bits per transfer.
#define SPI_BITS_12   0x00000040
 12 bits per transfer.
#define SPI_BITS_13   0x00000050
 13 bits per transfer.
#define SPI_BITS_14   0x00000060
 14 bits per transfer.
#define SPI_BITS_15   0x00000070
 15 bits per transfer.
#define SPI_BITS_16   0x00000080
 16 bits per transfer.
#define SPI_BITS_LSB   4
 Least significant bit of bits per transfer.
#define SPI_SCBR   0x0000FF00
 Serial clock baud rate mask.
#define SPI_SCBR_LSB   8
 Least significant bit of serial clock baud rate.
#define SPI_DLYBS   0x00FF0000
 Delay before SPCK mask.
#define SPI_DLYBS_LSB   16
 Least significant bit of delay before SPCK.
#define SPI_DLYBCT   0xFF000000
 Delay between consecutive transfers mask.
#define SPI_DLYBCT_LSB   24
 Least significant bit of delay between consecutive transfers.

Detailed Description

Serial peripheral interface registers.

Define Documentation

#define SPI_CR_OFF   0x00000000

Control register offset.

Referenced by At91SpiDisable(), At91SpiEnable(), and At91SpiReset().

#define SPI_SPIEN   0x00000001

SPI enable.

Referenced by At91SpiBus0Select(), and At91SpiEnable().

#define SPI_SPIDIS   0x00000002

SPI disable.

Referenced by At91SpiDisable().

#define SPI_SWRST   0x00000080

Software reset.

Referenced by At91SpiReset().

#define SPI_LASTXFER   0x01000000

Last transfer.

#define SPI_MR_OFF   0x00000004

Mode register offset.

Referenced by At91SpiGetCsDelay(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetCsDelay(), At91SpiSetModeFlags(), and At91SpiTransfer2().

#define SPI_MSTR   0x00000001

Master mode.

Referenced by At91SpiBusNodeInit(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetModeFlags(), and FeederThread().

#define SPI_PS   0x00000002

Peripheral select.

#define SPI_PCSDEC   0x00000004

Chip select decode.

Referenced by At91SpiGetModeFlags(), and At91SpiSetModeFlags().

#define SPI_FDIV   0x00000008

Clock selection.

#define SPI_MODFDIS   0x00000010

Mode fault detection.

Referenced by At91SpiBusNodeInit(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetModeFlags(), At91SpiSetup(), and FeederThread().

#define SPI_LLB   0x00000080

Local loopback enable.

Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), and At91SpiSetup().

#define SPI_PCS   0x000F0000

Peripheral chip select mask.

Referenced by At91SpiReset(), and At91SpiTransfer2().

#define SPI_PCS_0   0x000E0000

Peripheral chip select 0.

Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().

#define SPI_PCS_1   0x000D0000

Peripheral chip select 1.

Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().

#define SPI_PCS_2   0x000B0000

Peripheral chip select 2.

Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().

#define SPI_PCS_3   0x00070000

Peripheral chip select 3.

Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().

#define SPI_PCS_LSB   16

Least significant bit of peripheral chip select.

#define SPI_DLYBCS   0xFF000000

Mask for delay between chip selects.

Referenced by At91SpiSetCsDelay().

#define SPI_DLYBCS_LSB   24

Least significant bit of delay between chip selects.

Referenced by At91SpiGetCsDelay(), At91SpiReset(), and At91SpiSetCsDelay().

#define SPI_RDR_OFF   0x00000008

Receive data register offset.

#define SPI_RD   0x0000FFFF

Receive data mask.

#define SPI_RD_LSB   0

Least significant bit of receive data.

#define SPI_TDR_OFF   0x0000000C

Transmit data register offset.

Referenced by At91SpiBus0Transfer().

#define SPI_TD   0x0000FFFF

Transmit data mask.

#define SPI_TD_LSB   0

Least significant bit of transmit data.

#define SPI_SR_OFF   0x00000010

Status register offset.

Referenced by At91SpiTransfer2().

#define SPI_IER_OFF   0x00000014

Interrupt enable register offset.

Referenced by At91SpiBus0Transfer(), and At91SpiTransfer2().

#define SPI_IDR_OFF   0x00000018

Interrupt disable register offset.

Referenced by At91SpiBus0Transfer(), At91SpiBusNodeInit(), and At91SpiTransfer2().

#define SPI_IMR_OFF   0x0000001C

Interrupt mask register offset.

#define SPI_RDRF   0x00000001

Receive data register full.

Referenced by At91SpiBus0Transfer().

#define SPI_TDRE   0x00000002

Transmit data register empty.

#define SPI_MODF   0x00000004

Mode fault error.

#define SPI_OVRES   0x00000008

Overrun error status.

#define SPI_ENDRX   0x00000010

End of RX buffer.

#define SPI_ENDTX   0x00000020

End of TX buffer.

#define SPI_RXBUFF   0x00000040

RX buffer full.

Referenced by At91SpiTransfer2().

#define SPI_TXBUFE   0x00000080

TX buffer empty.

#define SPI_NSSR   0x00000100

NSS rising.

#define SPI_TXEMPTY   0x00000200

Transmission register empty.

#define SPI_SPIENS   0x00010000

SPI enable status.

#define SPI_CSR0_OFF   0x00000030

Chip select register 0 offset.

Referenced by At91SpiGetBits(), At91SpiGetModeFlags(), At91SpiGetSckDelay(), At91SpiGetTxDelay(), At91SpiSetBits(), At91SpiSetModeFlags(), At91SpiSetRate(), At91SpiSetSckDelay(), and At91SpiSetTxDelay().

#define SPI_CSR1_OFF   0x00000034

Chip select register 1 offset.

Referenced by At91SpiSetRate().

#define SPI_CSR2_OFF   0x00000038

Chip select register 2 offset.

Referenced by At91SpiSetRate().

#define SPI_CSR3_OFF   0x0000003C

Chip select register 3 offset.

Referenced by At91SpiSetRate().

#define SPI_CPOL   0x00000001

Clock polarity.

Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), and At91SpiSetup().

#define SPI_NCPHA   0x00000002

Clock phase.

Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), At91SpiSetup(), and FeederThread().

#define SPI_CSAAT   0x00000008

Chip select active after transfer.

Referenced by At91SpiSetModeFlags(), and At91SpiSetup().

#define SPI_BITS   0x000000F0

Bits per transfer mask.

Referenced by At91SpiGetBits(), At91SpiSetBits(), and At91SpiSetup().

#define SPI_BITS_8   0x00000000

8 bits per transfer.

Referenced by At91SpiSetBits().

#define SPI_BITS_9   0x00000010

9 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_10   0x00000020

10 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_11   0x00000030

11 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_12   0x00000040

12 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_13   0x00000050

13 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_14   0x00000060

14 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_15   0x00000070

15 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_16   0x00000080

16 bits per transfer.

Referenced by At91SpiGetBits(), and At91SpiSetBits().

#define SPI_BITS_LSB   4

Least significant bit of bits per transfer.

Referenced by At91SpiSetup().

#define SPI_SCBR   0x0000FF00

Serial clock baud rate mask.

Referenced by At91SpiSetRate(), and At91SpiSetup().

#define SPI_SCBR_LSB   8

Least significant bit of serial clock baud rate.

Referenced by At91SpiSetRate(), At91SpiSetup(), and FeederThread().

#define SPI_DLYBS   0x00FF0000

Delay before SPCK mask.

Referenced by At91SpiSetSckDelay().

#define SPI_DLYBS_LSB   16

Least significant bit of delay before SPCK.

Referenced by At91SpiGetSckDelay(), and At91SpiSetSckDelay().

#define SPI_DLYBCT   0xFF000000

Delay between consecutive transfers mask.

Referenced by At91SpiSetTxDelay().

#define SPI_DLYBCT_LSB   24

Least significant bit of delay between consecutive transfers.

Referenced by At91SpiGetTxDelay(), and At91SpiSetTxDelay().