Nut/OS  5.0.5
API Reference
Functions | Variables
EMAC Module
AT91 Support

Ethernet MAC module registers. More...

Collaboration diagram for EMAC Module:

Functions

void EmacRxThread (void *arg)
 NIC receiver thread.
int EmacOutput (NUTDEVICE *dev, NETBUF *nb)
 Send Ethernet packet.
int EmacInit (NUTDEVICE *dev)
 Initialize Ethernet hardware.

Variables

NUTDEVICE devAt91Emac
 Device information structure.
NUTDEVICE devAvr32macb
 Device information structure.

Network Control Register

#define EMAC_NCR_OFF   0x00000000
 Network control register offset.
#define EMAC_NCR   (EMAC_BASE + EMAC_NCR_OFF)
 Network Control register address.
#define EMAC_LB   0x00000001
 PHY loopback.
#define EMAC_LLB   0x00000002
 EMAC loopback.
#define EMAC_RE   0x00000004
 Receive enable.
#define EMAC_TE   0x00000008
 Transmit enable.
#define EMAC_MPE   0x00000010
 Management port enable.
#define EMAC_CLRSTAT   0x00000020
 Clear statistics registers.
#define EMAC_INCSTAT   0x00000040
 Increment statistics registers.
#define EMAC_WESTAT   0x00000080
 Write enable for statistics registers.
#define EMAC_BP   0x00000100
 Back pressure.
#define EMAC_TSTART   0x00000200
 Start Transmission.
#define EMAC_THALT   0x00000400
 Transmission halt.
#define EMAC_TPFR   0x00000800
 Transmit pause frame.
#define EMAC_TZQ   0x00001000
 Transmit zero quantum pause frame.

Network Configuration Register

#define EMAC_NCFGR_OFF   0x00000004
 Network configuration register offset.
#define EMAC_NCFGR   (EMAC_BASE + EMAC_NCFGR_OFF)
 Network configuration register address.
#define EMAC_SPD   0x00000001
 Speed, set for 100Mb.
#define EMAC_FD   0x00000002
 Full duplex.
#define EMAC_JFRAME   0x00000008
 Jumbo Frames.
#define EMAC_CAF   0x00000010
 Copy all frames.
#define EMAC_NBC   0x00000020
 No broadcast.
#define EMAC_MTI   0x00000040
 Multicast hash event enable.
#define EMAC_UNI   0x00000080
 Unicast hash enable.
#define EMAC_BIG   0x00000100
 Receive 1522 bytes.
#define EMAC_EAE   0x00000200
 External address match enable.
#define EMAC_CLK   0x00000C00
 Clock divider mask.
#define EMAC_CLK_HCLK_8   0x00000000
 HCLK divided by 8.
#define EMAC_CLK_HCLK_16   0x00000400
 HCLK divided by 16.
#define EMAC_CLK_HCLK_32   0x00000800
 HCLK divided by 32.
#define EMAC_CLK_HCLK_64   0x00000C00
 HCLK divided by 64.
#define EMAC_RTY   0x00001000
 Retry test.
#define EMAC_PAE   0x00002000
 Pause enable.
#define EMAC_RBOF   0x0000C000
 Receive buffer offset.
#define EMAC_RBOF_OFFSET_0   0x00000000
 No offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_1   0x00004000
 One byte offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_2   0x00008000
 Two bytes offset from start of receive buffer.
#define EMAC_RBOF_OFFSET_3   0x0000C000
 Three bytes offset from start of receive buffer.
#define EMAC_RLCE   0x00010000
 Receive length field checking enable.
#define EMAC_DRFCS   0x00020000
 Discard receive FCS.
#define EMAC_EFRHD   0x00040000
 Allow receive during transmit in half duplex.
#define EMAC_IRXFCS   0x00080000
 Ignore received FCS.

Network Status Register

#define EMAC_NSR_OFF   0x00000008
 Network Status register offset.
#define EMAC_NSR   (EMAC_BASE + EMAC_NSR_OFF)
 Network Status register address.
#define EMAC_LINKR   0x00000001
 
#define EMAC_MDIO   0x00000002
 Status of MDIO input pin.
#define EMAC_IDLE   0x00000004
 Set when PHY is running.

Transmit Status Register

#define EMAC_TSR_OFF   0x00000014
 Transmit Status register offset.
#define EMAC_TSR   (EMAC_BASE + EMAC_TSR_OFF)
 Transmit Status register address.
#define EMAC_UBR   0x00000001
 Used bit read.
#define EMAC_COL   0x00000002
 Collision occurred.
#define EMAC_RLES   0x00000004
 Retry limit exceeded.
#define EMAC_TGO   0x00000008
 Transmit active.
#define EMAC_BEX   0x00000010
 Buffers exhausted mid frame.
#define EMAC_COMP   0x00000020
 Transmit complete.
#define EMAC_UND   0x00000040
 Transmit underrun.

Buffer Queue Pointer Register

#define EMAC_RBQP_OFF   0x00000018
 Receive buffer queue pointer.
#define EMAC_RBQP   (EMAC_BASE + EMAC_RBQP_OFF)
 Receive buffer queue pointer.
#define EMAC_TBQP_OFF   0x0000001C
 Transmit buffer queue pointer.
#define EMAC_TBQP   (EMAC_BASE + EMAC_TBQP_OFF)
 Transmit buffer queue pointer.

Receive Status Register

#define EMAC_RSR_OFF   0x00000020
 Receive status register offset.
#define EMAC_RSR   (EMAC_BASE + EMAC_RSR_OFF)
 Receive status register address.
#define EMAC_BNA   0x00000001
 Buffer not available.
#define EMAC_REC   0x00000002
 Frame received.
#define EMAC_OVR   0x00000004
 Receive overrun.

Interrupt Registers

#define EMAC_ISR_OFF   0x00000024
 Status register offset.
#define EMAC_ISR   (EMAC_BASE + EMAC_ISR_OFF)
 Status register address.
#define EMAC_IER_OFF   0x00000028
 Enable register offset.
#define EMAC_IER   (EMAC_BASE + EMAC_IER_OFF)
 Enable register address.
#define EMAC_IDR_OFF   0x0000002C
 Disable register offset.
#define EMAC_IDR   (EMAC_BASE + EMAC_IDR_OFF)
 Disable register address.
#define EMAC_IMR_OFF   0x00000030
 Mask register offset.
#define EMAC_IMR   (EMAC_BASE + EMAC_IMR_OFF)
 Mask register address.
#define EMAC_MFD   0x00000001
 Management frame done.
#define EMAC_RCOMP   0x00000002
 Receive complete.
#define EMAC_RXUBR   0x00000004
 Receive used bit read.
#define EMAC_TXUBR   0x00000008
 Transmit used bit read.
#define EMAC_TUND   0x00000010
 Ethernet transmit buffer underrun.
#define EMAC_RLEX   0x00000020
 Retry limit exceeded.
#define EMAC_TXERR   0x00000040
 Transmit error.
#define EMAC_TCOMP   0x00000080
 Transmit complete.
#define EMAC_LINK   0x00000200
 
#define EMAC_ROVR   0x00000400
 Receive overrun.
#define EMAC_HRESP   0x00000800
 DMA bus error.
#define EMAC_PFR   0x00001000
 Pause frame received.
#define EMAC_PTZ   0x00002000
 Pause time zero.

PHY Maintenance Register

#define EMAC_MAN_OFF   0x00000034
 PHY maintenance register offset.
#define EMAC_MAN   (EMAC_BASE + EMAC_MAN_OFF)
 PHY maintenance register address.
#define EMAC_DATA   0x0000FFFF
 PHY data mask.
#define EMAC_DATA_LSB   0
 PHY data LSB.
#define EMAC_CODE   0x00020000
 Fixed value.
#define EMAC_REGA   0x007C0000
 PHY register address mask.
#define EMAC_REGA_LSB   18
 PHY register address LSB.
#define EMAC_PHYA   0x0F800000
 PHY address mask.
#define EMAC_PHYA_LSB   23
 PHY address LSB.
#define EMAC_RW   0x30000000
 PHY read/write command mask.
#define EMAC_RW_READ   0x20000000
 PHY read command.
#define EMAC_RW_WRITE   0x10000000
 PHY write command.
#define EMAC_SOF   0x40000000
 Fixed value.

Pause Time Register

#define EMAC_PTR_OFF   0x00000038
 Pause time register offset.
#define EMAC_PTR   (EMAC_BASE + EMAC_PTR_OFF)
 Pause time register address.
#define EMAC_PTIME   0x0000FFFF
 Pause time mask.

Statistics Registers

#define EMAC_PFRR_OFF   0x0000003C
 Pause frames received register offset.
#define EMAC_PFRR   (EMAC_BASE + EMAC_PFRR_OFF)
 Pause frames received register address.
#define EMAC_FTO_OFF   0x00000040
 Frames transmitted OK register offset.
#define EMAC_FTO   (EMAC_BASE + EMAC_FTO_OFF)
 Frames transmitted OK register address.
#define EMAC_SCF_OFF   0x00000044
 Single collision frame register offset.
#define EMAC_SCF   (EMAC_BASE + EMAC_SCF_OFF)
 Single collision frame register address.
#define EMAC_MCF_OFF   0x00000048
 Multiple collision frame register offset.
#define EMAC_MCF   (EMAC_BASE + EMAC_MCF_OFF)
 Multiple collision frame register address.
#define EMAC_FRO_OFF   0x0000004C
 Frames received OK register offset.
#define EMAC_FRO   (EMAC_BASE + EMAC_FRO_OFF)
 Frames received OK register address.
#define EMAC_FCSE_OFF   0x00000050
 Frame check sequence error register offset.
#define EMAC_FCSE   (EMAC_BASE + EMAC_FCSE_OFF)
 Frame check sequence error register address.
#define EMAC_ALE_OFF   0x00000054
 Alignment error register offset.
#define EMAC_ALE   (EMAC_BASE + EMAC_ALE_OFF)
 Alignment error register address.
#define EMAC_DTF_OFF   0x00000058
 Deferred transmission frame register offset.
#define EMAC_DTF   (EMAC_BASE + EMAC_DTF_OFF)
 Deferred transmission frame register address.
#define EMAC_LCOL_OFF   0x0000005C
 Late collision register offset.
#define EMAC_LCOL   (EMAC_BASE + EMAC_LCOL_OFF)
 Late collision register address.
#define EMAC_ECOL_OFF   0x00000060
 Excessive collision register offset.
#define EMAC_ECOL   (EMAC_BASE + EMAC_ECOL_OFF)
 Excessive collision register address.
#define EMAC_TUNDR_OFF   0x00000064
 Transmit underrun error register offset.
#define EMAC_TUNDR   (EMAC_BASE + EMAC_TUNDR_OFF)
 Transmit underrun error register address.
#define EMAC_CSE_OFF   0x00000068
 Carrier sense error register offset.
#define EMAC_CSE   (EMAC_BASE + EMAC_CSE_OFF)
 Carrier sense error register address.
#define EMAC_RRE_OFF   0x0000006C
 Receive resource error register offset.
#define EMAC_RRE   (EMAC_BASE + EMAC_RRE_OFF)
 Receive resource error register address.
#define EMAC_ROV_OFF   0x00000070
 Receive overrun errors register offset.
#define EMAC_ROV   (EMAC_BASE + EMAC_ROV_OFF)
 Receive overrun errors register address.
#define EMAC_RSE_OFF   0x00000074
 Receive symbol errors register offset.
#define EMAC_RSE   (EMAC_BASE + EMAC_RSE_OFF)
 Receive symbol errors register address.
#define EMAC_ELE_OFF   0x00000078
 Excessive length errors register offset.
#define EMAC_ELE   (EMAC_BASE + EMAC_ELE_OFF)
 Excessive length errors register address.
#define EMAC_RJA_OFF   0x0000007C
 Receive jabbers register offset.
#define EMAC_RJA   (EMAC_BASE + EMAC_RJA_OFF)
 Receive jabbers register address.
#define EMAC_USF_OFF   0x00000080
 Undersize frames register offset.
#define EMAC_USF   (EMAC_BASE + EMAC_USF_OFF)
 Undersize frames register address.
#define EMAC_STE_OFF   0x00000084
 SQE test error register offset.
#define EMAC_STE   (EMAC_BASE + EMAC_STE_OFF)
 SQE test error register address.
#define EMAC_RLE_OFF   0x00000088
 Receive length field mismatch register offset.
#define EMAC_RLE   (EMAC_BASE + EMAC_RLE_OFF)
 Receive length field mismatch register address.
#define EMAC_TPF_OFF   0x0000008C
 Transmitted pause frames register offset.
#define EMAC_TPF   (EMAC_BASE + EMAC_TPF_OFF)
 Transmitted pause frames register address.

MAC Adressing Registers

#define EMAC_HRB_OFF   0x00000090
 Hash address bottom[31:0].
#define EMAC_HRB   (EMAC_BASE + EMAC_HRB_OFF)
 Hash address bottom[31:0].
#define EMAC_HRT_OFF   0x00000094
 Hash address top[63:32].
#define EMAC_HRT   (EMAC_BASE + EMAC_HRT_OFF)
 Hash address top[63:32].
#define EMAC_SA1L_OFF   0x00000098
 Specific address 1 bottom, first 4 bytes.
#define EMAC_SA1L   (EMAC_BASE + EMAC_SA1L_OFF)
 Specific address 1 bottom, first 4 bytes.
#define EMAC_SA1H_OFF   0x0000009C
 Specific address 1 top, last 2 bytes.
#define EMAC_SA1H   (EMAC_BASE + EMAC_SA1H_OFF)
 Specific address 1 top, last 2 bytes.
#define EMAC_SA2L_OFF   0x000000A0
 Specific address 2 bottom, first 4 bytes.
#define EMAC_SA2L   (EMAC_BASE + EMAC_SA2L_OFF)
 Specific address 2 bottom, first 4 bytes.
#define EMAC_SA2H_OFF   0x000000A4
 Specific address 2 top, last 2 bytes.
#define EMAC_SA2H   (EMAC_BASE + EMAC_SA2H_OFF)
 Specific address 2 top, last 2 bytes.
#define EMAC_SA3L_OFF   0x000000A8
 Specific address 3 bottom, first 4 bytes.
#define EMAC_SA3L   (EMAC_BASE + EMAC_SA3L_OFF)
 Specific address 3 bottom, first 4 bytes.
#define EMAC_SA3H_OFF   0x000000AC
 Specific address 3 top, last 2 bytes.
#define EMAC_SA3H   (EMAC_BASE + EMAC_SA3H_OFF)
 Specific address 3 top, last 2 bytes.
#define EMAC_SA4L_OFF   0x000000B0
 Specific address 4 bottom, first 4 bytes.
#define EMAC_SA4L   (EMAC_BASE + EMAC_SA4L_OFF)
 Specific address 4 bottom, first 4 bytes.
#define EMAC_SA4H_OFF   0x000000B4
 Specific address 4 top, last 2 bytes.
#define EMAC_SA4H   (EMAC_BASE + EMAC_SA4H_OFF)
 Specific address 4 top, last 2 bytes.

Type ID Register

#define EMAC_TID_OFF   0x000000B8
 Type ID checking register offset.
#define EMAC_TID   (EMAC_BASE + EMAC_TID_OFF)
 Type ID checking register address.
#define EMAC_TPQ_OFF   0x000000BC
 Transmit pause quantum register offset.
#define EMAC_TPQ   (EMAC_BASE + EMAC_TPQ_OFF)
 Transmit pause quantum register address.

User Input/Output Register

#define EMAC_USRIO_OFF   0x000000C0
 User input/output register offset.
#define EMAC_USRIO   (EMAC_BASE + EMAC_USRIO_OFF)
 User input/output register address.
#define EMAC_RMII   0x00000001
 Enable reduced MII.
#define EMAC_CLKEN   0x00000002
 Enable tranceiver input clock.

Wake On LAN Register

#define EMAC_WOL_OFF   0x000000C4
 Wake On LAN register offset.
#define EMAC_WOL   (EMAC_BASE + EMAC_WOL_OFF)
 Wake On LAN register address.
#define EMAC_IP   0x0000FFFF
 ARP request IP address mask.
#define EMAC_MAG   0x00010000
 Magic packet event enable.
#define EMAC_ARP   0x00020000
 ARP request event enable.
#define EMAC_SA1   0x00040000
 Specific address register 1 event enable.

Revision Register

#define EMAC_REV_OFF   0x000000FC
 Revision register offset.
#define EMAC_REV   (EMAC_BASE + EMAC_REV_OFF)
 Revision register address.
#define EMAC_REVREF   0x0000FFFF
 Revision.
#define EMAC_PARTREF   0xFFFF0000
 Part.

Detailed Description

Ethernet MAC module registers.

Define Documentation

#define EMAC_NCR_OFF   0x00000000

Network control register offset.

#define EMAC_NCR   (EMAC_BASE + EMAC_NCR_OFF)

Network Control register address.

#define EMAC_LB   0x00000001

PHY loopback.

#define EMAC_LLB   0x00000002

EMAC loopback.

#define EMAC_RE   0x00000004

Receive enable.

#define EMAC_TE   0x00000008

Transmit enable.

#define EMAC_MPE   0x00000010

Management port enable.

#define EMAC_CLRSTAT   0x00000020

Clear statistics registers.

#define EMAC_INCSTAT   0x00000040

Increment statistics registers.

#define EMAC_WESTAT   0x00000080

Write enable for statistics registers.

#define EMAC_BP   0x00000100

Back pressure.

#define EMAC_TSTART   0x00000200

Start Transmission.

#define EMAC_THALT   0x00000400

Transmission halt.

#define EMAC_TPFR   0x00000800

Transmit pause frame.

#define EMAC_TZQ   0x00001000

Transmit zero quantum pause frame.

#define EMAC_NCFGR_OFF   0x00000004

Network configuration register offset.

#define EMAC_NCFGR   (EMAC_BASE + EMAC_NCFGR_OFF)

Network configuration register address.

#define EMAC_SPD   0x00000001

Speed, set for 100Mb.

#define EMAC_FD   0x00000002

Full duplex.

#define EMAC_JFRAME   0x00000008

Jumbo Frames.

#define EMAC_CAF   0x00000010

Copy all frames.

#define EMAC_NBC   0x00000020

No broadcast.

#define EMAC_MTI   0x00000040

Multicast hash event enable.

#define EMAC_UNI   0x00000080

Unicast hash enable.

#define EMAC_BIG   0x00000100

Receive 1522 bytes.

#define EMAC_EAE   0x00000200

External address match enable.

#define EMAC_CLK   0x00000C00

Clock divider mask.

#define EMAC_CLK_HCLK_8   0x00000000

HCLK divided by 8.

#define EMAC_CLK_HCLK_16   0x00000400

HCLK divided by 16.

#define EMAC_CLK_HCLK_32   0x00000800

HCLK divided by 32.

#define EMAC_CLK_HCLK_64   0x00000C00

HCLK divided by 64.

#define EMAC_RTY   0x00001000

Retry test.

#define EMAC_PAE   0x00002000

Pause enable.

#define EMAC_RBOF   0x0000C000

Receive buffer offset.

#define EMAC_RBOF_OFFSET_0   0x00000000

No offset from start of receive buffer.

#define EMAC_RBOF_OFFSET_1   0x00004000

One byte offset from start of receive buffer.

#define EMAC_RBOF_OFFSET_2   0x00008000

Two bytes offset from start of receive buffer.

#define EMAC_RBOF_OFFSET_3   0x0000C000

Three bytes offset from start of receive buffer.

#define EMAC_RLCE   0x00010000

Receive length field checking enable.

#define EMAC_DRFCS   0x00020000

Discard receive FCS.

#define EMAC_EFRHD   0x00040000

Allow receive during transmit in half duplex.

#define EMAC_IRXFCS   0x00080000

Ignore received FCS.

#define EMAC_NSR_OFF   0x00000008

Network Status register offset.

#define EMAC_NSR   (EMAC_BASE + EMAC_NSR_OFF)

Network Status register address.

#define EMAC_LINKR   0x00000001

#define EMAC_MDIO   0x00000002

Status of MDIO input pin.

#define EMAC_IDLE   0x00000004

Set when PHY is running.

#define EMAC_TSR_OFF   0x00000014

Transmit Status register offset.

#define EMAC_TSR   (EMAC_BASE + EMAC_TSR_OFF)

Transmit Status register address.

Referenced by EmacOutput().

#define EMAC_UBR   0x00000001

Used bit read.

#define EMAC_COL   0x00000002

Collision occurred.

#define EMAC_RLES   0x00000004

Retry limit exceeded.

#define EMAC_TGO   0x00000008

Transmit active.

#define EMAC_BEX   0x00000010

Buffers exhausted mid frame.

#define EMAC_COMP   0x00000020

Transmit complete.

Referenced by EmacOutput().

#define EMAC_UND   0x00000040

Transmit underrun.

Referenced by EmacOutput().

#define EMAC_RBQP_OFF   0x00000018

Receive buffer queue pointer.

#define EMAC_RBQP   (EMAC_BASE + EMAC_RBQP_OFF)

Receive buffer queue pointer.

#define EMAC_TBQP_OFF   0x0000001C

Transmit buffer queue pointer.

#define EMAC_TBQP   (EMAC_BASE + EMAC_TBQP_OFF)

Transmit buffer queue pointer.

#define EMAC_RSR_OFF   0x00000020

Receive status register offset.

#define EMAC_RSR   (EMAC_BASE + EMAC_RSR_OFF)

Receive status register address.

#define EMAC_BNA   0x00000001

Buffer not available.

#define EMAC_REC   0x00000002

Frame received.

#define EMAC_OVR   0x00000004

Receive overrun.

#define EMAC_ISR_OFF   0x00000024

Status register offset.

#define EMAC_ISR   (EMAC_BASE + EMAC_ISR_OFF)

Status register address.

#define EMAC_IER_OFF   0x00000028

Enable register offset.

#define EMAC_IER   (EMAC_BASE + EMAC_IER_OFF)

Enable register address.

Referenced by EmacRxThread().

#define EMAC_IDR_OFF   0x0000002C

Disable register offset.

#define EMAC_IDR   (EMAC_BASE + EMAC_IDR_OFF)

Disable register address.

#define EMAC_IMR_OFF   0x00000030

Mask register offset.

#define EMAC_IMR   (EMAC_BASE + EMAC_IMR_OFF)

Mask register address.

#define EMAC_MFD   0x00000001

Management frame done.

#define EMAC_RCOMP   0x00000002

Receive complete.

Referenced by EmacRxThread().

#define EMAC_RXUBR   0x00000004

Receive used bit read.

Referenced by EmacRxThread().

#define EMAC_TXUBR   0x00000008

Transmit used bit read.

#define EMAC_TUND   0x00000010

Ethernet transmit buffer underrun.

Referenced by EmacRxThread().

#define EMAC_RLEX   0x00000020

Retry limit exceeded.

#define EMAC_TXERR   0x00000040

Transmit error.

#define EMAC_TCOMP   0x00000080

Transmit complete.

#define EMAC_LINK   0x00000200

#define EMAC_ROVR   0x00000400

Receive overrun.

Referenced by EmacRxThread().

#define EMAC_HRESP   0x00000800

DMA bus error.

#define EMAC_PFR   0x00001000

Pause frame received.

#define EMAC_PTZ   0x00002000

Pause time zero.

#define EMAC_MAN_OFF   0x00000034

PHY maintenance register offset.

#define EMAC_MAN   (EMAC_BASE + EMAC_MAN_OFF)

PHY maintenance register address.

#define EMAC_DATA   0x0000FFFF

PHY data mask.

#define EMAC_DATA_LSB   0

PHY data LSB.

#define EMAC_CODE   0x00020000

Fixed value.

#define EMAC_REGA   0x007C0000

PHY register address mask.

#define EMAC_REGA_LSB   18

PHY register address LSB.

#define EMAC_PHYA   0x0F800000

PHY address mask.

#define EMAC_PHYA_LSB   23

PHY address LSB.

#define EMAC_RW   0x30000000

PHY read/write command mask.

#define EMAC_RW_READ   0x20000000

PHY read command.

#define EMAC_RW_WRITE   0x10000000

PHY write command.

#define EMAC_SOF   0x40000000

Fixed value.

#define EMAC_PTR_OFF   0x00000038

Pause time register offset.

#define EMAC_PTR   (EMAC_BASE + EMAC_PTR_OFF)

Pause time register address.

#define EMAC_PTIME   0x0000FFFF

Pause time mask.

#define EMAC_PFRR_OFF   0x0000003C

Pause frames received register offset.

#define EMAC_PFRR   (EMAC_BASE + EMAC_PFRR_OFF)

Pause frames received register address.

#define EMAC_FTO_OFF   0x00000040

Frames transmitted OK register offset.

#define EMAC_FTO   (EMAC_BASE + EMAC_FTO_OFF)

Frames transmitted OK register address.

#define EMAC_SCF_OFF   0x00000044

Single collision frame register offset.

#define EMAC_SCF   (EMAC_BASE + EMAC_SCF_OFF)

Single collision frame register address.

#define EMAC_MCF_OFF   0x00000048

Multiple collision frame register offset.

#define EMAC_MCF   (EMAC_BASE + EMAC_MCF_OFF)

Multiple collision frame register address.

#define EMAC_FRO_OFF   0x0000004C

Frames received OK register offset.

#define EMAC_FRO   (EMAC_BASE + EMAC_FRO_OFF)

Frames received OK register address.

#define EMAC_FCSE_OFF   0x00000050

Frame check sequence error register offset.

#define EMAC_FCSE   (EMAC_BASE + EMAC_FCSE_OFF)

Frame check sequence error register address.

#define EMAC_ALE_OFF   0x00000054

Alignment error register offset.

#define EMAC_ALE   (EMAC_BASE + EMAC_ALE_OFF)

Alignment error register address.

#define EMAC_DTF_OFF   0x00000058

Deferred transmission frame register offset.

#define EMAC_DTF   (EMAC_BASE + EMAC_DTF_OFF)

Deferred transmission frame register address.

#define EMAC_LCOL_OFF   0x0000005C

Late collision register offset.

#define EMAC_LCOL   (EMAC_BASE + EMAC_LCOL_OFF)

Late collision register address.

#define EMAC_ECOL_OFF   0x00000060

Excessive collision register offset.

#define EMAC_ECOL   (EMAC_BASE + EMAC_ECOL_OFF)

Excessive collision register address.

#define EMAC_TUNDR_OFF   0x00000064

Transmit underrun error register offset.

#define EMAC_TUNDR   (EMAC_BASE + EMAC_TUNDR_OFF)

Transmit underrun error register address.

#define EMAC_CSE_OFF   0x00000068

Carrier sense error register offset.

#define EMAC_CSE   (EMAC_BASE + EMAC_CSE_OFF)

Carrier sense error register address.

#define EMAC_RRE_OFF   0x0000006C

Receive resource error register offset.

#define EMAC_RRE   (EMAC_BASE + EMAC_RRE_OFF)

Receive resource error register address.

#define EMAC_ROV_OFF   0x00000070

Receive overrun errors register offset.

#define EMAC_ROV   (EMAC_BASE + EMAC_ROV_OFF)

Receive overrun errors register address.

#define EMAC_RSE_OFF   0x00000074

Receive symbol errors register offset.

#define EMAC_RSE   (EMAC_BASE + EMAC_RSE_OFF)

Receive symbol errors register address.

#define EMAC_ELE_OFF   0x00000078

Excessive length errors register offset.

#define EMAC_ELE   (EMAC_BASE + EMAC_ELE_OFF)

Excessive length errors register address.

#define EMAC_RJA_OFF   0x0000007C

Receive jabbers register offset.

#define EMAC_RJA   (EMAC_BASE + EMAC_RJA_OFF)

Receive jabbers register address.

#define EMAC_USF_OFF   0x00000080

Undersize frames register offset.

#define EMAC_USF   (EMAC_BASE + EMAC_USF_OFF)

Undersize frames register address.

#define EMAC_STE_OFF   0x00000084

SQE test error register offset.

#define EMAC_STE   (EMAC_BASE + EMAC_STE_OFF)

SQE test error register address.

#define EMAC_RLE_OFF   0x00000088

Receive length field mismatch register offset.

#define EMAC_RLE   (EMAC_BASE + EMAC_RLE_OFF)

Receive length field mismatch register address.

#define EMAC_TPF_OFF   0x0000008C

Transmitted pause frames register offset.

#define EMAC_TPF   (EMAC_BASE + EMAC_TPF_OFF)

Transmitted pause frames register address.

#define EMAC_HRB_OFF   0x00000090

Hash address bottom[31:0].

#define EMAC_HRB   (EMAC_BASE + EMAC_HRB_OFF)

Hash address bottom[31:0].

#define EMAC_HRT_OFF   0x00000094

Hash address top[63:32].

#define EMAC_HRT   (EMAC_BASE + EMAC_HRT_OFF)

Hash address top[63:32].

#define EMAC_SA1L_OFF   0x00000098

Specific address 1 bottom, first 4 bytes.

#define EMAC_SA1L   (EMAC_BASE + EMAC_SA1L_OFF)

Specific address 1 bottom, first 4 bytes.

#define EMAC_SA1H_OFF   0x0000009C

Specific address 1 top, last 2 bytes.

#define EMAC_SA1H   (EMAC_BASE + EMAC_SA1H_OFF)

Specific address 1 top, last 2 bytes.

#define EMAC_SA2L_OFF   0x000000A0

Specific address 2 bottom, first 4 bytes.

#define EMAC_SA2L   (EMAC_BASE + EMAC_SA2L_OFF)

Specific address 2 bottom, first 4 bytes.

#define EMAC_SA2H_OFF   0x000000A4

Specific address 2 top, last 2 bytes.

#define EMAC_SA2H   (EMAC_BASE + EMAC_SA2H_OFF)

Specific address 2 top, last 2 bytes.

#define EMAC_SA3L_OFF   0x000000A8

Specific address 3 bottom, first 4 bytes.

#define EMAC_SA3L   (EMAC_BASE + EMAC_SA3L_OFF)

Specific address 3 bottom, first 4 bytes.

#define EMAC_SA3H_OFF   0x000000AC

Specific address 3 top, last 2 bytes.

#define EMAC_SA3H   (EMAC_BASE + EMAC_SA3H_OFF)

Specific address 3 top, last 2 bytes.

#define EMAC_SA4L_OFF   0x000000B0

Specific address 4 bottom, first 4 bytes.

#define EMAC_SA4L   (EMAC_BASE + EMAC_SA4L_OFF)

Specific address 4 bottom, first 4 bytes.

#define EMAC_SA4H_OFF   0x000000B4

Specific address 4 top, last 2 bytes.

#define EMAC_SA4H   (EMAC_BASE + EMAC_SA4H_OFF)

Specific address 4 top, last 2 bytes.

#define EMAC_TID_OFF   0x000000B8

Type ID checking register offset.

#define EMAC_TID   (EMAC_BASE + EMAC_TID_OFF)

Type ID checking register address.

#define EMAC_TPQ_OFF   0x000000BC

Transmit pause quantum register offset.

#define EMAC_TPQ   (EMAC_BASE + EMAC_TPQ_OFF)

Transmit pause quantum register address.

#define EMAC_USRIO_OFF   0x000000C0

User input/output register offset.

#define EMAC_USRIO   (EMAC_BASE + EMAC_USRIO_OFF)

User input/output register address.

#define EMAC_RMII   0x00000001

Enable reduced MII.

#define EMAC_CLKEN   0x00000002

Enable tranceiver input clock.

#define EMAC_WOL_OFF   0x000000C4

Wake On LAN register offset.

#define EMAC_WOL   (EMAC_BASE + EMAC_WOL_OFF)

Wake On LAN register address.

#define EMAC_IP   0x0000FFFF

ARP request IP address mask.

#define EMAC_MAG   0x00010000

Magic packet event enable.

#define EMAC_ARP   0x00020000

ARP request event enable.

#define EMAC_SA1   0x00040000

Specific address register 1 event enable.

#define EMAC_REV_OFF   0x000000FC

Revision register offset.

#define EMAC_REV   (EMAC_BASE + EMAC_REV_OFF)

Revision register address.

#define EMAC_REVREF   0x0000FFFF

Revision.

#define EMAC_PARTREF   0xFFFF0000

Part.

Function Documentation

EmacRxThread ( void *  arg)

NIC receiver thread.

References _NUTDEVICE::dev_dcb, _NUTDEVICE::dev_icb, EMAC_IER, EMAC_LINK_LOOPS, EMAC_RCOMP, EMAC_ROVR, EMAC_RXUBR, EMAC_TUND, EMPRINTF, ETHER_IS_UNICAST, ifnet::if_mac, ifnet::if_recv, _NETBUF::nb_dl, _EMACINFO::ni_insane, _EMACINFO::ni_mutex, _EMACINFO::ni_rx_rdy, _EMACINFO::ni_tx_quelen, _EMACINFO::ni_tx_queued, NutEventPost(), NutEventWait(), NutIrqEnable(), NutNetBufFree(), NutSleep(), NutThreadSetPriority(), outr, sig_EMAC, and _NBDATA::sz.

Referenced by EmacInit().

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int EmacOutput ( NUTDEVICE *  dev,
NETBUF *  nb 
)

Send Ethernet packet.

Parameters:
devIdentifies the device to use.
nbNetwork buffer structure containing the packet to be sent. The structure must have been allocated by a previous call NutNetBufAlloc().
Returns:
0 on success, -1 in case of any errors.

References _NUTDEVICE::dev_dcb, EMAC_COMP, EMAC_TSR, EMAC_UND, inr, _EMACINFO::ni_insane, _EMACINFO::ni_mutex, _EMACINFO::ni_tx_rdy, NutEventPost(), NutEventWait(), outr, rc, _BufDescriptor::stat, and TXS_USED.

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int EmacInit ( NUTDEVICE *  dev)

Initialize Ethernet hardware.

Applications should do not directly call this function. It is automatically executed during during device registration by NutRegisterDevice().

Parameters:
devIdentifies the device to initialize.

References _NUTDEVICE::dev_dcb, EMAC_LINK_LOOPS, EmacRxThread(), EMPRINTF, memset(), NULL, NUT_THREAD_NICRXSTACK, NUT_THREAD_STACK_ADD, NUT_THREAD_STACK_MULT, NutRegisterIrqHandler(), NutThreadCreate(), and sig_EMAC.

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Variable Documentation

NUTDEVICE devAt91Emac
Initial value:
 {
    0,                          
    {'e', 't', 'h', '0', 0, 0, 0, 0, 0},        
    IFTYP_NET,                  
    0,                          
    0,                          
    &ifn_eth0,                  
    &dcb_eth0,                  
    EmacInit,                   
    0,                          
    0,                          
    0,                          

    0,                          

    0,                          
    0,                          
    0                           
}

Device information structure.

A pointer to this structure must be passed to NutRegisterDevice() to bind this Ethernet device driver to the Nut/OS kernel. An application may then call NutNetIfConfig() with the name eth0 of this driver to initialize the network interface.

NUTDEVICE devAvr32macb
Initial value:
 {
    0,                          
    {'e', 't', 'h', '0', 0, 0, 0, 0, 0},        
    IFTYP_NET,                  
    AVR32_MACB_ADDRESS,         
    0,                          
    &ifn_eth0,                  
    &dcb_eth0,                  
    EmacInit,                   
    0,                          
    0,                          
    0,                          

    0,                          

    0,                          
    0,                          
    0                           
}

Device information structure.

A pointer to this structure must be passed to NutRegisterDevice() to bind this Ethernet device driver to the Nut/OS kernel. An application may then call NutNetIfConfig() with the name eth0 of this driver to initialize the network interface.