Routines for using the Ethernut CPLD. More...
Defines | |
#define | NPL_BASE 0xFF00 |
CPLD register base address. | |
#define | NPL_RSCR _SFR_MEM8(NPL_BASE + 0x00) |
RS232 command register. | |
#define | NPL_RSFON_BIT 0 |
Force on bit. | |
#define | NPL_RSFON (1 << NPL_RSFON_BIT) |
Force on mask. | |
#define | NPL_RSFOFF_BIT 1 |
Force off bit. | |
#define | NPL_RSFOFF (1 << NPL_RSFOFF_BIT) |
Force off mask. | |
#define | NPL_RSDTR_BIT 2 |
DTR handshake bit. | |
#define | NPL_RSDTR (1 << NPL_RSDTR_BIT) |
DTR handshake mask. | |
#define | NPL_RSRTS_BIT 3 |
RTS handshake bit. | |
#define | NPL_RSRTS (1 << NPL_RSRTS_BIT) |
RTS handshake mask. | |
#define | NPL_RSUS0E_BIT 5 |
USART0 select bit. | |
#define | NPL_RSUS0E (1 << NPL_RSUS0E_BIT) |
USART0 select mask. | |
#define | NPL_RSUS1E_BIT 6 |
USART1 select bit. | |
#define | NPL_RSUS1E (1 << NPL_RSUS1E_BIT) |
USART1 select mask. | |
#define | NPL_RSUS1P_BIT 7 |
USART1 primary bit. | |
#define | NPL_RSUS1P (1 << NPL_RSUS1P_BIT) |
USART1 primary mask. | |
#define | NPL_IMR _SFR_MEM16(NPL_BASE + 0x04) |
Interrupt mask register. | |
#define | NPL_SPICTRL _SFR_MEM8(NPL_BASE + 0x08) |
SPI clock divider register. | |
#define | NPL_SLR _SFR_MEM16(NPL_BASE + 0x0C) |
Signal latch register. | |
#define | NPL_SCR _SFR_MEM16(NPL_BASE + 0x10) |
Signal clear register. | |
#define | NPL_STATUS _SFR_MEM16(NPL_BASE + 0x10) |
Status register. | |
#define | NPL_RSCTS_BIT 0 |
RS232 CTS interrupt bit. | |
#define | NPL_RSCTS (1 << NPL_RSCTS_BIT) |
RS232 CTS interrupt mask. | |
#define | NPL_RSDSR_BIT 1 |
RS232 DSR interrupt bit. | |
#define | NPL_RSDSR (1 << NPL_RSDSR_BIT) |
RS232 DSR interrupt mask. | |
#define | NPL_RSDCD_BIT 2 |
RS232 DCD interrupt bit. | |
#define | NPL_RSDCD (1 << NPL_RSDCD_BIT) |
RS232 DCD interrupt mask. | |
#define | NPL_RSRI_BIT 3 |
RS232 RI interrupt bit. | |
#define | NPL_RSRI (1 << NPL_RSRI_BIT) |
RS232 RI interrupt mask. | |
#define | NPL_RTCALARM_BIT 4 |
RTC alarm interrupt bit. | |
#define | NPL_RTCALARM (1 << NPL_RTCALARM_BIT) |
RTC alarm interrupt mask. | |
#define | NPL_LANWAKEUP_BIT 5 |
NIC wakeup interrupt bit. | |
#define | NPL_LANWAKEUP (1 << NPL_LANWAKEUP_BIT) |
NIC wakeup interrupt mask. | |
#define | NPL_FMBUSY_BIT 6 |
FLASH ready interrupt bit. | |
#define | NPL_FMBUSY (1 << NPL_FMBUSY_BIT) |
FLASH ready interrupt mask. | |
#define | NPL_MMCREADY_BIT 7 |
MMC shift register ready bit. | |
#define | NPL_MMCREADY (1 << NPL_MMCREADY_BIT) |
MMC shift register ready mask. | |
#define | NPL_RSINVAL_BIT 8 |
RS232 invalid interrupt bit. | |
#define | NPL_RSINVAL (1 << NPL_RSINVAL_BIT) |
RS232 invalid interrupt mask. | |
#define | NPL_NRSINVAL_BIT 9 |
RS232 valid interrupt bit. | |
#define | NPL_NRSINVAL (1 << NPL_NRSINVAL_BIT) |
RS232 valid interrupt mask. | |
#define | NPL_MMCD_BIT 10 |
MMC insert interrupt bit. | |
#define | NPL_MMCD (1 << NPL_MMCD_BIT) |
MMC insert interrupt mask. | |
#define | NPL_NMMCD_BIT 11 |
MMC remove interrupt bit. | |
#define | NPL_NMMCD (1 << NPL_NMMCD_BIT) |
MMC remove interrupt mask. | |
#define | NPL_MMCDR _SFR_MEM8(NPL_BASE + 0x14) |
MMC data register. | |
#define | NPL_XER _SFR_MEM8(NPL_BASE + 0x18) |
External enable register. | |
#define | NPL_MMCS 0x0001 |
MMC select. | |
#define | NPL_PANCS 0x0002 |
Panel select. | |
#define | NPL_USRLED 0x0004 |
User LED. | |
#define | NPL_NPCS0 0x0008 |
DataFlash CS. | |
#define | NPL_VIDR _SFR_MEM8(NPL_BASE + 0x1C) |
Version identifier register. | |
#define | ULED_ON 1 |
ULED status definitions. | |
#define | ULED_OFF 0 |
Functions | |
int | NplRegisterIrqHandler (IRQ_HANDLER *irq, void(*handler)(void *), void *arg) |
Register an NPL interrupt handler. | |
int | NplIrqEnable (IRQ_HANDLER *irq) |
Enable a specified NPL interrupt. | |
int | NplIrqDisable (IRQ_HANDLER *irq) |
Disable a specified NPL interrupt. | |
void | NplUledCntl (int status) |
Low Level User LED (Green) Access. | |
int | NplUledStatus (void) |
User LED status routine. | |
Variables | |
IRQ_HANDLER | sig_RSCTS |
RS232 CTS interrupt handler info. | |
IRQ_HANDLER | sig_RSDSR |
RS232 DSR interrupt handler info. | |
IRQ_HANDLER | sig_RSDCD |
RS232 DCD interrupt handler info. | |
IRQ_HANDLER | sig_RSRI |
RS232 RI interrupt handler info. | |
IRQ_HANDLER | sig_RTCALARM |
RTC alarm interrupt handler info. | |
IRQ_HANDLER | sig_LANWAKEUP |
LAN wakeup interrupt handler info. | |
IRQ_HANDLER | sig_FMBUSY |
Flash memory busy interrupt handler info. | |
IRQ_HANDLER | sig_MMCREADY |
IRQ_HANDLER | sig_RSINVAL |
RS232 signal invalid interrupt handler info. | |
IRQ_HANDLER | sig_NRSINVAL |
RS232 signal valid interrupt handler info. | |
IRQ_HANDLER | sig_MMCD |
Multimedia card insertion interrupt handler info. | |
IRQ_HANDLER | sig_NMMCD |
Multimedia card removal interrupt handler info. | |
IRQ_HANDLER | sig_RSCTS |
RS232 CTS interrupt handler info. | |
IRQ_HANDLER | sig_RSDSR |
RS232 DSR interrupt handler info. | |
IRQ_HANDLER | sig_RSDCD |
RS232 DCD interrupt handler info. | |
IRQ_HANDLER | sig_RSRI |
RS232 RI interrupt handler info. | |
IRQ_HANDLER | sig_RTCALARM |
RTC alarm interrupt handler info. | |
IRQ_HANDLER | sig_LANWAKEUP |
LAN wakeup interrupt handler info. | |
IRQ_HANDLER | sig_FMBUSY |
Flash memory busy interrupt handler info. | |
IRQ_HANDLER | sig_RSINVAL |
RS232 signal invalid interrupt handler info. | |
IRQ_HANDLER | sig_NRSINVAL |
RS232 signal valid interrupt handler info. | |
IRQ_HANDLER | sig_MMCD |
Multimedia card insertion interrupt handler info. | |
IRQ_HANDLER | sig_NMMCD |
Multimedia card removal interrupt handler info. |
Routines for using the Ethernut CPLD.
Nut Programmable Logic.
The CPLD on Ethernut 3 contains a set of registers, which can be used to control various system functions.
* * $Log$ * Revision 1.4 2009/01/17 11:26:46 haraldkipp * Getting rid of two remaining BSD types in favor of stdint. * Replaced 'u_int' by 'unsinged int' and 'uptr_t' by 'uintptr_t'. * * Revision 1.3 2008/08/11 06:59:42 haraldkipp * BSD types replaced by stdint types (feature request #1282721). * * Revision 1.2 2006/05/25 09:30:23 haraldkipp * Compiles for AVR. Still not tested, though. * * Revision 1.1 2006/01/05 16:30:57 haraldkipp * First check-in. * * *
#define NPL_BASE 0xFF00 |
CPLD register base address.
On Ethernut 3 the CPLD is selected via NCS2 (GPIO 27), which is configured to 0x21000000 - 0x210FFFFF in the CRT initialization startup file.
#define NPL_RSCR _SFR_MEM8(NPL_BASE + 0x00) |
RS232 command register.
#define NPL_RSFON_BIT 0 |
Force on bit.
#define NPL_RSFON (1 << NPL_RSFON_BIT) |
Force on mask.
#define NPL_RSFOFF_BIT 1 |
Force off bit.
#define NPL_RSFOFF (1 << NPL_RSFOFF_BIT) |
Force off mask.
#define NPL_RSDTR_BIT 2 |
DTR handshake bit.
#define NPL_RSDTR (1 << NPL_RSDTR_BIT) |
DTR handshake mask.
#define NPL_RSRTS_BIT 3 |
RTS handshake bit.
#define NPL_RSRTS (1 << NPL_RSRTS_BIT) |
RTS handshake mask.
#define NPL_RSUS0E_BIT 5 |
USART0 select bit.
#define NPL_RSUS0E (1 << NPL_RSUS0E_BIT) |
USART0 select mask.
#define NPL_RSUS1E_BIT 6 |
USART1 select bit.
#define NPL_RSUS1E (1 << NPL_RSUS1E_BIT) |
USART1 select mask.
#define NPL_RSUS1P_BIT 7 |
USART1 primary bit.
#define NPL_RSUS1P (1 << NPL_RSUS1P_BIT) |
USART1 primary mask.
#define NPL_IMR _SFR_MEM16(NPL_BASE + 0x04) |
Interrupt mask register.
#define NPL_SPICTRL _SFR_MEM8(NPL_BASE + 0x08) |
SPI clock divider register.
#define NPL_SLR _SFR_MEM16(NPL_BASE + 0x0C) |
Signal latch register.
Referenced by NplSpiBusPollTransfer().
#define NPL_SCR _SFR_MEM16(NPL_BASE + 0x10) |
Signal clear register.
#define NPL_STATUS _SFR_MEM16(NPL_BASE + 0x10) |
Status register.
#define NPL_RSCTS_BIT 0 |
RS232 CTS interrupt bit.
#define NPL_RSCTS (1 << NPL_RSCTS_BIT) |
RS232 CTS interrupt mask.
#define NPL_RSDSR_BIT 1 |
RS232 DSR interrupt bit.
#define NPL_RSDSR (1 << NPL_RSDSR_BIT) |
RS232 DSR interrupt mask.
#define NPL_RSDCD_BIT 2 |
RS232 DCD interrupt bit.
#define NPL_RSDCD (1 << NPL_RSDCD_BIT) |
RS232 DCD interrupt mask.
#define NPL_RSRI_BIT 3 |
RS232 RI interrupt bit.
#define NPL_RSRI (1 << NPL_RSRI_BIT) |
RS232 RI interrupt mask.
#define NPL_RTCALARM_BIT 4 |
RTC alarm interrupt bit.
#define NPL_RTCALARM (1 << NPL_RTCALARM_BIT) |
RTC alarm interrupt mask.
#define NPL_LANWAKEUP_BIT 5 |
NIC wakeup interrupt bit.
#define NPL_LANWAKEUP (1 << NPL_LANWAKEUP_BIT) |
NIC wakeup interrupt mask.
#define NPL_FMBUSY_BIT 6 |
FLASH ready interrupt bit.
#define NPL_FMBUSY (1 << NPL_FMBUSY_BIT) |
FLASH ready interrupt mask.
#define NPL_MMCREADY_BIT 7 |
MMC shift register ready bit.
#define NPL_MMCREADY (1 << NPL_MMCREADY_BIT) |
MMC shift register ready mask.
Referenced by NplSpiBusPollTransfer().
#define NPL_RSINVAL_BIT 8 |
RS232 invalid interrupt bit.
#define NPL_RSINVAL (1 << NPL_RSINVAL_BIT) |
RS232 invalid interrupt mask.
#define NPL_NRSINVAL_BIT 9 |
RS232 valid interrupt bit.
#define NPL_NRSINVAL (1 << NPL_NRSINVAL_BIT) |
RS232 valid interrupt mask.
#define NPL_MMCD_BIT 10 |
MMC insert interrupt bit.
#define NPL_MMCD (1 << NPL_MMCD_BIT) |
MMC insert interrupt mask.
#define NPL_NMMCD_BIT 11 |
MMC remove interrupt bit.
#define NPL_NMMCD (1 << NPL_NMMCD_BIT) |
MMC remove interrupt mask.
#define NPL_MMCDR _SFR_MEM8(NPL_BASE + 0x14) |
MMC data register.
Referenced by NplSpiBusPollTransfer().
#define NPL_XER _SFR_MEM8(NPL_BASE + 0x18) |
External enable register.
Referenced by NplUledCntl(), and NplUledStatus().
#define NPL_MMCS 0x0001 |
MMC select.
#define NPL_PANCS 0x0002 |
Panel select.
#define NPL_USRLED 0x0004 |
User LED.
Referenced by NplUledCntl(), and NplUledStatus().
#define NPL_NPCS0 0x0008 |
DataFlash CS.
#define NPL_VIDR _SFR_MEM8(NPL_BASE + 0x1C) |
Version identifier register.
#define ULED_ON 1 |
ULED status definitions.
Referenced by NplUledCntl().
#define ULED_OFF 0 |
Referenced by NplUledCntl().
int NplRegisterIrqHandler | ( | IRQ_HANDLER * | irq, |
void(*)(void *) | handler, | ||
void * | arg | ||
) |
Register an NPL interrupt handler.
This function is typically called by device drivers, but applications may also implement their local interrupt handlers.
irq | Interrupt to be associated with this handler. |
handler | This routine will be called by Nut/OS, when the specified interrupt occurs. |
arg | Argument to be passed to the interrupt handler. |
References _BV, IRQ_HANDLER::ir_arg, IRQ_HANDLER::ir_ctl, IRQ_HANDLER::ir_handler, NULL, NUT_IRQCTL_INIT, NUT_IRQMODE_LOWLEVEL, NutIrqEnable(), NutIrqSetMode(), NutRegisterIrqHandler(), outr, rc, and sig_INTERRUPT0.
int NplIrqEnable | ( | IRQ_HANDLER * | irq | ) |
Enable a specified NPL interrupt.
irq | Interrupt to enable. |
References IRQ_HANDLER::ir_ctl, NULL, and NUT_IRQCTL_ENABLE.
int NplIrqDisable | ( | IRQ_HANDLER * | irq | ) |
Disable a specified NPL interrupt.
irq | Interrupt to disable. |
References IRQ_HANDLER::ir_ctl, NULL, and NUT_IRQCTL_DISABLE.
void NplUledCntl | ( | int | status | ) |
Low Level User LED (Green) Access.
Low level User LED (Green) hardware routines for the programmable logic provided on the Ethernut 3 reference design.
** * Revision 1.0 2006/01/22 10:01:02 alex (k.vassliev) * First check-in. * * *
User LED control routine.
status | ULED_ON of ULED_OFF |
Activate negated chip select.
Deactivate negated chip select.
References inb, NPL_USRLED, NPL_XER, outb, ULED_OFF, and ULED_ON.
int NplUledStatus | ( | void | ) |
User LED status routine.
References inb, NPL_USRLED, NPL_XER, and rc.
RS232 CTS interrupt handler info.
RS232 DSR interrupt handler info.
RS232 DCD interrupt handler info.
RS232 RI interrupt handler info.
RTC alarm interrupt handler info.
LAN wakeup interrupt handler info.
Flash memory busy interrupt handler info.
RS232 signal invalid interrupt handler info.
RS232 signal valid interrupt handler info.
Multimedia card insertion interrupt handler info.
Multimedia card removal interrupt handler info.