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Defines | |
#define | EMAC_MAC1_MASK 0xcf1f |
#define | EMAC_MAC1_REC_EN 0x00000001 |
#define | EMAC_MAC1_PASS_ALL 0x00000002 |
#define | EMAC_MAC1_RX_FLOWC 0x00000004 |
#define | EMAC_MAC1_TX_FLOWC 0x00000008 |
#define | EMAC_MAC1_LOOPB 0x00000010 |
#define | EMAC_MAC1_RES_TX 0x00000100 |
#define | EMAC_MAC1_RES_MCS_TX 0x00000200 |
#define | EMAC_MAC1_RES_RX 0x00000400 |
#define | EMAC_MAC1_RES_MCS_RX 0x00000800 |
#define | EMAC_MAC1_SIM_RES 0x00004000 |
#define | EMAC_MAC1_SOFT_RES 0x00008000 |
#define | EMAC_MAC2_MASK 0x73ff |
#define | EMAC_MAC2_FULL_DUP 0x00000001 |
#define | EMAC_MAC2_FRM_LEN_CHK 0x00000002 |
#define | EMAC_MAC2_HUGE_FRM_EN 0x00000004 |
#define | EMAC_MAC2_DLY_CRC 0x00000008 |
#define | EMAC_MAC2_CRC_EN 0x00000010 |
#define | EMAC_MAC2_PAD_EN 0x00000020 |
#define | EMAC_MAC2_VLAN_PAD_EN 0x00000040 |
#define | EMAC_MAC2_ADET_PAD_EN 0x00000080 |
#define | EMAC_MAC2_PPREAM_ENF 0x00000100 |
#define | EMAC_MAC2_LPREAM_ENF 0x00000200 |
#define | EMAC_MAC2_NO_BACKOFF 0x00001000 |
#define | EMAC_MAC2_BACK_PRESSURE 0x00002000 |
#define | EMAC_MAC2_EXCESS_DEF 0x00004000 |
#define | EMAC_IPGT_BBIPG(n) (n&0x7F) |
#define | EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) |
#define | EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) |
#define | EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) |
#define | EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) |
#define | EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) |
#define | EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) |
#define | EMAC_CLRT_MAX_RETX(n) (n&0x0F) |
#define | EMAC_CLRT_COLL(n) ((n&0x3F)<<8) |
#define | EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) |
#define | EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) |
#define | EMAC_MAXF_MAXFRMLEN_DEF (0x6000) |
#define | EMAC_SUPP_SPEED 0x00000100 |
#define | EMAC_SUPP_RES_RMII 0x00000800 |
#define | EMAC_TEST_SHCUT_PQUANTA 0x00000001 |
#define | EMAC_TEST_TST_PAUSE 0x00000002 |
#define | EMAC_TEST_TST_BACKP 0x00000004 |
#define | EMAC_MCFG_SCAN_INC 0x00000001 |
#define | EMAC_MCFG_SUPP_PREAM 0x00000002 |
#define | EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) |
#define | EMAC_MCFG_RES_MII 0x00008000 |
#define | EMAC_MCFG_MII_MAXCLK 2500000UL |
#define | EMAC_MCMD_READ 0x00000001 |
#define | EMAC_MCMD_SCAN 0x00000002 |
#define | EMAC_MII_WR_TOUT 0x00050000 |
#define | EMAC_MII_RD_TOUT 0x00050000 |
#define | EMAC_MADR_REG_ADR(n) (n&0x1F) |
#define | EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) |
#define | EMAC_MWTD_DATA(n) (n&0xFFFF) |
#define | EMAC_MRDD_DATA(n) (n&0xFFFF) |
#define | EMAC_MIND_BUSY 0x00000001 |
#define | EMAC_MIND_SCAN 0x00000002 |
#define | EMAC_MIND_NOT_VAL 0x00000004 |
#define | EMAC_MIND_MII_LINK_FAIL 0x00000008 |
#define | EMAC_CR_RX_EN 0x00000001 |
#define | EMAC_CR_TX_EN 0x00000002 |
#define | EMAC_CR_REG_RES 0x00000008 |
#define | EMAC_CR_TX_RES 0x00000010 |
#define | EMAC_CR_RX_RES 0x00000020 |
#define | EMAC_CR_PASS_RUNT_FRM 0x00000040 |
#define | EMAC_CR_PASS_RX_FILT 0x00000080 |
#define | EMAC_CR_TX_FLOW_CTRL 0x00000100 |
#define | EMAC_CR_RMII 0x00000200 |
#define | EMAC_CR_FULL_DUP 0x00000400 |
#define | EMAC_SR_RX_EN 0x00000001 |
#define | EMAC_SR_TX_EN 0x00000002 |
#define | EMAC_TSV0_CRC_ERR 0x00000001 |
#define | EMAC_TSV0_LEN_CHKERR 0x00000002 |
#define | EMAC_TSV0_LEN_OUTRNG 0x00000004 |
#define | EMAC_TSV0_DONE 0x00000008 |
#define | EMAC_TSV0_MCAST 0x00000010 |
#define | EMAC_TSV0_BCAST 0x00000020 |
#define | EMAC_TSV0_PKT_DEFER 0x00000040 |
#define | EMAC_TSV0_EXC_DEFER 0x00000080 |
#define | EMAC_TSV0_EXC_COLL 0x00000100 |
#define | EMAC_TSV0_LATE_COLL 0x00000200 |
#define | EMAC_TSV0_GIANT 0x00000400 |
#define | EMAC_TSV0_UNDERRUN 0x00000800 |
#define | EMAC_TSV0_BYTES 0x0FFFF000 |
#define | EMAC_TSV0_CTRL_FRAME 0x10000000 |
#define | EMAC_TSV0_PAUSE 0x20000000 |
#define | EMAC_TSV0_BACK_PRESS 0x40000000 |
#define | EMAC_TSV0_VLAN 0x80000000 |
#define | EMAC_TSV1_BYTE_CNT 0x0000FFFF |
#define | EMAC_TSV1_COLL_CNT 0x000F0000 |
#define | EMAC_RSV_BYTE_CNT 0x0000FFFF |
#define | EMAC_RSV_PKT_IGNORED 0x00010000 |
#define | EMAC_RSV_RXDV_SEEN 0x00020000 |
#define | EMAC_RSV_CARR_SEEN 0x00040000 |
#define | EMAC_RSV_REC_CODEV 0x00080000 |
#define | EMAC_RSV_CRC_ERR 0x00100000 |
#define | EMAC_RSV_LEN_CHKERR 0x00200000 |
#define | EMAC_RSV_LEN_OUTRNG 0x00400000 |
#define | EMAC_RSV_REC_OK 0x00800000 |
#define | EMAC_RSV_MCAST 0x01000000 |
#define | EMAC_RSV_BCAST 0x02000000 |
#define | EMAC_RSV_DRIB_NIBB 0x04000000 |
#define | EMAC_RSV_CTRL_FRAME 0x08000000 |
#define | EMAC_RSV_PAUSE 0x10000000 |
#define | EMAC_RSV_UNSUPP_OPC 0x20000000 |
#define | EMAC_RSV_VLAN 0x40000000 |
#define | EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) |
#define | EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) |
#define | EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) |
#define | EMAC_RFC_UCAST_EN 0x00000001 |
#define | EMAC_RFC_BCAST_EN 0x00000002 |
#define | EMAC_RFC_MCAST_EN 0x00000004 |
#define | EMAC_RFC_UCAST_HASH_EN 0x00000008 |
#define | EMAC_RFC_MCAST_HASH_EN 0x00000010 |
#define | EMAC_RFC_PERFECT_EN 0x00000020 |
#define | EMAC_RFC_MAGP_WOL_EN 0x00001000 |
#define | EMAC_RFC_PFILT_WOL_EN 0x00002000 |
#define | EMAC_WOL_UCAST 0x00000001 |
#define | EMAC_WOL_BCAST 0x00000002 |
#define | EMAC_WOL_MCAST 0x00000004 |
#define | EMAC_WOL_UCAST_HASH 0x00000008 |
#define | EMAC_WOL_MCAST_HASH 0x00000010 |
#define | EMAC_WOL_PERFECT 0x00000020 |
#define | EMAC_WOL_RX_FILTER 0x00000080 |
#define | EMAC_WOL_MAG_PACKET 0x00000100 |
#define | EMAC_WOL_BITMASK 0x01BF |
#define | EMAC_INT_RX_OVERRUN 0x00000001 |
#define | EMAC_INT_RX_ERR 0x00000002 |
#define | EMAC_INT_RX_FIN 0x00000004 |
#define | EMAC_INT_RX_DONE 0x00000008 |
#define | EMAC_INT_TX_UNDERRUN 0x00000010 |
#define | EMAC_INT_TX_ERR 0x00000020 |
#define | EMAC_INT_TX_FIN 0x00000040 |
#define | EMAC_INT_TX_DONE 0x00000080 |
#define | EMAC_INT_SOFT_INT 0x00001000 |
#define | EMAC_INT_WAKEUP 0x00002000 |
#define | EMAC_PD_POWER_DOWN 0x80000000 |
#define | EMAC_NUM_RX_FRAG 6 |
#define | EMAC_NUM_TX_FRAG 4 |
#define | EMAC_ETH_MAX_FLEN 1536 |
#define | EMAC_TX_FRAME_TOUT 0x00100000 |
#define | RX_DESC_BASE 0x20004000 |
#define | RX_STAT_BASE (RX_DESC_BASE + EMAC_NUM_RX_FRAG * 8) |
#define | TX_DESC_BASE (RX_STAT_BASE + EMAC_NUM_RX_FRAG * 8) |
#define | TX_STAT_BASE (TX_DESC_BASE + EMAC_NUM_TX_FRAG * 8) |
#define | RX_BUF_BASE (TX_STAT_BASE + EMAC_NUM_TX_FRAG * 4) |
#define | TX_BUF_BASE (RX_BUF_BASE + EMAC_NUM_RX_FRAG * EMAC_ETH_MAX_FLEN) |
#define | RX_DESC_PACKET(i) (*(uint32_t *)(RX_DESC_BASE + 8 * i)) |
#define | RX_DESC_CTRL(i) (*(uint32_t *)(RX_DESC_BASE + 4 + 8 * i)) |
#define | RX_STAT_INFO(i) (*(uint32_t *)(RX_STAT_BASE + 8 * i)) |
#define | RX_STAT_HASHCRC(i) (*(uint32_t *)(RX_STAT_BASE + 4 + 8 * i)) |
#define | TX_DESC_PACKET(i) (*(uint32_t *)(TX_DESC_BASE + 8 * i)) |
#define | TX_DESC_CTRL(i) (*(uint32_t *)(TX_DESC_BASE + 4 + 8 * i)) |
#define | TX_STAT_INFO(i) (*(uint32_t *)(TX_STAT_BASE + 4 * i)) |
#define | RX_BUF(i) (RX_BUF_BASE + EMAC_ETH_MAX_FLEN * i) |
#define | TX_BUF(i) (TX_BUF_BASE + EMAC_ETH_MAX_FLEN * i) |
#define | EMAC_RCTRL_SIZE(n) (n&0x7FF) |
#define | EMAC_RCTRL_INT 0x80000000 |
#define | EMAC_RHASH_SA 0x000001FF |
#define | EMAC_RHASH_DA 0x001FF000 |
#define | EMAC_RINFO_SIZE 0x000007FF |
#define | EMAC_RINFO_CTRL_FRAME 0x00040000 |
#define | EMAC_RINFO_VLAN 0x00080000 |
#define | EMAC_RINFO_FAIL_FILT 0x00100000 |
#define | EMAC_RINFO_MCAST 0x00200000 |
#define | EMAC_RINFO_BCAST 0x00400000 |
#define | EMAC_RINFO_CRC_ERR 0x00800000 |
#define | EMAC_RINFO_SYM_ERR 0x01000000 |
#define | EMAC_RINFO_LEN_ERR 0x02000000 |
#define | EMAC_RINFO_RANGE_ERR 0x04000000 |
#define | EMAC_RINFO_ALIGN_ERR 0x08000000 |
#define | EMAC_RINFO_OVERRUN 0x10000000 |
#define | EMAC_RINFO_NO_DESCR 0x20000000 |
#define | EMAC_RINFO_LAST_FLAG 0x40000000 |
#define | EMAC_RINFO_ERR 0x80000000 |
#define | EMAC_RINFO_ERR_MASK |
#define | EMAC_TCTRL_SIZE 0x000007FF |
#define | EMAC_TCTRL_OVERRIDE 0x04000000 |
#define | EMAC_TCTRL_HUGE 0x08000000 |
#define | EMAC_TCTRL_PAD 0x10000000 |
#define | EMAC_TCTRL_CRC 0x20000000 |
#define | EMAC_TCTRL_LAST 0x40000000 |
#define | EMAC_TCTRL_INT 0x80000000 |
#define | EMAC_TINFO_COL_CNT 0x01E00000 |
#define | EMAC_TINFO_DEFER 0x02000000 |
#define | EMAC_TINFO_EXCESS_DEF 0x04000000 |
#define | EMAC_TINFO_EXCESS_COL 0x08000000 |
#define | EMAC_TINFO_LATE_COL 0x10000000 |
#define | EMAC_TINFO_UNDERRUN 0x20000000 |
#define | EMAC_TINFO_NO_DESCR 0x40000000 |
#define | EMAC_TINFO_ERR 0x80000000 |
Enumerations | |
enum | EMAC_BUFF_STATUS { EMAC_BUFF_EMPTY, EMAC_BUFF_PARTIAL_FULL, EMAC_BUFF_FULL } |
enum | EMAC_BUFF_IDX { EMAC_TX_BUFF, EMAC_RX_BUFF } |
#define EMAC_MAC1_MASK 0xcf1f |
* $Id: $ *
#define EMAC_MAC1_REC_EN 0x00000001 |
#define EMAC_MAC1_PASS_ALL 0x00000002 |
#define EMAC_MAC1_RX_FLOWC 0x00000004 |
#define EMAC_MAC1_TX_FLOWC 0x00000008 |
#define EMAC_MAC1_LOOPB 0x00000010 |
#define EMAC_MAC1_RES_TX 0x00000100 |
#define EMAC_MAC1_RES_MCS_TX 0x00000200 |
#define EMAC_MAC1_RES_RX 0x00000400 |
#define EMAC_MAC1_RES_MCS_RX 0x00000800 |
#define EMAC_MAC1_SIM_RES 0x00004000 |
#define EMAC_MAC1_SOFT_RES 0x00008000 |
#define EMAC_MAC2_MASK 0x73ff |
#define EMAC_MAC2_FULL_DUP 0x00000001 |
#define EMAC_MAC2_FRM_LEN_CHK 0x00000002 |
#define EMAC_MAC2_HUGE_FRM_EN 0x00000004 |
#define EMAC_MAC2_DLY_CRC 0x00000008 |
#define EMAC_MAC2_CRC_EN 0x00000010 |
#define EMAC_MAC2_PAD_EN 0x00000020 |
#define EMAC_MAC2_VLAN_PAD_EN 0x00000040 |
#define EMAC_MAC2_ADET_PAD_EN 0x00000080 |
#define EMAC_MAC2_PPREAM_ENF 0x00000100 |
#define EMAC_MAC2_LPREAM_ENF 0x00000200 |
#define EMAC_MAC2_NO_BACKOFF 0x00001000 |
#define EMAC_MAC2_BACK_PRESSURE 0x00002000 |
#define EMAC_MAC2_EXCESS_DEF 0x00004000 |
#define EMAC_IPGT_BBIPG | ( | n | ) | (n&0x7F) |
#define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) |
#define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) |
#define EMAC_IPGR_NBBIPG_P2 | ( | n | ) | (n&0x7F) |
#define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) |
#define EMAC_IPGR_NBBIPG_P1 | ( | n | ) | ((n&0x7F)<<8) |
#define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) |
#define EMAC_CLRT_MAX_RETX | ( | n | ) | (n&0x0F) |
#define EMAC_CLRT_COLL | ( | n | ) | ((n&0x3F)<<8) |
#define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) |
#define EMAC_MAXF_MAXFRMLEN | ( | n | ) | (n&0xFFFF) |
#define EMAC_MAXF_MAXFRMLEN_DEF (0x6000) |
#define EMAC_SUPP_SPEED 0x00000100 |
#define EMAC_SUPP_RES_RMII 0x00000800 |
#define EMAC_TEST_SHCUT_PQUANTA 0x00000001 |
#define EMAC_TEST_TST_PAUSE 0x00000002 |
#define EMAC_TEST_TST_BACKP 0x00000004 |
#define EMAC_MCFG_SCAN_INC 0x00000001 |
#define EMAC_MCFG_SUPP_PREAM 0x00000002 |
#define EMAC_MCFG_CLK_SEL | ( | n | ) | ((n&0x0F)<<2) |
#define EMAC_MCFG_RES_MII 0x00008000 |
#define EMAC_MCFG_MII_MAXCLK 2500000UL |
#define EMAC_MCMD_READ 0x00000001 |
#define EMAC_MCMD_SCAN 0x00000002 |
#define EMAC_MII_WR_TOUT 0x00050000 |
#define EMAC_MII_RD_TOUT 0x00050000 |
#define EMAC_MADR_REG_ADR | ( | n | ) | (n&0x1F) |
#define EMAC_MADR_PHY_ADR | ( | n | ) | ((n&0x1F)<<8) |
#define EMAC_MWTD_DATA | ( | n | ) | (n&0xFFFF) |
#define EMAC_MRDD_DATA | ( | n | ) | (n&0xFFFF) |
#define EMAC_MIND_BUSY 0x00000001 |
#define EMAC_MIND_SCAN 0x00000002 |
#define EMAC_MIND_NOT_VAL 0x00000004 |
#define EMAC_MIND_MII_LINK_FAIL 0x00000008 |
#define EMAC_CR_RX_EN 0x00000001 |
#define EMAC_CR_TX_EN 0x00000002 |
#define EMAC_CR_REG_RES 0x00000008 |
#define EMAC_CR_TX_RES 0x00000010 |
#define EMAC_CR_RX_RES 0x00000020 |
#define EMAC_CR_PASS_RUNT_FRM 0x00000040 |
#define EMAC_CR_PASS_RX_FILT 0x00000080 |
#define EMAC_CR_TX_FLOW_CTRL 0x00000100 |
#define EMAC_CR_RMII 0x00000200 |
#define EMAC_CR_FULL_DUP 0x00000400 |
#define EMAC_SR_RX_EN 0x00000001 |
#define EMAC_SR_TX_EN 0x00000002 |
#define EMAC_TSV0_CRC_ERR 0x00000001 |
#define EMAC_TSV0_LEN_CHKERR 0x00000002 |
#define EMAC_TSV0_LEN_OUTRNG 0x00000004 |
#define EMAC_TSV0_DONE 0x00000008 |
#define EMAC_TSV0_MCAST 0x00000010 |
#define EMAC_TSV0_BCAST 0x00000020 |
#define EMAC_TSV0_PKT_DEFER 0x00000040 |
#define EMAC_TSV0_EXC_DEFER 0x00000080 |
#define EMAC_TSV0_EXC_COLL 0x00000100 |
#define EMAC_TSV0_LATE_COLL 0x00000200 |
#define EMAC_TSV0_GIANT 0x00000400 |
#define EMAC_TSV0_UNDERRUN 0x00000800 |
#define EMAC_TSV0_BYTES 0x0FFFF000 |
#define EMAC_TSV0_CTRL_FRAME 0x10000000 |
#define EMAC_TSV0_PAUSE 0x20000000 |
#define EMAC_TSV0_BACK_PRESS 0x40000000 |
#define EMAC_TSV0_VLAN 0x80000000 |
#define EMAC_TSV1_BYTE_CNT 0x0000FFFF |
#define EMAC_TSV1_COLL_CNT 0x000F0000 |
#define EMAC_RSV_BYTE_CNT 0x0000FFFF |
#define EMAC_RSV_PKT_IGNORED 0x00010000 |
#define EMAC_RSV_RXDV_SEEN 0x00020000 |
#define EMAC_RSV_CARR_SEEN 0x00040000 |
#define EMAC_RSV_REC_CODEV 0x00080000 |
#define EMAC_RSV_CRC_ERR 0x00100000 |
#define EMAC_RSV_LEN_CHKERR 0x00200000 |
#define EMAC_RSV_LEN_OUTRNG 0x00400000 |
#define EMAC_RSV_REC_OK 0x00800000 |
#define EMAC_RSV_MCAST 0x01000000 |
#define EMAC_RSV_BCAST 0x02000000 |
#define EMAC_RSV_DRIB_NIBB 0x04000000 |
#define EMAC_RSV_CTRL_FRAME 0x08000000 |
#define EMAC_RSV_PAUSE 0x10000000 |
#define EMAC_RSV_UNSUPP_OPC 0x20000000 |
#define EMAC_RSV_VLAN 0x40000000 |
#define EMAC_FCC_MIRR_CNT | ( | n | ) | (n&0xFFFF) |
#define EMAC_FCC_PAUSE_TIM | ( | n | ) | ((n&0xFFFF)<<16) |
#define EMAC_FCS_MIRR_CNT | ( | n | ) | (n&0xFFFF) |
#define EMAC_RFC_UCAST_EN 0x00000001 |
#define EMAC_RFC_BCAST_EN 0x00000002 |
#define EMAC_RFC_MCAST_EN 0x00000004 |
#define EMAC_RFC_UCAST_HASH_EN 0x00000008 |
#define EMAC_RFC_MCAST_HASH_EN 0x00000010 |
#define EMAC_RFC_PERFECT_EN 0x00000020 |
#define EMAC_RFC_MAGP_WOL_EN 0x00001000 |
#define EMAC_RFC_PFILT_WOL_EN 0x00002000 |
#define EMAC_WOL_UCAST 0x00000001 |
#define EMAC_WOL_BCAST 0x00000002 |
#define EMAC_WOL_MCAST 0x00000004 |
#define EMAC_WOL_UCAST_HASH 0x00000008 |
#define EMAC_WOL_MCAST_HASH 0x00000010 |
#define EMAC_WOL_PERFECT 0x00000020 |
#define EMAC_WOL_RX_FILTER 0x00000080 |
#define EMAC_WOL_MAG_PACKET 0x00000100 |
#define EMAC_WOL_BITMASK 0x01BF |
#define EMAC_INT_RX_OVERRUN 0x00000001 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_RX_ERR 0x00000002 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_RX_FIN 0x00000004 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_RX_DONE 0x00000008 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_TX_UNDERRUN 0x00000010 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_TX_ERR 0x00000020 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_TX_FIN 0x00000040 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_TX_DONE 0x00000080 |
Referenced by Lpc17xxEmacRxThread().
#define EMAC_INT_SOFT_INT 0x00001000 |
#define EMAC_INT_WAKEUP 0x00002000 |
#define EMAC_PD_POWER_DOWN 0x80000000 |
#define EMAC_NUM_RX_FRAG 6 |
#define EMAC_NUM_TX_FRAG 4 |
#define EMAC_ETH_MAX_FLEN 1536 |
#define EMAC_TX_FRAME_TOUT 0x00100000 |
#define RX_DESC_BASE 0x20004000 |
#define RX_STAT_BASE (RX_DESC_BASE + EMAC_NUM_RX_FRAG * 8) |
#define TX_DESC_BASE (RX_STAT_BASE + EMAC_NUM_RX_FRAG * 8) |
#define TX_STAT_BASE (TX_DESC_BASE + EMAC_NUM_TX_FRAG * 8) |
#define RX_BUF_BASE (TX_STAT_BASE + EMAC_NUM_TX_FRAG * 4) |
#define TX_BUF_BASE (RX_BUF_BASE + EMAC_NUM_RX_FRAG * EMAC_ETH_MAX_FLEN) |
#define RX_DESC_PACKET | ( | i | ) | (*(uint32_t *)(RX_DESC_BASE + 8 * i)) |
#define RX_DESC_CTRL | ( | i | ) | (*(uint32_t *)(RX_DESC_BASE + 4 + 8 * i)) |
#define RX_STAT_INFO | ( | i | ) | (*(uint32_t *)(RX_STAT_BASE + 8 * i)) |
#define RX_STAT_HASHCRC | ( | i | ) | (*(uint32_t *)(RX_STAT_BASE + 4 + 8 * i)) |
#define TX_DESC_PACKET | ( | i | ) | (*(uint32_t *)(TX_DESC_BASE + 8 * i)) |
#define TX_DESC_CTRL | ( | i | ) | (*(uint32_t *)(TX_DESC_BASE + 4 + 8 * i)) |
#define TX_STAT_INFO | ( | i | ) | (*(uint32_t *)(TX_STAT_BASE + 4 * i)) |
#define RX_BUF | ( | i | ) | (RX_BUF_BASE + EMAC_ETH_MAX_FLEN * i) |
#define TX_BUF | ( | i | ) | (TX_BUF_BASE + EMAC_ETH_MAX_FLEN * i) |
#define EMAC_RCTRL_SIZE | ( | n | ) | (n&0x7FF) |
#define EMAC_RCTRL_INT 0x80000000 |
#define EMAC_RHASH_SA 0x000001FF |
#define EMAC_RHASH_DA 0x001FF000 |
#define EMAC_RINFO_SIZE 0x000007FF |
#define EMAC_RINFO_CTRL_FRAME 0x00040000 |
#define EMAC_RINFO_VLAN 0x00080000 |
#define EMAC_RINFO_FAIL_FILT 0x00100000 |
#define EMAC_RINFO_MCAST 0x00200000 |
#define EMAC_RINFO_BCAST 0x00400000 |
#define EMAC_RINFO_CRC_ERR 0x00800000 |
#define EMAC_RINFO_SYM_ERR 0x01000000 |
#define EMAC_RINFO_LEN_ERR 0x02000000 |
#define EMAC_RINFO_RANGE_ERR 0x04000000 |
#define EMAC_RINFO_ALIGN_ERR 0x08000000 |
#define EMAC_RINFO_OVERRUN 0x10000000 |
#define EMAC_RINFO_NO_DESCR 0x20000000 |
#define EMAC_RINFO_LAST_FLAG 0x40000000 |
#define EMAC_RINFO_ERR 0x80000000 |
#define EMAC_RINFO_ERR_MASK |
(EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | \ EMAC_RINFO_SYM_ERR | EMAC_RINFO_LEN_ERR | \ EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
#define EMAC_TCTRL_SIZE 0x000007FF |
#define EMAC_TCTRL_OVERRIDE 0x04000000 |
#define EMAC_TCTRL_HUGE 0x08000000 |
#define EMAC_TCTRL_PAD 0x10000000 |
#define EMAC_TCTRL_CRC 0x20000000 |
#define EMAC_TCTRL_LAST 0x40000000 |
#define EMAC_TCTRL_INT 0x80000000 |
#define EMAC_TINFO_COL_CNT 0x01E00000 |
#define EMAC_TINFO_DEFER 0x02000000 |
#define EMAC_TINFO_EXCESS_DEF 0x04000000 |
#define EMAC_TINFO_EXCESS_COL 0x08000000 |
#define EMAC_TINFO_LATE_COL 0x10000000 |
#define EMAC_TINFO_UNDERRUN 0x20000000 |
#define EMAC_TINFO_NO_DESCR 0x40000000 |
#define EMAC_TINFO_ERR 0x80000000 |
enum EMAC_BUFF_STATUS |
enum EMAC_BUFF_IDX |