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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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#include <cfg/arch.h>Go to the source code of this file.
Data Structures | |
| struct | mci_cid |
| Multimedia card identification register. More... | |
Defines | |
| #define | HIGH_LVL (1) |
| #define | LOW_LVL (0) |
| #define | CMD0_GO_IDLE_STATE 0 |
| #define | CMD1_SEND_OP_COND 1 |
| #define | CMD2_ALL_SEND_CID 2 |
| #define | CMD3_SET_RELATIVE_ADDR 3 |
| #define | ACMD6_SET_BUS_WIDTH 6 |
| #define | CMD7_SELECT_CARD 7 |
| #define | CMD8_SEND_IF_COND 8 |
| #define | CMD9_SEND_CSD 9 |
| #define | CMD12_STOP_TRANSMISSION 12 |
| #define | CMD13_SEND_STATUS 13 |
| #define | CMD16_SET_BLOCK_LEN 16 |
| #define | CMD17_READ_SINGLE_BLOCK 17 |
| #define | CMD18_READ_MULTIPLE_BLOCK 18 |
| #define | CMD24_WRITE_BLOCK 24 |
| #define | CMD25_WRITE_MULTIPLE_BLOCK 25 |
| #define | CMD32_ERASE_WR_BLK_START 32 |
| #define | CMD33_ERASE_WR_BLK_END 33 |
| #define | CMD38_ERASE 38 |
| #define | ACMD41_SEND_APP_OP_COND 41 |
| #define | CMD55_APP_CMD 55 |
| #define | OCR_INDEX 0x00FF8000 |
| #define | CARD_STATUS_ACMD_ENABLE (1 << 5) |
| #define | CARD_STATUS_RDY_DATA (1 << 8) |
| #define | CARD_STATUS_CURRENT_STATE (0x0F << 9) |
| #define | CARD_STATUS_ERASE_RESET (1 << 13) |
| #define | MCI_SLOW_RATE 1 |
| #define | MCI_NORMAL_RATE 2 |
| #define | SD_1_BIT 0 |
| #define | SD_4_BIT 1 |
| #define | CARD_UNKNOWN 0 |
| #define | MMC_CARD 1 |
| #define | SD_CARD 2 |
| #define | MCLKDIV_SLOW (75 - 1) |
| #define | MCLKDIV_NORMAL (60 - 1) |
| #define | DATA_TIMER_VALUE 0x10000 |
| #define | EXPECT_NO_RESP 0 |
| #define | EXPECT_SHORT_RESP 1 |
| #define | EXPECT_LONG_RESP 2 |
| #define | MCI_OUTPUT_MODE_PUSHPULL (0) |
| #define | MCI_OUTPUT_MODE_OPENDRAIN (1) |
| #define | NOT_ALLOW_CMD_TIMER 0 |
| #define | ALLOW_CMD_TIMER 1 |
| #define | MCI_DISABLE_CMD_TIMER (1<<8) |
| #define | MCI_DMA_SIZE (1000UL) |
| #define | MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE |
| #define | MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE) |
| #define | MMC_BLOCK_MODE 0 |
| #define | MMC_BYTE_MODE 1 |
| #define | DATA_BLOCK_LEN 9 |
| #define | BLOCK_LENGTH (1 << DATA_BLOCK_LEN) |
| #define | BLOCK_NUM 0x80 |
| #define | FIFO_SIZE 16 |
| #define | BUS_WIDTH_1BIT 0 |
| #define | BUS_WIDTH_4BITS 10 |
| #define | MCI_CMD_CRC_FAIL (1 << 0) |
| #define | MCI_DATA_CRC_FAIL (1 << 1) |
| #define | MCI_CMD_TIMEOUT (1 << 2) |
| #define | MCI_DATA_TIMEOUT (1 << 3) |
| #define | MCI_TX_UNDERRUN (1 << 4) |
| #define | MCI_RX_OVERRUN (1 << 5) |
| #define | MCI_CMD_RESP_END (1 << 6) |
| #define | MCI_CMD_SENT (1 << 7) |
| #define | MCI_DATA_END (1 << 8) |
| #define | MCI_START_BIT_ERR (1 << 9) |
| #define | MCI_DATA_BLK_END (1 << 10) |
| #define | MCI_CMD_ACTIVE (1 << 11) |
| #define | MCI_TX_ACTIVE (1 << 12) |
| #define | MCI_RX_ACTIVE (1 << 13) |
| #define | MCI_TX_HALF_EMPTY (1 << 14) |
| #define | MCI_RX_HALF_FULL (1 << 15) |
| #define | MCI_TX_FIFO_FULL (1 << 16) |
| #define | MCI_RX_FIFO_FULL (1 << 17) |
| #define | MCI_TX_FIFO_EMPTY (1 << 18) |
| #define | MCI_RX_FIFO_EMPTY (1 << 19) |
| #define | MCI_TX_DATA_AVAIL (1 << 20) |
| #define | MCI_RX_DATA_AVAIL (1 << 21) |
| #define | MCI_DATACTRL_ENABLE_POS (0) |
| #define | MCI_DATACTRL_ENABLE_MASK (0x01) |
| #define | MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS) |
| #define | MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS) |
| #define | MCI_DATACTRL_DIR_POS (1) |
| #define | MCI_DATACTRL_DIR_MASK (0x01) |
| #define | MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS) |
| #define | MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS) |
| #define | MCI_DATACTRL_XFER_MODE_POS (2) |
| #define | MCI_DATACTRL_XFER_MODE_MASK (0x01) |
| #define | MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS) |
| #define | MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS) |
| #define | MCI_DATACTRL_DMA_ENABLE_POS (3) |
| #define | MCI_DATACTRL_DMA_ENABLE_MASK (0x01) |
| #define | MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS) |
| #define | MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS) |
| #define | MCI_DTATCTRL_BLOCKSIZE(n) _SBF(4, (n & 0xF)) |
| #define | CMD_INT_MASK |
| #define | DATA_ERR_INT_MASK |
| #define | ACTIVE_INT_MASK (MCI_TX_ACTIVE | MCI_RX_ACTIVE) |
| #define | FIFO_INT_MASK |
| #define | FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY) |
| #define | FIFO_RX_INT_MASK (MCI_RX_HALF_FULL ) |
| #define | DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END) |
| #define | ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR) |
| #define | ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR) |
| #define | INVALID_RESPONSE 0xFFFFFFFF |
Typedefs | |
| typedef enum mci_card_state | en_Mci_CardState |
| typedef enum mci_func_error | en_Mci_Func_Error |
| typedef enum mci_card_type | en_Mci_CardType |
| typedef struct mci_cid | st_Mci_CardId |
| Multimedia card identification register. | |
Enumerations | |
| enum | mci_card_state { MCI_CARDSTATE_IDLE = 0, MCI_CARDSTATE_READY, MCI_CARDSTATE_IDENDTIFIED, MCI_CARDSTATE_STBY, MCI_CARDSTATE_TRAN, MCI_CARDSTATE_DATA, MCI_CARDSTATE_RCV, MCI_CARDSTATE_PRG, MCI_CARDSTATE_DIS } |
| enum | mci_func_error { MCI_FUNC_OK = 0, MCI_FUNC_FAILED = -1, MCI_FUNC_BAD_PARAMETERS = -2, MCI_FUNC_BUS_NOT_IDLE = -3, MCI_FUNC_TIMEOUT = -3, MCI_FUNC_ERR_STATE = -4, MCI_FUNC_NOT_READY = -5 } |
| enum | mci_card_type { MCI_SDHC_SDXC_CARD = 3, MCI_SDSC_V2_CARD = 2, MCI_MMC_CARD = 1, MCI_SDSC_V1_CARD = 0, MCI_CARD_UNKNOWN = -1 } |
Functions | |
| int32_t | Lpc177x_8x_MciInit (uint8_t powerActiveLevel) |
| Do initialization the MCI block as set its clock, registers, setup NVIC for interrupts, configure the pins used for MCI function, do initialize the card in slot... | |
| void | Lpc177x_8x_MciSendCmd (uint32_t CmdIndex, uint32_t Argument, uint32_t ExpectResp, uint32_t AllowTimeout) |
| The routine is used to send a CMD to the card. | |
| int32_t | Lpc177x_8x_MciGetCmdResp (uint32_t CmdIndex, uint32_t NeedRespFlag, uint32_t *CmdRespStatus) |
| The routine is to get the reponse from card after commands. This function is always used in pair of Lpc177x_8x_MciSendCmd() func. | |
| int32_t | Lpc177x_8x_MciCmdResp (uint32_t CmdIndex, uint32_t Argument, uint32_t ExpectResp, uint32_t *CmdResp, uint32_t AllowTimeout) |
| The routine is to send command to cards then get back the reponses (if required). | |
| void | Lpc177x_8x_MciSet_MCIClock (uint32_t clockrate) |
| Set MCI clock rate, during initialization phase < 400K during data phase < 20Mhz. | |
| int32_t | Lpc177x_8x_MciSetBusWidth (uint32_t width) |
| Set the Width to 1-bit Bus or 4-bit Bus. | |
| int32_t | Lpc177x_8x_MciAcmd_SendOpCond (uint8_t hcsVal) |
| Send ACMD41 (SEND_APP_OP_COND) to Host Capacity Support (HCS) information and asks the accessed card to send its operating condition (OCR). | |
| int32_t | Lpc177x_8x_MciCardInit (void) |
| Do initialization for the card in the slot. | |
| en_Mci_CardType | Lpc177x_8x_MciGetCardType (void) |
| Get the type of card that is currently used in the slot. | |
| int32_t | Lpc177x_8x_MciCardReset (void) |
| To reset the card, the CMD0 is sent and then the card is put in idle state. This is the very first command to be sent to initialize either MMC or SD card. | |
| int32_t | Lpc177x_8x_MciCmd_SendIfCond (void) |
| Send CMD8 (SEND_IF_COND) for interface condition to card. | |
| int32_t | Lpc177x_8x_MciGetCID (st_Mci_CardId *cidValue) |
| Get the all the Identifier (CID) of the card by sending the CMD2 (ALL_SEND_CID) command. Then parse 4-byte data obtained from the card by the CID meaning. | |
| int32_t | Lpc177x_8x_MciSetCardAddress (void) |
| Set the address for the card in the slot by sending CMD3 (SET_RELATIVE_ADDR) command. To get the address of the card currently in used, needs to call Lpc177x_8x_MciGetCardAddress() | |
| uint32_t | Lpc177x_8x_MciGetCardAddress (void) |
| Get the address for the card in the slot. | |
| int32_t | Lpc177x_8x_MciGetCSD (uint32_t *csdVal) |
| Get the Card-Specific Data of in-slot card by sending CMD9 (SEND_CSD) command. | |
| int32_t | Lpc177x_8x_MciCmd_SelectCard (void) |
| Select the card by the specified address. This is done by sending out the CMD7 with the address argument to needed card. | |
| int32_t | Lpc177x_8x_MciGetCardStatus (int32_t *cardStatus) |
| Get the status of the card. The return is from the card. By sending CMD13 (SEND_STATUS), the status of the card will be responded from card addressed. | |
| uint32_t | Lpc177x_8x_MciGetDataXferEndState (void) |
| Get the state of data transfer to see if it is ended or not. | |
| uint32_t | Lpc177x_8x_MciGetXferErrState (void) |
| Get the error state of the lastest data transfer. | |
| int32_t | Lpc177x_8x_MciSetBlockLen (uint32_t blockLength) |
| Set the length for the blocks in the next action on data manipulation (as read, write, erase). This function is to send CMD16 (SET_BLOCK_LEN) to cards. | |
| int32_t | Lpc177x_8x_MciAcmd_SendBusWidth (uint32_t buswidth) |
| Set bus-width (1 bit or 4 bit) to work with the card by command CMD6 (SET_ACMD_BUS_WIDTH). | |
| int32_t | Lpc177x_8x_MciCmd_StopTransmission (void) |
| Stop the current transmission on the bus by sending command CMD12 (STOP_TRANSMISSION). In this case, the card may be in a unknown state. So that it need a warm reset for normal operation. | |
| int32_t | Lpc177x_8x_MciCmd_WriteBlock (uint32_t blockNum, uint32_t numOfBlock) |
| Write blocks to card by sending command CMD24 (WRITE_BLOCK) or command CMD25 (WRITE_MULTIPLE_BLOCK) followed by the blocks of data to be written. | |
| int32_t | Lpc177x_8x_MciCmd_ReadBlock (uint32_t blockNum, uint32_t numOfBlock) |
| Read blocks to card by sending CMD17 (READ_SINGLE_BLOCK) or CMD18 (READ_MULTIPLE_BLOCK) commands followed by the blocks of data to be read. | |
| int32_t | Lpc177x_8x_MciWriteBlock (uint8_t *memblock, uint32_t blockNum, uint32_t numOfBlock) |
| Write data at a specific address to starting block with number of blocks will be written from first block. | |
| int32_t | Lpc177x_8x_MciReadBlock (uint8_t *destBlock, uint32_t blockNum, uint32_t numOfBlock) |
| Read data at a specific address to starting block with number of blocks will be read from first block. | |
| #define HIGH_LVL (1) |
| #define LOW_LVL (0) |
Referenced by Lpc177x_8x_MciInit().
| #define CMD0_GO_IDLE_STATE 0 |
Referenced by Lpc177x_8x_MciCardReset().
| #define CMD1_SEND_OP_COND 1 |
Referenced by Lpc177x_8x_MciCmd_SendOpCond(), and Lpc177x_8x_MciGetCmdResp().
| #define CMD2_ALL_SEND_CID 2 |
Referenced by Lpc177x_8x_MciGetCID(), and Lpc177x_8x_MciGetCmdResp().
| #define CMD3_SET_RELATIVE_ADDR 3 |
Referenced by Lpc177x_8x_MciSetCardAddress().
| #define ACMD6_SET_BUS_WIDTH 6 |
Referenced by Lpc177x_8x_MciAcmd_SendBusWidth().
| #define CMD7_SELECT_CARD 7 |
Referenced by Lpc177x_8x_MciCmd_SelectCard().
| #define CMD8_SEND_IF_COND 8 |
Referenced by Lpc177x_8x_MciCmd_SendIfCond().
| #define CMD9_SEND_CSD 9 |
Referenced by Lpc177x_8x_MciGetCmdResp(), and Lpc177x_8x_MciGetCSD().
| #define CMD12_STOP_TRANSMISSION 12 |
Referenced by Lpc177x_8x_MciCmd_StopTransmission(), and Lpc177x_8x_MciGetCmdResp().
| #define CMD13_SEND_STATUS 13 |
Referenced by Lpc177x_8x_MciGetCardStatus().
| #define CMD16_SET_BLOCK_LEN 16 |
Referenced by Lpc177x_8x_MciSetBlockLen().
| #define CMD17_READ_SINGLE_BLOCK 17 |
Referenced by Lpc177x_8x_MciCmd_ReadBlock().
| #define CMD18_READ_MULTIPLE_BLOCK 18 |
Referenced by Lpc177x_8x_MciCmd_ReadBlock().
| #define CMD24_WRITE_BLOCK 24 |
Referenced by Lpc177x_8x_MciCmd_WriteBlock().
| #define CMD25_WRITE_MULTIPLE_BLOCK 25 |
Referenced by Lpc177x_8x_MciCmd_WriteBlock().
| #define CMD32_ERASE_WR_BLK_START 32 |
| #define CMD33_ERASE_WR_BLK_END 33 |
| #define CMD38_ERASE 38 |
| #define ACMD41_SEND_APP_OP_COND 41 |
Referenced by Lpc177x_8x_MciAcmd_SendOpCond(), and Lpc177x_8x_MciGetCmdResp().
| #define CMD55_APP_CMD 55 |
Referenced by Lpc177x_8x_MciCmd_SendACMD().
| #define OCR_INDEX 0x00FF8000 |
Referenced by Lpc177x_8x_MciAcmd_SendOpCond(), and Lpc177x_8x_MciCmd_SendOpCond().
| #define CARD_STATUS_ACMD_ENABLE (1 << 5) |
Referenced by Lpc177x_8x_MciCmd_SendACMD().
| #define CARD_STATUS_RDY_DATA (1 << 8) |
| #define CARD_STATUS_CURRENT_STATE (0x0F << 9) |
| #define CARD_STATUS_ERASE_RESET (1 << 13) |
| #define MCI_SLOW_RATE 1 |
Referenced by Lpc177x_8x_MciInit(), and Lpc177x_8x_MciSet_MCIClock().
| #define MCI_NORMAL_RATE 2 |
Referenced by Lpc177x_8x_MciSet_MCIClock().
| #define SD_1_BIT 0 |
Referenced by Lpc177x_8x_MciSetBusWidth().
| #define SD_4_BIT 1 |
Referenced by Lpc177x_8x_MciSetBusWidth().
| #define CARD_UNKNOWN 0 |
| #define MMC_CARD 1 |
| #define SD_CARD 2 |
| #define MCLKDIV_SLOW (75 - 1) |
Referenced by Lpc177x_8x_MciSet_MCIClock().
| #define MCLKDIV_NORMAL (60 - 1) |
Referenced by Lpc177x_8x_MciSet_MCIClock().
| #define DATA_TIMER_VALUE 0x10000 |
Referenced by Lpc177x_8x_MciReadBlock(), and Lpc177x_8x_MciWriteBlock().
| #define EXPECT_NO_RESP 0 |
Referenced by Lpc177x_8x_MciCardReset(), Lpc177x_8x_MciCmdResp(), Lpc177x_8x_MciGetCmdResp(), and Lpc177x_8x_MciSendCmd().
| #define EXPECT_SHORT_RESP 1 |
Referenced by Lpc177x_8x_MciAcmd_SendBusWidth(), Lpc177x_8x_MciAcmd_SendOpCond(), Lpc177x_8x_MciCmd_ReadBlock(), Lpc177x_8x_MciCmd_SelectCard(), Lpc177x_8x_MciCmd_SendACMD(), Lpc177x_8x_MciCmd_SendIfCond(), Lpc177x_8x_MciCmd_SendOpCond(), Lpc177x_8x_MciCmd_StopTransmission(), Lpc177x_8x_MciCmd_WriteBlock(), Lpc177x_8x_MciGetCardStatus(), Lpc177x_8x_MciGetCmdResp(), Lpc177x_8x_MciSendCmd(), Lpc177x_8x_MciSetBlockLen(), and Lpc177x_8x_MciSetCardAddress().
| #define EXPECT_LONG_RESP 2 |
Referenced by Lpc177x_8x_MciGetCID(), Lpc177x_8x_MciGetCmdResp(), Lpc177x_8x_MciGetCSD(), and Lpc177x_8x_MciSendCmd().
| #define MCI_OUTPUT_MODE_PUSHPULL (0) |
Referenced by Lpc177x_8x_MciAcmd_SendOpCond(), and Lpc177x_8x_MciCardInit().
| #define MCI_OUTPUT_MODE_OPENDRAIN (1) |
Referenced by Lpc177x_8x_MciCardInit(), and Lpc177x_8x_MciSetOutputMode().
| #define NOT_ALLOW_CMD_TIMER 0 |
| #define ALLOW_CMD_TIMER 1 |
Referenced by Lpc177x_8x_MciAcmd_SendBusWidth(), Lpc177x_8x_MciAcmd_SendOpCond(), Lpc177x_8x_MciCmd_ReadBlock(), Lpc177x_8x_MciCmd_SelectCard(), Lpc177x_8x_MciCmd_SendACMD(), Lpc177x_8x_MciCmd_SendIfCond(), Lpc177x_8x_MciCmd_SendOpCond(), Lpc177x_8x_MciCmd_StopTransmission(), Lpc177x_8x_MciCmd_WriteBlock(), Lpc177x_8x_MciGetCardStatus(), Lpc177x_8x_MciGetCID(), Lpc177x_8x_MciGetCSD(), Lpc177x_8x_MciSendCmd(), Lpc177x_8x_MciSetBlockLen(), and Lpc177x_8x_MciSetCardAddress().
| #define MCI_DISABLE_CMD_TIMER (1<<8) |
Referenced by Lpc177x_8x_MciSendCmd().
| #define MCI_DMA_SIZE (1000UL) |
| #define MCI_DMA_SRC_ADDR LPC_PERI_RAM_BASE |
| #define MCI_DMA_DST_ADDR (MCI_DMA_SRC_ADDR + MCI_DMA_SIZE) |
| #define MMC_BLOCK_MODE 0 |
Referenced by Lpc177x_8x_MciCardInit(), Lpc177x_8x_MciCmd_ReadBlock(), and Lpc177x_8x_MciCmd_WriteBlock().
| #define MMC_BYTE_MODE 1 |
Referenced by Lpc177x_8x_MciCardInit().
| #define DATA_BLOCK_LEN 9 |
Referenced by Lpc177x_8x_MciReadBlock(), and Lpc177x_8x_MciWriteBlock().
| #define BLOCK_LENGTH (1 << DATA_BLOCK_LEN) |
| #define BLOCK_NUM 0x80 |
| #define FIFO_SIZE 16 |
| #define BUS_WIDTH_1BIT 0 |
| #define BUS_WIDTH_4BITS 10 |
Referenced by Lpc177x_8x_MciSetBusWidth().
| #define MCI_CMD_CRC_FAIL (1 << 0) |
| #define MCI_DATA_CRC_FAIL (1 << 1) |
Referenced by Lpc177x_8x_MciDataErrorProcess().
| #define MCI_CMD_TIMEOUT (1 << 2) |
Referenced by Lpc177x_8x_MciAcmd_SendOpCond(), Lpc177x_8x_MciCmd_SelectCard(), Lpc177x_8x_MciCmd_SendIfCond(), Lpc177x_8x_MciCmd_SendOpCond(), Lpc177x_8x_MciCmdProcess(), Lpc177x_8x_MciGetCardStatus(), Lpc177x_8x_MciGetCID(), Lpc177x_8x_MciGetCmdResp(), Lpc177x_8x_MciGetCSD(), Lpc177x_8x_MciSetBlockLen(), and Lpc177x_8x_MciSetCardAddress().
| #define MCI_DATA_TIMEOUT (1 << 3) |
Referenced by Lpc177x_8x_MciDataErrorProcess().
| #define MCI_TX_UNDERRUN (1 << 4) |
Referenced by Lpc177x_8x_MciDataErrorProcess().
| #define MCI_RX_OVERRUN (1 << 5) |
Referenced by Lpc177x_8x_MciDataErrorProcess().
| #define MCI_CMD_RESP_END (1 << 6) |
| #define MCI_CMD_SENT (1 << 7) |
Referenced by Lpc177x_8x_MciCmdProcess().
| #define MCI_DATA_END (1 << 8) |
Referenced by Lpc177x_8x_MciDATA_END_InterruptService().
| #define MCI_START_BIT_ERR (1 << 9) |
Referenced by Lpc177x_8x_MciDataErrorProcess().
| #define MCI_DATA_BLK_END (1 << 10) |
Referenced by Lpc177x_8x_MciDATA_END_InterruptService().
| #define MCI_CMD_ACTIVE (1 << 11) |
Referenced by Lpc177x_8x_MciCmdProcess(), and Lpc177x_8x_MciSendCmd().
| #define MCI_TX_ACTIVE (1 << 12) |
Referenced by Lpc177x_8x_MciDATA_END_InterruptService().
| #define MCI_RX_ACTIVE (1 << 13) |
Referenced by Lpc177x_8x_MciDATA_END_InterruptService().
| #define MCI_TX_HALF_EMPTY (1 << 14) |
Referenced by Lpc177x_8x_MciFIFOInterruptService().
| #define MCI_RX_HALF_FULL (1 << 15) |
Referenced by Lpc177x_8x_MciFIFOInterruptService().
| #define MCI_TX_FIFO_FULL (1 << 16) |
| #define MCI_RX_FIFO_FULL (1 << 17) |
| #define MCI_TX_FIFO_EMPTY (1 << 18) |
| #define MCI_RX_FIFO_EMPTY (1 << 19) |
| #define MCI_TX_DATA_AVAIL (1 << 20) |
| #define MCI_RX_DATA_AVAIL (1 << 21) |
| #define MCI_DATACTRL_ENABLE_POS (0) |
| #define MCI_DATACTRL_ENABLE_MASK (0x01) |
| #define MCI_DATACTRL_ENABLE (1 << MCI_DATACTRL_ENABLE_POS) |
Referenced by Lpc177x_8x_MciReadBlock(), and Lpc177x_8x_MciWriteBlock().
| #define MCI_DATACTRL_DISABLE (0 << MCI_DATACTRL_ENABLE_POS) |
| #define MCI_DATACTRL_DIR_POS (1) |
| #define MCI_DATACTRL_DIR_MASK (0x01) |
| #define MCI_DATACTRL_DIR_FROM_CARD (1 << MCI_DATACTRL_DIR_POS) |
Referenced by Lpc177x_8x_MciReadBlock().
| #define MCI_DATACTRL_DIR_TO_CARD (0 << MCI_DATACTRL_DIR_POS) |
Referenced by Lpc177x_8x_MciWriteBlock().
| #define MCI_DATACTRL_XFER_MODE_POS (2) |
| #define MCI_DATACTRL_XFER_MODE_MASK (0x01) |
| #define MCI_DATACTRL_XFER_MODE_STREAM (1 << MCI_DATACTRL_XFER_MODE_POS) |
| #define MCI_DATACTRL_XFER_MODE_BLOCK (0 << MCI_DATACTRL_XFER_MODE_POS) |
| #define MCI_DATACTRL_DMA_ENABLE_POS (3) |
| #define MCI_DATACTRL_DMA_ENABLE_MASK (0x01) |
| #define MCI_DATACTRL_DMA_ENABLE (1 << MCI_DATACTRL_DMA_ENABLE_POS) |
| #define MCI_DATACTRL_DMA_DISABLE (0 << MCI_DATACTRL_DMA_ENABLE_POS) |
| #define MCI_DTATCTRL_BLOCKSIZE | ( | n | ) | _SBF(4, (n & 0xF)) |
Data block length macro
Referenced by Lpc177x_8x_MciReadBlock(), and Lpc177x_8x_MciWriteBlock().
| #define CMD_INT_MASK |
(MCI_CMD_CRC_FAIL | MCI_CMD_TIMEOUT | MCI_CMD_RESP_END | \ MCI_CMD_SENT | MCI_CMD_ACTIVE)
| #define DATA_ERR_INT_MASK |
(MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | \ MCI_RX_OVERRUN | MCI_START_BIT_ERR)
| #define ACTIVE_INT_MASK (MCI_TX_ACTIVE | MCI_RX_ACTIVE) |
| #define FIFO_INT_MASK |
(MCI_TX_HALF_EMPTY | MCI_RX_HALF_FULL | \ MCI_TX_FIFO_FULL | MCI_RX_FIFO_FULL | \ MCI_TX_FIFO_EMPTY | MCI_RX_FIFO_EMPTY | \ MCI_DATA_BLK_END )
| #define FIFO_TX_INT_MASK (MCI_TX_HALF_EMPTY) |
Referenced by Lpc177x_8x_MciFIFOInterruptService(), Lpc177x_8x_MciTXDisable(), and Lpc177x_8x_MciTXEnable().
| #define FIFO_RX_INT_MASK (MCI_RX_HALF_FULL ) |
Referenced by Lpc177x_8x_MciFIFOInterruptService(), Lpc177x_8x_MciRXDisable(), and Lpc177x_8x_MciRXEnable().
| #define DATA_END_INT_MASK (MCI_DATA_END | MCI_DATA_BLK_END) |
Referenced by Lpc177x_8x_MciRXDisable(), Lpc177x_8x_MciRXEnable(), Lpc177x_8x_MciTXDisable(), and Lpc177x_8x_MciTXEnable().
| #define ERR_TX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_TX_UNDERRUN | MCI_START_BIT_ERR) |
Referenced by Lpc177x_8x_MciTXDisable(), and Lpc177x_8x_MciTXEnable().
| #define ERR_RX_INT_MASK (MCI_DATA_CRC_FAIL | MCI_DATA_TIMEOUT | MCI_RX_OVERRUN | MCI_START_BIT_ERR) |
Referenced by Lpc177x_8x_MciRXDisable(), and Lpc177x_8x_MciRXEnable().
| #define INVALID_RESPONSE 0xFFFFFFFF |
Referenced by Lpc177x_8x_MciGetCmdResp().
| typedef enum mci_card_state en_Mci_CardState |
| typedef enum mci_func_error en_Mci_Func_Error |
| typedef enum mci_card_type en_Mci_CardType |
| typedef struct mci_cid st_Mci_CardId |
Multimedia card identification register.
| enum mci_card_state |
| enum mci_func_error |
| enum mci_card_type |