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00143 #include <sys/thread.h>
00144 #include <sys/heap.h>
00145 #include <cfg/memory.h>
00146 #include <cfg/os.h>
00147 #include <cfg/arch/avr.h>
00148 #include <cfg/arch.h>
00149
00154
00155 #ifdef NUTXMEM_SIZE
00156
00159 #define NUTMEM_END (uint16_t)(NUTXMEM_START + (uint16_t)NUTXMEM_SIZE - 1U)
00160
00161 #else
00162
00168 #define NUTMEM_END (uint16_t)(NUTMEM_START + (uint16_t)NUTMEM_SIZE - 1U)
00169
00170 #endif
00171
00172 #ifndef NUT_THREAD_MAINSTACK
00173 #define NUT_THREAD_MAINSTACK 1024
00174 #endif
00175
00176 #ifndef NUT_THREAD_IDLESTACK
00177 #if defined(__GNUC__)
00178
00179 #define NUT_THREAD_IDLESTACK 128
00180 #else
00181
00182 #define NUT_THREAD_IDLESTACK 256
00183 #endif
00184 #endif
00185
00186 #ifdef NUTMEM_RESERVED
00187
00197 uint8_t nutmem_onchip[NUTMEM_RESERVED];
00198 #endif
00199
00200
00201 #if defined(__GNUC__) && defined(__AVR_ENHANCED__)
00202 uint8_t idle_sleep_mode = SLEEP_MODE_NONE;
00203
00204
00205 #if defined(SMCR)
00206 #define AVR_SLEEP_CTRL_REG SMCR
00207 #else
00208 #define AVR_SLEEP_CTRL_REG MCUCR
00209 #endif
00210
00211 #endif
00212
00213
00214
00215
00216
00217 #if defined(RTL_EESK_BIT) && defined(__GNUC__)
00218
00219 #ifndef RTL_BASE_ADDR
00220 #define RTL_BASE_ADDR 0x8300
00221 #endif
00222 #define NIC_CR _MMIO_BYTE(RTL_BASE_ADDR)
00223 #define NIC_EE _MMIO_BYTE(RTL_BASE_ADDR + 1)
00224
00225 #if (RTL_EEMU_AVRPORT == AVRPORTB)
00226 #define RTL_EEMU_PORT PORTB
00227 #define RTL_EEMU_DDR DDRB
00228
00229 #elif (RTL_EEMU_AVRPORT == AVRPORTD)
00230 #define RTL_EEMU_PORT PORTD
00231 #define RTL_EEMU_DDR DDRD
00232
00233 #elif (RTL_EEMU_AVRPORT == AVRPORTE)
00234 #define RTL_EEMU_PORT PORTE
00235 #define RTL_EEMU_DDR DDRE
00236
00237 #elif (RTL_EEMU_AVRPORT == AVRPORTF)
00238 #define RTL_EEMU_PORT PORTF
00239 #define RTL_EEMU_DDR DDRF
00240
00241 #else
00242 #define RTL_EE_MEMBUS
00243 #define RTL_EEMU_PORT PORTC
00244 #define RTL_EEMU_DDR DDRC
00245
00246 #endif
00247
00248 #if (RTL_EEDO_AVRPORT == AVRPORTB)
00249 #define RTL_EEDO_PORT PORTB
00250 #define RTL_EEDO_DDR DDRB
00251
00252 #elif (RTL_EEDO_AVRPORT == AVRPORTD)
00253 #define RTL_EEDO_PORT PORTD
00254 #define RTL_EEDO_DDR DDRD
00255
00256 #elif (RTL_EEDO_AVRPORT == AVRPORTE)
00257 #define RTL_EEDO_PORT PORTE
00258 #define RTL_EEDO_DDR DDRE
00259
00260 #elif (RTL_EEDO_AVRPORT == AVRPORTF)
00261 #define RTL_EEDO_PORT PORTF
00262 #define RTL_EEDO_DDR DDRF
00263
00264 #else
00265 #define RTL_EE_MEMBUS
00266 #define RTL_EEDO_PORT PORTC
00267 #define RTL_EEDO_DDR DDRC
00268
00269 #endif
00270
00271 #if (RTL_EESK_AVRPORT == AVRPORTB)
00272 #define RTL_EESK_PIN PINB
00273 #define RTL_EESK_DDR DDRB
00274
00275 #elif (RTL_EESK_AVRPORT == AVRPORTD)
00276 #define RTL_EESK_PIN PIND
00277 #define RTL_EESK_DDR DDRD
00278
00279 #elif (RTL_EESK_AVRPORT == AVRPORTE)
00280 #define RTL_EESK_PIN PINE
00281 #define RTL_EESK_DDR DDRE
00282
00283 #elif (RTL_EESK_AVRPORT == AVRPORTF)
00284 #define RTL_EESK_PIN PINF
00285 #define RTL_EESK_DDR DDRF
00286
00287 #else
00288 #define RTL_EE_MEMBUS
00289 #define RTL_EESK_PIN PINC
00290 #define RTL_EESK_DDR DDRC
00291
00292 #endif
00293 #endif
00294
00295 #ifdef __GNUC__
00296
00297
00298
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314
00315
00316
00317 void NutInit(void) __attribute__ ((naked)) __attribute__ ((section(".init8")));
00318 extern void NutAppMain(void *arg) __attribute__ ((noreturn));
00319 #else
00320 extern void main(void *);
00321 #endif
00322
00323
00324
00325
00326 #if defined(__GNUC__) && defined(NUTXMEM_SIZE)
00327
00328
00329
00330
00331 static void NutInitXRAM(void) __attribute__ ((naked, section(".init1"), used));
00332 void NutInitXRAM(void)
00333 {
00334 #if defined(__AVR_AT90CAN128__) || defined(__AVR_ATmega2560__) || defined(__AVR_ATmega2561__)
00335
00336
00337
00338
00339 #ifdef NUT_3WAITSTATES
00340 XMCRA = _BV(SRE) | _BV(SRL2) | _BV(SRW00) | _BV(SRW10) | _BV(SRW11);
00341 #else
00342 XMCRA = _BV(SRE) | _BV(SRW10);
00343 #endif
00344
00345 #elif defined(__AVR_ATmega128__)
00346
00347 MCUCR = _BV(SRE) | _BV(SRW10);
00348
00349
00350
00351
00352
00353 #ifdef NUT_3WAITSTATES
00354 XMCRA |= _BV(SRL2) | _BV(SRW00) | _BV(SRW11);
00355 XMCRB = 0;
00356 #endif
00357
00358 #else
00359 MCUCR = _BV(SRE) | _BV(SRW);
00360 #endif
00361 }
00362
00363 #endif
00364
00365
00366 #if defined(RTL_EESK_BIT) && defined(__GNUC__) && defined(NUTXMEM_SIZE)
00367
00368
00369
00370
00371
00372
00373
00374
00375
00376
00377
00378 static void FakeNicEeprom(void) __attribute__ ((naked, section(".init1"), used));
00379 void FakeNicEeprom(void)
00380 {
00381
00382
00383
00384
00385 #ifdef RTL_EEMU_BIT
00386 sbi(RTL_EEMU_PORT, RTL_EEMU_BIT);
00387 sbi(RTL_EEMU_DDR, RTL_EEMU_BIT);
00388 #endif
00389 sbi(RTL_EEDO_PORT, RTL_EEDO_BIT);
00390 sbi(RTL_EEDO_DDR, RTL_EEDO_BIT);
00391
00392
00393 NIC_CR = 0xE1;
00394 NIC_EE = 0x40;
00395
00396
00397 #ifdef RTL_EE_MEMBUS
00398 cbi(MCUCR, SRE);
00399 #endif
00400
00401
00402
00403
00404
00405
00406 __asm__ __volatile__("\n"
00407 "EmuLoop: " "\n"
00408 " ldi r24, 0 " "\n"
00409 " ldi r25, 0 " "\n"
00410 " sbis %0, %1 " "\n"
00411 " rjmp EmuClkClr " "\n"
00412 "EmuClkSet: " "\n"
00413 " adiw r24, 1 " "\n"
00414 " breq EmuDone " "\n"
00415 " sbis %0, %1 " "\n"
00416 " rjmp EmuLoop " "\n"
00417 " rjmp EmuClkSet " "\n"
00418 "EmuClkClr: " "\n"
00419 " adiw r24, 1 " "\n"
00420 " breq EmuDone " "\n"
00421 " sbic %0, %1 " "\n"
00422 " rjmp EmuLoop " "\n"
00423 " rjmp EmuClkClr " "\n"
00424 "EmuDone: \n\t"
00425 :
00426 :"I"(_SFR_IO_ADDR(RTL_EESK_PIN)),
00427 "I"(RTL_EESK_BIT)
00428 :"r24", "r25");
00429
00430
00431 #ifdef RTL_EE_MEMBUS
00432 sbi(MCUCR, SRE);
00433 #endif
00434
00435
00436 #ifdef RTL_EEMU_BIT
00437 cbi(RTL_EEMU_PORT, RTL_EEMU_BIT);
00438 cbi(RTL_EEMU_DDR, RTL_EEMU_BIT);
00439 #endif
00440 cbi(RTL_EEDO_PORT, RTL_EEDO_BIT);
00441 cbi(RTL_EEDO_DDR, RTL_EEDO_BIT);
00442 }
00443
00444 #endif
00445
00457 #if defined(__GNUC__) && defined(__AVR_ENHANCED__)
00458 uint8_t NutThreadSetSleepMode(uint8_t mode)
00459 {
00460 uint8_t old_mode = idle_sleep_mode;
00461 idle_sleep_mode = mode;
00462 return old_mode;
00463 }
00464 #endif
00465
00471 THREAD(NutIdle, arg)
00472 {
00473 #if defined(__GNUC__) && defined(__AVR_ENHANCED__)
00474 uint8_t sleep_mode;
00475 #endif
00476 #ifdef IDLE_HEARTBEAT_BIT
00477 uint8_t beat = 0;
00478 #endif
00479
00480
00481 NutTimerInit();
00482
00483
00484 NutThreadCreate("main", main, 0,
00485 (NUT_THREAD_MAINSTACK * NUT_THREAD_STACK_MULT) + NUT_THREAD_STACK_ADD);
00486
00487
00488
00489
00490
00491
00492 NutThreadSetPriority(254);
00493 for (;;) {
00494 NutThreadYield();
00495 NutThreadDestroy();
00496
00497 #ifdef IDLE_HEARTBEAT_BIT
00498 if ((beat = !beat) == 0) {
00499
00500 cbi(IDLE_HEARTBEAT_PORT, IDLE_HEARTBEAT_BIT);
00501 }
00502 else {
00503 sbi(IDLE_HEARTBEAT_PORT, IDLE_HEARTBEAT_BIT);
00504 }
00505 sbi(IDLE_HEARTBEAT_DDR, IDLE_HEARTBEAT_BIT);
00506 #endif
00507
00508 #if defined(__GNUC__) && defined(__AVR_ENHANCED__)
00509 if (idle_sleep_mode != SLEEP_MODE_NONE) {
00510 sleep_mode = AVR_SLEEP_CTRL_REG & _SLEEP_MODE_MASK;
00511 set_sleep_mode(idle_sleep_mode);
00512 #ifdef IDLE_THREAD_ADC_OFF
00513 uint8_t adc = bit_is_set(ADCSR, ADEN);
00514 cbi(ADCSR, ADEN);
00515 #endif
00516 #ifdef IDLE_THREAD_BUSKEEPER_OFF
00517 uint8_t bitkeeper = bit_is_set(XMCRB, XMBK);
00518 cbi(XMCRB, XMBK);
00519 #endif
00520
00521
00522 AVR_SLEEP_CTRL_REG |= _BV(SE);
00523 __asm__ __volatile__ ("sleep" "\n\t" :: );
00524 AVR_SLEEP_CTRL_REG &= ~_BV(SE);
00525 #ifdef IDLE_THREAD_ADC_OFF
00526 if (bitkeeper) {
00527 sbi(XMCRB, XMBK);
00528 }
00529 #endif
00530 #ifdef IDLE_THREAD_BUSKEEPER_OFF
00531 if (adc) {
00532 sbi(ADCSR, ADEN);
00533 }
00534 #endif
00535 set_sleep_mode(sleep_mode);
00536 }
00537 #endif
00538 }
00539 }
00540
00541 #if defined(__GNUC__)
00542 static void NutInitSP(void) __attribute__ ((naked, section (".init5"), used));
00543 void NutInitSP(void)
00544 {
00545 #if defined (__AVR_AT90CAN128__)
00546
00547 #else
00548
00549
00550
00551 SP = (uint16_t)(NUTMEM_END);
00552 #endif
00553 }
00554 #endif
00555
00556 #if defined(__GNUC__)
00557 static void NutInitHeap(void) __attribute__ ((naked, section (".init5"), used));
00558 #endif
00559 void NutInitHeap()
00560 {
00561 #if defined (NUTMEM_STACKHEAP)
00562 NutStackAdd((void *) NUTMEM_START, NUTMEM_STACKHEAP);
00563 #endif
00564
00565
00566
00567
00568
00569
00570 if ((uint16_t)NUTMEM_END - (uint16_t) (&__heap_start) > 384) {
00571 NutHeapAdd(&__heap_start, (uint16_t) NUTMEM_END - 256 - (uint16_t) (&__heap_start));
00572 }
00573 }
00574
00575 #if defined(__GNUC__)
00576 static void NutCustomInit(void) __attribute__ ((naked, section (".init1"), used));
00577 #endif
00578
00587 void NutCustomInit(void)
00588
00589
00590
00591 #if defined(MMNET02) || defined(MMNET03) || defined(MMNET04) ||\
00592 defined(MMNET102) || defined(MMNET103) || defined(MMNET104)
00593 {
00594 volatile uint8_t *breg = (uint8_t *)((size_t)-1 & ~0xFF);
00595
00596 *(breg + 1) = 0x01;
00597
00598
00599 outp(7, UBRR);
00600 outp(7, UBRR1L);
00601 }
00602
00603
00604
00605 #elif defined(ARTHERNET1)
00606 {
00607
00608
00609
00610
00611
00612 MCUCR = _BV(SRE);
00613 XMCRA |= _BV(SRL0) | _BV(SRW01) | _BV(SRW00);
00614 XMCRB = 0;
00615
00616 *((volatile uint8_t *)(ARTHERCPLDSTART)) = 0x10;
00617 *((volatile uint8_t *)(ARTHERCPLDSPI)) = 0xFF;
00618
00619
00620 outp(25, UBRR);
00621 outp(25, UBRR1L);
00622 }
00623
00624
00625
00626 #elif defined(XNUT_100) || defined(XNUT_105)
00627 {
00628 PORTB = 0x35;
00629 DDRB = 0x3F;
00630 PORTD = 0xE8;
00631 DDRD = 0xB0;
00632 PORTE = 0x0E;
00633 DDRE = 0x02;
00634 PORTF = 0xF0;
00635 DDRF = 0x0F;
00636 PORTG = 0x1F;
00637 DDRG = 0x07;
00638
00639 ACSR |= _BV(ACD);
00640
00641
00642 TWSR = 0;
00643 TWBR = (NUT_CPU_FREQ / 100000UL - 16) / 2;
00644
00645
00646 #if NUT_CPU_FREQ == 14745600
00647 UBRR0L = (NUT_CPU_FREQ / (16 * 9600UL)) - 1;
00648 UBRR1L = (NUT_CPU_FREQ / (16 * 9600UL)) - 1;
00649 #else
00650 sbi(UCSR0A, U2X0);
00651 sbi(UCSR1A, U2X1);
00652 UBRR0L = (NUT_CPU_FREQ / (8 * 9600UL)) - 1;
00653 UBRR1L = (NUT_CPU_FREQ / (8 * 9600UL)) - 1;
00654 #endif
00655 }
00656
00657
00658
00659 #elif defined(HHOPEN_63F)
00660 {
00661 PORTA = 0xF8; DDRA = 0x08;
00662 PORTB = 0x01; DDRB = 0xE7;
00663 PORTC = 0xFF; DDRC = 0x01;
00664 PORTD = 0x18; DDRD = 0xDB;
00665 PORTE = 0x5A; DDRE = 0xEA;
00666 PORTF = 0x80; DDRF = 0xFF;
00667 PORTG = 0x00; DDRG = 0xFF;
00668
00669 ACSR |= _BV(ACD);
00670
00671
00672 TWSR = 0;
00673 TWBR = (NUT_CPU_FREQ / 100000UL - 16) / 2;
00674
00675
00676 #if NUT_CPU_FREQ == 14745600
00677 UBRR0L = (NUT_CPU_FREQ / (16 * 9600UL)) - 1;
00678 UBRR1L = (NUT_CPU_FREQ / (16 * 9600UL)) - 1;
00679 #else
00680 sbi(UCSR0A, U2X0);
00681 sbi(UCSR1A, U2X1);
00682 UBRR0L = (NUT_CPU_FREQ / (8 * 9600UL)) - 1;
00683 UBRR1L = (NUT_CPU_FREQ / (8 * 9600UL)) - 1;
00684 #endif
00685 }
00686
00687
00688
00689
00690 #else
00691 {
00692
00693 outp(7, UBRR);
00694 #ifdef __AVR_ENHANCED__
00695 outp(7, UBRR1L);
00696 #endif
00697 }
00698 #endif
00699
00732 void NutInit(void)
00733 {
00734
00735
00736
00737
00738 #ifdef NUTDEBUG
00739
00740 outp(BV(RXEN) | BV(TXEN), UCR);
00741 #endif
00742
00743 #ifndef __GNUC__
00744 NutCustomInit();
00745
00746
00747
00748
00749 SP = (uint16_t)(NUTMEM_END);
00750
00751
00752
00753 NutInitHeap();
00754 #endif
00755
00756
00757 NutLoadConfig();
00758
00759
00760
00761 NutThreadCreate("idle", NutIdle, 0,
00762 (NUT_THREAD_IDLESTACK * NUT_THREAD_STACK_MULT) + NUT_THREAD_STACK_ADD);
00763 }
00764