atom.h

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00001 /*
00002  * Copyright (C) 2001-2009 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: atom.h,v $
00036  *
00037  */
00038 
00039 /*
00040     WHEN CHANGING PLEASE NOTICE:
00041     Errata 41.5.5.5 reads:
00042     "Need two NOPs instruction after instructions masking interrupts
00043     The instructions following in the pipeline the instruction masking the interrupt through SR
00044     may behave abnormally.
00045     Fix/Workaround
00046     Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR."
00047 */
00048 
00049 #ifndef _SYS_ATOM_H_
00050 #error "Do not include this file directly. Use sys/atom.h instead!"
00051 #endif
00052 
00053 #if (__GNUC__ && __AVR32__)
00054 
00055 #include <avr32/io.h>
00056 
00057 #if defined(NUT_CRITICAL_NESTING)
00058 
00059 #if defined(NUT_CRITICAL_NESTING_STACK)
00060 
00061 // This doesn't work right now. Not sure how to fix yet.
00062 // but this is unreacheable since critical neasting can't be enabled in the configurator
00063 // for AVR32
00064 #error Not Working
00065 #define NutEnterCritical()               \
00066 {                                        \
00067     register int temp_;                  \
00068     __asm__ volatile (                       \
00069     "mfsr    r10, %[SR]"                "\n\t" \
00070     "pushm   r10"     "\n\t"        \
00071     "ssrf    %[SR_GM_OFFSET]"     "\n\t"        \
00072     : [temp] "=r" (temp_) \
00073     : [SR] "i" (AVR32_SR), \
00074       [SR_GM_OFFSET] "i" (AVR32_SR_GM_OFFSET) \
00075     : "memory", "cc", "r10"); \
00076 }
00077 
00078 #define NutExitCritical() \
00079 { \
00080     register int temp_; \
00081     __asm__ volatile (             \
00082     "popm    r10"                                     "\n\t" \
00083     "andl    r10, LO(%[SR_GM_MASK])"               "\n\t" \
00084     "andh    r10, HI(%[SR_GM_MASK])"               "\n\t" \
00085     "cp.w    r10, 0"                               "\n\t" \
00086     "breq   LABEL_INT_SKIP_ENABLE_INTERRUPTS_%[LINE]" "\n\t" \
00087     "csrf   %[SR_GM_OFFSET]"                          "\n\t" \
00088     "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"            "\n\t" \
00089     : [temp] "=r" (temp_)                                    \
00090     : [SR_GM_OFFSET] "i" (AVR32_SR_GM_OFFSET),               \
00091       [SR_GM_MASK]   "i" (AVR32_SR_GM_MASK),                 \
00092       [LINE] "i" (__LINE__)                                  \
00093     : "memory", "cc", "r10");                                \
00094 }
00095 
00096 #else /* NUT_CRITICAL_NESTING_STACK */
00097 
00098 // If we ever enable critical nesting, implement me.
00099 #error Not implemented
00100 extern unsigned int critical_nesting_level;
00101 
00102 #define NutEnterCritical()
00103 
00104 #define NutExitCritical()
00105 
00106 #endif /* NUT_CRITICAL_NESTING_STACK */
00107 
00108 #else /* NUT_CRITICAL_NESTING */
00109 
00110 #define NutEnterCritical() \
00111 {                                 \
00112     __asm__ __volatile__ (        \
00113     "ssrf\t%0"      "\n\t"        \
00114     "nop"           "\n\t"        \
00115     "nop"           "\n\t"        \
00116     :: "i" (AVR32_SR_GM_OFFSET)   \
00117     : "memory");                  \
00118 }
00119 
00120 #define NutExitCritical()         \
00121 {                                 \
00122     __asm__ __volatile__ (        \
00123     "csrf\t%0"      "\n\t"        \
00124     :: "i" (AVR32_SR_GM_OFFSET)   \
00125     : "memory");                  \
00126 }
00127 
00128 #endif /* NUT_CRITICAL_NESTING */
00129 
00130 #define NutJumpOutCritical()    NutExitCritical()
00131 
00132 #endif

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