Watchdog Registers
Watchdog timer registers.
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Watch Dog Control Register |
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#define | WDT_CR_OFF 0x00000000 |
| Watchdog control register offset.
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#define | WDT_CR (WDT_BASE + WDT_CR_OFF) |
| Watchdog control register address.
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#define | WDT_WDRSTT 0x00000001 |
| Watchdog restart.
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#define | WDT_KEY 0xA5000000 |
| Watchdog password.
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Watch Dog Mode Register |
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#define | WDT_MR_OFF 0x00000004 |
| Mode register offset.
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#define | WDT_MR (WDT_BASE + WDT_MR_OFF) |
| Mode register address.
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#define | WDT_WDV 0x00000FFF |
| Counter value mask.
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#define | WDT_WDV_LSB 0 |
| Counter value LSB.
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#define | WDT_WDFIEN 0x00001000 |
| Fault interrupt enable.
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#define | WDT_WDRSTEN 0x00002000 |
| Reset enable.
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#define | WDT_WDRPROC 0x00004000 |
| Eset processor enable.
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#define | WDT_WDDIS 0x00008000 |
| Watchdog disable.
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#define | WDT_WDD 0x0FFF0000 |
| Delta value mask.
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#define | WDT_WDD_LSB 16 |
| Delta value LSB.
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#define | WDT_WDDBGHLT 0x10000000 |
| Watchdog debug halt.
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#define | WDT_WDIDLEHLT 0x20000000 |
| Watchdog idle halt.
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Watch Dog Status Register |
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#define | WDT_SR_OFF 0x00000008 |
| Status register offset.
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#define | WDT_SR (WDT_BASE + WDT_SR_OFF) |
| Status register address.
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#define | WDT_WDUNF 0x00000001 |
| Watchdog underflow.
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#define | WDT_WDERR 0x00000002 |
| Watchdog error.
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Detailed Description
Watchdog timer registers.
The Watch Dog is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt.
Define Documentation
#define WDT_CR_OFF 0x00000000 |
Watchdog control register offset.
Definition at line 66 of file at91_wdt.h.
#define WDT_CR (WDT_BASE + WDT_CR_OFF) |
Watchdog control register address.
Definition at line 67 of file at91_wdt.h.
#define WDT_WDRSTT 0x00000001 |
#define WDT_KEY 0xA5000000 |
Watchdog password.
Definition at line 69 of file at91_wdt.h.
#define WDT_MR_OFF 0x00000004 |
Mode register offset.
Definition at line 74 of file at91_wdt.h.
#define WDT_MR (WDT_BASE + WDT_MR_OFF) |
Mode register address.
Definition at line 75 of file at91_wdt.h.
#define WDT_WDV 0x00000FFF |
Counter value mask.
Definition at line 76 of file at91_wdt.h.
Counter value LSB.
Definition at line 77 of file at91_wdt.h.
#define WDT_WDFIEN 0x00001000 |
Fault interrupt enable.
Definition at line 78 of file at91_wdt.h.
#define WDT_WDRSTEN 0x00002000 |
#define WDT_WDRPROC 0x00004000 |
Eset processor enable.
Definition at line 80 of file at91_wdt.h.
#define WDT_WDDIS 0x00008000 |
#define WDT_WDD 0x0FFF0000 |
#define WDT_WDDBGHLT 0x10000000 |
Watchdog debug halt.
Definition at line 84 of file at91_wdt.h.
#define WDT_WDIDLEHLT 0x20000000 |
Watchdog idle halt.
Definition at line 85 of file at91_wdt.h.
#define WDT_SR_OFF 0x00000008 |
Status register offset.
Definition at line 90 of file at91_wdt.h.
#define WDT_SR (WDT_BASE + WDT_SR_OFF) |
Status register address.
Definition at line 91 of file at91_wdt.h.
#define WDT_WDUNF 0x00000001 |
Watchdog underflow.
Definition at line 92 of file at91_wdt.h.
#define WDT_WDERR 0x00000002 |