at91_tc.h

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00001 #ifndef _ARCH_ARM_AT91_TC_H_
00002 #define _ARCH_ARM_AT91_TC_H_
00003 
00004 /*
00005  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00024  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00054 
00057 #define TC0_CCR         (TC_BASE + 0x00)        
00058 #define TC1_CCR         (TC_BASE + 0x40)        
00059 #define TC2_CCR         (TC_BASE + 0x80)        
00060 #define TC_CLKEN                0x00000001      
00061 #define TC_CLKDIS               0x00000002      
00062 #define TC_SWTRG                0x00000004      
00064 
00065 
00067 #define TC0_CMR         (TC_BASE + 0x04)        
00068 #define TC1_CMR         (TC_BASE + 0x44)        
00069 #define TC2_CMR         (TC_BASE + 0x84)        
00071 #define TC_CLKS                 0x00000007      
00072 #define TC_CLKS_MCK2            0x00000000      
00073 #define TC_CLKS_MCK8            0x00000001      
00074 #define TC_CLKS_MCK32           0x00000002      
00075 #define TC_CLKS_MCK128          0x00000003      
00076 #define TC_CLKS_MCK1024         0x00000004      
00077 #define TC_CLKS_XC0             0x00000005      
00078 #define TC_CLKS_XC1             0x00000006      
00079 #define TC_CLKS_XC2             0x00000007      
00081 #define TC_CLKI                 0x00000008      
00083 #define TC_BURST                0x00000030      
00084 #define TC_BURST_NONE           0x00000000      
00085 #define TC_BUSRT_XC0            0x00000010      
00086 #define TC_BURST_XC1            0x00000020      
00087 #define TC_BURST_XC2            0x00000030      
00089 #define TC_CPCTRG               0x00004000      
00091 #define TC_WAVE                 0x00008000      
00092 #define TC_CAPT                 0x00000000      
00094 
00095 
00097 #define TC_LDBSTOP              0x00000040      
00098 #define TC_LDBDIS               0x00000080      
00100 #define TC_ETRGEDG              0x00000300      
00101 #define TC_ETRGEDG_RISING_EDGE  0x00000100      
00102 #define TC_ETRGEDG_FALLING_EDGE 0x00000200      
00103 #define TC_ETRGEDG_BOTH_EDGE    0x00000300      
00105 #define TC_ABETRG               0x00000400      
00106 #define TC_ABETRG_TIOB          0x00000000      
00107 #define TC_ABETRG_TIOA          0x00000400      
00109 #define TC_LDRA                 0x00030000      
00110 #define TC_LDRA_RISING_EDGE     0x00010000      
00111 #define TC_LDRA_FALLING_EDGE    0x00020000      
00112 #define TC_LDRA_BOTH_EDGE       0x00030000      
00114 #define TC_LDRB                 0x000C0000      
00115 #define TC_LDRB_RISING_EDGE     0x00040000      
00116 #define TC_LDRB_FALLING_EDGE    0x00080000      
00117 #define TC_LDRB_BOTH_EDGE       0x000C0000      
00120 
00121 
00123 #define TC_CPCSTOP              0x00000040      
00124 #define TC_CPCDIS               0x00000080      
00126 #define TC_EEVTEDG              0x00000300      
00127 #define TC_EEVTEDG_RISING_EDGE  0x00000100      
00128 #define TC_EEVTEDG_FALLING_EDGE 0x00000200      
00129 #define TC_EEVTEDG_BOTH_EDGE    0x00000300      
00131 #define TC_EEVT                 0x00000C00      
00132 #define TC_EEVT_TIOB            0x00000000      
00133 #define TC_EEVT_XC0             0x00000400      
00134 #define TC_EEVT_XC1             0x00000800      
00135 #define TC_EEVT_XC2             0x00000C00      
00137 #define TC_ENETRG               0x00001000      
00139 #define TC_ACPA                 0x00030000      
00140 #define TC_ACPA_SET_OUTPUT      0x00010000      
00141 #define TC_ACPA_CLEAR_OUTPUT    0x00020000      
00142 #define TC_ACPA_TOGGLE_OUTPUT   0x00030000      
00144 #define TC_ACPC                 0x000C0000      
00145 #define TC_ACPC_SET_OUTPUT      0x00040000      
00146 #define TC_ACPC_CLEAR_OUTPUT    0x00080000      
00147 #define TC_ACPC_TOGGLE_OUTPUT   0x000C0000      
00149 #define TC_AEEVT                0x00300000      
00150 #define TC_AEEVT_SET_OUTPUT     0x00100000      
00151 #define TC_AEEVT_CLEAR_OUTPUT   0x00200000      
00152 #define TC_AEEVT_TOGGLE_OUTPUT  0x00300000      
00154 #define TC_ASWTRG               0x00C00000      
00155 #define TC_ASWTRG_SET_OUTPUT    0x00400000      
00156 #define TC_ASWTRG_CLEAR_OUTPUT  0x00800000      
00157 #define TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000      
00159 #define TC_BCPB                 0x03000000      
00160 #define TC_BCPB_SET_OUTPUT      0x01000000      
00161 #define TC_BCPB_CLEAR_OUTPUT    0x02000000      
00162 #define TC_BCPB_TOGGLE_OUTPUT   0x03000000      
00164 #define TC_BCPC                 0x0C000000      
00165 #define TC_BCPC_SET_OUTPUT      0x04000000      
00166 #define TC_BCPC_CLEAR_OUTPUT    0x08000000      
00167 #define TC_BCPC_TOGGLE_OUTPUT   0x0C000000      
00169 #define TC_BEEVT                0x30000000      
00170 #define TC_BEEVT_SET_OUTPUT     0x10000000      
00171 #define TC_BEEVT_CLEAR_OUTPUT   0x20000000      
00172 #define TC_BEEVT_TOGGLE_OUTPUT  0x30000000      
00174 #define TC_BSWTRG               0xC0000000      
00175 #define TC_BSWTRG_SET_OUTPUT    0x40000000      
00176 #define TC_BSWTRG_CLEAR_OUTPUT  0x80000000      
00177 #define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000      
00179 
00180 
00182 #define TC0_CV          (TC_BASE + 0x10)        
00183 #define TC1_CV          (TC_BASE + 0x50)        
00184 #define TC2_CV          (TC_BASE + 0x90)        
00186 
00187 
00189 #define TC0_RA          (TC_BASE + 0x14)        
00190 #define TC1_RA          (TC_BASE + 0x54)        
00191 #define TC2_RA          (TC_BASE + 0x94)        
00193 
00194 
00196 #define TC0_RB          (TC_BASE + 0x18)        
00197 #define TC1_RB          (TC_BASE + 0x58)        
00198 #define TC2_RB          (TC_BASE + 0x98)        
00200 
00201 
00203 #define TC0_RC          (TC_BASE + 0x1C)        
00204 #define TC1_RC          (TC_BASE + 0x5C)        
00205 #define TC2_RC          (TC_BASE + 0x9C)        
00207 
00208 
00211 #define TC0_SR          (TC_BASE + 0x20)        
00212 #define TC1_SR          (TC_BASE + 0x60)        
00213 #define TC2_SR          (TC_BASE + 0xA0)        
00215 #define TC0_IER         (TC_BASE + 0x24)        
00216 #define TC1_IER         (TC_BASE + 0x64)        
00217 #define TC2_IER         (TC_BASE + 0xA4)        
00219 #define TC0_IDR         (TC_BASE + 0x28)        
00220 #define TC1_IDR         (TC_BASE + 0x68)        
00221 #define TC2_IDR         (TC_BASE + 0xA8)        
00223 #define TC0_IMR         (TC_BASE + 0x2C)        
00224 #define TC1_IMR         (TC_BASE + 0x6C)        
00225 #define TC2_IMR         (TC_BASE + 0xAC)        
00227 #define TC_COVFS                0x00000001      
00228 #define TC_LOVRS                0x00000002      
00229 #define TC_CPAS                 0x00000004      
00230 #define TC_CPBS                 0x00000008      
00231 #define TC_CPCS                 0x00000010      
00232 #define TC_LDRAS                0x00000020      
00233 #define TC_LDRBS                0x00000040      
00234 #define TC_ETRGS                0x00000080      
00235 #define TC_CLKSTA               0x00010000      
00236 #define TC_MTIOA                0x00020000      
00237 #define TC_MTIOB                0x00040000      
00239 
00240 
00242 #define TC_BCR          (TC_BASE + 0xC0)        
00243 #define TC_SYNC                 0x00000001      
00245 
00246 
00248 #define TC_BMR          (TC_BASE + 0xC4)        
00249 #define TC_TC0XC0S              0x00000003      
00250 #define TC_TCLK0XC0             0x00000000      
00251 #define TC_NONEXC0              0x00000001      
00252 #define TC_TIOA1XC0             0x00000002      
00253 #define TC_TIOA2XC0             0x00000003      
00255 #define TC_TC1XC1S              0x0000000C      
00256 #define TC_TCLK1XC1             0x00000000      
00257 #define TC_NONEXC1              0x00000004      
00258 #define TC_TIOA0XC1             0x00000008      
00259 #define TC_TIOA2XC1             0x0000000C      
00261 #define TC_TC2XC2S              0x00000030      
00262 #define TC_TCLK2XC2             0x00000000      
00263 #define TC_NONEXC2              0x00000010      
00264 #define TC_TIOA0XC2             0x00000020      
00265 #define TC_TIOA1XC2             0x00000030      
00267 
00268 
00270 #endif                          /* _ARCH_ARM_AT91_TC_H_ */

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