at91sam9g45.h File Reference

AT91SAM9G45 peripherals. More...

Go to the source code of this file.

Defines

#define FLASH_BASE   0x100000UL
#define RAM_BASE   0x200000UL
#define NAND_FLASH_BASE   0x40000000
#define LCDC_BASE   0x00500000
 USB device port base address.
#define UDP_BASE   0xFFF78000
 USB device port base address.
#define TC_BASE   0xFFF7C000
 Timer/counter base address. (TC0-TC2).
#define MCI_BASE   0xFFF80000
 MMC/SDCard interface base address. (MCI0).
#define TWI_BASE   0xFFF84000
 Two-wire interface base address. (TWI0-TWI1).
#define USART0_BASE   0xFFF8C000
 USART 0 base address.
#define USART1_BASE   0xFFF90000
 USART 1 base address.
#define USART2_BASE   0xFFF94000
 USART 2 base address.
#define USART3_BASE   0xFFF98000
 USART 2 base address.
#define SSC_BASE   0xFFF9C000
 Serial synchronous controller base address. (SSC0-SSC1).
#define SPI0_BASE   0xFFFA4000
 SPI0 0 base address.
#define SPI1_BASE   0xFFFA8000
 SPI0 1 base address.
#define AC97_BASE   0xFFFAC000
 AC97 Codec interface.
#define TSADCC_BASE   0xFFFB0000
 Touch screen ADC controller.
#define ISI_BASE   0xFFFB4000
 Image sensor interface base address.
#define PWMC_BASE   0xFFFB8000
 PWM controller base address.
#define EMAC_BASE   0xFFFBC000
 EMAC base address.
#define TRNG_BASE   0xFFFCC000
 True random number generator.
#define MCI1_BASE   0xFFFD0000
 MMC/SDCard interface base address. (MCI1).
#define TC345_BASE   0xFFFD4000
 Timer/counter base address. (TC3-TC5).
#define DDRSDRC1_BASE   0xFFFFE400
 DDRSDRC1 base address.
#define DDRSDRC0_BASE   0xFFFFE600
 DDRSDRC0 base address.
#define SMC_BASE   0xFFFFE800
 SMC base address.
#define MATRIX_BASE   0xFFFFEA00
 MATRIX base address.
#define DMAC_BASE   0xFFFFEC00
 DMA controller base address.
#define DBGU_BASE   0xFFFFEE00
 DBGU base address.
#define AIC_BASE   0xFFFFF000
 AIC base address.
#define PIOA_BASE   0xFFFFF200
 PIO A base address.
#define PIOB_BASE   0xFFFFF400
 PIO B base address.
#define PIOC_BASE   0xFFFFF600
 PIO C base address.
#define PIOD_BASE   0xFFFFF800
 PIO D base address.
#define PIOE_BASE   0xFFFFFA00
 PIO E base address.
#define PMC_BASE   0xFFFFFC00
 PMC base address.
#define RSTC_BASE   0xFFFFFD00
 Resect controller register base address.
#define SHDWC_BASE   0xFFFFFD10
 Shutdown controller.
#define RTT_BASE   0xFFFFFD20
 Realtime timer base address.
#define PIT_BASE   0xFFFFFD30
 Periodic interval timer base address.
#define WDT_BASE   0xFFFFFD40
 Watch Dog register base address.
#define SCKCR_BASE   0xFFFFFD50
 Slow clock control register.
#define GPBR_BASE   0xFFFFFD60
 General purpose backup registers.
#define RTC_BASE   0xFFFFFDB0
 RTC.
#define ECC_BASE   0xFFFFE200
 ECC base address.
#define PERIPH_RPR_OFF   0x00000100
 Receive pointer register offset.
#define PERIPH_RCR_OFF   0x00000104
 Receive counter register offset.
#define PERIPH_TPR_OFF   0x00000108
 Transmit pointer register offset.
#define PERIPH_TCR_OFF   0x0000010C
 Transmit counter register offset.
#define PERIPH_RNPR_OFF   0x00000110
 Receive next pointer register offset.
#define PERIPH_RNCR_OFF   0x00000114
 Receive next counter register offset.
#define PERIPH_TNPR_OFF   0x00000118
 Transmit next pointer register offset.
#define PERIPH_TNCR_OFF   0x0000011C
 Transmit next counter register offset.
#define PERIPH_PTCR_OFF   0x00000120
 PDC transfer control register offset.
#define PERIPH_PTSR_OFF   0x00000124
 PDC transfer status register offset.
#define PDC_RXTEN   0x00000001
 Receiver transfer enable.
#define PDC_RXTDIS   0x00000002
 Receiver transfer disable.
#define PDC_TXTEN   0x00000100
 Transmitter transfer enable.
#define PDC_TXTDIS   0x00000200
 Transmitter transfer disable.
#define DBGU_HAS_PDC
#define SPI_HAS_PDC
#define SSC_HAS_PDC
#define USART_HAS_PDC
#define USART_HAS_MODE
#define MCI_HAS_PDC
#define PMC_HAS_PLLB
#define PMC_HAS_MDIV
#define EBI_HAS_CSA
#define PIO_HAS_MULTIDRIVER
#define PIO_HAS_PULLUP
#define PIO_HAS_PERIPHERALSELECT
#define PIO_HAS_OUTPUTWRITEENABLE
#define SPI1_CS3_PIO_BASE   PIOD_BASE
#define SPI1_CS3_PSR_OFF   PIO_ASR_OFF
#define PB20_ISI_D0_A   20
#define PB21_ISI_D1_A   21
#define PB22_ISI_D2_A   22
#define PB23_ISI_D3_A   23
#define PB24_ISI_D4_A   24
#define PB25_ISI_D5_A   25
#define PB26_ISI_D6_A   26
#define PB27_ISI_D7_A   27
#define PB10_ISI_D8_B   10
#define PB11_ISI_D9_B   11
#define PB12_ISI_D10_B   12
#define PB13_ISI_D11_B   13
#define PB28_ISI_PCK_A   28
#define PB29_ISI_VSYNC_A   29
#define PB30_ISI_HSYNC_A   30
#define PB31_ISI_MCK_A   31
#define PA6_ETX2_B   6
#define PA7_ETX3_B   7
#define PA10_ETX0_A   10
#define PA11_ETX1_A   11
#define PA12_ERX0_A   12
#define PA13_ERX1_A   13
#define PA14_ETXEN_A   14
#define PA15_ERXDV_A   15
#define PA16_ERXER_A   16
#define PA17_ETXCK_A   17
#define PA18_EMDC_A   18
#define PA19_EMDIO_A   19
#define PA27_ETXER_B   27
#define PA8_ERX2_B   8
#define PA9_ERX3_B   9
#define PA28_ERXCK_B   28
#define PA29_ECRS_B   29
#define PA30_ECOL_B   30
#define PHY_MODE_RMII
#define EMAC_PIO_ASR   PIO_ASR_OFF
#define PHY_MII_PINS_A
#define EMAC_PIO_BSR   PIO_BSR_OFF
#define PHY_MII_PINS_B   (PA6_ETX2_B | PA7_ETX3_B | PA27_ETXER_B | PA8_ERX2_B | PA9_ERX3_B | PA28_ERXCK_B | PA29_ECRS_B | PA30_ECOL_B)
#define EMAC_PIO_PDR   PIOA_PDR
#define PD28_ADTRG_A   28
#define PB12_DRXD_A   12
#define PB13_DTXD_A   13
#define PD2_TD0_A   2
#define PD3_RD0_A   3
#define PD0_TK0_A   0
#define PD4_RK0_A   4
#define PD1_TF0_A   1
#define PD5_RF0_A   5
#define PA20_TWD0_A   20
#define PA21_TWCK0_A   21
#define PB10_TWD1_A   10
#define PB11_TWCK1_A   11
#define PD23_TCLK0_A   23
#define PD20_TIOA0_A   20
#define PD30_TIOB0_A   30
#define PD29_TCLK1_A   29
#define PD21_TIOA1_A   21
#define PD31_TIOB1_A   31
#define PC10_TCLK2_B   10
#define PD22_TIOA2_A   22
#define PA26_TIOB2_B   26
#define PA0_TCLK3_B   0
#define PA1_TIOA3_B   1
#define PA2_TIOB3_B   2
#define PA3_TCLK4_B   3
#define PA4_TIOA4_B   4
#define PA5_TIOB4_B   5
#define PD9_TCLK5_B   9
#define PD7_TIOA5_B   7
#define PD8_TIOB5_B   8
#define PD26_PCK0_A   26
#define PE0_PCK0_B   0
#define PD27_PCK1_A   27
#define PE31_PCK1_B   31
#define PC12_A25_CFRNW_A   12
#define PC10_NCS4_CFCS0_A   10
#define PC11_NCS5_CFCS1_A   11
#define PC8_CFCE1_A   8
#define PC9_CFCE2_A   9
#define PC16_D16_A   16
#define PC17_D17_A   17
#define PC18_D18_A   18
#define PC19_D19_A   19
#define PC20_D20_A   20
#define PC21_D21_A   21
#define PC22_D22_A   22
#define PC23_D23_A   23
#define PC24_D24_A   24
#define PC25_D25_A   25
#define PC26_D26_A   26
#define PC27_D27_A   27
#define PC28_D28_A   28
#define PC29_D29_A   29
#define PC30_D30_A   30
#define PC31_D31_A   31
#define PC6_A23_A   6
#define PC7_A24_A   7
#define PC13_NCS2_A   13
#define PC14_NCS3_NANDCS_A   14
#define PC15_NWAIT_A   15
#define PD19_FIQ_B   19
#define PC18_IRQ_B   18
#define LCDC_PIO_BASE   PIOE_BASE
#define LCDC_PINS_A   0x6FEFFFDE
#define LCDC_PINS_B   0x10100000
#define LCDC_PINS   (LCDC_PINS_A | LCDC_PINS_B)
#define LCDC_PIO_ASR   PIOE_ASR
#define LCDC_PIO_BSR   PIOE_BSR
#define LCDC_PIO_PDR   PIOE_PDR

Peripheral Identifiers and Interrupts



#define FIQ_ID   0
 Fast interrupt.
#define SYSC_ID   1
 System interrupt.
#define PIOA_ID   2
 Parallel I/O controller A.
#define PIOB_ID   3
 Parallel I/O controller B.
#define PIOC_ID   4
 Parallel I/O controller C.
#define PIODE_ID   5
 Parallel I/O controller C.
#define RNG_ID   6
 Analog to digital converter.
#define US0_ID   7
 USART 0.
#define US1_ID   8
 USART 1.
#define US2_ID   9
 USART 2.
#define US3_ID   10
 USART 3.
#define MCI0_ID   11
 MMC interface.
#define TWI0_ID   12
 Two wire interface.
#define TWI1_ID   13
 Two wire interface.
#define SPI0_ID   14
 Serial peripheral 0.
#define SPI1_ID   15
 Serial peripheral 1.
#define SSC0_ID   16
 Serial peripheral interface.
#define SSC1_ID   17
 Serial peripheral interface.
#define TC0_ID   18
 Timer/counter 0.
#define TC1_ID   18
 Timer/counter 1.
#define TC2_ID   18
 Timer/counter 2.
#define TC3_ID   18
 Timer/counter 3.
#define TC4_ID   18
 Timer/counter 4.
#define TC5_ID   18
 Timer/counter 5.
#define PWMC_ID   19
 Pulse Width Modulation Controller.
#define TSADCC_ID   20
 Touch Screen ADC Controller.
#define DMA_ID   21
 DMA Controller.
#define UHP_ID   22
 USB host port.
#define LCDC_ID   23
 LCD controller.
#define AC97_ID   24
 AC97 controller.
#define EMAC_ID   25
 Ethernet MAC.
#define ISI_ID   26
 Image sensor interface.
#define UDP_ID   27
 USB device port.
#define MCI1_ID   29
 MMC interface.
#define IRQ0_ID   31
 External interrupt 0.
#define TWI_ID   TWI0_ID
 Two wire interface.
#define MCI_ID   MCI0_ID
 MMC interface.
#define SSC_ID   SSC0_ID
 Serial peripheral interface.

USART Peripheral Multiplexing



#define PB16_SCK0_B   16
 Channel 0 serial clock pin.
#define PB19_TXD0_A   19
 Channel 0 transmit data pin.
#define PB18_RXD0_A   18
 Channel 0 receive data pin.
#define PB15_CTS0_B   15
 Channel 0 clear to send pin.
#define PB17_RTS0_B   17
 Channel 0 request to send pin.
#define PD29_SCK1_B   29
 Channel 1 serial clock pin.
#define PB4_TXD1_A   4
 Channel 1 transmit data pin.
#define PB5_RXD1_A   5
 Channel 1 receive data pin.
#define PD17_CTS1_A   17
 Channel 1 clear to send pin.
#define PD16_RTS1_A   16
 Channel 1 request to send pin.
#define PD30_SCK2_B   30
 Channel 2 serial clock pin.
#define PB6_TXD2_A   6
 Channel 2 transmit data pin.
#define PB7_RXD2_A   7
 Channel 2 receive data pin.
#define PC11_CTS2_B   11
 Channel 2 clear to send pin.
#define PC9_RTS2_B   9
 Channel 2 request to send pin.
#define PA22_SCK3_B   22
 Channel 3 serial clock pin.
#define PB8_TXD3_A   8
 Channel 3 transmit data pin.
#define PB9_RXD3_A   9
 Channel 3 receive data pin.
#define PA24_CTS3_B   24
 Channel 3 clear to send pin.
#define PA23_RTS3_B   23
 Channel 3 request to send pin.

SPI Peripheral Multiplexing



#define PB0_SPI0_MISO_A   0
 Channel 0 master input slave output pin.
#define PB1_SPI0_MOSI_A   1
 Channel 0 master output slave input pin.
#define PB2_SPI0_SPCK_A   2
 Channel 0 serial clock pin.
#define PB3_SPI0_NPCS0_A   3
 Channel 0 chip select 0 pin.
#define PB18_SPI0_NPCS1_B   18
 Channel 0 chip select 1 pin.
#define PD24_SPI0_NPCS1_A   24
 Channel 0 chip select 1 pin.
#define PB19_SPI0_NPCS2_B   19
 Channel 0 chip select 2 pin.
#define PD25_SPI0_NPCS2_A   25
 Channel 0 chip select 1 pin.
#define PD27_SPI0_NPCS3_B   27
 Channel 0 chip select 3 pin.
#define SPI0_PINS   _BV(PB0_SPI0_MISO_A) | _BV(PB1_SPI0_MOSI_A) | _BV(PB2_SPI0_SPCK_A)
#define SPI0_PIO_BASE   PIOA_BASE
#define SPI0_PSR_OFF   PIO_ASR_OFF
#define SPI0_CS0_PIN   _BV(PB3_SPI0_NPCS0_A)
#define SPI0_CS0_PIO_BASE   PIOB_BASE
#define SPI0_CS0_PSR_OFF   PIO_ASR_OFF
#define SPI0_CS1_PIN   _BV(PB18_SPI0_NPCS1_B)
#define SPI0_CS1_PIO_BASE   PIOB_BASE
#define SPI0_CS1_PSR_OFF   PIO_BSR_OFF
#define PB14_SPI1_MISO_A   14
 Channel 1 master input slave output pin.
#define PB15_SPI1_MOSI_A   15
 Channel 1 master output slave input pin.
#define PB16_SPI1_SPCK_A   16
 Channel 1 serial clock pin.
#define PB17_SPI1_NPCS0_A   17
 Channel 1 chip select 0 pin.
#define PD28_SPI1_NPCS1_B   28
 Channel 1 chip select 1 pin.
#define PD18_SPI1_NPCS2_A   18
 Channel 1 chip select 2 pin.
#define PD19_SPI1_NPCS3_A   19
 Channel 1 chip select 3 pin.
#define SPI1_PINS   _BV(PB14_SPI1_MISO_A) | _BV(PB15_SPI1_MOSI_A) | _BV(PB16_SPI1_SPCK_A)
#define SPI1_PIO_BASE   PIOB_BASE
#define SPI1_PSR_OFF   PIO_ASR_OFF
#define SPI1_CS0_PIN   _BV(PB17_SPI1_NPCS0_A)
#define SPI1_CS0_PIO_BASE   PIOB_BASE
#define SPI1_CS0_PSR_OFF   PIO_ASR_OFF

Detailed Description

AT91SAM9G45 peripherals.

Definition in file at91sam9g45.h.


Define Documentation

#define FLASH_BASE   0x100000UL

Definition at line 49 of file at91sam9g45.h.

#define RAM_BASE   0x200000UL

Definition at line 50 of file at91sam9g45.h.

#define NAND_FLASH_BASE   0x40000000

Definition at line 51 of file at91sam9g45.h.

#define LCDC_BASE   0x00500000

USB device port base address.

Definition at line 54 of file at91sam9g45.h.

#define UDP_BASE   0xFFF78000

USB device port base address.

Definition at line 56 of file at91sam9g45.h.

#define TC_BASE   0xFFF7C000

Timer/counter base address. (TC0-TC2).

Definition at line 57 of file at91sam9g45.h.

#define MCI_BASE   0xFFF80000

MMC/SDCard interface base address. (MCI0).

Definition at line 58 of file at91sam9g45.h.

#define TWI_BASE   0xFFF84000

Two-wire interface base address. (TWI0-TWI1).

Definition at line 59 of file at91sam9g45.h.

#define USART0_BASE   0xFFF8C000

USART 0 base address.

Definition at line 60 of file at91sam9g45.h.

#define USART1_BASE   0xFFF90000

USART 1 base address.

Definition at line 61 of file at91sam9g45.h.

#define USART2_BASE   0xFFF94000

USART 2 base address.

Definition at line 62 of file at91sam9g45.h.

#define USART3_BASE   0xFFF98000

USART 2 base address.

Definition at line 63 of file at91sam9g45.h.

#define SSC_BASE   0xFFF9C000

Serial synchronous controller base address. (SSC0-SSC1).

Definition at line 64 of file at91sam9g45.h.

#define SPI0_BASE   0xFFFA4000

SPI0 0 base address.

Definition at line 65 of file at91sam9g45.h.

#define SPI1_BASE   0xFFFA8000

SPI0 1 base address.

Definition at line 66 of file at91sam9g45.h.

#define AC97_BASE   0xFFFAC000

AC97 Codec interface.

Definition at line 67 of file at91sam9g45.h.

#define TSADCC_BASE   0xFFFB0000

Touch screen ADC controller.

Definition at line 68 of file at91sam9g45.h.

#define ISI_BASE   0xFFFB4000

Image sensor interface base address.

Definition at line 69 of file at91sam9g45.h.

#define PWMC_BASE   0xFFFB8000

PWM controller base address.

Definition at line 70 of file at91sam9g45.h.

#define EMAC_BASE   0xFFFBC000

EMAC base address.

Definition at line 71 of file at91sam9g45.h.

#define TRNG_BASE   0xFFFCC000

True random number generator.

Definition at line 72 of file at91sam9g45.h.

#define MCI1_BASE   0xFFFD0000

MMC/SDCard interface base address. (MCI1).

Definition at line 73 of file at91sam9g45.h.

#define TC345_BASE   0xFFFD4000

Timer/counter base address. (TC3-TC5).

Definition at line 74 of file at91sam9g45.h.

#define DDRSDRC1_BASE   0xFFFFE400

DDRSDRC1 base address.

Definition at line 77 of file at91sam9g45.h.

#define DDRSDRC0_BASE   0xFFFFE600

DDRSDRC0 base address.

Definition at line 78 of file at91sam9g45.h.

#define SMC_BASE   0xFFFFE800

SMC base address.

Definition at line 79 of file at91sam9g45.h.

#define MATRIX_BASE   0xFFFFEA00

MATRIX base address.

Definition at line 80 of file at91sam9g45.h.

#define DMAC_BASE   0xFFFFEC00

DMA controller base address.

Definition at line 81 of file at91sam9g45.h.

#define DBGU_BASE   0xFFFFEE00

DBGU base address.

Definition at line 82 of file at91sam9g45.h.

#define AIC_BASE   0xFFFFF000

AIC base address.

Definition at line 83 of file at91sam9g45.h.

#define PIOA_BASE   0xFFFFF200

PIO A base address.

Definition at line 84 of file at91sam9g45.h.

#define PIOB_BASE   0xFFFFF400

PIO B base address.

Definition at line 85 of file at91sam9g45.h.

#define PIOC_BASE   0xFFFFF600

PIO C base address.

Definition at line 86 of file at91sam9g45.h.

#define PIOD_BASE   0xFFFFF800

PIO D base address.

Definition at line 87 of file at91sam9g45.h.

#define PIOE_BASE   0xFFFFFA00

PIO E base address.

Definition at line 88 of file at91sam9g45.h.

#define PMC_BASE   0xFFFFFC00

PMC base address.

Definition at line 89 of file at91sam9g45.h.

#define RSTC_BASE   0xFFFFFD00

Resect controller register base address.

Definition at line 90 of file at91sam9g45.h.

#define SHDWC_BASE   0xFFFFFD10

Shutdown controller.

Definition at line 91 of file at91sam9g45.h.

#define RTT_BASE   0xFFFFFD20

Realtime timer base address.

Definition at line 92 of file at91sam9g45.h.

#define PIT_BASE   0xFFFFFD30

Periodic interval timer base address.

Definition at line 93 of file at91sam9g45.h.

#define WDT_BASE   0xFFFFFD40

Watch Dog register base address.

Definition at line 94 of file at91sam9g45.h.

#define SCKCR_BASE   0xFFFFFD50

Slow clock control register.

Definition at line 95 of file at91sam9g45.h.

#define GPBR_BASE   0xFFFFFD60

General purpose backup registers.

Definition at line 96 of file at91sam9g45.h.

#define RTC_BASE   0xFFFFFDB0

RTC.

Definition at line 97 of file at91sam9g45.h.

#define ECC_BASE   0xFFFFE200

ECC base address.

Definition at line 100 of file at91sam9g45.h.

#define PERIPH_RPR_OFF   0x00000100

Receive pointer register offset.

Definition at line 103 of file at91sam9g45.h.

#define PERIPH_RCR_OFF   0x00000104

Receive counter register offset.

Definition at line 104 of file at91sam9g45.h.

#define PERIPH_TPR_OFF   0x00000108

Transmit pointer register offset.

Definition at line 105 of file at91sam9g45.h.

#define PERIPH_TCR_OFF   0x0000010C

Transmit counter register offset.

Definition at line 106 of file at91sam9g45.h.

#define PERIPH_RNPR_OFF   0x00000110

Receive next pointer register offset.

Definition at line 107 of file at91sam9g45.h.

#define PERIPH_RNCR_OFF   0x00000114

Receive next counter register offset.

Definition at line 108 of file at91sam9g45.h.

#define PERIPH_TNPR_OFF   0x00000118

Transmit next pointer register offset.

Definition at line 109 of file at91sam9g45.h.

#define PERIPH_TNCR_OFF   0x0000011C

Transmit next counter register offset.

Definition at line 110 of file at91sam9g45.h.

#define PERIPH_PTCR_OFF   0x00000120

PDC transfer control register offset.

Definition at line 111 of file at91sam9g45.h.

#define PERIPH_PTSR_OFF   0x00000124

PDC transfer status register offset.

Definition at line 112 of file at91sam9g45.h.

#define PDC_RXTEN   0x00000001

Receiver transfer enable.

Definition at line 115 of file at91sam9g45.h.

#define PDC_RXTDIS   0x00000002

Receiver transfer disable.

Definition at line 116 of file at91sam9g45.h.

#define PDC_TXTEN   0x00000100

Transmitter transfer enable.

Definition at line 117 of file at91sam9g45.h.

#define PDC_TXTDIS   0x00000200

Transmitter transfer disable.

Definition at line 118 of file at91sam9g45.h.

#define DBGU_HAS_PDC

Definition at line 121 of file at91sam9g45.h.

#define SPI_HAS_PDC

Definition at line 122 of file at91sam9g45.h.

#define SSC_HAS_PDC

Definition at line 123 of file at91sam9g45.h.

#define USART_HAS_PDC

Definition at line 124 of file at91sam9g45.h.

#define USART_HAS_MODE

Definition at line 125 of file at91sam9g45.h.

#define MCI_HAS_PDC

Definition at line 126 of file at91sam9g45.h.

#define PMC_HAS_PLLB

Definition at line 127 of file at91sam9g45.h.

#define PMC_HAS_MDIV

Definition at line 128 of file at91sam9g45.h.

#define EBI_HAS_CSA

Definition at line 129 of file at91sam9g45.h.

#define PIO_HAS_MULTIDRIVER

Definition at line 132 of file at91sam9g45.h.

#define PIO_HAS_PULLUP

Definition at line 133 of file at91sam9g45.h.

#define PIO_HAS_PERIPHERALSELECT

Definition at line 134 of file at91sam9g45.h.

#define PIO_HAS_OUTPUTWRITEENABLE

Definition at line 135 of file at91sam9g45.h.

#define SPI1_CS3_PIO_BASE   PIOD_BASE
#define SPI1_CS3_PSR_OFF   PIO_ASR_OFF
#define PB20_ISI_D0_A   20
#define PB21_ISI_D1_A   21
#define PB22_ISI_D2_A   22
#define PB23_ISI_D3_A   23
#define PB24_ISI_D4_A   24
#define PB25_ISI_D5_A   25
#define PB26_ISI_D6_A   26
#define PB27_ISI_D7_A   27
#define PB10_ISI_D8_B   10
#define PB11_ISI_D9_B   11
#define PB12_ISI_D10_B   12
#define PB13_ISI_D11_B   13
#define PB28_ISI_PCK_A   28
#define PB29_ISI_VSYNC_A   29
#define PB30_ISI_HSYNC_A   30
#define PB31_ISI_MCK_A   31
#define PA6_ETX2_B   6
#define PA7_ETX3_B   7
#define PA10_ETX0_A   10
#define PA11_ETX1_A   11
#define PA12_ERX0_A   12
#define PA13_ERX1_A   13
#define PA14_ETXEN_A   14
#define PA15_ERXDV_A   15
#define PA16_ERXER_A   16
#define PA17_ETXCK_A   17
#define PA18_EMDC_A   18
#define PA19_EMDIO_A   19
#define PA27_ETXER_B   27
#define PA8_ERX2_B   8
#define PA9_ERX3_B   9
#define PA28_ERXCK_B   28
#define PA29_ECRS_B   29
#define PA30_ECOL_B   30
#define PHY_MODE_RMII
#define EMAC_PIO_ASR   PIO_ASR_OFF
#define PHY_MII_PINS_A
#define EMAC_PIO_BSR   PIO_BSR_OFF
#define PHY_MII_PINS_B   (PA6_ETX2_B | PA7_ETX3_B | PA27_ETXER_B | PA8_ERX2_B | PA9_ERX3_B | PA28_ERXCK_B | PA29_ECRS_B | PA30_ECOL_B)
#define EMAC_PIO_PDR   PIOA_PDR
#define PD28_ADTRG_A   28
#define PB12_DRXD_A   12
#define PB13_DTXD_A   13
#define PD2_TD0_A   2
#define PD3_RD0_A   3
#define PD0_TK0_A   0
#define PD4_RK0_A   4
#define PD1_TF0_A   1
#define PD5_RF0_A   5
#define PA20_TWD0_A   20
#define PA21_TWCK0_A   21
#define PB10_TWD1_A   10
#define PB11_TWCK1_A   11
#define PD23_TCLK0_A   23
#define PD20_TIOA0_A   20
#define PD30_TIOB0_A   30
#define PD29_TCLK1_A   29
#define PD21_TIOA1_A   21
#define PD31_TIOB1_A   31
#define PC10_TCLK2_B   10
#define PD22_TIOA2_A   22
#define PA26_TIOB2_B   26
#define PA0_TCLK3_B   0
#define PA1_TIOA3_B   1
#define PA2_TIOB3_B   2
#define PA3_TCLK4_B   3
#define PA4_TIOA4_B   4
#define PA5_TIOB4_B   5
#define PD9_TCLK5_B   9
#define PD7_TIOA5_B   7
#define PD8_TIOB5_B   8
#define PD26_PCK0_A   26
#define PE0_PCK0_B   0
#define PD27_PCK1_A   27
#define PE31_PCK1_B   31
#define PC12_A25_CFRNW_A   12
#define PC10_NCS4_CFCS0_A   10
#define PC11_NCS5_CFCS1_A   11
#define PC8_CFCE1_A   8
#define PC9_CFCE2_A   9
#define PC16_D16_A   16
#define PC17_D17_A   17
#define PC18_D18_A   18
#define PC19_D19_A   19
#define PC20_D20_A   20
#define PC21_D21_A   21
#define PC22_D22_A   22
#define PC23_D23_A   23
#define PC24_D24_A   24
#define PC25_D25_A   25
#define PC26_D26_A   26
#define PC27_D27_A   27
#define PC28_D28_A   28
#define PC29_D29_A   29
#define PC30_D30_A   30
#define PC31_D31_A   31
#define PC6_A23_A   6
#define PC7_A24_A   7
#define PC13_NCS2_A   13
#define PC14_NCS3_NANDCS_A   14
#define PC15_NWAIT_A   15
#define PD19_FIQ_B   19
#define PC18_IRQ_B   18
#define LCDC_PIO_BASE   PIOE_BASE
#define LCDC_PINS_A   0x6FEFFFDE
#define LCDC_PINS_B   0x10100000
#define LCDC_PINS   (LCDC_PINS_A | LCDC_PINS_B)
#define LCDC_PIO_ASR   PIOE_ASR
#define LCDC_PIO_BSR   PIOE_BSR
#define LCDC_PIO_PDR   PIOE_PDR

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