Peripheral Identifiers and Interrupts | |
| |
#define | FIQ_ID 0 |
Fast interrupt. | |
#define | SYSC_ID 1 |
System interrupt. | |
#define | PIOA_ID 2 |
Parallel I/O controller A. | |
#define | PIOB_ID 3 |
Parallel I/O controller B. | |
#define | PIOC_ID 4 |
Parallel I/O controller C. | |
#define | PIODE_ID 5 |
Parallel I/O controller C. | |
#define | RNG_ID 6 |
Analog to digital converter. | |
#define | US0_ID 7 |
USART 0. | |
#define | US1_ID 8 |
USART 1. | |
#define | US2_ID 9 |
USART 2. | |
#define | US3_ID 10 |
USART 3. | |
#define | MCI0_ID 11 |
MMC interface. | |
#define | TWI0_ID 12 |
Two wire interface. | |
#define | TWI1_ID 13 |
Two wire interface. | |
#define | SPI0_ID 14 |
Serial peripheral 0. | |
#define | SPI1_ID 15 |
Serial peripheral 1. | |
#define | SSC0_ID 16 |
Serial peripheral interface. | |
#define | SSC1_ID 17 |
Serial peripheral interface. | |
#define | TC0_ID 18 |
Timer/counter 0. | |
#define | TC1_ID 18 |
Timer/counter 1. | |
#define | TC2_ID 18 |
Timer/counter 2. | |
#define | TC3_ID 18 |
Timer/counter 3. | |
#define | TC4_ID 18 |
Timer/counter 4. | |
#define | TC5_ID 18 |
Timer/counter 5. | |
#define | PWMC_ID 19 |
Pulse Width Modulation Controller. | |
#define | TSADCC_ID 20 |
Touch Screen ADC Controller. | |
#define | DMA_ID 21 |
DMA Controller. | |
#define | UHP_ID 22 |
USB host port. | |
#define | LCDC_ID 23 |
LCD controller. | |
#define | AC97_ID 24 |
AC97 controller. | |
#define | EMAC_ID 25 |
Ethernet MAC. | |
#define | ISI_ID 26 |
Image sensor interface. | |
#define | UDP_ID 27 |
USB device port. | |
#define | MCI1_ID 29 |
MMC interface. | |
#define | IRQ0_ID 31 |
External interrupt 0. | |
#define | TWI_ID TWI0_ID |
Two wire interface. | |
#define | MCI_ID MCI0_ID |
MMC interface. | |
#define | SSC_ID SSC0_ID |
Serial peripheral interface. | |
USART Peripheral Multiplexing | |
| |
#define | PB16_SCK0_B 16 |
Channel 0 serial clock pin. | |
#define | PB19_TXD0_A 19 |
Channel 0 transmit data pin. | |
#define | PB18_RXD0_A 18 |
Channel 0 receive data pin. | |
#define | PB15_CTS0_B 15 |
Channel 0 clear to send pin. | |
#define | PB17_RTS0_B 17 |
Channel 0 request to send pin. | |
#define | PD29_SCK1_B 29 |
Channel 1 serial clock pin. | |
#define | PB4_TXD1_A 4 |
Channel 1 transmit data pin. | |
#define | PB5_RXD1_A 5 |
Channel 1 receive data pin. | |
#define | PD17_CTS1_A 17 |
Channel 1 clear to send pin. | |
#define | PD16_RTS1_A 16 |
Channel 1 request to send pin. | |
#define | PD30_SCK2_B 30 |
Channel 2 serial clock pin. | |
#define | PB6_TXD2_A 6 |
Channel 2 transmit data pin. | |
#define | PB7_RXD2_A 7 |
Channel 2 receive data pin. | |
#define | PC11_CTS2_B 11 |
Channel 2 clear to send pin. | |
#define | PC9_RTS2_B 9 |
Channel 2 request to send pin. | |
#define | PA22_SCK3_B 22 |
Channel 3 serial clock pin. | |
#define | PB8_TXD3_A 8 |
Channel 3 transmit data pin. | |
#define | PB9_RXD3_A 9 |
Channel 3 receive data pin. | |
#define | PA24_CTS3_B 24 |
Channel 3 clear to send pin. | |
#define | PA23_RTS3_B 23 |
Channel 3 request to send pin. | |
SPI Peripheral Multiplexing | |
| |
#define | PB0_SPI0_MISO_A 0 |
Channel 0 master input slave output pin. | |
#define | PB1_SPI0_MOSI_A 1 |
Channel 0 master output slave input pin. | |
#define | PB2_SPI0_SPCK_A 2 |
Channel 0 serial clock pin. | |
#define | PB3_SPI0_NPCS0_A 3 |
Channel 0 chip select 0 pin. | |
#define | PB18_SPI0_NPCS1_B 18 |
Channel 0 chip select 1 pin. | |
#define | PD24_SPI0_NPCS1_A 24 |
Channel 0 chip select 1 pin. | |
#define | PB19_SPI0_NPCS2_B 19 |
Channel 0 chip select 2 pin. | |
#define | PD25_SPI0_NPCS2_A 25 |
Channel 0 chip select 1 pin. | |
#define | PD27_SPI0_NPCS3_B 27 |
Channel 0 chip select 3 pin. | |
#define | SPI0_PINS _BV(PB0_SPI0_MISO_A) | _BV(PB1_SPI0_MOSI_A) | _BV(PB2_SPI0_SPCK_A) |
#define | SPI0_PIO_BASE PIOA_BASE |
#define | SPI0_PSR_OFF PIO_ASR_OFF |
#define | SPI0_CS0_PIN _BV(PB3_SPI0_NPCS0_A) |
#define | SPI0_CS0_PIO_BASE PIOB_BASE |
#define | SPI0_CS0_PSR_OFF PIO_ASR_OFF |
#define | SPI0_CS1_PIN _BV(PB18_SPI0_NPCS1_B) |
#define | SPI0_CS1_PIO_BASE PIOB_BASE |
#define | SPI0_CS1_PSR_OFF PIO_BSR_OFF |
#define | PB14_SPI1_MISO_A 14 |
Channel 1 master input slave output pin. | |
#define | PB15_SPI1_MOSI_A 15 |
Channel 1 master output slave input pin. | |
#define | PB16_SPI1_SPCK_A 16 |
Channel 1 serial clock pin. | |
#define | PB17_SPI1_NPCS0_A 17 |
Channel 1 chip select 0 pin. | |
#define | PD28_SPI1_NPCS1_B 28 |
Channel 1 chip select 1 pin. | |
#define | PD18_SPI1_NPCS2_A 18 |
Channel 1 chip select 2 pin. | |
#define | PD19_SPI1_NPCS3_A 19 |
Channel 1 chip select 3 pin. | |
#define | SPI1_PINS _BV(PB14_SPI1_MISO_A) | _BV(PB15_SPI1_MOSI_A) | _BV(PB16_SPI1_SPCK_A) |
#define | SPI1_PIO_BASE PIOB_BASE |
#define | SPI1_PSR_OFF PIO_ASR_OFF |
#define | SPI1_CS0_PIN _BV(PB17_SPI1_NPCS0_A) |
#define | SPI1_CS0_PIO_BASE PIOB_BASE |
#define | SPI1_CS0_PSR_OFF PIO_ASR_OFF |
#define FIQ_ID 0 |
Fast interrupt.
Definition at line 167 of file at91sam9g45.h.
#define SYSC_ID 1 |
System interrupt.
Definition at line 168 of file at91sam9g45.h.
#define PIOA_ID 2 |
Parallel I/O controller A.
Definition at line 169 of file at91sam9g45.h.
#define PIOB_ID 3 |
Parallel I/O controller B.
Definition at line 170 of file at91sam9g45.h.
#define PIOC_ID 4 |
Parallel I/O controller C.
Definition at line 171 of file at91sam9g45.h.
#define PIODE_ID 5 |
Parallel I/O controller C.
Definition at line 172 of file at91sam9g45.h.
#define RNG_ID 6 |
Analog to digital converter.
Definition at line 173 of file at91sam9g45.h.
#define US0_ID 7 |
USART 0.
Definition at line 174 of file at91sam9g45.h.
#define US1_ID 8 |
USART 1.
Definition at line 175 of file at91sam9g45.h.
#define US2_ID 9 |
USART 2.
Definition at line 176 of file at91sam9g45.h.
#define US3_ID 10 |
USART 3.
Definition at line 177 of file at91sam9g45.h.
#define MCI0_ID 11 |
MMC interface.
Definition at line 178 of file at91sam9g45.h.
#define TWI0_ID 12 |
Two wire interface.
Definition at line 179 of file at91sam9g45.h.
#define TWI1_ID 13 |
Two wire interface.
Definition at line 180 of file at91sam9g45.h.
#define SPI0_ID 14 |
Serial peripheral 0.
Definition at line 181 of file at91sam9g45.h.
#define SPI1_ID 15 |
Serial peripheral 1.
Definition at line 182 of file at91sam9g45.h.
#define SSC0_ID 16 |
Serial peripheral interface.
Definition at line 183 of file at91sam9g45.h.
#define SSC1_ID 17 |
Serial peripheral interface.
Definition at line 184 of file at91sam9g45.h.
#define TC0_ID 18 |
Timer/counter 0.
Definition at line 185 of file at91sam9g45.h.
#define TC1_ID 18 |
Timer/counter 1.
Definition at line 186 of file at91sam9g45.h.
#define TC2_ID 18 |
Timer/counter 2.
Definition at line 187 of file at91sam9g45.h.
#define TC3_ID 18 |
Timer/counter 3.
Definition at line 188 of file at91sam9g45.h.
#define TC4_ID 18 |
Timer/counter 4.
Definition at line 189 of file at91sam9g45.h.
#define TC5_ID 18 |
Timer/counter 5.
Definition at line 190 of file at91sam9g45.h.
#define PWMC_ID 19 |
Pulse Width Modulation Controller.
Definition at line 191 of file at91sam9g45.h.
#define TSADCC_ID 20 |
Touch Screen ADC Controller.
Definition at line 192 of file at91sam9g45.h.
#define DMA_ID 21 |
DMA Controller.
Definition at line 193 of file at91sam9g45.h.
#define UHP_ID 22 |
USB host port.
Definition at line 194 of file at91sam9g45.h.
#define LCDC_ID 23 |
LCD controller.
Definition at line 195 of file at91sam9g45.h.
#define AC97_ID 24 |
AC97 controller.
Definition at line 196 of file at91sam9g45.h.
#define EMAC_ID 25 |
Ethernet MAC.
Definition at line 197 of file at91sam9g45.h.
#define ISI_ID 26 |
Image sensor interface.
Definition at line 198 of file at91sam9g45.h.
#define UDP_ID 27 |
USB device port.
Definition at line 199 of file at91sam9g45.h.
#define MCI1_ID 29 |
MMC interface.
Definition at line 200 of file at91sam9g45.h.
#define IRQ0_ID 31 |
External interrupt 0.
Definition at line 201 of file at91sam9g45.h.
#define TWI_ID TWI0_ID |
Two wire interface.
Definition at line 203 of file at91sam9g45.h.
#define MCI_ID MCI0_ID |
MMC interface.
Definition at line 204 of file at91sam9g45.h.
#define SSC_ID SSC0_ID |
Serial peripheral interface.
Definition at line 205 of file at91sam9g45.h.
#define PB16_SCK0_B 16 |
Channel 0 serial clock pin.
Definition at line 211 of file at91sam9g45.h.
#define PB19_TXD0_A 19 |
Channel 0 transmit data pin.
Definition at line 212 of file at91sam9g45.h.
#define PB18_RXD0_A 18 |
Channel 0 receive data pin.
Definition at line 213 of file at91sam9g45.h.
#define PB15_CTS0_B 15 |
Channel 0 clear to send pin.
Definition at line 214 of file at91sam9g45.h.
#define PB17_RTS0_B 17 |
Channel 0 request to send pin.
Definition at line 215 of file at91sam9g45.h.
#define PD29_SCK1_B 29 |
Channel 1 serial clock pin.
Definition at line 217 of file at91sam9g45.h.
#define PB4_TXD1_A 4 |
Channel 1 transmit data pin.
Definition at line 218 of file at91sam9g45.h.
#define PB5_RXD1_A 5 |
Channel 1 receive data pin.
Definition at line 219 of file at91sam9g45.h.
#define PD17_CTS1_A 17 |
Channel 1 clear to send pin.
Definition at line 220 of file at91sam9g45.h.
#define PD16_RTS1_A 16 |
Channel 1 request to send pin.
Definition at line 221 of file at91sam9g45.h.
#define PD30_SCK2_B 30 |
Channel 2 serial clock pin.
Definition at line 223 of file at91sam9g45.h.
#define PB6_TXD2_A 6 |
Channel 2 transmit data pin.
Definition at line 224 of file at91sam9g45.h.
#define PB7_RXD2_A 7 |
Channel 2 receive data pin.
Definition at line 225 of file at91sam9g45.h.
#define PC11_CTS2_B 11 |
Channel 2 clear to send pin.
Definition at line 226 of file at91sam9g45.h.
#define PC9_RTS2_B 9 |
Channel 2 request to send pin.
Definition at line 227 of file at91sam9g45.h.
#define PA22_SCK3_B 22 |
Channel 3 serial clock pin.
Definition at line 229 of file at91sam9g45.h.
#define PB8_TXD3_A 8 |
Channel 3 transmit data pin.
Definition at line 230 of file at91sam9g45.h.
#define PB9_RXD3_A 9 |
Channel 3 receive data pin.
Definition at line 231 of file at91sam9g45.h.
#define PA24_CTS3_B 24 |
Channel 3 clear to send pin.
Definition at line 232 of file at91sam9g45.h.
#define PA23_RTS3_B 23 |
Channel 3 request to send pin.
Definition at line 233 of file at91sam9g45.h.
#define PB0_SPI0_MISO_A 0 |
Channel 0 master input slave output pin.
Definition at line 238 of file at91sam9g45.h.
#define PB1_SPI0_MOSI_A 1 |
Channel 0 master output slave input pin.
Definition at line 239 of file at91sam9g45.h.
#define PB2_SPI0_SPCK_A 2 |
Channel 0 serial clock pin.
Definition at line 240 of file at91sam9g45.h.
#define PB3_SPI0_NPCS0_A 3 |
Channel 0 chip select 0 pin.
Definition at line 241 of file at91sam9g45.h.
#define PB18_SPI0_NPCS1_B 18 |
Channel 0 chip select 1 pin.
Definition at line 242 of file at91sam9g45.h.
#define PD24_SPI0_NPCS1_A 24 |
Channel 0 chip select 1 pin.
Definition at line 243 of file at91sam9g45.h.
#define PB19_SPI0_NPCS2_B 19 |
Channel 0 chip select 2 pin.
Definition at line 244 of file at91sam9g45.h.
#define PD25_SPI0_NPCS2_A 25 |
Channel 0 chip select 1 pin.
Definition at line 245 of file at91sam9g45.h.
#define PD27_SPI0_NPCS3_B 27 |
Channel 0 chip select 3 pin.
Definition at line 246 of file at91sam9g45.h.
#define SPI0_PINS _BV(PB0_SPI0_MISO_A) | _BV(PB1_SPI0_MOSI_A) | _BV(PB2_SPI0_SPCK_A) |
Definition at line 248 of file at91sam9g45.h.
#define SPI0_PIO_BASE PIOA_BASE |
Definition at line 249 of file at91sam9g45.h.
#define SPI0_PSR_OFF PIO_ASR_OFF |
Definition at line 250 of file at91sam9g45.h.
#define SPI0_CS0_PIN _BV(PB3_SPI0_NPCS0_A) |
Definition at line 252 of file at91sam9g45.h.
#define SPI0_CS0_PIO_BASE PIOB_BASE |
Definition at line 253 of file at91sam9g45.h.
#define SPI0_CS0_PSR_OFF PIO_ASR_OFF |
Definition at line 254 of file at91sam9g45.h.
#define SPI0_CS1_PIN _BV(PB18_SPI0_NPCS1_B) |
Definition at line 256 of file at91sam9g45.h.
#define SPI0_CS1_PIO_BASE PIOB_BASE |
Definition at line 257 of file at91sam9g45.h.
#define SPI0_CS1_PSR_OFF PIO_BSR_OFF |
Definition at line 258 of file at91sam9g45.h.
#define PB14_SPI1_MISO_A 14 |
Channel 1 master input slave output pin.
Definition at line 260 of file at91sam9g45.h.
#define PB15_SPI1_MOSI_A 15 |
Channel 1 master output slave input pin.
Definition at line 261 of file at91sam9g45.h.
#define PB16_SPI1_SPCK_A 16 |
Channel 1 serial clock pin.
Definition at line 262 of file at91sam9g45.h.
#define PB17_SPI1_NPCS0_A 17 |
Channel 1 chip select 0 pin.
Definition at line 263 of file at91sam9g45.h.
#define PD28_SPI1_NPCS1_B 28 |
Channel 1 chip select 1 pin.
Definition at line 264 of file at91sam9g45.h.
#define PD18_SPI1_NPCS2_A 18 |
Channel 1 chip select 2 pin.
Definition at line 265 of file at91sam9g45.h.
#define PD19_SPI1_NPCS3_A 19 |
Channel 1 chip select 3 pin.
Definition at line 266 of file at91sam9g45.h.
#define SPI1_PINS _BV(PB14_SPI1_MISO_A) | _BV(PB15_SPI1_MOSI_A) | _BV(PB16_SPI1_SPCK_A) |
Definition at line 268 of file at91sam9g45.h.
#define SPI1_PIO_BASE PIOB_BASE |
Definition at line 269 of file at91sam9g45.h.
#define SPI1_PSR_OFF PIO_ASR_OFF |
Definition at line 270 of file at91sam9g45.h.
#define SPI1_CS0_PIN _BV(PB17_SPI1_NPCS0_A) |
Definition at line 272 of file at91sam9g45.h.
#define SPI1_CS0_PIO_BASE PIOB_BASE |
Definition at line 273 of file at91sam9g45.h.
#define SPI1_CS0_PSR_OFF PIO_ASR_OFF |
Definition at line 274 of file at91sam9g45.h.