XgUARTClock
[UART I/O Control Functions]

UART device clock modes. More...

Collaboration diagram for XgUARTClock:

Defines

#define UART_SYNC   0x01
#define UART_MASTER   0x02
#define UART_NCLOCK   0x04
#define UART_HIGHSPEED   0x20
#define UART_ASYNC   0x00
 Normal asynchronous mode.
#define UART_SYNCSLAVE   UART_SYNC
 Synchronous slave mode.
#define UART_SYNCMASTER   (UART_SYNC | UART_MASTER)
 Synchronous master mode.
#define UART_NSYNCSLAVE   (UART_SYNC | UART_NCLOCK)
 Synchronous slave mode, clock negated.
#define UART_NSYNCMASTER   (UART_SYNC | UART_NCLOCK | UART_MASTER)
 Synchronous master mode, clock negated.
#define UART_ASYNC_HS   UART_HIGHSPEED
 Asynchronous high speed mode.

Detailed Description

UART device clock modes.

Any of these values may be used by the _ioctl() commands UART_SETCLOCKMODE and UART_GETCLOCKMODE. Most drivers require to set the bit rate after modifying the clock mode. In order to avoid unknown clock output frequencies in master mode, set the clock mode to UART_SYNCSLAVE first, than use UART_SETSPEED to select the bit rate and finally switch to UART_SYNCMASTER or UART_NSYNCMASTER.


Define Documentation

#define UART_SYNC   0x01

Definition at line 547 of file uart.h.

#define UART_MASTER   0x02

Definition at line 548 of file uart.h.

#define UART_NCLOCK   0x04

Definition at line 549 of file uart.h.

#define UART_HIGHSPEED   0x20

Definition at line 550 of file uart.h.

#define UART_ASYNC   0x00

Normal asynchronous mode.

Definition at line 554 of file uart.h.

#define UART_SYNCSLAVE   UART_SYNC

Synchronous slave mode.

Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock input.

Definition at line 561 of file uart.h.

#define UART_SYNCMASTER   (UART_SYNC | UART_MASTER)

Synchronous master mode.

Transmit data changes on rising edge and receive data is sampled on the falling edge of the clock output.

Definition at line 568 of file uart.h.

#define UART_NSYNCSLAVE   (UART_SYNC | UART_NCLOCK)

Synchronous slave mode, clock negated.

Similar to UART_SYNCSLAVE, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock input.

Definition at line 575 of file uart.h.

#define UART_NSYNCMASTER   (UART_SYNC | UART_NCLOCK | UART_MASTER)

Synchronous master mode, clock negated.

Similar to UART_SYNCMASTER, but transmit data changes on falling edge and receive data is sampled on the rising edge of the clock output.

Definition at line 582 of file uart.h.

#define UART_ASYNC_HS   UART_HIGHSPEED

Asynchronous high speed mode.

More deviation sensitive than normal mode, but supports higher speed.

Definition at line 588 of file uart.h.


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