Register definitions. More...
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Peripheral Identifiers and Interrupts | |
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#define | FIQ_ID 0 |
Fast interrupt. | |
#define | SYSC_ID 2 |
System controller. | |
#define | PIOA_ID 2 |
Parallel I/O controller A. | |
#define | PIOB_ID 3 |
Parallel I/O controller B. | |
#define | PIOC_ID 4 |
Parallel I/O controller C. | |
#define | ADC_ID 5 |
Analog to digital converter. | |
#define | US0_ID 6 |
USART 0. | |
#define | US1_ID 7 |
USART 1. | |
#define | US2_ID 8 |
USART 2. | |
#define | MCI_ID 9 |
MMC interface. | |
#define | UDP_ID 10 |
USB device port. | |
#define | TWI_ID 11 |
Two wire interface 0. | |
#define | SPI0_ID 12 |
Serial peripheral 0. | |
#define | SPI1_ID 13 |
Serial peripheral 1. | |
#define | SSC_ID 14 |
Serial peripheral interface. | |
#define | TC0_ID 17 |
Timer/counter 0. | |
#define | TC1_ID 18 |
Timer/counter 1. | |
#define | TC2_ID 19 |
Timer/counter 2. | |
#define | UHP_ID 20 |
USB host port. | |
#define | EMAC_ID 21 |
Ethernet MAC. | |
#define | ISI_ID 22 |
Image sensor interface. | |
#define | US3_ID 23 |
USART 3. | |
#define | US4_ID 24 |
USART 4. | |
#define | TWI1_ID 25 |
Two wire interface 1. | |
#define | TC3_ID 26 |
Timer/counter 3. | |
#define | TC4_ID 27 |
Timer/counter 4. | |
#define | TC5_ID 28 |
Timer/counter 5. | |
#define | IRQ0_ID 29 |
External interrupt 0. | |
#define | IRQ1_ID 30 |
External interrupt 1. | |
#define | IRQ2_ID 31 |
External interrupt 2. | |
USART Peripheral Multiplexing | |
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#define | PA31_SCK0_A 31 |
Channel 0 serial clock pin. | |
#define | PB4_TXD0_A 4 |
Channel 0 transmit data pin. | |
#define | PB5_RXD0_A 5 |
Channel 0 receive data pin. | |
#define | PB27_CTS0_A 27 |
Channel 0 clear to send pin. | |
#define | PB26_RTS0_A 26 |
Channel 0 request to send pin. | |
#define | PB25_RI0_A 25 |
Channel 0 ring indicator pin. | |
#define | PB22_DSR0_A 22 |
Channel 0 data set ready pin. | |
#define | PB23_DCD0_A 23 |
Channel 0 data carrier detect pin. | |
#define | PB24_DTR0_A 24 |
Channel 0 data terminal ready pin. | |
#define | PA29_SCK1_A 29 |
Channel 1 serial clock pin. | |
#define | PB6_TXD1_A 6 |
Channel 1 transmit data pin. | |
#define | PB7_RXD1_A 7 |
Channel 1 receive data pin. | |
#define | PB29_CTS1_A 29 |
Channel 1 clear to send pin. | |
#define | PB28_RTS1_A 28 |
Channel 1 request to send pin. | |
#define | PA30_SCK2_A 30 |
Channel 2 serial clock pin. | |
#define | PB8_TXD2_A 8 |
Channel 2 transmit data pin. | |
#define | PB9_RXD2_A 9 |
Channel 2 receive data pin. | |
#define | PA5_CTS2_A 5 |
Channel 2 clear to send pin. | |
#define | PA4_RTS2_A 4 |
Channel 2 request to send pin. | |
#define | PC0_SCK3_B 0 |
Channel 3 serial clock pin. | |
#define | PB10_TXD3_A 10 |
Channel 3 transmit data pin. | |
#define | PB11_RXD3_A 11 |
Channel 3 receive data pin. | |
#define | PC10_CTS3_B 10 |
Channel 3 clear to send pin. | |
#define | PC8_RTS3_B 8 |
Channel 3 request to send pin. | |
#define | PA31_TXD4_B 31 |
Channel 4 transmit data pin. | |
#define | PA30_RXD4_B 30 |
Channel 4 receive data pin. | |
SPI Peripheral Multiplexing | |
| |
#define | PA0_SPI0_MISO_A 0 |
Channel 0 master input slave output pin. | |
#define | PA1_SPI0_MOSI_A 1 |
Channel 0 master output slave input pin. | |
#define | PA2_SPI0_SPCK_A 2 |
Channel 0 serial clock pin. | |
#define | PA3_SPI0_NPCS0_A 3 |
Channel 0 chip select 0 pin. | |
#define | PC11_SPI0_NPCS1_B 11 |
Channel 0 chip select 1 pin. | |
#define | PC16_SPI0_NPCS2_B 16 |
Channel 0 chip select 2 pin. | |
#define | PC17_SPI0_NPCS3_B 17 |
Channel 0 chip select 3 pin. | |
#define | SPI0_PINS _BV(PA0_SPI0_MISO_A) | _BV(PA1_SPI0_MOSI_A) | _BV(PA2_SPI0_SPCK_A) |
#define | SPI0_PIO_BASE PIOA_BASE |
#define | SPI0_PSR_OFF PIO_ASR_OFF |
#define | SPI0_CS0_PIN _BV(PA3_SPI0_NPCS0_A) |
#define | SPI0_CS0_PIO_BASE PIOA_BASE |
#define | SPI0_CS0_PSR_OFF PIO_ASR_OFF |
#define | SPI0_CS1_PIN _BV(PC11_SPI0_NPCS1_B) |
#define | SPI0_CS1_PIO_BASE PIOC_BASE |
#define | SPI0_CS1_PSR_OFF PIO_BSR_OFF |
#define | PB0_SPI1_MISO_A 0 |
Channel 1 master input slave output pin. | |
#define | PB1_SPI1_MOSI_A 1 |
Channel 1 master output slave input pin. | |
#define | PB2_SPI1_SPCK_A 2 |
Channel 1 serial clock pin. | |
#define | PB3_SPI1_NPCS0_A 3 |
Channel 1 chip select 0 pin. | |
#define | PC5_SPI1_NPCS1_B 5 |
Channel 1 chip select 1 pin. | |
#define | PC18_SPI1_NPCS1_B 18 |
Channel 1 chip select 1 pin. | |
#define | PC4_SPI1_NPCS2_B 4 |
Channel 1 chip select 2 pin. | |
#define | PC19_SPI1_NPCS2_B 19 |
Channel 1 chip select 2 pin. | |
#define | PC3_SPI1_NPCS3_B 3 |
Channel 1 chip select 3 pin. | |
#define | PC20_SPI1_NPCS3_B 20 |
Channel 1 chip select 3 pin. | |
#define | SPI1_PINS _BV(PB0_SPI1_MISO_A) | _BV(PB1_SPI1_MOSI_A) | _BV(PB2_SPI1_SPCK_A) |
#define | SPI1_PIO_BASE PIOB_BASE |
#define | SPI1_PSR_OFF PIO_ASR_OFF |
#define | SPI1_CS0_PIN _BV(PB3_SPI1_NPCS0_A) |
#define | SPI1_CS0_PIO_BASE PIOB_BASE |
#define | SPI1_CS0_PSR_OFF PIO_ASR_OFF |
Register definitions.
#define FIQ_ID 0 |
Fast interrupt.
Definition at line 157 of file at91sam9xe.h.
#define SYSC_ID 2 |
System controller.
Definition at line 158 of file at91sam9xe.h.
#define PIOA_ID 2 |
Parallel I/O controller A.
Definition at line 159 of file at91sam9xe.h.
#define PIOB_ID 3 |
Parallel I/O controller B.
Definition at line 160 of file at91sam9xe.h.
#define PIOC_ID 4 |
Parallel I/O controller C.
Definition at line 161 of file at91sam9xe.h.
#define ADC_ID 5 |
Analog to digital converter.
Definition at line 162 of file at91sam9xe.h.
#define US0_ID 6 |
USART 0.
Definition at line 163 of file at91sam9xe.h.
#define US1_ID 7 |
USART 1.
Definition at line 164 of file at91sam9xe.h.
#define US2_ID 8 |
USART 2.
Definition at line 165 of file at91sam9xe.h.
#define MCI_ID 9 |
MMC interface.
Definition at line 166 of file at91sam9xe.h.
#define UDP_ID 10 |
USB device port.
Definition at line 167 of file at91sam9xe.h.
#define TWI_ID 11 |
Two wire interface 0.
Definition at line 168 of file at91sam9xe.h.
#define SPI0_ID 12 |
Serial peripheral 0.
Definition at line 169 of file at91sam9xe.h.
#define SPI1_ID 13 |
Serial peripheral 1.
Definition at line 170 of file at91sam9xe.h.
#define SSC_ID 14 |
Serial peripheral interface.
Definition at line 171 of file at91sam9xe.h.
#define TC0_ID 17 |
Timer/counter 0.
Definition at line 172 of file at91sam9xe.h.
#define TC1_ID 18 |
Timer/counter 1.
Definition at line 173 of file at91sam9xe.h.
#define TC2_ID 19 |
Timer/counter 2.
Definition at line 174 of file at91sam9xe.h.
#define UHP_ID 20 |
USB host port.
Definition at line 175 of file at91sam9xe.h.
#define EMAC_ID 21 |
Ethernet MAC.
Definition at line 176 of file at91sam9xe.h.
#define ISI_ID 22 |
Image sensor interface.
Definition at line 177 of file at91sam9xe.h.
#define US3_ID 23 |
USART 3.
Definition at line 178 of file at91sam9xe.h.
#define US4_ID 24 |
USART 4.
Definition at line 179 of file at91sam9xe.h.
#define TWI1_ID 25 |
Two wire interface 1.
Definition at line 180 of file at91sam9xe.h.
#define TC3_ID 26 |
Timer/counter 3.
Definition at line 181 of file at91sam9xe.h.
#define TC4_ID 27 |
Timer/counter 4.
Definition at line 182 of file at91sam9xe.h.
#define TC5_ID 28 |
Timer/counter 5.
Definition at line 183 of file at91sam9xe.h.
#define IRQ0_ID 29 |
External interrupt 0.
Definition at line 184 of file at91sam9xe.h.
#define IRQ1_ID 30 |
External interrupt 1.
Definition at line 185 of file at91sam9xe.h.
#define IRQ2_ID 31 |
External interrupt 2.
Definition at line 186 of file at91sam9xe.h.
#define PA31_SCK0_A 31 |
Channel 0 serial clock pin.
Definition at line 192 of file at91sam9xe.h.
#define PB4_TXD0_A 4 |
Channel 0 transmit data pin.
Definition at line 193 of file at91sam9xe.h.
#define PB5_RXD0_A 5 |
Channel 0 receive data pin.
Definition at line 194 of file at91sam9xe.h.
#define PB27_CTS0_A 27 |
Channel 0 clear to send pin.
Definition at line 195 of file at91sam9xe.h.
#define PB26_RTS0_A 26 |
Channel 0 request to send pin.
Definition at line 196 of file at91sam9xe.h.
#define PB25_RI0_A 25 |
Channel 0 ring indicator pin.
Definition at line 197 of file at91sam9xe.h.
#define PB22_DSR0_A 22 |
Channel 0 data set ready pin.
Definition at line 198 of file at91sam9xe.h.
#define PB23_DCD0_A 23 |
Channel 0 data carrier detect pin.
Definition at line 199 of file at91sam9xe.h.
#define PB24_DTR0_A 24 |
Channel 0 data terminal ready pin.
Definition at line 200 of file at91sam9xe.h.
#define PA29_SCK1_A 29 |
Channel 1 serial clock pin.
Definition at line 202 of file at91sam9xe.h.
#define PB6_TXD1_A 6 |
Channel 1 transmit data pin.
Definition at line 203 of file at91sam9xe.h.
#define PB7_RXD1_A 7 |
Channel 1 receive data pin.
Definition at line 204 of file at91sam9xe.h.
#define PB29_CTS1_A 29 |
Channel 1 clear to send pin.
Definition at line 205 of file at91sam9xe.h.
#define PB28_RTS1_A 28 |
Channel 1 request to send pin.
Definition at line 206 of file at91sam9xe.h.
#define PA30_SCK2_A 30 |
Channel 2 serial clock pin.
Definition at line 208 of file at91sam9xe.h.
#define PB8_TXD2_A 8 |
Channel 2 transmit data pin.
Definition at line 209 of file at91sam9xe.h.
#define PB9_RXD2_A 9 |
Channel 2 receive data pin.
Definition at line 210 of file at91sam9xe.h.
#define PA5_CTS2_A 5 |
Channel 2 clear to send pin.
Definition at line 211 of file at91sam9xe.h.
#define PA4_RTS2_A 4 |
Channel 2 request to send pin.
Definition at line 212 of file at91sam9xe.h.
#define PC0_SCK3_B 0 |
Channel 3 serial clock pin.
Definition at line 214 of file at91sam9xe.h.
#define PB10_TXD3_A 10 |
Channel 3 transmit data pin.
Definition at line 215 of file at91sam9xe.h.
#define PB11_RXD3_A 11 |
Channel 3 receive data pin.
Definition at line 216 of file at91sam9xe.h.
#define PC10_CTS3_B 10 |
Channel 3 clear to send pin.
Definition at line 217 of file at91sam9xe.h.
#define PC8_RTS3_B 8 |
Channel 3 request to send pin.
Definition at line 218 of file at91sam9xe.h.
#define PA31_TXD4_B 31 |
Channel 4 transmit data pin.
Definition at line 220 of file at91sam9xe.h.
#define PA30_RXD4_B 30 |
Channel 4 receive data pin.
Definition at line 221 of file at91sam9xe.h.
#define PA0_SPI0_MISO_A 0 |
Channel 0 master input slave output pin.
Definition at line 226 of file at91sam9xe.h.
#define PA1_SPI0_MOSI_A 1 |
Channel 0 master output slave input pin.
Definition at line 227 of file at91sam9xe.h.
#define PA2_SPI0_SPCK_A 2 |
Channel 0 serial clock pin.
Definition at line 228 of file at91sam9xe.h.
#define PA3_SPI0_NPCS0_A 3 |
Channel 0 chip select 0 pin.
Definition at line 229 of file at91sam9xe.h.
#define PC11_SPI0_NPCS1_B 11 |
Channel 0 chip select 1 pin.
Definition at line 230 of file at91sam9xe.h.
#define PC16_SPI0_NPCS2_B 16 |
Channel 0 chip select 2 pin.
Definition at line 231 of file at91sam9xe.h.
#define PC17_SPI0_NPCS3_B 17 |
Channel 0 chip select 3 pin.
Definition at line 232 of file at91sam9xe.h.
#define SPI0_PINS _BV(PA0_SPI0_MISO_A) | _BV(PA1_SPI0_MOSI_A) | _BV(PA2_SPI0_SPCK_A) |
Definition at line 234 of file at91sam9xe.h.
#define SPI0_PIO_BASE PIOA_BASE |
Definition at line 235 of file at91sam9xe.h.
#define SPI0_PSR_OFF PIO_ASR_OFF |
Definition at line 236 of file at91sam9xe.h.
#define SPI0_CS0_PIN _BV(PA3_SPI0_NPCS0_A) |
Definition at line 238 of file at91sam9xe.h.
#define SPI0_CS0_PIO_BASE PIOA_BASE |
Definition at line 239 of file at91sam9xe.h.
#define SPI0_CS0_PSR_OFF PIO_ASR_OFF |
Definition at line 240 of file at91sam9xe.h.
#define SPI0_CS1_PIN _BV(PC11_SPI0_NPCS1_B) |
Definition at line 242 of file at91sam9xe.h.
#define SPI0_CS1_PIO_BASE PIOC_BASE |
Definition at line 243 of file at91sam9xe.h.
#define SPI0_CS1_PSR_OFF PIO_BSR_OFF |
Definition at line 244 of file at91sam9xe.h.
#define PB0_SPI1_MISO_A 0 |
Channel 1 master input slave output pin.
Definition at line 246 of file at91sam9xe.h.
#define PB1_SPI1_MOSI_A 1 |
Channel 1 master output slave input pin.
Definition at line 247 of file at91sam9xe.h.
#define PB2_SPI1_SPCK_A 2 |
Channel 1 serial clock pin.
Definition at line 248 of file at91sam9xe.h.
#define PB3_SPI1_NPCS0_A 3 |
Channel 1 chip select 0 pin.
Definition at line 249 of file at91sam9xe.h.
#define PC5_SPI1_NPCS1_B 5 |
Channel 1 chip select 1 pin.
Definition at line 250 of file at91sam9xe.h.
#define PC18_SPI1_NPCS1_B 18 |
Channel 1 chip select 1 pin.
Definition at line 251 of file at91sam9xe.h.
#define PC4_SPI1_NPCS2_B 4 |
Channel 1 chip select 2 pin.
Definition at line 252 of file at91sam9xe.h.
#define PC19_SPI1_NPCS2_B 19 |
Channel 1 chip select 2 pin.
Definition at line 253 of file at91sam9xe.h.
#define PC3_SPI1_NPCS3_B 3 |
Channel 1 chip select 3 pin.
Definition at line 254 of file at91sam9xe.h.
#define PC20_SPI1_NPCS3_B 20 |
Channel 1 chip select 3 pin.
Definition at line 255 of file at91sam9xe.h.
#define SPI1_PINS _BV(PB0_SPI1_MISO_A) | _BV(PB1_SPI1_MOSI_A) | _BV(PB2_SPI1_SPCK_A) |
Definition at line 257 of file at91sam9xe.h.
#define SPI1_PIO_BASE PIOB_BASE |
Definition at line 258 of file at91sam9xe.h.
#define SPI1_PSR_OFF PIO_ASR_OFF |
Definition at line 259 of file at91sam9xe.h.
#define SPI1_CS0_PIN _BV(PB3_SPI1_NPCS0_A) |
Definition at line 261 of file at91sam9xe.h.
#define SPI1_CS0_PIO_BASE PIOB_BASE |
Definition at line 262 of file at91sam9xe.h.
#define SPI1_CS0_PSR_OFF PIO_ASR_OFF |
Definition at line 263 of file at91sam9xe.h.