at91_twi.c

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00001 /*
00002  * Copyright (C) 2001-2005 by EmbeddedIT, 
00003  * Ole Reinhardt <ole.reinhardt@embedded-it.de> All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EMBEDDED IT AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EMBEDDED IT
00022  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
00023  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
00024  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 
00025  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00026  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
00027  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00028  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: at91_twi.c,v $
00036  * Revision 1.7  2008/10/03 11:31:27  haraldkipp
00037  * Added TWI support for the AT91SAM9260.
00038  *
00039  * Revision 1.6  2008/08/11 06:59:04  haraldkipp
00040  * BSD types replaced by stdint types (feature request #1282721).
00041  *
00042  * Revision 1.5  2008/02/15 16:58:41  haraldkipp
00043  * Spport for AT91SAM7SE512 added.
00044  *
00045  * Revision 1.4  2007/12/09 22:17:23  olereinhardt
00046  * fixed typo
00047  *
00048  * Revision 1.3  2007/12/09 21:52:27  olereinhardt
00049  * Added doxygen tags
00050  *
00051  * Revision 1.2  2007/10/04 19:51:56  olereinhardt
00052  * Support for sam7s added
00053  *
00054  * Revision 1.1  2007/09/06 19:36:00  olereinhardt
00055  * First checkin, new twi driver for at91 (currently SAM7X256 is supported
00056  * only)
00057  *
00058  */
00059 
00060 #include <arch/arm.h>
00061 #include <dev/irqreg.h>
00062 
00063 #include <sys/event.h>
00064 #include <sys/atom.h>
00065 #include <sys/timer.h>
00066 #include <sys/thread.h>
00067 #include <sys/heap.h>
00068 
00069 #include <dev/twif.h>
00070 
00075 
00076 HANDLE tw_mm_mutex;                 /* Exclusive master access. */
00077 HANDLE tw_mm_que;                   /* Threads waiting for master transfer done. */
00078 
00079 static uint8_t tw_mm_sla;            /* Destination slave address. */
00080 static volatile uint8_t tw_mm_err;   /* Current master mode error. */
00081 static uint8_t tw_mm_error;          /* Last master mode error. */
00082 
00083 static CONST uint8_t *tw_mt_buf;     /* Pointer to the master transmit buffer. */
00084 static volatile uint16_t tw_mt_len;  /* Number of bytes to transmit in master mode. */
00085 static volatile uint16_t tw_mt_idx;  /* Current master transmit buffer index. */
00086 
00087 static uint8_t *tw_mr_buf;           /* Pointer to the master receive buffer. */
00088 static volatile uint16_t tw_mr_siz;  /* Size of the master receive buffer. */
00089 static volatile uint16_t tw_mr_idx;  /* Current master receive buffer index. */
00090 
00091 #if defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256) || defined (MCU_AT91SAM7SE512)
00092 
00093 #define TWI_PIO_ASR PIOA_ASR
00094 #define TWI_PIO_PDR PIOA_PDR
00095 #define TWI_PIO_MDER PIOA_MDER
00096 
00097    #if defined (MCU_AT91SAM7X256)
00098       #define TWI_TWD  PA10_TWD_A
00099       #define TWI_TWCK PA11_TWCK_A
00100    #elif defined (MCU_AT91SAM7S256) || defined (MCU_AT91SAM7SE512)
00101       #define TWI_TWD  PA3_TWD_A
00102       #define TWI_TWCK PA4_TWCK_A
00103    #endif
00104 #endif
00105 
00106 #if defined (MCU_AT91SAM9260)
00107 #define TWI_PIO_ASR     PIOA_ASR
00108 #define TWI_PIO_PDR     PIOA_PDR
00109 #define TWI_PIO_MDER    PIOA_MDER
00110 #define TWI_TWD         PA23_TWD_A
00111 #define TWI_TWCK        PA24_TWCK_A
00112 #endif
00113 
00114 /*
00115  * TWI interrupt handler.
00116  */
00117 static void TwInterrupt(void *arg)
00118 {
00119     register u_int twsr = inr(TWI_SR) & (TWI_NACK | TWI_RXRDY | TWI_TXRDY | TWI_TXCOMP);;   
00120 
00121     /* Transmission is complete, signal waiting threads */
00122     if (twsr & TWI_TXCOMP) {
00123         outr(TWI_IDR, 0xFFFFFFFF);
00124         NutEventPostFromIrq(&tw_mm_que);
00125     }
00126     
00127     if (twsr & TWI_RXRDY) {
00128         if (tw_mr_idx < tw_mr_siz) {
00129             tw_mr_buf[tw_mr_idx++] = inb(TWI_RHR);
00130             /* The last byte will follow, just set the stop condition */
00131             if (tw_mr_idx == tw_mr_siz - 1) {
00132                 outr(TWI_CR, TWI_STOP);
00133             }
00134                 
00135             if (tw_mr_idx == tw_mr_siz) {
00136                 /* Last byte received. Send stop condition and set IRQs */
00137                 outr(TWI_IDR, TWI_RXRDY);
00138                 outr(TWI_IER, TWI_TXCOMP);
00139             }
00140         } 
00141     }
00142     
00143     if (twsr & TWI_TXRDY) {
00144         if (tw_mt_idx < tw_mt_len) {
00145             outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00146             /* Last byte? No bytes to read? So send stop condition else if bytes to read switch to read mode */
00147             if (tw_mt_idx == tw_mt_len) {
00148                 if (tw_mr_siz == 0) {
00149                     outr(TWI_CR, TWI_STOP);
00150                     outr(TWI_IDR, TWI_TXRDY);
00151                     outr(TWI_IER, TWI_TXCOMP);
00152                 } else {
00153                     /* Ok, now switch to read mode and send second start condition */
00154                     outr(TWI_MMR, inb(TWI_MMR) | TWI_MREAD);
00155                     outr(TWI_CR,  TWI_START | (tw_mr_siz == 1) ? TWI_STOP : 0);
00156                     outr(TWI_IDR, TWI_TXRDY);
00157                     outr(TWI_IER, TWI_RXRDY);
00158                 }
00159             }
00160         } 
00161     }
00162     
00163     /* We got a nack, stop transmission and wait for TWI_TXCOMP */
00164     if (twsr & TWI_NACK) {;
00165         /* send stop condition and wake up threads */
00166         outr(TWI_CR, TWI_STOP);
00167         tw_mm_err = TWERR_DATA_NACK;
00168         tw_mt_idx = 0;
00169         tw_mt_len = 0;
00170         tw_mr_siz = 0;
00171         outr(TWI_IDR, 0xFFFFFFFF);
00172         /* Wake up the application. */
00173         NutEventPostFromIrq(&tw_mm_que);
00174     }
00175 }
00176 
00203 int TwMasterTransact(uint8_t sla, CONST void *txdata, uint16_t txlen, void *rxdata, uint16_t rxsiz, uint32_t tmo)
00204 {
00205     int rc = -1;
00206 
00207     /* This routine is marked reentrant, so lock the interface. */
00208     if(NutEventWait(&tw_mm_mutex, 500)) {
00209         tw_mm_err = TWERR_IF_LOCKED;
00210         NutEventPost(&tw_mm_mutex);
00211         return -1;
00212     }
00213     NutIrqEnable(&sig_TWI);
00214 
00215     NutEnterCritical();
00216     /* Set all parameters for master mode. */
00217     tw_mm_sla = sla;
00218     tw_mm_err = 0;
00219     tw_mt_len = txlen;
00220     tw_mt_idx = 0;
00221     tw_mt_buf = txdata;
00222     tw_mr_siz = rxsiz;
00223     tw_mr_buf = rxdata;
00224     tw_mr_idx = 0;
00225 
00226     if ((tw_mt_len == 0) && (tw_mr_siz == 0)) return -1;
00227 
00228     /* Set slave address enable interrupts and start transmission */
00229     
00230     outr(TWI_MMR, (tw_mm_sla << 16) | (tw_mt_len == 0 ? TWI_MREAD : 0));
00231     
00232     /* Enable interrupts depending on read / write direction and data size */     
00233     if (tw_mt_len == 0) {  
00234         outr(TWI_IDR, TWI_TXRDY | TWI_TXCOMP);
00235         outr(TWI_IER, TWI_RXRDY | TWI_NACK);
00236     } else {
00237         outr(TWI_IDR, TWI_RXRDY);
00238         if ((tw_mt_len == 1) && (tw_mr_siz == 0)) {
00239             outr(TWI_IDR, TWI_TXRDY);
00240             outr(TWI_IER, TWI_TXCOMP);
00241         } else {            
00242             outr(TWI_IER, TWI_TXRDY);
00243             outr(TWI_IDR, TWI_TXCOMP);
00244         }
00245         outr(TWI_IER, TWI_NACK);        
00246     }
00247 
00248     /* Now start transmission if we have any data */
00249     if (tw_mt_len > 0) {
00250         outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00251     }     
00252     
00253     /* Send start condition. If read / write only one byte send stop as well */
00254     outr(TWI_CR, TWI_START | (((tw_mt_len == 1) && (tw_mr_siz == 0)) || 
00255                               ((tw_mt_len == 0) && (tw_mr_siz == 1))) ? TWI_STOP : 0);
00256         
00257     NutExitCritical();
00258         
00259     /* Wait for master transmission to be done. */
00260     rc = -1;
00261     if (NutEventWait(&tw_mm_que, tmo)) {
00262         tw_mm_error = TWERR_TIMEOUT;
00263     } else {
00264         NutEnterCritical();
00265         if (tw_mm_err) {
00266             tw_mm_error = tw_mm_err;
00267         } else {
00268             rc = tw_mr_idx;
00269         }
00270         NutExitCritical();
00271     }
00272 
00273     NutIrqDisable(&sig_TWI);
00274     
00275     /* Release the interface. */
00276     NutEventPost(&tw_mm_mutex);
00277     
00278     return rc;
00279 }
00280 
00290 int TwMasterError(void)
00291 {
00292     int rc = (int) tw_mm_error;
00293     tw_mm_error = 0;
00294     return rc;
00295 }
00296 
00312 int TwIOCtl(int req, void *conf)
00313 {
00314     int rc = 0;
00315     unsigned int cldiv, ckdiv;     
00316     unsigned int twi_clk;
00317     switch (req) {
00318 
00319     case TWI_SETSPEED:
00320         ckdiv=1 ;
00321         twi_clk = *((uint32_t *) conf);
00322 
00323         if (twi_clk > 400000) return -1;
00324         
00325         /*
00326          * CLDIV = ((Tlow x 2^CKDIV) -3) x Tmck
00327          * CHDIV = ((THigh x 2^CKDIV) -3) x Tmck
00328          * Only CLDIV is computed since CLDIV = CHDIV (50% duty cycle) 
00329          */
00330 
00331         while ((cldiv = ((NutGetCpuClock() / (2*twi_clk))-3 ) / (1 << ckdiv)) > 255) {
00332             ckdiv++;
00333         }
00334 
00335         /* BUG 41.2.7.1, datasheet SAM7X256  p. 626 */
00336         if (cldiv * (2 << ckdiv) > 8191) return -1; 
00337         
00338         outr(TWI_CWGR, (ckdiv << 16) | ((u_int) cldiv << 8) | (u_int) cldiv);
00339         break;
00340 
00341     case TWI_GETSPEED:
00342         ckdiv=1 ;
00343         twi_clk = *((uint32_t *) conf);
00344         
00345         cldiv = inr(TWI_CWGR) & 0x000000FF;
00346         ckdiv = (inr(TWI_CWGR) >> 16) & 0x00000007;
00347             
00348         *((uint32_t *) conf) = NutGetCpuClock() * ((cldiv * 2 << ckdiv) - 3);
00349         break;
00350 
00351     case TWI_GETSTATUS:
00352         break;
00353         
00354     case TWI_SETSTATUS:
00355         break;
00356 
00357     default:
00358         rc = -1;
00359         break;
00360     }
00361     return rc;
00362 }
00363 
00376 int TwInit(uint8_t sla)
00377 {
00378     uint32_t speed = 2400;
00379 
00380     if (NutRegisterIrqHandler(&sig_TWI, TwInterrupt, 0)) {
00381         return -1;
00382     }
00383 
00384     outr(TWI_PIO_ASR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Set TWD and TWCK as peripheral line
00385     outr(TWI_PIO_PDR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Let periperal control the PIO lines
00386     
00387     outr(TWI_PIO_MDER, _BV(TWI_TWD) | _BV(TWI_TWCK)); // Enabled OpenDrain output on both lines
00388     
00389     outr(PMC_PCER, _BV(TWI_ID));              // Enable TWI clock in PMC
00390     
00391     outr(TWI_IDR, 0xFFFFFFFF);                // Disable all interrupts 
00392     outr(TWI_CR, TWI_SWRST);                  // Reset bus
00393     outr(TWI_CR, TWI_MSEN | TWI_SVDIS);       // Enable master mode
00394     
00395     TwIOCtl(TWI_SETSPEED, &speed);
00396 
00397     /* Initialize mutex semaphores. */
00398     NutEventPost(&tw_mm_mutex);
00399 
00400     return 0;
00401 }

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