sbbif0.h

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00001 #ifndef _DEV_SBBIF0_H_
00002 #define _DEV_SBBIF0_H_
00003 /*
00004  * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * 1. Redistributions of source code must retain the above copyright
00011  *    notice, this list of conditions and the following disclaimer.
00012  * 2. Redistributions in binary form must reproduce the above copyright
00013  *    notice, this list of conditions and the following disclaimer in the
00014  *    documentation and/or other materials provided with the distribution.
00015  * 3. Neither the name of the copyright holders nor the names of
00016  *    contributors may be used to endorse or promote products derived
00017  *    from this software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00020  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00021  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00022  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00023  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00024  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00025  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00026  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00027  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00028  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00029  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00030  * SUCH DAMAGE.
00031  *
00032  * For additional information see http://www.ethernut.de/
00033  */
00034 
00055 #include <cfg/arch/gpio.h>
00056 #include <stdint.h>
00057 
00061 #ifndef SBBI0_MAX_DEVICES
00062 #define SBBI0_MAX_DEVICES   4
00063 #endif
00064 
00065 #if defined(__AVR__)            /* MCU */
00066 /*
00067  * AVR implementation.
00068  * ======================================
00069  */
00070 
00071 #ifdef SBBI0_CS0_BIT
00072 
00073 #if (SBBI0_CS0_PORT == AVRPORTB)
00074 #define SBBI0_CS0_SOD_REG PORTB
00075 #define SBBI0_CS0_OE_REG  DDRB
00076 #elif (SBBI0_CS0_PORT == AVRPORTD)
00077 #define SBBI0_CS0_SOD_REG PORTD
00078 #define SBBI0_CS0_OE_REG  DDRD
00079 #elif (SBBI0_CS0_PORT == AVRPORTE)
00080 #define SBBI0_CS0_SOD_REG PORTE
00081 #define SBBI0_CS0_OE_REG  DDRE
00082 #elif (SBBI0_CS0_PORT == AVRPORTF)
00083 #define SBBI0_CS0_SOD_REG PORTF
00084 #define SBBI0_CS0_OE_REG  DDRF
00085 #elif (SBBI0_CS0_PORT == AVRPORTG)
00086 #define SBBI0_CS0_SOD_REG PORTG
00087 #define SBBI0_CS0_OE_REG  DDRG
00088 #elif (SBBI0_CS0_PORT == AVRPORTH)
00089 #define SBBI0_CS0_SOD_REG PORTH
00090 #define SBBI0_CS0_OE_REG  DDRH
00091 #endif
00092 
00094 #define SBBI0_CS0_ENA()      sbi(SBBI0_CS0_OE_REG, SBBI0_CS0_BIT)
00095 
00096 #define SBBI0_CS0_CLR()      cbi(SBBI0_CS0_SOD_REG, SBBI0_CS0_BIT)
00097 
00098 #define SBBI0_CS0_SET()      sbi(SBBI0_CS0_SOD_REG, SBBI0_CS0_BIT)
00099 
00100 #else /* SBBI0_CS0_BIT */
00101 
00102 #define SBBI0_CS0_ENA()
00103 #define SBBI0_CS0_CLR()
00104 #define SBBI0_CS0_SET()
00105 
00106 #endif /* SBBI0_CS0_BIT */
00107 
00108 #ifdef SBBI0_CS1_BIT
00109 
00110 #if (SBBI0_CS1_PORT == AVRPORTB)
00111 #define SBBI0_CS1_SOD_REG PORTB
00112 #define SBBI0_CS1_OE_REG  DDRB
00113 #elif (SBBI0_CS1_PORT == AVRPORTD)
00114 #define SBBI0_CS1_SOD_REG PORTD
00115 #define SBBI0_CS1_OE_REG  DDRD
00116 #elif (SBBI0_CS1_PORT == AVRPORTE)
00117 #define SBBI0_CS1_SOD_REG PORTE
00118 #define SBBI0_CS1_OE_REG  DDRE
00119 #elif (SBBI0_CS1_PORT == AVRPORTF)
00120 #define SBBI0_CS1_SOD_REG PORTF
00121 #define SBBI0_CS1_OE_REG  DDRF
00122 #elif (SBBI0_CS1_PORT == AVRPORTG)
00123 #define SBBI0_CS1_SOD_REG PORTG
00124 #define SBBI0_CS1_OE_REG  DDRG
00125 #elif (SBBI0_CS1_PORT == AVRPORTH)
00126 #define SBBI0_CS1_SOD_REG PORTH
00127 #define SBBI0_CS1_OE_REG  DDRH
00128 #endif
00129 
00131 #define SBBI0_CS1_ENA()      sbi(SBBI0_CS1_OE_REG, SBBI0_CS1_BIT)
00132 
00133 #define SBBI0_CS1_CLR()      cbi(SBBI0_CS1_SOD_REG, SBBI0_CS1_BIT)
00134 
00135 #define SBBI0_CS1_SET()      sbi(SBBI0_CS1_SOD_REG, SBBI0_CS1_BIT)
00136 
00137 #else /* SBBI0_CS1_BIT */
00138 
00139 #define SBBI0_CS1_ENA()
00140 #define SBBI0_CS1_CLR()
00141 #define SBBI0_CS1_SET()
00142 
00143 #endif /* SBBI0_CS1_BIT */
00144 
00145 #ifdef SBBI0_CS2_BIT
00146 
00147 #if (SBBI0_CS2_PORT == AVRPORTB)
00148 #define SBBI0_CS2_SOD_REG PORTB
00149 #define SBBI0_CS2_OE_REG  DDRB
00150 #elif (SBBI0_CS2_PORT == AVRPORTD)
00151 #define SBBI0_CS2_SOD_REG PORTD
00152 #define SBBI0_CS2_OE_REG  DDRD
00153 #elif (SBBI0_CS2_PORT == AVRPORTE)
00154 #define SBBI0_CS2_SOD_REG PORTE
00155 #define SBBI0_CS2_OE_REG  DDRE
00156 #elif (SBBI0_CS2_PORT == AVRPORTF)
00157 #define SBBI0_CS2_SOD_REG PORTF
00158 #define SBBI0_CS2_OE_REG  DDRF
00159 #elif (SBBI0_CS2_PORT == AVRPORTG)
00160 #define SBBI0_CS2_SOD_REG PORTG
00161 #define SBBI0_CS2_OE_REG  DDRG
00162 #elif (SBBI0_CS2_PORT == AVRPORTH)
00163 #define SBBI0_CS2_SOD_REG PORTH
00164 #define SBBI0_CS2_OE_REG  DDRH
00165 #endif
00166 
00168 #define SBBI0_CS2_ENA()      sbi(SBBI0_CS2_OE_REG, SBBI0_CS2_BIT)
00169 
00170 #define SBBI0_CS2_CLR()      cbi(SBBI0_CS2_SOD_REG, SBBI0_CS2_BIT)
00171 
00172 #define SBBI0_CS2_SET()      sbi(SBBI0_CS2_SOD_REG, SBBI0_CS2_BIT)
00173 
00174 #else /* SBBI0_CS2_BIT */
00175 
00176 #define SBBI0_CS2_ENA()
00177 #define SBBI0_CS2_CLR()
00178 #define SBBI0_CS2_SET()
00179 
00180 #endif /* SBBI0_CS2_BIT */
00181 
00182 #ifdef SBBI0_CS3_BIT
00183 
00184 #if (SBBI0_CS3_PORT == AVRPORTB)
00185 #define SBBI0_CS3_SOD_REG PORTB
00186 #define SBBI0_CS3_OE_REG  DDRB
00187 #elif (SBBI0_CS3_PORT == AVRPORTD)
00188 #define SBBI0_CS3_SOD_REG PORTD
00189 #define SBBI0_CS3_OE_REG  DDRD
00190 #elif (SBBI0_CS3_PORT == AVRPORTE)
00191 #define SBBI0_CS3_SOD_REG PORTE
00192 #define SBBI0_CS3_OE_REG  DDRE
00193 #elif (SBBI0_CS3_PORT == AVRPORTF)
00194 #define SBBI0_CS3_SOD_REG PORTF
00195 #define SBBI0_CS3_OE_REG  DDRF
00196 #elif (SBBI0_CS3_PORT == AVRPORTG)
00197 #define SBBI0_CS3_SOD_REG PORTG
00198 #define SBBI0_CS3_OE_REG  DDRG
00199 #elif (SBBI0_CS3_PORT == AVRPORTH)
00200 #define SBBI0_CS3_SOD_REG PORTH
00201 #define SBBI0_CS3_OE_REG  DDRH
00202 #endif
00203 
00205 #define SBBI0_CS3_ENA()      sbi(SBBI0_CS3_OE_REG, SBBI0_CS3_BIT)
00206 
00207 #define SBBI0_CS3_CLR()      cbi(SBBI0_CS3_SOD_REG, SBBI0_CS3_BIT)
00208 
00209 #define SBBI0_CS3_SET()      sbi(SBBI0_CS3_SOD_REG, SBBI0_CS3_BIT)
00210 
00211 #else /* SBBI0_CS3_BIT */
00212 
00213 #define SBBI0_CS3_ENA()
00214 #define SBBI0_CS3_CLR()
00215 #define SBBI0_CS3_SET()
00216 
00217 #endif /* SBBI0_CS3_BIT */
00218 
00219 #ifdef SBBI0_RST0_BIT
00220 
00221 #if (SBBI0_RST0_PORT == AVRPORTB)
00222 #define SBBI0_RST0_SOD_REG PORTB
00223 #define SBBI0_RST0_OE_REG  DDRB
00224 #elif (SBBI0_RST0_PORT == AVRPORTD)
00225 #define SBBI0_RST0_SOD_REG PORTD
00226 #define SBBI0_RST0_OE_REG  DDRD
00227 #elif (SBBI0_RST0_PORT == AVRPORTE)
00228 #define SBBI0_RST0_SOD_REG PORTE
00229 #define SBBI0_RST0_OE_REG  DDRE
00230 #elif (SBBI0_RST0_PORT == AVRPORTF)
00231 #define SBBI0_RST0_SOD_REG PORTF
00232 #define SBBI0_RST0_OE_REG  DDRF
00233 #elif (SBBI0_RST0_PORT == AVRPORTG)
00234 #define SBBI0_RST0_SOD_REG PORTG
00235 #define SBBI0_RST0_OE_REG  DDRG
00236 #elif (SBBI0_RST0_PORT == AVRPORTH)
00237 #define SBBI0_RST0_SOD_REG PORTH
00238 #define SBBI0_RST0_OE_REG  DDRH
00239 #endif
00240 
00242 #define SBBI0_RST0_ENA()      sbi(SBBI0_RST0_OE_REG, SBBI0_RST0_BIT)
00243 
00244 #define SBBI0_RST0_CLR()      cbi(SBBI0_RST0_SOD_REG, SBBI0_RST0_BIT)
00245 
00246 #define SBBI0_RST0_SET()      sbi(SBBI0_RST0_SOD_REG, SBBI0_RST0_BIT)
00247 
00248 #else /* SBBI0_RST0_BIT */
00249 
00250 #define SBBI0_RST0_ENA()
00251 #define SBBI0_RST0_CLR()
00252 #define SBBI0_RST0_SET()
00253 
00254 #endif /* SBBI0_RST0_BIT */
00255 
00256 #ifdef SBBI0_RST1_BIT
00257 
00258 #if (SBBI0_RST1_PORT == AVRPORTB)
00259 #define SBBI0_RST1_SOD_REG PORTB
00260 #define SBBI0_RST1_OE_REG  DDRB
00261 #elif (SBBI0_RST1_PORT == AVRPORTD)
00262 #define SBBI0_RST1_SOD_REG PORTD
00263 #define SBBI0_RST1_OE_REG  DDRD
00264 #elif (SBBI0_RST1_PORT == AVRPORTE)
00265 #define SBBI0_RST1_SOD_REG PORTE
00266 #define SBBI0_RST1_OE_REG  DDRE
00267 #elif (SBBI0_RST1_PORT == AVRPORTF)
00268 #define SBBI0_RST1_SOD_REG PORTF
00269 #define SBBI0_RST1_OE_REG  DDRF
00270 #elif (SBBI0_RST1_PORT == AVRPORTG)
00271 #define SBBI0_RST1_SOD_REG PORTG
00272 #define SBBI0_RST1_OE_REG  DDRG
00273 #elif (SBBI0_RST1_PORT == AVRPORTH)
00274 #define SBBI0_RST1_SOD_REG PORTH
00275 #define SBBI0_RST1_OE_REG  DDRH
00276 #endif
00277 
00279 #define SBBI0_RST1_ENA()      sbi(SBBI0_RST1_OE_REG, SBBI0_RST1_BIT)
00280 
00281 #define SBBI0_RST1_CLR()      cbi(SBBI0_RST1_SOD_REG, SBBI0_RST1_BIT)
00282 
00283 #define SBBI0_RST1_SET()      sbi(SBBI0_RST1_SOD_REG, SBBI0_RST1_BIT)
00284 
00285 #else /* SBBI0_RST1_BIT */
00286 
00287 #define SBBI0_RST1_ENA()
00288 #define SBBI0_RST1_CLR()
00289 #define SBBI0_RST1_SET()
00290 
00291 #endif /* SBBI0_RST1_BIT */
00292 
00293 #ifdef SBBI0_RST2_BIT
00294 
00295 #if (SBBI0_RST2_PORT == AVRPORTB)
00296 #define SBBI0_RST2_SOD_REG PORTB
00297 #define SBBI0_RST2_OE_REG  DDRB
00298 #elif (SBBI0_RST2_PORT == AVRPORTD)
00299 #define SBBI0_RST2_SOD_REG PORTD
00300 #define SBBI0_RST2_OE_REG  DDRD
00301 #elif (SBBI0_RST2_PORT == AVRPORTE)
00302 #define SBBI0_RST2_SOD_REG PORTE
00303 #define SBBI0_RST2_OE_REG  DDRE
00304 #elif (SBBI0_RST2_PORT == AVRPORTF)
00305 #define SBBI0_RST2_SOD_REG PORTF
00306 #define SBBI0_RST2_OE_REG  DDRF
00307 #elif (SBBI0_RST2_PORT == AVRPORTG)
00308 #define SBBI0_RST2_SOD_REG PORTG
00309 #define SBBI0_RST2_OE_REG  DDRG
00310 #elif (SBBI0_RST2_PORT == AVRPORTH)
00311 #define SBBI0_RST2_SOD_REG PORTH
00312 #define SBBI0_RST2_OE_REG  DDRH
00313 #endif
00314 
00316 #define SBBI0_RST2_ENA()      sbi(SBBI0_RST2_OE_REG, SBBI0_RST2_BIT)
00317 
00318 #define SBBI0_RST2_CLR()      cbi(SBBI0_RST2_SOD_REG, SBBI0_RST2_BIT)
00319 
00320 #define SBBI0_RST2_SET()      sbi(SBBI0_RST2_SOD_REG, SBBI0_RST2_BIT)
00321 
00322 #else /* SBBI0_RST2_BIT */
00323 
00324 #define SBBI0_RST2_ENA()
00325 #define SBBI0_RST2_CLR()
00326 #define SBBI0_RST2_SET()
00327 
00328 #endif /* SBBI0_RST2_BIT */
00329 
00330 #ifdef SBBI0_RST3_BIT
00331 
00332 #if (SBBI0_RST3_PORT == AVRPORTB)
00333 #define SBBI0_RST3_SOD_REG PORTB
00334 #define SBBI0_RST3_OE_REG  DDRB
00335 #elif (SBBI0_RST3_PORT == AVRPORTD)
00336 #define SBBI0_RST3_SOD_REG PORTD
00337 #define SBBI0_RST3_OE_REG  DDRD
00338 #elif (SBBI0_RST3_PORT == AVRPORTE)
00339 #define SBBI0_RST3_SOD_REG PORTE
00340 #define SBBI0_RST3_OE_REG  DDRE
00341 #elif (SBBI0_RST3_PORT == AVRPORTF)
00342 #define SBBI0_RST3_SOD_REG PORTF
00343 #define SBBI0_RST3_OE_REG  DDRF
00344 #elif (SBBI0_RST3_PORT == AVRPORTG)
00345 #define SBBI0_RST3_SOD_REG PORTG
00346 #define SBBI0_RST3_OE_REG  DDRG
00347 #elif (SBBI0_RST3_PORT == AVRPORTH)
00348 #define SBBI0_RST3_SOD_REG PORTH
00349 #define SBBI0_RST3_OE_REG  DDRH
00350 #endif
00351 
00353 #define SBBI0_RST3_ENA()      sbi(SBBI0_RST3_OE_REG, SBBI0_RST3_BIT)
00354 
00355 #define SBBI0_RST3_CLR()      cbi(SBBI0_RST3_SOD_REG, SBBI0_RST3_BIT)
00356 
00357 #define SBBI0_RST3_SET()      sbi(SBBI0_RST3_SOD_REG, SBBI0_RST3_BIT)
00358 
00359 #else /* SBBI0_RST3_BIT */
00360 
00361 #define SBBI0_RST3_ENA()
00362 #define SBBI0_RST3_CLR()
00363 #define SBBI0_RST3_SET()
00364 
00365 #endif /* SBBI0_RST3_BIT */
00366 
00367 #ifdef SBBI0_SCK_BIT
00368 
00369 #if (SBBI0_SCK_PORT == AVRPORTB)
00370 #define SBBI0_SCK_SOD_REG PORTB
00371 #define SBBI0_SCK_OE_REG  DDRB
00372 #elif (SBBI0_SCK_PORT == AVRPORTD)
00373 #define SBBI0_SCK_SOD_REG PORTD
00374 #define SBBI0_SCK_OE_REG  DDRD
00375 #elif (SBBI0_SCK_PORT == AVRPORTE)
00376 #define SBBI0_SCK_SOD_REG PORTE
00377 #define SBBI0_SCK_OE_REG  DDRE
00378 #elif (SBBI0_SCK_PORT == AVRPORTF)
00379 #define SBBI0_SCK_SOD_REG PORTF
00380 #define SBBI0_SCK_OE_REG  DDRF
00381 #elif (SBBI0_SCK_PORT == AVRPORTG)
00382 #define SBBI0_SCK_SOD_REG PORTG
00383 #define SBBI0_SCK_OE_REG  DDRG
00384 #elif (SBBI0_SCK_PORT == AVRPORTH)
00385 #define SBBI0_SCK_SOD_REG PORTH
00386 #define SBBI0_SCK_OE_REG  DDRH
00387 #endif
00388 
00390 #define SBBI0_SCK_ENA()      sbi(SBBI0_SCK_OE_REG, SBBI0_SCK_BIT)
00391 
00392 #define SBBI0_SCK_CLR()      cbi(SBBI0_SCK_SOD_REG, SBBI0_SCK_BIT)
00393 
00394 #define SBBI0_SCK_SET()      sbi(SBBI0_SCK_SOD_REG, SBBI0_SCK_BIT)
00395 
00396 #if defined(SBBI0_MOSI_BIT)
00397 
00398 #if (SBBI0_MOSI_PORT == AVRPORTB)
00399 #define SBBI0_MOSI_SOD_REG PORTB
00400 #define SBBI0_MOSI_OE_REG  DDRB
00401 #elif (SBBI0_MOSI_PORT == AVRPORTD)
00402 #define SBBI0_MOSI_SOD_REG PORTD
00403 #define SBBI0_MOSI_OE_REG  DDRD
00404 #elif (SBBI0_MOSI_PORT == AVRPORTE)
00405 #define SBBI0_MOSI_SOD_REG PORTE
00406 #define SBBI0_MOSI_OE_REG  DDRE
00407 #elif (SBBI0_MOSI_PORT == AVRPORTF)
00408 #define SBBI0_MOSI_SOD_REG PORTF
00409 #define SBBI0_MOSI_OE_REG  DDRF
00410 #elif (SBBI0_MOSI_PORT == AVRPORTG)
00411 #define SBBI0_MOSI_SOD_REG PORTG
00412 #define SBBI0_MOSI_OE_REG  DDRG
00413 #elif (SBBI0_MOSI_PORT == AVRPORTH)
00414 #define SBBI0_MOSI_SOD_REG PORTH
00415 #define SBBI0_MOSI_OE_REG  DDRH
00416 #endif
00417 
00419 #define SBBI0_MOSI_ENA()      sbi(SBBI0_MOSI_OE_REG, SBBI0_MOSI_BIT)
00420 
00421 #define SBBI0_MOSI_CLR()      cbi(SBBI0_MOSI_SOD_REG, SBBI0_MOSI_BIT)
00422 
00423 #define SBBI0_MOSI_SET()      sbi(SBBI0_MOSI_SOD_REG, SBBI0_MOSI_BIT)
00424 
00425 #else                           /* SBBI0_MOSI_BIT */
00426 
00427 #define SBBI0_MOSI_ENA()
00428 #define SBBI0_MOSI_CLR()
00429 #define SBBI0_MOSI_SET()
00430 
00431 #endif                          /* SBBI0_MOSI_BIT */
00432 
00433 #if defined(SBBI0_MISO_BIT)
00434 
00435 #if (SBBI0_MISO_PORT == AVRPORTB)
00436 #define SBBI0_MISO_PDS_REG PINB
00437 #define SBBI0_MISO_PUE_REG PORTB
00438 #define SBBI0_MISO_OE_REG  DDRB
00439 #elif (SBBI0_MISO_PORT == AVRPORTD)
00440 #define SBBI0_MISO_PDS_REG PIND
00441 #define SBBI0_MISO_PUE_REG PORTD
00442 #define SBBI0_MISO_OE_REG  DDRD
00443 #elif (SBBI0_MISO_PORT == AVRPORTE)
00444 #define SBBI0_MISO_PDS_REG PINE
00445 #define SBBI0_MISO_PUE_REG PORTE
00446 #define SBBI0_MISO_OE_REG  DDRE
00447 #elif (SBBI0_MISO_PORT == AVRPORTF)
00448 #define SBBI0_MISO_PDS_REG PINF
00449 #define SBBI0_MISO_PUE_REG PORTF
00450 #define SBBI0_MISO_OE_REG  DDRF
00451 #elif (SBBI0_MISO_PORT == AVRPORTG)
00452 #define SBBI0_MISO_PDS_REG PING
00453 #define SBBI0_MISO_PUE_REG PORTG
00454 #define SBBI0_MISO_OE_REG  DDRG
00455 #elif (SBBI0_MISO_PORT == AVRPORTH)
00456 #define SBBI0_MISO_PDS_REG PINH
00457 #define SBBI0_MISO_PUE_REG PORTH
00458 #define SBBI0_MISO_OE_REG  DDRH
00459 #endif
00460 
00462 #define SBBI0_MISO_ENA() \
00463     cbi(SBBI0_MISO_OE_REG, SBBI0_MISO_BIT); \
00464     sbi(SBBI0_MISO_PUE_REG, SBBI0_MISO_BIT)
00465 
00466 #define SBBI0_MISO_TST()    ((inb(SBBI0_MISO_PDS_REG) & _BV(SBBI0_MISO_BIT)) == _BV(SBBI0_MISO_BIT))
00467 
00468 #else                           /* SBBI0_MISO_BIT */
00469 
00470 #define SBBI0_MISO_ENA()
00471 #define SBBI0_MISO_TST()   0
00472 
00473 #endif                          /* SBBI0_MISO_BIT */
00474 
00475 #else                           /* SBBI0_SCK_BIT */
00476 
00477 #define SBBI0_SCK_ENA()
00478 #define SBBI0_SCK_CLR()
00479 #define SBBI0_SCK_SET()
00480 
00481 #define SBBI0_MOSI_ENA()
00482 #define SBBI0_MOSI_CLR()
00483 #define SBBI0_MOSI_SET()
00484 
00485 #define SBBI0_MISO_ENA()
00486 #define SBBI0_MISO_TST()   0
00487 
00488 #endif                          /* SBBI0_SCK_BIT */
00489 
00490 #else                           /* MCU */
00491 /*
00492  * AT91 implementation.
00493  * ======================================
00494  */
00495 
00496 #ifdef SBBI0_CS0_BIT
00497 
00498 #if !defined(SBBI0_CS0_PIO_ID)
00499 #define SBBI0_CS0_PE_REG        PIO_PER
00500 #define SBBI0_CS0_OE_REG        PIO_OER
00501 #define SBBI0_CS0_COD_REG       PIO_CODR
00502 #define SBBI0_CS0_SOD_REG       PIO_SODR
00503 #elif SBBI0_CS0_PIO_ID == PIO_ID
00504 #define SBBI0_CS0_PE_REG        PIO_PER
00505 #define SBBI0_CS0_OE_REG        PIO_OER
00506 #define SBBI0_CS0_COD_REG       PIO_CODR
00507 #define SBBI0_CS0_SOD_REG       PIO_SODR
00508 #elif SBBI0_CS0_PIO_ID == PIOA_ID
00509 #define SBBI0_CS0_PE_REG        PIOA_PER
00510 #define SBBI0_CS0_OE_REG        PIOA_OER
00511 #define SBBI0_CS0_COD_REG       PIOA_CODR
00512 #define SBBI0_CS0_SOD_REG       PIOA_SODR
00513 #elif SBBI0_CS0_PIO_ID == PIOB_ID
00514 #define SBBI0_CS0_PE_REG        PIOB_PER
00515 #define SBBI0_CS0_OE_REG        PIOB_OER
00516 #define SBBI0_CS0_COD_REG       PIOB_CODR
00517 #define SBBI0_CS0_SOD_REG       PIOB_SODR
00518 #elif SBBI0_CS0_PIO_ID == PIOC_ID
00519 #define SBBI0_CS0_PE_REG        PIOC_PER
00520 #define SBBI0_CS0_OE_REG        PIOC_OER
00521 #define SBBI0_CS0_COD_REG       PIOC_CODR
00522 #define SBBI0_CS0_SOD_REG       PIOC_SODR
00523 #endif
00524 
00526 #define SBBI0_CS0_ENA() \
00527     outr(SBBI0_CS0_PE_REG, _BV(SBBI0_CS0_BIT)); \
00528     outr(SBBI0_CS0_OE_REG, _BV(SBBI0_CS0_BIT))
00529 
00530 #define SBBI0_CS0_CLR()   outr(SBBI0_CS0_COD_REG, _BV(SBBI0_CS0_BIT))
00531 
00532 #define SBBI0_CS0_SET()   outr(SBBI0_CS0_SOD_REG, _BV(SBBI0_CS0_BIT))
00533 
00534 #else /* SBBI0_CS0_BIT */
00535 
00536 #define SBBI0_CS0_ENA()
00537 #define SBBI0_CS0_CLR()
00538 #define SBBI0_CS0_SET()
00539 
00540 #endif /* SBBI0_CS0_BIT */
00541 
00542 #ifdef SBBI0_CS1_BIT
00543 
00544 #if !defined(SBBI0_CS1_PIO_ID)
00545 #define SBBI0_CS1_PE_REG        PIO_PER
00546 #define SBBI0_CS1_OE_REG        PIO_OER
00547 #define SBBI0_CS1_COD_REG       PIO_CODR
00548 #define SBBI0_CS1_SOD_REG       PIO_SODR
00549 #elif SBBI0_CS1_PIO_ID == PIO_ID
00550 #define SBBI0_CS1_PE_REG        PIO_PER
00551 #define SBBI0_CS1_OE_REG        PIO_OER
00552 #define SBBI0_CS1_COD_REG       PIO_CODR
00553 #define SBBI0_CS1_SOD_REG       PIO_SODR
00554 #elif SBBI0_CS1_PIO_ID == PIOA_ID
00555 #define SBBI0_CS1_PE_REG        PIOA_PER
00556 #define SBBI0_CS1_OE_REG        PIOA_OER
00557 #define SBBI0_CS1_COD_REG       PIOA_CODR
00558 #define SBBI0_CS1_SOD_REG       PIOA_SODR
00559 #elif SBBI0_CS1_PIO_ID == PIOB_ID
00560 #define SBBI0_CS1_PE_REG        PIOB_PER
00561 #define SBBI0_CS1_OE_REG        PIOB_OER
00562 #define SBBI0_CS1_COD_REG       PIOB_CODR
00563 #define SBBI0_CS1_SOD_REG       PIOB_SODR
00564 #elif SBBI0_CS1_PIO_ID == PIOC_ID
00565 #define SBBI0_CS1_PE_REG        PIOC_PER
00566 #define SBBI0_CS1_OE_REG        PIOC_OER
00567 #define SBBI0_CS1_COD_REG       PIOC_CODR
00568 #define SBBI0_CS1_SOD_REG       PIOC_SODR
00569 #endif
00570 
00572 #define SBBI0_CS1_ENA() \
00573     outr(SBBI0_CS1_PE_REG, _BV(SBBI0_CS1_BIT)); \
00574     outr(SBBI0_CS1_OE_REG, _BV(SBBI0_CS1_BIT))
00575 
00576 #define SBBI0_CS1_CLR()   outr(SBBI0_CS1_COD_REG, _BV(SBBI0_CS1_BIT))
00577 
00578 #define SBBI0_CS1_SET()   outr(SBBI0_CS1_SOD_REG, _BV(SBBI0_CS1_BIT))
00579 
00580 #else /* SBBI0_CS1_BIT */
00581 
00582 #define SBBI0_CS1_ENA()
00583 #define SBBI0_CS1_CLR()
00584 #define SBBI0_CS1_SET()
00585 
00586 #endif /* SBBI0_CS1_BIT */
00587 
00588 #ifdef SBBI0_CS2_BIT
00589 
00590 #if !defined(SBBI0_CS2_PIO_ID)
00591 #define SBBI0_CS2_PE_REG        PIO_PER
00592 #define SBBI0_CS2_OE_REG        PIO_OER
00593 #define SBBI0_CS2_COD_REG       PIO_CODR
00594 #define SBBI0_CS2_SOD_REG       PIO_SODR
00595 #elif SBBI0_CS2_PIO_ID == PIO_ID
00596 #define SBBI0_CS2_PE_REG        PIO_PER
00597 #define SBBI0_CS2_OE_REG        PIO_OER
00598 #define SBBI0_CS2_COD_REG       PIO_CODR
00599 #define SBBI0_CS2_SOD_REG       PIO_SODR
00600 #elif SBBI0_CS2_PIO_ID == PIOA_ID
00601 #define SBBI0_CS2_PE_REG        PIOA_PER
00602 #define SBBI0_CS2_OE_REG        PIOA_OER
00603 #define SBBI0_CS2_COD_REG       PIOA_CODR
00604 #define SBBI0_CS2_SOD_REG       PIOA_SODR
00605 #elif SBBI0_CS2_PIO_ID == PIOB_ID
00606 #define SBBI0_CS2_PE_REG        PIOB_PER
00607 #define SBBI0_CS2_OE_REG        PIOB_OER
00608 #define SBBI0_CS2_COD_REG       PIOB_CODR
00609 #define SBBI0_CS2_SOD_REG       PIOB_SODR
00610 #elif SBBI0_CS2_PIO_ID == PIOC_ID
00611 #define SBBI0_CS2_PE_REG        PIOC_PER
00612 #define SBBI0_CS2_OE_REG        PIOC_OER
00613 #define SBBI0_CS2_COD_REG       PIOC_CODR
00614 #define SBBI0_CS2_SOD_REG       PIOC_SODR
00615 #endif
00616 
00618 #define SBBI0_CS2_ENA() \
00619     outr(SBBI0_CS2_PE_REG, _BV(SBBI0_CS2_BIT)); \
00620     outr(SBBI0_CS2_OE_REG, _BV(SBBI0_CS2_BIT))
00621 
00622 #define SBBI0_CS2_CLR()   outr(SBBI0_CS2_COD_REG, _BV(SBBI0_CS2_BIT))
00623 
00624 #define SBBI0_CS2_SET()   outr(SBBI0_CS2_SOD_REG, _BV(SBBI0_CS2_BIT))
00625 
00626 #else /* SBBI0_CS2_BIT */
00627 
00628 #define SBBI0_CS2_ENA()
00629 #define SBBI0_CS2_CLR()
00630 #define SBBI0_CS2_SET()
00631 
00632 #endif /* SBBI0_CS2_BIT */
00633 
00634 #ifdef SBBI0_CS3_BIT
00635 
00636 #if !defined(SBBI0_CS3_PIO_ID)
00637 #define SBBI0_CS3_PE_REG        PIO_PER
00638 #define SBBI0_CS3_OE_REG        PIO_OER
00639 #define SBBI0_CS3_COD_REG       PIO_CODR
00640 #define SBBI0_CS3_SOD_REG       PIO_SODR
00641 #elif SBBI0_CS3_PIO_ID == PIO_ID
00642 #define SBBI0_CS3_PE_REG        PIO_PER
00643 #define SBBI0_CS3_OE_REG        PIO_OER
00644 #define SBBI0_CS3_COD_REG       PIO_CODR
00645 #define SBBI0_CS3_SOD_REG       PIO_SODR
00646 #elif SBBI0_CS3_PIO_ID == PIOA_ID
00647 #define SBBI0_CS3_PE_REG        PIOA_PER
00648 #define SBBI0_CS3_OE_REG        PIOA_OER
00649 #define SBBI0_CS3_COD_REG       PIOA_CODR
00650 #define SBBI0_CS3_SOD_REG       PIOA_SODR
00651 #elif SBBI0_CS3_PIO_ID == PIOB_ID
00652 #define SBBI0_CS3_PE_REG        PIOB_PER
00653 #define SBBI0_CS3_OE_REG        PIOB_OER
00654 #define SBBI0_CS3_COD_REG       PIOB_CODR
00655 #define SBBI0_CS3_SOD_REG       PIOB_SODR
00656 #elif SBBI0_CS3_PIO_ID == PIOC_ID
00657 #define SBBI0_CS3_PE_REG        PIOC_PER
00658 #define SBBI0_CS3_OE_REG        PIOC_OER
00659 #define SBBI0_CS3_COD_REG       PIOC_CODR
00660 #define SBBI0_CS3_SOD_REG       PIOC_SODR
00661 #endif
00662 
00664 #define SBBI0_CS3_ENA() \
00665     outr(SBBI0_CS3_PE_REG, _BV(SBBI0_CS3_BIT)); \
00666     outr(SBBI0_CS3_OE_REG, _BV(SBBI0_CS3_BIT))
00667 
00668 #define SBBI0_CS3_CLR()   outr(SBBI0_CS3_COD_REG, _BV(SBBI0_CS3_BIT))
00669 
00670 #define SBBI0_CS3_SET()   outr(SBBI0_CS3_SOD_REG, _BV(SBBI0_CS3_BIT))
00671 
00672 #else /* SBBI0_CS3_BIT */
00673 
00674 #define SBBI0_CS3_ENA()
00675 #define SBBI0_CS3_CLR()
00676 #define SBBI0_CS3_SET()
00677 
00678 #endif /* SBBI0_CS3_BIT */
00679 
00680 #ifdef SBBI0_RST0_BIT
00681 
00682 #if !defined(SBBI0_RST0_PIO_ID)
00683 #define SBBI0_RST0_PE_REG      PIO_PER
00684 #define SBBI0_RST0_OE_REG      PIO_OER
00685 #define SBBI0_RST0_COD_REG     PIO_CODR
00686 #define SBBI0_RST0_SOD_REG     PIO_SODR
00687 #elif SBBI0_RST0_PIO_ID == PIO_ID
00688 #define SBBI0_RST0_PE_REG      PIO_PER
00689 #define SBBI0_RST0_OE_REG      PIO_OER
00690 #define SBBI0_RST0_COD_REG     PIO_CODR
00691 #define SBBI0_RST0_SOD_REG     PIO_SODR
00692 #elif SBBI0_RST0_PIO_ID == PIOA_ID
00693 #define SBBI0_RST0_PE_REG      PIOA_PER
00694 #define SBBI0_RST0_OE_REG      PIOA_OER
00695 #define SBBI0_RST0_COD_REG     PIOA_CODR
00696 #define SBBI0_RST0_SOD_REG     PIOA_SODR
00697 #elif SBBI0_RST0_PIO_ID == PIOB_ID
00698 #define SBBI0_RST0_PE_REG      PIOB_PER
00699 #define SBBI0_RST0_OE_REG      PIOB_OER
00700 #define SBBI0_RST0_COD_REG     PIOB_CODR
00701 #define SBBI0_RST0_SOD_REG     PIOB_SODR
00702 #elif SBBI0_RST0_PIO_ID == PIOC_ID
00703 #define SBBI0_RST0_PE_REG      PIOC_PER
00704 #define SBBI0_RST0_OE_REG      PIOC_OER
00705 #define SBBI0_RST0_COD_REG     PIOC_CODR
00706 #define SBBI0_RST0_SOD_REG     PIOC_SODR
00707 #endif
00708 
00710 #define SBBI0_RST0_ENA() \
00711     outr(SBBI0_RST0_PE_REG, _BV(SBBI0_RST0_BIT)); \
00712     outr(SBBI0_RST0_OE_REG, _BV(SBBI0_RST0_BIT))
00713 
00714 #define SBBI0_RST0_CLR()   outr(SBBI0_RST0_COD_REG, _BV(SBBI0_RST0_BIT))
00715 
00716 #define SBBI0_RST0_SET()   outr(SBBI0_RST0_SOD_REG, _BV(SBBI0_RST0_BIT))
00717 
00718 #else /* SBBI0_RST0_BIT */
00719 
00720 #define SBBI0_RST0_ENA()
00721 #define SBBI0_RST0_CLR()
00722 #define SBBI0_RST0_SET()
00723 
00724 #endif /* SBBI0_RST0_BIT */
00725 
00726 #ifdef SBBI0_RST1_BIT
00727 
00728 #if !defined(SBBI0_RST1_PIO_ID)
00729 #define SBBI0_RST1_PE_REG      PIO_PER
00730 #define SBBI0_RST1_OE_REG      PIO_OER
00731 #define SBBI0_RST1_COD_REG     PIO_CODR
00732 #define SBBI0_RST1_SOD_REG     PIO_SODR
00733 #elif SBBI0_RST1_PIO_ID == PIO_ID
00734 #define SBBI0_RST1_PE_REG      PIO_PER
00735 #define SBBI0_RST1_OE_REG      PIO_OER
00736 #define SBBI0_RST1_COD_REG     PIO_CODR
00737 #define SBBI0_RST1_SOD_REG     PIO_SODR
00738 #elif SBBI0_RST1_PIO_ID == PIOA_ID
00739 #define SBBI0_RST1_PE_REG      PIOA_PER
00740 #define SBBI0_RST1_OE_REG      PIOA_OER
00741 #define SBBI0_RST1_COD_REG     PIOA_CODR
00742 #define SBBI0_RST1_SOD_REG     PIOA_SODR
00743 #elif SBBI0_RST1_PIO_ID == PIOB_ID
00744 #define SBBI0_RST1_PE_REG      PIOB_PER
00745 #define SBBI0_RST1_OE_REG      PIOB_OER
00746 #define SBBI0_RST1_COD_REG     PIOB_CODR
00747 #define SBBI0_RST1_SOD_REG     PIOB_SODR
00748 #elif SBBI0_RST1_PIO_ID == PIOC_ID
00749 #define SBBI0_RST1_PE_REG      PIOC_PER
00750 #define SBBI0_RST1_OE_REG      PIOC_OER
00751 #define SBBI0_RST1_COD_REG     PIOC_CODR
00752 #define SBBI0_RST1_SOD_REG     PIOC_SODR
00753 #endif
00754 
00756 #define SBBI0_RST1_ENA() \
00757     outr(SBBI0_RST1_PE_REG, _BV(SBBI0_RST1_BIT)); \
00758     outr(SBBI0_RST1_OE_REG, _BV(SBBI0_RST1_BIT))
00759 
00760 #define SBBI0_RST1_CLR()   outr(SBBI0_RST1_COD_REG, _BV(SBBI0_RST1_BIT))
00761 
00762 #define SBBI0_RST1_SET()   outr(SBBI0_RST1_SOD_REG, _BV(SBBI0_RST1_BIT))
00763 
00764 #else /* SBBI0_RST1_BIT */
00765 
00766 #define SBBI0_RST1_ENA()
00767 #define SBBI0_RST1_CLR()
00768 #define SBBI0_RST1_SET()
00769 
00770 #endif /* SBBI0_RST1_BIT */
00771 
00772 #ifdef SBBI0_RST2_BIT
00773 
00774 #if !defined(SBBI0_RST2_PIO_ID)
00775 #define SBBI0_RST2_PE_REG      PIO_PER
00776 #define SBBI0_RST2_OE_REG      PIO_OER
00777 #define SBBI0_RST2_COD_REG     PIO_CODR
00778 #define SBBI0_RST2_SOD_REG     PIO_SODR
00779 #elif SBBI0_RST2_PIO_ID == PIO_ID
00780 #define SBBI0_RST2_PE_REG      PIO_PER
00781 #define SBBI0_RST2_OE_REG      PIO_OER
00782 #define SBBI0_RST2_COD_REG     PIO_CODR
00783 #define SBBI0_RST2_SOD_REG     PIO_SODR
00784 #elif SBBI0_RST2_PIO_ID == PIOA_ID
00785 #define SBBI0_RST2_PE_REG      PIOA_PER
00786 #define SBBI0_RST2_OE_REG      PIOA_OER
00787 #define SBBI0_RST2_COD_REG     PIOA_CODR
00788 #define SBBI0_RST2_SOD_REG     PIOA_SODR
00789 #elif SBBI0_RST2_PIO_ID == PIOB_ID
00790 #define SBBI0_RST2_PE_REG      PIOB_PER
00791 #define SBBI0_RST2_OE_REG      PIOB_OER
00792 #define SBBI0_RST2_COD_REG     PIOB_CODR
00793 #define SBBI0_RST2_SOD_REG     PIOB_SODR
00794 #elif SBBI0_RST2_PIO_ID == PIOC_ID
00795 #define SBBI0_RST2_PE_REG      PIOC_PER
00796 #define SBBI0_RST2_OE_REG      PIOC_OER
00797 #define SBBI0_RST2_COD_REG     PIOC_CODR
00798 #define SBBI0_RST2_SOD_REG     PIOC_SODR
00799 #endif
00800 
00802 #define SBBI0_RST2_ENA() \
00803     outr(SBBI0_RST2_PE_REG, _BV(SBBI0_RST2_BIT)); \
00804     outr(SBBI0_RST2_OE_REG, _BV(SBBI0_RST2_BIT))
00805 
00806 #define SBBI0_RST2_CLR()   outr(SBBI0_RST2_COD_REG, _BV(SBBI0_RST2_BIT))
00807 
00808 #define SBBI0_RST2_SET()   outr(SBBI0_RST2_SOD_REG, _BV(SBBI0_RST2_BIT))
00809 
00810 #else /* SBBI0_RST2_BIT */
00811 
00812 #define SBBI0_RST2_ENA()
00813 #define SBBI0_RST2_CLR()
00814 #define SBBI0_RST2_SET()
00815 
00816 #endif /* SBBI0_RST2_BIT */
00817 
00818 #ifdef SBBI0_RST3_BIT
00819 
00820 #if !defined(SBBI0_RST3_PIO_ID)
00821 #define SBBI0_RST3_PE_REG      PIO_PER
00822 #define SBBI0_RST3_OE_REG      PIO_OER
00823 #define SBBI0_RST3_COD_REG     PIO_CODR
00824 #define SBBI0_RST3_SOD_REG     PIO_SODR
00825 #elif SBBI0_RST3_PIO_ID == PIO_ID
00826 #define SBBI0_RST3_PE_REG      PIO_PER
00827 #define SBBI0_RST3_OE_REG      PIO_OER
00828 #define SBBI0_RST3_COD_REG     PIO_CODR
00829 #define SBBI0_RST3_SOD_REG     PIO_SODR
00830 #elif SBBI0_RST3_PIO_ID == PIOA_ID
00831 #define SBBI0_RST3_PE_REG      PIOA_PER
00832 #define SBBI0_RST3_OE_REG      PIOA_OER
00833 #define SBBI0_RST3_COD_REG     PIOA_CODR
00834 #define SBBI0_RST3_SOD_REG     PIOA_SODR
00835 #elif SBBI0_RST3_PIO_ID == PIOB_ID
00836 #define SBBI0_RST3_PE_REG      PIOB_PER
00837 #define SBBI0_RST3_OE_REG      PIOB_OER
00838 #define SBBI0_RST3_COD_REG     PIOB_CODR
00839 #define SBBI0_RST3_SOD_REG     PIOB_SODR
00840 #elif SBBI0_RST3_PIO_ID == PIOC_ID
00841 #define SBBI0_RST3_PE_REG      PIOC_PER
00842 #define SBBI0_RST3_OE_REG      PIOC_OER
00843 #define SBBI0_RST3_COD_REG     PIOC_CODR
00844 #define SBBI0_RST3_SOD_REG     PIOC_SODR
00845 #endif
00846 
00848 #define SBBI0_RST3_ENA() \
00849     outr(SBBI0_RST3_PE_REG, _BV(SBBI0_RST3_BIT)); \
00850     outr(SBBI0_RST3_OE_REG, _BV(SBBI0_RST3_BIT))
00851 
00852 #define SBBI0_RST3_CLR()   outr(SBBI0_RST3_COD_REG, _BV(SBBI0_RST3_BIT))
00853 
00854 #define SBBI0_RST3_SET()   outr(SBBI0_RST3_SOD_REG, _BV(SBBI0_RST3_BIT))
00855 
00856 #else /* SBBI0_RST3_BIT */
00857 
00858 #define SBBI0_RST3_ENA()
00859 #define SBBI0_RST3_CLR()
00860 #define SBBI0_RST3_SET()
00861 
00862 #endif /* SBBI0_RST3_BIT */
00863 
00864 #ifdef SBBI0_SCK_BIT
00865 
00866 #if !defined(SBBI0_SCK_PIO_ID)
00867 #define SBBI0_SCK_PE_REG        PIO_PER
00868 #define SBBI0_SCK_OE_REG        PIO_OER
00869 #define SBBI0_SCK_COD_REG       PIO_CODR
00870 #define SBBI0_SCK_SOD_REG       PIO_SODR
00871 #elif SBBI0_SCK_PIO_ID == PIO_ID
00872 #define SBBI0_SCK_PE_REG        PIO_PER
00873 #define SBBI0_SCK_OE_REG        PIO_OER
00874 #define SBBI0_SCK_COD_REG       PIO_CODR
00875 #define SBBI0_SCK_SOD_REG       PIO_SODR
00876 #elif SBBI0_SCK_PIO_ID == PIOA_ID
00877 #define SBBI0_SCK_PE_REG        PIOA_PER
00878 #define SBBI0_SCK_OE_REG        PIOA_OER
00879 #define SBBI0_SCK_COD_REG       PIOA_CODR
00880 #define SBBI0_SCK_SOD_REG       PIOA_SODR
00881 #elif SBBI0_SCK_PIO_ID == PIOB_ID
00882 #define SBBI0_SCK_PE_REG        PIOB_PER
00883 #define SBBI0_SCK_OE_REG        PIOB_OER
00884 #define SBBI0_SCK_COD_REG       PIOB_CODR
00885 #define SBBI0_SCK_SOD_REG       PIOB_SODR
00886 #elif SBBI0_SCK_PIO_ID == PIOC_ID
00887 #define SBBI0_SCK_PE_REG        PIOC_PER
00888 #define SBBI0_SCK_OE_REG        PIOC_OER
00889 #define SBBI0_SCK_COD_REG       PIOC_CODR
00890 #define SBBI0_SCK_SOD_REG       PIOC_SODR
00891 #endif
00892 
00894 #define SBBI0_SCK_ENA() \
00895     outr(SBBI0_SCK_PE_REG, _BV(SBBI0_SCK_BIT)); \
00896     outr(SBBI0_SCK_OE_REG, _BV(SBBI0_SCK_BIT))
00897 
00898 #define SBBI0_SCK_CLR()     outr(SBBI0_SCK_COD_REG, _BV(SBBI0_SCK_BIT))
00899 
00900 #define SBBI0_SCK_SET()     outr(SBBI0_SCK_SOD_REG, _BV(SBBI0_SCK_BIT))
00901 
00902 #ifdef SBBI0_MOSI_BIT
00903 
00904 #if !defined(SBBI0_MOSI_PIO_ID)
00905 #define SBBI0_MOSI_PE_REG       PIO_PER
00906 #define SBBI0_MOSI_OE_REG       PIO_OER
00907 #define SBBI0_MOSI_COD_REG      PIO_CODR
00908 #define SBBI0_MOSI_SOD_REG      PIO_SODR
00909 #elif SBBI0_MOSI_PIO_ID == PIO_ID
00910 #define SBBI0_MOSI_PE_REG       PIO_PER
00911 #define SBBI0_MOSI_OE_REG       PIO_OER
00912 #define SBBI0_MOSI_COD_REG      PIO_CODR
00913 #define SBBI0_MOSI_SOD_REG      PIO_SODR
00914 #elif SBBI0_MOSI_PIO_ID == PIOA_ID
00915 #define SBBI0_MOSI_PE_REG       PIOA_PER
00916 #define SBBI0_MOSI_OE_REG       PIOA_OER
00917 #define SBBI0_MOSI_COD_REG      PIOA_CODR
00918 #define SBBI0_MOSI_SOD_REG      PIOA_SODR
00919 #elif SBBI0_MOSI_PIO_ID == PIOB_ID
00920 #define SBBI0_MOSI_PE_REG       PIOB_PER
00921 #define SBBI0_MOSI_OE_REG       PIOB_OER
00922 #define SBBI0_MOSI_COD_REG      PIOB_CODR
00923 #define SBBI0_MOSI_SOD_REG      PIOB_SODR
00924 #elif SBBI0_MOSI_PIO_ID == PIOC_ID
00925 #define SBBI0_MOSI_PE_REG       PIOC_PER
00926 #define SBBI0_MOSI_OE_REG       PIOC_OER
00927 #define SBBI0_MOSI_COD_REG      PIOC_CODR
00928 #define SBBI0_MOSI_SOD_REG      PIOC_SODR
00929 #endif
00930 
00932 #define SBBI0_MOSI_ENA() \
00933     outr(SBBI0_MOSI_PE_REG, _BV(SBBI0_MOSI_BIT)); \
00934     outr(SBBI0_MOSI_OE_REG, _BV(SBBI0_MOSI_BIT))
00935 
00936 #define SBBI0_MOSI_CLR()    outr(SBBI0_MOSI_COD_REG, _BV(SBBI0_MOSI_BIT))
00937 
00938 #define SBBI0_MOSI_SET()    outr(SBBI0_MOSI_SOD_REG, _BV(SBBI0_MOSI_BIT))
00939 
00940 #else                           /* SBBI0_MOSI_BIT */
00941 
00942 #define SBBI0_MOSI_ENA()
00943 #define SBBI0_MOSI_CLR()
00944 #define SBBI0_MOSI_SET()
00945 
00946 #endif                          /* SBBI0_MOSI_BIT */
00947 
00948 #ifdef SBBI0_MISO_BIT
00949 
00950 #if !defined(SBBI0_MISO_PIO_ID)
00951 #define SBBI0_MISO_PE_REG       PIO_PER
00952 #define SBBI0_MISO_OD_REG       PIO_ODR
00953 #define SBBI0_MISO_PDS_REG      PIO_PDSR
00954 #elif SBBI0_MISO_PIO_ID == PIO_ID
00955 #define SBBI0_MISO_PE_REG       PIO_PER
00956 #define SBBI0_MISO_OD_REG       PIO_ODR
00957 #define SBBI0_MISO_PDS_REG      PIO_PDSR
00958 #elif SBBI0_MISO_PIO_ID == PIOA_ID
00959 #define SBBI0_MISO_PE_REG       PIOA_PER
00960 #define SBBI0_MISO_OD_REG       PIOA_ODR
00961 #define SBBI0_MISO_PDS_REG      PIOA_PDSR
00962 #elif SBBI0_MISO_PIO_ID == PIOB_ID
00963 #define SBBI0_MISO_PE_REG       PIOB_PER
00964 #define SBBI0_MISO_OD_REG       PIOB_ODR
00965 #define SBBI0_MISO_PDS_REG      PIOB_PDSR
00966 #elif SBBI0_MISO_PIO_ID == PIOC_ID
00967 #define SBBI0_MISO_PE_REG       PIOC_PER
00968 #define SBBI0_MISO_OD_REG       PIOC_ODR
00969 #define SBBI0_MISO_PDS_REG      PIOC_PDSR
00970 #endif
00971 
00973 #define SBBI0_MISO_ENA() \
00974     outr(SBBI0_MISO_PE_REG, _BV(SBBI0_MISO_BIT)); \
00975     outr(SBBI0_MISO_OD_REG, _BV(SBBI0_MISO_BIT))
00976 
00977 #define SBBI0_MISO_TST()    ((inr(SBBI0_MISO_PDS_REG) & _BV(SBBI0_MISO_BIT)) == _BV(SBBI0_MISO_BIT))
00978 
00979 #else                           /* SBBI0_MISO_BIT */
00980 
00981 #define SBBI0_MISO_ENA()
00982 #define SBBI0_MISO_TST()   0
00983 
00984 #endif                          /* SBBI0_MISO_BIT */
00985 
00986 #else                           /* SBBI0_SCK_BIT */
00987 
00988 #define SBBI0_SCK_ENA()
00989 #define SBBI0_SCK_CLR()
00990 #define SBBI0_SCK_SET()
00991 
00992 #define SBBI0_MOSI_ENA()
00993 #define SBBI0_MOSI_CLR()
00994 #define SBBI0_MOSI_SET()
00995 
00996 #define SBBI0_MISO_ENA()
00997 #define SBBI0_MISO_TST()   0
00998 
00999 #endif                          /* SBBI0_SCK_BIT */
01000 
01001 #endif                          /* MCU */
01002 
01003 #define SBBI0_INIT() \
01004 { \
01005     SBBI0_SCK_CLR(); \
01006     SBBI0_SCK_ENA(); \
01007     SBBI0_MOSI_CLR(); \
01008     SBBI0_MOSI_ENA(); \
01009     SBBI0_MISO_ENA(); \
01010 }
01011 
01012 __BEGIN_DECLS
01013 /* Function prototypes */
01014 
01015 extern int Sbbi0SetMode(ureg_t ix, ureg_t mode);
01016 extern void Sbbi0SetSpeed(ureg_t ix, uint32_t rate);
01017 extern void Sbbi0Enable(ureg_t ix);
01018 extern void Sbbi0ChipReset(ureg_t ix, ureg_t hi);
01019 extern void Sbbi0ChipSelect(ureg_t ix, ureg_t hi);
01020 extern void Sbbi0SelectDevice(ureg_t ix);
01021 extern void Sbbi0DeselectDevice(ureg_t ix);
01022 extern void Sbbi0NegSelectDevice(ureg_t ix);
01023 extern void Sbbi0NegDeselectDevice(ureg_t ix);
01024 extern uint8_t Sbbi0Byte(uint8_t data);
01025 extern void Sbbi0Transact(CONST void *wdata, void *rdata, size_t len);
01026 
01027 __END_DECLS
01028 /* End of prototypes */
01029 
01030 #endif

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