vs10xx.c

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00001 /*
00002  * Copyright (C) 2001-2007 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  * -
00032  *
00033  * This software has been inspired by all the valuable work done by
00034  * Jesper Hansen and Pavel Chromy. Many thanks for all their help.
00035  */
00036 
00037 /*
00038  * $Log: vs10xx.c,v $
00039  * Revision 1.5  2008/10/23 08:54:07  haraldkipp
00040  * Include the correct header file.
00041  *
00042  * Revision 1.4  2008/09/18 09:51:58  haraldkipp
00043  * Use the correct PORT macros.
00044  *
00045  * Revision 1.3  2008/09/02 14:30:28  haraldkipp
00046  * Make it compile for targets without specific configuration.
00047  *
00048  * Revision 1.2  2008/08/11 06:59:42  haraldkipp
00049  * BSD types replaced by stdint types (feature request #1282721).
00050  *
00051  * Revision 1.1  2007/04/12 08:59:55  haraldkipp
00052  * VS10XX decoder support added.
00053  *
00054  */
00055 
00056 #include <sys/atom.h>
00057 #include <sys/event.h>
00058 #include <sys/timer.h>
00059 #include <sys/heap.h>
00060 
00061 #include <cfg/arch/gpio.h>
00062 #include <cfg/audio.h>
00063 #include <dev/irqreg.h>
00064 #include <dev/vs10xx.h>
00065 
00066 #include <sys/bankmem.h>
00067 
00068 #include <stddef.h>
00069 
00074 
00075 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C)
00076 #define AUDIO_VS1001K
00077 #endif
00078 
00079 #ifndef VS10XX_FREQ
00080 
00081 #define VS10XX_FREQ             12288000UL
00082 #endif
00083 
00084 #ifndef VS10XX_HWRST_DURATION
00085 
00086 #define VS10XX_HWRST_DURATION   1
00087 #endif
00088 
00089 #ifndef VS10XX_HWRST_RECOVER
00090 
00091 #define VS10XX_HWRST_RECOVER    4
00092 #endif
00093 
00094 #ifndef VS10XX_SWRST_RECOVER
00095 
00096 #define VS10XX_SWRST_RECOVER    2
00097 #endif
00098 
00099 #ifndef VS10XX_SCI_MODE
00100 #define VS10XX_SCI_MODE         0
00101 #endif
00102 
00103 #ifndef VS10XX_SCI_RATE
00104 #define VS10XX_SCI_RATE         (VS10XX_FREQ / 4)
00105 #endif
00106 
00107 #ifndef VS10XX_SDI_MODE
00108 #define VS10XX_SDI_MODE         0
00109 #endif
00110 
00111 #ifndef VS10XX_SDI_RATE
00112 #define VS10XX_SDI_RATE         (VS10XX_FREQ / 4)
00113 #endif
00114 
00115 #if defined(VS10XX_SCI_SPI0_DEVICE) /* Command SPI device. */
00116 
00117 #include <dev/sppif0.h>
00118 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00119 #define SciReset(act)       Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00120 #else
00121 #define SciReset(act)       Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00122 #endif
00123 #define SciSetMode()        Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00124 #define SciSetSpeed()       Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00125 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00126 #define SciSelect()         Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00127 #define SciDeselect()       Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00128 #else
00129 #define SciSelect()         Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00130 #define SciDeselect()       Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00131 #endif
00132 #define SciByte(b)          Sppi0Byte(b)
00133 
00134 #elif defined(VS10XX_SCI_SBBI0_DEVICE) /* Command SPI device. */
00135 
00136 #include <dev/sbbif0.h>
00137 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00138 #define SciReset(act)       Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00139 #else
00140 #define SciReset(act)       Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00141 #endif
00142 #define SciSetMode()        Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00143 #define SciSetSpeed()       Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00144 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00145 #define SciSelect()         Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00146 #define SciDeselect()       Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00147 #else
00148 #define SciSelect()         Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00149 #define SciDeselect()       Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00150 #endif
00151 #define SciByte(b)          Sbbi0Byte(b)
00152 
00153 #elif defined(VS10XX_SCI_SBBI1_DEVICE) /* Command SPI device. */
00154 
00155 #include <dev/sbbif1.h>
00156 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00157 #define SciReset(act)       Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00158 #else
00159 #define SciReset(act)       Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00160 #endif
00161 #define SciSetMode()        Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00162 #define SciSetSpeed()       Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00163 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00164 #define SciSelect()         Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00165 #define SciDeselect()       Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00166 #else
00167 #define SciSelect()         Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00168 #define SciDeselect()       Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00169 #endif
00170 #define SciByte(b)          Sbbi1Byte(b)
00171 
00172 #elif defined(VS10XX_SCI_SBBI2_DEVICE) /* Command SPI device. */
00173 
00174 #include <dev/sbbif2.h>
00175 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00176 #define SciReset(act)       Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00177 #else
00178 #define SciReset(act)       Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00179 #endif
00180 #define SciSetMode()        Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00181 #define SciSetSpeed()       Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00182 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00183 #define SciSelect()         Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00184 #define SciDeselect()       Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00185 #else
00186 #define SciSelect()         Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00187 #define SciDeselect()       Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00188 #endif
00189 #define SciByte(b)          Sbbi2Byte(b)
00190 
00191 #elif defined(VS10XX_SCI_SBBI3_DEVICE) /* Command SPI device. */
00192 
00193 #include <dev/sbbif3.h>
00194 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00195 #define SciReset(act)       Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00196 #else
00197 #define SciReset(act)       Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00198 #endif
00199 #define SciSetMode()        Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00200 #define SciSetSpeed()       Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00201 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00202 #define SciSelect()         Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00203 #define SciDeselect()       Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00204 #else
00205 #define SciSelect()         Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00206 #define SciDeselect()       Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00207 #endif
00208 #define SciByte(b)          Sbbi3Byte(b)
00209 
00210 #else /* Command SPI device. */
00211 
00212 #define SciReset(act)
00213 #define SciSetMode()        (-1)
00214 #define SciSetSpeed()
00215 #define SciSelect()
00216 #define SciDeselect()
00217 #define SciByte(b)          0
00218 
00219 #endif /* Command SPI device. */
00220 
00221 
00222 #if defined(VS10XX_SDI_SPI0_DEVICE) /* Data SPI device. */
00223 
00224 #include <dev/sppif0.h>
00225 #define SdiSetMode()        Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00226 #define SdiSetSpeed()       Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00227 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00228 #define SdiSelect()         Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00229 #define SdiDeselect()       Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00230 #else
00231 #define SdiSelect()         Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00232 #define SdiDeselect()       Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00233 #endif
00234 #define SdiByte(b)          Sppi0Byte(b)
00235 
00236 #elif defined(VS10XX_SDI_SBBI0_DEVICE) /* Data SPI device. */
00237 
00238 #include <dev/sbbif0.h>
00239 #define SdiSetMode()        Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00240 #define SdiSetSpeed()       Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00241 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00242 #define SdiSelect()         Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00243 #define SdiDeselect()       Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00244 #else
00245 #define SdiSelect()         Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00246 #define SdiDeselect()       Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00247 #endif
00248 #define SdiByte(b)          Sbbi0Byte(b)
00249 
00250 #elif defined(VS10XX_SDI_SBBI1_DEVICE) /* Data SPI device. */
00251 
00252 #include <dev/sbbif1.h>
00253 #define SdiSetMode()        Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00254 #define SdiSetSpeed()       Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00255 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00256 #define SdiSelect()         Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00257 #define SdiDeselect()       Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00258 #else
00259 #define SdiSelect()         Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00260 #define SdiDeselect()       Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00261 #endif
00262 #define SdiByte(b)          Sbbi1Byte(b)
00263 
00264 #elif defined(VS10XX_SDI_SBBI2_DEVICE) /* Data SPI device. */
00265 
00266 #include <dev/sbbif2.h>
00267 #define SdiSetMode()        Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00268 #define SdiSetSpeed()       Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00269 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00270 #define SdiSelect()         Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00271 #define SdiDeselect()       Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00272 #else
00273 #define SdiSelect()         Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00274 #define SdiDeselect()       Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00275 #endif
00276 #define SdiByte(b)          Sbbi2Byte(b)
00277 
00278 #elif defined(VS10XX_SDI_SBBI3_DEVICE) /* Data SPI device. */
00279 
00280 #include <dev/sbbif3.h>
00281 #define SdiSetMode()        Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00282 #define SdiSetSpeed()       Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00283 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00284 #define SdiSelect()         Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00285 #define SdiDeselect()       Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00286 #else
00287 #define SdiSelect()         Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00288 #define SdiDeselect()       Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00289 #endif
00290 #define SdiByte(b)          Sbbi3Byte(b)
00291 
00292 #else /* Data SPI device. */
00293 
00294 #define SdiSetMode()        (-1)
00295 #define SdiSetSpeed()
00296 #define SdiSelect()
00297 #define SdiDeselect()
00298 #define SdiByte(b)          0
00299 
00300 #endif /* Data SPI device. */
00301 
00302 /* -------------------------------------------------
00303  * AT91 port specifications.
00304  */
00305 #if MCU_AT91
00306 
00307 #if (VS10XX_SIGNAL_IRQ == INT0)
00308 #define VS10XX_SIGNAL       sig_INTERRUPT0
00309 #elif (VS10XX_SIGNAL_IRQ == INT1)
00310 #define VS10XX_SIGNAL       sig_INTERRUPT1
00311 #elif (VS10XX_SIGNAL_IRQ == INT2)
00312 #define VS10XX_SIGNAL       sig_INTERRUPT2
00313 #endif
00314 
00315 #if defined(VS10XX_XCS_BIT)
00316 
00317 #if !defined(VS10XX_XCS_PORT)
00318 #define VS10XX_XCS_PE_REG        PIO_PER
00319 #define VS10XX_XCS_OE_REG        PIO_OER
00320 #define VS10XX_XCS_COD_REG       PIO_CODR
00321 #define VS10XX_XCS_SOD_REG       PIO_SODR
00322 #elif VS10XX_XCS_PORT == PIOA_ID
00323 #define VS10XX_XCS_PE_REG        PIOA_PER
00324 #define VS10XX_XCS_OE_REG        PIOA_OER
00325 #define VS10XX_XCS_COD_REG       PIOA_CODR
00326 #define VS10XX_XCS_SOD_REG       PIOA_SODR
00327 #elif VS10XX_XCS_PORT == PIOB_ID
00328 #define VS10XX_XCS_PE_REG        PIOB_PER
00329 #define VS10XX_XCS_OE_REG        PIOB_OER
00330 #define VS10XX_XCS_COD_REG       PIOB_CODR
00331 #define VS10XX_XCS_SOD_REG       PIOB_SODR
00332 #elif VS10XX_XCS_PORT == PIOC_ID
00333 #define VS10XX_XCS_PE_REG        PIOC_PER
00334 #define VS10XX_XCS_OE_REG        PIOC_OER
00335 #define VS10XX_XCS_COD_REG       PIOC_CODR
00336 #define VS10XX_XCS_SOD_REG       PIOC_SODR
00337 #endif
00338 #define VS10XX_XCS_ENA() \
00339     outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00340     outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00341 #define VS10XX_XCS_CLR()   outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00342 #define VS10XX_XCS_SET()   outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00343 
00344 #else /* VS10XX_XCS_BIT */
00345 
00346 #define VS10XX_XCS_ENA()
00347 #define VS10XX_XCS_CLR()
00348 #define VS10XX_XCS_SET()
00349 
00350 #endif /* VS10XX_XCS_BIT */
00351 
00352 #if defined(VS10XX_XDCS_BIT)
00353 
00354 #if !defined(VS10XX_XDCS_PORT)
00355 #define VS10XX_XDCS_PE_REG        PIO_PER
00356 #define VS10XX_XDCS_OE_REG        PIO_OER
00357 #define VS10XX_XDCS_COD_REG       PIO_CODR
00358 #define VS10XX_XDCS_SOD_REG       PIO_SODR
00359 #elif VS10XX_XDCS_PORT == PIOA_ID
00360 #define VS10XX_XDCS_PE_REG        PIOA_PER
00361 #define VS10XX_XDCS_OE_REG        PIOA_OER
00362 #define VS10XX_XDCS_COD_REG       PIOA_CODR
00363 #define VS10XX_XDCS_SOD_REG       PIOA_SODR
00364 #elif VS10XX_XDCS_PORT == PIOB_ID
00365 #define VS10XX_XDCS_PE_REG        PIOB_PER
00366 #define VS10XX_XDCS_OE_REG        PIOB_OER
00367 #define VS10XX_XDCS_COD_REG       PIOB_CODR
00368 #define VS10XX_XDCS_SOD_REG       PIOB_SODR
00369 #elif VS10XX_XDCS_PORT == PIOC_ID
00370 #define VS10XX_XDCS_PE_REG        PIOC_PER
00371 #define VS10XX_XDCS_OE_REG        PIOC_OER
00372 #define VS10XX_XDCS_COD_REG       PIOC_CODR
00373 #define VS10XX_XDCS_SOD_REG       PIOC_SODR
00374 #endif
00375 #define VS10XX_XDCS_ENA() \
00376     outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00377     outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00378 #define VS10XX_XDCS_CLR()   outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00379 #define VS10XX_XDCS_SET()   outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00380 
00381 #else /* VS10XX_XDCS_BIT */
00382 
00383 #define VS10XX_XDCS_ENA()
00384 #define VS10XX_XDCS_CLR()
00385 #define VS10XX_XDCS_SET()
00386 
00387 #endif /* VS10XX_XDCS_BIT */
00388 
00389 #if defined(VS10XX_DREQ_BIT)
00390 
00391 #if !defined(VS10XX_DREQ_PIO_ID)
00392 #define VS10XX_DREQ_PE_REG       PIO_PER
00393 #define VS10XX_DREQ_OD_REG       PIO_ODR
00394 #define VS10XX_DREQ_PDS_REG      PIO_PDSR
00395 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00396 #define VS10XX_DREQ_PE_REG       PIOA_PER
00397 #define VS10XX_DREQ_OD_REG       PIOA_ODR
00398 #define VS10XX_DREQ_PDS_REG      PIOA_PDSR
00399 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00400 #define VS10XX_DREQ_PE_REG       PIOB_PER
00401 #define VS10XX_DREQ_OD_REG       PIOB_ODR
00402 #define VS10XX_DREQ_PDS_REG      PIOB_PDSR
00403 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00404 #define VS10XX_DREQ_PE_REG       PIOC_PER
00405 #define VS10XX_DREQ_OD_REG       PIOC_ODR
00406 #define VS10XX_DREQ_PDS_REG      PIOC_PDSR
00407 #endif
00408 
00409 #define VS10XX_DREQ_PD_REG      PIO_PDR
00410 #define VS10XX_DREQ_OD_REG      PIO_ODR
00411 #define VS10XX_DREQ_PDS_REG     PIO_PDSR
00412 #define VS10XX_DREQ_ENA() \
00413     outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00414     outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00415 #define VS10XX_DREQ_TST()    ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00416 
00417 #else /* VS10XX_DREQ_BIT */
00418 
00419 #define VS10XX_DREQ_ENA()
00420 #define VS10XX_DREQ_TST()   0
00421 
00422 #endif /* VS10XX_DREQ_BIT */
00423 
00424 #ifdef VS10XX_BSYNC_BIT
00425 
00426 #if !defined(VS10XX_BSYNC_PIO_ID)
00427 #define VS10XX_BSYNC_PE_REG        PIO_PER
00428 #define VS10XX_BSYNC_OE_REG        PIO_OER
00429 #define VS10XX_BSYNC_COD_REG       PIO_CODR
00430 #define VS10XX_BSYNC_SOD_REG       PIO_SODR
00431 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00432 #define VS10XX_BSYNC_PE_REG        PIOA_PER
00433 #define VS10XX_BSYNC_OE_REG        PIOA_OER
00434 #define VS10XX_BSYNC_COD_REG       PIOA_CODR
00435 #define VS10XX_BSYNC_SOD_REG       PIOA_SODR
00436 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00437 #define VS10XX_BSYNC_PE_REG        PIOB_PER
00438 #define VS10XX_BSYNC_OE_REG        PIOB_OER
00439 #define VS10XX_BSYNC_COD_REG       PIOB_CODR
00440 #define VS10XX_BSYNC_SOD_REG       PIOB_SODR
00441 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00442 #define VS10XX_BSYNC_PE_REG        PIOC_PER
00443 #define VS10XX_BSYNC_OE_REG        PIOC_OER
00444 #define VS10XX_BSYNC_COD_REG       PIOC_CODR
00445 #define VS10XX_BSYNC_SOD_REG       PIOC_SODR
00446 #endif
00447 #define VS10XX_BSYNC_ENA() \
00448     outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00449     outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00450 #define VS10XX_BSYNC_CLR()   outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00451 #define VS10XX_BSYNC_SET()   outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00452 
00453 #else /* VS10XX_BSYNC_BIT */
00454 
00455 #define VS10XX_BSYNC_ENA()
00456 #define VS10XX_BSYNC_CLR()
00457 #define VS10XX_BSYNC_SET()
00458 
00459 #endif /* VS10XX_BSYNC_BIT */
00460 
00461 
00462 /* -------------------------------------------------
00463  * AVR port specifications.
00464  */
00465 #elif defined(__AVR__)
00466 
00467 #if !defined(VS10XX_SIGNAL_IRQ)
00468 #define VS10XX_SIGNAL_IRQ   INT6
00469 #endif
00470 
00471 #if (VS10XX_SIGNAL_IRQ == INT0)
00472 #define VS10XX_SIGNAL       sig_INTERRUPT0
00473 #define VS10XX_DREQ_BIT     0
00474 #define VS10XX_DREQ_PDS_REG PIND
00475 #define VS10XX_DREQ_PUE_REG PORTD
00476 #define VS10XX_DREQ_OE_REG  DDRD
00477 
00478 #elif (VS10XX_SIGNAL_IRQ == INT1)
00479 #define VS10XX_SIGNAL       sig_INTERRUPT1
00480 #define VS10XX_DREQ_BIT     1
00481 #define VS10XX_DREQ_PDS_REG PIND
00482 #define VS10XX_DREQ_PUE_REG PORTD
00483 #define VS10XX_DREQ_OE_REG  DDRD
00484 
00485 #elif (VS10XX_SIGNAL_IRQ == INT2)
00486 #define VS10XX_SIGNAL       sig_INTERRUPT2
00487 #define VS10XX_DREQ_BIT     2
00488 #define VS10XX_DREQ_PDS_REG PIND
00489 #define VS10XX_DREQ_PUE_REG PORTD
00490 #define VS10XX_DREQ_OE_REG  DDRD
00491 
00492 #elif (VS10XX_SIGNAL_IRQ == INT3)
00493 #define VS10XX_SIGNAL       sig_INTERRUPT3
00494 #define VS10XX_DREQ_BIT     3
00495 #define VS10XX_DREQ_PDS_REG PIND
00496 #define VS10XX_DREQ_PUE_REG PORTD
00497 #define VS10XX_DREQ_OE_REG  DDRD
00498 
00499 #elif (VS10XX_SIGNAL_IRQ == INT4)
00500 #define VS10XX_SIGNAL       sig_INTERRUPT4
00501 #define VS10XX_DREQ_BIT     4
00502 #define VS10XX_DREQ_PDS_REG PINE
00503 #define VS10XX_DREQ_PUE_REG PORTE
00504 #define VS10XX_DREQ_OE_REG  DDRE
00505 
00506 #elif (VS10XX_SIGNAL_IRQ == INT5)
00507 #define VS10XX_SIGNAL       sig_INTERRUPT5
00508 #define VS10XX_DREQ_BIT     5
00509 #define VS10XX_DREQ_PDS_REG PINE
00510 #define VS10XX_DREQ_PUE_REG PORTE
00511 #define VS10XX_DREQ_OE_REG  DDRE
00512 
00513 #elif (VS10XX_SIGNAL_IRQ == INT7)
00514 #define VS10XX_SIGNAL       sig_INTERRUPT7
00515 #define VS10XX_DREQ_BIT     7
00516 #define VS10XX_DREQ_PDS_REG PINE
00517 #define VS10XX_DREQ_PUE_REG PORTE
00518 #define VS10XX_DREQ_OE_REG  DDRE
00519 
00520 #else
00521 #define VS10XX_SIGNAL       sig_INTERRUPT6
00522 #define VS10XX_DREQ_BIT     6
00523 #define VS10XX_DREQ_PDS_REG PINE
00524 #define VS10XX_DREQ_PUE_REG PORTE
00525 #define VS10XX_DREQ_OE_REG  DDRE
00526 
00527 #endif
00528 
00529 #define VS10XX_DREQ_ENA() \
00530     cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00531     sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00532 #define VS10XX_DREQ_TST()    ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00533 
00534 
00535 #if defined(VS10XX_XCS_BIT)
00536 
00537 #if (VS10XX_XCS_PORT == AVRPORTA)
00538 #define VS10XX_XCS_SOD_REG  PORTA
00539 #define VS10XX_XCS_OE_REG   DDRA
00540 #elif (VS10XX_XCS_PORT == AVRPORTB)
00541 #define VS10XX_XCS_SOD_REG  PORTB
00542 #define VS10XX_XCS_OE_REG   DDRB
00543 #elif (VS10XX_XCS_PORT == AVRPORTD)
00544 #define VS10XX_XCS_SOD_REG  PORTD
00545 #define VS10XX_XCS_OE_REG   DDRD
00546 #elif (VS10XX_XCS_PORT == AVRPORTE)
00547 #define VS10XX_XCS_SOD_REG  PORTE
00548 #define VS10XX_XCS_OE_REG   DDRE
00549 #elif (VS10XX_XCS_PORT == AVRPORTF)
00550 #define VS10XX_XCS_SOD_REG  PORTF
00551 #define VS10XX_XCS_OE_REG   DDRF
00552 #elif (VS10XX_XCS_PORT == AVRPORTG)
00553 #define VS10XX_XCS_SOD_REG  PORTG
00554 #define VS10XX_XCS_OE_REG   DDRG
00555 #elif (VS10XX_XCS_PORT == AVRPORTH)
00556 #define VS10XX_XCS_SOD_REG  PORTH
00557 #define VS10XX_XCS_OE_REG   DDRH
00558 #endif
00559 #define VS10XX_XCS_ENA()      sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00560 #define VS10XX_XCS_CLR()      cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00561 #define VS10XX_XCS_SET()      sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00562 
00563 #else /* VS10XX_XCS_BIT */
00564 
00565 #define VS10XX_XCS_ENA()
00566 #define VS10XX_XCS_CLR()
00567 #define VS10XX_XCS_SET()
00568 
00569 #endif /* VS10XX_XCS_BIT */
00570 
00571 #if defined(VS10XX_XDCS_BIT)
00572 
00573 #if (VS10XX_XDCS_PORT == AVRPORTA)
00574 #define VS10XX_XDCS_SOD_REG  PORTA
00575 #define VS10XX_XDCS_OE_REG   DDRA
00576 #elif (VS10XX_XDCS_PORT == AVRPORTB)
00577 #define VS10XX_XDCS_SOD_REG  PORTB
00578 #define VS10XX_XDCS_OE_REG   DDRB
00579 #elif (VS10XX_XDCS_PORT == AVRPORTD)
00580 #define VS10XX_XDCS_SOD_REG  PORTD
00581 #define VS10XX_XDCS_OE_REG   DDRD
00582 #elif (VS10XX_XDCS_PORT == AVRPORTE)
00583 #define VS10XX_XDCS_SOD_REG  PORTE
00584 #define VS10XX_XDCS_OE_REG   DDRE
00585 #elif (VS10XX_XDCS_PORT == AVRPORTF)
00586 #define VS10XX_XDCS_SOD_REG  PORTF
00587 #define VS10XX_XDCS_OE_REG   DDRF
00588 #elif (VS10XX_XDCS_PORT == AVRPORTG)
00589 #define VS10XX_XDCS_SOD_REG  PORTG
00590 #define VS10XX_XDCS_OE_REG   DDRG
00591 #elif (VS10XX_XDCS_PORT == AVRPORTH)
00592 #define VS10XX_XDCS_SOD_REG  PORTH
00593 #define VS10XX_XDCS_OE_REG   DDRH
00594 #endif
00595 #define VS10XX_XDCS_ENA()      sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00596 #define VS10XX_XDCS_CLR()      cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00597 #define VS10XX_XDCS_SET()      sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00598 
00599 #else /* VS10XX_XDCS_BIT */
00600 
00601 #define VS10XX_XDCS_ENA()
00602 #define VS10XX_XDCS_CLR()
00603 #define VS10XX_XDCS_SET()
00604 
00605 #endif /* VS10XX_XDCS_BIT */
00606 
00607 
00608 #if defined(VS10XX_BSYNC_BIT)
00609 
00610 #if (VS10XX_BSYNC_AVRPORT == AVRPORTA)
00611 #define VS10XX_BSYNC_SOD_REG  PORTA
00612 #define VS10XX_BSYNC_OE_REG   DDRA
00613 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTB)
00614 #define VS10XX_BSYNC_SOD_REG  PORTB
00615 #define VS10XX_BSYNC_OE_REG   DDRB
00616 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTD)
00617 #define VS10XX_BSYNC_SOD_REG  PORTD
00618 #define VS10XX_BSYNC_OE_REG   DDRD
00619 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTE)
00620 #define VS10XX_BSYNC_SOD_REG  PORTE
00621 #define VS10XX_BSYNC_OE_REG   DDRE
00622 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTF)
00623 #define VS10XX_BSYNC_SOD_REG  PORTF
00624 #define VS10XX_BSYNC_OE_REG   DDRF
00625 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTG)
00626 #define VS10XX_BSYNC_SOD_REG  PORTG
00627 #define VS10XX_BSYNC_OE_REG   DDRG
00628 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTH)
00629 #define VS10XX_BSYNC_SOD_REG  PORTH
00630 #define VS10XX_BSYNC_OE_REG   DDRH
00631 #endif
00632 #define VS10XX_BSYNC_ENA()      sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00633 #define VS10XX_BSYNC_CLR()      cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00634 #define VS10XX_BSYNC_SET()      sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00635 
00636 #else /* VS10XX_BSYNC_BIT */
00637 
00638 #define VS10XX_BSYNC_ENA()
00639 #define VS10XX_BSYNC_CLR()
00640 #define VS10XX_BSYNC_SET()
00641 
00642 #endif /* VS10XX_BSYNC_BIT */
00643 
00644 
00645 /* -------------------------------------------------
00646  * End of port specifications.
00647  */
00648 #endif
00649 
00650 
00651 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00652 static volatile u_int vs_flush;
00653 
00654 /*
00655  * \brief Write a byte to the VS10XX data interface.
00656  *
00657  * The caller is responsible for checking the DREQ line. Also make sure,
00658  * that decoder interrupts are disabled.
00659  *
00660  * \param b Byte to be shifted to the decoder's data interface.
00661  */
00662 static INLINE void VsSdiPutByte(ureg_t b)
00663 {
00664 #if defined(VS10XX_BSYNC_BIT)
00665 
00666 #if defined(VS10XX_SDI_SBBI0_DEVICE) /* VS10XX_SDI_DEVICE */
00667     ureg_t mask;
00668 
00669     VS10XX_BSYNC_SET();
00670 
00671     for (mask = 0x80; mask; mask >>= 1) {
00672         SBBI0_SCK_CLR();
00673         if (b & mask) {
00674             SBBI0_MOSI_SET();
00675         }
00676         else {
00677             SBBI0_MOSI_CLR();
00678         }
00679         SBBI0_SCK_SET();
00680         if (mask & 0x40) {
00681             VS10XX_BSYNC_CLR();
00682         }
00683     }
00684     SBBI0_SCK_CLR();
00685 #elif defined(VS10XX_SDI_SBBI1_DEVICE) /* VS10XX_SDI_DEVICE */
00686     ureg_t mask;
00687 
00688     VS10XX_BSYNC_SET();
00689 
00690     for (mask = 0x80; mask; mask >>= 1) {
00691         SBBI1_SCK_CLR();
00692         if (b & mask) {
00693             SBBI1_MOSI_SET();
00694         }
00695         else {
00696             SBBI1_MOSI_CLR();
00697         }
00698         SBBI1_SCK_SET();
00699         if (mask & 0x40) {
00700             VS10XX_BSYNC_CLR();
00701         }
00702     }
00703     SBBI1_SCK_CLR();
00704 #elif defined(VS10XX_SDI_SBBI2_DEVICE) /* VS10XX_SDI_DEVICE */
00705     ureg_t mask;
00706 
00707     VS10XX_BSYNC_SET();
00708 
00709     for (mask = 0x80; mask; mask >>= 1) {
00710         SBBI2_SCK_CLR();
00711         if (b & mask) {
00712             SBBI2_MOSI_SET();
00713         }
00714         else {
00715             SBBI2_MOSI_CLR();
00716         }
00717         SBBI2_SCK_SET();
00718         if (mask & 0x40) {
00719             VS10XX_BSYNC_CLR();
00720         }
00721     }
00722     SBBI2_SCK_CLR();
00723 #elif defined(VS10XX_SDI_SBBI3_DEVICE) /* VS10XX_SDI_DEVICE */
00724     ureg_t mask;
00725 
00726     VS10XX_BSYNC_SET();
00727 
00728     for (mask = 0x80; mask; mask >>= 1) {
00729         SBBI3_SCK_CLR();
00730         if (b & mask) {
00731             SBBI3_MOSI_SET();
00732         }
00733         else {
00734             SBBI3_MOSI_CLR();
00735         }
00736         SBBI3_SCK_SET();
00737         if (mask & 0x40) {
00738             VS10XX_BSYNC_CLR();
00739         }
00740     }
00741     SBBI3_SCK_CLR();
00742 #elif defined(VS10XX_SDI_SPI0_DEVICE) /* VS10XX_SDI_DEVICE */
00743     VS10XX_BSYNC_SET();
00744 
00745     outb(SPDR, b);
00746 
00747     _NOP();
00748     _NOP();
00749     _NOP();
00750     _NOP();
00751     VS10XX_BSYNC_CLR();
00752 
00753     /* Wait for SPI transfer to finish. */
00754     loop_until_bit_is_set(SPSR, SPIF);
00755 #endif  /* VS10XX_SDI_DEVICE */
00756 
00757 #else  /* !VS10XX_BSYNC_BIT */
00758 
00759     (void)SdiByte(b);
00760 
00761 #endif /* !VS10XX_BSYNC_BIT */
00762 
00763 }
00764 
00776 ureg_t VsPlayerInterrupts(ureg_t enable)
00777 {
00778     static ureg_t is_enabled = 0;
00779     ureg_t rc;
00780 
00781     rc = is_enabled;
00782     if(enable) {
00783         VS10XX_DREQ_ENA();
00784         NutIrqEnable(&VS10XX_SIGNAL);
00785     }
00786     else {
00787         NutIrqDisable(&VS10XX_SIGNAL);
00788     }
00789     is_enabled = enable;
00790 
00791     return rc;
00792 }
00793 
00818 ureg_t VsPlayerThrottle(ureg_t on)
00819 {
00820     static ureg_t is_throttled = 0;
00821     ureg_t rc;
00822 
00823     rc = is_throttled;
00824     if(on) {
00825         VS10XX_XDCS_SET();
00826         SdiDeselect();
00827     }
00828     else {
00829         VS10XX_XDCS_CLR();
00830         SdiSelect();
00831     }
00832     is_throttled = on;
00833 
00834     return rc;
00835 }
00836 
00840 static void VsSciSelect(ureg_t on)
00841 {
00842     if (on) {
00843         /* Disable data interface. */
00844         SdiDeselect();
00845 
00846 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00847         /* Hint given by Jesper Hansen: If data channel uses HW SPI and 
00848            command channel uses SW SPI, then disable HW SPI while sending 
00849            using the command channel. */
00850         cbi(SPCR, SPE);
00851 #endif
00852 
00853         /* Deselect data channel. */
00854         VS10XX_XDCS_SET();
00855         /* Select cmd channel. */
00856         VS10XX_XCS_CLR();
00857         /* Enable cmd interface. */
00858         SciSelect();
00859     }
00860     else {
00861         /* Disable cmd interface. */
00862         SciDeselect();
00863         /* Deselect cmd channel. */
00864         VS10XX_XCS_SET();
00865         /* Re-select data channel. */
00866         VS10XX_XDCS_CLR();
00867         /* Enable data interface. */
00868         SdiSelect();
00869     }
00870 }
00871 
00878 static int VsWaitReady(void)
00879 {
00880     int tmo;
00881 
00882     for (tmo = 0; tmo < 5000; tmo++) {
00883         if (VS10XX_DREQ_TST()) {
00884             return 0;
00885         }
00886     }
00887     return -1;
00888 }
00889 
00890 /*
00891  * \brief Write a specified number of bytes to the VS10XX data interface.
00892  *
00893  * This function will check the DREQ line. Decoder interrupts must have 
00894  * been disabled before calling this function.
00895  */
00896 static int VsSdiWrite(CONST uint8_t * data, size_t len)
00897 {
00898     while (len--) {
00899         if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00900             return -1;
00901         }
00902         VsSdiPutByte(*data);
00903         data++;
00904     }
00905     return 0;
00906 }
00907 
00908 /*
00909  * \brief Write a specified number of bytes from program space to the 
00910  *        VS10XX data interface.
00911  *
00912  * This function is similar to VsSdiWrite() except that the data is 
00913  * located in program space.
00914  */
00915 static int VsSdiWrite_P(PGM_P data, size_t len)
00916 {
00917     while (len--) {
00918         if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00919             return -1;
00920         }
00921         VsSdiPutByte(PRG_RDB(data));
00922         data++;
00923     }
00924     return 0;
00925 }
00926 
00927 /*
00928  * \brief Write to a decoder register.
00929  *
00930  * Decoder interrupts must have been disabled before calling this function.
00931  */
00932 static void VsRegWrite(ureg_t reg, uint16_t data)
00933 {
00934     /* Select command channel. */
00935     VsWaitReady();
00936     VsSciSelect(1);
00937     /*
00938      * The VS1011E datasheet demands a minimum of 5 ns between
00939      * the falling CS and the first rising SCK. This is a very
00940      * short time and doesn't require any additional delay
00941      * even on very fast CPUs.
00942      */
00943     (void)SciByte(VS_OPCODE_WRITE);
00944     (void)SciByte((uint8_t) reg);
00945     (void)SciByte((uint8_t) (data >> 8));
00946     (void)SciByte((uint8_t) data);
00947 
00948     /* Re-select data channel. */
00949     VsSciSelect(0);
00950 }
00951 
00952 /*
00953  * \brief Read from a register.
00954  *
00955  * Decoder interrupts must have been disabled before calling this function.
00956  * 
00957  * \return Register contents.
00958  */
00959 static uint16_t VsRegRead(ureg_t reg)
00960 {
00961     uint16_t data;
00962 
00963     /* Select command channel. */
00964     VsWaitReady();
00965     VsSciSelect(1);
00966 
00967     (void)SciByte(VS_OPCODE_READ);
00968     (void)SciByte((uint8_t) reg);
00969     data = (uint16_t)SciByte(0) << 8;
00970     data |= SciByte(0);
00971 
00972     /* Select data channel. */
00973     VsSciSelect(0);
00974 
00975     return data;
00976 }
00977 
00978 /*
00979  * \brief Feed the decoder with data.
00980  *
00981  * This function serves two purposes: 
00982  * - It is called by VsPlayerKick() to initially fill the decoder buffer.
00983  * - It is used as an interrupt handler for the decoder.
00984  */
00985 static void VsPlayerFeed(void *arg)
00986 {
00987     ureg_t j = 32;
00988     size_t total = 0;
00989 
00990     if (!VS10XX_DREQ_TST()) {
00991         return;
00992     }
00993 
00994     /* 
00995      * Feed the decoder until its buffer is full or we ran out of data.
00996      */
00997     if (vs_status == VS_STATUS_RUNNING) {
00998         char *bp = 0;
00999         size_t consumed = 0;
01000         size_t available = 0;
01001         do {
01002             if(consumed >= available) {
01003                 /* Commit previously consumed bytes. */
01004                 if(consumed) {
01005                     NutSegBufReadCommit(consumed);
01006                     consumed = 0;
01007                 }
01008                 /* All bytes consumed, request new. */
01009                 bp = NutSegBufReadRequest(&available);
01010                 if(available == 0) {
01011                     /* End of stream. */
01012                     vs_status = VS_STATUS_EOF;
01013                     break;
01014                 }
01015             }
01016             /* We have some data in the buffer, feed it. */
01017             VsSdiPutByte(*bp);
01018             bp++;
01019             consumed++;
01020             total++;
01021             if (total > 4096) {
01022                 vs_status = VS_STATUS_EOF;
01023                 break;
01024             }
01025 
01026             /* Allow 32 bytes to be sent as long as DREQ is set, This includes
01027                the one in progress. */
01028             if (VS10XX_DREQ_TST()) {
01029                 j = 32;
01030             }
01031         } while(j--);
01032 
01033         /* Finally re-enable the producer buffer. */
01034         NutSegBufReadLast(consumed);
01035     }
01036 
01037     /* 
01038      * Flush the internal VS buffer. 
01039      */
01040     if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01041         do {
01042             VsSdiPutByte(0);
01043             if (--vs_flush == 0) {
01044                 /* Decoder internal buffer is flushed. */
01045                 vs_status = VS_STATUS_EMPTY;
01046                 break;
01047             }
01048             /* Allow 32 bytes to be sent as long as DREQ is set, This includes
01049                the one in progress. */
01050             if (VS10XX_DREQ_TST()) {
01051                 j = 32;
01052             }
01053         } while(j--);
01054     }
01055 }
01056 
01068 int VsPlayerKick(void)
01069 {
01070     /*
01071      * Start feeding the decoder with data.
01072      */
01073     VsPlayerInterrupts(0);
01074     vs_status = VS_STATUS_RUNNING;
01075     VsPlayerFeed(NULL);
01076     VsPlayerInterrupts(1);
01077 
01078     return 0;
01079 }
01080 
01089 int VsPlayerStop(void)
01090 {
01091     ureg_t ief;
01092 
01093     ief = VsPlayerInterrupts(0);
01094     /* Check whether we need to stop at all to not overwrite other than running status */
01095     if (vs_status == VS_STATUS_RUNNING) {
01096         vs_status = VS_STATUS_STOPPED;
01097     }
01098     VsPlayerInterrupts(ief);
01099 
01100     return 0;
01101 }
01102 
01103 
01116 int VsPlayerFlush(void)
01117 {
01118     VsPlayerInterrupts(0);
01119     /* Set up fluhing unless both buffers are empty. */
01120     if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01121         if (vs_flush == 0) {
01122             vs_flush = VS_FLUSH_BYTES;
01123         }
01124         /* start the playback if necessary */
01125         if (vs_status != VS_STATUS_RUNNING) {
01126             VsPlayerKick();
01127         }
01128     }
01129     VsPlayerInterrupts(1);
01130 
01131     return 0;
01132 }
01133 
01139 int VsPlayerInit(void)
01140 {
01141     /* Disable decoder interrupts. */
01142     VsPlayerInterrupts(0);
01143 
01144     /* Keep decoder in reset state. */
01145     SciReset(1);
01146 
01147     /* Initialize command channel. */
01148     if (SciSetMode()) {
01149         return -1;
01150     }
01151     SciSetSpeed();
01152     SciDeselect();
01153 
01154     /* Initialize data channel. */
01155     if (SdiSetMode()) {
01156         return -1;
01157     }
01158     SdiSetSpeed();
01159     SdiDeselect();
01160 
01161     /* Set BSYNC output low. */
01162     VS10XX_BSYNC_CLR();
01163     VS10XX_BSYNC_ENA();
01164 
01165     /* Set low active data channel select output low. */
01166     VS10XX_XDCS_SET();
01167     VS10XX_XDCS_ENA();
01168 
01169     /* Set low active command channel select output high. */
01170     VS10XX_XCS_SET();
01171     VS10XX_XCS_ENA();
01172 
01173     /* Enable DREQ interrupt input. */
01174     VS10XX_DREQ_ENA();
01175 
01176     /* Register the interrupt routine */
01177     if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01178         return -1;
01179     }
01180 
01181     /* Rising edge will generate an interrupt. */
01182     NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01183 
01184     /* Release decoder reset line. */
01185     SciReset(0);
01186     NutDelay(VS10XX_HWRST_RECOVER);
01187 
01188     return VsPlayerReset(0);
01189 }
01190 
01217 int VsPlayerReset(uint16_t mode)
01218 {
01219     /* Disable decoder interrupts and feeding. */
01220     VsPlayerInterrupts(0);
01221     vs_status = VS_STATUS_STOPPED;
01222 
01223     /* Software reset, set modes of decoder. */
01224 #if defined(VS10XX_BSYNC_BIT)
01225     VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01226 #else
01227     VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01228 #endif
01229     /* The decoder needs 9600 XTAL cycles. This is at least twice. */
01230     NutDelay(VS10XX_SWRST_RECOVER);
01231 
01232     /*
01233      * Check for correct reset.
01234      */
01235     if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01236         /* If not succeeded, give it one more chance and try hw reset. */
01237         SciReset(1);
01238         /* No idea how long we must held reset low. */
01239         NutDelay(VS10XX_HWRST_DURATION);
01240         SciReset(0);
01241         /* No idea how long we need to wait here. */
01242         NutDelay(VS10XX_HWRST_RECOVER);
01243 
01244         /* Set the requested modes. */
01245 #if defined(VS10XX_BSYNC_BIT)
01246         VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01247 #else
01248         VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01249 #endif
01250         NutDelay(VS10XX_SWRST_RECOVER);
01251         if (!VS10XX_DREQ_TST()) {
01252             return -1;
01253         }
01254     }
01255 
01256 #if VS10XX_FREQ < 20000000UL
01257     VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01258 #else
01259     VsRegWrite(VS_CLOCKF_REG, (uint16_t)(VS10XX_FREQ / 2000UL));
01260 #endif
01261 #if defined(AUDIO_VS1001K)
01262     /* Force frequency change (see datasheet). */
01263     VsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01264 #endif
01265     NutDelay(1);
01266 
01267 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01268     /* Clear any spurious interrupts. */
01269     outb(EIFR, BV(VS10XX_DREQ_BIT));
01270 #endif
01271 
01272     return 0;
01273 }
01274 
01298 int VsPlayerSetMode(uint16_t mode)
01299 {
01300     ureg_t ief;
01301 
01302     ief = VsPlayerInterrupts(0);
01303 #if defined(VS10XX_BSYNC_BIT)
01304     VsRegWrite(VS_MODE_REG, mode);
01305 #else
01306     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01307 #endif
01308     VsPlayerInterrupts(ief);
01309 
01310     return 0;
01311 }
01312 
01318 uint16_t VsPlayTime(void)
01319 {
01320     uint16_t rc;
01321     ureg_t ief;
01322 
01323     ief = VsPlayerInterrupts(0);
01324     rc = VsRegRead(VS_DECODE_TIME_REG);
01325     VsPlayerInterrupts(ief);
01326 
01327     return rc;
01328 }
01329 
01339 u_int VsGetStatus(void)
01340 {
01341     return vs_status;
01342 }
01343 
01344 #ifdef __GNUC__
01345 
01353 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01354 {
01355     uint16_t *usp = (uint16_t *) vshi;
01356     ureg_t ief;
01357 
01358     ief = VsPlayerInterrupts(0);
01359     *usp = VsRegRead(VS_HDAT1_REG);
01360     *++usp = VsRegRead(VS_HDAT0_REG);
01361     VsPlayerInterrupts(ief);
01362 
01363     return 0;
01364 }
01365 #endif
01366 
01379 uint16_t VsMemoryTest(void)
01380 {
01381     uint16_t rc;
01382     ureg_t ief;
01383     static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01384 
01385     ief = VsPlayerInterrupts(0);
01386 #if defined(VS10XX_BSYNC_BIT)
01387     VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01388 #else
01389     VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01390 #endif
01391     VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01392     while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01393         NutDelay(1);
01394     }
01395 #if defined(VS10XX_BSYNC_BIT)
01396     VsRegWrite(VS_MODE_REG, 0);
01397 #else
01398     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01399 #endif
01400     VsPlayerInterrupts(ief);
01401 
01402     return rc;
01403 }
01404 
01414 int VsSetVolume(ureg_t left, ureg_t right)
01415 {
01416     ureg_t ief;
01417 
01418     ief = VsPlayerInterrupts(0);
01419     VsRegWrite(VS_VOL_REG, ((uint16_t)left << VS_VOL_LEFT_LSB) | ((uint16_t)right << VS_VOL_RIGHT_LSB));
01420     VsPlayerInterrupts(ief);
01421 
01422     return 0;
01423 }
01424 
01433 int VsBeep(uint8_t fsin, uint8_t ms)
01434 {
01435     ureg_t ief;
01436     static prog_char on[] = { 0x53, 0xEF, 0x6E };
01437     static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01438     static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01439 
01440     /* Disable decoder interrupts. */
01441     ief = VsPlayerInterrupts(0);
01442 
01443 #if defined(VS10XX_BSYNC_BIT)
01444     VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01445 #else
01446     VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01447 #endif
01448 
01449     fsin = 56 + (fsin & 7) * 9;
01450     VsSdiWrite_P(on, sizeof(on));
01451     VsSdiWrite(&fsin, 1);
01452     VsSdiWrite_P(end, sizeof(end));
01453     NutDelay(ms);
01454     VsSdiWrite_P(off, sizeof(off));
01455     VsSdiWrite_P(end, sizeof(end));
01456 
01457 #if defined(VS10XX_BSYNC_BIT)
01458     VsRegWrite(VS_MODE_REG, 0);
01459 #else
01460     VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01461 #endif
01462 
01463     /* Restore decoder interrupt enable. */
01464     VsPlayerInterrupts(ief);
01465 
01466     return 0;
01467 }
01468 
01469 

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