lanc111.c

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00001 /*
00002  * Copyright (C) 2003-2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: lanc111.c,v $
00036  * Revision 1.8  2008/08/28 11:12:15  haraldkipp
00037  * Added interface flags, which will be required to implement Ethernet ioctl
00038  * functions.
00039  *
00040  * Revision 1.7  2008/08/11 06:59:17  haraldkipp
00041  * BSD types replaced by stdint types (feature request #1282721).
00042  *
00043  * Revision 1.6  2007/05/02 11:22:51  haraldkipp
00044  * Added multicast table entry.
00045  *
00046  * Revision 1.5  2006/10/08 16:48:08  haraldkipp
00047  * Documentation fixed
00048  *
00049  * Revision 1.4  2006/06/28 14:30:19  haraldkipp
00050  * Post to the event queue on overflow interrupts.
00051  * Transmit event queue removed, because no one is listening.
00052  *
00053  * Revision 1.3  2005/10/24 18:02:34  haraldkipp
00054  * Fixes for ATmega103.
00055  *
00056  * Revision 1.2  2005/08/02 17:46:45  haraldkipp
00057  * Major API documentation update.
00058  *
00059  * Revision 1.1  2005/07/26 18:02:40  haraldkipp
00060  * Moved from dev.
00061  *
00062  * Revision 1.13  2005/04/30 16:42:41  chaac
00063  * Fixed bug in handling of NUTDEBUG. Added include for cfg/os.h. If NUTDEBUG
00064  * is defined in NutConf, it will make effect where it is used.
00065  *
00066  * Revision 1.12  2005/02/02 19:55:34  haraldkipp
00067  * If no Ethernet link was available on the LAN91C111, each outgoing packet
00068  * took 15 seconds and, even worse, the ouput routine doesn't return an error.
00069  * Now the first attempt to send a packet without Ethernet link will wait for
00070  * 5 seconds and subsequent attempts take 0.5 seconds only, always returning
00071  * an error.
00072  *
00073  * Revision 1.11  2005/01/24 21:11:49  freckle
00074  * renamed NutEventPostFromIRQ into NutEventPostFromIrq
00075  *
00076  * Revision 1.10  2005/01/22 19:24:11  haraldkipp
00077  * Changed AVR port configuration names from PORTx to AVRPORTx.
00078  *
00079  * Revision 1.9  2005/01/21 16:49:45  freckle
00080  * Seperated calls to NutEventPostAsync between Threads and IRQs
00081  *
00082  * Revision 1.8  2004/09/22 08:14:48  haraldkipp
00083  * Made configurable
00084  *
00085  * Revision 1.7  2004/03/08 11:14:17  haraldkipp
00086  * Added quick hack for fixed mode.
00087  *
00088  * Revision 1.6  2004/02/25 16:22:33  haraldkipp
00089  * Do not initialize MAC with all zeros
00090  *
00091  * Revision 1.5  2004/01/14 19:31:43  drsung
00092  * Speed improvement to NicWrite applied. Thanks to Kolja Waschk
00093  *
00094  * Revision 1.4  2003/11/06 09:26:50  haraldkipp
00095  * Removed silly line with hardcoded MAC, left over from testing
00096  *
00097  * Revision 1.3  2003/11/04 17:54:47  haraldkipp
00098  * PHY configuration timing changed again for reliable linking
00099  *
00100  * Revision 1.2  2003/11/03 17:12:53  haraldkipp
00101  * Allow linking with RTL8019 driver.
00102  * Links more reliable to 10 MBit networks now.
00103  * Reset MMU on allocation failures.
00104  * Some optimizations.
00105  *
00106  * Revision 1.1  2003/10/13 10:13:49  haraldkipp
00107  * First release
00108  *
00109  */
00110 
00111 #include <cfg/os.h>
00112 #include <cfg/arch/avr.h>
00113 
00114 #include <string.h>
00115 
00116 #include <sys/atom.h>
00117 #include <sys/heap.h>
00118 #include <sys/thread.h>
00119 #include <sys/event.h>
00120 #include <sys/timer.h>
00121 #include <sys/confnet.h>
00122 
00123 #include <netinet/if_ether.h>
00124 #include <net/ether.h>
00125 #include <net/if_var.h>
00126 
00127 #include <dev/irqreg.h>
00128 #include <dev/lanc111.h>
00129 
00130 #ifdef NUTDEBUG
00131 #include <stdio.h>
00132 #endif
00133 
00134 /*
00135  * Determine ports, which had not been explicitely configured.
00136  */
00137 #ifndef LANC111_BASE_ADDR
00138 #define LANC111_BASE_ADDR   0xC000
00139 #endif
00140 
00141 #ifndef LANC111_SIGNAL_IRQ
00142 #define LANC111_SIGNAL_IRQ  INT5
00143 #endif
00144 
00145 #ifdef LANC111_RESET_BIT
00146 
00147 #if (LANC111_RESET_AVRPORT == AVRPORTB)
00148 #define LANC111_RESET_PORT   PORTB
00149 #define LANC111_RESET_DDR    DDRB
00150 
00151 #elif (LANC111_RESET_AVRPORT == AVRPORTD)
00152 #define LANC111_RESET_PORT   PORTD
00153 #define LANC111_RESET_DDR    DDRD
00154 
00155 #elif (LANC111_RESET_AVRPORT == AVRPORTE)
00156 #define LANC111_RESET_PORT   PORTE
00157 #define LANC111_RESET_DDR    DDRE
00158 
00159 #elif (LANC111_RESET_AVRPORT == AVRPORTF)
00160 #define LANC111_RESET_PORT   PORTF
00161 #define LANC111_RESET_DDR    DDRF
00162 
00163 #endif /* LANC111_RESET_AVRPORT */
00164 
00165 #endif /* LANC111_RESET_BIT */
00166 
00167 /*
00168  * Determine interrupt settings.
00169  */
00170 #if (LANC111_SIGNAL_IRQ == INT0)
00171 #define LANC111_SIGNAL          sig_INTERRUPT0
00172 #define LANC111_SIGNAL_MODE()   sbi(EICRA, ISC00); sbi(EICRA, ISC01)
00173 
00174 #elif (LANC111_SIGNAL_IRQ == INT1)
00175 #define LANC111_SIGNAL          sig_INTERRUPT1
00176 #define LANC111_SIGNAL_MODE()   sbi(EICRA, ISC10); sbi(EICRA, ISC11)
00177 
00178 #elif (LANC111_SIGNAL_IRQ == INT2)
00179 #define LANC111_SIGNAL          sig_INTERRUPT2
00180 #define LANC111_SIGNAL_MODE()   sbi(EICRA, ISC20); sbi(EICRA, ISC21)
00181 
00182 #elif (LANC111_SIGNAL_IRQ == INT3)
00183 #define LANC111_SIGNAL          sig_INTERRUPT3
00184 #define LANC111_SIGNAL_MODE()   sbi(EICRA, ISC30); sbi(EICRA, ISC31)
00185 
00186 #elif (LANC111_SIGNAL_IRQ == INT4)
00187 #define LANC111_SIGNAL          sig_INTERRUPT4
00188 #define LANC111_SIGNAL_MODE()   sbi(EICR, ISC40); sbi(EICR, ISC41)
00189 
00190 #elif (LANC111_SIGNAL_IRQ == INT6)
00191 #define LANC111_SIGNAL          sig_INTERRUPT6
00192 #define LANC111_SIGNAL_MODE()   sbi(EICR, ISC60); sbi(EICR, ISC61)
00193 
00194 #elif (LANC111_SIGNAL_IRQ == INT7)
00195 #define LANC111_SIGNAL          sig_INTERRUPT7
00196 #define LANC111_SIGNAL_MODE()   sbi(EICR, ISC70); sbi(EICR, ISC71)
00197 
00198 #else
00199 #define LANC111_SIGNAL          sig_INTERRUPT5
00200 #define LANC111_SIGNAL_MODE()   sbi(EICR, ISC50); sbi(EICR, ISC51)
00201 
00202 #endif
00203 
00208 
00212 #define NIC_BSR         (LANC111_BASE_ADDR + 0x0E)
00213 
00217 #define NIC_TCR         (LANC111_BASE_ADDR + 0x00)
00218 
00219 #define TCR_SWFDUP      0x8000  
00220 #define TCR_EPH_LOOP    0x2000  
00221 #define TCR_STP_SQET    0x1000  
00222 #define TCR_FDUPLX      0x0800  
00223 #define TCR_MON_CSN     0x0400  
00224 #define TCR_NOCRC       0x0100  
00225 #define TCR_PAD_EN      0x0080  
00226 #define TCR_FORCOL      0x0004  
00227 #define TCR_LOOP        0x0002  
00228 #define TCR_TXENA       0x0001  
00234 #define NIC_EPHSR       (LANC111_BASE_ADDR + 0x02)
00235 
00239 #define NIC_RCR         (LANC111_BASE_ADDR + 0x04)
00240 
00241 #define RCR_SOFT_RST    0x8000  
00242 #define RCR_FILT_CAR    0x4000  
00243 #define RCR_ABORT_ENB   0x2000  
00244 #define RCR_STRIP_CRC   0x0200  
00245 #define RCR_RXEN        0x0100  
00246 #define RCR_ALMUL       0x0004  
00247 #define RCR_PRMS        0x0002  
00248 #define RCR_RX_ABORT    0x0001  
00253 #define NIC_ECR         (LANC111_BASE_ADDR + 0x06)
00254 
00258 #define NIC_MIR         (LANC111_BASE_ADDR + 0x08)
00259 
00263 #define NIC_RPCR        (LANC111_BASE_ADDR + 0x0A)
00264 
00265 #define RPCR_SPEED      0x2000  
00266 #define RPCR_DPLX       0x1000  
00267 #define RPCR_ANEG       0x0800  
00268 #define RPCR_LEDA_PAT   0x0000  
00269 #define RPCR_LEDB_PAT   0x0010  
00274 #define NIC_CR          (LANC111_BASE_ADDR + 0x00)
00275 
00276 #define CR_EPH_EN       0x8000  
00281 #define NIC_BAR         (LANC111_BASE_ADDR + 0x02)
00282 
00286 #define NIC_IAR         (LANC111_BASE_ADDR + 0x04)
00287 
00291 #define NIC_GPR         (LANC111_BASE_ADDR + 0x0A)
00292 
00296 #define NIC_CTR         (LANC111_BASE_ADDR + 0x0C)
00297 
00298 #define CTR_RCV_BAD     0x4000  
00299 #define CTR_AUTO_RELEASE 0x0800 
00304 #define NIC_MMUCR       (LANC111_BASE_ADDR + 0x00)
00305 
00306 #define MMUCR_BUSY      0x0001
00307 
00308 #define MMU_NOP         0
00309 #define MMU_ALO         (1<<5)
00310 #define MMU_RST         (2<<5)
00311 #define MMU_REM         (3<<5)
00312 #define MMU_TOP         (4<<5)
00313 #define MMU_PKT         (5<<5)
00314 #define MMU_ENQ         (6<<5)
00315 #define MMU_RTX         (7<<5)
00316 
00322 #define NIC_PNR         (LANC111_BASE_ADDR + 0x02)
00323 
00329 #define NIC_ARR         (LANC111_BASE_ADDR + 0x03)
00330 
00331 #define ARR_FAILED      0x80
00332 
00336 #define NIC_FIFO        (LANC111_BASE_ADDR + 0x04)
00337 
00341 #define NIC_PTR         (LANC111_BASE_ADDR + 0x06)
00342 
00343 #define PTR_RCV         0x8000  
00344 #define PTR_AUTO_INCR   0x4000  
00345 #define PTR_READ        0x2000  
00346 #define PTR_ETEN        0x1000  
00347 #define PTR_NOT_EMPTY   0x0800  
00352 #define NIC_DATA        (LANC111_BASE_ADDR + 0x08)
00353 
00357 #define NIC_IST         (LANC111_BASE_ADDR + 0x0C)
00358 
00362 #define NIC_ACK         (LANC111_BASE_ADDR + 0x0C)
00363 
00367 #define NIC_MSK         (LANC111_BASE_ADDR + 0x0D)
00368 
00369 #define INT_MD          0x80    
00370 #define INT_ERCV        0x40    
00371 #define INT_EPH         0x20    
00372 #define INT_RX_OVRN     0x10    
00373 #define INT_ALLOC       0x08    
00374 #define INT_TX_EMPTY    0x04    
00375 #define INT_TX          0x02    
00376 #define INT_RCV         0x01    
00381 #define NIC_MT          (LANC111_BASE_ADDR + 0x00)
00382 
00386 #define NIC_MGMT        (LANC111_BASE_ADDR + 0x08)
00387 
00388 #define MGMT_MDOE       0x08    
00389 #define MGMT_MCLK       0x04    
00390 #define MGMT_MDI        0x02    
00391 #define MGMT_MDO        0x01    
00396 #define NIC_REV         (LANC111_BASE_ADDR + 0x0A)
00397 
00401 #define NIC_ERCV        (LANC111_BASE_ADDR + 0x0C)
00402 
00406 #define NIC_PHYCR       0
00407 
00408 #define PHYCR_RST       0x8000  
00409 #define PHYCR_LPBK      0x4000  
00410 #define PHYCR_SPEED     0x2000  
00411 #define PHYCR_ANEG_EN   0x1000  
00412 #define PHYCR_PDN       0x0800  
00413 #define PHYCR_MII_DIS   0x0400  
00414 #define PHYCR_ANEG_RST  0x0200  
00415 #define PHYCR_DPLX      0x0100  
00416 #define PHYCR_COLST     0x0080  
00422 #define NIC_PHYSR       1
00423 
00424 #define PHYSR_CAP_T4    0x8000  
00425 #define PHYSR_CAP_TXF   0x4000  
00426 #define PHYSR_CAP_TXH   0x2000  
00427 #define PHYSR_CAP_TF    0x1000  
00428 #define PHYSR_CAP_TH    0x0800  
00429 #define PHYSR_CAP_SUPR  0x0040  
00430 #define PHYSR_ANEG_ACK  0x0020  
00431 #define PHYSR_REM_FLT   0x0010  
00432 #define PHYSR_CAP_ANEG  0x0008  
00433 #define PHYSR_LINK      0x0004  
00434 #define PHYSR_JAB       0x0002  
00435 #define PHYSR_EXREG     0x0001  
00441 #define NIC_PHYID1      2
00442 
00446 #define NIC_PHYID2      3
00447 
00451 #define NIC_PHYANAD     4
00452 
00453 #define PHYANAD_NP      0x8000  
00454 #define PHYANAD_ACK     0x4000  
00455 #define PHYANAD_RF      0x2000  
00456 #define PHYANAD_T4      0x0200  
00457 #define PHYANAD_TX_FDX  0x0100  
00458 #define PHYANAD_TX_HDX  0x0080  
00459 #define PHYANAD_10FDX   0x0040  
00460 #define PHYANAD_10_HDX  0x0020  
00461 #define PHYANAD_CSMA    0x0001  
00466 #define NIC_PHYANRC     5
00467 
00471 #define NIC_PHYCFR1     16
00472 
00476 #define NIC_PHYCFR2     17
00477 
00481 #define NIC_PHYSOR      18
00482 
00483 #define PHYSOR_INT      0x8000  
00484 #define PHYSOR_LNKFAIL  0x4000  
00485 #define PHYSOR_LOSSSYNC 0x2000  
00486 #define PHYSOR_CWRD     0x1000  
00487 #define PHYSOR_SSD      0x0800  
00488 #define PHYSOR_ESD      0x0400  
00489 #define PHYSOR_RPOL     0x0200  
00490 #define PHYSOR_JAB      0x0100  
00491 #define PHYSOR_SPDDET   0x0080  
00492 #define PHYSOR_DPLXDET  0x0040  
00497 #define NIC_PHYMSK      19
00498 
00499 #define PHYMSK_MINT     0x8000  
00500 #define PHYMSK_MLNKFAIL 0x4000  
00501 #define PHYMSK_MLOSSSYN 0x2000  
00502 #define PHYMSK_MCWRD    0x1000  
00503 #define PHYMSK_MSSD     0x0800  
00504 #define PHYMSK_MESD     0x0400  
00505 #define PHYMSK_MRPOL    0x0200  
00506 #define PHYMSK_MJAB     0x0100  
00507 #define PHYMSK_MSPDDT   0x0080  
00508 #define PHYMSK_MDPLDT   0x0040  
00512 #define MSBV(bit)       (1 << ((bit) - 8))
00513 
00514 #define nic_outlb(addr, val) (*(volatile uint8_t *)(addr) = (val))
00515 #define nic_outhb(addr, val) (*(volatile uint8_t *)((addr) + 1) = (val))
00516 #define nic_outwx(addr, val) (*(volatile uint16_t *)(addr) = (val))
00517 #define nic_outw(addr, val) { \
00518     *(volatile uint8_t *)(addr) = (uint8_t)(val); \
00519     *((volatile uint8_t *)(addr) + 1) = (uint8_t)((val) >> 8); \
00520 }
00521 
00522 #define nic_inlb(addr) (*(volatile uint8_t *)(addr))
00523 #define nic_inhb(addr) (*(volatile uint8_t *)((addr) + 1))
00524 #define nic_inw(addr) (*(volatile uint16_t *)(addr))
00525 
00526 #define nic_bs(bank)    nic_outlb(NIC_BSR, bank)
00527 
00532 struct _NICINFO {
00533     HANDLE volatile ni_rx_rdy;  
00534     uint16_t ni_tx_cnt;          
00535     uint32_t ni_rx_packets;       
00536     uint32_t ni_tx_packets;       
00537     uint32_t ni_interrupts;       
00538     uint32_t ni_overruns;         
00539     uint32_t ni_rx_frame_errors;  
00540     uint32_t ni_rx_crc_errors;    
00541     uint32_t ni_rx_missed_errors; 
00542 };
00543 
00547 typedef struct _NICINFO NICINFO;
00548 
00555 
00556 
00557 static HANDLE mutex;
00558 static HANDLE maq;
00559 
00570 static uint8_t NicPhyRegSelect(uint8_t reg, uint8_t we)
00571 {
00572     uint8_t rs;
00573     uint8_t msk;
00574     uint8_t i;
00575 
00576     nic_bs(3);
00577     rs = (nic_inlb(NIC_MGMT) & ~(MGMT_MCLK | MGMT_MDO)) | MGMT_MDOE;
00578 
00579     /* Send idle pattern. */
00580     for (i = 0; i < 33; i++) {
00581         nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00582         nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00583     }
00584 
00585     /* Send start sequence. */
00586     nic_outlb(NIC_MGMT, rs);
00587     nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00588     nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00589     nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00590 
00591     /* Write or read mode. */
00592     if (we) {
00593         nic_outlb(NIC_MGMT, rs);
00594         nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00595         nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00596         nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00597     } else {
00598         nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00599         nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00600         nic_outlb(NIC_MGMT, rs);
00601         nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00602     }
00603 
00604     /* Send PHY address. Zero is used for the internal PHY. */
00605     for (i = 0; i < 5; i++) {
00606         nic_outlb(NIC_MGMT, rs);
00607         nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00608     }
00609 
00610     /* Send PHY register number. */
00611     for (msk = 0x10; msk; msk >>= 1) {
00612         if (reg & msk) {
00613             nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00614             nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00615         } else {
00616             nic_outlb(NIC_MGMT, rs);
00617             nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00618         }
00619     }
00620     nic_outlb(NIC_MGMT, rs);
00621 
00622     return rs;
00623 }
00624 
00634 static uint16_t NicPhyRead(uint8_t reg)
00635 {
00636     uint16_t rc = 0;
00637     uint8_t rs;
00638     uint8_t i;
00639 
00640     /* Select register for reading. */
00641     rs = NicPhyRegSelect(reg, 0);
00642 
00643     /* Switch data direction. */
00644     rs &= ~MGMT_MDOE;
00645     nic_outlb(NIC_MGMT, rs);
00646     nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00647 
00648     /* Clock data in. */
00649     for (i = 0; i < 16; i++) {
00650         nic_outlb(NIC_MGMT, rs);
00651         nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00652         rc <<= 1;
00653         rc |= (nic_inlb(NIC_MGMT) & MGMT_MDI) != 0;
00654     }
00655 
00656     /* This will set the clock line to low. */
00657     nic_outlb(NIC_MGMT, rs);
00658 
00659     return rc;
00660 }
00661 
00670 static void NicPhyWrite(uint8_t reg, uint16_t val)
00671 {
00672     uint16_t msk;
00673     uint8_t rs;
00674 
00675     /* Select register for writing. */
00676     rs = NicPhyRegSelect(reg, 1);
00677 
00678     /* Switch data direction dummy. */
00679     nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00680     nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00681     nic_outlb(NIC_MGMT, rs);
00682     nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00683 
00684     /* Clock data out. */
00685     for (msk = 0x8000; msk; msk >>= 1) {
00686         if (val & msk) {
00687             nic_outlb(NIC_MGMT, rs | MGMT_MDO);
00688             nic_outlb(NIC_MGMT, rs | MGMT_MDO | MGMT_MCLK);
00689         } else {
00690             nic_outlb(NIC_MGMT, rs);
00691             nic_outlb(NIC_MGMT, rs | MGMT_MCLK);
00692         }
00693     }
00694 
00695     /* Set clock line low and output line int z-state. */
00696     nic_outlb(NIC_MGMT, rs & ~MGMT_MDOE);
00697 }
00698 
00704 static int NicPhyConfig(void)
00705 {
00706     uint16_t phy_sor;
00707     uint16_t phy_sr;
00708     uint16_t phy_to;
00709     uint16_t mode;
00710 
00711     /* 
00712      * Reset the PHY and wait until this self clearing bit
00713      * becomes zero. We sleep 63 ms before each poll and
00714      * give up after 3 retries. 
00715      */
00716     //printf("Reset PHY..");
00717     NicPhyWrite(NIC_PHYCR, PHYCR_RST);
00718     for (phy_to = 0;; phy_to++) {
00719         NutSleep(63);
00720         if ((NicPhyRead(NIC_PHYCR) & PHYCR_RST) == 0)
00721             break;
00722         if (phy_to > 3)
00723             return -1;
00724     }
00725     //printf("OK\n");
00726 
00727     /* Store PHY status output. */
00728     phy_sor = NicPhyRead(NIC_PHYSOR);
00729 
00730     /* Enable PHY interrupts. */
00731     NicPhyWrite(NIC_PHYMSK, PHYMSK_MLOSSSYN | PHYMSK_MCWRD | PHYMSK_MSSD |
00732                 PHYMSK_MESD | PHYMSK_MRPOL | PHYMSK_MJAB | PHYMSK_MSPDDT | PHYMSK_MDPLDT);
00733 
00734     /* Set RPC register. */
00735     mode = RPCR_ANEG | RPCR_LEDA_PAT | RPCR_LEDB_PAT;
00736     nic_bs(0);
00737     nic_outw(NIC_RPCR, mode);
00738 
00739 #ifdef NIC_FIXED
00740     /* Disable link. */
00741     phy_sr = NicPhyRead(NIC_PHYCFR1);
00742     NicPhyWrite(NIC_PHYCFR1, phy_sr | 0x8000);
00743     NutSleep(63);
00744 
00745     /* Set fixed capabilities. */
00746     NicPhyWrite(NIC_PHYCR, NIC_FIXED);
00747     nic_bs(0);
00748     nic_outw(NIC_RPCR, mode);
00749 
00750     /* Enable link. */
00751     phy_sr = NicPhyRead(NIC_PHYCFR1);
00752     NicPhyWrite(NIC_PHYCFR1, phy_sr & ~0x8000);
00753     phy_sr = NicPhyRead(NIC_PHYCFR1);
00754 
00755 #else
00756     /*
00757      * Advertise our capabilities, initiate auto negotiation
00758      * and wait until this has been completed.
00759      */
00760     //printf("Negotiate..");
00761     NicPhyWrite(NIC_PHYANAD, PHYANAD_TX_FDX | PHYANAD_TX_HDX | PHYANAD_10FDX | PHYANAD_10_HDX | PHYANAD_CSMA);
00762     NutSleep(63);
00763     for (phy_to = 0, phy_sr = 0;; phy_to++) {
00764         /* Give up after 10 seconds. */
00765         if (phy_to >= 1024)
00766             return -1;
00767         /* Restart auto negotiation every 4 seconds or on failures. */
00768         if ((phy_to & 127) == 0 /* || (phy_sr & PHYSR_REM_FLT) != 0 */ ) {
00769             NicPhyWrite(NIC_PHYCR, PHYCR_ANEG_EN | PHYCR_ANEG_RST);
00770             //printf("Restart..");
00771             NutSleep(63);
00772         }
00773         /* Check if we are done. */
00774         phy_sr = NicPhyRead(NIC_PHYSR);
00775         //printf("[SR %04X]", phy_sr);
00776         if (phy_sr & PHYSR_ANEG_ACK)
00777             break;
00778         NutSleep(63);
00779     }
00780     //printf("OK\n");
00781 #endif
00782 
00783     return 0;
00784 }
00785 
00796 static INLINE int NicMmuWait(uint16_t tmo)
00797 {
00798     while (tmo--) {
00799         if ((nic_inlb(NIC_MMUCR) & MMUCR_BUSY) == 0)
00800             break;
00801         NutDelay(1);
00802     }
00803     return tmo ? 0 : -1;
00804 }
00805 
00811 static int NicReset(void)
00812 {
00813 #ifdef LANC111_RESET_BIT
00814     sbi(LANC111_RESET_DDR, LANC111_RESET_BIT);
00815     sbi(LANC111_RESET_PORT, LANC111_RESET_BIT);
00816     NutDelay(WAIT100);
00817     cbi(LANC111_RESET_PORT, LANC111_RESET_BIT);
00818     NutDelay(WAIT250);
00819     NutDelay(WAIT250);
00820 #endif
00821 
00822     /* Disable all interrupts. */
00823     nic_outlb(NIC_MSK, 0);
00824 
00825     /* MAC and PHY software reset. */
00826     nic_bs(0);
00827     nic_outw(NIC_RCR, RCR_SOFT_RST);
00828 
00829     /* Enable Ethernet protocol handler. */
00830     nic_bs(1);
00831     nic_outw(NIC_CR, CR_EPH_EN);
00832 
00833     NutDelay(10);
00834 
00835     /* Disable transmit and receive. */
00836     nic_bs(0);
00837     nic_outw(NIC_RCR, 0);
00838     nic_outw(NIC_TCR, 0);
00839 
00840     /* Enable auto release. */
00841     nic_bs(1);
00842     nic_outw(NIC_CTR, CTR_AUTO_RELEASE);
00843 
00844     /* Reset MMU. */
00845     nic_bs(2);
00846     nic_outlb(NIC_MMUCR, MMU_RST);
00847     if (NicMmuWait(1000))
00848         return -1;
00849 
00850     return 0;
00851 }
00852 
00853 /*
00854  * Fires up the network interface. NIC interrupts
00855  * should have been disabled when calling this
00856  * function.
00857  *
00858  * \param mac Six byte unique MAC address.
00859  */
00860 static int NicStart(CONST uint8_t * mac)
00861 {
00862     uint8_t i;
00863 
00864     if (NicReset())
00865         return -1;
00866 
00867     /* Enable receiver. */
00868     nic_bs(3);
00869     nic_outlb(NIC_ERCV, 7);
00870     nic_bs(0);
00871     nic_outw(NIC_RCR, RCR_RXEN);
00872 
00873     /* Enable transmitter and padding. */
00874     nic_outw(NIC_TCR, TCR_PAD_EN | TCR_TXENA);
00875 
00876     /* Configure the PHY. */
00877     if (NicPhyConfig())
00878         return -1;
00879 
00880     /* Set MAC address. */
00881     //printf("Set MAC %02X%02X%02X%02X%02X%02X", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
00882     nic_bs(1);
00883     for (i = 0; i < 6; i++)
00884         nic_outlb(NIC_IAR + i, mac[i]);
00885     //printf("OK\n");
00886 
00887     /* Enable interrupts. */
00888     nic_bs(2);
00889     nic_outlb(NIC_MSK, INT_ERCV | INT_RCV | INT_RX_OVRN);
00890 
00891     return 0;
00892 }
00893 
00894 /*
00895  * NIC interrupt entry.
00896  */
00897 static void NicInterrupt(void *arg)
00898 {
00899     uint8_t isr;
00900     uint8_t imr;
00901     NICINFO *ni = (NICINFO *) ((NUTDEVICE *) arg)->dev_dcb;
00902 
00903     ni->ni_interrupts++;
00904 
00905     /* Read the interrupt mask and disable all interrupts. */
00906     nic_bs(2);
00907     imr = nic_inlb(NIC_MSK);
00908     nic_outlb(NIC_MSK, 0);
00909 
00910     /* Read the interrupt status and acknowledge all interrupts. */
00911     isr = nic_inlb(NIC_IST);
00912     //printf("\n!%02X-%02X ", isr, imr);
00913     isr &= imr;
00914 
00915     /*
00916      * If this is a transmit interrupt, then a packet has been sent. 
00917      * So we can clear the transmitter busy flag and wake up the 
00918      * transmitter thread.
00919      */
00920     if (isr & INT_TX_EMPTY) {
00921         nic_outlb(NIC_ACK, INT_TX_EMPTY);
00922         imr &= ~INT_TX_EMPTY;
00923     }
00924     /* Transmit error. */
00925     else if (isr & INT_TX) {
00926         /* re-enable transmit */
00927         nic_bs(0);
00928         nic_outw(NIC_TCR, nic_inlb(NIC_TCR) | TCR_TXENA);
00929         nic_bs(2);
00930         nic_outlb(NIC_ACK, INT_TX);
00931         /* kill the packet */
00932         nic_outlb(NIC_MMUCR, MMU_PKT);
00933     }
00934 
00935 
00936     /*
00937      * If this is a receive interrupt, then wake up the receiver 
00938      * thread.
00939      */
00940     if (isr & INT_RX_OVRN) {
00941         nic_outlb(NIC_ACK, INT_RX_OVRN);
00942         //nic_outlb(NIC_MMUCR, MMU_TOP);
00943         NutEventPostFromIrq(&ni->ni_rx_rdy);
00944     }
00945     if (isr & INT_ERCV) {
00946         nic_outlb(NIC_ACK, INT_ERCV);
00947         NutEventPostFromIrq(&ni->ni_rx_rdy);
00948     }
00949     if (isr & INT_RCV) {
00950         nic_outlb(NIC_ACK, INT_RCV);
00951         imr &= ~INT_RCV;
00952         NutEventPostFromIrq(&ni->ni_rx_rdy);
00953     }
00954 
00955     if (isr & INT_ALLOC) {
00956         imr &= ~INT_ALLOC;
00957         NutEventPostFromIrq(&maq);
00958     }
00959     //printf(" -%02X-%02X- ", nic_inlb(NIC_IST), inb(PINE) & 0x20);
00960     nic_outlb(NIC_MSK, imr);
00961 }
00962 
00963 /*
00964  * Write data block to the NIC.
00965  */
00966 static void NicWrite(uint8_t * buf, uint16_t len)
00967 {
00968     register uint16_t l = len - 1;
00969     register uint8_t ih = (uint16_t) l >> 8;
00970     register uint8_t il = (uint8_t) l;
00971 
00972     if (!len)
00973         return;
00974 
00975     do {
00976         do {
00977             nic_outlb(NIC_DATA, *buf++);
00978         } while (il-- != 0);
00979     } while (ih-- != 0);
00980 }
00981 
00982 /*
00983  * Read data block from the NIC.
00984  */
00985 static void NicRead(uint8_t * buf, uint16_t len)
00986 {
00987     register uint16_t l = len - 1;
00988     register uint8_t ih = (uint16_t) l >> 8;
00989     register uint8_t il = (uint8_t) l;
00990 
00991     if (!len)
00992         return;
00993 
00994     do {
00995         do {
00996             *buf++ = nic_inlb(NIC_DATA);
00997         } while (il-- != 0);
00998     } while (ih-- != 0);
00999 }
01000 
01011 static NETBUF *NicGetPacket(void)
01012 {
01013     NETBUF *nb = 0;
01014     //uint8_t *buf;
01015     uint16_t fsw;
01016     uint16_t fbc;
01017 
01018     /* Check the fifo empty bit. If it is set, then there is 
01019        nothing in the receiver fifo. */
01020     nic_bs(2);
01021     if (nic_inw(NIC_FIFO) & 0x8000) {
01022         return 0;
01023     }
01024 
01025     /* Inialize pointer register. */
01026     nic_outw(NIC_PTR, PTR_READ | PTR_RCV | PTR_AUTO_INCR);
01027     _NOP();
01028     _NOP();
01029     _NOP();
01030     _NOP();
01031 
01032     /* Read status word and byte count. */
01033     fsw = nic_inw(NIC_DATA);
01034     fbc = nic_inw(NIC_DATA);
01035     //printf("[SW=%04X,BC=%04X]", fsw, fbc);
01036 
01037     /* Check for frame errors. */
01038     if (fsw & 0xAC00) {
01039         nb = (NETBUF *) 0xFFFF;
01040     }
01041     /* Check the byte count. */
01042     else if (fbc < 66 || fbc > 1524) {
01043         nb = (NETBUF *) 0xFFFF;
01044     }
01045 
01046     else {
01047         /* 
01048          * Allocate a NETBUF. 
01049          * Hack alert: Rev A chips never set the odd frame indicator.
01050          */
01051         fbc -= 3;
01052         nb = NutNetBufAlloc(0, NBAF_DATALINK, fbc);
01053 
01054         /* Perform the read. */
01055         if (nb)
01056             NicRead(nb->nb_dl.vp, fbc);
01057     }
01058 
01059     /* Release the packet. */
01060     nic_outlb(NIC_MMUCR, MMU_TOP);
01061 
01062     return nb;
01063 }
01064 
01079 static int NicPutPacket(NETBUF * nb)
01080 {
01081     uint16_t sz;
01082     uint8_t odd = 0;
01083     uint8_t imsk;
01084 
01085     //printf("[P]");
01086     /*
01087      * Calculate the number of bytes to be send. Do not send packets 
01088      * larger than the Ethernet maximum transfer unit. The MTU
01089      * consist of 1500 data bytes plus the 14 byte Ethernet header
01090      * plus 4 bytes CRC. We check the data bytes only.
01091      */
01092     if ((sz = nb->nb_nw.sz + nb->nb_tp.sz + nb->nb_ap.sz) > ETHERMTU)
01093         return -1;
01094 
01095     /* Disable all interrupts. */
01096     imsk = nic_inlb(NIC_MSK);
01097     nic_outlb(NIC_MSK, 0);
01098 
01099     /* Allocate packet buffer space. */
01100     nic_bs(2);
01101     nic_outlb(NIC_MMUCR, MMU_ALO);
01102     if (NicMmuWait(100))
01103         return -1;
01104 
01105     /* Enable interrupts including allocation success. */
01106     nic_outlb(NIC_MSK, imsk | INT_ALLOC);
01107 
01108     /* The MMU needs some time. Use it to calculate the byte count. */
01109     sz += nb->nb_dl.sz;
01110     sz += 6;
01111     if (sz & 1) {
01112         sz++;
01113         odd++;
01114     }
01115 
01116     /* Wait for allocation success. */
01117     while ((nic_inlb(NIC_IST) & INT_ALLOC) == 0) {
01118         if (NutEventWait(&maq, 125)) {
01119             nic_outlb(NIC_MMUCR, MMU_RST);
01120             NicMmuWait(1000);
01121             nic_outlb(NIC_MMUCR, MMU_ALO);
01122             if (NicMmuWait(100) || (nic_inlb(NIC_IST) & INT_ALLOC) == 0) {
01123                 if (NutEventWait(&maq, 125)) {
01124                     return -1;
01125                 }
01126             }
01127         }
01128     }
01129 
01130     /* Disable interrupts. */
01131     imsk = nic_inlb(NIC_MSK);
01132     nic_outlb(NIC_MSK, 0);
01133 
01134 
01135     nic_outlb(NIC_PNR, nic_inhb(NIC_PNR));
01136 
01137     nic_outw(NIC_PTR, 0x4000);
01138 
01139     /* Transfer control word. */
01140     nic_outlb(NIC_DATA, 0);
01141     nic_outlb(NIC_DATA, 0);
01142 
01143     /* Transfer the byte count. */
01144     nic_outw(NIC_DATA, sz);
01145 
01146     /* Transfer the Ethernet frame. */
01147     NicWrite(nb->nb_dl.vp, nb->nb_dl.sz);
01148     NicWrite(nb->nb_nw.vp, nb->nb_nw.sz);
01149     NicWrite(nb->nb_tp.vp, nb->nb_tp.sz);
01150     NicWrite(nb->nb_ap.vp, nb->nb_ap.sz);
01151 
01152     if (odd)
01153         nic_outlb(NIC_DATA, 0);
01154 
01155     /* Transfer the control word. */
01156     nic_outw(NIC_DATA, 0);
01157 
01158     /* Enqueue packet. */
01159     if (NicMmuWait(100))
01160         return -1;
01161     nic_outlb(NIC_MMUCR, MMU_ENQ);
01162 
01163     /* Enable interrupts. */
01164     imsk |= INT_TX | INT_TX_EMPTY;
01165     nic_outlb(NIC_MSK, imsk);
01166 
01167     return 0;
01168 }
01169 
01170 
01175 THREAD(NicRxLanc, arg)
01176 {
01177     NUTDEVICE *dev;
01178     IFNET *ifn;
01179     NICINFO *ni;
01180     NETBUF *nb;
01181     uint8_t imsk;
01182 
01183     dev = arg;
01184     ifn = (IFNET *) dev->dev_icb;
01185     ni = (NICINFO *) dev->dev_dcb;
01186 
01187     /*
01188      * This is a temporary hack. Due to a change in initialization,
01189      * we may not have got a MAC address yet. Wait until one has been
01190      * set.
01191      */
01192     for (;;) {
01193         if (*((uint32_t *) (ifn->if_mac)) && *((uint32_t *) (ifn->if_mac)) != 0xFFFFFFFFUL) {
01194             break;
01195         }
01196         NutSleep(63);
01197     }
01198 
01199     /*
01200      * Do not continue unless we managed to start the NIC. We are
01201      * trapped here if the Ethernet link cannot be established.
01202      * This happens, for example, if no Ethernet cable is plugged
01203      * in.
01204      */
01205     while(NicStart(ifn->if_mac)) {
01206         NutSleep(1000);
01207     }
01208 
01209     LANC111_SIGNAL_MODE();
01210     sbi(EIMSK, LANC111_SIGNAL_IRQ);
01211 
01212     NutEventPost(&mutex);
01213 
01214     /* Run at high priority. */
01215     NutThreadSetPriority(9);
01216 
01217     for (;;) {
01218 
01219         /*
01220          * Wait for the arrival of new packets or
01221          * check the receiver every two second.
01222          */
01223         NutEventWait(&ni->ni_rx_rdy, 2000);
01224 
01225         /*
01226          * Fetch all packets from the NIC's internal
01227          * buffer and pass them to the registered handler.
01228          */
01229         imsk = nic_inlb(NIC_MSK);
01230         nic_outlb(NIC_MSK, 0);
01231         while ((nb = NicGetPacket()) != 0) {
01232             if (nb != (NETBUF *) 0xFFFF) {
01233                 ni->ni_rx_packets++;
01234                 (*ifn->if_recv) (dev, nb);
01235             }
01236         }
01237         nic_outlb(NIC_MSK, imsk | INT_RCV | INT_ERCV);
01238     }
01239 }
01240 
01251 int LancOutput(NUTDEVICE * dev, NETBUF * nb)
01252 {
01253     static uint32_t mx_wait = 5000;
01254     int rc = -1;
01255     NICINFO *ni;
01256 
01257     /*
01258      * After initialization we are waiting for a long time to give
01259      * the PHY a chance to establish an Ethernet link.
01260      */
01261     if (NutEventWait(&mutex, mx_wait) == 0) {
01262         ni = (NICINFO *) dev->dev_dcb;
01263 
01264         if (NicPutPacket(nb) == 0) {
01265             ni->ni_tx_packets++;
01266             rc = 0;
01267             /* Ethernet works. Set a long waiting time in case we
01268                temporarly lose the link next time. */
01269             mx_wait = 5000;
01270         }
01271         NutEventPost(&mutex);
01272     }
01273     /*
01274      * Probably no Ethernet link. Significantly reduce the waiting
01275      * time, so following transmission will soon return an error.
01276      */
01277     else {
01278         mx_wait = 500;
01279     }
01280     return rc;
01281 }
01282 
01300 int LancInit(NUTDEVICE * dev)
01301 {
01302     /* Disable NIC interrupt and clear NICINFO structure. */
01303     cbi(EIMSK, LANC111_SIGNAL_IRQ);
01304     memset(dev->dev_dcb, 0, sizeof(NICINFO));
01305 
01306     /* Register interrupt handler and enable interrupts. */
01307     if (NutRegisterIrqHandler(&LANC111_SIGNAL, NicInterrupt, dev))
01308         return -1;
01309 
01310     /*
01311      * Start the receiver thread.
01312      */
01313     NutThreadCreate("rxi5", NicRxLanc, dev, 640);
01314 
01315     //NutSleep(500);
01316 
01317     return 0;
01318 }
01319 
01320 static NICINFO dcb_eth0;
01321 
01327 static IFNET ifn_eth0 = {
01328     IFT_ETHER,                  
01329     0,                          
01330     {0, 0, 0, 0, 0, 0},         
01331     0,                          
01332     0,                          
01333     0,                          
01334     ETHERMTU,                   
01335     0,                          
01336     0,                          
01337     0,                          
01338     NutEtherInput,              
01339     LancOutput,                 
01340     NutEtherOutput              
01341 };
01342 
01352 NUTDEVICE devSmsc111 = {
01353     0,                          /* Pointer to next device. */
01354     {'e', 't', 'h', '0', 0, 0, 0, 0, 0},        /* Unique device name. */
01355     IFTYP_NET,                  /* Type of device. */
01356     0,                          /* Base address. */
01357     0,                          /* First interrupt number. */
01358     &ifn_eth0,                  /* Interface control block. */
01359     &dcb_eth0,                  /* Driver control block. */
01360     LancInit,                   /* Driver initialization routine. */
01361     0,                          /* Driver specific control function. */
01362     0,                          /* Read from device. */
01363     0,                          /* Write to device. */
01364     0,                          /* Write from program space data to device. */
01365     0,                          /* Open a device or file. */
01366     0,                          /* Close a device or file. */
01367     0                           /* Request file size. */
01368 };
01369 

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