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00071 #include <arch/arm.h>
00072
00073 #include <string.h>
00074
00075
00076 #include <sys/atom.h>
00077 #include <sys/heap.h>
00078 #include <sys/thread.h>
00079 #include <sys/event.h>
00080 #include <sys/timer.h>
00081 #include <sys/confnet.h>
00082
00083 #include <dev/irqreg.h>
00084 #include <dev/ax88796.h>
00085 #include "reg_ax88796.h"
00086
00087 #define ASIX_RESET_PIN 10
00088
00089 static NICINFO dcb_eth0;
00090
00095
00096
00102 static IFNET ifn_eth0 = {
00103 IFT_ETHER,
00104 0,
00105 {0, 0, 0, 0, 0, 0},
00106 0,
00107 0,
00108 0,
00109 ETHERMTU,
00110 0,
00111 0,
00112 0,
00113 NutEtherInput,
00114 AsixOutput,
00115 NutEtherOutput
00116 };
00117
00127 NUTDEVICE devAx88796 = {
00128 0,
00129 {'e', 't', 'h', '0', 0, 0, 0, 0, 0},
00130 IFTYP_NET,
00131 0,
00132 0,
00133 &ifn_eth0,
00134 &dcb_eth0,
00135 AsixInit,
00136 0,
00137 0,
00138 0,
00139 0,
00140 0,
00141 0
00142 };
00143
00147 struct nic_pkt_header {
00148 uint8_t ph_status;
00149 uint8_t ph_nextpg;
00150 uint16_t ph_size;
00151 };
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162 void Delay16Cycles(void)
00163 {
00164 _NOP();
00165 _NOP();
00166 _NOP();
00167 _NOP();
00168 _NOP();
00169 _NOP();
00170 _NOP();
00171 _NOP();
00172 _NOP();
00173 _NOP();
00174 _NOP();
00175 _NOP();
00176 _NOP();
00177 _NOP();
00178 _NOP();
00179 _NOP();
00180 }
00181
00182
00188 static uint16_t MIIPutGet(uint16_t data, uint8_t bitCount)
00189 {
00190 uint16_t rc = 0;
00191 uint16_t mask;
00192 uint8_t i;
00193
00194 mask = 1 << (bitCount - 1);
00195
00196 for (i = 0; i < bitCount; i++) {
00197
00198
00199 if (data & mask) {
00200 Asix_Write(MII_EEP, (Asix_Read(MII_EEP) | MII_EEP_MDO));
00201 } else {
00202 Asix_Write(MII_EEP, (Asix_Read(MII_EEP) & ~(MII_EEP_MDO)));
00203 }
00204
00205 Asix_Write(MII_EEP, (Asix_Read(MII_EEP) | MII_EEP_MDC));
00206 Delay16Cycles();
00207
00208 data <<= 1;
00209 rc <<= 1;
00210 rc |= (Asix_Read(MII_EEP) & MII_EEP_MDI) != 0;
00211 Asix_Write(MII_EEP, (Asix_Read(MII_EEP) & ~(MII_EEP_MDC)));
00212 }
00213 return rc;
00214 }
00215
00216
00223 uint16_t NicPhyRead(uint8_t reg)
00224 {
00225 uint16_t rc = 0;
00226
00227
00228 Asix_Write(CR, (Asix_Read(CR) & ~(CR_PS0)));
00229
00230
00231 MIIPutGet(0xFFFF, 16);
00232 MIIPutGet(0xFFFF, 16);
00233
00234
00235 MIIPutGet(0xD0, 9);
00236
00237
00238 MIIPutGet(reg, 5);
00239
00240
00241 MIIPutGet(0x0, 1);
00242
00243
00244 rc = MIIPutGet(0, 16);
00245
00246 return rc;
00247 }
00248
00249
00258 void NicPhyWrite(uint8_t reg, uint16_t val)
00259 {
00260
00261
00262 Asix_Write(CR, (Asix_Read(CR) & ~(CR_PS0)));
00263
00264
00265 MIIPutGet(0xFFFF, 16);
00266 MIIPutGet(0xFFFF, 16);
00267
00268
00269 MIIPutGet(0xB0, 9);
00270
00271
00272 MIIPutGet(reg, 5);
00273
00274
00275 MIIPutGet(0x02, 2);
00276
00277
00278 MIIPutGet(val, 16);
00279 }
00280
00281
00282
00286 static void NicCompleteDma(void)
00287 {
00288 uint8_t i;
00289
00290
00291 do {
00292 i = Asix_Read(PG0_ISR);
00293 } while ((i & ISR_RDC) == 0);
00294
00295
00296 Asix_Write(CR, CR_START | CR_RD2);
00297
00298
00299 Asix_Write(PG0_ISR, ISR_RDC);
00300
00301
00302 Delay16Cycles();
00303 }
00304
00305
00311 static int NicReset(void)
00312 {
00313 int tmp;
00314
00315
00316
00317 outr(PIO_PER, _BV(ASIX_RESET_PIN));
00318 outr(PIO_OER, _BV(ASIX_RESET_PIN));
00319 outr(PIO_SODR, _BV(ASIX_RESET_PIN));
00320 NutDelay(100);
00321 outr(PIO_CODR, _BV(ASIX_RESET_PIN));
00322
00323
00324 tmp = 10;
00325 while (1) {
00326 NutDelay(255);
00327 if (!(Asix_Read(TR) & TR_RST_B))
00328 break;
00329 if (tmp-- == 0)
00330 return -1;
00331 }
00332
00333
00334
00335
00336
00337
00338
00339
00340
00341
00342
00343 return 0;
00344 }
00345
00346
00347
00348
00349
00350
00351
00352
00353
00354 static int NicStart(CONST uint8_t * mac)
00355 {
00356 uint8_t i;
00357
00358
00359 if (NicReset())
00360 return -1;
00361
00362
00363 Asix_Write(CR, (CR_RD2 | CR_STOP));
00364
00365
00366 Asix_Write(PG0_DCR, DCR_WTS);
00367
00368
00369 Asix_Write(PG0_RBCR0, 0x00);
00370 Asix_Write(PG0_RBCR1, 0x00);
00371
00372
00373 Asix_Write(PG0_RCR, RCR_MON);
00374
00375
00376 Asix_Write(PG0_TCR, TCR_LB0);
00377
00378
00379 Asix_Write(PG0_BNRY, RXSTART_INIT);
00380 Asix_Write(PG0_PSTART, RXSTART_INIT);
00381 Asix_Write(PG0_PSTOP, RXSTOP_INIT);
00382
00383
00384 Asix_Write(PG0_ISR, 0xFF);
00385
00386
00387 Asix_Write(PG0_IMR, IMR_PRXE | IMR_PTXE | IMR_RXEE | IMR_TXEE | IMR_OVWE);
00388
00389
00390 Asix_Write(CR, (CR_PS0 | CR_RD2 | CR_STOP));
00391 Delay16Cycles();
00392
00393
00394 for (i = 0; i < 6; i++) {
00395 Asix_Write(PG1_PAR0 + i, mac[i]);
00396 }
00397
00398
00399 for (i = 0; i < 8; i++) {
00400 Asix_Write(PG1_MAR0 + i, 0x00);
00401 }
00402
00403
00404 Asix_Write(PG1_CPR, RXSTART_INIT + 1);
00405
00406
00407 Asix_Write(CR, (CR_RD2 | CR_START));
00408 Delay16Cycles();
00409
00410
00411 Asix_Write(GPOC, 0x10);
00412
00413
00414 if (Asix_Read(GPI) & 0x04) {
00415
00416 Asix_Write(PG0_TCR, TCR_FDU);
00417 }
00418 else {
00419
00420 Asix_Write(PG0_TCR, 0);
00421 }
00422
00423
00424
00425 Asix_Write(PG0_RCR, RCR_AB);
00426
00427 return 0;
00428 }
00429
00430
00431
00432
00433
00434 static void NicWrite(uint8_t * buf, uint16_t len)
00435 {
00436 register uint16_t *wp = (uint16_t *) buf;
00437
00438 if (len & 1)
00439 len++;
00440 len >>= 1;
00441
00442 while (len--) {
00443
00444 Asix_WriteWord(DATAPORT, *wp);
00445 wp++;
00446 }
00447
00448 }
00449
00450
00451
00452
00453
00454 static void NicRead(uint8_t * buf, uint16_t len)
00455 {
00456 register uint16_t *wp = (uint16_t *) buf;
00457
00458 if (len & 1)
00459 len++;
00460 len >>= 1;
00461
00462 while (len--) {
00463 *wp = Asix_ReadWord(DATAPORT);
00464
00465 wp++;
00466 }
00467
00468 }
00469
00470
00481 static NETBUF *NicGetPacket(void)
00482 {
00483 NETBUF *nb = 0;
00484 struct nic_pkt_header hdr;
00485 uint16_t count;
00486 uint8_t nextpg;
00487 uint8_t bnry;
00488 uint8_t curr;
00489 uint8_t drop = 0;
00490
00491
00492 NutEnterCritical();
00493
00494
00495
00496
00497
00498 curr = Asix_Read(PG0_CPR);
00499
00500
00501
00502
00503
00504
00505
00506
00507 if ((bnry = Asix_Read(PG0_BNRY) + 1) >= RXSTOP_INIT) {
00508
00509 bnry = RXSTART_INIT;
00510 }
00511 if (bnry == curr) {
00512
00513 NutJumpOutCritical();
00514 return 0;
00515 }
00516
00517
00518
00519 Asix_Write(PG0_RBCR0, sizeof(struct nic_pkt_header));
00520 Asix_Write(PG0_RBCR1, 0);
00521 Asix_Write(PG0_RSAR0, 0);
00522 Asix_Write(PG0_RSAR1, bnry);
00523 Asix_Write(CR, CR_START | CR_RD0);
00524 Delay16Cycles();
00525
00526 NicRead((uint8_t *) & hdr, sizeof(struct nic_pkt_header));
00527 NicCompleteDma();
00528
00529
00530
00531
00532
00533 if (hdr.ph_size < 60 + sizeof(struct nic_pkt_header) || hdr.ph_size > 1514 + sizeof(struct nic_pkt_header)) {
00534
00535 drop = 1;
00536 }
00537
00538
00539
00540
00541
00542
00543
00544
00545
00546
00547
00548
00549
00550
00551
00552 nextpg = bnry + (hdr.ph_size >> 8) + ((hdr.ph_size & 0xFF) != 0);
00553
00554
00555 if (nextpg >= RXSTOP_INIT) {
00556 nextpg -= RXSTOP_INIT;
00557 nextpg += RXSTART_INIT;
00558 }
00559 if (nextpg != hdr.ph_nextpg) {
00560 uint8_t nextpg1 = nextpg + 1;
00561 if (nextpg1 >= RXSTOP_INIT) {
00562 nextpg1 -= RXSTOP_INIT;
00563 nextpg1 += RXSTART_INIT;
00564 }
00565
00566
00567
00568 nextpg = nextpg1;
00569 }
00570
00571
00572
00573
00574
00575
00576
00577
00578 if (!drop && ((hdr.ph_status & 0x0E) == 0)) {
00579
00580
00581 count = hdr.ph_size - sizeof(struct nic_pkt_header);
00582
00583 if ((nb = NutNetBufAlloc(0, NBAF_DATALINK, count))) {
00584
00585
00586
00587
00588
00589 Asix_Write(PG0_RBCR0, count);
00590 Asix_Write(PG0_RBCR1, count >> 8);
00591 Asix_Write(PG0_RSAR0, sizeof(struct nic_pkt_header));
00592 Asix_Write(PG0_RSAR1, bnry);
00593
00594
00595
00596
00597 Asix_Write(CR, CR_START | CR_RD0);
00598 Delay16Cycles();
00599 NicRead(nb->nb_dl.vp, count);
00600 NicCompleteDma();
00601 }
00602 }
00603
00604
00605
00606
00607
00608 if (--nextpg < RXSTART_INIT)
00609 nextpg = RXSTOP_INIT - 1;
00610 Asix_Write(PG0_BNRY, nextpg);
00611 NutExitCritical();
00612 return nb;
00613
00614 }
00615
00616
00617
00618
00619
00620
00621
00622
00623
00624
00625
00626
00627
00628
00629
00630
00631
00632
00633
00634
00635 static uint8_t NicOverflow(volatile uint8_t * base)
00636 {
00637 u_int cr;
00638 u_int resend = 0;
00639 u_int curr;
00640
00641
00642
00643
00644
00645
00646 while (Asix_Read(CR) & CR_TXP);
00647 cr = Asix_Read(CR);
00648
00649
00650
00651
00652
00653 Asix_Write(CR, CR_STOP | CR_RD2 | CR_PS0);
00654 curr = Asix_Read(PG1_CPR);
00655 Asix_Write(CR, CR_STOP | CR_RD2);
00656
00657
00658 Asix_Write(PG0_RBCR0, 0);
00659 Asix_Write(PG0_RBCR1, 0);
00660
00661
00662 if ((cr & CR_TXP) && ((Asix_Read(PG0_ISR) & (ISR_PTX | ISR_TXE)) == 0)) {
00663 resend = 1;
00664 }
00665
00666
00667 Asix_Write(PG0_TCR, TCR_LB0);
00668 Asix_Write(CR, CR_START | CR_RD2);
00669
00670
00671
00672
00673
00674 if (--curr < TXSTART_INIT) {
00675 curr = RXSTOP_INIT - 1;
00676 }
00677 Asix_Write(PG0_BNRY, curr);
00678
00679
00680 Asix_Write(PG0_TCR, 0);
00681
00682
00683 if (resend) {
00684 Asix_Write(CR, CR_START | CR_TXP | CR_RD2);
00685 }
00686
00687
00688 Asix_Write(PG0_ISR, ISR_OVW);
00689 return resend;
00690 }
00691
00692
00693 static int NicPutPacket(NETBUF * nb)
00694 {
00695 uint16_t sz;
00696 uint16_t send_sz;
00697 static uint8_t first_put = 0;
00698 int tmp;
00699
00700
00701
00702
00703
00704 if (first_put != 1) {
00705 Asix_Write(CR, 0x21);
00706 NutDelay(1);
00707 Asix_Write(CR, 0x22);
00708 first_put = 1;
00709 }
00710
00711
00712
00713
00714
00715 sz = nb->nb_dl.sz + nb->nb_nw.sz + nb->nb_tp.sz + nb->nb_ap.sz;
00716 if (sz > 1518)
00717 return -1;
00718
00719
00720
00721
00722
00723
00724 send_sz = sz;
00725 if (sz <= 60)
00726 send_sz = 60;
00727
00728
00729 NutEnterCritical();
00730
00731 Asix_Write(CR, (CR_RD2 | CR_START));
00732
00733
00734
00735
00736
00737
00738
00739 tmp = 120;
00740 while ((Asix_Read(CR) & CR_TXP) && tmp--)
00741 NutDelay(1);
00742
00743
00744
00745 Asix_Write(PG0_RSAR0, 0x00);
00746 Asix_Write(PG0_RSAR1, TXSTART_INIT);
00747
00748
00749 Asix_Write(PG0_RBCR0, (unsigned char) (sz));
00750 Asix_Write(PG0_RBCR1, (unsigned char) (sz >> 8));
00751
00752
00753 Asix_Write(CR, (CR_RD1 | CR_START));
00754
00755
00756 NicWrite(nb->nb_dl.vp, nb->nb_dl.sz);
00757 NicWrite(nb->nb_nw.vp, nb->nb_nw.sz);
00758 NicWrite(nb->nb_tp.vp, nb->nb_tp.sz);
00759 NicWrite(nb->nb_ap.vp, nb->nb_ap.sz);
00760
00761
00762 NicCompleteDma();
00763
00764
00765 Asix_Write(PG0_ISR, (ISR_PTX | ISR_TXE));
00766 Delay16Cycles();
00767
00768
00769 Asix_Write(CR, CR_START | CR_RD2);
00770
00771 Asix_Write(PG0_TBCR0, (unsigned char) (send_sz));
00772 Asix_Write(PG0_TBCR1, (unsigned char) ((send_sz) >> 8));
00773 Asix_Write(PG0_TPSR, TXSTART_INIT);
00774
00775
00776 Asix_Write(CR, CR_START | CR_TXP | CR_RD2);
00777
00778
00779 NutExitCritical();
00780 return 0;
00781 }
00782
00783
00788 THREAD(NicRxAsix, arg)
00789 {
00790
00791 NUTDEVICE *dev;
00792 IFNET *ifn;
00793 NICINFO *ni;
00794 NETBUF *nb;
00795
00796
00797 dev = &devAx88796;
00798
00799 ifn = (IFNET *) dev->dev_icb;
00800 ni = (NICINFO *) dev->dev_dcb;
00801
00802 for (;;) {
00803 if (*((uint32_t *) (ifn->if_mac)) && *((uint32_t *) (ifn->if_mac)) != 0xFFFFFFFFUL) {
00804 break;
00805 }
00806 NutSleep(63);
00807 }
00808
00809 NutEnterCritical();
00810 NicStart(ifn->if_mac);
00811 NutExitCritical();
00812
00813
00814
00815 NutThreadSetPriority(9);
00816
00817 while (1) {
00818
00819 NutEventWait(&ni->ni_rx_rdy, 0);
00820
00821
00822
00823
00824
00825 do {
00826 nb = NicGetPacket();
00827
00828
00829 if (0) {
00830 NicStart(ifn->if_mac);
00831
00832 } else if (nb) {
00833 ni->ni_rx_packets++;
00834 (*ifn->if_recv) (dev, nb);
00835 }
00836 } while (nb);
00837 }
00838 }
00839
00840
00841
00842
00843
00844 static void NicInterrupt(void *arg)
00845 {
00846 uint8_t isr;
00847 volatile uint8_t *base = (uint8_t *) (((NUTDEVICE *) arg)->dev_base);
00848 NICINFO *ni = (NICINFO *) ((NUTDEVICE *) arg)->dev_dcb;
00849
00850 ni->ni_interrupts++;
00851
00852 isr = Asix_Read(PG0_ISR);
00853 Delay16Cycles();
00854 Asix_Write(PG0_ISR, isr);
00855
00856
00857
00858
00859
00860
00861
00862
00863
00864
00865
00866 if (isr & ISR_OVW) {
00867 ni->ni_rx_pending++;
00868 if (NicOverflow(base))
00869 ni->ni_tx_bsy++;
00870 else {
00871 NutEventPostAsync(&ni->ni_tx_rdy);
00872 }
00873 ni->ni_overruns++;
00874 } else {
00875
00876
00877
00878
00879
00880
00881 if (isr & (ISR_PTX | ISR_TXE)) {
00882 ni->ni_tx_bsy = 0;
00883 }
00884
00885
00886
00887
00888
00889 if (isr & ISR_PRX) {
00890 ni->ni_rx_pending++;
00891
00892 NutEventPostFromIrq(&ni->ni_rx_rdy);
00893 }
00894
00895
00896 if (isr & ISR_RXE) {
00897 if (Asix_Read(PG0_RSR) & RSR_FAE)
00898 ni->ni_rx_frame_errors++;
00899 if (Asix_Read(PG0_RSR) & RSR_CR)
00900 ni->ni_rx_crc_errors++;
00901 if (Asix_Read(PG0_RSR) & RSR_MPA)
00902 ni->ni_rx_missed_errors++;
00903 }
00904 }
00905 }
00906
00907 void NicInterruptEntry(void) __attribute__ ((naked));
00908 void NicInterruptEntry(void)
00909 {
00910 IRQ_ENTRY();
00911
00912 NicInterrupt(&devAx88796);
00913 IRQ_EXIT();
00914 }
00915
00916
00927 int AsixOutput(NUTDEVICE * dev, NETBUF * nb)
00928 {
00929 int rc = -1;
00930 NICINFO *ni = (NICINFO *) dev->dev_dcb;
00931
00932 if (NicPutPacket(nb) == 0) {
00933 ni->ni_tx_packets++;
00934 rc = 0;
00935 }
00936 return rc;
00937 }
00938
00939
00957 int AsixInit(NUTDEVICE * dev)
00958 {
00959
00960 confnet.cd_size = sizeof(CONFNET);
00961 strcpy(confnet.cd_name, "eth0");
00962 memset(confnet.cdn_mac, 0xFF, 6);
00963
00964
00965
00966 memset(dev->dev_dcb, 0, sizeof(NICINFO));
00967
00968
00969
00970
00971
00972 NutThreadCreate("rxi5", NicRxAsix, dev, 1024);
00973
00974 outr(PIO_PDR, _BV(9));
00975
00976
00977 outr(AIC_IDCR, _BV(IRQ0_ID));
00978
00979 outr(AIC_SVR(IRQ0_ID), (unsigned int) NicInterruptEntry);
00980
00981
00982 outr(AIC_SMR(IRQ0_ID), (AIC_SRCTYPE_EXT_NEGATIVE_EDGE | 5));
00983
00984 outr(AIC_ICCR, _BV(IRQ0_ID));
00985
00986 outr(AIC_IECR, _BV(IRQ0_ID));
00987
00988
00989 return 0;
00990 }
00991