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00050 #include <arch/arm.h>
00051 #include <dev/irqreg.h>
00052
00053 #ifndef NUT_IRQPRI_IRQ1
00054 #define NUT_IRQPRI_IRQ1 4
00055 #endif
00056
00057 static int Interrupt1Ctl(int cmd, void *param);
00058
00059 IRQ_HANDLER sig_INTERRUPT1 = {
00060 #ifdef NUT_PERFMON
00061 0,
00062 #endif
00063 NULL,
00064 NULL,
00065 Interrupt1Ctl
00066 };
00067
00071 static void Interrupt1Entry(void) __attribute__ ((naked));
00072 void Interrupt1Entry(void)
00073 {
00074 IRQ_ENTRY();
00075 #ifdef NUT_PERFMON
00076 sig_INTERRUPT1.ir_count++;
00077 #endif
00078 if (sig_INTERRUPT1.ir_handler) {
00079 (sig_INTERRUPT1.ir_handler) (sig_INTERRUPT1.ir_arg);
00080 }
00081 IRQ_EXIT();
00082 }
00083
00099 static int Interrupt1Ctl(int cmd, void *param)
00100 {
00101 int rc = 0;
00102 unsigned int *ival = (unsigned int *)param;
00103 int_fast8_t enabled = inr(AIC_IMR) & _BV(IRQ1_ID);
00104
00105
00106 if (enabled) {
00107 outr(AIC_IDCR, _BV(IRQ1_ID));
00108 }
00109
00110 switch(cmd) {
00111 case NUT_IRQCTL_INIT:
00112
00113 outr(AIC_SVR(IRQ1_ID), (unsigned int)Interrupt1Entry);
00114
00115 outr(AIC_SMR(IRQ1_ID), AIC_SRCTYPE_EXT_HIGH_LEVEL | NUT_IRQPRI_IRQ1);
00116
00117 outr(AIC_ICCR, _BV(IRQ1_ID));
00118 break;
00119 case NUT_IRQCTL_STATUS:
00120 if (enabled) {
00121 *ival |= 1;
00122 }
00123 else {
00124 *ival &= ~1;
00125 }
00126 break;
00127 case NUT_IRQCTL_ENABLE:
00128 enabled = 1;
00129 break;
00130 case NUT_IRQCTL_DISABLE:
00131 enabled = 0;
00132 break;
00133 case NUT_IRQCTL_GETMODE:
00134 {
00135 unsigned int val = inr(AIC_SMR(IRQ1_ID)) & AIC_SRCTYPE;
00136 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00137 *ival = NUT_IRQMODE_LOWLEVEL;
00138 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00139 *ival = NUT_IRQMODE_HIGHLEVEL;
00140 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00141 *ival = NUT_IRQMODE_RISINGEDGE;
00142 } else {
00143 *ival = NUT_IRQMODE_FALLINGEDGE;
00144 }
00145 }
00146 break;
00147 case NUT_IRQCTL_SETMODE:
00148 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00149 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00150 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00151 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00152 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00153 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00154 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00155 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00156 } else {
00157 rc = -1;
00158 }
00159 break;
00160 case NUT_IRQCTL_GETPRIO:
00161 *ival = inr(AIC_SMR(IRQ1_ID)) & AIC_PRIOR;
00162 break;
00163 case NUT_IRQCTL_SETPRIO:
00164 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_PRIOR) | *ival);
00165 break;
00166 #ifdef NUT_PERFMON
00167 case NUT_IRQCTL_GETCOUNT:
00168 *ival = (unsigned int)sig_INTERRUPT1.ir_count;
00169 sig_INTERRUPT1.ir_count = 0;
00170 break;
00171 #endif
00172 default:
00173 rc = -1;
00174 break;
00175 }
00176
00177
00178 if (enabled) {
00179 outr(AIC_IECR, _BV(IRQ1_ID));
00180 }
00181 return rc;
00182 }
00183