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00051 #include <arch/arm.h>
00052 #include <dev/irqreg.h>
00053
00054 #ifndef NUT_IRQPRI_TC0
00055 #define NUT_IRQPRI_TC0 0
00056 #endif
00057
00058 static int TimerCounter0IrqCtl(int cmd, void *param);
00059
00060 IRQ_HANDLER sig_TC0 = {
00061 #ifdef NUT_PERFMON
00062 0,
00063 #endif
00064 NULL,
00065 NULL,
00066 TimerCounter0IrqCtl
00067 };
00068
00072 static u_int dummy;
00073 static void TimerCounter0IrqEntry(void) __attribute__ ((naked));
00074 void TimerCounter0IrqEntry(void)
00075 {
00076 IRQ_ENTRY();
00077 #ifdef NUT_PERFMON
00078 sig_TC0.ir_count++;
00079 #endif
00080 dummy = inr(TC0_SR);
00081 if (sig_TC0.ir_handler) {
00082 (sig_TC0.ir_handler) (sig_TC0.ir_arg);
00083 }
00084 IRQ_EXIT();
00085 }
00086
00104 static int TimerCounter0IrqCtl(int cmd, void *param)
00105 {
00106 int rc = 0;
00107 u_int *ival = (u_int *)param;
00108 int enabled = inr(AIC_IMR) & _BV(TC0_ID);
00109
00110
00111 if (enabled) {
00112 outr(AIC_IDCR, _BV(TC0_ID));
00113 }
00114
00115 switch(cmd) {
00116 case NUT_IRQCTL_INIT:
00117
00118 outr(AIC_SVR(TC0_ID), (unsigned int)TimerCounter0IrqEntry);
00119
00120 outr(AIC_SMR(TC0_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC0);
00121
00122 outr(AIC_ICCR, _BV(TC0_ID));
00123 break;
00124 case NUT_IRQCTL_STATUS:
00125 if (enabled) {
00126 *ival |= 1;
00127 }
00128 else {
00129 *ival &= ~1;
00130 }
00131 break;
00132 case NUT_IRQCTL_ENABLE:
00133 enabled = 1;
00134 break;
00135 case NUT_IRQCTL_DISABLE:
00136 enabled = 0;
00137 break;
00138 case NUT_IRQCTL_GETMODE:
00139 {
00140 u_int val = inr(AIC_SMR(TC0_ID)) & AIC_SRCTYPE;
00141 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00142 *ival = NUT_IRQMODE_LEVEL;
00143 } else {
00144 *ival = NUT_IRQMODE_EDGE;
00145 }
00146 }
00147 break;
00148 case NUT_IRQCTL_SETMODE:
00149 if (*ival == NUT_IRQMODE_LEVEL) {
00150 outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00151 } else if (*ival == NUT_IRQMODE_EDGE) {
00152 outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00153 } else {
00154 rc = -1;
00155 }
00156 break;
00157 case NUT_IRQCTL_GETPRIO:
00158 *ival = inr(AIC_SMR(TC0_ID)) & AIC_PRIOR;
00159 break;
00160 case NUT_IRQCTL_SETPRIO:
00161 outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_PRIOR) | *ival);
00162 break;
00163 #ifdef NUT_PERFMON
00164 case NUT_IRQCTL_GETCOUNT:
00165 *ival = (u_int)sig_TC0.ir_count;
00166 sig_TC0.ir_count = 0;
00167 break;
00168 #endif
00169 default:
00170 rc = -1;
00171 break;
00172 }
00173
00174
00175 if (enabled) {
00176 outr(AIC_IECR, _BV(TC0_ID));
00177 }
00178 return rc;
00179 }