sppif0.h

Go to the documentation of this file.
00001 #ifndef _DEV_SPPIF0_H_
00002 #define _DEV_SPPIF0_H_
00003 /*
00004  * Copyright (C) 2007 by egnite Software GmbH. All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * 1. Redistributions of source code must retain the above copyright
00011  *    notice, this list of conditions and the following disclaimer.
00012  * 2. Redistributions in binary form must reproduce the above copyright
00013  *    notice, this list of conditions and the following disclaimer in the
00014  *    documentation and/or other materials provided with the distribution.
00015  * 3. Neither the name of the copyright holders nor the names of
00016  *    contributors may be used to endorse or promote products derived
00017  *    from this software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00020  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00021  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00022  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00023  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00024  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00025  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00026  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00027  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00028  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00029  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00030  * SUCH DAMAGE.
00031  *
00032  * For additional information see http://www.ethernut.de/
00033  */
00034 
00049 #include <cfg/arch/gpio.h>
00050 
00054 #ifndef SPPI0_MAX_DEVICES
00055 #define SPPI0_MAX_DEVICES   4
00056 #endif
00057 
00058 #if defined(__AVR__)            /* MCU */
00059 /*
00060  * AVR implementation.
00061  * ======================================
00062  */
00063 
00064 #ifdef SPPI0_CS0_BIT
00065 
00066 #if (SPPI0_CS0_AVRPORT == AVRPORTB)
00067 #define SPPI0_CS0_SOD_REG PORTB
00068 #define SPPI0_CS0_OE_REG  DDRB
00069 #elif (SPPI0_CS0_AVRPORT == AVRPORTD)
00070 #define SPPI0_CS0_SOD_REG PORTD
00071 #define SPPI0_CS0_OE_REG  DDRD
00072 #elif (SPPI0_CS0_AVRPORT == AVRPORTE)
00073 #define SPPI0_CS0_SOD_REG PORTE
00074 #define SPPI0_CS0_OE_REG  DDRE
00075 #elif (SPPI0_CS0_AVRPORT == AVRPORTF)
00076 #define SPPI0_CS0_SOD_REG PORTF
00077 #define SPPI0_CS0_OE_REG  DDRF
00078 #elif (SPPI0_CS0_AVRPORT == AVRPORTG)
00079 #define SPPI0_CS0_SOD_REG PORTG
00080 #define SPPI0_CS0_OE_REG  DDRG
00081 #elif (SPPI0_CS0_AVRPORT == AVRPORTH)
00082 #define SPPI0_CS0_SOD_REG PORTH
00083 #define SPPI0_CS0_OE_REG  DDRH
00084 #endif
00085 
00087 #define SPPI0_CS0_ENA()      sbi(SPPI0_CS0_OE_REG, SPPI0_CS0_BIT)
00088 
00089 #define SPPI0_CS0_CLR()      cbi(SPPI0_CS0_SOD_REG, SPPI0_CS0_BIT)
00090 
00091 #define SPPI0_CS0_SET()      sbi(SPPI0_CS0_SOD_REG, SPPI0_CS0_BIT)
00092 
00093 #endif                          /* SPPI0_CS0_BIT */
00094 
00095 #ifdef SPPI0_CS1_BIT
00096 
00097 #if (SPPI0_CS1_AVRPORT == AVRPORTB)
00098 #define SPPI0_CS1_SOD_REG PORTB
00099 #define SPPI0_CS1_OE_REG  DDRB
00100 #elif (SPPI0_CS1_AVRPORT == AVRPORTD)
00101 #define SPPI0_CS1_SOD_REG PORTD
00102 #define SPPI0_CS1_OE_REG  DDRD
00103 #elif (SPPI0_CS1_AVRPORT == AVRPORTE)
00104 #define SPPI0_CS1_SOD_REG PORTE
00105 #define SPPI0_CS1_OE_REG  DDRE
00106 #elif (SPPI0_CS1_AVRPORT == AVRPORTF)
00107 #define SPPI0_CS1_SOD_REG PORTF
00108 #define SPPI0_CS1_OE_REG  DDRF
00109 #elif (SPPI0_CS1_AVRPORT == AVRPORTG)
00110 #define SPPI0_CS1_SOD_REG PORTG
00111 #define SPPI0_CS1_OE_REG  DDRG
00112 #elif (SPPI0_CS1_AVRPORT == AVRPORTH)
00113 #define SPPI0_CS1_SOD_REG PORTH
00114 #define SPPI0_CS1_OE_REG  DDRH
00115 #endif
00116 
00118 #define SPPI0_CS1_ENA()      sbi(SPPI0_CS1_OE_REG, SPPI0_CS1_BIT)
00119 
00120 #define SPPI0_CS1_CLR()      cbi(SPPI0_CS1_SOD_REG, SPPI0_CS1_BIT)
00121 
00122 #define SPPI0_CS1_SET()      sbi(SPPI0_CS1_SOD_REG, SPPI0_CS1_BIT)
00123 
00124 #endif                          /* SPPI0_CS1_BIT */
00125 
00126 #ifdef SPPI0_CS2_BIT
00127 
00128 #if (SPPI0_CS2_AVRPORT == AVRPORTB)
00129 #define SPPI0_CS2_SOD_REG PORTB
00130 #define SPPI0_CS2_OE_REG  DDRB
00131 #elif (SPPI0_CS2_AVRPORT == AVRPORTD)
00132 #define SPPI0_CS2_SOD_REG PORTD
00133 #define SPPI0_CS2_OE_REG  DDRD
00134 #elif (SPPI0_CS2_AVRPORT == AVRPORTE)
00135 #define SPPI0_CS2_SOD_REG PORTE
00136 #define SPPI0_CS2_OE_REG  DDRE
00137 #elif (SPPI0_CS2_AVRPORT == AVRPORTF)
00138 #define SPPI0_CS2_SOD_REG PORTF
00139 #define SPPI0_CS2_OE_REG  DDRF
00140 #elif (SPPI0_CS2_AVRPORT == AVRPORTG)
00141 #define SPPI0_CS2_SOD_REG PORTG
00142 #define SPPI0_CS2_OE_REG  DDRG
00143 #elif (SPPI0_CS2_AVRPORT == AVRPORTH)
00144 #define SPPI0_CS2_SOD_REG PORTH
00145 #define SPPI0_CS2_OE_REG  DDRH
00146 #endif
00147 
00149 #define SPPI0_CS2_ENA()      sbi(SPPI0_CS2_OE_REG, SPPI0_CS2_BIT)
00150 
00151 #define SPPI0_CS2_CLR()      cbi(SPPI0_CS2_SOD_REG, SPPI0_CS2_BIT)
00152 
00153 #define SPPI0_CS2_SET()      sbi(SPPI0_CS2_SOD_REG, SPPI0_CS2_BIT)
00154 
00155 #endif                          /* SPPI0_CS2_BIT */
00156 
00157 #ifdef SPPI0_CS3_BIT
00158 
00159 #if (SPPI0_CS3_AVRPORT == AVRPORTB)
00160 #define SPPI0_CS3_SOD_REG PORTB
00161 #define SPPI0_CS3_OE_REG  DDRB
00162 #elif (SPPI0_CS3_AVRPORT == AVRPORTD)
00163 #define SPPI0_CS3_SOD_REG PORTD
00164 #define SPPI0_CS3_OE_REG  DDRD
00165 #elif (SPPI0_CS3_AVRPORT == AVRPORTE)
00166 #define SPPI0_CS3_SOD_REG PORTE
00167 #define SPPI0_CS3_OE_REG  DDRE
00168 #elif (SPPI0_CS3_AVRPORT == AVRPORTF)
00169 #define SPPI0_CS3_SOD_REG PORTF
00170 #define SPPI0_CS3_OE_REG  DDRF
00171 #elif (SPPI0_CS3_AVRPORT == AVRPORTG)
00172 #define SPPI0_CS3_SOD_REG PORTG
00173 #define SPPI0_CS3_OE_REG  DDRG
00174 #elif (SPPI0_CS3_AVRPORT == AVRPORTH)
00175 #define SPPI0_CS3_SOD_REG PORTH
00176 #define SPPI0_CS3_OE_REG  DDRH
00177 #endif
00178 
00180 #define SPPI0_CS3_ENA()      sbi(SPPI0_CS3_OE_REG, SPPI0_CS3_BIT)
00181 
00182 #define SPPI0_CS3_CLR()      cbi(SPPI0_CS3_SOD_REG, SPPI0_CS3_BIT)
00183 
00184 #define SPPI0_CS3_SET()      sbi(SPPI0_CS3_SOD_REG, SPPI0_CS3_BIT)
00185 
00186 #endif                          /* SPPI0_CS3_BIT */
00187 
00188 #ifdef SPPI0_RST0_BIT
00189 
00190 #if (SPPI0_RST0_AVRPORT == AVRPORTB)
00191 #define SPPI0_RST0_SOD_REG PORTB
00192 #define SPPI0_RST0_OE_REG  DDRB
00193 #elif (SPPI0_RST0_AVRPORT == AVRPORTD)
00194 #define SPPI0_RST0_SOD_REG PORTD
00195 #define SPPI0_RST0_OE_REG  DDRD
00196 #elif (SPPI0_RST0_AVRPORT == AVRPORTE)
00197 #define SPPI0_RST0_SOD_REG PORTE
00198 #define SPPI0_RST0_OE_REG  DDRE
00199 #elif (SPPI0_RST0_AVRPORT == AVRPORTF)
00200 #define SPPI0_RST0_SOD_REG PORTF
00201 #define SPPI0_RST0_OE_REG  DDRF
00202 #elif (SPPI0_RST0_AVRPORT == AVRPORTG)
00203 #define SPPI0_RST0_SOD_REG PORTG
00204 #define SPPI0_RST0_OE_REG  DDRG
00205 #elif (SPPI0_RST0_AVRPORT == AVRPORTH)
00206 #define SPPI0_RST0_SOD_REG PORTH
00207 #define SPPI0_RST0_OE_REG  DDRH
00208 #endif
00209 
00211 #define SPPI0_RST0_ENA()      sbi(SPPI0_RST0_OE_REG, SPPI0_RST0_BIT)
00212 
00213 #define SPPI0_RST0_CLR()      cbi(SPPI0_RST0_SOD_REG, SPPI0_RST0_BIT)
00214 
00215 #define SPPI0_RST0_SET()      sbi(SPPI0_RST0_SOD_REG, SPPI0_RST0_BIT)
00216 
00217 #endif                          /* SPPI0_RST0_BIT */
00218 
00219 #ifdef SPPI0_RST1_BIT
00220 
00221 #if (SPPI0_RST1_AVRPORT == AVRPORTB)
00222 #define SPPI0_RST1_SOD_REG PORTB
00223 #define SPPI0_RST1_OE_REG  DDRB
00224 #elif (SPPI0_RST1_AVRPORT == AVRPORTD)
00225 #define SPPI0_RST1_SOD_REG PORTD
00226 #define SPPI0_RST1_OE_REG  DDRD
00227 #elif (SPPI0_RST1_AVRPORT == AVRPORTE)
00228 #define SPPI0_RST1_SOD_REG PORTE
00229 #define SPPI0_RST1_OE_REG  DDRE
00230 #elif (SPPI0_RST1_AVRPORT == AVRPORTF)
00231 #define SPPI0_RST1_SOD_REG PORTF
00232 #define SPPI0_RST1_OE_REG  DDRF
00233 #elif (SPPI0_RST1_AVRPORT == AVRPORTG)
00234 #define SPPI0_RST1_SOD_REG PORTG
00235 #define SPPI0_RST1_OE_REG  DDRG
00236 #elif (SPPI0_RST1_AVRPORT == AVRPORTH)
00237 #define SPPI0_RST1_SOD_REG PORTH
00238 #define SPPI0_RST1_OE_REG  DDRH
00239 #endif
00240 
00242 #define SPPI0_RST1_ENA()      sbi(SPPI0_RST1_OE_REG, SPPI0_RST1_BIT)
00243 
00244 #define SPPI0_RST1_CLR()      cbi(SPPI0_RST1_SOD_REG, SPPI0_RST1_BIT)
00245 
00246 #define SPPI0_RST1_SET()      sbi(SPPI0_RST1_SOD_REG, SPPI0_RST1_BIT)
00247 
00248 #endif                          /* SPPI0_RST1_BIT */
00249 
00250 #ifdef SPPI0_RST2_BIT
00251 
00252 #if (SPPI0_RST2_AVRPORT == AVRPORTB)
00253 #define SPPI0_RST2_SOD_REG PORTB
00254 #define SPPI0_RST2_OE_REG  DDRB
00255 #elif (SPPI0_RST2_AVRPORT == AVRPORTD)
00256 #define SPPI0_RST2_SOD_REG PORTD
00257 #define SPPI0_RST2_OE_REG  DDRD
00258 #elif (SPPI0_RST2_AVRPORT == AVRPORTE)
00259 #define SPPI0_RST2_SOD_REG PORTE
00260 #define SPPI0_RST2_OE_REG  DDRE
00261 #elif (SPPI0_RST2_AVRPORT == AVRPORTF)
00262 #define SPPI0_RST2_SOD_REG PORTF
00263 #define SPPI0_RST2_OE_REG  DDRF
00264 #elif (SPPI0_RST2_AVRPORT == AVRPORTG)
00265 #define SPPI0_RST2_SOD_REG PORTG
00266 #define SPPI0_RST2_OE_REG  DDRG
00267 #elif (SPPI0_RST2_AVRPORT == AVRPORTH)
00268 #define SPPI0_RST2_SOD_REG PORTH
00269 #define SPPI0_RST2_OE_REG  DDRH
00270 #endif
00271 
00273 #define SPPI0_RST2_ENA()      sbi(SPPI0_RST2_OE_REG, SPPI0_RST2_BIT)
00274 
00275 #define SPPI0_RST2_CLR()      cbi(SPPI0_RST2_SOD_REG, SPPI0_RST2_BIT)
00276 
00277 #define SPPI0_RST2_SET()      sbi(SPPI0_RST2_SOD_REG, SPPI0_RST2_BIT)
00278 
00279 #endif                          /* SPPI0_RST2_BIT */
00280 
00281 #ifdef SPPI0_RST3_BIT
00282 
00283 #if (SPPI0_RST3_AVRPORT == AVRPORTB)
00284 #define SPPI0_RST3_SOD_REG PORTB
00285 #define SPPI0_RST3_OE_REG  DDRB
00286 #elif (SPPI0_RST3_AVRPORT == AVRPORTD)
00287 #define SPPI0_RST3_SOD_REG PORTD
00288 #define SPPI0_RST3_OE_REG  DDRD
00289 #elif (SPPI0_RST3_AVRPORT == AVRPORTE)
00290 #define SPPI0_RST3_SOD_REG PORTE
00291 #define SPPI0_RST3_OE_REG  DDRE
00292 #elif (SPPI0_RST3_AVRPORT == AVRPORTF)
00293 #define SPPI0_RST3_SOD_REG PORTF
00294 #define SPPI0_RST3_OE_REG  DDRF
00295 #elif (SPPI0_RST3_AVRPORT == AVRPORTG)
00296 #define SPPI0_RST3_SOD_REG PORTG
00297 #define SPPI0_RST3_OE_REG  DDRG
00298 #elif (SPPI0_RST3_AVRPORT == AVRPORTH)
00299 #define SPPI0_RST3_SOD_REG PORTH
00300 #define SPPI0_RST3_OE_REG  DDRH
00301 #endif
00302 
00304 #define SPPI0_RST3_ENA()      sbi(SPPI0_RST3_OE_REG, SPPI0_RST3_BIT)
00305 
00306 #define SPPI0_RST3_CLR()      cbi(SPPI0_RST3_SOD_REG, SPPI0_RST3_BIT)
00307 
00308 #define SPPI0_RST3_SET()      sbi(SPPI0_RST3_SOD_REG, SPPI0_RST3_BIT)
00309 
00310 #endif                          /* SPPI0_RST3_BIT */
00311 
00312 
00313 #else                           /* MCU */
00314 /*
00315  * AT91 implementation.
00316  * ======================================
00317  */
00318 
00319 #ifdef SPPI0_CS0_BIT
00320 
00321 #if !defined(SPPI0_CS0_PIO_ID)
00322 #define SPPI0_CS0_PE_REG        PIO_PER
00323 #define SPPI0_CS0_OE_REG        PIO_OER
00324 #define SPPI0_CS0_COD_REG       PIO_CODR
00325 #define SPPI0_CS0_SOD_REG       PIO_SODR
00326 #elif SPPI0_CS0_PIO_ID == PIO_ID
00327 #define SPPI0_CS0_PE_REG        PIO_PER
00328 #define SPPI0_CS0_OE_REG        PIO_OER
00329 #define SPPI0_CS0_COD_REG       PIO_CODR
00330 #define SPPI0_CS0_SOD_REG       PIO_SODR
00331 #elif SPPI0_CS0_PIO_ID == PIOA_ID
00332 #define SPPI0_CS0_PE_REG        PIOA_PER
00333 #define SPPI0_CS0_OE_REG        PIOA_OER
00334 #define SPPI0_CS0_COD_REG       PIOA_CODR
00335 #define SPPI0_CS0_SOD_REG       PIOA_SODR
00336 #elif SPPI0_CS0_PIO_ID == PIOB_ID
00337 #define SPPI0_CS0_PE_REG        PIOB_PER
00338 #define SPPI0_CS0_OE_REG        PIOB_OER
00339 #define SPPI0_CS0_COD_REG       PIOB_CODR
00340 #define SPPI0_CS0_SOD_REG       PIOB_SODR
00341 #elif SPPI0_CS0_PIO_ID == PIOC_ID
00342 #define SPPI0_CS0_PE_REG        PIOC_PER
00343 #define SPPI0_CS0_OE_REG        PIOC_OER
00344 #define SPPI0_CS0_COD_REG       PIOC_CODR
00345 #define SPPI0_CS0_SOD_REG       PIOC_SODR
00346 #endif
00347 
00349 #define SPPI0_CS0_ENA() \
00350     outr(SPPI0_CS0_PE_REG, _BV(SPPI0_CS0_BIT)); \
00351     outr(SPPI0_CS0_OE_REG, _BV(SPPI0_CS0_BIT))
00352 
00353 #define SPPI0_CS0_CLR()   outr(SPPI0_CS0_COD_REG, _BV(SPPI0_CS0_BIT))
00354 
00355 #define SPPI0_CS0_SET()   outr(SPPI0_CS0_SOD_REG, _BV(SPPI0_CS0_BIT))
00356 
00357 #endif                          /* SPPI0_CS0_BIT */
00358 
00359 #ifdef SPPI0_CS1_BIT
00360 
00361 #if !defined(SPPI0_CS1_PIO_ID)
00362 #define SPPI0_CS1_PE_REG        PIO_PER
00363 #define SPPI0_CS1_OE_REG        PIO_OER
00364 #define SPPI0_CS1_COD_REG       PIO_CODR
00365 #define SPPI0_CS1_SOD_REG       PIO_SODR
00366 #elif SPPI0_CS1_PIO_ID == PIO_ID
00367 #define SPPI0_CS1_PE_REG        PIO_PER
00368 #define SPPI0_CS1_OE_REG        PIO_OER
00369 #define SPPI0_CS1_COD_REG       PIO_CODR
00370 #define SPPI0_CS1_SOD_REG       PIO_SODR
00371 #elif SPPI0_CS1_PIO_ID == PIOA_ID
00372 #define SPPI0_CS1_PE_REG        PIOA_PER
00373 #define SPPI0_CS1_OE_REG        PIOA_OER
00374 #define SPPI0_CS1_COD_REG       PIOA_CODR
00375 #define SPPI0_CS1_SOD_REG       PIOA_SODR
00376 #elif SPPI0_CS1_PIO_ID == PIOB_ID
00377 #define SPPI0_CS1_PE_REG        PIOB_PER
00378 #define SPPI0_CS1_OE_REG        PIOB_OER
00379 #define SPPI0_CS1_COD_REG       PIOB_CODR
00380 #define SPPI0_CS1_SOD_REG       PIOB_SODR
00381 #elif SPPI0_CS1_PIO_ID == PIOC_ID
00382 #define SPPI0_CS1_PE_REG        PIOC_PER
00383 #define SPPI0_CS1_OE_REG        PIOC_OER
00384 #define SPPI0_CS1_COD_REG       PIOC_CODR
00385 #define SPPI0_CS1_SOD_REG       PIOC_SODR
00386 #endif
00387 
00389 #define SPPI0_CS1_ENA() \
00390     outr(SPPI0_CS1_PE_REG, _BV(SPPI0_CS1_BIT)); \
00391     outr(SPPI0_CS1_OE_REG, _BV(SPPI0_CS1_BIT))
00392 
00393 #define SPPI0_CS1_CLR()   outr(SPPI0_CS1_COD_REG, _BV(SPPI0_CS1_BIT))
00394 
00395 #define SPPI0_CS1_SET()   outr(SPPI0_CS1_SOD_REG, _BV(SPPI0_CS1_BIT))
00396 
00397 #endif                          /* SPPI0_CS1_BIT */
00398 
00399 #ifdef SPPI0_CS2_BIT
00400 
00401 #if !defined(SPPI0_CS2_PIO_ID)
00402 #define SPPI0_CS2_PE_REG        PIO_PER
00403 #define SPPI0_CS2_OE_REG        PIO_OER
00404 #define SPPI0_CS2_COD_REG       PIO_CODR
00405 #define SPPI0_CS2_SOD_REG       PIO_SODR
00406 #elif SPPI0_CS2_PIO_ID == PIO_ID
00407 #define SPPI0_CS2_PE_REG        PIO_PER
00408 #define SPPI0_CS2_OE_REG        PIO_OER
00409 #define SPPI0_CS2_COD_REG       PIO_CODR
00410 #define SPPI0_CS2_SOD_REG       PIO_SODR
00411 #elif SPPI0_CS2_PIO_ID == PIOA_ID
00412 #define SPPI0_CS2_PE_REG        PIOA_PER
00413 #define SPPI0_CS2_OE_REG        PIOA_OER
00414 #define SPPI0_CS2_COD_REG       PIOA_CODR
00415 #define SPPI0_CS2_SOD_REG       PIOA_SODR
00416 #elif SPPI0_CS2_PIO_ID == PIOB_ID
00417 #define SPPI0_CS2_PE_REG        PIOB_PER
00418 #define SPPI0_CS2_OE_REG        PIOB_OER
00419 #define SPPI0_CS2_COD_REG       PIOB_CODR
00420 #define SPPI0_CS2_SOD_REG       PIOB_SODR
00421 #elif SPPI0_CS2_PIO_ID == PIOC_ID
00422 #define SPPI0_CS2_PE_REG        PIOC_PER
00423 #define SPPI0_CS2_OE_REG        PIOC_OER
00424 #define SPPI0_CS2_COD_REG       PIOC_CODR
00425 #define SPPI0_CS2_SOD_REG       PIOC_SODR
00426 #endif
00427 
00429 #define SPPI0_CS2_ENA() \
00430     outr(SPPI0_CS2_PE_REG, _BV(SPPI0_CS2_BIT)); \
00431     outr(SPPI0_CS2_OE_REG, _BV(SPPI0_CS2_BIT))
00432 
00433 #define SPPI0_CS2_CLR()   outr(SPPI0_CS2_COD_REG, _BV(SPPI0_CS2_BIT))
00434 
00435 #define SPPI0_CS2_SET()   outr(SPPI0_CS2_SOD_REG, _BV(SPPI0_CS2_BIT))
00436 
00437 #endif                          /* SPPI0_CS2_BIT */
00438 
00439 #ifdef SPPI0_CS3_BIT
00440 
00441 #if !defined(SPPI0_CS3_PIO_ID)
00442 #define SPPI0_CS3_PE_REG        PIO_PER
00443 #define SPPI0_CS3_OE_REG        PIO_OER
00444 #define SPPI0_CS3_COD_REG       PIO_CODR
00445 #define SPPI0_CS3_SOD_REG       PIO_SODR
00446 #elif SPPI0_CS3_PIO_ID == PIO_ID
00447 #define SPPI0_CS3_PE_REG        PIO_PER
00448 #define SPPI0_CS3_OE_REG        PIO_OER
00449 #define SPPI0_CS3_COD_REG       PIO_CODR
00450 #define SPPI0_CS3_SOD_REG       PIO_SODR
00451 #elif SPPI0_CS3_PIO_ID == PIOA_ID
00452 #define SPPI0_CS3_PE_REG        PIOA_PER
00453 #define SPPI0_CS3_OE_REG        PIOA_OER
00454 #define SPPI0_CS3_COD_REG       PIOA_CODR
00455 #define SPPI0_CS3_SOD_REG       PIOA_SODR
00456 #elif SPPI0_CS3_PIO_ID == PIOB_ID
00457 #define SPPI0_CS3_PE_REG        PIOB_PER
00458 #define SPPI0_CS3_OE_REG        PIOB_OER
00459 #define SPPI0_CS3_COD_REG       PIOB_CODR
00460 #define SPPI0_CS3_SOD_REG       PIOB_SODR
00461 #elif SPPI0_CS3_PIO_ID == PIOC_ID
00462 #define SPPI0_CS3_PE_REG        PIOC_PER
00463 #define SPPI0_CS3_OE_REG        PIOC_OER
00464 #define SPPI0_CS3_COD_REG       PIOC_CODR
00465 #define SPPI0_CS3_SOD_REG       PIOC_SODR
00466 #endif
00467 
00469 #define SPPI0_CS3_ENA() \
00470     outr(SPPI0_CS3_PE_REG, _BV(SPPI0_CS3_BIT)); \
00471     outr(SPPI0_CS3_OE_REG, _BV(SPPI0_CS3_BIT))
00472 
00473 #define SPPI0_CS3_CLR()   outr(SPPI0_CS3_COD_REG, _BV(SPPI0_CS3_BIT))
00474 
00475 #define SPPI0_CS3_SET()   outr(SPPI0_CS3_SOD_REG, _BV(SPPI0_CS3_BIT))
00476 
00477 #endif                          /* SPPI0_CS3_BIT */
00478 
00479 #ifdef SPPI0_RST0_BIT
00480 
00481 #if !defined(SPPI0_RST0_PIO_ID)
00482 #define SPPI0_RST0_PE_REG      PIO_PER
00483 #define SPPI0_RST0_OE_REG      PIO_OER
00484 #define SPPI0_RST0_COD_REG     PIO_CODR
00485 #define SPPI0_RST0_SOD_REG     PIO_SODR
00486 #elif SPPI0_RST0_PIO_ID == PIO_ID
00487 #define SPPI0_RST0_PE_REG      PIO_PER
00488 #define SPPI0_RST0_OE_REG      PIO_OER
00489 #define SPPI0_RST0_COD_REG     PIO_CODR
00490 #define SPPI0_RST0_SOD_REG     PIO_SODR
00491 #elif SPPI0_RST0_PIO_ID == PIOA_ID
00492 #define SPPI0_RST0_PE_REG      PIOA_PER
00493 #define SPPI0_RST0_OE_REG      PIOA_OER
00494 #define SPPI0_RST0_COD_REG     PIOA_CODR
00495 #define SPPI0_RST0_SOD_REG     PIOA_SODR
00496 #elif SPPI0_RST0_PIO_ID == PIOB_ID
00497 #define SPPI0_RST0_PE_REG      PIOB_PER
00498 #define SPPI0_RST0_OE_REG      PIOB_OER
00499 #define SPPI0_RST0_COD_REG     PIOB_CODR
00500 #define SPPI0_RST0_SOD_REG     PIOB_SODR
00501 #elif SPPI0_RST0_PIO_ID == PIOC_ID
00502 #define SPPI0_RST0_PE_REG      PIOC_PER
00503 #define SPPI0_RST0_OE_REG      PIOC_OER
00504 #define SPPI0_RST0_COD_REG     PIOC_CODR
00505 #define SPPI0_RST0_SOD_REG     PIOC_SODR
00506 #endif
00507 
00509 #define SPPI0_RST0_ENA() \
00510     outr(SPPI0_RST0_PE_REG, _BV(SPPI0_RST0_BIT)); \
00511     outr(SPPI0_RST0_OE_REG, _BV(SPPI0_RST0_BIT))
00512 
00513 #define SPPI0_RST0_CLR()   outr(SPPI0_RST0_COD_REG, _BV(SPPI0_RST0_BIT))
00514 
00515 #define SPPI0_RST0_SET()   outr(SPPI0_RST0_SOD_REG, _BV(SPPI0_RST0_BIT))
00516 
00517 #endif                          /* SPPI0_RST0_BIT */
00518 
00519 #ifdef SPPI0_RST1_BIT
00520 
00521 #if !defined(SPPI0_RST1_PIO_ID)
00522 #define SPPI0_RST1_PE_REG      PIO_PER
00523 #define SPPI0_RST1_OE_REG      PIO_OER
00524 #define SPPI0_RST1_COD_REG     PIO_CODR
00525 #define SPPI0_RST1_SOD_REG     PIO_SODR
00526 #elif SPPI0_RST1_PIO_ID == PIO_ID
00527 #define SPPI0_RST1_PE_REG      PIO_PER
00528 #define SPPI0_RST1_OE_REG      PIO_OER
00529 #define SPPI0_RST1_COD_REG     PIO_CODR
00530 #define SPPI0_RST1_SOD_REG     PIO_SODR
00531 #elif SPPI0_RST1_PIO_ID == PIOA_ID
00532 #define SPPI0_RST1_PE_REG      PIOA_PER
00533 #define SPPI0_RST1_OE_REG      PIOA_OER
00534 #define SPPI0_RST1_COD_REG     PIOA_CODR
00535 #define SPPI0_RST1_SOD_REG     PIOA_SODR
00536 #elif SPPI0_RST1_PIO_ID == PIOB_ID
00537 #define SPPI0_RST1_PE_REG      PIOB_PER
00538 #define SPPI0_RST1_OE_REG      PIOB_OER
00539 #define SPPI0_RST1_COD_REG     PIOB_CODR
00540 #define SPPI0_RST1_SOD_REG     PIOB_SODR
00541 #elif SPPI0_RST1_PIO_ID == PIOC_ID
00542 #define SPPI0_RST1_PE_REG      PIOC_PER
00543 #define SPPI0_RST1_OE_REG      PIOC_OER
00544 #define SPPI0_RST1_COD_REG     PIOC_CODR
00545 #define SPPI0_RST1_SOD_REG     PIOC_SODR
00546 #endif
00547 
00549 #define SPPI0_RST1_ENA() \
00550     outr(SPPI0_RST1_PE_REG, _BV(SPPI0_RST1_BIT)); \
00551     outr(SPPI0_RST1_OE_REG, _BV(SPPI0_RST1_BIT))
00552 
00553 #define SPPI0_RST1_CLR()   outr(SPPI0_RST1_COD_REG, _BV(SPPI0_RST1_BIT))
00554 
00555 #define SPPI0_RST1_SET()   outr(SPPI0_RST1_SOD_REG, _BV(SPPI0_RST1_BIT))
00556 
00557 #endif                          /* SPPI0_RST1_BIT */
00558 
00559 #ifdef SPPI0_RST2_BIT
00560 
00561 #if !defined(SPPI0_RST2_PIO_ID)
00562 #define SPPI0_RST2_PE_REG      PIO_PER
00563 #define SPPI0_RST2_OE_REG      PIO_OER
00564 #define SPPI0_RST2_COD_REG     PIO_CODR
00565 #define SPPI0_RST2_SOD_REG     PIO_SODR
00566 #elif SPPI0_RST2_PIO_ID == PIO_ID
00567 #define SPPI0_RST2_PE_REG      PIO_PER
00568 #define SPPI0_RST2_OE_REG      PIO_OER
00569 #define SPPI0_RST2_COD_REG     PIO_CODR
00570 #define SPPI0_RST2_SOD_REG     PIO_SODR
00571 #elif SPPI0_RST2_PIO_ID == PIOA_ID
00572 #define SPPI0_RST2_PE_REG      PIOA_PER
00573 #define SPPI0_RST2_OE_REG      PIOA_OER
00574 #define SPPI0_RST2_COD_REG     PIOA_CODR
00575 #define SPPI0_RST2_SOD_REG     PIOA_SODR
00576 #elif SPPI0_RST2_PIO_ID == PIOB_ID
00577 #define SPPI0_RST2_PE_REG      PIOB_PER
00578 #define SPPI0_RST2_OE_REG      PIOB_OER
00579 #define SPPI0_RST2_COD_REG     PIOB_CODR
00580 #define SPPI0_RST2_SOD_REG     PIOB_SODR
00581 #elif SPPI0_RST2_PIO_ID == PIOC_ID
00582 #define SPPI0_RST2_PE_REG      PIOC_PER
00583 #define SPPI0_RST2_OE_REG      PIOC_OER
00584 #define SPPI0_RST2_COD_REG     PIOC_CODR
00585 #define SPPI0_RST2_SOD_REG     PIOC_SODR
00586 #endif
00587 
00589 #define SPPI0_RST2_ENA() \
00590     outr(SPPI0_RST2_PE_REG, _BV(SPPI0_RST2_BIT)); \
00591     outr(SPPI0_RST2_OE_REG, _BV(SPPI0_RST2_BIT))
00592 
00593 #define SPPI0_RST2_CLR()   outr(SPPI0_RST2_COD_REG, _BV(SPPI0_RST2_BIT))
00594 
00595 #define SPPI0_RST2_SET()   outr(SPPI0_RST2_SOD_REG, _BV(SPPI0_RST2_BIT))
00596 
00597 #endif                          /* SPPI0_RST2_BIT */
00598 
00599 #ifdef SPPI0_RST3_BIT
00600 
00601 #if !defined(SPPI0_RST3_PIO_ID)
00602 #define SPPI0_RST3_PE_REG      PIO_PER
00603 #define SPPI0_RST3_OE_REG      PIO_OER
00604 #define SPPI0_RST3_COD_REG     PIO_CODR
00605 #define SPPI0_RST3_SOD_REG     PIO_SODR
00606 #elif SPPI0_RST3_PIO_ID == PIO_ID
00607 #define SPPI0_RST3_PE_REG      PIO_PER
00608 #define SPPI0_RST3_OE_REG      PIO_OER
00609 #define SPPI0_RST3_COD_REG     PIO_CODR
00610 #define SPPI0_RST3_SOD_REG     PIO_SODR
00611 #elif SPPI0_RST3_PIO_ID == PIOA_ID
00612 #define SPPI0_RST3_PE_REG      PIOA_PER
00613 #define SPPI0_RST3_OE_REG      PIOA_OER
00614 #define SPPI0_RST3_COD_REG     PIOA_CODR
00615 #define SPPI0_RST3_SOD_REG     PIOA_SODR
00616 #elif SPPI0_RST3_PIO_ID == PIOB_ID
00617 #define SPPI0_RST3_PE_REG      PIOB_PER
00618 #define SPPI0_RST3_OE_REG      PIOB_OER
00619 #define SPPI0_RST3_COD_REG     PIOB_CODR
00620 #define SPPI0_RST3_SOD_REG     PIOB_SODR
00621 #elif SPPI0_RST3_PIO_ID == PIOC_ID
00622 #define SPPI0_RST3_PE_REG      PIOC_PER
00623 #define SPPI0_RST3_OE_REG      PIOC_OER
00624 #define SPPI0_RST3_COD_REG     PIOC_CODR
00625 #define SPPI0_RST3_SOD_REG     PIOC_SODR
00626 #endif
00627 
00629 #define SPPI0_RST3_ENA() \
00630     outr(SPPI0_RST3_PE_REG, _BV(SPPI0_RST3_BIT)); \
00631     outr(SPPI0_RST3_OE_REG, _BV(SPPI0_RST3_BIT))
00632 
00633 #define SPPI0_RST3_CLR()   outr(SPPI0_RST3_COD_REG, _BV(SPPI0_RST3_BIT))
00634 
00635 #define SPPI0_RST3_SET()   outr(SPPI0_RST3_SOD_REG, _BV(SPPI0_RST3_BIT))
00636 
00637 #endif                          /* SPPI0_RST3_BIT */
00638 
00639 #endif                          /* MCU */
00640 
00641 __BEGIN_DECLS
00642 /* Function prototypes */
00643 
00644 extern int Sppi0SetMode(ureg_t ix, ureg_t mode);
00645 extern void Sppi0SetSpeed(ureg_t ix, u_long rate);
00646 extern void Sppi0Enable(ureg_t ix);
00647 extern void Sppi0ChipReset(ureg_t ix, u_char hi);
00648 extern void Sppi0ChipSelect(ureg_t ix, u_char hi);
00649 extern void Sppi0SelectDevice(ureg_t ix);
00650 extern void Sppi0DeselectDevice(ureg_t ix);
00651 extern void Sppi0NegSelectDevice(ureg_t ix);
00652 extern void Sppi0NegDeselectDevice(ureg_t ix);
00653 extern u_char Sppi0Byte(u_char data);
00654 extern void Sppi0Transact(CONST void *wdata, void *rdata, size_t len);
00655 
00656 __END_DECLS
00657 /* End of prototypes */
00658 
00659 #endif

© 2000-2007 by egnite Software GmbH - visit http://www.ethernut.de/