at91_adc.h

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00001 /*
00002  * Copyright (C) 2004 by Ole Reinhardt <ole.reinhardt@embedded-it.de>,
00003  *                       Kernelconcepts http://www.embedded-it.de
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00022  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00023  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00024  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00025  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00026  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00027  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00028  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00029  * SUCH DAMAGE.
00030  *
00031  * For additional information see http://www.ethernut.de/
00032  *
00033  */
00034 
00035 /*
00036  * $Log: at91_adc.h,v $
00037  * Revision 1.2  2007/12/09 22:12:49  olereinhardt
00038  * Added cvs log tag
00039  *
00040  */
00041 
00042 #ifndef _ARCH_ARM_AT91_ADC_H_
00043 #define _ARCH_ARM_AT91_ADC_H_
00044 
00066 
00069 #define ADC_CR_OFF              0x00000000      
00070 #define ADC_CR      (ADC_BASE + ADC_CR_OFF)     
00071 #define ADC_SWRST               0x00000001      
00072 #define ADC_START               0x00000002      
00074 
00075 
00077 #define ADC_MR_OFF              0x00000004      
00078 #define ADC_MR      (ADC_BASE + ADC_MR_OFF)     
00079 #define ADC_TRGEN               0x00000001      
00080 #define ADC_START               0x00000002      
00081 #define ADC_TRGSEL              0x0000000E      
00082 #define   ADC_TRGSEL_TIOA0      0x00000000      
00083 #define   ADC_TRGSEL_TIOA1      0x00000002      
00084 #define   ADC_TRGSEL_TIOA2      0x00000004      
00085 #define   ADC_TRGSEL_EXT        0x0000000C      
00086 #define ADC_LOWRES              0x00000010      
00087 #define ADC_SLEEP               0x00000020      
00088 #define ADC_PRESCAL             0x00003F00      
00089 #define ADC_PRESCAL_LSB         8               
00090 #define ADC_STARTUP             0x001F0000      
00091 #define ADC_STARTUP_LSB         16              
00092 #define ADC_SHTIM               0x0F000000      
00093 #define ADC_SHTIM_LSB           24              
00095 
00096 
00098 #define ADC_CHER_OFF            0x00000010      
00099 #define ADC_CHER    (ADC_BASE + ADC_CHER_OFF)   
00101 #define ADC_CH(x) ((unsigned long)BV(x))        
00102 #define ADC_CH0                 0x00000001      
00103 #define ADC_CH1                 0x00000002      
00104 #define ADC_CH2                 0x00000004      
00105 #define ADC_CH3                 0x00000008      
00106 #define ADC_CH4                 0x00000010      
00107 #define ADC_CH5                 0x00000020      
00108 #define ADC_CH6                 0x00000040      
00109 #define ADC_CH7                 0x00000080      
00111 
00112 
00114 #define ADC_CHDR_OFF            0x00000014      
00115 #define ADC_CHDR    (ADC_BASE + ADC_CHDR_OFF)   
00117 
00118 
00120 #define ADC_CHSR_OFF            0x00000018      
00121 #define ADC_CHSR    (ADC_BASE + ADC_CHSR_OFF)   
00123 
00124 
00126 #define ADC_SR_OFF              0x0000001C      
00127 #define ADC_SR      (ADC_BASE + ADC_SR_OFF)     
00129 #define ADC_EOC(x)((unsigned long)BV(x))        
00131 #define ADC_EOC0                0x00000001      
00132 #define ADC_EOC1                0x00000002      
00133 #define ADC_EOC2                0x00000004      
00134 #define ADC_EOC3                0x00000008      
00135 #define ADC_EOC4                0x00000010      
00136 #define ADC_EOC5                0x00000020      
00137 #define ADC_EOC6                0x00000040      
00138 #define ADC_EOC7                0x00000080      
00140 #define ADC_OVRE(x)((unsigned long)BV(x+8))     
00141 #define ADC_OVRE0               0x00000100      
00142 #define ADC_OVRE1               0x00000200      
00143 #define ADC_OVRE2               0x00000400      
00144 #define ADC_OVRE3               0x00000800      
00145 #define ADC_OVRE4               0x00001000      
00146 #define ADC_OVRE5               0x00002000      
00147 #define ADC_OVRE6               0x00004000      
00148 #define ADC_OVRE7               0x00008000      
00150 #define ADC_DRDY                0x00010000      
00151 #define ADC_GOVRE               0x00020000      
00152 #define ADC_ENDRX               0x00040000      
00153 #define ADC_RXBUF               0x00080000      
00155 
00156 
00158 #define ADC_LCDR_OFF            0x00000020      
00159 #define ADC_LCDR    (ADC_BASE + ADC_LCDR_OFF)   
00161 #define ADC_LCDR_MASK           0x000003FF      
00163 
00164 
00166 #define ADC_IER_OFF             0x00000024      
00167 #define ADC_IER     (ADC_BASE + ADC_IER_OFF)    
00169 
00170 
00172 #define ADC_IDR_OFF             0x00000028      
00173 #define ADC_IDR     (ADC_BASE + ADC_IDR_OFF)    
00175 
00176 
00178 #define ADC_IMR_OFF             0x0000002C      
00179 #define ADC_IMR     (ADC_BASE + ADC_IMR_OFF)    
00181 
00182 
00184 #define ADC_CDR_OFF             0x00000030      
00185 #define ADC_CDR(x) (ADC_BASE + ADC_CDR_OFF + ((x) << 2))    
00187 #define ADC_CDR_MASK           0x000003FF       
00189 
00190 
00191 
00192 #endif

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