ih_at91tc0.c

Go to the documentation of this file.
00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91tc0.c,v $
00036  * Revision 1.4  2008/07/26 09:43:01  haraldkipp
00037  * Added support for retrieving and setting the interrupt mode.
00038  *
00039  * Revision 1.3  2006/09/29 12:36:48  haraldkipp
00040  * Default interrupt priority changed from 4 to 0. As this is typically used
00041  * by the system timer, lowest priority is fine.
00042  *
00043  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00044  * Include more general header file for ARM.
00045  *
00046  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00047  * First check in.
00048  *
00049  */
00050 
00051 #include <arch/arm.h>
00052 #include <dev/irqreg.h>
00053 
00054 #ifndef NUT_IRQPRI_TC0
00055 #define NUT_IRQPRI_TC0  0
00056 #endif
00057 
00058 static int TimerCounter0IrqCtl(int cmd, void *param);
00059 
00060 IRQ_HANDLER sig_TC0 = {
00061 #ifdef NUT_PERFMON
00062     0,                  /* Interrupt counter, ir_count. */
00063 #endif
00064     NULL,               /* Passed argument, ir_arg. */
00065     NULL,               /* Handler subroutine, ir_handler. */
00066     TimerCounter0IrqCtl /* Interrupt control, ir_ctl. */
00067 };
00068 
00072 static u_int dummy;
00073 static void TimerCounter0IrqEntry(void) __attribute__ ((naked));
00074 void TimerCounter0IrqEntry(void)
00075 {
00076     IRQ_ENTRY();
00077 #ifdef NUT_PERFMON
00078     sig_TC0.ir_count++;
00079 #endif
00080     dummy = inr(TC0_SR);
00081     if (sig_TC0.ir_handler) {
00082         (sig_TC0.ir_handler) (sig_TC0.ir_arg);
00083     }
00084     IRQ_EXIT();
00085 }
00086 
00104 static int TimerCounter0IrqCtl(int cmd, void *param)
00105 {
00106     int rc = 0;
00107     u_int *ival = (u_int *)param;
00108     int enabled = inr(AIC_IMR) & _BV(TC0_ID);
00109 
00110     /* Disable interrupt. */
00111     if (enabled) {
00112         outr(AIC_IDCR, _BV(TC0_ID));
00113     }
00114 
00115     switch(cmd) {
00116     case NUT_IRQCTL_INIT:
00117         /* Set the vector. */
00118         outr(AIC_SVR(TC0_ID), (unsigned int)TimerCounter0IrqEntry);
00119         /* Initialize to edge triggered with defined priority. */
00120         outr(AIC_SMR(TC0_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC0);
00121         /* Clear interrupt */
00122         outr(AIC_ICCR, _BV(TC0_ID));
00123         break;
00124     case NUT_IRQCTL_STATUS:
00125         if (enabled) {
00126             *ival |= 1;
00127         }
00128         else {
00129             *ival &= ~1;
00130         }
00131         break;
00132     case NUT_IRQCTL_ENABLE:
00133         enabled = 1;
00134         break;
00135     case NUT_IRQCTL_DISABLE:
00136         enabled = 0;
00137         break;
00138     case NUT_IRQCTL_GETMODE:
00139         {
00140             u_int val = inr(AIC_SMR(TC0_ID)) & AIC_SRCTYPE;
00141             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00142                 *ival = NUT_IRQMODE_LEVEL;
00143             } else  {
00144                 *ival = NUT_IRQMODE_EDGE;
00145             }
00146         }
00147         break;
00148     case NUT_IRQCTL_SETMODE:
00149         if (*ival == NUT_IRQMODE_LEVEL) {
00150             outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00151         } else if (*ival == NUT_IRQMODE_EDGE) {
00152             outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00153         } else  {
00154             rc = -1;
00155         }
00156         break;
00157     case NUT_IRQCTL_GETPRIO:
00158         *ival = inr(AIC_SMR(TC0_ID)) & AIC_PRIOR;
00159         break;
00160     case NUT_IRQCTL_SETPRIO:
00161         outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_PRIOR) | *ival);
00162         break;
00163 #ifdef NUT_PERFMON
00164     case NUT_IRQCTL_GETCOUNT:
00165         *ival = (u_int)sig_TC0.ir_count;
00166         sig_TC0.ir_count = 0;
00167         break;
00168 #endif
00169     default:
00170         rc = -1;
00171         break;
00172     }
00173 
00174     /* Enable interrupt. */
00175     if (enabled) {
00176         outr(AIC_IECR, _BV(TC0_ID));
00177     }
00178     return rc;
00179 }

© 2000-2007 by egnite Software GmbH - visit http://www.ethernut.de/