00001 /* 00002 * Copyright (C) 2001-2007 by egnite Software GmbH. All rights reserved. 00003 * 00004 * Redistribution and use in source and binary forms, with or without 00005 * modification, are permitted provided that the following conditions 00006 * are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright 00009 * notice, this list of conditions and the following disclaimer. 00010 * 2. Redistributions in binary form must reproduce the above copyright 00011 * notice, this list of conditions and the following disclaimer in the 00012 * documentation and/or other materials provided with the distribution. 00013 * 3. Neither the name of the copyright holders nor the names of 00014 * contributors may be used to endorse or promote products derived 00015 * from this software without specific prior written permission. 00016 * 00017 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00018 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00019 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00020 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00021 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00022 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00023 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00024 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00025 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00026 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00027 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00028 * SUCH DAMAGE. 00029 * 00030 * For additional information see http://www.ethernut.de/ 00031 * 00032 */ 00033 00034 /* 00035 * $Log: ostimer_at91.c,v $ 00036 * Revision 1.19 2008/07/08 08:25:04 haraldkipp 00037 * NutDelay is no more architecture specific. 00038 * Number of loops per millisecond is configurable or will be automatically 00039 * determined. 00040 * A new function NutMicroDelay provides shorter delays. 00041 * 00042 * Revision 1.18 2008/02/15 16:58:41 haraldkipp 00043 * Spport for AT91SAM7SE512 added. 00044 * 00045 * Revision 1.17 2007/10/04 19:59:47 olereinhardt 00046 * Support for SAM7S256 added 00047 * 00048 * Revision 1.16 2007/08/17 10:44:37 haraldkipp 00049 * Timer enable/disable macro replaces previous global interrupt 00050 * enable/disable or function calling. 00051 * 00052 * Revision 1.15 2007/04/12 09:03:48 haraldkipp 00053 * Miserable delay routine will now honor milliseconds on a 73 MHz ARM. 00054 * 00055 * Revision 1.14 2007/02/15 16:14:39 haraldkipp 00056 * Periodic interrupt timer can be used as a system clock. 00057 * 00058 * Revision 1.13 2006/10/08 16:48:07 haraldkipp 00059 * Documentation fixed 00060 * 00061 * Revision 1.12 2006/09/29 12:37:36 haraldkipp 00062 * Now working correctly, if the CPU is running on the second PLL. 00063 * 00064 * Revision 1.11 2006/09/05 12:27:25 haraldkipp 00065 * PLL clock calculation re-arranged to prevent 32-bit overflow. 00066 * NutTimerMillisToTicks() returned wrong result. Shane Buckham reported 00067 * this long time ago. Many thanks. Needs to be fixed for other platforms too. 00068 * 00069 * Revision 1.10 2006/08/31 18:59:50 haraldkipp 00070 * Added support for the AT91SAM9260. We now determine between processor and 00071 * master clock. A new API function At91GetMasterClock() had been added to 00072 * query the latter. 00073 * 00074 * Revision 1.9 2006/08/05 12:00:01 haraldkipp 00075 * NUT_CPU_FREQ did not override AT91_PLL_MAINCK or NUT_PLL_CPUCLK. Fixed. 00076 * 00077 * Revision 1.8 2006/07/26 11:17:16 haraldkipp 00078 * Defining AT91_PLL_MAINCK will automatically determine SAM7X clock by 00079 * reading PLL settings. 00080 * 00081 * Revision 1.7 2006/07/05 07:59:41 haraldkipp 00082 * Daidai's support for AT91SAM7X added. 00083 * 00084 * Revision 1.6 2006/06/28 17:10:35 haraldkipp 00085 * Include more general header file for ARM. 00086 * 00087 * Revision 1.5 2006/03/02 19:53:01 haraldkipp 00088 * Bugfix. The system timer configuration was based on a fixed MCU clock 00089 * of 66.6 MHz. Now it uses the actual frequency. 00090 * 00091 * Revision 1.4 2006/01/05 16:46:25 haraldkipp 00092 * Added support for CY22393 programmable clock chip. 00093 * 00094 * Revision 1.3 2005/10/24 08:34:13 haraldkipp 00095 * Moved AT91 family specific header files to sbudir arm. 00096 * Use new IRQ API. 00097 * 00098 * Revision 1.2 2005/08/02 17:46:45 haraldkipp 00099 * Major API documentation update. 00100 * 00101 * Revision 1.1 2005/07/26 18:02:26 haraldkipp 00102 * Moved from dev. 00103 * 00104 * Revision 1.2 2005/07/20 09:17:26 haraldkipp 00105 * Default NUT_CPU_FREQ and NUT_TICK_FREQ added. 00106 * NutTimerIntr() removed, because we can use the hardware independent code. 00107 * 00108 * Revision 1.1 2005/05/27 17:16:40 drsung 00109 * Moved the file. 00110 * 00111 * Revision 1.5 2005/04/05 17:50:46 haraldkipp 00112 * Use register names in gba.h. 00113 * 00114 * Revision 1.4 2004/11/08 19:16:37 haraldkipp 00115 * Hacked in Gameboy timer support 00116 * 00117 * Revision 1.3 2004/10/03 18:42:21 haraldkipp 00118 * No GBA support yet, but let the compiler run through 00119 * 00120 * Revision 1.2 2004/09/08 10:19:39 haraldkipp 00121 * Running on AT91 and S3C, thanks to James Tyou 00122 * 00123 */ 00124 00125 #include <cfg/os.h> 00126 #include <cfg/clock.h> 00127 #include <arch/arm.h> 00128 #include <dev/irqreg.h> 00129 #include <sys/timer.h> 00130 00131 #ifndef NUT_CPU_FREQ 00132 #ifdef NUT_PLL_CPUCLK 00133 #include <dev/cy2239x.h> 00134 #elif !defined(AT91_PLL_MAINCK) 00135 #define NUT_CPU_FREQ 73728000UL 00136 #endif /* !AT91_PLL_MAINCK */ 00137 #endif /* !NUT_CPU_FREQ */ 00138 00139 00144 00145 #ifndef NUT_TICK_FREQ 00146 #define NUT_TICK_FREQ 1000UL 00147 #endif 00148 00160 void NutRegisterTimer(void (*handler) (void *)) 00161 { 00162 #if defined(NUT_TICK_AT91PIT) 00163 00164 /* Set compare value for the specified tick frequency. */ 00165 #if defined(AT91_PLL_MAINCK) 00166 outr(PIT_MR, (At91GetMasterClock() / (16 * NUT_TICK_FREQ) - 1) << PIT_PIV_LSB); 00167 #else 00168 outr(PIT_MR, (NutGetCpuClock() / (16 * NUT_TICK_FREQ) - 1) << PIT_PIV_LSB); 00169 #endif 00170 00171 /* Register system interrupt handler. */ 00172 NutRegisterSysIrqHandler(&syssig_PIT, handler, NULL); 00173 /* Enable interval timer and interval timer interrupts */ 00174 outr(PIT_MR, inr(PIT_MR) | PIT_PITEN | PIT_PITIEN); 00175 NutSysIrqEnable(&syssig_PIT); 00176 inr(PIT_PIVR); 00177 00178 #else /* NUT_TICK_AT91PIT */ 00179 00180 int dummy; 00181 00182 #if defined(MCU_AT91SAM7X256) || defined(MCU_AT91SAM7S256) || defined(MCU_AT91SAM9260) || defined (MCU_AT91SAM7SE512) 00183 /* Enable TC0 clock. */ 00184 outr(PMC_PCER, _BV(TC0_ID)); 00185 #endif 00186 00187 /* Disable the Clock Counter */ 00188 outr(TC0_CCR, TC_CLKDIS); 00189 /* Disable all interrupts */ 00190 outr(TC0_IDR, 0xFFFFFFFF); 00191 /* Clear the status register. */ 00192 dummy = inr(TC0_SR); 00193 /* Select divider and compare trigger */ 00194 outr(TC0_CMR, TC_CLKS_MCK32 | TC_CPCTRG); 00195 /* Enable the Clock counter */ 00196 outr(TC0_CCR, TC_CLKEN); 00197 /* Validate the RC compare interrupt */ 00198 outr(TC0_IER, TC_CPCS); 00199 00200 /* Register timer interrupt handler. */ 00201 NutRegisterIrqHandler(&sig_TC0, handler, 0); 00202 /* Set to lowest priority. */ 00203 NutIrqSetPriority(&sig_TC0, 0); 00204 00205 /* Enable timer 0 interrupts */ 00206 NutIrqEnable(&sig_TC0); 00207 //outr(AIC_IECR, _BV(TC0_ID)); 00208 00209 /* Set compare value for 1 ms. */ 00210 #if defined(AT91_PLL_MAINCK) 00211 outr(TC0_RC, At91GetMasterClock() / (32 * NUT_TICK_FREQ)); 00212 #else 00213 outr(TC0_RC, NutGetCpuClock() / (32 * NUT_TICK_FREQ)); 00214 #endif 00215 00216 /* Software trigger starts the clock. */ 00217 outr(TC0_CCR, TC_SWTRG); 00218 00219 #endif /* NUT_TICK_AT91PIT */ 00220 } 00221 00222 #if defined(AT91_PLL_MAINCK) 00223 00224 #if !defined(AT91_SLOW_CLOCK) 00225 /* This is just a guess and may be completely wrong. */ 00226 #define AT91_SLOW_CLOCK 32000 00227 #endif 00228 00236 static u_int At91GetPllClock(int plla) 00237 { 00238 u_int rc; 00239 u_int pllr; 00240 u_int divider; 00241 00242 /* 00243 * The main oscillator clock frequency is specified by the 00244 * configuration. It's usually equal to the on-board crystal. 00245 */ 00246 rc = AT91_PLL_MAINCK; 00247 00248 /* Retrieve the clock generator register of the selected PLL. */ 00249 #if defined(CKGR_PLLAR) && defined(CKGR_PLLBR) 00250 pllr = plla ? inr(CKGR_PLLAR) : inr(CKGR_PLLBR); 00251 #else 00252 pllr = inr(CKGR_PLLR); 00253 #endif 00254 00255 /* Extract the divider value. */ 00256 divider = (pllr & CKGR_DIV) >> CKGR_DIV_LSB; 00257 00258 if (divider) { 00259 rc /= divider; 00260 rc *= ((pllr & CKGR_MUL) >> CKGR_MUL_LSB) + 1; 00261 } 00262 return rc; 00263 } 00264 00270 static u_long At91GetProcessorClock(void) 00271 { 00272 u_int rc = 0; 00273 u_int mckr = inr(PMC_MCKR); 00274 00275 /* Determine the clock source. */ 00276 switch(mckr & PMC_CSS) { 00277 case PMC_CSS_SLOW_CLK: 00278 /* Slow clock selected. */ 00279 rc = AT91_SLOW_CLOCK; 00280 break; 00281 case PMC_CSS_MAIN_CLK: 00282 /* Main clock selected. */ 00283 rc = AT91_PLL_MAINCK; 00284 break; 00285 #if defined(PMC_CSS_PLLA_CLK) 00286 case PMC_CSS_PLLA_CLK: 00287 /* PLL A clock selected. */ 00288 rc = At91GetPllClock(1); 00289 break; 00290 #endif 00291 #if defined(PMC_CSS_PLLB_CLK) 00292 case PMC_CSS_PLLB_CLK: 00293 /* PLL (B) clock selected. */ 00294 rc = At91GetPllClock(0); 00295 break; 00296 #elif defined(PMC_CSS_PLL_CLK) 00297 case PMC_CSS_PLL_CLK: 00298 /* PLL (B) clock selected. */ 00299 rc = At91GetPllClock(0); 00300 break; 00301 #endif 00302 } 00303 00304 /* Handle pre-scaling. */ 00305 mckr &= PMC_PRES; 00306 mckr >>= PMC_PRES_LSB; 00307 if (mckr < 7) { 00308 rc /= _BV(mckr); 00309 } 00310 else { 00311 rc = 0; 00312 } 00313 return rc; 00314 } 00315 00321 u_long At91GetMasterClock(void) 00322 { 00323 u_long rc = At91GetProcessorClock(); 00324 00325 #if defined(MCU_AT91SAM9260) 00326 switch(inr(PMC_MCKR) & PMC_MDIV) { 00327 case PMC_MDIV_2: 00328 rc /= 2; 00329 break; 00330 case PMC_MDIV_4: 00331 rc /= 4; 00332 break; 00333 } 00334 #endif 00335 return rc; 00336 } 00337 00338 #endif /* AT91_PLL_MAINCK */ 00339 00349 u_long NutGetCpuClock(void) 00350 { 00351 #if defined(NUT_CPU_FREQ) 00352 return NUT_CPU_FREQ; 00353 #elif defined(AT91_PLL_MAINCK) 00354 return At91GetProcessorClock(); 00355 #elif defined(NUT_PLL_CPUCLK) 00356 return Cy2239xGetFreq(NUT_PLL_CPUCLK, 7); 00357 #else 00358 #warning "No CPU Clock defined" 00359 return 0; 00360 #endif 00361 } 00362 00368 u_long NutGetTickClock(void) 00369 { 00370 u_int rc; 00371 00372 #if defined(NUT_TICK_AT91PIT) 00373 rc = ((inr(PIT_MR) & PIT_PIV) + 1) * 16; 00374 #else 00375 rc = inr(TC0_RC) * 32; 00376 #endif 00377 00378 if (rc) { 00379 #if defined(AT91_PLL_MAINCK) 00380 return At91GetMasterClock() / rc; 00381 #else 00382 return NutGetCpuClock() / rc; 00383 #endif 00384 } 00385 return NUT_TICK_FREQ; 00386 } 00387 00391 u_long NutTimerMillisToTicks(u_long ms) 00392 { 00393 return (ms * NutGetTickClock()) / 1000; 00394 } 00395