ih_at91tc2.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91tc2.c,v $
00036  * Revision 1.3  2008/07/26 09:43:01  haraldkipp
00037  * Added support for retrieving and setting the interrupt mode.
00038  *
00039  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00040  * Include more general header file for ARM.
00041  *
00042  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00043  * First check in.
00044  *
00045  */
00046 
00047 #include <arch/arm.h>
00048 #include <dev/irqreg.h>
00049 
00050 #ifndef NUT_IRQPRI_TC2
00051 #define NUT_IRQPRI_TC2  4
00052 #endif
00053 
00054 static int TimerCounter2IrqCtl(int cmd, void *param);
00055 
00056 IRQ_HANDLER sig_TC2 = {
00057 #ifdef NUT_PERFMON
00058     0,                  /* Interrupt counter, ir_count. */
00059 #endif
00060     NULL,               /* Passed argument, ir_arg. */
00061     NULL,               /* Handler subroutine, ir_handler. */
00062     TimerCounter2IrqCtl /* Interrupt control, ir_ctl. */
00063 };
00064 
00068 static u_int dummy;
00069 static void TimerCounter2IrqEntry(void) __attribute__ ((naked));
00070 void TimerCounter2IrqEntry(void)
00071 {
00072     IRQ_ENTRY();
00073 #ifdef NUT_PERFMON
00074     sig_TC2.ir_count++;
00075 #endif
00076     dummy = inr(TC2_SR);
00077     if (sig_TC2.ir_handler) {
00078         (sig_TC2.ir_handler) (sig_TC2.ir_arg);
00079     }
00080     IRQ_EXIT();
00081 }
00082 
00100 static int TimerCounter2IrqCtl(int cmd, void *param)
00101 {
00102     int rc = 0;
00103     u_int *ival = (u_int *)param;
00104     int enabled = inr(AIC_IMR) & _BV(TC2_ID);
00105 
00106     /* Disable interrupt. */
00107     if (enabled) {
00108         outr(AIC_IDCR, _BV(TC2_ID));
00109     }
00110 
00111     switch(cmd) {
00112     case NUT_IRQCTL_INIT:
00113         /* Set the vector. */
00114         outr(AIC_SVR(TC2_ID), (unsigned int)TimerCounter2IrqEntry);
00115         /* Initialize to edge triggered with defined priority. */
00116         outr(AIC_SMR(TC2_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC2);
00117         /* Clear interrupt */
00118         outr(AIC_ICCR, _BV(TC2_ID));
00119         break;
00120     case NUT_IRQCTL_STATUS:
00121         if (enabled) {
00122             *ival |= 1;
00123         }
00124         else {
00125             *ival &= ~1;
00126         }
00127         break;
00128     case NUT_IRQCTL_ENABLE:
00129         enabled = 1;
00130         break;
00131     case NUT_IRQCTL_DISABLE:
00132         enabled = 0;
00133         break;
00134     case NUT_IRQCTL_GETMODE:
00135         {
00136             u_int val = inr(AIC_SMR(TC2_ID)) & AIC_SRCTYPE;
00137             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00138                 *ival = NUT_IRQMODE_LEVEL;
00139             } else  {
00140                 *ival = NUT_IRQMODE_EDGE;
00141             }
00142         }
00143         break;
00144     case NUT_IRQCTL_SETMODE:
00145         if (*ival == NUT_IRQMODE_LEVEL) {
00146             outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00147         } else if (*ival == NUT_IRQMODE_EDGE) {
00148             outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00149         } else  {
00150             rc = -1;
00151         }
00152         break;
00153     case NUT_IRQCTL_GETPRIO:
00154         *ival = inr(AIC_SMR(TC2_ID)) & AIC_PRIOR;
00155         break;
00156     case NUT_IRQCTL_SETPRIO:
00157         outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_PRIOR) | *ival);
00158         break;
00159 #ifdef NUT_PERFMON
00160     case NUT_IRQCTL_GETCOUNT:
00161         *ival = (u_int)sig_TC2.ir_count;
00162         sig_TC2.ir_count = 0;
00163         break;
00164 #endif
00165     default:
00166         rc = -1;
00167         break;
00168     }
00169 
00170     /* Enable interrupt. */
00171     if (enabled) {
00172         outr(AIC_IECR, _BV(TC2_ID));
00173     }
00174     return rc;
00175 }

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