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00052 #include <arch/arm.h>
00053 #include <dev/irqreg.h>
00054
00055 #ifndef NUT_IRQPRI_FIQ
00056 #define NUT_IRQPRI_FIQ 4
00057 #endif
00058
00059 static int FastIrqCtl(int cmd, void *param);
00060
00061 IRQ_HANDLER sig_FIQ = {
00062 #ifdef NUT_PERFMON
00063 0,
00064 #endif
00065 NULL,
00066 NULL,
00067 FastIrqCtl
00068 };
00069
00075 static void FastIrqEntry(void) __attribute__ ((naked));
00076 void FastIrqEntry(void)
00077 {
00078 FIQ_ENTRY();
00079 #ifdef NUT_PERFMON
00080 sig_FIQ.ir_count++;
00081 #endif
00082 if (sig_FIQ.ir_handler) {
00083 (sig_FIQ.ir_handler) (sig_FIQ.ir_arg);
00084 }
00085 FIQ_EXIT();
00086 }
00087
00103 static int FastIrqCtl(int cmd, void *param)
00104 {
00105 int rc = 0;
00106 u_int *ival = (u_int *)param;
00107 int enabled = inr(AIC_IMR) & _BV(FIQ_ID);
00108
00109
00110 if (enabled) {
00111 outr(AIC_IDCR, _BV(FIQ_ID));
00112 }
00113
00114 switch(cmd) {
00115 case NUT_IRQCTL_INIT:
00116
00117 outr(AIC_SVR(FIQ_ID), (unsigned int)FastIrqEntry);
00118
00119 outr(AIC_SMR(FIQ_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_FIQ);
00120
00121 outr(AIC_ICCR, _BV(FIQ_ID));
00122 break;
00123 case NUT_IRQCTL_STATUS:
00124 if (enabled) {
00125 *ival |= 1;
00126 }
00127 else {
00128 *ival &= ~1;
00129 }
00130 break;
00131 case NUT_IRQCTL_ENABLE:
00132 enabled = 1;
00133 break;
00134 case NUT_IRQCTL_DISABLE:
00135 enabled = 0;
00136 break;
00137 case NUT_IRQCTL_GETMODE:
00138 {
00139 u_int val = inr(AIC_SMR(FIQ_ID)) & AIC_SRCTYPE;
00140 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00141 *ival = NUT_IRQMODE_LOWLEVEL;
00142 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00143 *ival = NUT_IRQMODE_HIGHLEVEL;
00144 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00145 *ival = NUT_IRQMODE_RISINGEDGE;
00146 } else {
00147 *ival = NUT_IRQMODE_FALLINGEDGE;
00148 }
00149 }
00150 break;
00151 case NUT_IRQCTL_SETMODE:
00152 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00153 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00154 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00155 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00156 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00157 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00158 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00159 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00160 } else {
00161 rc = -1;
00162 }
00163 break;
00164 #ifdef NUT_PERFMON
00165 case NUT_IRQCTL_GETCOUNT:
00166 *ival = (u_int)sig_FIQ.ir_count;
00167 sig_FIQ.ir_count = 0;
00168 break;
00169 #endif
00170 default:
00171 rc = -1;
00172 break;
00173 }
00174
00175
00176 if (enabled) {
00177 outr(AIC_IECR, _BV(FIQ_ID));
00178 }
00179 return rc;
00180 }