ih_at91uart0.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91uart0.c,v $
00036  * Revision 1.3  2008/07/26 09:42:21  haraldkipp
00037  * Use level sensitive interrupts by default.
00038  * Added support for retrieving and setting the interrupt mode.
00039  *
00040  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00041  * Include more general header file for ARM.
00042  *
00043  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00044  * First check in.
00045  *
00046  */
00047 
00048 #include <arch/arm.h>
00049 #include <dev/irqreg.h>
00050 
00051 #ifndef NUT_IRQPRI_UART0
00052 #define NUT_IRQPRI_UART0  4
00053 #endif
00054 
00055 static int Uart0IrqCtl(int cmd, void *param);
00056 
00057 IRQ_HANDLER sig_UART0 = {
00058 #ifdef NUT_PERFMON
00059     0,                  /* Interrupt counter, ir_count. */
00060 #endif
00061     NULL,               /* Passed argument, ir_arg. */
00062     NULL,               /* Handler subroutine, ir_handler. */
00063     Uart0IrqCtl         /* Interrupt control, ir_ctl. */
00064 };
00065 
00069 static void Uart0IrqEntry(void) __attribute__ ((naked));
00070 void Uart0IrqEntry(void)
00071 {
00072     IRQ_ENTRY();
00073 #ifdef NUT_PERFMON
00074     sig_UART0.ir_count++;
00075 #endif
00076     if (sig_UART0.ir_handler) {
00077         (sig_UART0.ir_handler) (sig_UART0.ir_arg);
00078     }
00079     IRQ_EXIT();
00080 }
00081 
00099 static int Uart0IrqCtl(int cmd, void *param)
00100 {
00101     int rc = 0;
00102     u_int *ival = (u_int *)param;
00103     int enabled = inr(AIC_IMR) & _BV(US0_ID);
00104 
00105     /* Disable interrupt. */
00106     if (enabled) {
00107         outr(AIC_IDCR, _BV(US0_ID));
00108     }
00109 
00110     switch(cmd) {
00111     case NUT_IRQCTL_INIT:
00112         /* Set the vector. */
00113         outr(AIC_SVR(US0_ID), (unsigned int)Uart0IrqEntry);
00114         /* Initialize to edge triggered with defined priority. */
00115         outr(AIC_SMR(US0_ID), AIC_SRCTYPE_INT_LEVEL_SENSITIVE | NUT_IRQPRI_UART0);
00116         /* Clear interrupt */
00117         outr(AIC_ICCR, _BV(US0_ID));
00118         break;
00119     case NUT_IRQCTL_STATUS:
00120         if (enabled) {
00121             *ival |= 1;
00122         }
00123         else {
00124             *ival &= ~1;
00125         }
00126         break;
00127     case NUT_IRQCTL_ENABLE:
00128         enabled = 1;
00129         break;
00130     case NUT_IRQCTL_DISABLE:
00131         enabled = 0;
00132         break;
00133     case NUT_IRQCTL_GETMODE:
00134         {
00135             u_int val = inr(AIC_SMR(US0_ID)) & AIC_SRCTYPE;
00136             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00137                 *ival = NUT_IRQMODE_LEVEL;
00138             } else  {
00139                 *ival = NUT_IRQMODE_EDGE;
00140             }
00141         }
00142         break;
00143     case NUT_IRQCTL_SETMODE:
00144         if (*ival == NUT_IRQMODE_LEVEL) {
00145             outr(AIC_SMR(US0_ID), (inr(AIC_SMR(US0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00146         } else if (*ival == NUT_IRQMODE_EDGE) {
00147             outr(AIC_SMR(US0_ID), (inr(AIC_SMR(US0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00148         } else  {
00149             rc = -1;
00150         }
00151         break;
00152     case NUT_IRQCTL_GETPRIO:
00153         *ival = inr(AIC_SMR(US0_ID)) & AIC_PRIOR;
00154         break;
00155     case NUT_IRQCTL_SETPRIO:
00156         outr(AIC_SMR(US0_ID), (inr(AIC_SMR(US0_ID)) & ~AIC_PRIOR) | *ival);
00157         break;
00158 #ifdef NUT_PERFMON
00159     case NUT_IRQCTL_GETCOUNT:
00160         *ival = (u_int)sig_UART0.ir_count;
00161         sig_UART0.ir_count = 0;
00162         break;
00163 #endif
00164     default:
00165         rc = -1;
00166         break;
00167     }
00168 
00169     /* Enable interrupt. */
00170     if (enabled) {
00171         outr(AIC_IECR, _BV(US0_ID));
00172     }
00173     return rc;
00174 }

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