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00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046
00047 #if defined(ADC_ID)
00048
00049 #ifndef NUT_IRQPRI_ADC
00050 #define NUT_IRQPRI_ADC 4
00051 #endif
00052
00053 static int AdcIrqCtl(int cmd, void *param);
00054
00055 IRQ_HANDLER sig_ADC = {
00056 #ifdef NUT_PERFMON
00057 0,
00058 #endif
00059 NULL,
00060 NULL,
00061 AdcIrqCtl
00062 };
00063
00067 static void AdcIrqEntry(void) __attribute__ ((naked));
00068 void AdcIrqEntry(void)
00069 {
00070 IRQ_ENTRY();
00071 #ifdef NUT_PERFMON
00072 sig_ADC.ir_count++;
00073 #endif
00074 if (sig_ADC.ir_handler) {
00075 (sig_ADC.ir_handler) (sig_ADC.ir_arg);
00076 }
00077 IRQ_EXIT();
00078 }
00079
00097 static int AdcIrqCtl(int cmd, void *param)
00098 {
00099 int rc = 0;
00100 u_int *ival = (u_int *)param;
00101 int enabled = inr(AIC_IMR) & _BV(ADC_ID);
00102
00103
00104 if (enabled) {
00105 outr(AIC_IDCR, _BV(ADC_ID));
00106 }
00107
00108 switch(cmd) {
00109 case NUT_IRQCTL_INIT:
00110
00111 outr(AIC_SVR(ADC_ID), (unsigned int)AdcIrqEntry);
00112
00113 outr(AIC_SMR(ADC_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_ADC);
00114
00115 outr(AIC_ICCR, _BV(ADC_ID));
00116 break;
00117 case NUT_IRQCTL_STATUS:
00118 if (enabled) {
00119 *ival |= 1;
00120 }
00121 else {
00122 *ival &= ~1;
00123 }
00124 break;
00125 case NUT_IRQCTL_ENABLE:
00126 enabled = 1;
00127 break;
00128 case NUT_IRQCTL_DISABLE:
00129 enabled = 0;
00130 break;
00131 case NUT_IRQCTL_GETMODE:
00132 {
00133 u_int val = inr(AIC_SMR(ADC_ID)) & AIC_SRCTYPE;
00134 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00135 *ival = NUT_IRQMODE_LEVEL;
00136 } else {
00137 *ival = NUT_IRQMODE_EDGE;
00138 }
00139 }
00140 break;
00141 case NUT_IRQCTL_SETMODE:
00142 if (*ival == NUT_IRQMODE_LEVEL) {
00143 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00144 } else if (*ival == NUT_IRQMODE_EDGE) {
00145 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00146 } else {
00147 rc = -1;
00148 }
00149 break;
00150 case NUT_IRQCTL_GETPRIO:
00151 *ival = inr(AIC_SMR(ADC_ID)) & AIC_PRIOR;
00152 break;
00153 case NUT_IRQCTL_SETPRIO:
00154 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_PRIOR) | *ival);
00155 break;
00156 #ifdef NUT_PERFMON
00157 case NUT_IRQCTL_GETCOUNT:
00158 *ival = (u_int)sig_ADC.ir_count;
00159 sig_ADC.ir_count = 0;
00160 break;
00161 #endif
00162 default:
00163 rc = -1;
00164 break;
00165 }
00166
00167
00168 if (enabled) {
00169 outr(AIC_IECR, _BV(ADC_ID));
00170 }
00171 return rc;
00172 }
00173
00174 #endif