at91_mci.h

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00001 #ifndef _ARCH_ARM_AT91_MCI_H_
00002 #define _ARCH_ARM_AT91_MCI_H_
00003 
00004 /*
00005  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00024  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00059 
00062 #define MCI_CR_OFF              0x00000000      
00063 #define MCI_CR      (MCI_BASE + MCI_CR_OFF)     
00064 #define MCI_MCIEN               0x00000001      
00065 #define MCI_MCIDIS              0x00000002      
00066 #define MCI_PWSEN               0x00000004      
00067 #define MCI_PWSDIS              0x00000008      
00068 #define MCI_SWRST               0x00000080      
00070 
00071 
00073 #define MCI_MR_OFF              0x00000004      
00074 #define MCI_MR      (MCI_BASE + MCI_MR_OFF)     
00075 #define MCI_CLKDIV              0x000000FF      
00076 #define MCI_CLKDIV_LSB                  0       
00077 #define MCI_PWSDIV              0x00000700      
00078 #define MCI_PWSDIV_LSB                  8       
00079 #define MCI_RDPROOF             0x00000800      
00080 #define MCI_WRPROOF             0x00001000      
00081 #define MCI_PDCFBYTE            0x00002000      
00082 #define MCI_PDCPADV             0x00004000      
00083 #define MCI_PDCMODE             0x00008000      
00084 #define MCI_BLKLEN              0xFFFF0000      
00085 #define MCI_BLKLEN_LSB                  16      
00087 
00088 
00090 #define MCI_DTOR_OFF            0x00000008      
00091 #define MCI_DTOR    (MCI_BASE + MCI_DTOR_OFF)   
00092 #define MCI_DTOCYC              0x0000000F      
00093 #define MCI_DTOCYC_LSB                  0       
00094 #define MCI_DTOMUL              0x00000070      
00095 #define MCI_DTOMUL_1            0x00000000      
00096 #define MCI_DTOMUL_16           0x00000010      
00097 #define MCI_DTOMUL_128          0x00000020      
00098 #define MCI_DTOMUL_256          0x00000030      
00099 #define MCI_DTOMUL_1K           0x00000040      
00100 #define MCI_DTOMUL_4K           0x00000050      
00101 #define MCI_DTOMUL_64K          0x00000060      
00102 #define MCI_DTOMUL_1M           0x00000070      
00104 
00105 
00107 #define MCI_SDCR_OFF            0x0000000C      
00108 #define MCI_SDCR    (MCI_BASE + MCI_SDCR_OFF)   
00109 #define MCI_SDCSEL              0x00000003      
00110 #define MCI_SDCSEL_SLOTA        0x00000000      
00111 #define MCI_SDCSEL_SLOTB        0x00000001      
00112 #define MCI_SDCBUS              0x00000080      
00114 
00115 
00117 #define MCI_ARGR_OFF            0x00000010      
00118 #define MCI_ARGR    (MCI_BASE + MCI_ARGR_OFF)   
00120 
00121 
00123 #define MCI_CMDR_OFF            0x00000014      
00124 #define MCI_CMDR    (MCI_BASE + MCI_CMDR_OFF)   
00125 #define MCI_CMDNB               0x0000003F      
00126 #define MCI_CMDNB_LSB                   0       
00127 #define MCI_RSPTYP              0x000000C0      
00128 #define MCI_RSPTYP_NONE         0x00000000      
00129 #define MCI_RSPTYP_48           0x00000040      
00130 #define MCI_RSPTYP_136          0x00000080      
00131 #define MCI_SPCMD               0x00000700      
00132 #define MCI_SPCMD_NONE          0x00000000      
00133 #define MCI_SPCMD_INIT          0x00000100      
00134 #define MCI_SPCMD_SYNC          0x00000200      
00135 #define MCI_SPCMD_ICMD          0x00000400      
00136 #define MCI_SPCMD_IRSP          0x00000500      
00137 #define MCI_OPCMD               0x00000800      
00138 #define MCI_MAXLAT              0x00001000      
00139 #define MCI_TRCMD               0x00030000      
00140 #define MCI_TRCMD_NONE          0x00000000      
00141 #define MCI_TRCMD_START         0x00010000      
00142 #define MCI_TRCMD_STOP          0x00020000      
00143 #define MCI_TRDIR               0x00040000      
00144 #define MCI_TRTYP               0x00380000      
00145 #define MCI_TRTYP_MMC_SBLK      0x00000000      
00146 #define MCI_TRTYP_MMC_MBLK      0x00080000      
00147 #define MCI_TRTYP_MMC_STREAM    0x00100000      
00148 #define MCI_TRTYP_SDIO_BYTE     0x00200000      
00149 #define MCI_TRTYP_SDIO_BLK      0x00280000      
00150 #define MCI_IOSPCMD             0x03000000      
00151 #define MCI_IOSPCMD_NONE        0x00000000      
00152 #define MCI_IOSPCMD_SUSPEND     0x01000000      
00153 #define MCI_IOSPCMD_RESUME      0x02000000      
00155 
00156 
00158 #define MCI_BLKR_OFF            0x00000018      
00159 #define MCI_BLKR    (MCI_BASE + MCI_BLKR_OFF)   
00160 #define MCI_BCNT                0x0000FFFF      
00161 #define MCI_BCNT_LSB                    0       
00163 
00164 
00166 #define MCI_RSPR_OFF            0x00000020      
00167 #define MCI_RSPR    (MCI_BASE + MCI_RSPR_OFF)   
00169 
00170 
00172 #define MCI_RDR_OFF             0x00000030      
00173 #define MCI_RDR     (MCI_BASE + MCI_RDR_OFF)    
00175 
00176 
00178 #define MCI_TDR_OFF             0x00000034      
00179 #define MCI_TDR     (MCI_BASE + MCI_TDR_OFF)    
00181 
00182 
00184 #define MCI_SR_OFF              0x00000040      
00185 #define MCI_SR      (MCI_BASE + MCI_SR_OFF)     
00187 #define MCI_IER_OFF             0x00000044      
00188 #define MCI_IER     (MCI_BASE + MCI_IER_OFF)    
00190 #define MCI_IDR_OFF             0x00000048      
00191 #define MCI_IDR     (MCI_BASE + MCI_IDR_OFF)    
00193 #define MCI_IMR_OFF             0x0000004C      
00194 #define MCI_IMR     (MCI_BASE + MCI_IMR_OFF)    
00196 #define MCI_CMDRDY              0x00000001      
00197 #define MCI_RXRDY               0x00000002      
00198 #define MCI_TXRDY               0x00000004      
00199 #define MCI_BLKE                0x00000008      
00200 #define MCI_DTIP                0x00000010      
00201 #define MCI_NOTBUSY             0x00000020      
00202 #define MCI_ENDRX               0x00000040      
00203 #define MCI_ENDTX               0x00000080      
00204 #define MCI_SDIOIRQA            0x00000100      
00205 #define MCI_SDIOIRQB            0x00000200      
00206 #define MCI_RXBUFF              0x00004000      
00207 #define MCI_TXBUFE              0x00008000      
00208 #define MCI_RINDE               0x00010000      
00209 #define MCI_RDIRE               0x00020000      
00210 #define MCI_RCRCE               0x00040000      
00211 #define MCI_RENDE               0x00080000      
00212 #define MCI_RTOE                0x00100000      
00213 #define MCI_DCRCE               0x00200000      
00214 #define MCI_DTOE                0x00400000      
00215 #define MCI_OVRE                0x40000000      
00216 #define MCI_UNRE                0x80000000      
00219 
00220 #if defined(MCI_HAS_PDC)
00221 
00224 #define MCI_RPR    (MCI_BASE + PERIPH_RPR_OFF)  
00226 
00227 
00229 #define MCI_RCR    (MCI_BASE + PERIPH_RCR_OFF)  
00231 
00232 
00234 #define MCI_TPR    (MCI_BASE + PERIPH_TPR_OFF)  
00236 
00237 
00239 #define MCI_TCR    (MCI_BASE + PERIPH_TCR_OFF)  
00241 
00242 
00244 #define MCI_RNPR   (MCI_BASE + PERIPH_RNPR_OFF) 
00246 
00247 
00249 #define MCI_RNCR   (MCI_BASE + PERIPH_RNCR_OFF) 
00251 
00252 
00254 #define MCI_TNPR   (MCI_BASE + PERIPH_TNPR_OFF) 
00256 
00257 
00259 #define MCI_TNCR   (MCI_BASE + PERIPH_TNCR_OFF) 
00261 
00262 
00264 #define MCI_PTCR   (MCI_BASE + PERIPH_PTCR_OFF) 
00266 
00267 
00269 #define MCI_PTSR   (MCI_BASE + PERIPH_PTSR_OFF) 
00271 
00272 #endif
00273 
00276 #endif                          /* _ARCH_ARM_AT91_MCI_H_ */

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