ih_at91tc1.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91tc1.c,v $
00036  * Revision 1.3  2008/07/26 09:43:01  haraldkipp
00037  * Added support for retrieving and setting the interrupt mode.
00038  *
00039  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00040  * Include more general header file for ARM.
00041  *
00042  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00043  * First check in.
00044  *
00045  */
00046 
00047 #include <arch/arm.h>
00048 #include <dev/irqreg.h>
00049 
00050 #ifndef NUT_IRQPRI_TC1
00051 #define NUT_IRQPRI_TC1  4
00052 #endif
00053 
00054 static int TimerCounter1IrqCtl(int cmd, void *param);
00055 
00056 IRQ_HANDLER sig_TC1 = {
00057 #ifdef NUT_PERFMON
00058     0,                  /* Interrupt counter, ir_count. */
00059 #endif
00060     NULL,               /* Passed argument, ir_arg. */
00061     NULL,               /* Handler subroutine, ir_handler. */
00062     TimerCounter1IrqCtl /* Interrupt control, ir_ctl. */
00063 };
00064 
00068 static u_int dummy;
00069 static void TimerCounter1IrqEntry(void) __attribute__ ((naked));
00070 void TimerCounter1IrqEntry(void)
00071 {
00072     IRQ_ENTRY();
00073 #ifdef NUT_PERFMON
00074     sig_TC1.ir_count++;
00075 #endif
00076     dummy = inr(TC1_SR);
00077     if (sig_TC1.ir_handler) {
00078         (sig_TC1.ir_handler) (sig_TC1.ir_arg);
00079     }
00080     IRQ_EXIT();
00081 }
00082 
00100 static int TimerCounter1IrqCtl(int cmd, void *param)
00101 {
00102     int rc = 0;
00103     u_int *ival = (u_int *)param;
00104     int enabled = inr(AIC_IMR) & _BV(TC1_ID);
00105 
00106     /* Disable interrupt. */
00107     if (enabled) {
00108         outr(AIC_IDCR, _BV(TC1_ID));
00109     }
00110     switch(cmd) {
00111     case NUT_IRQCTL_INIT:
00112         /* Set the vector. */
00113         outr(AIC_SVR(TC1_ID), (unsigned int)TimerCounter1IrqEntry);
00114         /* Initialize to edge triggered with defined priority. */
00115         outr(AIC_SMR(TC1_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC1);
00116         /* Clear interrupt */
00117         outr(AIC_ICCR, _BV(TC1_ID));
00118         /* Init will return with interrupts disabled. */
00119         enabled = 0;
00120         break;
00121     case NUT_IRQCTL_STATUS:
00122         if (enabled) {
00123             *ival |= 1;
00124         }
00125         else {
00126             *ival &= ~1;
00127         }
00128         break;
00129     case NUT_IRQCTL_ENABLE:
00130         enabled = 1;
00131         break;
00132     case NUT_IRQCTL_DISABLE:
00133         enabled = 0;
00134         break;
00135     case NUT_IRQCTL_GETMODE:
00136         {
00137             u_int val = inr(AIC_SMR(TC1_ID)) & AIC_SRCTYPE;
00138             if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00139                 *ival = NUT_IRQMODE_LEVEL;
00140             } else  {
00141                 *ival = NUT_IRQMODE_EDGE;
00142             }
00143         }
00144         break;
00145     case NUT_IRQCTL_SETMODE:
00146         if (*ival == NUT_IRQMODE_LEVEL) {
00147             outr(AIC_SMR(TC1_ID), (inr(AIC_SMR(TC1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00148         } else if (*ival == NUT_IRQMODE_EDGE) {
00149             outr(AIC_SMR(TC1_ID), (inr(AIC_SMR(TC1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00150         } else  {
00151             rc = -1;
00152         }
00153         break;
00154     case NUT_IRQCTL_GETPRIO:
00155         *ival = inr(AIC_SMR(TC1_ID)) & AIC_PRIOR;
00156         break;
00157     case NUT_IRQCTL_SETPRIO:
00158         outr(AIC_SMR(TC1_ID), (inr(AIC_SMR(TC1_ID)) & ~AIC_PRIOR) | *ival);
00159         break;
00160 #ifdef NUT_PERFMON
00161     case NUT_IRQCTL_GETCOUNT:
00162         *ival = (u_int)sig_TC1.ir_count;
00163         sig_TC1.ir_count = 0;
00164         break;
00165 #endif
00166     default:
00167         rc = -1;
00168         break;
00169     }
00170 
00171     /* Enable interrupt. */
00172     if (enabled) {
00173         outr(AIC_IECR, _BV(TC1_ID));
00174     }
00175     return rc;
00176 }

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