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00073 #include <cfg/clock.h>
00074
00075 #include <sys/atom.h>
00076 #include <sys/event.h>
00077 #include <sys/timer.h>
00078
00079 #include <dev/irqreg.h>
00080
00081 #include <dev/usartat91.h>
00082
00087
00088
00089 #define ASCII_XON 0x11
00090
00091 #define ASCII_XOFF 0x13
00092
00093
00094 #define XON_PENDING 0x10
00095
00096 #define XOFF_PENDING 0x20
00097
00098 #define XOFF_SENT 0x40
00099
00100 #define XOFF_RCVD 0x80
00101
00102
00106 static ureg_t rx_errors;
00107
00111 static ureg_t flow_control;
00112
00116 static ureg_t tx_aframe;
00117
00118 #ifdef UART_HDX_BIT
00119
00120 #ifdef UART_HDX_FLIP_BIT
00121 #define UART_HDX_TX cbi
00122 #define UART_HDX_RX sbi
00123 #else
00124 #define UART_HDX_TX sbi
00125 #define UART_HDX_RX cbi
00126 #endif
00127 #endif
00128
00129
00130 #ifdef UART_HDX_BIT
00131
00137 static ureg_t hdx_control;
00138 #endif
00139
00140 #ifdef UART_RTS_BIT
00141
00147 static ureg_t rts_control;
00148 #endif
00149
00150 #ifdef UART_CTS_BIT
00151
00157 static ureg_t cts_sense;
00158 #endif
00159
00160 #ifdef UART_CTS_BIT
00161
00171 static void At91UsartCts(void *arg)
00172 {
00173
00174
00175
00176
00177 }
00178 #endif
00179
00180 #ifdef UART_HDX_BIT
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192 static void At91UsartTxEmpty(RINGBUF *rbf)
00193 {
00194
00195
00196
00197
00198 if (hdx_control && rbf->rbf_cnt == 0) {
00199
00200 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
00201 }
00202 }
00203 #endif
00204
00205
00206
00207
00208
00209
00210 static void At91UsartTxReady(RINGBUF *rbf)
00211 {
00212 register u_char *cp = rbf->rbf_tail;
00213
00214
00215
00216
00217 if (flow_control & (XON_PENDING | XOFF_PENDING)) {
00218 if (flow_control & XON_PENDING) {
00219 outr(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00220 flow_control |= XOFF_SENT;
00221 } else {
00222 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
00223 flow_control &= ~XOFF_SENT;
00224 }
00225 flow_control &= ~(XON_PENDING | XOFF_PENDING);
00226 return;
00227 }
00228
00229 if (flow_control & XOFF_RCVD) {
00230
00231
00232
00233
00234 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00235 return;
00236 }
00237
00238 if (rbf->rbf_cnt) {
00239
00240 #ifdef UART_CTS_BIT
00241
00242
00243
00244
00245 if (cts_sense && bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00246 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00247 sbi(EIMSK, UART_CTS_BIT);
00248 return;
00249 }
00250 #endif
00251 rbf->rbf_cnt--;
00252
00253
00254
00255
00256 if (tx_aframe) {
00257 outr(USARTn_BASE + US_CR_OFF, US_SENDA);
00258 }
00259
00260
00261
00262
00263 outr(USARTn_BASE + US_THR_OFF, *cp);
00264
00265
00266
00267
00268 if (++cp == rbf->rbf_last) {
00269 cp = rbf->rbf_start;
00270 }
00271 rbf->rbf_tail = cp;
00272 if (rbf->rbf_cnt == rbf->rbf_lwm) {
00273 NutEventPostFromIrq(&rbf->rbf_que);
00274 }
00275 }
00276
00277
00278
00279
00280 else {
00281 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00282 rbf->rbf_cnt = 0;
00283 NutEventPostFromIrq(&rbf->rbf_que);
00284 }
00285 }
00286
00287
00288
00289
00290
00291
00292
00293
00294
00295 static void At91UsartRxReady(RINGBUF *rbf)
00296 {
00297 register size_t cnt;
00298 register u_char ch;
00299
00300
00301
00302
00303
00304 ch = inb(USARTn_BASE + US_RHR_OFF);
00305
00306
00307 rx_errors |= inr(USARTn_BASE + US_CSR_OFF) & (US_OVRE | US_FRAME | US_PARE);
00308
00309
00310
00311
00312
00313
00314 if (flow_control) {
00315
00316 if (ch == ASCII_XOFF) {
00317 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00318 flow_control |= XOFF_RCVD;
00319 return;
00320 }
00321
00322 else if (ch == ASCII_XON) {
00323 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
00324 flow_control &= ~XOFF_RCVD;
00325 return;
00326 }
00327 }
00328
00329
00330
00331
00332 cnt = rbf->rbf_cnt;
00333 if (cnt >= rbf->rbf_siz) {
00334 rx_errors |= US_OVRE;
00335 return;
00336 }
00337
00338
00339 if (cnt++ == 0){
00340 NutEventPostFromIrq(&rbf->rbf_que);
00341 }
00342
00343
00344
00345
00346
00347 else if (flow_control) {
00348 if(cnt >= rbf->rbf_hwm) {
00349 if((flow_control & XOFF_SENT) == 0) {
00350 if (inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY) {
00351 outb(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00352 flow_control |= XOFF_SENT;
00353 flow_control &= ~XOFF_PENDING;
00354 } else {
00355 flow_control |= XOFF_PENDING;
00356 }
00357 }
00358 }
00359 }
00360
00361 #ifdef UART_RTS_BIT
00362
00363
00364
00365
00366 else if (rts_control && cnt >= rbf->rbf_hwm) {
00367 sbi(UART_RTS_PORT, UART_RTS_BIT);
00368 }
00369 #endif
00370
00371
00372
00373
00374 *rbf->rbf_head++ = ch;
00375 if (rbf->rbf_head == rbf->rbf_last) {
00376 rbf->rbf_head = rbf->rbf_start;
00377 }
00378
00379
00380 rbf->rbf_cnt = cnt;
00381 }
00382
00388 static void At91UsartInterrupt(void *arg)
00389 {
00390 USARTDCB *dcb = (USARTDCB *)arg;
00391 ureg_t csr = inr(USARTn_BASE + US_CSR_OFF);
00392
00393 if (csr & US_RXRDY) {
00394 At91UsartRxReady(&dcb->dcb_rx_rbf);
00395 }
00396 if (csr & US_TXRDY) {
00397 At91UsartTxReady(&dcb->dcb_tx_rbf);
00398 }
00399
00400 #ifdef UART_HDX_BIT
00401 if (csr & US_TXEMPTY) {
00402 At91UsartTxEmpty(&dcb->dcb_tx_rbf);
00403 }
00404 #endif
00405 }
00406
00413 static void At91UsartEnable(void)
00414 {
00415 NutEnterCritical();
00416
00417
00418 outr(USARTn_BASE + US_CR_OFF, US_RXEN | US_TXEN);
00419
00420
00421 outr(USARTn_BASE + US_IER_OFF, US_RXRDY | US_TXRDY);
00422 NutIrqEnable(&SIG_UART);
00423
00424 #ifdef UART_HDX_BIT
00425 if (hdx_control) {
00426
00427 sbi(UCSRnB, TXCIE);
00428 }
00429 #endif
00430
00431 NutExitCritical();
00432 }
00433
00437 static void At91UsartDisable(void)
00438 {
00439
00440
00441
00442 NutEnterCritical();
00443 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
00444 NutExitCritical();
00445
00446
00447
00448
00449 NutDelay(10);
00450
00451
00452
00453
00454 outr(USARTn_BASE + US_CR_OFF, US_RXDIS | US_TXDIS);
00455 }
00456
00465 static u_long At91UsartGetSpeed(void)
00466 {
00467 ureg_t cs = inr(USARTn_BASE + US_MR_OFF);
00468 u_long clk;
00469
00470 #if defined(AT91_PLL_MAINCK)
00471 clk = At91GetMasterClock();
00472 #else
00473 clk = NutGetCpuClock();
00474 #endif
00475 if ((cs & US_CLKS) == US_CLKS_MCK8) {
00476 clk /= 8;
00477 }
00478 else if ((cs & US_CLKS) != US_CLKS_MCK) {
00479 clk = 0;
00480 }
00481 return clk / (16UL * (inr(USARTn_BASE + US_BRGR_OFF) & 0xFFFF));
00482 }
00483
00494 static int At91UsartSetSpeed(u_long rate)
00495 {
00496 At91UsartDisable();
00497 #if defined(AT91_PLL_MAINCK)
00498 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (rate)) + 1) / 2);
00499 #else
00500 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (rate)) + 1) / 2);
00501 #endif
00502 At91UsartEnable();
00503
00504 return 0;
00505 }
00506
00515 static u_char At91UsartGetDataBits(void)
00516 {
00517 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00518
00519 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00520 val = 9;
00521 }
00522 else {
00523 val &= US_CHRL;
00524 if (val == US_CHRL_5) {
00525 val = 5;
00526 }
00527 else if (val == US_CHRL_6) {
00528 val = 6;
00529 }
00530 else if (val == US_CHRL_7) {
00531 val = 7;
00532 }
00533 else {
00534 val = 8;
00535 }
00536 }
00537 return (u_char)val;
00538 }
00539
00548 static int At91UsartSetDataBits(u_char bits)
00549 {
00550 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00551
00552 if (bits == 9) {
00553 val &= ~US_PAR;
00554 val |= US_PAR_MULTIDROP;
00555 }
00556 else {
00557 val &= ~US_CHRL;
00558 if (bits == 5) {
00559 val |= US_CHRL_5;
00560 }
00561 else if (bits == 6) {
00562 val |= US_CHRL_6;
00563 }
00564 else if (bits == 7) {
00565 val |= US_CHRL_7;
00566 }
00567 else if (bits == 8) {
00568 val |= US_CHRL_8;
00569 }
00570 }
00571
00572 At91UsartDisable();
00573 outr(USARTn_BASE + US_MR_OFF, val);
00574 At91UsartEnable();
00575
00576
00577
00578
00579 if (At91UsartGetDataBits() != bits) {
00580 return -1;
00581 }
00582 return 0;
00583 }
00584
00593 static u_char At91UsartGetParity(void)
00594 {
00595 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_PAR;
00596
00597 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00598 val = 9;
00599 }
00600 else {
00601 if (val == US_PAR_ODD) {
00602 val = 1;
00603 }
00604 else if (val == US_PAR_EVEN) {
00605 val = 2;
00606 }
00607 else {
00608 val = 0;
00609 }
00610 }
00611 return (u_char)val;
00612 }
00613
00624 static int At91UsartSetParity(u_char mode)
00625 {
00626 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_PAR;
00627
00628 switch (mode) {
00629 case 0:
00630 val |= US_PAR_NO;
00631 break;
00632 case 1:
00633 val |= US_PAR_ODD;
00634 break;
00635 case 2:
00636 val |= US_PAR_EVEN;
00637 break;
00638 }
00639 At91UsartDisable();
00640 outr(USARTn_BASE + US_MR_OFF, val);
00641 At91UsartEnable();
00642
00643
00644
00645
00646 if (At91UsartGetParity() != mode) {
00647 return -1;
00648 }
00649 return 0;
00650 }
00651
00660 static u_char At91UsartGetStopBits(void)
00661 {
00662 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_NBSTOP;
00663 if (val == US_NBSTOP_1) {
00664 val = 1;
00665 }
00666 else if (val == US_NBSTOP_2) {
00667 val = 2;
00668 }
00669 else {
00670 val = 3;
00671 }
00672 return (u_char)val;
00673 }
00674
00683 static int At91UsartSetStopBits(u_char bits)
00684 {
00685 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_NBSTOP;
00686
00687 switch(bits) {
00688 case 1:
00689 val |= US_NBSTOP_1;
00690 break;
00691 case 2:
00692 val |= US_NBSTOP_2;
00693 break;
00694 case 3:
00695 val |= US_NBSTOP_1_5;
00696 break;
00697 }
00698 At91UsartDisable();
00699 outr(USARTn_BASE + US_MR_OFF, val);
00700 At91UsartEnable();
00701
00702
00703
00704
00705 if (At91UsartGetStopBits() != bits) {
00706 return -1;
00707 }
00708 return 0;
00709 }
00710
00716 static u_long At91UsartGetStatus(void)
00717 {
00718 u_long rc = 0;
00719
00720
00721
00722
00723 if ((rx_errors & US_FRAME) != 0) {
00724 rc |= UART_FRAMINGERROR;
00725 }
00726 if ((rx_errors & US_OVRE) != 0) {
00727 rc |= UART_OVERRUNERROR;
00728 }
00729 if ((rx_errors & US_PARE) != 0) {
00730 rc |= UART_PARITYERROR;
00731 }
00732
00733
00734
00735
00736
00737 if (flow_control) {
00738 if (flow_control & XOFF_SENT) {
00739 rc |= UART_RXDISABLED;
00740 }
00741 if (flow_control & XOFF_RCVD) {
00742 rc |= UART_TXDISABLED;
00743 }
00744 }
00745 #ifdef UART_RTS_BIT
00746
00747
00748
00749 if (bit_is_set(UART_RTS_PORT, UART_RTS_BIT)) {
00750 rc |= UART_RTSDISABLED;
00751 if (rts_control) {
00752 rc |= UART_RXDISABLED;
00753 }
00754 } else {
00755 rc |= UART_RTSENABLED;
00756 }
00757 #endif
00758
00759 #ifdef UART_CTS_BIT
00760
00761
00762
00763 if (bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00764 rc |= UART_CTSDISABLED;
00765 if (cts_sense) {
00766 rc |= UART_RXDISABLED;
00767 }
00768 } else {
00769 rc |= UART_CTSENABLED;
00770 }
00771 #endif
00772
00773
00774
00775
00776
00777 if ((rc & UART_RXDISABLED) == 0) {
00778 rc |= UART_RXENABLED;
00779 }
00780 if ((rc & UART_TXDISABLED) == 0) {
00781 rc |= UART_TXENABLED;
00782 }
00783
00784
00785
00786
00787 if (tx_aframe) {
00788 rc |= UART_TXADDRFRAME;
00789 } else {
00790 rc |= UART_TXNORMFRAME;
00791 }
00792 return rc;
00793 }
00794
00802 static int At91UsartSetStatus(u_long flags)
00803 {
00804
00805
00806
00807 if (flow_control) {
00808
00809
00810 NutEnterCritical();
00811
00812
00813
00814
00815
00816 if (flags & UART_RXENABLED) {
00817 flow_control &= ~XOFF_SENT;
00818 } else if (flags & UART_RXDISABLED) {
00819 flow_control |= XOFF_SENT;
00820 }
00821
00822
00823
00824
00825
00826 if (flags & UART_TXENABLED) {
00827 flow_control &= ~XOFF_RCVD;
00828 } else if (flags & UART_TXDISABLED) {
00829 flow_control |= XOFF_RCVD;
00830 }
00831 NutExitCritical();
00832 }
00833 #ifdef UART_RTS_BIT
00834
00835
00836
00837 if (rts_control) {
00838 if (flags & UART_RXDISABLED) {
00839 sbi(UART_RTS_PORT, UART_RTS_BIT);
00840 }
00841 if (flags & UART_RXENABLED) {
00842 cbi(UART_RTS_PORT, UART_RTS_BIT);
00843 }
00844 }
00845 if (flags & UART_RTSDISABLED) {
00846 sbi(UART_RTS_PORT, UART_RTS_BIT);
00847 }
00848 if (flags & UART_RTSENABLED) {
00849 cbi(UART_RTS_PORT, UART_RTS_BIT);
00850 }
00851 #endif
00852
00853
00854
00855
00856 if (flags & UART_TXADDRFRAME) {
00857 tx_aframe = 1;
00858 }
00859 if (flags & UART_TXNORMFRAME) {
00860 tx_aframe = 0;
00861 }
00862
00863
00864
00865
00866 if (flags & UART_ERRORS) {
00867 outr(USARTn_BASE + US_CR_OFF, US_RSTSTA);
00868 }
00869
00870
00871
00872
00873 if ((At91UsartGetStatus() & ~UART_ERRORS) != flags) {
00874 return -1;
00875 }
00876 return 0;
00877 }
00878
00888 static u_char At91UsartGetClockMode(void)
00889 {
00890 u_char rc = 0;
00891
00892 return rc;
00893 }
00894
00906 static int At91UsartSetClockMode(u_char mode)
00907 {
00908
00909
00910
00911 if (At91UsartGetClockMode() != mode) {
00912 return -1;
00913 }
00914 return 0;
00915 }
00916
00925 static u_long At91UsartGetFlowControl(void)
00926 {
00927 u_long rc = 0;
00928
00929 if (flow_control) {
00930 rc |= USART_MF_XONXOFF;
00931 } else {
00932 rc &= ~USART_MF_XONXOFF;
00933 }
00934
00935 #ifdef UART_RTS_BIT
00936 if (rts_control) {
00937 rc |= USART_MF_RTSCONTROL;
00938 } else {
00939 rc &= ~USART_MF_RTSCONTROL;
00940 }
00941 #endif
00942
00943 #ifdef UART_CTS_BIT
00944 if (cts_sense) {
00945 rc |= USART_MF_CTSSENSE;
00946 } else {
00947 rc &= ~USART_MF_CTSSENSE;
00948 }
00949 #endif
00950
00951 #ifdef UART_HDX_BIT
00952 if (hdx_control) {
00953 rc |= USART_MF_HALFDUPLEX;
00954 } else {
00955 rc &= ~USART_MF_HALFDUPLEX;
00956 }
00957 #endif
00958
00959 return rc;
00960 }
00961
00972 static int At91UsartSetFlowControl(u_long flags)
00973 {
00974
00975
00976
00977 if (flags & USART_MF_XONXOFF) {
00978 if(flow_control == 0) {
00979 NutEnterCritical();
00980 flow_control = 1 | XOFF_SENT;
00981 NutExitCritical();
00982 }
00983 } else {
00984 NutEnterCritical();
00985 flow_control = 0;
00986 NutExitCritical();
00987 }
00988
00989 #ifdef UART_RTS_BIT
00990
00991
00992
00993 if (flags & USART_MF_RTSCONTROL) {
00994 sbi(UART_RTS_PORT, UART_RTS_BIT);
00995 sbi(UART_RTS_DDR, UART_RTS_BIT);
00996 rts_control = 1;
00997 } else if (rts_control) {
00998 rts_control = 0;
00999 cbi(UART_RTS_DDR, UART_RTS_BIT);
01000 }
01001 #endif
01002
01003 #ifdef UART_CTS_BIT
01004
01005
01006
01007 if (flags & USART_MF_CTSSENSE) {
01008
01009 if (NutRegisterIrqHandler(&UART_CTS_SIGNAL, At91UsartCts, 0)) {
01010 return -1;
01011 }
01012 sbi(UART_CTS_PORT, UART_CTS_BIT);
01013 cbi(UART_CTS_DDR, UART_CTS_BIT);
01014 cts_sense = 1;
01015 } else if (cts_sense) {
01016 cts_sense = 0;
01017
01018 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01019 cbi(UART_CTS_DDR, UART_CTS_BIT);
01020 }
01021 #endif
01022
01023 #ifdef UART_HDX_BIT
01024
01025
01026
01027 if (flags & USART_MF_HALFDUPLEX) {
01028
01029 if (NutRegisterIrqHandler(&sig_UART_TRANS, At91UsartTxComplete, &dcb_usart.dcb_rx_rbf)) {
01030 return -1;
01031 }
01032
01033 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
01034 sbi(UART_HDX_DDR, UART_HDX_BIT);
01035 hdx_control = 1;
01036
01037 sbi(UCSRnB, TXCIE);
01038 } else if (hdx_control) {
01039 hdx_control = 0;
01040
01041 cbi(UCSRnB, TXCIE);
01042
01043 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01044 cbi(UART_HDX_DDR, UART_HDX_BIT);
01045 }
01046 #endif
01047
01048
01049
01050
01051 if (At91UsartGetFlowControl() != flags) {
01052 return -1;
01053 }
01054 return 0;
01055 }
01056
01064 static void At91UsartTxStart(void)
01065 {
01066 #ifdef UART_HDX_BIT
01067 if (hdx_control) {
01068
01069 UART_HDX_TX(UART_HDX_PORT, UART_HDX_BIT);
01070 }
01071 #endif
01072
01073 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
01074 }
01075
01084 static void At91UsartRxStart(void)
01085 {
01086
01087
01088
01089 if (flow_control && (flow_control & XOFF_SENT) != 0) {
01090 NutEnterCritical();
01091 if ((inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY)) {
01092 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
01093 flow_control &= ~XON_PENDING;
01094 } else {
01095 flow_control |= XON_PENDING;
01096 }
01097 flow_control &= ~(XOFF_SENT | XOFF_PENDING);
01098 NutExitCritical();
01099 }
01100 #ifdef UART_RTS_BIT
01101 if (rts_control) {
01102
01103 cbi(UART_RTS_PORT, UART_RTS_BIT);
01104 }
01105 #endif
01106 }
01107
01108
01109
01110
01111
01112
01113
01114
01115
01116 static int At91UsartInit(void)
01117 {
01118
01119
01120
01121 if (NutRegisterIrqHandler(&SIG_UART, At91UsartInterrupt, &dcb_usart)) {
01122 return -1;
01123 }
01124
01125 #if defined (MCU_AT91R40008)
01126
01127 outr(PS_PCER, _BV(US_ID));
01128
01129 outr(PIO_PDR, US_GPIO_PINS);
01130 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256) || defined(MCU_AT91SAM7SE512)
01131 outr(PMC_PCER, _BV(US_ID));
01132 outr(PIOA_PDR, US_GPIO_PINS);
01133 #endif
01134
01135 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01136
01137 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01138
01139 #if defined (US_RCR_OFF)
01140 outr(USARTn_BASE + US_RCR_OFF, 0);
01141 #endif
01142 #if defined (US_TCR_OFF)
01143 outr(USARTn_BASE + US_TCR_OFF, 0);
01144 #endif
01145
01146 #if defined(AT91_PLL_MAINCK)
01147 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (115200)) + 1) / 2);
01148 #else
01149 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
01150 #endif
01151
01152
01153 #ifdef AT91_UART_RS485_MODE
01154 outr(USARTn_BASE + US_MR_OFF, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_MODE_RS485);
01155 #else
01156 outr(USARTn_BASE + US_MR_OFF, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
01157 #endif
01158
01159 return 0;
01160 }
01161
01162
01163
01164
01165
01166
01167
01168
01169
01170 static int At91UsartDeinit(void)
01171 {
01172
01173 NutRegisterIrqHandler(&SIG_UART, 0, 0);
01174
01175
01176 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01177
01178 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01179 #if defined (MCU_AT91R40008)
01180
01181 outr(PS_PCDR, _BV(US_ID));
01182
01183 outr(PIO_PER, US_GPIO_PINS);
01184 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256) || defined(MCU_AT91SAM7SE512)
01185 outr(PMC_PCDR, _BV(US_ID));
01186 outr(PIOA_PER, US_GPIO_PINS);
01187 #endif
01188
01189
01190
01191
01192
01193
01194 #ifdef UART_HDX_BIT
01195
01196 if (hdx_control) {
01197 hdx_control = 0;
01198 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01199 }
01200 #endif
01201
01202 #ifdef UART_CTS_BIT
01203 if (cts_sense) {
01204 cts_sense = 0;
01205 cbi(UART_CTS_DDR, UART_CTS_BIT);
01206
01207 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01208 }
01209 #endif
01210
01211 #ifdef UART_RTS_BIT
01212 if (rts_control) {
01213 rts_control = 0;
01214 cbi(UART_RTS_DDR, UART_RTS_BIT);
01215 }
01216 #endif
01217
01218 return 0;
01219 }
01220