at91_twi.c

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00001 /*
00002  * Copyright (C) 2001-2005 by EmbeddedIT, 
00003  * Ole Reinhardt <ole.reinhardt@embedded-it.de> All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EMBEDDED IT AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EMBEDDED IT
00022  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
00023  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
00024  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 
00025  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00026  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
00027  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00028  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: at91_twi.c,v $
00036  * Revision 1.5  2008/02/15 16:58:41  haraldkipp
00037  * Spport for AT91SAM7SE512 added.
00038  *
00039  * Revision 1.4  2007/12/09 22:17:23  olereinhardt
00040  * fixed typo
00041  *
00042  * Revision 1.3  2007/12/09 21:52:27  olereinhardt
00043  * Added doxygen tags
00044  *
00045  * Revision 1.2  2007/10/04 19:51:56  olereinhardt
00046  * Support for sam7s added
00047  *
00048  * Revision 1.1  2007/09/06 19:36:00  olereinhardt
00049  * First checkin, new twi driver for at91 (currently SAM7X256 is supported
00050  * only)
00051  *
00052  */
00053 
00054 #include <arch/arm.h>
00055 #include <dev/irqreg.h>
00056 
00057 #include <sys/event.h>
00058 #include <sys/atom.h>
00059 #include <sys/timer.h>
00060 #include <sys/thread.h>
00061 #include <sys/heap.h>
00062 
00063 #include <dev/twif.h>
00064 
00069 
00070 HANDLE tw_mm_mutex;                 /* Exclusive master access. */
00071 HANDLE tw_mm_que;                   /* Threads waiting for master transfer done. */
00072 
00073 static u_char tw_mm_sla;            /* Destination slave address. */
00074 static volatile u_char tw_mm_err;   /* Current master mode error. */
00075 static u_char tw_mm_error;          /* Last master mode error. */
00076 
00077 static CONST u_char *tw_mt_buf;     /* Pointer to the master transmit buffer. */
00078 static volatile u_short tw_mt_len;  /* Number of bytes to transmit in master mode. */
00079 static volatile u_short tw_mt_idx;  /* Current master transmit buffer index. */
00080 
00081 static u_char *tw_mr_buf;           /* Pointer to the master receive buffer. */
00082 static volatile u_short tw_mr_siz;  /* Size of the master receive buffer. */
00083 static volatile u_short tw_mr_idx;  /* Current master receive buffer index. */
00084 
00085 #if defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256) || defined (MCU_AT91SAM7SE512)
00086 
00087 #define TWI_PIO_ASR PIOA_ASR
00088 #define TWI_PIO_PDR PIOA_PDR
00089 #define TWI_PIO_MDER PIOA_MDER
00090 
00091    #if defined (MCU_AT91SAM7X256)
00092       #define TWI_TWD  PA10_TWD_A
00093       #define TWI_TWCK PA11_TWCK_A
00094    #elif defined (MCU_AT91SAM7S256) || defined (MCU_AT91SAM7SE512)
00095       #define TWI_TWD  PA3_TWD_A
00096       #define TWI_TWCK PA4_TWCK_A
00097    #endif
00098 #endif
00099 
00100 /*
00101  * TWI interrupt handler.
00102  */
00103 static void TwInterrupt(void *arg)
00104 {
00105     register u_int twsr = inr(TWI_SR) & (TWI_NACK | TWI_RXRDY | TWI_TXRDY | TWI_TXCOMP);;   
00106 
00107     /* Transmission is complete, signal waiting threads */
00108     if (twsr & TWI_TXCOMP) {
00109         outr(TWI_IDR, 0xFFFFFFFF);
00110         NutEventPostFromIrq(&tw_mm_que);
00111     }
00112     
00113     if (twsr & TWI_RXRDY) {
00114         if (tw_mr_idx < tw_mr_siz) {
00115             tw_mr_buf[tw_mr_idx++] = inb(TWI_RHR);
00116             /* The last byte will follow, just set the stop condition */
00117             if (tw_mr_idx == tw_mr_siz - 1) {
00118                 outr(TWI_CR, TWI_STOP);
00119             }
00120                 
00121             if (tw_mr_idx == tw_mr_siz) {
00122                 /* Last byte received. Send stop condition and set IRQs */
00123                 outr(TWI_IDR, TWI_RXRDY);
00124                 outr(TWI_IER, TWI_TXCOMP);
00125             }
00126         } 
00127     }
00128     
00129     if (twsr & TWI_TXRDY) {
00130         if (tw_mt_idx < tw_mt_len) {
00131             outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00132             /* Last byte? No bytes to read? So send stop condition else if bytes to read switch to read mode */
00133             if (tw_mt_idx == tw_mt_len) {
00134                 if (tw_mr_siz == 0) {
00135                     outr(TWI_CR, TWI_STOP);
00136                     outr(TWI_IDR, TWI_TXRDY);
00137                     outr(TWI_IER, TWI_TXCOMP);
00138                 } else {
00139                     /* Ok, now switch to read mode and send second start condition */
00140                     outr(TWI_MMR, inb(TWI_MMR) | TWI_MREAD);
00141                     outr(TWI_CR,  TWI_START | (tw_mr_siz == 1) ? TWI_STOP : 0);
00142                     outr(TWI_IDR, TWI_TXRDY);
00143                     outr(TWI_IER, TWI_RXRDY);
00144                 }
00145             }
00146         } 
00147     }
00148     
00149     /* We got a nack, stop transmission and wait for TWI_TXCOMP */
00150     if (twsr & TWI_NACK) {;
00151         /* send stop condition and wake up threads */
00152         outr(TWI_CR, TWI_STOP);
00153         tw_mm_err = TWERR_DATA_NACK;
00154         tw_mt_idx = 0;
00155         tw_mt_len = 0;
00156         tw_mr_siz = 0;
00157         outr(TWI_IDR, 0xFFFFFFFF);
00158         /* Wake up the application. */
00159         NutEventPostFromIrq(&tw_mm_que);
00160     }
00161 }
00162 
00189 int TwMasterTransact(u_char sla, CONST void *txdata, u_short txlen, void *rxdata, u_short rxsiz, u_long tmo)
00190 {
00191     int rc = -1;
00192 
00193     /* This routine is marked reentrant, so lock the interface. */
00194     if(NutEventWait(&tw_mm_mutex, 500)) {
00195         tw_mm_err = TWERR_IF_LOCKED;
00196         NutEventPost(&tw_mm_mutex);
00197         return -1;
00198     }
00199     NutIrqEnable(&sig_TWI);
00200 
00201     NutEnterCritical();
00202     /* Set all parameters for master mode. */
00203     tw_mm_sla = sla;
00204     tw_mm_err = 0;
00205     tw_mt_len = txlen;
00206     tw_mt_idx = 0;
00207     tw_mt_buf = txdata;
00208     tw_mr_siz = rxsiz;
00209     tw_mr_buf = rxdata;
00210     tw_mr_idx = 0;
00211 
00212     if ((tw_mt_len == 0) && (tw_mr_siz == 0)) return -1;
00213 
00214     /* Set slave address enable interrupts and start transmission */
00215     
00216     outr(TWI_MMR, (tw_mm_sla << 16) | (tw_mt_len == 0 ? TWI_MREAD : 0));
00217     
00218     /* Enable interrupts depending on read / write direction and data size */     
00219     if (tw_mt_len == 0) {  
00220         outr(TWI_IDR, TWI_TXRDY | TWI_TXCOMP);
00221         outr(TWI_IER, TWI_RXRDY | TWI_NACK);
00222     } else {
00223         outr(TWI_IDR, TWI_RXRDY);
00224         if ((tw_mt_len == 1) && (tw_mr_siz == 0)) {
00225             outr(TWI_IDR, TWI_TXRDY);
00226             outr(TWI_IER, TWI_TXCOMP);
00227         } else {            
00228             outr(TWI_IER, TWI_TXRDY);
00229             outr(TWI_IDR, TWI_TXCOMP);
00230         }
00231         outr(TWI_IER, TWI_NACK);        
00232     }
00233 
00234     /* Now start transmission if we have any data */
00235     if (tw_mt_len > 0) {
00236         outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00237     }     
00238     
00239     /* Send start condition. If read / write only one byte send stop as well */
00240     outr(TWI_CR, TWI_START | (((tw_mt_len == 1) && (tw_mr_siz == 0)) || 
00241                               ((tw_mt_len == 0) && (tw_mr_siz == 1))) ? TWI_STOP : 0);
00242         
00243     NutExitCritical();
00244         
00245     /* Wait for master transmission to be done. */
00246     rc = -1;
00247     if (NutEventWait(&tw_mm_que, tmo)) {
00248         tw_mm_error = TWERR_TIMEOUT;
00249     } else {
00250         NutEnterCritical();
00251         if (tw_mm_err) {
00252             tw_mm_error = tw_mm_err;
00253         } else {
00254             rc = tw_mr_idx;
00255         }
00256         NutExitCritical();
00257     }
00258 
00259     NutIrqDisable(&sig_TWI);
00260     
00261     /* Release the interface. */
00262     NutEventPost(&tw_mm_mutex);
00263     
00264     return rc;
00265 }
00266 
00276 int TwMasterError(void)
00277 {
00278     int rc = (int) tw_mm_error;
00279     tw_mm_error = 0;
00280     return rc;
00281 }
00282 
00298 int TwIOCtl(int req, void *conf)
00299 {
00300     int rc = 0;
00301     unsigned int cldiv, ckdiv;     
00302     unsigned int twi_clk;
00303     switch (req) {
00304 
00305     case TWI_SETSPEED:
00306         ckdiv=1 ;
00307         twi_clk = *((u_long *) conf);
00308 
00309         if (twi_clk > 400000) return -1;
00310         
00311         /*
00312          * CLDIV = ((Tlow x 2^CKDIV) -3) x Tmck
00313          * CHDIV = ((THigh x 2^CKDIV) -3) x Tmck
00314          * Only CLDIV is computed since CLDIV = CHDIV (50% duty cycle) 
00315          */
00316 
00317         while ((cldiv = ((NutGetCpuClock() / (2*twi_clk))-3 ) / (1 << ckdiv)) > 255) {
00318             ckdiv++;
00319         }
00320 
00321         /* BUG 41.2.7.1, datasheet SAM7X256  p. 626 */
00322         if (cldiv * (2 << ckdiv) > 8191) return -1; 
00323         
00324         outr(TWI_CWGR, (ckdiv << 16) | ((u_int) cldiv << 8) | (u_int) cldiv);
00325         break;
00326 
00327     case TWI_GETSPEED:
00328         ckdiv=1 ;
00329         twi_clk = *((u_long *) conf);
00330         
00331         cldiv = inr(TWI_CWGR) & 0x000000FF;
00332         ckdiv = (inr(TWI_CWGR) >> 16) & 0x00000007;
00333             
00334         *((u_long *) conf) = NutGetCpuClock() * ((cldiv * 2 << ckdiv) - 3);
00335         break;
00336 
00337     case TWI_GETSTATUS:
00338         break;
00339         
00340     case TWI_SETSTATUS:
00341         break;
00342 
00343     default:
00344         rc = -1;
00345         break;
00346     }
00347     return rc;
00348 }
00349 
00362 int TwInit(u_char sla)
00363 {
00364     u_long speed = 2400;
00365 
00366     if (NutRegisterIrqHandler(&sig_TWI, TwInterrupt, 0)) {
00367         return -1;
00368     }
00369 
00370     outr(TWI_PIO_ASR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Set TWD and TWCK as peripheral line
00371     outr(TWI_PIO_PDR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Let periperal control the PIO lines
00372     
00373     outr(TWI_PIO_MDER, _BV(TWI_TWD) | _BV(TWI_TWCK)); // Enabled OpenDrain output on both lines
00374     
00375     outr(PMC_PCER, _BV(TWI_ID));              // Enable TWI clock in PMC
00376     
00377     outr(TWI_IDR, 0xFFFFFFFF);                // Disable all interrupts 
00378     outr(TWI_CR, TWI_SWRST);                  // Reset bus
00379     outr(TWI_CR, TWI_MSEN | TWI_SVDIS);       // Enable master mode
00380     
00381     TwIOCtl(TWI_SETSPEED, &speed);
00382 
00383     /* Initialize mutex semaphores. */
00384     NutEventPost(&tw_mm_mutex);
00385 
00386     return 0;
00387 }

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