ih_timer2_comp.c

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00001 /*
00002  * Copyright (C) 2001-2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00077 #include <dev/irqreg.h>
00078 
00079 #if defined(MCU_AT90CAN128) || defined(MCU_ATMEGA2561)
00080 #define INT_MASK_REG    TIMSK2
00081 #define INT_STATUS_REG  TIFR2
00082 #define INT_ENABLE_BIT  OCIE2A
00083 #define INT_STATUS_BIT  OCF2A
00084 #define INT_PRIORITY    8
00085 #else
00086 #define INT_MASK_REG    TIMSK
00087 #define INT_STATUS_REG  TIFR
00088 #define INT_ENABLE_BIT  OCIE2
00089 #define INT_STATUS_BIT  OCF2
00090 #define INT_PRIORITY    8
00091 #endif
00092 
00097 
00098 static int AvrTimer2CompIrqCtl(int cmd, void *param);
00099 
00100 IRQ_HANDLER sig_OUTPUT_COMPARE2 = {
00101 #ifdef NUT_PERFMON
00102     0,                          /* Interrupt counter, ir_count. */
00103 #endif
00104     NULL,                       /* Passed argument, ir_arg. */
00105     NULL,                       /* Handler subroutine, ir_handler. */
00106     AvrTimer2CompIrqCtl         /* Interrupt control, ir_ctl. */
00107 };
00108 
00124 static int AvrTimer2CompIrqCtl(int cmd, void *param)
00125 {
00126     int rc = 0;
00127     u_int *ival = (u_int *) param;
00128     int enabled = bit_is_set(INT_MASK_REG, INT_ENABLE_BIT);
00129 
00130     /* Disable interrupt. */
00131     cbi(INT_MASK_REG, INT_ENABLE_BIT);
00132 
00133     switch (cmd) {
00134     case NUT_IRQCTL_INIT:
00135         enabled = 0;
00136     case NUT_IRQCTL_CLEAR:
00137         /* Clear any pending interrupt. */
00138         outb(INT_STATUS_REG, _BV(INT_STATUS_BIT));
00139         break;
00140     case NUT_IRQCTL_STATUS:
00141         if (bit_is_set(INT_STATUS_REG, INT_STATUS_BIT)) {
00142             *ival = 1;
00143         } else {
00144             *ival = 0;
00145         }
00146         if (enabled) {
00147             *ival |= 0x80;
00148         }
00149         break;
00150     case NUT_IRQCTL_ENABLE:
00151         enabled = 1;
00152         break;
00153     case NUT_IRQCTL_DISABLE:
00154         enabled = 0;
00155         break;
00156     case NUT_IRQCTL_GETPRIO:
00157         *ival = INT_PRIORITY;
00158         break;
00159 #ifdef NUT_PERFMON
00160     case NUT_IRQCTL_GETCOUNT:
00161         *ival = (u_int) sig_OUTPUT_COMPARE2.ir_count;
00162         sig_OUTPUT_COMPARE2.ir_count = 0;
00163         break;
00164 #endif
00165     default:
00166         rc = -1;
00167         break;
00168     }
00169 
00170     /* Enable interrupt. */
00171     if (enabled) {
00172         sbi(INT_MASK_REG, INT_ENABLE_BIT);
00173     }
00174     return rc;
00175 }
00176 
00180 #ifdef __IMAGECRAFT__
00181 #ifdef ATMega2561
00182 #pragma interrupt_handler SIG_OUTPUT_COMPARE2:iv_TIMER2_COMPA
00183 #else
00184 #pragma interrupt_handler SIG_OUTPUT_COMPARE2:iv_TIMER2_COMP
00185 #endif
00186 NUTSIGNAL(SIG_OUTPUT_COMPARE2, sig_OUTPUT_COMPARE2)
00187 #else
00188 #if defined(MCU_ATMEGA2561)
00189 NUTSIGNAL(SIG_OUTPUT_COMPARE2A, sig_OUTPUT_COMPARE2)
00190 #else
00191 NUTSIGNAL(SIG_OUTPUT_COMPARE2, sig_OUTPUT_COMPARE2)
00192 #endif
00193 #endif
00194 

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