at91_pmc.h

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00001 #ifndef _ARCH_ARM_AT91_PMC_H_
00002 #define _ARCH_ARM_AT91_PMC_H_
00003 
00004 /*
00005  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00006  *
00007  * Redistribution and use in source and binary forms, with or without
00008  * modification, are permitted provided that the following conditions
00009  * are met:
00010  *
00011  * 1. Redistributions of source code must retain the above copyright
00012  *    notice, this list of conditions and the following disclaimer.
00013  * 2. Redistributions in binary form must reproduce the above copyright
00014  *    notice, this list of conditions and the following disclaimer in the
00015  *    documentation and/or other materials provided with the distribution.
00016  * 3. Neither the name of the copyright holders nor the names of
00017  *    contributors may be used to endorse or promote products derived
00018  *    from this software without specific prior written permission.
00019  *
00020  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00021  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00022  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00023  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00024  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00025  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00026  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00027  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00028  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00029  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00030  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00031  * SUCH DAMAGE.
00032  *
00033  * For additional information see http://www.ethernut.de/
00034  */
00035 
00072 
00075 #define PMC_SCER_OFF                0x00000000  
00076 #define PMC_SCER    (PMC_BASE + PMC_SCER_OFF)   
00077 #define PMC_SCDR_OFF                0x00000004  
00078 #define PMC_SCDR    (PMC_BASE + PMC_SCDR_OFF)   
00079 #define PMC_SCSR_OFF                0x00000008  
00080 #define PMC_SCSR    (PMC_BASE + PMC_SCSR_OFF)   
00082 #define PMC_PCK                     0x00000001  
00083 #define PMC_UHP                     0x00000040  
00084 #define PMC_UDP                     0x00000080  
00085 #define PMC_PCK0                    0x00000100  
00086 #define PMC_PCK1                    0x00000200  
00087 #define PMC_PCK2                    0x00000400  
00088 #define PMC_PCK3                    0x00000800  
00090 
00091 
00093 #define PMC_PCER_OFF                0x00000010  
00094 #define PMC_PCER    (PMC_BASE + PMC_PCER_OFF)   
00095 #define PMC_PCDR_OFF                0x00000014  
00096 #define PMC_PCDR    (PMC_BASE + PMC_PCDR_OFF)   
00097 #define PMC_PCSR_OFF                0x00000018  
00098 #define PMC_PCSR    (PMC_BASE + PMC_PCSR_OFF)   
00100 
00101 
00103 #define CKGR_MOR_OFF                0x00000020  
00104 #define CKGR_MOR    (PMC_BASE + CKGR_MOR_OFF)   
00106 #define CKGR_MOSCEN                 0x00000001  
00107 #define CKGR_OSCBYPASS              0x00000002  
00108 #define CKGR_OSCOUNT                0x0000FF00  
00109 #define CKGR_OSCOUNT_LSB                    8   
00111 
00112 
00114 #define CKGR_MCFR_OFF               0x00000024  
00115 #define CKGR_MCFR   (PMC_BASE + CKGR_MCFR_OFF)  
00117 #define CKGR_MAINF                  0x0000FFFF  
00118 #define CKGR_MAINF_OFF                      0   
00119 #define CKGR_MAINRDY                0x00010000  
00121 
00122 
00124 #if defined (MCU_AT91SAM9260)
00125 #define CKGR_PLLAR_OFF              0x00000028  
00126 #define CKGR_PLLAR  (PMC_BASE + CKGR_PLLAR_OFF) 
00127 #define CKGR_PLLBR_OFF              0x0000002C  
00128 #define CKGR_PLLBR  (PMC_BASE + CKGR_PLLBR_OFF) 
00129 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
00130 #define CKGR_PLLR_OFF               0x0000002C  
00131 #define CKGR_PLLR   (PMC_BASE + CKGR_PLLR_OFF)  
00132 #endif
00133 
00134 #define CKGR_DIV                    0x000000FF  
00135 #define CKGR_DIV_LSB                        0   
00136 #define CKGR_DIV_0                  0x00000000  
00137 #define CKGR_DIV_BYPASS             0x00000001  
00138 #define CKGR_PLLCOUNT               0x00003F00  
00139 #define CKGR_PLLCOUNT_LSB                   8   
00140 #define CKGR_OUT                    0x0000C000  
00141 #define CKGR_OUT_0                  0x00000000  
00142 #define CKGR_OUT_1                  0x00004000  
00143 #define CKGR_OUT_2                  0x00008000  
00144 #define CKGR_OUT_3                  0x0000C000  
00145 #define CKGR_MUL                    0x07FF0000  
00146 #define CKGR_MUL_LSB                        16  
00147 #define CKGR_USBDIV                 0x30000000  
00148 #define CKGR_USBDIV_1               0x00000000  
00149 #define CKGR_USBDIV_2               0x10000000  
00150 #define CKGR_USBDIV_4               0x20000000  
00152 
00153 
00155 #define PMC_MCKR_OFF                0x00000030  
00156 #define PMC_MCKR    (PMC_BASE + PMC_MCKR_OFF)   
00157 #define PMC_ACKR_OFF                0x00000034  
00158 #define PMC_ACKR    (PMC_BASE + PMC_ACKR_OFF)   
00159 #define PMC_PCKR0_OFF               0x00000040  
00160 #define PMC_PCKR0   (PMC_BASE + PMC_PCKR0_OFF)  
00161 #define PMC_PCKR1_OFF               0x00000044  
00162 #define PMC_PCKR1   (PMC_BASE + PMC_PCKR1_OFF)  
00163 #define PMC_PCKR2_OFF               0x00000048  
00164 #define PMC_PCKR2   (PMC_BASE + PMC_PCKR2_OFF)  
00165 #define PMC_PCKR3_OFF               0x0000004C  
00166 #define PMC_PCKR3   (PMC_BASE + PMC_PCKR3_OFF)  
00168 #define PMC_CSS                     0x00000003  
00169 #define PMC_CSS_SLOW_CLK            0x00000000  
00170 #define PMC_CSS_MAIN_CLK            0x00000001  
00171 #if defined (MCU_AT91SAM9260)
00172 #define PMC_CSS_PLLA_CLK            0x00000002  
00173 #define PMC_CSS_PLLB_CLK            0x00000003  
00174 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
00175 #define PMC_CSS_PLL_CLK             0x00000003  
00176 #endif
00177 #define PMC_PRES                    0x0000001C  
00178 #define PMC_PRES_LSB                        2   
00179 #define PMC_PRES_CLK                0x00000000  
00180 #define PMC_PRES_CLK_2              0x00000004  
00181 #define PMC_PRES_CLK_4              0x00000008  
00182 #define PMC_PRES_CLK_8              0x0000000C  
00183 #define PMC_PRES_CLK_16             0x00000010  
00184 #define PMC_PRES_CLK_32             0x00000014  
00185 #define PMC_PRES_CLK_64             0x00000018  
00186 #if defined (MCU_AT91SAM9260)
00187 #define PMC_MDIV                    0x00000300  
00188 #define PMC_MDIV_1                  0x00000000  
00189 #define PMC_MDIV_2                  0x00000100  
00190 #define PMC_MDIV_4                  0x00000200  
00191 #endif
00192 
00196 #define PMC_IER_OFF                 0x00000060  
00197 #define PMC_IER     (PMC_BASE + PMC_IER_OFF)    
00198 #define PMC_IDR_OFF                 0x00000064  
00199 #define PMC_IDR     (PMC_BASE + PMC_IDR_OFF)    
00200 #define PMC_SR_OFF                  0x00000068  
00201 #define PMC_SR      (PMC_BASE + PMC_SR_OFF)     
00202 #define PMC_IMR_OFF                 0x0000006C  
00203 #define PMC_IMR     (PMC_BASE + PMC_IMR_OFF)    
00205 #define PMC_MOSCS                   0x00000001  
00206 #if defined (MCU_AT91SAM9260)
00207 #define PMC_LOCKA                   0x00000002  
00208 #define PMC_LOCKB                   0x00000004  
00209 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
00210 #define PMC_LOCK                    0x00000004  
00211 #endif
00212 #define PMC_MCKRDY                  0x00000008  
00213 #define PMC_OSC_SEL                 0x00000080  
00214 #define PMC_PCKRDY0                 0x00000100  
00215 #define PMC_PCKRDY1                 0x00000200  
00216 #define PMC_PCKRDY2                 0x00000400  
00217 #define PMC_PCKRDY3                 0x00000800  
00219 
00220 
00223 #endif                          /* _ARCH_ARM_AT91_PMC_H_ */

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