debug_at91.c

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00001 /*
00002  * Copyright (C) 2001-2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00087 #include <cfg/os.h>
00088 #include <cfg/clock.h>
00089 
00090 #include <dev/debug.h>
00091 #include <sys/device.h>
00092 #include <sys/file.h>
00093 #include <sys/timer.h>
00094 
00095 #define static
00096 
00101 
00102 #if defined(DBGU_BASE)
00103 static NUTFILE dbgfile;
00104 #else
00105 static NUTFILE dbgfile0;
00106 static NUTFILE dbgfile1;
00107 #endif
00108 
00109 #if defined(DBGU_BASE)
00110 
00117 static int DebugIOCtl(NUTDEVICE * dev, int req, void *conf)
00118 {
00119     if(req == UART_SETSPEED) {
00120 #if defined(AT91_PLL_MAINCK)
00121         outr(DBGU_BRGR, (At91GetMasterClock() / (8 * (*((u_long *)conf))) + 1) / 2);
00122 #else
00123         outr(DBGU_BRGR, (NutGetCpuClock() / (8 * (*((u_long *)conf))) + 1) / 2);
00124 #endif
00125         return 0;
00126     }
00127     return -1;
00128 }
00129 
00135 static int DebugInit(NUTDEVICE * dev)
00136 {
00137 #if defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
00138     /* Disable GPIO on UART tx/rx pins. */
00139     #if defined (MCU_AT91SAM7X256)
00140        outr(PIOA_PDR, _BV(27) | _BV(28));
00141     #elif defined (MCU_AT91SAM7S256)
00142        outr(PIOA_PDR, _BV(9) | _BV(10));
00143     #endif
00144     /* Reset UART. */
00145     outr(DBGU_CR, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
00146     /* Disable all UART interrupts. */
00147     outr(DBGU_IDR, 0xFFFFFFFF);
00148     /* Set UART baud rate generator register. */
00149     outr(DBGU_BRGR, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
00150     /* Set UART mode to 8 data bits, no parity and 1 stop bit. */
00151     outr(DBGU_MR, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
00152     /* Enable UART receiver and transmitter. */
00153     outr(DBGU_CR, US_RXEN | US_TXEN);
00154 #endif
00155 
00156     return 0;
00157 }
00158 
00159 #else /* !DBGU_BASE */
00160 
00168 static int Debug0IOCtl(NUTDEVICE * dev, int req, void *conf)
00169 {
00170     if(req == UART_SETSPEED) {
00171         outr(US0_BRGR, (NutGetCpuClock() / (8 * (*((u_long *)conf))) + 1) / 2);
00172         return 0;
00173     }
00174     return -1;
00175 }
00176 
00184 static int Debug1IOCtl(NUTDEVICE * dev, int req, void *conf)
00185 {
00186     if(req == UART_SETSPEED) {
00187         outr(US1_BRGR, (NutGetCpuClock() / (8 * (*((u_long *)conf))) + 1) / 2);
00188         return 0;
00189     }
00190     return -1;
00191 }
00192 
00198 static int Debug0Init(NUTDEVICE * dev)
00199 {
00200 #if defined (MCU_AT91R40008)
00201     /* Enable UART clock. */
00202     outr(PS_PCER, _BV(US0_ID));
00203     /* Disable GPIO on UART tx/rx pins. */
00204     outr(PIO_PDR, _BV(14) | _BV(15));
00205 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM9260) || defined (MCU_AT91SAM7S256)
00206     /* Enable UART clock. */
00207     outr(PMC_PCER, _BV(US0_ID));
00208     /* Disable GPIO on UART tx/rx pins. */
00209     #if defined (MCU_AT91SAM7S256)
00210        outr(PIOA_PDR, _BV(5) | _BV(6));
00211     #else
00212        outr(PIOA_PDR, _BV(0) | _BV(1));
00213     #endif
00214 #endif
00215     /* Reset UART. */
00216     outr(US0_CR, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
00217     /* Disable all UART interrupts. */
00218     outr(US0_IDR, 0xFFFFFFFF);
00219 #if defined (US0_RCR) && defined(US0_TCR)
00220     /* Clear UART counter registers. */
00221     outr(US0_RCR, 0);
00222     outr(US0_TCR, 0);
00223 #endif
00224     /* Set UART baud rate generator register. */
00225     outr(US0_BRGR, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
00226     /* Set UART mode to 8 data bits, no parity and 1 stop bit. */
00227     outr(US0_MR, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
00228     /* Enable UART receiver and transmitter. */
00229     outr(US0_CR, US_RXEN | US_TXEN);
00230 
00231     return 0;
00232 }
00233 
00239 static int Debug1Init(NUTDEVICE * dev)
00240 {
00241 #if defined (MCU_AT91R40008)
00242     /* Enable UART clock. */
00243     outr(PS_PCER, _BV(US1_ID));
00244     /* Disable GPIO on UART tx/rx pins. */
00245     outr(PIO_PDR, _BV(21) | _BV(22));
00246 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM9260) || defined (MCU_AT91SAM7S256)
00247     /* Enable UART clock. */
00248     outr(PMC_PCER, _BV(US1_ID));
00249     /* Disable GPIO on UART tx/rx pins. */
00250     #if defined (MCU_AT91SAM7S256)
00251        outr(PIOA_PDR, _BV(21) | _BV(22));
00252     #else
00253        outr(PIOA_PDR, _BV(5) | _BV(6));
00254     #endif
00255 #endif
00256     /* Reset UART. */
00257     outr(US1_CR, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
00258     /* Disable all UART interrupts. */
00259     outr(US1_IDR, 0xFFFFFFFF);
00260 #if defined (US1_RCR) && defined(US1_TCR)
00261     /* Clear UART counter registers. */
00262     outr(US1_RCR, 0);
00263     outr(US1_TCR, 0);
00264 #endif
00265     /* Set UART baud rate generator register. */
00266     outr(US1_BRGR, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
00267     /* Set UART mode to 8 data bits, no parity and 1 stop bit. */
00268     outr(US1_MR, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
00269     /* Enable UART receiver and transmitter. */
00270     outr(US1_CR, US_RXEN | US_TXEN);
00271 
00272     return 0;
00273 }
00274 
00275 #endif
00276 
00277 
00284 static void DebugPut(CONST NUTDEVICE * dev, char ch)
00285 {
00286     while ((inr(dev->dev_base + US_CSR_OFF) & US_TXRDY) == 0);
00287     outr(dev->dev_base + US_THR_OFF, ch);
00288     if (ch == '\n') {
00289         DebugPut(dev, '\r');
00290     }
00291 }
00292 
00301 static int DebugWrite(NUTFILE * fp, CONST void *buffer, int len)
00302 {
00303     int c = len;
00304     CONST char *cp = buffer;
00305 
00306     while (c--) {
00307         DebugPut(fp->nf_dev, *cp++);
00308     }
00309     return len;
00310 }
00311 
00317 static NUTFILE *DebugOpen(NUTDEVICE * dev, CONST char *name, int mode, int acc)
00318 {
00319     NUTFILE *fp = (NUTFILE *) (dev->dev_dcb);
00320 
00321     fp->nf_next = 0;
00322     fp->nf_dev = dev;
00323     fp->nf_fcb = 0;
00324 
00325     return fp;
00326 }
00327 
00333 static int DebugClose(NUTFILE * fp)
00334 {
00335     return 0;
00336 }
00337 
00338 #if defined(DBGU_BASE)
00339 
00343 NUTDEVICE devDebug = {
00344     0,                          
00345     {'d', 'b', 'g', 'u', 0, 0, 0, 0, 0}
00346     ,                           
00347     0,                          
00348     DBGU_BASE,                  
00349     0,                          
00350     0,                          
00351     &dbgfile,                   
00352     DebugInit,                  
00353     DebugIOCtl,                 
00354     0,                          
00355     DebugWrite,                 
00356     DebugOpen,                  
00357     DebugClose,                 
00358     0                           
00359 };
00360 
00361 #else   /* !DBGU_BASE */
00362 
00366 NUTDEVICE devDebug0 = {
00367     0,                          
00368     {'u', 'a', 'r', 't', '0', 0, 0, 0, 0}
00369     ,                           
00370     0,                          
00371     USART0_BASE,                
00372     0,                          
00373     0,                          
00374     &dbgfile0,                  
00375     Debug0Init,                 
00376     Debug0IOCtl,                
00377     0,                          
00378     DebugWrite,                 
00379     DebugOpen,                  
00380     DebugClose,                 
00381     0                           
00382 };
00383 
00387 NUTDEVICE devDebug1 = {
00388     0,                          
00389     {'u', 'a', 'r', 't', '1', 0, 0, 0, 0}
00390     ,                           
00391     0,                          
00392     USART1_BASE,                
00393     0,                          
00394     0,                          
00395     &dbgfile1,                  
00396     Debug1Init,                 
00397     Debug1IOCtl,                
00398     0,                          
00399     DebugWrite,                 
00400     DebugOpen,                  
00401     DebugClose,                 
00402     0                           
00403 };
00404 
00405 #endif  /* !DBGU_BASE */
00406 

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