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00067 #include <cfg/clock.h>
00068
00069 #include <sys/atom.h>
00070 #include <sys/event.h>
00071 #include <sys/timer.h>
00072
00073 #include <dev/irqreg.h>
00074
00075 #include <dev/usartat91.h>
00076
00081
00082
00083 #define ASCII_XON 0x11
00084
00085 #define ASCII_XOFF 0x13
00086
00087
00088 #define XON_PENDING 0x10
00089
00090 #define XOFF_PENDING 0x20
00091
00092 #define XOFF_SENT 0x40
00093
00094 #define XOFF_RCVD 0x80
00095
00096
00100 static ureg_t rx_errors;
00101
00105 static ureg_t flow_control;
00106
00110 static ureg_t tx_aframe;
00111
00112 #ifdef UART_HDX_BIT
00113
00114 #ifdef UART_HDX_FLIP_BIT
00115 #define UART_HDX_TX cbi
00116 #define UART_HDX_RX sbi
00117 #else
00118 #define UART_HDX_TX sbi
00119 #define UART_HDX_RX cbi
00120 #endif
00121 #endif
00122
00123
00124 #ifdef UART_HDX_BIT
00125
00131 static ureg_t hdx_control;
00132 #endif
00133
00134 #ifdef UART_RTS_BIT
00135
00141 static ureg_t rts_control;
00142 #endif
00143
00144 #ifdef UART_CTS_BIT
00145
00151 static ureg_t cts_sense;
00152 #endif
00153
00154 #ifdef UART_CTS_BIT
00155
00165 static void At91UsartCts(void *arg)
00166 {
00167
00168
00169
00170
00171 }
00172 #endif
00173
00174 #ifdef UART_HDX_BIT
00175
00176
00177
00178
00179
00180
00181
00182
00183
00184
00185
00186 static void At91UsartTxEmpty(RINGBUF *rbf)
00187 {
00188
00189
00190
00191
00192 if (hdx_control && rbf->rbf_cnt == 0) {
00193
00194 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
00195 }
00196 }
00197 #endif
00198
00199
00200
00201
00202
00203
00204 static void At91UsartTxReady(RINGBUF *rbf)
00205 {
00206 register u_char *cp = rbf->rbf_tail;
00207
00208
00209
00210
00211 if (flow_control & (XON_PENDING | XOFF_PENDING)) {
00212 if (flow_control & XON_PENDING) {
00213 outr(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00214 flow_control |= XOFF_SENT;
00215 } else {
00216 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
00217 flow_control &= ~XOFF_SENT;
00218 }
00219 flow_control &= ~(XON_PENDING | XOFF_PENDING);
00220 return;
00221 }
00222
00223 if (flow_control & XOFF_RCVD) {
00224
00225
00226
00227
00228 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00229 return;
00230 }
00231
00232 if (rbf->rbf_cnt) {
00233
00234 #ifdef UART_CTS_BIT
00235
00236
00237
00238
00239 if (cts_sense && bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00240 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00241 sbi(EIMSK, UART_CTS_BIT);
00242 return;
00243 }
00244 #endif
00245 rbf->rbf_cnt--;
00246
00247
00248
00249
00250 if (tx_aframe) {
00251 outr(USARTn_BASE + US_CR_OFF, US_SENDA);
00252 }
00253
00254
00255
00256
00257 outr(USARTn_BASE + US_THR_OFF, *cp);
00258
00259
00260
00261
00262 if (++cp == rbf->rbf_last) {
00263 cp = rbf->rbf_start;
00264 }
00265 rbf->rbf_tail = cp;
00266 if (rbf->rbf_cnt == rbf->rbf_lwm) {
00267 NutEventPostFromIrq(&rbf->rbf_que);
00268 }
00269 }
00270
00271
00272
00273
00274 else {
00275 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00276 rbf->rbf_cnt = 0;
00277 NutEventPostFromIrq(&rbf->rbf_que);
00278 }
00279 }
00280
00281
00282
00283
00284
00285
00286
00287
00288
00289 static void At91UsartRxReady(RINGBUF *rbf)
00290 {
00291 register size_t cnt;
00292 register u_char ch;
00293
00294
00295
00296
00297
00298 ch = inb(USARTn_BASE + US_RHR_OFF);
00299
00300
00301 rx_errors |= inr(USARTn_BASE + US_CSR_OFF) & (US_OVRE | US_FRAME | US_PARE);
00302
00303
00304
00305
00306
00307
00308 if (flow_control) {
00309
00310 if (ch == ASCII_XOFF) {
00311 outr(USARTn_BASE + US_IDR_OFF, US_TXRDY);
00312 flow_control |= XOFF_RCVD;
00313 return;
00314 }
00315
00316 else if (ch == ASCII_XON) {
00317 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
00318 flow_control &= ~XOFF_RCVD;
00319 return;
00320 }
00321 }
00322
00323
00324
00325
00326 cnt = rbf->rbf_cnt;
00327 if (cnt >= rbf->rbf_siz) {
00328 rx_errors |= US_OVRE;
00329 return;
00330 }
00331
00332
00333 if (cnt++ == 0){
00334 NutEventPostFromIrq(&rbf->rbf_que);
00335 }
00336
00337
00338
00339
00340
00341 else if (flow_control) {
00342 if(cnt >= rbf->rbf_hwm) {
00343 if((flow_control & XOFF_SENT) == 0) {
00344 if (inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY) {
00345 outb(USARTn_BASE + US_THR_OFF, ASCII_XOFF);
00346 flow_control |= XOFF_SENT;
00347 flow_control &= ~XOFF_PENDING;
00348 } else {
00349 flow_control |= XOFF_PENDING;
00350 }
00351 }
00352 }
00353 }
00354
00355 #ifdef UART_RTS_BIT
00356
00357
00358
00359
00360 else if (rts_control && cnt >= rbf->rbf_hwm) {
00361 sbi(UART_RTS_PORT, UART_RTS_BIT);
00362 }
00363 #endif
00364
00365
00366
00367
00368 *rbf->rbf_head++ = ch;
00369 if (rbf->rbf_head == rbf->rbf_last) {
00370 rbf->rbf_head = rbf->rbf_start;
00371 }
00372
00373
00374 rbf->rbf_cnt = cnt;
00375 }
00376
00382 static void At91UsartInterrupt(void *arg)
00383 {
00384 USARTDCB *dcb = (USARTDCB *)arg;
00385 ureg_t csr = inr(USARTn_BASE + US_CSR_OFF);
00386
00387 if (csr & US_RXRDY) {
00388 At91UsartRxReady(&dcb->dcb_rx_rbf);
00389 }
00390 if (csr & US_TXRDY) {
00391 At91UsartTxReady(&dcb->dcb_tx_rbf);
00392 }
00393
00394 #ifdef UART_HDX_BIT
00395 if (csr & US_TXEMPTY) {
00396 At91UsartTxEmpty(&dcb->dcb_tx_rbf);
00397 }
00398 #endif
00399 }
00400
00407 static void At91UsartEnable(void)
00408 {
00409 NutEnterCritical();
00410
00411
00412 outr(USARTn_BASE + US_CR_OFF, US_RXEN | US_TXEN);
00413
00414
00415 outr(USARTn_BASE + US_IER_OFF, US_RXRDY | US_TXRDY);
00416 NutIrqEnable(&SIG_UART);
00417
00418 #ifdef UART_HDX_BIT
00419 if (hdx_control) {
00420
00421 sbi(UCSRnB, TXCIE);
00422 }
00423 #endif
00424
00425 NutExitCritical();
00426 }
00427
00431 static void At91UsartDisable(void)
00432 {
00433
00434
00435
00436 NutEnterCritical();
00437 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
00438 NutExitCritical();
00439
00440
00441
00442
00443 NutDelay(10);
00444
00445
00446
00447
00448 outr(USARTn_BASE + US_CR_OFF, US_RXDIS | US_TXDIS);
00449 }
00450
00459 static u_long At91UsartGetSpeed(void)
00460 {
00461 ureg_t cs = inr(USARTn_BASE + US_MR_OFF);
00462 u_long clk;
00463
00464 #if defined(AT91_PLL_MAINCK)
00465 clk = At91GetMasterClock();
00466 #else
00467 clk = NutGetCpuClock();
00468 #endif
00469 if ((cs & US_CLKS) == US_CLKS_MCK8) {
00470 clk /= 8;
00471 }
00472 else if ((cs & US_CLKS) != US_CLKS_MCK) {
00473 clk = 0;
00474 }
00475 return clk / (16UL * (inr(USARTn_BASE + US_BRGR_OFF) & 0xFFFF));
00476 }
00477
00488 static int At91UsartSetSpeed(u_long rate)
00489 {
00490 At91UsartDisable();
00491 #if defined(AT91_PLL_MAINCK)
00492 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (rate)) + 1) / 2);
00493 #else
00494 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (rate)) + 1) / 2);
00495 #endif
00496 At91UsartEnable();
00497
00498 return 0;
00499 }
00500
00509 static u_char At91UsartGetDataBits(void)
00510 {
00511 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00512
00513 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00514 val = 9;
00515 }
00516 else {
00517 val &= US_CHRL;
00518 if (val == US_CHRL_5) {
00519 val = 5;
00520 }
00521 else if (val == US_CHRL_6) {
00522 val = 6;
00523 }
00524 else if (val == US_CHRL_7) {
00525 val = 7;
00526 }
00527 else {
00528 val = 8;
00529 }
00530 }
00531 return (u_char)val;
00532 }
00533
00542 static int At91UsartSetDataBits(u_char bits)
00543 {
00544 ureg_t val = inr(USARTn_BASE + US_MR_OFF);
00545
00546 if (bits == 9) {
00547 val &= ~US_PAR;
00548 val |= US_PAR_MULTIDROP;
00549 }
00550 else {
00551 val &= ~US_CHRL;
00552 if (bits == 5) {
00553 val |= US_CHRL_5;
00554 }
00555 else if (bits == 6) {
00556 val |= US_CHRL_6;
00557 }
00558 else if (bits == 7) {
00559 val |= US_CHRL_7;
00560 }
00561 else if (bits == 8) {
00562 val |= US_CHRL_8;
00563 }
00564 }
00565
00566 At91UsartDisable();
00567 outr(USARTn_BASE + US_MR_OFF, val);
00568 At91UsartEnable();
00569
00570
00571
00572
00573 if (At91UsartGetDataBits() != bits) {
00574 return -1;
00575 }
00576 return 0;
00577 }
00578
00587 static u_char At91UsartGetParity(void)
00588 {
00589 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_PAR;
00590
00591 if ((val & US_PAR) == US_PAR_MULTIDROP) {
00592 val = 9;
00593 }
00594 else {
00595 if (val == US_PAR_ODD) {
00596 val = 1;
00597 }
00598 else if (val == US_PAR_EVEN) {
00599 val = 2;
00600 }
00601 else {
00602 val = 0;
00603 }
00604 }
00605 return (u_char)val;
00606 }
00607
00618 static int At91UsartSetParity(u_char mode)
00619 {
00620 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_PAR;
00621
00622 switch (mode) {
00623 case 0:
00624 val |= US_PAR_NO;
00625 break;
00626 case 1:
00627 val |= US_PAR_ODD;
00628 break;
00629 case 2:
00630 val |= US_PAR_EVEN;
00631 break;
00632 }
00633 At91UsartDisable();
00634 outr(USARTn_BASE + US_MR_OFF, val);
00635 At91UsartEnable();
00636
00637
00638
00639
00640 if (At91UsartGetParity() != mode) {
00641 return -1;
00642 }
00643 return 0;
00644 }
00645
00654 static u_char At91UsartGetStopBits(void)
00655 {
00656 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & US_NBSTOP;
00657 if (val == US_NBSTOP_1) {
00658 val = 1;
00659 }
00660 else if (val == US_NBSTOP_2) {
00661 val = 2;
00662 }
00663 else {
00664 val = 3;
00665 }
00666 return (u_char)val;
00667 }
00668
00677 static int At91UsartSetStopBits(u_char bits)
00678 {
00679 ureg_t val = inr(USARTn_BASE + US_MR_OFF) & ~US_NBSTOP;
00680
00681 switch(bits) {
00682 case 1:
00683 val |= US_NBSTOP_1;
00684 break;
00685 case 2:
00686 val |= US_NBSTOP_2;
00687 break;
00688 case 3:
00689 val |= US_NBSTOP_1_5;
00690 break;
00691 }
00692 At91UsartDisable();
00693 outr(USARTn_BASE + US_MR_OFF, val);
00694 At91UsartEnable();
00695
00696
00697
00698
00699 if (At91UsartGetStopBits() != bits) {
00700 return -1;
00701 }
00702 return 0;
00703 }
00704
00710 static u_long At91UsartGetStatus(void)
00711 {
00712 u_long rc = 0;
00713
00714
00715
00716
00717 if ((rx_errors & US_FRAME) != 0) {
00718 rc |= UART_FRAMINGERROR;
00719 }
00720 if ((rx_errors & US_OVRE) != 0) {
00721 rc |= UART_OVERRUNERROR;
00722 }
00723 if ((rx_errors & US_PARE) != 0) {
00724 rc |= UART_PARITYERROR;
00725 }
00726
00727
00728
00729
00730
00731 if (flow_control) {
00732 if (flow_control & XOFF_SENT) {
00733 rc |= UART_RXDISABLED;
00734 }
00735 if (flow_control & XOFF_RCVD) {
00736 rc |= UART_TXDISABLED;
00737 }
00738 }
00739 #ifdef UART_RTS_BIT
00740
00741
00742
00743 if (bit_is_set(UART_RTS_PORT, UART_RTS_BIT)) {
00744 rc |= UART_RTSDISABLED;
00745 if (rts_control) {
00746 rc |= UART_RXDISABLED;
00747 }
00748 } else {
00749 rc |= UART_RTSENABLED;
00750 }
00751 #endif
00752
00753 #ifdef UART_CTS_BIT
00754
00755
00756
00757 if (bit_is_set(UART_CTS_PIN, UART_CTS_BIT)) {
00758 rc |= UART_CTSDISABLED;
00759 if (cts_sense) {
00760 rc |= UART_RXDISABLED;
00761 }
00762 } else {
00763 rc |= UART_CTSENABLED;
00764 }
00765 #endif
00766
00767
00768
00769
00770
00771 if ((rc & UART_RXDISABLED) == 0) {
00772 rc |= UART_RXENABLED;
00773 }
00774 if ((rc & UART_TXDISABLED) == 0) {
00775 rc |= UART_TXENABLED;
00776 }
00777
00778
00779
00780
00781 if (tx_aframe) {
00782 rc |= UART_TXADDRFRAME;
00783 } else {
00784 rc |= UART_TXNORMFRAME;
00785 }
00786 return rc;
00787 }
00788
00796 static int At91UsartSetStatus(u_long flags)
00797 {
00798
00799
00800
00801 if (flow_control) {
00802
00803
00804 NutEnterCritical();
00805
00806
00807
00808
00809
00810 if (flags & UART_RXENABLED) {
00811 flow_control &= ~XOFF_SENT;
00812 } else if (flags & UART_RXDISABLED) {
00813 flow_control |= XOFF_SENT;
00814 }
00815
00816
00817
00818
00819
00820 if (flags & UART_TXENABLED) {
00821 flow_control &= ~XOFF_RCVD;
00822 } else if (flags & UART_TXDISABLED) {
00823 flow_control |= XOFF_RCVD;
00824 }
00825 NutExitCritical();
00826 }
00827 #ifdef UART_RTS_BIT
00828
00829
00830
00831 if (rts_control) {
00832 if (flags & UART_RXDISABLED) {
00833 sbi(UART_RTS_PORT, UART_RTS_BIT);
00834 }
00835 if (flags & UART_RXENABLED) {
00836 cbi(UART_RTS_PORT, UART_RTS_BIT);
00837 }
00838 }
00839 if (flags & UART_RTSDISABLED) {
00840 sbi(UART_RTS_PORT, UART_RTS_BIT);
00841 }
00842 if (flags & UART_RTSENABLED) {
00843 cbi(UART_RTS_PORT, UART_RTS_BIT);
00844 }
00845 #endif
00846
00847
00848
00849
00850 if (flags & UART_TXADDRFRAME) {
00851 tx_aframe = 1;
00852 }
00853 if (flags & UART_TXNORMFRAME) {
00854 tx_aframe = 0;
00855 }
00856
00857
00858
00859
00860 if (flags & UART_ERRORS) {
00861 outr(USARTn_BASE + US_CR_OFF, US_RSTSTA);
00862 }
00863
00864
00865
00866
00867 if ((At91UsartGetStatus() & ~UART_ERRORS) != flags) {
00868 return -1;
00869 }
00870 return 0;
00871 }
00872
00882 static u_char At91UsartGetClockMode(void)
00883 {
00884 u_char rc = 0;
00885
00886 return rc;
00887 }
00888
00900 static int At91UsartSetClockMode(u_char mode)
00901 {
00902
00903
00904
00905 if (At91UsartGetClockMode() != mode) {
00906 return -1;
00907 }
00908 return 0;
00909 }
00910
00919 static u_long At91UsartGetFlowControl(void)
00920 {
00921 u_long rc = 0;
00922
00923 if (flow_control) {
00924 rc |= USART_MF_XONXOFF;
00925 } else {
00926 rc &= ~USART_MF_XONXOFF;
00927 }
00928
00929 #ifdef UART_RTS_BIT
00930 if (rts_control) {
00931 rc |= USART_MF_RTSCONTROL;
00932 } else {
00933 rc &= ~USART_MF_RTSCONTROL;
00934 }
00935 #endif
00936
00937 #ifdef UART_CTS_BIT
00938 if (cts_sense) {
00939 rc |= USART_MF_CTSSENSE;
00940 } else {
00941 rc &= ~USART_MF_CTSSENSE;
00942 }
00943 #endif
00944
00945 #ifdef UART_HDX_BIT
00946 if (hdx_control) {
00947 rc |= USART_MF_HALFDUPLEX;
00948 } else {
00949 rc &= ~USART_MF_HALFDUPLEX;
00950 }
00951 #endif
00952
00953 return rc;
00954 }
00955
00966 static int At91UsartSetFlowControl(u_long flags)
00967 {
00968
00969
00970
00971 if (flags & USART_MF_XONXOFF) {
00972 if(flow_control == 0) {
00973 NutEnterCritical();
00974 flow_control = 1 | XOFF_SENT;
00975 NutExitCritical();
00976 }
00977 } else {
00978 NutEnterCritical();
00979 flow_control = 0;
00980 NutExitCritical();
00981 }
00982
00983 #ifdef UART_RTS_BIT
00984
00985
00986
00987 if (flags & USART_MF_RTSCONTROL) {
00988 sbi(UART_RTS_PORT, UART_RTS_BIT);
00989 sbi(UART_RTS_DDR, UART_RTS_BIT);
00990 rts_control = 1;
00991 } else if (rts_control) {
00992 rts_control = 0;
00993 cbi(UART_RTS_DDR, UART_RTS_BIT);
00994 }
00995 #endif
00996
00997 #ifdef UART_CTS_BIT
00998
00999
01000
01001 if (flags & USART_MF_CTSSENSE) {
01002
01003 if (NutRegisterIrqHandler(&UART_CTS_SIGNAL, At91UsartCts, 0)) {
01004 return -1;
01005 }
01006 sbi(UART_CTS_PORT, UART_CTS_BIT);
01007 cbi(UART_CTS_DDR, UART_CTS_BIT);
01008 cts_sense = 1;
01009 } else if (cts_sense) {
01010 cts_sense = 0;
01011
01012 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01013 cbi(UART_CTS_DDR, UART_CTS_BIT);
01014 }
01015 #endif
01016
01017 #ifdef UART_HDX_BIT
01018
01019
01020
01021 if (flags & USART_MF_HALFDUPLEX) {
01022
01023 if (NutRegisterIrqHandler(&sig_UART_TRANS, At91UsartTxComplete, &dcb_usart.dcb_rx_rbf)) {
01024 return -1;
01025 }
01026
01027 UART_HDX_RX(UART_HDX_PORT, UART_HDX_BIT);
01028 sbi(UART_HDX_DDR, UART_HDX_BIT);
01029 hdx_control = 1;
01030
01031 sbi(UCSRnB, TXCIE);
01032 } else if (hdx_control) {
01033 hdx_control = 0;
01034
01035 cbi(UCSRnB, TXCIE);
01036
01037 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01038 cbi(UART_HDX_DDR, UART_HDX_BIT);
01039 }
01040 #endif
01041
01042
01043
01044
01045 if (At91UsartGetFlowControl() != flags) {
01046 return -1;
01047 }
01048 return 0;
01049 }
01050
01058 static void At91UsartTxStart(void)
01059 {
01060 #ifdef UART_HDX_BIT
01061 if (hdx_control) {
01062
01063 UART_HDX_TX(UART_HDX_PORT, UART_HDX_BIT);
01064 }
01065 #endif
01066
01067 outr(USARTn_BASE + US_IER_OFF, US_TXRDY);
01068 }
01069
01078 static void At91UsartRxStart(void)
01079 {
01080
01081
01082
01083 if (flow_control && (flow_control & XOFF_SENT) != 0) {
01084 NutEnterCritical();
01085 if ((inr(USARTn_BASE + US_CSR_OFF) & US_TXRDY)) {
01086 outr(USARTn_BASE + US_THR_OFF, ASCII_XON);
01087 flow_control &= ~XON_PENDING;
01088 } else {
01089 flow_control |= XON_PENDING;
01090 }
01091 flow_control &= ~(XOFF_SENT | XOFF_PENDING);
01092 NutExitCritical();
01093 }
01094 #ifdef UART_RTS_BIT
01095 if (rts_control) {
01096
01097 cbi(UART_RTS_PORT, UART_RTS_BIT);
01098 }
01099 #endif
01100 }
01101
01102
01103
01104
01105
01106
01107
01108
01109
01110 static int At91UsartInit(void)
01111 {
01112
01113
01114
01115 if (NutRegisterIrqHandler(&SIG_UART, At91UsartInterrupt, &dcb_usart)) {
01116 return -1;
01117 }
01118
01119 #if defined (MCU_AT91R40008)
01120
01121 outr(PS_PCER, _BV(US_ID));
01122
01123 outr(PIO_PDR, US_GPIO_PINS);
01124 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
01125 outr(PMC_PCER, _BV(US_ID));
01126 outr(PIOA_PDR, US_GPIO_PINS);
01127 #endif
01128
01129 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01130
01131 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01132
01133 #if defined (US_RCR_OFF)
01134 outr(USARTn_BASE + US_RCR_OFF, 0);
01135 #endif
01136 #if defined (US_TCR_OFF)
01137 outr(USARTn_BASE + US_TCR_OFF, 0);
01138 #endif
01139
01140 #if defined(AT91_PLL_MAINCK)
01141 outr(USARTn_BASE + US_BRGR_OFF, (At91GetMasterClock() / (8 * (115200)) + 1) / 2);
01142 #else
01143 outr(USARTn_BASE + US_BRGR_OFF, (NutGetCpuClock() / (8 * (115200)) + 1) / 2);
01144 #endif
01145
01146 outr(USARTn_BASE + US_MR_OFF, US_CHMODE_NORMAL | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1);
01147
01148 return 0;
01149 }
01150
01151
01152
01153
01154
01155
01156
01157
01158
01159 static int At91UsartDeinit(void)
01160 {
01161
01162 NutRegisterIrqHandler(&SIG_UART, 0, 0);
01163
01164
01165 outr(USARTn_BASE + US_CR_OFF, US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS);
01166
01167 outr(USARTn_BASE + US_IDR_OFF, 0xFFFFFFFF);
01168 #if defined (MCU_AT91R40008)
01169
01170 outr(PS_PCDR, _BV(US_ID));
01171
01172 outr(PIO_PER, US_GPIO_PINS);
01173 #elif defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
01174 outr(PMC_PCDR, _BV(US_ID));
01175 outr(PIOA_PER, US_GPIO_PINS);
01176 #endif
01177
01178
01179
01180
01181
01182
01183 #ifdef UART_HDX_BIT
01184
01185 if (hdx_control) {
01186 hdx_control = 0;
01187 NutRegisterIrqHandler(&sig_UART_TRANS, 0, 0);
01188 }
01189 #endif
01190
01191 #ifdef UART_CTS_BIT
01192 if (cts_sense) {
01193 cts_sense = 0;
01194 cbi(UART_CTS_DDR, UART_CTS_BIT);
01195
01196 NutRegisterIrqHandler(&UART_CTS_SIGNAL, 0, 0);
01197 }
01198 #endif
01199
01200 #ifdef UART_RTS_BIT
01201 if (rts_control) {
01202 rts_control = 0;
01203 cbi(UART_RTS_DDR, UART_RTS_BIT);
01204 }
01205 #endif
01206
01207 return 0;
01208 }
01209