ih_at91irq0.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91irq0.c,v $
00036  * Revision 1.4  2006/06/28 17:10:15  haraldkipp
00037  * Include more general header file for ARM.
00038  *
00039  * Revision 1.3  2006/04/07 12:20:55  haraldkipp
00040  * Fixed wrong setting of high level sense.
00041  *
00042  * Revision 1.2  2006/01/05 16:44:53  haraldkipp
00043  * Edge and level trigger modes now configurable.
00044  *
00045  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00046  * First check in.
00047  *
00048  */
00049 
00050 #include <arch/arm.h>
00051 #include <dev/irqreg.h>
00052 
00053 #ifndef NUT_IRQPRI_IRQ0
00054 #define NUT_IRQPRI_IRQ0  4
00055 #endif
00056 
00057 static int Interrupt0Ctl(int cmd, void *param);
00058 
00059 IRQ_HANDLER sig_INTERRUPT0 = {
00060 #ifdef NUT_PERFMON
00061     0,                  /* Interrupt counter, ir_count. */
00062 #endif
00063     NULL,               /* Passed argument, ir_arg. */
00064     NULL,               /* Handler subroutine, ir_handler. */
00065     Interrupt0Ctl       /* Interrupt control, ir_ctl. */
00066 };
00067 
00071 static void Interrupt0Entry(void) __attribute__ ((naked));
00072 void Interrupt0Entry(void)
00073 {
00074     IRQ_ENTRY();
00075 #ifdef NUT_PERFMON
00076     sig_INTERRUPT0.ir_count++;
00077 #endif
00078     if (sig_INTERRUPT0.ir_handler) {
00079         (sig_INTERRUPT0.ir_handler) (sig_INTERRUPT0.ir_arg);
00080     }
00081     IRQ_EXIT();
00082 }
00083 
00099 static int Interrupt0Ctl(int cmd, void *param)
00100 {
00101     int rc = 0;
00102     u_int *ival = (u_int *)param;
00103     int enabled = inr(AIC_IMR) & _BV(IRQ0_ID);
00104 
00105     /* Disable interrupt. */
00106     if (enabled) {
00107         outr(AIC_IDCR, _BV(IRQ0_ID));
00108     }
00109 
00110     switch(cmd) {
00111     case NUT_IRQCTL_INIT:
00112         /* Set the vector. */
00113         outr(AIC_SVR(IRQ0_ID), (unsigned int)Interrupt0Entry);
00114         /* Initialize to edge triggered with defined priority. */
00115         outr(AIC_SMR(IRQ0_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_IRQ0);
00116         /* Clear interrupt */
00117         outr(AIC_ICCR, _BV(IRQ0_ID));
00118         break;
00119     case NUT_IRQCTL_STATUS:
00120         if (enabled) {
00121             *ival |= 1;
00122         }
00123         else {
00124             *ival &= ~1;
00125         }
00126         break;
00127     case NUT_IRQCTL_ENABLE:
00128         enabled = 1;
00129         break;
00130     case NUT_IRQCTL_DISABLE:
00131         enabled = 0;
00132         break;
00133     case NUT_IRQCTL_GETMODE:
00134         {
00135             u_int val = inr(AIC_SMR(IRQ0_ID)) & AIC_SRCTYPE;
00136             if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00137                 *ival = NUT_IRQMODE_LOWLEVEL;
00138             } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00139                 *ival = NUT_IRQMODE_HIGHLEVEL;
00140             } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00141                 *ival = NUT_IRQMODE_RISINGEDGE;
00142             } else  {
00143                 *ival = NUT_IRQMODE_FALLINGEDGE;
00144             }
00145         }
00146         break;
00147     case NUT_IRQCTL_SETMODE:
00148         if (*ival == NUT_IRQMODE_LOWLEVEL) {
00149             outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00150         } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00151             outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00152         } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00153             outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00154         } else  if (*ival == NUT_IRQMODE_RISINGEDGE) {
00155             outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00156         } else  {
00157             rc = -1;
00158         }
00159         break;
00160     case NUT_IRQCTL_GETPRIO:
00161         *ival = inr(AIC_SMR(IRQ0_ID)) & AIC_PRIOR;
00162         break;
00163     case NUT_IRQCTL_SETPRIO:
00164         outr(AIC_SMR(IRQ0_ID), (inr(AIC_SMR(IRQ0_ID)) & ~AIC_PRIOR) | *ival);
00165         break;
00166 #ifdef NUT_PERFMON
00167     case NUT_IRQCTL_GETCOUNT:
00168         *ival = (u_int)sig_INTERRUPT0.ir_count;
00169         sig_INTERRUPT0.ir_count = 0;
00170         break;
00171 #endif
00172     default:
00173         rc = -1;
00174         break;
00175     }
00176 
00177     /* Enable interrupt. */
00178     if (enabled) {
00179         outr(AIC_IECR, _BV(IRQ0_ID));
00180     }
00181     return rc;
00182 }
00183 

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