ih_at91tc1.c

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00001 /*
00002  * Copyright (C) 2005 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: ih_at91tc1.c,v $
00036  * Revision 1.2  2006/06/28 17:10:27  haraldkipp
00037  * Include more general header file for ARM.
00038  *
00039  * Revision 1.1  2005/10/24 08:56:09  haraldkipp
00040  * First check in.
00041  *
00042  */
00043 
00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046 
00047 #ifndef NUT_IRQPRI_TC1
00048 #define NUT_IRQPRI_TC1  4
00049 #endif
00050 
00051 static int TimerCounter1IrqCtl(int cmd, void *param);
00052 
00053 IRQ_HANDLER sig_TC1 = {
00054 #ifdef NUT_PERFMON
00055     0,                  /* Interrupt counter, ir_count. */
00056 #endif
00057     NULL,               /* Passed argument, ir_arg. */
00058     NULL,               /* Handler subroutine, ir_handler. */
00059     TimerCounter1IrqCtl /* Interrupt control, ir_ctl. */
00060 };
00061 
00065 static u_int dummy;
00066 static void TimerCounter1IrqEntry(void) __attribute__ ((naked));
00067 void TimerCounter1IrqEntry(void)
00068 {
00069     IRQ_ENTRY();
00070 #ifdef NUT_PERFMON
00071     sig_TC1.ir_count++;
00072 #endif
00073     dummy = inr(TC1_SR);
00074     if (sig_TC1.ir_handler) {
00075         (sig_TC1.ir_handler) (sig_TC1.ir_arg);
00076     }
00077     IRQ_EXIT();
00078 }
00079 
00095 static int TimerCounter1IrqCtl(int cmd, void *param)
00096 {
00097     int rc = 0;
00098     u_int *ival = (u_int *)param;
00099     int enabled = inr(AIC_IMR) & _BV(TC1_ID);
00100 
00101     /* Disable interrupt. */
00102     if (enabled) {
00103         outr(AIC_IDCR, _BV(TC1_ID));
00104     }
00105     switch(cmd) {
00106     case NUT_IRQCTL_INIT:
00107         /* Set the vector. */
00108         outr(AIC_SVR(TC1_ID), (unsigned int)TimerCounter1IrqEntry);
00109         /* Initialize to edge triggered with defined priority. */
00110         outr(AIC_SMR(TC1_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC1);
00111         /* Clear interrupt */
00112         outr(AIC_ICCR, _BV(TC1_ID));
00113         /* Init will return with interrupts disabled. */
00114         enabled = 0;
00115         break;
00116     case NUT_IRQCTL_STATUS:
00117         if (enabled) {
00118             *ival |= 1;
00119         }
00120         else {
00121             *ival &= ~1;
00122         }
00123         break;
00124     case NUT_IRQCTL_ENABLE:
00125         enabled = 1;
00126         break;
00127     case NUT_IRQCTL_DISABLE:
00128         enabled = 0;
00129         break;
00130     case NUT_IRQCTL_GETPRIO:
00131         *ival = inr(AIC_SMR(TC1_ID)) & AIC_PRIOR;
00132         break;
00133     case NUT_IRQCTL_SETPRIO:
00134         outr(AIC_SMR(TC1_ID), (inr(AIC_SMR(TC1_ID)) & ~AIC_PRIOR) | *ival);
00135         break;
00136 #ifdef NUT_PERFMON
00137     case NUT_IRQCTL_GETCOUNT:
00138         *ival = (u_int)sig_TC1.ir_count;
00139         sig_TC1.ir_count = 0;
00140         break;
00141 #endif
00142     default:
00143         rc = -1;
00144         break;
00145     }
00146 
00147     /* Enable interrupt. */
00148     if (enabled) {
00149         outr(AIC_IECR, _BV(TC1_ID));
00150     }
00151     return rc;
00152 }

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