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00047 #include <arch/arm.h>
00048 #include <dev/irqreg.h>
00049
00050 #ifndef NUT_IRQPRI_IRQ1
00051 #define NUT_IRQPRI_IRQ1 4
00052 #endif
00053
00054 static int Interrupt1Ctl(int cmd, void *param);
00055
00056 IRQ_HANDLER sig_INTERRUPT1 = {
00057 #ifdef NUT_PERFMON
00058 0,
00059 #endif
00060 NULL,
00061 NULL,
00062 Interrupt1Ctl
00063 };
00064
00068 static void Interrupt1Entry(void) __attribute__ ((naked));
00069 void Interrupt1Entry(void)
00070 {
00071 IRQ_ENTRY();
00072 #ifdef NUT_PERFMON
00073 sig_INTERRUPT1.ir_count++;
00074 #endif
00075 if (sig_INTERRUPT1.ir_handler) {
00076 (sig_INTERRUPT1.ir_handler) (sig_INTERRUPT1.ir_arg);
00077 }
00078 IRQ_EXIT();
00079 }
00080
00096 static int Interrupt1Ctl(int cmd, void *param)
00097 {
00098 int rc = 0;
00099 u_int *ival = (u_int *)param;
00100 int enabled = inr(AIC_IMR) & _BV(IRQ1_ID);
00101
00102
00103 if (enabled) {
00104 outr(AIC_IDCR, _BV(IRQ1_ID));
00105 }
00106
00107 switch(cmd) {
00108 case NUT_IRQCTL_INIT:
00109
00110 outr(AIC_SVR(IRQ1_ID), (unsigned int)Interrupt1Entry);
00111
00112 outr(AIC_SMR(IRQ1_ID), AIC_SRCTYPE_EXT_HIGH_LEVEL | NUT_IRQPRI_IRQ1);
00113
00114 outr(AIC_ICCR, _BV(IRQ1_ID));
00115 break;
00116 case NUT_IRQCTL_STATUS:
00117 if (enabled) {
00118 *ival |= 1;
00119 }
00120 else {
00121 *ival &= ~1;
00122 }
00123 break;
00124 case NUT_IRQCTL_ENABLE:
00125 enabled = 1;
00126 break;
00127 case NUT_IRQCTL_DISABLE:
00128 enabled = 0;
00129 break;
00130 case NUT_IRQCTL_GETMODE:
00131 {
00132 u_int val = inr(AIC_SMR(IRQ1_ID)) & AIC_SRCTYPE;
00133 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00134 *ival = NUT_IRQMODE_LOWLEVEL;
00135 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00136 *ival = NUT_IRQMODE_HIGHLEVEL;
00137 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00138 *ival = NUT_IRQMODE_RISINGEDGE;
00139 } else {
00140 *ival = NUT_IRQMODE_FALLINGEDGE;
00141 }
00142 }
00143 break;
00144 case NUT_IRQCTL_SETMODE:
00145 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00146 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00147 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00148 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00149 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00150 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00151 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00152 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00153 } else {
00154 rc = -1;
00155 }
00156 break;
00157 case NUT_IRQCTL_GETPRIO:
00158 *ival = inr(AIC_SMR(IRQ1_ID)) & AIC_PRIOR;
00159 break;
00160 case NUT_IRQCTL_SETPRIO:
00161 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_PRIOR) | *ival);
00162 break;
00163 #ifdef NUT_PERFMON
00164 case NUT_IRQCTL_GETCOUNT:
00165 *ival = (u_int)sig_INTERRUPT1.ir_count;
00166 sig_INTERRUPT1.ir_count = 0;
00167 break;
00168 #endif
00169 default:
00170 rc = -1;
00171 break;
00172 }
00173
00174
00175 if (enabled) {
00176 outr(AIC_IECR, _BV(IRQ1_ID));
00177 }
00178 return rc;
00179 }
00180