at91_twi.c

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00001 /*
00002  * Copyright (C) 2001-2005 by EmbeddedIT, 
00003  * Ole Reinhardt <ole.reinhardt@embedded-it.de> All rights reserved.
00004  *
00005  * Redistribution and use in source and binary forms, with or without
00006  * modification, are permitted provided that the following conditions
00007  * are met:
00008  *
00009  * 1. Redistributions of source code must retain the above copyright
00010  *    notice, this list of conditions and the following disclaimer.
00011  * 2. Redistributions in binary form must reproduce the above copyright
00012  *    notice, this list of conditions and the following disclaimer in the
00013  *    documentation and/or other materials provided with the distribution.
00014  * 3. Neither the name of the copyright holders nor the names of
00015  *    contributors may be used to endorse or promote products derived
00016  *    from this software without specific prior written permission.
00017  *
00018  * THIS SOFTWARE IS PROVIDED BY EMBEDDED IT AND CONTRIBUTORS
00019  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00020  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00021  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EMBEDDED IT
00022  * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
00023  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
00024  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 
00025  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
00026  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
00027  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
00028  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  *
00032  */
00033 
00034 /*
00035  * $Log: at91_twi.c,v $
00036  * Revision 1.4  2007/12/09 22:17:23  olereinhardt
00037  * fixed typo
00038  *
00039  * Revision 1.3  2007/12/09 21:52:27  olereinhardt
00040  * Added doxygen tags
00041  *
00042  * Revision 1.2  2007/10/04 19:51:56  olereinhardt
00043  * Support for sam7s added
00044  *
00045  * Revision 1.1  2007/09/06 19:36:00  olereinhardt
00046  * First checkin, new twi driver for at91 (currently SAM7X256 is supported
00047  * only)
00048  *
00049  */
00050 
00051 #include <arch/arm.h>
00052 #include <dev/irqreg.h>
00053 
00054 #include <sys/event.h>
00055 #include <sys/atom.h>
00056 #include <sys/timer.h>
00057 #include <sys/thread.h>
00058 #include <sys/heap.h>
00059 
00060 #include <dev/twif.h>
00061 
00066 
00067 HANDLE tw_mm_mutex;                 /* Exclusive master access. */
00068 HANDLE tw_mm_que;                   /* Threads waiting for master transfer done. */
00069 
00070 static u_char tw_mm_sla;            /* Destination slave address. */
00071 static volatile u_char tw_mm_err;   /* Current master mode error. */
00072 static u_char tw_mm_error;          /* Last master mode error. */
00073 
00074 static CONST u_char *tw_mt_buf;     /* Pointer to the master transmit buffer. */
00075 static volatile u_short tw_mt_len;  /* Number of bytes to transmit in master mode. */
00076 static volatile u_short tw_mt_idx;  /* Current master transmit buffer index. */
00077 
00078 static u_char *tw_mr_buf;           /* Pointer to the master receive buffer. */
00079 static volatile u_short tw_mr_siz;  /* Size of the master receive buffer. */
00080 static volatile u_short tw_mr_idx;  /* Current master receive buffer index. */
00081 
00082 #if defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM7S256)
00083 
00084 #define TWI_PIO_ASR PIOA_ASR
00085 #define TWI_PIO_PDR PIOA_PDR
00086 #define TWI_PIO_MDER PIOA_MDER
00087 
00088    #if defined (MCU_AT91SAM7X256)
00089       #define TWI_TWD  PA10_TWD_A
00090       #define TWI_TWCK PA11_TWCK_A
00091    #elif defined (MCU_AT91SAM7S256)
00092       #define TWI_TWD  PA3_TWD_A
00093       #define TWI_TWCK PA4_TWCK_A
00094    #endif
00095 #endif
00096 
00097 /*
00098  * TWI interrupt handler.
00099  */
00100 static void TwInterrupt(void *arg)
00101 {
00102     register u_int twsr = inr(TWI_SR) & (TWI_NACK | TWI_RXRDY | TWI_TXRDY | TWI_TXCOMP);;   
00103 
00104     /* Transmission is complete, signal waiting threads */
00105     if (twsr & TWI_TXCOMP) {
00106         outr(TWI_IDR, 0xFFFFFFFF);
00107         NutEventPostFromIrq(&tw_mm_que);
00108     }
00109     
00110     if (twsr & TWI_RXRDY) {
00111         if (tw_mr_idx < tw_mr_siz) {
00112             tw_mr_buf[tw_mr_idx++] = inb(TWI_RHR);
00113             /* The last byte will follow, just set the stop condition */
00114             if (tw_mr_idx == tw_mr_siz - 1) {
00115                 outr(TWI_CR, TWI_STOP);
00116             }
00117                 
00118             if (tw_mr_idx == tw_mr_siz) {
00119                 /* Last byte received. Send stop condition and set IRQs */
00120                 outr(TWI_IDR, TWI_RXRDY);
00121                 outr(TWI_IER, TWI_TXCOMP);
00122             }
00123         } 
00124     }
00125     
00126     if (twsr & TWI_TXRDY) {
00127         if (tw_mt_idx < tw_mt_len) {
00128             outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00129             /* Last byte? No bytes to read? So send stop condition else if bytes to read switch to read mode */
00130             if (tw_mt_idx == tw_mt_len) {
00131                 if (tw_mr_siz == 0) {
00132                     outr(TWI_CR, TWI_STOP);
00133                     outr(TWI_IDR, TWI_TXRDY);
00134                     outr(TWI_IER, TWI_TXCOMP);
00135                 } else {
00136                     /* Ok, now switch to read mode and send second start condition */
00137                     outr(TWI_MMR, inb(TWI_MMR) | TWI_MREAD);
00138                     outr(TWI_CR,  TWI_START | (tw_mr_siz == 1) ? TWI_STOP : 0);
00139                     outr(TWI_IDR, TWI_TXRDY);
00140                     outr(TWI_IER, TWI_RXRDY);
00141                 }
00142             }
00143         } 
00144     }
00145     
00146     /* We got a nack, stop transmission and wait for TWI_TXCOMP */
00147     if (twsr & TWI_NACK) {;
00148         /* send stop condition and wake up threads */
00149         outr(TWI_CR, TWI_STOP);
00150         tw_mm_err = TWERR_DATA_NACK;
00151         tw_mt_idx = 0;
00152         tw_mt_len = 0;
00153         tw_mr_siz = 0;
00154         outr(TWI_IDR, 0xFFFFFFFF);
00155         /* Wake up the application. */
00156         NutEventPostFromIrq(&tw_mm_que);
00157     }
00158 }
00159 
00186 int TwMasterTransact(u_char sla, CONST void *txdata, u_short txlen, void *rxdata, u_short rxsiz, u_long tmo)
00187 {
00188     int rc = -1;
00189 
00190     /* This routine is marked reentrant, so lock the interface. */
00191     if(NutEventWait(&tw_mm_mutex, 500)) {
00192         tw_mm_err = TWERR_IF_LOCKED;
00193         NutEventPost(&tw_mm_mutex);
00194         return -1;
00195     }
00196     NutIrqEnable(&sig_TWI);
00197 
00198     NutEnterCritical();
00199     /* Set all parameters for master mode. */
00200     tw_mm_sla = sla;
00201     tw_mm_err = 0;
00202     tw_mt_len = txlen;
00203     tw_mt_idx = 0;
00204     tw_mt_buf = txdata;
00205     tw_mr_siz = rxsiz;
00206     tw_mr_buf = rxdata;
00207     tw_mr_idx = 0;
00208 
00209     if ((tw_mt_len == 0) && (tw_mr_siz == 0)) return -1;
00210 
00211     /* Set slave address enable interrupts and start transmission */
00212     
00213     outr(TWI_MMR, (tw_mm_sla << 16) | (tw_mt_len == 0 ? TWI_MREAD : 0));
00214     
00215     /* Enable interrupts depending on read / write direction and data size */     
00216     if (tw_mt_len == 0) {  
00217         outr(TWI_IDR, TWI_TXRDY | TWI_TXCOMP);
00218         outr(TWI_IER, TWI_RXRDY | TWI_NACK);
00219     } else {
00220         outr(TWI_IDR, TWI_RXRDY);
00221         if ((tw_mt_len == 1) && (tw_mr_siz == 0)) {
00222             outr(TWI_IDR, TWI_TXRDY);
00223             outr(TWI_IER, TWI_TXCOMP);
00224         } else {            
00225             outr(TWI_IER, TWI_TXRDY);
00226             outr(TWI_IDR, TWI_TXCOMP);
00227         }
00228         outr(TWI_IER, TWI_NACK);        
00229     }
00230 
00231     /* Now start transmission if we have any data */
00232     if (tw_mt_len > 0) {
00233         outb(TWI_THR, tw_mt_buf[tw_mt_idx++]);
00234     }     
00235     
00236     /* Send start condition. If read / write only one byte send stop as well */
00237     outr(TWI_CR, TWI_START | (((tw_mt_len == 1) && (tw_mr_siz == 0)) || 
00238                               ((tw_mt_len == 0) && (tw_mr_siz == 1))) ? TWI_STOP : 0);
00239         
00240     NutExitCritical();
00241         
00242     /* Wait for master transmission to be done. */
00243     rc = -1;
00244     if (NutEventWait(&tw_mm_que, tmo)) {
00245         tw_mm_error = TWERR_TIMEOUT;
00246     } else {
00247         NutEnterCritical();
00248         if (tw_mm_err) {
00249             tw_mm_error = tw_mm_err;
00250         } else {
00251             rc = tw_mr_idx;
00252         }
00253         NutExitCritical();
00254     }
00255 
00256     NutIrqDisable(&sig_TWI);
00257     
00258     /* Release the interface. */
00259     NutEventPost(&tw_mm_mutex);
00260     
00261     return rc;
00262 }
00263 
00273 int TwMasterError(void)
00274 {
00275     int rc = (int) tw_mm_error;
00276     tw_mm_error = 0;
00277     return rc;
00278 }
00279 
00295 int TwIOCtl(int req, void *conf)
00296 {
00297     int rc = 0;
00298     unsigned int cldiv, ckdiv;     
00299     unsigned int twi_clk;
00300     switch (req) {
00301 
00302     case TWI_SETSPEED:
00303         ckdiv=1 ;
00304         twi_clk = *((u_long *) conf);
00305 
00306         if (twi_clk > 400000) return -1;
00307         
00308         /*
00309          * CLDIV = ((Tlow x 2^CKDIV) -3) x Tmck
00310          * CHDIV = ((THigh x 2^CKDIV) -3) x Tmck
00311          * Only CLDIV is computed since CLDIV = CHDIV (50% duty cycle) 
00312          */
00313 
00314         while ((cldiv = ((NutGetCpuClock() / (2*twi_clk))-3 ) / (1 << ckdiv)) > 255) {
00315             ckdiv++;
00316         }
00317 
00318         /* BUG 41.2.7.1, datasheet SAM7X256  p. 626 */
00319         if (cldiv * (2 << ckdiv) > 8191) return -1; 
00320         
00321         outr(TWI_CWGR, (ckdiv << 16) | ((u_int) cldiv << 8) | (u_int) cldiv);
00322         break;
00323 
00324     case TWI_GETSPEED:
00325         ckdiv=1 ;
00326         twi_clk = *((u_long *) conf);
00327         
00328         cldiv = inr(TWI_CWGR) & 0x000000FF;
00329         ckdiv = (inr(TWI_CWGR) >> 16) & 0x00000007;
00330             
00331         *((u_long *) conf) = NutGetCpuClock() * ((cldiv * 2 << ckdiv) - 3);
00332         break;
00333 
00334     case TWI_GETSTATUS:
00335         break;
00336         
00337     case TWI_SETSTATUS:
00338         break;
00339 
00340     default:
00341         rc = -1;
00342         break;
00343     }
00344     return rc;
00345 }
00346 
00359 int TwInit(u_char sla)
00360 {
00361     u_long speed = 2400;
00362 
00363     if (NutRegisterIrqHandler(&sig_TWI, TwInterrupt, 0)) {
00364         return -1;
00365     }
00366 
00367     outr(TWI_PIO_ASR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Set TWD and TWCK as peripheral line
00368     outr(TWI_PIO_PDR, _BV(TWI_TWD) | _BV(TWI_TWCK));  // Let periperal control the PIO lines
00369     
00370     outr(TWI_PIO_MDER, _BV(TWI_TWD) | _BV(TWI_TWCK)); // Enabled OpenDrain output on both lines
00371     
00372     outr(PMC_PCER, _BV(TWI_ID));              // Enable TWI clock in PMC
00373     
00374     outr(TWI_IDR, 0xFFFFFFFF);                // Disable all interrupts 
00375     outr(TWI_CR, TWI_SWRST);                  // Reset bus
00376     outr(TWI_CR, TWI_MSEN | TWI_SVDIS);       // Enable master mode
00377     
00378     TwIOCtl(TWI_SETSPEED, &speed);
00379 
00380     /* Initialize mutex semaphores. */
00381     NutEventPost(&tw_mm_mutex);
00382 
00383     return 0;
00384 }

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