spimmc_at91.c

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00001 /*
00002  * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
00003  *
00004  * Redistribution and use in source and binary forms, with or without
00005  * modification, are permitted provided that the following conditions
00006  * are met:
00007  *
00008  * 1. Redistributions of source code must retain the above copyright
00009  *    notice, this list of conditions and the following disclaimer.
00010  * 2. Redistributions in binary form must reproduce the above copyright
00011  *    notice, this list of conditions and the following disclaimer in the
00012  *    documentation and/or other materials provided with the distribution.
00013  * 3. Neither the name of the copyright holders nor the names of
00014  *    contributors may be used to endorse or promote products derived
00015  *    from this software without specific prior written permission.
00016  *
00017  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00018  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00019  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00020  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00021  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00022  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00023  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00024  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00025  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00026  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00027  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00028  * SUCH DAMAGE.
00029  *
00030  * For additional information see http://www.ethernut.de/
00031  */
00032 
00057 #include <cfg/arch.h>
00058 #include <cfg/arch/gpio.h>
00059 
00060 #include <dev/mmcard.h>
00061 #include <dev/spimmc_at91.h>
00062 
00063 #if 0
00064 /* Use for local debugging. */
00065 #define NUTDEBUG
00066 #include <stdio.h>
00067 #endif
00068 
00073 
00074 #if defined(MCU_AT91SAM9260)
00075 
00076 #ifndef MMC_CS_BIT
00077 #define MMC_CS_BIT      PA3_SPI0_NPCS0_A
00078 #endif
00079 #define MMC_DATAOUT_BIT PA0_SPI0_MISO_A
00080 #define MMC_DATAIN_BIT  PA1_SPI0_MOSI_A
00081 #define MMC_CLK_BIT     PA2_SPI0_SPCK_A
00082 
00083 #elif defined(MCU_AT91SAM7X256)
00084 
00085 #ifndef MMC_CS_BIT
00086 #define MMC_CS_BIT      SPI0_NPCS1_PA13A
00087 #endif
00088 #define MMC_DATAOUT_BIT SPI0_MISO_PA16A
00089 #define MMC_DATAIN_BIT  SPI0_MOSI_PA17A
00090 #define MMC_CLK_BIT     SPI0_SPCK_PA18A
00091 
00092 #elif defined(MCU_AT91SAM7S256)
00093 
00094 #ifndef MMC_CS_BIT
00095 #define MMC_CS_BIT      SPI0_NPCS0_PA11A
00096 #endif
00097 #define MMC_DATAOUT_BIT SPI0_MISO_PA12A
00098 #define MMC_DATAIN_BIT  SPI0_MOSI_PA13A
00099 #define MMC_CLK_BIT     SPI0_SPCK_PA14A
00100 
00101 #else   /* MCU_AT91SAM7X256 */
00102 #warning "MMC SPI mode not supported on this MCU"
00103 #endif
00104 
00105 #ifndef MMC_PIO_ASR
00106 #define MMC_PIO_ASR     PIOA_ASR
00107 #endif
00108 
00109 #ifndef MMC_PIO_BSR
00110 #define MMC_PIO_BSR     PIOA_BSR
00111 #endif
00112 
00113 #ifndef MMC_PIO_PDR
00114 #define MMC_PIO_PDR     PIOA_PDR
00115 #endif
00116 
00117 #ifndef MMC_PINS_A
00118 #define MMC_PINS_A      (_BV(MMC_DATAOUT_BIT) | _BV(MMC_DATAIN_BIT) | _BV(MMC_CLK_BIT))
00119 #endif
00120 
00121 #ifndef MMC_PINS_B
00122 #define MMC_PINS_B      0
00123 #endif
00124 
00125 #ifndef MMC_CS_PER
00126 #define MMC_CS_PER      PIOA_PER
00127 #endif
00128 
00129 #ifndef MMC_CS_OER
00130 #define MMC_CS_OER      PIOA_OER
00131 #endif
00132 
00133 #ifndef MMC_CS_SODR
00134 #define MMC_CS_SODR     PIOA_SODR
00135 #endif
00136 
00137 #ifndef MMC_CS_CODR
00138 #define MMC_CS_CODR     PIOA_CODR
00139 #endif
00140 
00141 #ifndef MMC_SPI_CR
00142 #define MMC_SPI_CR      SPI0_CR
00143 #endif
00144 
00145 #ifndef MMC_SPI_MR
00146 #define MMC_SPI_MR      SPI0_MR
00147 #endif
00148 
00149 #ifndef MMC_SPI_RDR
00150 #define MMC_SPI_RDR     SPI0_RDR
00151 #endif
00152 
00153 #ifndef MMC_SPI_TDR
00154 #define MMC_SPI_TDR     SPI0_TDR
00155 #endif
00156 
00157 #ifndef MMC_SPI_SR
00158 #define MMC_SPI_SR      SPI0_SR
00159 #endif
00160 
00161 #ifndef MMC_SPI_CSR1
00162 #define MMC_SPI_CSR1    SPI0_CSR1
00163 #endif
00164 
00165 #ifndef MMC_SPI_ID
00166 #define MMC_SPI_ID      SPI0_ID
00167 #endif
00168 
00169 
00178 static int At91SpiMmCard0Init(void)
00179 {
00180     return 0;
00181 }
00182 
00191 static int At91SpiMmCard0Select(int on)
00192 {
00193     int rc = (inr(PIOA_ODSR) & _BV(MMC_CS_BIT)) == 0;
00194 
00195     /* MMC select is low active. */
00196     if (on == 1) {
00197         outr(MMC_CS_CODR, _BV(MMC_CS_BIT));
00198     } else if (on == 0) {
00199         outr(MMC_CS_SODR, _BV(MMC_CS_BIT));
00200     }
00201     return rc;
00202 }
00203 
00211 static u_char At91SpiMmCard0Io(u_char val)
00212 {
00213 #ifdef NUTDEBUG
00214     putchar('[');
00215     if (val != 0xFF) {
00216         printf("s%02X", val);
00217     }
00218 #endif
00219 
00220     /* Transmission is started by writing the transmit data. */
00221     outr(MMC_SPI_TDR, val);
00222     /* Wait for receiver data register full. */
00223     while((inr(MMC_SPI_SR) & SPI_RDRF) == 0);
00224     /* Read data. */
00225     val = (u_char)inr(MMC_SPI_RDR);
00226 
00227 #ifdef NUTDEBUG
00228     if (val != 0xFF) {
00229         printf("r%02X", val);
00230     }
00231     putchar(']');
00232 #endif
00233     return val;
00234 }
00235 
00246 int At91SpiMmCard0Avail(void)
00247 {
00248     return 1;
00249 }
00250 
00258 int At91SpiMmCard0WrProt(void)
00259 {
00260     return 0;
00261 }
00262 
00271 static int At91SpiMmcIfcInit(NUTDEVICE * dev)
00272 {
00273     /* Disable PIO lines used for SPI. */
00274     outr(MMC_PIO_PDR, MMC_PINS_A | MMC_PINS_B);
00275     /* Enable peripherals. */
00276     outr(MMC_PIO_ASR, MMC_PINS_A);
00277     outr(MMC_PIO_BSR, MMC_PINS_B);
00278 
00279     /* MMC chip select is manually controlled. */
00280     outr(MMC_CS_PER, _BV(MMC_CS_BIT));
00281     outr(MMC_CS_SODR, _BV(MMC_CS_BIT));
00282     outr(MMC_CS_OER, _BV(MMC_CS_BIT));
00283 
00284     /* Enable SPI clock. */
00285     outr(PMC_PCER, _BV(MMC_SPI_ID));
00286 
00287     /* SPI enable and reset. */
00288     outr(MMC_SPI_CR, SPI_SPIEN | SPI_SWRST);
00289     outr(MMC_SPI_CR, SPI_SPIEN);
00290 
00291     /* Set SPI to master mode, fixed peripheral at CS1, fault detection disabled. */
00292     outr(MMC_SPI_MR, (1 << SPI_PCS_LSB) | SPI_MODFDIS | SPI_MSTR);
00293 
00294     /* Data changes during clock low and will be sampled on rising edges. */
00295     outr(MMC_SPI_CSR1, (3 << SPI_SCBR_LSB) | SPI_CPOL);
00296 
00297     return MmCardDevInit(dev);
00298 }
00299 
00300 static MMCIFC mmc0_ifc = {
00301     At91SpiMmCard0Init,             
00302     At91SpiMmCard0Io,               
00303     At91SpiMmCard0Select,           
00304     At91SpiMmCard0Avail,            
00305     At91SpiMmCard0WrProt            
00306 };
00307 
00320 NUTDEVICE devAt91SpiMmc0 = {
00321     0,                          
00322     {'M', 'M', 'C', '0', 0, 0, 0, 0, 0}
00323     ,                           
00324     0,                          
00325     0,                          
00326     0,                          
00327     &mmc0_ifc,                  
00328     0,                          
00329     At91SpiMmcIfcInit,          
00330     MmCardIOCtl,                
00331     MmCardBlockRead,            
00332     MmCardBlockWrite,           
00333 #ifdef __HARVARD_ARCH__
00334     MmCardBlockWrite_P,         
00335 #endif
00336     MmCardMount,                
00337     MmCardUnmount,              
00338     0                           
00339 };
00340 

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