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00044 #include <arch/arm.h>
00045 #include <dev/irqreg.h>
00046
00047 #ifndef NUT_IRQPRI_TC2
00048 #define NUT_IRQPRI_TC2 4
00049 #endif
00050
00051 static int TimerCounter2IrqCtl(int cmd, void *param);
00052
00053 IRQ_HANDLER sig_TC2 = {
00054 #ifdef NUT_PERFMON
00055 0,
00056 #endif
00057 NULL,
00058 NULL,
00059 TimerCounter2IrqCtl
00060 };
00061
00065 static u_int dummy;
00066 static void TimerCounter2IrqEntry(void) __attribute__ ((naked));
00067 void TimerCounter2IrqEntry(void)
00068 {
00069 IRQ_ENTRY();
00070 #ifdef NUT_PERFMON
00071 sig_TC2.ir_count++;
00072 #endif
00073 dummy = inr(TC2_SR);
00074 if (sig_TC2.ir_handler) {
00075 (sig_TC2.ir_handler) (sig_TC2.ir_arg);
00076 }
00077 IRQ_EXIT();
00078 }
00079
00095 static int TimerCounter2IrqCtl(int cmd, void *param)
00096 {
00097 int rc = 0;
00098 u_int *ival = (u_int *)param;
00099 int enabled = inr(AIC_IMR) & _BV(TC2_ID);
00100
00101
00102 if (enabled) {
00103 outr(AIC_IDCR, _BV(TC2_ID));
00104 }
00105
00106 switch(cmd) {
00107 case NUT_IRQCTL_INIT:
00108
00109 outr(AIC_SVR(TC2_ID), (unsigned int)TimerCounter2IrqEntry);
00110
00111 outr(AIC_SMR(TC2_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC2);
00112
00113 outr(AIC_ICCR, _BV(TC2_ID));
00114 break;
00115 case NUT_IRQCTL_STATUS:
00116 if (enabled) {
00117 *ival |= 1;
00118 }
00119 else {
00120 *ival &= ~1;
00121 }
00122 break;
00123 case NUT_IRQCTL_ENABLE:
00124 enabled = 1;
00125 break;
00126 case NUT_IRQCTL_DISABLE:
00127 enabled = 0;
00128 break;
00129 case NUT_IRQCTL_GETPRIO:
00130 *ival = inr(AIC_SMR(TC2_ID)) & AIC_PRIOR;
00131 break;
00132 case NUT_IRQCTL_SETPRIO:
00133 outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_PRIOR) | *ival);
00134 break;
00135 #ifdef NUT_PERFMON
00136 case NUT_IRQCTL_GETCOUNT:
00137 *ival = (u_int)sig_TC2.ir_count;
00138 sig_TC2.ir_count = 0;
00139 break;
00140 #endif
00141 default:
00142 rc = -1;
00143 break;
00144 }
00145
00146
00147 if (enabled) {
00148 outr(AIC_IECR, _BV(TC2_ID));
00149 }
00150 return rc;
00151 }