at91sam7x.h

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00001 #ifndef _ARCH_ARM_SAM7X_H_
00002 #define _ARCH_ARM_SAM7X_H_
00003 /*
00004  * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * 1. Redistributions of source code must retain the above copyright
00011  *    notice, this list of conditions and the following disclaimer.
00012  * 2. Redistributions in binary form must reproduce the above copyright
00013  *    notice, this list of conditions and the following disclaimer in the
00014  *    documentation and/or other materials provided with the distribution.
00015  * 3. Neither the name of the copyright holders nor the names of
00016  *    contributors may be used to endorse or promote products derived
00017  *    from this software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00020  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00021  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00022  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00023  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00024  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00025  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00026  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00027  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00028  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00029  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00030  * SUCH DAMAGE.
00031  *
00032  * For additional information see http://www.ethernut.de/
00033  */
00034 
00093 #define FLASH_BASE      0x100000UL
00094 #define RAM_BASE        0x200000UL
00095 
00096 #define TC_BASE         0xFFFA0000      
00097 #define UDP_BASE        0xFFFB0000      
00098 #define TWI_BASE        0xFFFB8000      
00099 #define USART0_BASE     0xFFFC0000      
00100 #define USART1_BASE     0xFFFC4000      
00101 #define PWMC_BASE       0xFFFCC000      
00102 #define CAN_BASE        0xFFFD0000      
00103 #define SSC_BASE        0xFFFD4000      
00104 #define ADC_BASE        0xFFFD8000      
00105 #define EMAC_BASE       0xFFFDC000      
00106 #define SPI0_BASE       0xFFFE0000      
00107 #define SPI1_BASE       0xFFFE4000      
00109 #define AIC_BASE        0xFFFFF000      
00110 #define DBGU_BASE       0xFFFFF200      
00111 #define PIOA_BASE       0xFFFFF400      
00112 #define PIOB_BASE       0xFFFFF600      
00113 #define PMC_BASE        0xFFFFFC00      
00114 #define RSTC_BASE       0xFFFFFD00      
00115 #define RTT_BASE        0xFFFFFD20      
00116 #define PIT_BASE        0xFFFFFD30      
00117 #define WDT_BASE        0xFFFFFD40      
00118 #define VREG_BASE       0xFFFFFD60      
00119 #define MC_BASE         0xFFFFFF00      
00121 #define PERIPH_RPR_OFF  0x00000100      
00122 #define PERIPH_RCR_OFF  0x00000104      
00123 #define PERIPH_TPR_OFF  0x00000108      
00124 #define PERIPH_TCR_OFF  0x0000010C      
00125 #define PERIPH_RNPR_OFF 0x00000110      
00126 #define PERIPH_RNCR_OFF 0x00000114      
00127 #define PERIPH_TNPR_OFF 0x00000118      
00128 #define PERIPH_TNCR_OFF 0x0000011C      
00129 #define PERIPH_PTCR_OFF 0x00000120      
00130 #define PERIPH_PTSR_OFF 0x00000124      
00132 #define PDC_RXTEN       0x00000001      
00133 #define PDC_RXTDIS      0x00000002      
00134 #define PDC_TXTEN       0x00000100      
00135 #define PDC_TXTDIS      0x00000200      
00137 #define DBGU_HAS_PDC
00138 #define SPI_HAS_PDC
00139 #define SSC_HAS_PDC
00140 #define USART_HAS_PDC
00141 
00142 #define PIO_HAS_MULTIDRIVER
00143 #define PIO_HAS_PULLUP
00144 #define PIO_HAS_PERIPHERALSELECT
00145 #define PIO_HAS_OUTPUTWRITEENABLE
00146 
00147 #include <arch/arm/at91_tc.h>
00148 #include <arch/arm/at91_us.h>
00149 #include <arch/arm/at91_dbgu.h>
00150 #include <arch/arm/at91_emac.h>
00151 #include <arch/arm/at91_spi.h>
00152 #include <arch/arm/at91_aic.h>
00153 #include <arch/arm/at91_pio.h>
00154 #include <arch/arm/at91_pmc.h>
00155 #include <arch/arm/at91_rstc.h>
00156 #include <arch/arm/at91_wdt.h>
00157 #include <arch/arm/at91_pit.h>
00158 #include <arch/arm/at91_mc.h>
00159 #include <arch/arm/at91_ssc.h>
00160 #include <arch/arm/at91_udp.h>
00161 #include <arch/arm/at91_twi.h>
00162 
00165 
00168 #define FIQ_ID      0       
00169 #define SYSC_ID     1       
00170 #define PIOA_ID     2       
00171 #define PIOB_ID     3       
00172 #define SPI0_ID     4       
00173 #define SPI1_ID     5       
00174 #define US0_ID      6       
00175 #define US1_ID      7       
00176 #define SSC_ID      8       
00177 #define TWI_ID      9       
00178 #define PWMC_ID     10      
00179 #define UDP_ID      11      
00180 #define TC0_ID      12      
00181 #define TC1_ID      13      
00182 #define TC2_ID      14      
00183 #define CAN_ID      15      
00184 #define EMAC_ID     16      
00185 #define ADC_ID      17      
00186 #define IRQ0_ID     30      
00187 #define IRQ1_ID     31      
00189 
00190 
00192 #define SPI0_NPCS0_PA12A    12  
00193 #define SPI0_NPCS1_PA13A    13  
00194 #define SPI0_NPCS1_PA07B    7   
00195 #define SPI0_NPCS1_PB13B    13  
00196 #define SPI0_NPCS2_PA14A    14  
00197 #define SPI0_NPCS2_PA08B    8   
00198 #define SPI0_NPCS2_PB14B    14  
00199 #define SPI0_NPCS3_PA15A    15  
00200 #define SPI0_NPCS3_PA09B    9   
00201 #define SPI0_NPCS3_PB17B    17  
00202 #define SPI0_MISO_PA16A     16  
00203 #define SPI0_MOSI_PA17A     17  
00204 #define SPI0_SPCK_PA18A     18  
00206 
00207 
00209 #define PA0_RXD0_A          0
00210 #define PA1_TXD0_A          1
00211 #define PA2_SCK0_A          2
00212 #define PA3_RTS0_A          3
00213 #define PA4_CTS0_A          4
00214 
00215 #define PA5_RXD1_A          5
00216 #define PA6_TXD1_A          6
00217 #define PA7_SCK1_A          7
00218 #define PA8_RTS1_A          8
00219 #define PA9_CTS1_A          9
00220 #define PB23_DCD1_B         23
00221 #define PB24_DSR1_B         24
00222 #define PB25_DTR1_B         25
00223 #define PB26_RI1_B          26
00224 
00228 #define PA16_SPI0_MISO_A    16
00229 #define PA17_SPI0_MOSI_A    17
00230 #define PA18_SPI0_SPCK_A    18
00231 #define PA12_SPI0_NPCS0_A   12
00232 #define PA13_SPI0_NPCS1_A   13
00233 #define PA7_SPI0_NPCS1_B    7
00234 #define PA14_SPI0_NPCS2_A   14
00235 #define PB14_SPI0_NPCS2_B   14
00236 #define PA8_SPI0_NPCS2_B    8
00237 #define PA15_SPI0_NPCS3_A   15
00238 #define PA9_SPI0_NPCS3_B    9
00239 
00240 #define SPI0_PINS           _BV(PA16_SPI0_MISO_A) | _BV(PA17_SPI0_MOSI_A) | _BV(PA18_SPI0_SPCK_A)
00241 #define SPI0_PIO_BASE       PIOA_BASE
00242 #define SPI0_PSR_OFF        PIO_ASR_OFF
00243 
00244 #define SPI0_CS0_PIN        _BV(PA12_SPI0_NPCS0_A)
00245 #define SPI0_CS0_PIO_BASE   PIOA_BASE
00246 #define SPI0_CS0_PSR_OFF    PIO_ASR_OFF
00247 
00248 #ifndef SPI0_CS1_PIN
00249 #define SPI0_CS1_PIN        _BV(PA13_SPI0_NPCS1_A)
00250 #define SPI0_CS1_PIO_BASE   PIOA_BASE
00251 #define SPI0_CS1_PSR_OFF    PIO_ASR_OFF
00252 #endif
00253 
00254 #ifndef SPI0_CS2_PIN
00255 #define SPI0_CS2_PIN        _BV(PA14_SPI0_NPCS2_A)
00256 #define SPI0_CS2_PIO_BASE   PIOA_BASE
00257 #define SPI0_CS2_PSR_OFF    PIO_ASR_OFF
00258 #endif
00259 
00260 #ifndef SPI0_CS3_PIN
00261 #define SPI0_CS3_PIN        _BV(PA15_SPI0_NPCS3_A)
00262 #define SPI0_CS3_PIO_BASE   PIOA_BASE
00263 #define SPI0_CS3_PSR_OFF    PIO_ASR_OFF
00264 #endif
00265 
00266 #define PA24_SPI1_MISO_B    24
00267 #define PA23_SPI1_MOSI_B    23
00268 #define PA22_SPI1_SPCK_B    22
00269 #define PA21_SPI1_NPCS0_B   21
00270 #define PA25_SPI1_NPCS1_B   25
00271 #define PB13_SPI0_NPCS1_B   13
00272 #define PA2_SPI1_NPCS1_B    2
00273 #define PB10_SPI1_NPCS1_B   10
00274 #define PA26_SPI1_NPCS2_B   26
00275 #define PA3_SPI1_NPCS2_B    3
00276 #define PB11_SPI1_NPCS2_B   11
00277 #define PB17_SPI0_NPCS3_B   17
00278 #define PA4_SPI1_NPCS3_B    4
00279 #define PA29_SPI1_NPCS3_B   29
00280 #define PB16_SPI1_NPCS3_B   16
00281 
00282 #define SPI1_PINS           _BV(PA24_SPI1_MISO_B) | _BV(PA23_SPI1_MOSI_B) | _BV(PA22_SPI1_SPCK_B)
00283 #define SPI1_PIO_BASE       PIOA_BASE
00284 #define SPI1_PSR_OFF        PIO_BSR_OFF
00285 
00286 #define SPI1_CS0_PIN        _BV(PA21_SPI1_NPCS0_B)
00287 #define SPI1_CS0_PIO_BASE   PIOA_BASE
00288 #define SPI1_CS0_PSR_OFF    PIO_BSR_OFF
00289 
00290 #ifndef SPI1_CS1_PIN
00291 #define SPI1_CS1_PIN        _BV(PA25_SPI1_NPCS1_B)
00292 #define SPI1_CS1_PIO_BASE   PIOA_BASE
00293 #define SPI1_CS1_PSR_OFF    PIO_BSR_OFF
00294 #endif
00295 
00296 #ifndef SPI1_CS2_PIN
00297 #define SPI1_CS2_PIN        _BV(PA26_SPI1_NPCS2_B)
00298 #define SPI1_CS2_PIO_BASE   PIOA_BASE
00299 #define SPI1_CS2_PSR_OFF    PIO_BSR_OFF
00300 #endif
00301 
00302 #ifndef SPI1_CS3_PIN
00303 #define SPI1_CS3_PIN        _BV(PA29_SPI1_NPCS3_B)
00304 #define SPI1_CS3_PIO_BASE   PIOA_BASE
00305 #define SPI1_CS3_PSR_OFF    PIO_BSR_OFF
00306 #endif
00307 
00312 #define PB0_ETXCK_EREFCK_A  0
00313 #define PB1_ETXEN_A         1
00314 #define PB2_ETX0_A          2
00315 #define PB3_ETX1_A          3
00316 #define PB4_ECRS_A          4
00317 #define PB5_ERX0_A          5
00318 #define PB6_ERX1_A          6
00319 #define PB7_ERXER_A         7
00320 #define PB8_EMDC_A          8
00321 #define PB9_EMDIO_A         9
00322 #define PB10_ETX2_A         10
00323 #define PB11_ETX3_A         11
00324 #define PB12_ETXER_A        12
00325 #define PB13_ERX2_A         13
00326 #define PB14_ERX3_A         14
00327 #define PB15_ERXDV_ECRSDV_A 15
00328 #define PB16_ECOL_A         16
00329 #define PB17_ERXCK_A        17
00330 #define PB18_EF100_A        18
00331 
00335 #define PA27_DRXD_A         27
00336 #define PA28_DTXD_A         28
00337 
00341 #define PA23_TD_A           23  
00342 #define PA24_RD_A           24  
00343 #define PA22_TK_A           22  
00344 #define PA25_RK_A           25  
00345 #define PA21_TF_A           21  
00346 #define PA26_RF_A           26  
00348 
00349 
00351 #define PA10_TWD_A          10  
00352 #define PA11_TWCK_A         11  
00354 
00355 
00357 #define PB23_TIOA0_A        23
00358 #define PB24_TIOB0_A        24
00359 #define PB12_TCLK0_B        12
00360 
00361 #define PB25_TIOA1_A        25
00362 #define PB26_TIOB1_A        26
00363 #define PB19_TCLK1_B        19
00364 
00365 #define PB27_TIOA2_A        27
00366 #define PB28_TIOB2_A        28
00367 #define PA15_TCLK2_B        15
00368 
00372 #define PB0_PCK0_B          0
00373 #define PB20_PCK0_B         20
00374 #define PA13_PCK1_B         13
00375 #define PB29_PCK1_A         29
00376 #define PB21_PCK1_B         21
00377 #define PA30_PCK2_B         30
00378 #define PB30_PCK2_A         30
00379 #define PB22_PCK2_B         22
00380 #define PA27_PCK3_B         27
00381 
00385 #define PA29_FIQ_A          29
00386 #define PA30_IRQ0_A         30
00387 #define PA14_IRQ1_B         14
00388 
00392 #define PB18_ADTRG_B        18  
00394 
00395 
00397 #define PA19_CANRX_A        19
00398 #define PA20_CANTX_A        20
00399 
00403 #define PB19_PWM0_A         19
00404 #define PB27_PWM0_B         27
00405 #define PB20_PWM1_A         20
00406 #define PB28_PWM1_B         28
00407 #define PB21_PWM2_A         21
00408 #define PB29_PWM2_B         29
00409 #define PB22_PWM3_A         22
00410 #define PB30_PWM3_B         30
00411 
00413 
00415 #endif                          /* _ARCH_ARM_AT91SAM7X_H_ */

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