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00044 #include <cfg/arch/avr.h>
00045 #include <cfg/audio.h>
00046
00047 #include <sys/atom.h>
00048 #include <sys/event.h>
00049 #include <sys/timer.h>
00050 #include <sys/heap.h>
00051
00052 #include <dev/irqreg.h>
00053 #include <dev/vs10xx.h>
00054
00055 #include <sys/bankmem.h>
00056
00057 #include <stddef.h>
00058
00063
00064 #if !defined(AUDIO_VS1001K) && !defined(AUDIO_VS1011E) && !defined(AUDIO_VS1002D) && !defined(AUDIO_VS1003B) && !defined(AUDIO_VS1033C)
00065 #define AUDIO_VS1001K
00066 #endif
00067
00068 #ifndef VS10XX_FREQ
00069
00070 #define VS10XX_FREQ 12288000UL
00071 #endif
00072
00073 #ifndef VS10XX_HWRST_DURATION
00074
00075 #define VS10XX_HWRST_DURATION 1
00076 #endif
00077
00078 #ifndef VS10XX_HWRST_RECOVER
00079
00080 #define VS10XX_HWRST_RECOVER 4
00081 #endif
00082
00083 #ifndef VS10XX_SWRST_RECOVER
00084
00085 #define VS10XX_SWRST_RECOVER 2
00086 #endif
00087
00088 #ifndef VS10XX_SCI_MODE
00089 #define VS10XX_SCI_MODE 0
00090 #endif
00091
00092 #ifndef VS10XX_SCI_RATE
00093 #define VS10XX_SCI_RATE (VS10XX_FREQ / 4)
00094 #endif
00095
00096 #ifndef VS10XX_SDI_MODE
00097 #define VS10XX_SDI_MODE 0
00098 #endif
00099
00100 #ifndef VS10XX_SDI_RATE
00101 #define VS10XX_SDI_RATE (VS10XX_FREQ / 4)
00102 #endif
00103
00104 #if defined(VS10XX_SCI_SPI0_DEVICE)
00105
00106 #include <dev/sppif0.h>
00107 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00108 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, act)
00109 #else
00110 #define SciReset(act) Sppi0ChipReset(VS10XX_SCI_SPI0_DEVICE, !act)
00111 #endif
00112 #define SciSetMode() Sppi0SetMode(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_MODE)
00113 #define SciSetSpeed() Sppi0SetSpeed(VS10XX_SCI_SPI0_DEVICE, VS10XX_SCI_RATE)
00114 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00115 #define SciSelect() Sppi0SelectDevice(VS10XX_SCI_SPI0_DEVICE)
00116 #define SciDeselect() Sppi0DeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00117 #else
00118 #define SciSelect() Sppi0NegSelectDevice(VS10XX_SCI_SPI0_DEVICE)
00119 #define SciDeselect() Sppi0NegDeselectDevice(VS10XX_SCI_SPI0_DEVICE)
00120 #endif
00121 #define SciByte Sppi0Byte
00122
00123 #elif defined(VS10XX_SCI_SBBI0_DEVICE)
00124
00125 #include <dev/sbbif0.h>
00126 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00127 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, act)
00128 #else
00129 #define SciReset(act) Sbbi0ChipReset(VS10XX_SCI_SBBI0_DEVICE, !act)
00130 #endif
00131 #define SciSetMode() Sbbi0SetMode(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_MODE)
00132 #define SciSetSpeed() Sbbi0SetSpeed(VS10XX_SCI_SBBI0_DEVICE, VS10XX_SCI_RATE)
00133 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00134 #define SciSelect() Sbbi0SelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00135 #define SciDeselect() Sbbi0DeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00136 #else
00137 #define SciSelect() Sbbi0NegSelectDevice(VS10XX_SCI_SBBI0_DEVICE)
00138 #define SciDeselect() Sbbi0NegDeselectDevice(VS10XX_SCI_SBBI0_DEVICE)
00139 #endif
00140 #define SciByte Sbbi0Byte
00141
00142 #elif defined(VS10XX_SCI_SBBI1_DEVICE)
00143
00144 #include <dev/sbbif1.h>
00145 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00146 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, act)
00147 #else
00148 #define SciReset(act) Sbbi1ChipReset(VS10XX_SCI_SBBI1_DEVICE, !act)
00149 #endif
00150 #define SciSetMode() Sbbi1SetMode(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_MODE)
00151 #define SciSetSpeed() Sbbi1SetSpeed(VS10XX_SCI_SBBI1_DEVICE, VS10XX_SCI_RATE)
00152 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00153 #define SciSelect() Sbbi1SelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00154 #define SciDeselect() Sbbi1DeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00155 #else
00156 #define SciSelect() Sbbi1NegSelectDevice(VS10XX_SCI_SBBI1_DEVICE)
00157 #define SciDeselect() Sbbi1NegDeselectDevice(VS10XX_SCI_SBBI1_DEVICE)
00158 #endif
00159 #define SciByte Sbbi1Byte
00160
00161 #elif defined(VS10XX_SCI_SBBI2_DEVICE)
00162
00163 #include <dev/sbbif2.h>
00164 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00165 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, act)
00166 #else
00167 #define SciReset(act) Sbbi2ChipReset(VS10XX_SCI_SBBI2_DEVICE, !act)
00168 #endif
00169 #define SciSetMode() Sbbi2SetMode(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_MODE)
00170 #define SciSetSpeed() Sbbi2SetSpeed(VS10XX_SCI_SBBI2_DEVICE, VS10XX_SCI_RATE)
00171 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00172 #define SciSelect() Sbbi2SelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00173 #define SciDeselect() Sbbi2DeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00174 #else
00175 #define SciSelect() Sbbi2NegSelectDevice(VS10XX_SCI_SBBI2_DEVICE)
00176 #define SciDeselect() Sbbi2NegDeselectDevice(VS10XX_SCI_SBBI2_DEVICE)
00177 #endif
00178 #define SciByte Sbbi2Byte
00179
00180 #elif defined(VS10XX_SCI_SBBI3_DEVICE)
00181
00182 #include <dev/sbbif3.h>
00183 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00184 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, act)
00185 #else
00186 #define SciReset(act) Sbbi3ChipReset(VS10XX_SCI_SBBI3_DEVICE, !act)
00187 #endif
00188 #define SciSetMode() Sbbi3SetMode(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_MODE)
00189 #define SciSetSpeed() Sbbi3SetSpeed(VS10XX_SCI_SBBI3_DEVICE, VS10XX_SCI_RATE)
00190 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00191 #define SciSelect() Sbbi3SelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00192 #define SciDeselect() Sbbi3DeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00193 #else
00194 #define SciSelect() Sbbi3NegSelectDevice(VS10XX_SCI_SBBI3_DEVICE)
00195 #define SciDeselect() Sbbi3NegDeselectDevice(VS10XX_SCI_SBBI3_DEVICE)
00196 #endif
00197 #define SciByte Sbbi3Byte
00198
00199 #endif
00200
00201
00202 #if defined(VS10XX_SDI_SPI0_DEVICE)
00203
00204 #include <dev/sppif0.h>
00205 #define SdiSetMode() Sppi0SetMode(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_MODE)
00206 #define SdiSetSpeed() Sppi0SetSpeed(VS10XX_SDI_SPI0_DEVICE, VS10XX_SDI_RATE)
00207 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00208 #define SdiSelect() Sppi0SelectDevice(VS10XX_SDI_SPI0_DEVICE)
00209 #define SdiDeselect() Sppi0DeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00210 #else
00211 #define SdiSelect() Sppi0NegSelectDevice(VS10XX_SDI_SPI0_DEVICE)
00212 #define SdiDeselect() Sppi0NegDeselectDevice(VS10XX_SDI_SPI0_DEVICE)
00213 #endif
00214 #define SdiByte Sppi0Byte
00215
00216 #elif defined(VS10XX_SDI_SBBI0_DEVICE)
00217
00218 #include <dev/sbbif0.h>
00219 #define SdiSetMode() Sbbi0SetMode(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_MODE)
00220 #define SdiSetSpeed() Sbbi0SetSpeed(VS10XX_SDI_SBBI0_DEVICE, VS10XX_SDI_RATE)
00221 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00222 #define SdiSelect() Sbbi0SelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00223 #define SdiDeselect() Sbbi0DeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00224 #else
00225 #define SdiSelect() Sbbi0NegSelectDevice(VS10XX_SDI_SBBI0_DEVICE)
00226 #define SdiDeselect() Sbbi0NegDeselectDevice(VS10XX_SDI_SBBI0_DEVICE)
00227 #endif
00228 #define SdiByte Sbbi0Byte
00229
00230 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00231
00232 #include <dev/sbbif1.h>
00233 #define SdiSetMode() Sbbi1SetMode(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_MODE)
00234 #define SdiSetSpeed() Sbbi1SetSpeed(VS10XX_SDI_SBBI1_DEVICE, VS10XX_SDI_RATE)
00235 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00236 #define SdiSelect() Sbbi1SelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00237 #define SdiDeselect() Sbbi1DeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00238 #else
00239 #define SdiSelect() Sbbi1NegSelectDevice(VS10XX_SDI_SBBI1_DEVICE)
00240 #define SdiDeselect() Sbbi1NegDeselectDevice(VS10XX_SDI_SBBI1_DEVICE)
00241 #endif
00242 #define SdiByte Sbbi1Byte
00243
00244 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00245
00246 #include <dev/sbbif2.h>
00247 #define SdiSetMode() Sbbi2SetMode(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_MODE)
00248 #define SdiSetSpeed() Sbbi2SetSpeed(VS10XX_SDI_SBBI2_DEVICE, VS10XX_SDI_RATE)
00249 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00250 #define SdiSelect() Sbbi2SelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00251 #define SdiDeselect() Sbbi2DeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00252 #else
00253 #define SdiSelect() Sbbi2NegSelectDevice(VS10XX_SDI_SBBI2_DEVICE)
00254 #define SdiDeselect() Sbbi2NegDeselectDevice(VS10XX_SDI_SBBI2_DEVICE)
00255 #endif
00256 #define SdiByte Sbbi2Byte
00257
00258 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00259
00260 #include <dev/sbbif3.h>
00261 #define SdiSetMode() Sbbi3SetMode(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_MODE)
00262 #define SdiSetSpeed() Sbbi3SetSpeed(VS10XX_SDI_SBBI3_DEVICE, VS10XX_SDI_RATE)
00263 #if defined(VS10XX_SELECT_ACTIVE_HIGH)
00264 #define SdiSelect() Sbbi3SelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00265 #define SdiDeselect() Sbbi3DeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00266 #else
00267 #define SdiSelect() Sbbi3NegSelectDevice(VS10XX_SDI_SBBI3_DEVICE)
00268 #define SdiDeselect() Sbbi3NegDeselectDevice(VS10XX_SDI_SBBI3_DEVICE)
00269 #endif
00270 #define SdiByte Sbbi3Byte
00271
00272 #endif
00273
00274
00275
00276
00277 #if defined (MCU_AT91R40008) || defined (MCU_AT91SAM7X256) || defined (MCU_AT91SAM9260)
00278
00279 #if VS10XX_DREQ_BIT == 9
00280 #define VS10XX_SIGNAL sig_INTERRUPT0
00281 #else
00282 #define VS10XX_SIGNAL sig_INTERRUPT2
00283 #endif
00284
00285 #if defined(VS10XX_XCS_BIT)
00286
00287 #if !defined(VS10XX_XCS_PIO_ID)
00288 #define VS10XX_XCS_PE_REG PIO_PER
00289 #define VS10XX_XCS_OE_REG PIO_OER
00290 #define VS10XX_XCS_COD_REG PIO_CODR
00291 #define VS10XX_XCS_SOD_REG PIO_SODR
00292 #elif VS10XX_XCS_PIO_ID == PIOA_ID
00293 #define VS10XX_XCS_PE_REG PIOA_PER
00294 #define VS10XX_XCS_OE_REG PIOA_OER
00295 #define VS10XX_XCS_COD_REG PIOA_CODR
00296 #define VS10XX_XCS_SOD_REG PIOA_SODR
00297 #elif VS10XX_XCS_PIO_ID == PIOB_ID
00298 #define VS10XX_XCS_PE_REG PIOB_PER
00299 #define VS10XX_XCS_OE_REG PIOB_OER
00300 #define VS10XX_XCS_COD_REG PIOB_CODR
00301 #define VS10XX_XCS_SOD_REG PIOB_SODR
00302 #elif VS10XX_XCS_PIO_ID == PIOC_ID
00303 #define VS10XX_XCS_PE_REG PIOC_PER
00304 #define VS10XX_XCS_OE_REG PIOC_OER
00305 #define VS10XX_XCS_COD_REG PIOC_CODR
00306 #define VS10XX_XCS_SOD_REG PIOC_SODR
00307 #endif
00308 #define VS10XX_XCS_ENA() \
00309 outr(VS10XX_XCS_PE_REG, _BV(VS10XX_XCS_BIT)); \
00310 outr(VS10XX_XCS_OE_REG, _BV(VS10XX_XCS_BIT))
00311 #define VS10XX_XCS_CLR() outr(VS10XX_XCS_COD_REG, _BV(VS10XX_XCS_BIT))
00312 #define VS10XX_XCS_SET() outr(VS10XX_XCS_SOD_REG, _BV(VS10XX_XCS_BIT))
00313
00314 #else
00315
00316 #define VS10XX_XCS_ENA()
00317 #define VS10XX_XCS_CLR()
00318 #define VS10XX_XCS_SET()
00319
00320 #endif
00321
00322 #if defined(VS10XX_XDCS_BIT)
00323
00324 #if !defined(VS10XX_XDCS_PIO_ID)
00325 #define VS10XX_XDCS_PE_REG PIO_PER
00326 #define VS10XX_XDCS_OE_REG PIO_OER
00327 #define VS10XX_XDCS_COD_REG PIO_CODR
00328 #define VS10XX_XDCS_SOD_REG PIO_SODR
00329 #elif VS10XX_XDCS_PIO_ID == PIOA_ID
00330 #define VS10XX_XDCS_PE_REG PIOA_PER
00331 #define VS10XX_XDCS_OE_REG PIOA_OER
00332 #define VS10XX_XDCS_COD_REG PIOA_CODR
00333 #define VS10XX_XDCS_SOD_REG PIOA_SODR
00334 #elif VS10XX_XDCS_PIO_ID == PIOB_ID
00335 #define VS10XX_XDCS_PE_REG PIOB_PER
00336 #define VS10XX_XDCS_OE_REG PIOB_OER
00337 #define VS10XX_XDCS_COD_REG PIOB_CODR
00338 #define VS10XX_XDCS_SOD_REG PIOB_SODR
00339 #elif VS10XX_XDCS_PIO_ID == PIOC_ID
00340 #define VS10XX_XDCS_PE_REG PIOC_PER
00341 #define VS10XX_XDCS_OE_REG PIOC_OER
00342 #define VS10XX_XDCS_COD_REG PIOC_CODR
00343 #define VS10XX_XDCS_SOD_REG PIOC_SODR
00344 #endif
00345 #define VS10XX_XDCS_ENA() \
00346 outr(VS10XX_XDCS_PE_REG, _BV(VS10XX_XDCS_BIT)); \
00347 outr(VS10XX_XDCS_OE_REG, _BV(VS10XX_XDCS_BIT))
00348 #define VS10XX_XDCS_CLR() outr(VS10XX_XDCS_COD_REG, _BV(VS10XX_XDCS_BIT))
00349 #define VS10XX_XDCS_SET() outr(VS10XX_XDCS_SOD_REG, _BV(VS10XX_XDCS_BIT))
00350
00351 #else
00352
00353 #define VS10XX_XDCS_ENA()
00354 #define VS10XX_XDCS_CLR()
00355 #define VS10XX_XDCS_SET()
00356
00357 #endif
00358
00359 #if defined(VS10XX_DREQ_BIT)
00360
00361 #if !defined(VS10XX_DREQ_PIO_ID)
00362 #define VS10XX_DREQ_PE_REG PIO_PER
00363 #define VS10XX_DREQ_OD_REG PIO_ODR
00364 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00365 #elif VS10XX_DREQ_PIO_ID == PIOA_ID
00366 #define VS10XX_DREQ_PE_REG PIOA_PER
00367 #define VS10XX_DREQ_OD_REG PIOA_ODR
00368 #define VS10XX_DREQ_PDS_REG PIOA_PDSR
00369 #elif VS10XX_DREQ_PIO_ID == PIOB_ID
00370 #define VS10XX_DREQ_PE_REG PIOB_PER
00371 #define VS10XX_DREQ_OD_REG PIOB_ODR
00372 #define VS10XX_DREQ_PDS_REG PIOB_PDSR
00373 #elif VS10XX_DREQ_PIO_ID == PIOC_ID
00374 #define VS10XX_DREQ_PE_REG PIOC_PER
00375 #define VS10XX_DREQ_OD_REG PIOC_ODR
00376 #define VS10XX_DREQ_PDS_REG PIOC_PDSR
00377 #endif
00378
00379 #define VS10XX_DREQ_PD_REG PIO_PDR
00380 #define VS10XX_DREQ_OD_REG PIO_ODR
00381 #define VS10XX_DREQ_PDS_REG PIO_PDSR
00382 #define VS10XX_DREQ_ENA() \
00383 outr(VS10XX_DREQ_PD_REG, _BV(VS10XX_DREQ_BIT)); \
00384 outr(VS10XX_DREQ_OD_REG, _BV(VS10XX_DREQ_BIT))
00385 #define VS10XX_DREQ_TST() ((inr(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00386
00387 #else
00388
00389 #define VS10XX_DREQ_ENA()
00390 #define VS10XX_DREQ_TST() 0
00391
00392 #endif
00393
00394 #ifdef VS10XX_BSYNC_BIT
00395
00396 #if !defined(VS10XX_BSYNC_PIO_ID)
00397 #define VS10XX_BSYNC_PE_REG PIO_PER
00398 #define VS10XX_BSYNC_OE_REG PIO_OER
00399 #define VS10XX_BSYNC_COD_REG PIO_CODR
00400 #define VS10XX_BSYNC_SOD_REG PIO_SODR
00401 #elif VS10XX_BSYNC_PIO_ID == PIOA_ID
00402 #define VS10XX_BSYNC_PE_REG PIOA_PER
00403 #define VS10XX_BSYNC_OE_REG PIOA_OER
00404 #define VS10XX_BSYNC_COD_REG PIOA_CODR
00405 #define VS10XX_BSYNC_SOD_REG PIOA_SODR
00406 #elif VS10XX_BSYNC_PIO_ID == PIOB_ID
00407 #define VS10XX_BSYNC_PE_REG PIOB_PER
00408 #define VS10XX_BSYNC_OE_REG PIOB_OER
00409 #define VS10XX_BSYNC_COD_REG PIOB_CODR
00410 #define VS10XX_BSYNC_SOD_REG PIOB_SODR
00411 #elif VS10XX_BSYNC_PIO_ID == PIOC_ID
00412 #define VS10XX_BSYNC_PE_REG PIOC_PER
00413 #define VS10XX_BSYNC_OE_REG PIOC_OER
00414 #define VS10XX_BSYNC_COD_REG PIOC_CODR
00415 #define VS10XX_BSYNC_SOD_REG PIOC_SODR
00416 #endif
00417 #define VS10XX_BSYNC_ENA() \
00418 outr(VS10XX_BSYNC_PE_REG, _BV(VS10XX_BSYNC_BIT)); \
00419 outr(VS10XX_BSYNC_OE_REG, _BV(VS10XX_BSYNC_BIT))
00420 #define VS10XX_BSYNC_CLR() outr(VS10XX_BSYNC_COD_REG, _BV(VS10XX_BSYNC_BIT))
00421 #define VS10XX_BSYNC_SET() outr(VS10XX_BSYNC_SOD_REG, _BV(VS10XX_BSYNC_BIT))
00422
00423 #else
00424
00425 #define VS10XX_BSYNC_ENA()
00426 #define VS10XX_BSYNC_CLR()
00427 #define VS10XX_BSYNC_SET()
00428
00429 #endif
00430
00431
00432
00433
00434
00435 #elif defined(__AVR__)
00436
00437 #if !defined(VS10XX_SIGNAL_IRQ)
00438 #define VS10XX_SIGNAL_IRQ INT6
00439 #endif
00440
00441 #if (VS10XX_SIGNAL_IRQ == INT0)
00442 #define VS10XX_SIGNAL sig_INTERRUPT0
00443 #define VS10XX_DREQ_BIT 0
00444 #define VS10XX_DREQ_PDS_REG PIND
00445 #define VS10XX_DREQ_PUE_REG PORTD
00446 #define VS10XX_DREQ_OE_REG DDRD
00447
00448 #elif (VS10XX_SIGNAL_IRQ == INT1)
00449 #define VS10XX_SIGNAL sig_INTERRUPT1
00450 #define VS10XX_DREQ_BIT 1
00451 #define VS10XX_DREQ_PDS_REG PIND
00452 #define VS10XX_DREQ_PUE_REG PORTD
00453 #define VS10XX_DREQ_OE_REG DDRD
00454
00455 #elif (VS10XX_SIGNAL_IRQ == INT2)
00456 #define VS10XX_SIGNAL sig_INTERRUPT2
00457 #define VS10XX_DREQ_BIT 2
00458 #define VS10XX_DREQ_PDS_REG PIND
00459 #define VS10XX_DREQ_PUE_REG PORTD
00460 #define VS10XX_DREQ_OE_REG DDRD
00461
00462 #elif (VS10XX_SIGNAL_IRQ == INT3)
00463 #define VS10XX_SIGNAL sig_INTERRUPT3
00464 #define VS10XX_DREQ_BIT 3
00465 #define VS10XX_DREQ_PDS_REG PIND
00466 #define VS10XX_DREQ_PUE_REG PORTD
00467 #define VS10XX_DREQ_OE_REG DDRD
00468
00469 #elif (VS10XX_SIGNAL_IRQ == INT4)
00470 #define VS10XX_SIGNAL sig_INTERRUPT4
00471 #define VS10XX_DREQ_BIT 4
00472 #define VS10XX_DREQ_PDS_REG PINE
00473 #define VS10XX_DREQ_PUE_REG PORTE
00474 #define VS10XX_DREQ_OE_REG DDRE
00475
00476 #elif (VS10XX_SIGNAL_IRQ == INT5)
00477 #define VS10XX_SIGNAL sig_INTERRUPT5
00478 #define VS10XX_DREQ_BIT 5
00479 #define VS10XX_DREQ_PDS_REG PINE
00480 #define VS10XX_DREQ_PUE_REG PORTE
00481 #define VS10XX_DREQ_OE_REG DDRE
00482
00483 #elif (VS10XX_SIGNAL_IRQ == INT7)
00484 #define VS10XX_SIGNAL sig_INTERRUPT7
00485 #define VS10XX_DREQ_BIT 7
00486 #define VS10XX_DREQ_PDS_REG PINE
00487 #define VS10XX_DREQ_PUE_REG PORTE
00488 #define VS10XX_DREQ_OE_REG DDRE
00489
00490 #else
00491 #define VS10XX_SIGNAL sig_INTERRUPT6
00492 #define VS10XX_DREQ_BIT 6
00493 #define VS10XX_DREQ_PDS_REG PINE
00494 #define VS10XX_DREQ_PUE_REG PORTE
00495 #define VS10XX_DREQ_OE_REG DDRE
00496
00497 #endif
00498
00499 #define VS10XX_DREQ_ENA() \
00500 cbi(VS10XX_DREQ_OE_REG, VS10XX_DREQ_BIT); \
00501 sbi(VS10XX_DREQ_PUE_REG, VS10XX_DREQ_BIT)
00502 #define VS10XX_DREQ_TST() ((inb(VS10XX_DREQ_PDS_REG) & _BV(VS10XX_DREQ_BIT)) == _BV(VS10XX_DREQ_BIT))
00503
00504
00505 #if defined(VS10XX_XCS_BIT)
00506
00507 #if (VS10XX_XCS_AVRPORT == AVRPORTA)
00508 #define VS10XX_XCS_SOD_REG PORTA
00509 #define VS10XX_XCS_OE_REG DDRA
00510 #elif (VS10XX_XCS_AVRPORT == AVRPORTB)
00511 #define VS10XX_XCS_SOD_REG PORTB
00512 #define VS10XX_XCS_OE_REG DDRB
00513 #elif (VS10XX_XCS_AVRPORT == AVRPORTD)
00514 #define VS10XX_XCS_SOD_REG PORTD
00515 #define VS10XX_XCS_OE_REG DDRD
00516 #elif (VS10XX_XCS_AVRPORT == AVRPORTE)
00517 #define VS10XX_XCS_SOD_REG PORTE
00518 #define VS10XX_XCS_OE_REG DDRE
00519 #elif (VS10XX_XCS_AVRPORT == AVRPORTF)
00520 #define VS10XX_XCS_SOD_REG PORTF
00521 #define VS10XX_XCS_OE_REG DDRF
00522 #elif (VS10XX_XCS_AVRPORT == AVRPORTG)
00523 #define VS10XX_XCS_SOD_REG PORTG
00524 #define VS10XX_XCS_OE_REG DDRG
00525 #elif (VS10XX_XCS_AVRPORT == AVRPORTH)
00526 #define VS10XX_XCS_SOD_REG PORTH
00527 #define VS10XX_XCS_OE_REG DDRH
00528 #endif
00529 #define VS10XX_XCS_ENA() sbi(VS10XX_XCS_OE_REG, VS10XX_XCS_BIT)
00530 #define VS10XX_XCS_CLR() cbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00531 #define VS10XX_XCS_SET() sbi(VS10XX_XCS_SOD_REG, VS10XX_XCS_BIT)
00532
00533 #else
00534
00535 #define VS10XX_XCS_ENA()
00536 #define VS10XX_XCS_CLR()
00537 #define VS10XX_XCS_SET()
00538
00539 #endif
00540
00541 #if defined(VS10XX_XDCS_BIT)
00542
00543 #if (VS10XX_XDCS_AVRPORT == AVRPORTA)
00544 #define VS10XX_XDCS_SOD_REG PORTA
00545 #define VS10XX_XDCS_OE_REG DDRA
00546 #elif (VS10XX_XDCS_AVRPORT == AVRPORTB)
00547 #define VS10XX_XDCS_SOD_REG PORTB
00548 #define VS10XX_XDCS_OE_REG DDRB
00549 #elif (VS10XX_XDCS_AVRPORT == AVRPORTD)
00550 #define VS10XX_XDCS_SOD_REG PORTD
00551 #define VS10XX_XDCS_OE_REG DDRD
00552 #elif (VS10XX_XDCS_AVRPORT == AVRPORTE)
00553 #define VS10XX_XDCS_SOD_REG PORTE
00554 #define VS10XX_XDCS_OE_REG DDRE
00555 #elif (VS10XX_XDCS_AVRPORT == AVRPORTF)
00556 #define VS10XX_XDCS_SOD_REG PORTF
00557 #define VS10XX_XDCS_OE_REG DDRF
00558 #elif (VS10XX_XDCS_AVRPORT == AVRPORTG)
00559 #define VS10XX_XDCS_SOD_REG PORTG
00560 #define VS10XX_XDCS_OE_REG DDRG
00561 #elif (VS10XX_XDCS_AVRPORT == AVRPORTH)
00562 #define VS10XX_XDCS_SOD_REG PORTH
00563 #define VS10XX_XDCS_OE_REG DDRH
00564 #endif
00565 #define VS10XX_XDCS_ENA() sbi(VS10XX_XDCS_OE_REG, VS10XX_XDCS_BIT)
00566 #define VS10XX_XDCS_CLR() cbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00567 #define VS10XX_XDCS_SET() sbi(VS10XX_XDCS_SOD_REG, VS10XX_XDCS_BIT)
00568
00569 #else
00570
00571 #define VS10XX_XDCS_ENA()
00572 #define VS10XX_XDCS_CLR()
00573 #define VS10XX_XDCS_SET()
00574
00575 #endif
00576
00577
00578 #if defined(VS10XX_BSYNC_BIT)
00579
00580 #if (VS10XX_BSYNC_AVRPORT == AVRPORTA)
00581 #define VS10XX_BSYNC_SOD_REG PORTA
00582 #define VS10XX_BSYNC_OE_REG DDRA
00583 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTB)
00584 #define VS10XX_BSYNC_SOD_REG PORTB
00585 #define VS10XX_BSYNC_OE_REG DDRB
00586 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTD)
00587 #define VS10XX_BSYNC_SOD_REG PORTD
00588 #define VS10XX_BSYNC_OE_REG DDRD
00589 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTE)
00590 #define VS10XX_BSYNC_SOD_REG PORTE
00591 #define VS10XX_BSYNC_OE_REG DDRE
00592 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTF)
00593 #define VS10XX_BSYNC_SOD_REG PORTF
00594 #define VS10XX_BSYNC_OE_REG DDRF
00595 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTG)
00596 #define VS10XX_BSYNC_SOD_REG PORTG
00597 #define VS10XX_BSYNC_OE_REG DDRG
00598 #elif (VS10XX_BSYNC_AVRPORT == AVRPORTH)
00599 #define VS10XX_BSYNC_SOD_REG PORTH
00600 #define VS10XX_BSYNC_OE_REG DDRH
00601 #endif
00602 #define VS10XX_BSYNC_ENA() sbi(VS10XX_BSYNC_OE_REG, VS10XX_BSYNC_BIT)
00603 #define VS10XX_BSYNC_CLR() cbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00604 #define VS10XX_BSYNC_SET() sbi(VS10XX_BSYNC_SOD_REG, VS10XX_BSYNC_BIT)
00605
00606 #else
00607
00608 #define VS10XX_BSYNC_ENA()
00609 #define VS10XX_BSYNC_CLR()
00610 #define VS10XX_BSYNC_SET()
00611
00612 #endif
00613
00614
00615
00616
00617
00618 #endif
00619
00620
00621 static volatile ureg_t vs_status = VS_STATUS_STOPPED;
00622 static volatile u_int vs_flush;
00623
00624
00625
00626
00627
00628
00629
00630
00631
00632 static INLINE void VsSdiPutByte(ureg_t b)
00633 {
00634 #if defined(VS10XX_BSYNC_BIT)
00635
00636 #if defined(VS10XX_SDI_SBBI0_DEVICE)
00637 ureg_t mask;
00638
00639 VS10XX_BSYNC_SET();
00640
00641 for (mask = 0x80; mask; mask >>= 1) {
00642 SBBI0_SCK_CLR();
00643 if (b & mask) {
00644 SBBI0_MOSI_SET();
00645 }
00646 else {
00647 SBBI0_MOSI_CLR();
00648 }
00649 SBBI0_SCK_SET();
00650 if (mask & 0x40) {
00651 VS10XX_BSYNC_CLR();
00652 }
00653 }
00654 SBBI0_SCK_CLR();
00655 #elif defined(VS10XX_SDI_SBBI1_DEVICE)
00656 ureg_t mask;
00657
00658 VS10XX_BSYNC_SET();
00659
00660 for (mask = 0x80; mask; mask >>= 1) {
00661 SBBI1_SCK_CLR();
00662 if (b & mask) {
00663 SBBI1_MOSI_SET();
00664 }
00665 else {
00666 SBBI1_MOSI_CLR();
00667 }
00668 SBBI1_SCK_SET();
00669 if (mask & 0x40) {
00670 VS10XX_BSYNC_CLR();
00671 }
00672 }
00673 SBBI1_SCK_CLR();
00674 #elif defined(VS10XX_SDI_SBBI2_DEVICE)
00675 ureg_t mask;
00676
00677 VS10XX_BSYNC_SET();
00678
00679 for (mask = 0x80; mask; mask >>= 1) {
00680 SBBI2_SCK_CLR();
00681 if (b & mask) {
00682 SBBI2_MOSI_SET();
00683 }
00684 else {
00685 SBBI2_MOSI_CLR();
00686 }
00687 SBBI2_SCK_SET();
00688 if (mask & 0x40) {
00689 VS10XX_BSYNC_CLR();
00690 }
00691 }
00692 SBBI2_SCK_CLR();
00693 #elif defined(VS10XX_SDI_SBBI3_DEVICE)
00694 ureg_t mask;
00695
00696 VS10XX_BSYNC_SET();
00697
00698 for (mask = 0x80; mask; mask >>= 1) {
00699 SBBI3_SCK_CLR();
00700 if (b & mask) {
00701 SBBI3_MOSI_SET();
00702 }
00703 else {
00704 SBBI3_MOSI_CLR();
00705 }
00706 SBBI3_SCK_SET();
00707 if (mask & 0x40) {
00708 VS10XX_BSYNC_CLR();
00709 }
00710 }
00711 SBBI3_SCK_CLR();
00712 #elif defined(VS10XX_SDI_SPI0_DEVICE)
00713 VS10XX_BSYNC_SET();
00714
00715 outb(SPDR, b);
00716
00717 _NOP();
00718 _NOP();
00719 _NOP();
00720 _NOP();
00721 VS10XX_BSYNC_CLR();
00722
00723
00724 loop_until_bit_is_set(SPSR, SPIF);
00725 #endif
00726
00727 #else
00728
00729 SdiByte(b);
00730
00731 #endif
00732
00733 }
00734
00746 ureg_t VsPlayerInterrupts(ureg_t enable)
00747 {
00748 static ureg_t is_enabled = 0;
00749 ureg_t rc;
00750
00751 rc = is_enabled;
00752 if(enable) {
00753 VS10XX_DREQ_ENA();
00754 NutIrqEnable(&VS10XX_SIGNAL);
00755 }
00756 else {
00757 NutIrqDisable(&VS10XX_SIGNAL);
00758 }
00759 is_enabled = enable;
00760
00761 return rc;
00762 }
00763
00788 ureg_t VsPlayerThrottle(ureg_t on)
00789 {
00790 static ureg_t is_throttled = 0;
00791 ureg_t rc;
00792
00793 rc = is_throttled;
00794 if(on) {
00795 VS10XX_XDCS_SET();
00796 SdiDeselect();
00797 }
00798 else {
00799 VS10XX_XDCS_CLR();
00800 SdiSelect();
00801 }
00802 is_throttled = on;
00803
00804 return rc;
00805 }
00806
00810 static void VsSciSelect(ureg_t on)
00811 {
00812 if (on) {
00813
00814 SdiDeselect();
00815
00816 #if defined(VS10XX_SDI_SPI0_DEVICE) && !defined(VS10XX_SCI_SPI0_DEVICE)
00817
00818
00819
00820 cbi(SPCR, SPE);
00821 #endif
00822
00823
00824 VS10XX_XDCS_SET();
00825
00826 VS10XX_XCS_CLR();
00827
00828 SciSelect();
00829 }
00830 else {
00831
00832 SciDeselect();
00833
00834 VS10XX_XCS_SET();
00835
00836 VS10XX_XDCS_CLR();
00837
00838 SdiSelect();
00839 }
00840 }
00841
00848 static int VsWaitReady(void)
00849 {
00850 int tmo;
00851
00852 for (tmo = 0; tmo < 5000; tmo++) {
00853 if (VS10XX_DREQ_TST()) {
00854 return 0;
00855 }
00856 }
00857 return -1;
00858 }
00859
00860
00861
00862
00863
00864
00865
00866 static int VsSdiWrite(CONST u_char * data, size_t len)
00867 {
00868 while (len--) {
00869 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00870 return -1;
00871 }
00872 VsSdiPutByte(*data);
00873 data++;
00874 }
00875 return 0;
00876 }
00877
00878
00879
00880
00881
00882
00883
00884
00885 static int VsSdiWrite_P(PGM_P data, size_t len)
00886 {
00887 while (len--) {
00888 if (!VS10XX_DREQ_TST() && VsWaitReady()) {
00889 return -1;
00890 }
00891 VsSdiPutByte(PRG_RDB(data));
00892 data++;
00893 }
00894 return 0;
00895 }
00896
00897
00898
00899
00900
00901
00902 static void VsRegWrite(ureg_t reg, u_short data)
00903 {
00904
00905 VsWaitReady();
00906 VsSciSelect(1);
00907
00908
00909
00910
00911
00912
00913 SciByte(VS_OPCODE_WRITE);
00914 SciByte((u_char) reg);
00915 SciByte((u_char) (data >> 8));
00916 SciByte((u_char) data);
00917
00918
00919 VsSciSelect(0);
00920 }
00921
00922
00923
00924
00925
00926
00927
00928
00929 static u_short VsRegRead(ureg_t reg)
00930 {
00931 u_short data;
00932
00933
00934 VsWaitReady();
00935 VsSciSelect(1);
00936
00937 SciByte(VS_OPCODE_READ);
00938 SciByte((u_char) reg);
00939 data = (u_short)SciByte(0) << 8;
00940 data |= SciByte(0);
00941
00942
00943 VsSciSelect(0);
00944
00945 return data;
00946 }
00947
00948
00949
00950
00951
00952
00953
00954
00955 static void VsPlayerFeed(void *arg)
00956 {
00957 ureg_t j = 32;
00958 size_t total = 0;
00959
00960 if (!VS10XX_DREQ_TST()) {
00961 return;
00962 }
00963
00964
00965
00966
00967 if (vs_status == VS_STATUS_RUNNING) {
00968 char *bp = 0;
00969 size_t consumed = 0;
00970 size_t available = 0;
00971 do {
00972 if(consumed >= available) {
00973
00974 if(consumed) {
00975 NutSegBufReadCommit(consumed);
00976 consumed = 0;
00977 }
00978
00979 bp = NutSegBufReadRequest(&available);
00980 if(available == 0) {
00981
00982 vs_status = VS_STATUS_EOF;
00983 break;
00984 }
00985 }
00986
00987 VsSdiPutByte(*bp);
00988 bp++;
00989 consumed++;
00990 total++;
00991 if (total > 4096) {
00992 vs_status = VS_STATUS_EOF;
00993 break;
00994 }
00995
00996
00997
00998 if (VS10XX_DREQ_TST()) {
00999 j = 32;
01000 }
01001 } while(j--);
01002
01003
01004 NutSegBufReadLast(consumed);
01005 }
01006
01007
01008
01009
01010 if(vs_status != VS_STATUS_RUNNING && vs_flush) {
01011 do {
01012 VsSdiPutByte(0);
01013 if (--vs_flush == 0) {
01014
01015 vs_status = VS_STATUS_EMPTY;
01016 break;
01017 }
01018
01019
01020 if (VS10XX_DREQ_TST()) {
01021 j = 32;
01022 }
01023 } while(j--);
01024 }
01025 }
01026
01038 int VsPlayerKick(void)
01039 {
01040
01041
01042
01043 VsPlayerInterrupts(0);
01044 vs_status = VS_STATUS_RUNNING;
01045 VsPlayerFeed(NULL);
01046 VsPlayerInterrupts(1);
01047
01048 return 0;
01049 }
01050
01059 int VsPlayerStop(void)
01060 {
01061 ureg_t ief;
01062
01063 ief = VsPlayerInterrupts(0);
01064
01065 if (vs_status == VS_STATUS_RUNNING) {
01066 vs_status = VS_STATUS_STOPPED;
01067 }
01068 VsPlayerInterrupts(ief);
01069
01070 return 0;
01071 }
01072
01073
01086 int VsPlayerFlush(void)
01087 {
01088 VsPlayerInterrupts(0);
01089
01090 if (vs_status != VS_STATUS_EMPTY || NutSegBufUsed()) {
01091 if (vs_flush == 0) {
01092 vs_flush = VS_FLUSH_BYTES;
01093 }
01094
01095 if (vs_status != VS_STATUS_RUNNING) {
01096 VsPlayerKick();
01097 }
01098 }
01099 VsPlayerInterrupts(1);
01100
01101 return 0;
01102 }
01103
01109 int VsPlayerInit(void)
01110 {
01111
01112 VsPlayerInterrupts(0);
01113
01114
01115 SciReset(1);
01116
01117
01118 if (SciSetMode()) {
01119 return -1;
01120 }
01121 SciSetSpeed();
01122 SciDeselect();
01123
01124
01125 if (SdiSetMode()) {
01126 return -1;
01127 }
01128 SdiSetSpeed();
01129 SdiDeselect();
01130
01131
01132 VS10XX_BSYNC_CLR();
01133 VS10XX_BSYNC_ENA();
01134
01135
01136 VS10XX_XDCS_SET();
01137 VS10XX_XDCS_ENA();
01138
01139
01140 VS10XX_XCS_SET();
01141 VS10XX_XCS_ENA();
01142
01143
01144 VS10XX_DREQ_ENA();
01145
01146
01147 if (NutRegisterIrqHandler(&VS10XX_SIGNAL, VsPlayerFeed, NULL)) {
01148 return -1;
01149 }
01150
01151
01152 NutIrqSetMode(&VS10XX_SIGNAL, NUT_IRQMODE_RISINGEDGE);
01153
01154
01155 SciReset(0);
01156 NutDelay(VS10XX_HWRST_RECOVER);
01157
01158 return VsPlayerReset(0);
01159 }
01160
01187 int VsPlayerReset(u_short mode)
01188 {
01189
01190 VsPlayerInterrupts(0);
01191 vs_status = VS_STATUS_STOPPED;
01192
01193
01194 #if defined(VS10XX_BSYNC_BIT)
01195 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01196 #else
01197 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01198 #endif
01199
01200 NutDelay(VS10XX_SWRST_RECOVER);
01201
01202
01203
01204
01205 if ((mode & VS_SM_RESET) != 0 || !VS10XX_DREQ_TST()) {
01206
01207 SciReset(1);
01208
01209 NutDelay(VS10XX_HWRST_DURATION);
01210 SciReset(0);
01211
01212 NutDelay(VS10XX_HWRST_RECOVER);
01213
01214
01215 #if defined(VS10XX_BSYNC_BIT)
01216 VsRegWrite(VS_MODE_REG, VS_SM_RESET | mode);
01217 #else
01218 VsRegWrite(VS_MODE_REG, VS_SM_RESET | VS_SM_SDINEW | mode);
01219 #endif
01220 NutDelay(VS10XX_SWRST_RECOVER);
01221 if (!VS10XX_DREQ_TST()) {
01222 return -1;
01223 }
01224 }
01225
01226 #if VS10XX_FREQ < 20000000UL
01227 VsRegWrite(VS_CLOCKF_REG, (u_short)(VS_CF_DOUBLER | (VS10XX_FREQ / 2000UL)));
01228 #else
01229 VsRegWrite(VS_CLOCKF_REG, (u_short)(VS10XX_FREQ / 2000UL));
01230 #endif
01231 #if defined(AUDIO_VS1001K)
01232
01233 xVsRegWrite(VS_INT_FCTLH_REG, 0x8008);
01234 #endif
01235 NutDelay(1);
01236
01237 #if defined(VS10XX_SDI_SPI0_DEVICE) || defined(VS10XX_SCI_SPI0_DEVICE)
01238
01239 outb(EIFR, BV(VS10XX_DREQ_BIT));
01240 #endif
01241
01242 return 0;
01243 }
01244
01268 int VsPlayerSetMode(u_short mode)
01269 {
01270 ureg_t ief;
01271
01272 ief = VsPlayerInterrupts(0);
01273 #if defined(VS10XX_BSYNC_BIT)
01274 VsRegWrite(VS_MODE_REG, mode);
01275 #else
01276 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW | mode);
01277 #endif
01278 VsPlayerInterrupts(ief);
01279
01280 return 0;
01281 }
01282
01288 u_short VsPlayTime(void)
01289 {
01290 u_short rc;
01291 ureg_t ief;
01292
01293 ief = VsPlayerInterrupts(0);
01294 rc = VsRegRead(VS_DECODE_TIME_REG);
01295 VsPlayerInterrupts(ief);
01296
01297 return rc;
01298 }
01299
01309 u_int VsGetStatus(void)
01310 {
01311 return vs_status;
01312 }
01313
01314 #ifdef __GNUC__
01315
01323 int VsGetHeaderInfo(VS_HEADERINFO * vshi)
01324 {
01325 u_short *usp = (u_short *) vshi;
01326 ureg_t ief;
01327
01328 ief = VsPlayerInterrupts(0);
01329 *usp = VsRegRead(VS_HDAT1_REG);
01330 *++usp = VsRegRead(VS_HDAT0_REG);
01331 VsPlayerInterrupts(ief);
01332
01333 return 0;
01334 }
01335 #endif
01336
01349 u_short VsMemoryTest(void)
01350 {
01351 u_short rc;
01352 ureg_t ief;
01353 static prog_char mtcmd[] = { 0x4D, 0xEA, 0x6D, 0x54, 0x00, 0x00, 0x00, 0x00 };
01354
01355 ief = VsPlayerInterrupts(0);
01356 #if defined(VS10XX_BSYNC_BIT)
01357 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01358 #else
01359 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01360 #endif
01361 VsSdiWrite_P(mtcmd, sizeof(mtcmd));
01362 while(((rc = VsRegRead(VS_HDAT0_REG)) & 0x8000) == 0) {
01363 NutDelay(1);
01364 }
01365 #if defined(VS10XX_BSYNC_BIT)
01366 VsRegWrite(VS_MODE_REG, 0);
01367 #else
01368 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01369 #endif
01370 VsPlayerInterrupts(ief);
01371
01372 return rc;
01373 }
01374
01384 int VsSetVolume(ureg_t left, ureg_t right)
01385 {
01386 ureg_t ief;
01387
01388 ief = VsPlayerInterrupts(0);
01389 VsRegWrite(VS_VOL_REG, ((u_short)left << VS_VOL_LEFT_LSB) | ((u_short)right << VS_VOL_RIGHT_LSB));
01390 VsPlayerInterrupts(ief);
01391
01392 return 0;
01393 }
01394
01403 int VsBeep(u_char fsin, u_char ms)
01404 {
01405 ureg_t ief;
01406 static prog_char on[] = { 0x53, 0xEF, 0x6E };
01407 static prog_char off[] = { 0x45, 0x78, 0x69, 0x74 };
01408 static prog_char end[] = { 0x00, 0x00, 0x00, 0x00 };
01409
01410
01411 ief = VsPlayerInterrupts(0);
01412
01413 #if defined(VS10XX_BSYNC_BIT)
01414 VsRegWrite(VS_MODE_REG, VS_SM_TESTS);
01415 #else
01416 VsRegWrite(VS_MODE_REG, VS_SM_TESTS | VS_SM_SDINEW);
01417 #endif
01418
01419 fsin = 56 + (fsin & 7) * 9;
01420 VsSdiWrite_P(on, sizeof(on));
01421 VsSdiWrite(&fsin, 1);
01422 VsSdiWrite_P(end, sizeof(end));
01423 NutDelay(ms);
01424 VsSdiWrite_P(off, sizeof(off));
01425 VsSdiWrite_P(end, sizeof(end));
01426
01427 #if defined(VS10XX_BSYNC_BIT)
01428 VsRegWrite(VS_MODE_REG, 0);
01429 #else
01430 VsRegWrite(VS_MODE_REG, VS_SM_SDINEW);
01431 #endif
01432
01433
01434 VsPlayerInterrupts(ief);
01435
01436 return 0;
01437 }
01438
01439