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* AT91
[ArchitecturesARM]

Collaboration diagram for * AT91:


Detailed Description

AT91 peripheral registers.

The AT91 peripherals are connected to the 32-bit wide advanced peripheral bus. All registers are word accessible only.


Modules

 * Bus Interface
 External bus interface registers.
 Power Saving
 Power saving registers.
 Interrupt Controller
 Advanced interrupt controller registers.
 Parallel I/O
 Parallel I/O controller registers.
 Watchdog Registers
 Watchdog timer registers.
 Watchdog Functions
 AT91 on-chip watchdog timer.
 Special Function
 Special function registers.
 USART
 Universal synchronous / asynchronous receiver / transmitter registers.
 Timer/Counter
 Timer / Counter registers.

Peripheral Identifiers and Interrupts

#define FIQ_ID
 Fast interrupt ID.
#define SWIRQ_ID
 Software interrupt ID.
#define US0_ID
 USART 0 ID.
#define US1_ID
 USART 1 ID.
#define TC0_ID
 Timer 0 ID.
#define TC1_ID
 Timer 1 ID.
#define TC2_ID
 Timer 2 ID.
#define WDI_ID
 Watchdog interrupt ID.
#define PIO_ID
 Parallel I/O controller ID.
#define IRQ0_ID
 External interrupt 0 ID.
#define IRQ1_ID
 External interrupt 1 ID.
#define IRQ2_ID
 External interrupt 2 ID.


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