Collaboration diagram for Interrupt Controller:
![]() |
The AT91 series provides an 8-level priority, individually maskable, vectored interrupt controller.
Interrupt Source Mode Registers | |
#define | AIC_SMR(i) |
Source mode register array. | |
#define | AIC_PRIOR |
Priority mask. | |
#define | AIC_SRCTYPE |
Interrupt source type mask. | |
#define | AIC_SRCTYPE_INT_LEVEL_SENSITIVE |
Internal level sensitive. | |
#define | AIC_SRCTYPE_INT_EDGE_TRIGGERED |
Internal edge triggered. | |
#define | AIC_SRCTYPE_EXT_LOW_LEVEL |
External low level. | |
#define | AIC_SRCTYPE_EXT_NEGATIVE_EDGE |
External falling edge. | |
#define | AIC_SRCTYPE_EXT_HIGH_LEVEL |
External high level. | |
#define | AIC_SRCTYPE_EXT_POSITIVE_EDGE |
External rising edge. | |
Interrupt Source Vector Registers | |
#define | AIC_SVR(i) |
Source vector register array. | |
Interrupt Vector Register | |
#define | AIC_IVR |
IRQ vector register address. | |
Fast Interrupt Vector Register | |
#define | AIC_FVR |
FIQ vector register address. | |
Interrupt Status Register | |
#define | AIC_ISR |
Interrupt status register address. | |
#define | AIC_IRQID |
Current interrupt identifier mask. | |
Interrupt Pending Register | |
#define | AIC_IPR |
Interrupt pending register address. | |
Interrupt Mask Register | |
#define | AIC_IMR |
Interrupt mask register address. | |
Interrupt Core Status Register | |
#define | AIC_CISR |
Core interrupt status register address. | |
#define | AIC_NFIQ |
Core FIQ Status. | |
#define | AIC_NIRQ |
Core IRQ Status. | |
Interrupt Enable Command Register | |
#define | AIC_IECR |
Interrupt enable command register address. | |
Interrupt Disable Command Register | |
#define | AIC_IDCR |
Interrupt disable command register address. | |
Interrupt Clear Command Register | |
#define | AIC_ICCR |
Interrupt clear command register address. | |
Interrupt Set Command Register | |
#define | AIC_ISCR |
Interrupt set command register address. | |
End Of Interrupt Command Register | |
#define | AIC_EOICR |
End of interrupt command register address. | |
Spurious Interrupt Vector Register | |
#define | AIC_SPU |
Spurious vector register address. | |
Defines | |
#define | AIC_BASE |
#define | IRQ_ENTRY() |
Interrupt entry. | |
#define | IRQ_EXIT() |
Interrupt exit. |
|
AIC base address. |
|
Priority mask. Priority levels can be between 0 (lowest) and 7 (highest). |
|
Interrupt source type mask. Internal interrupts can level sensitive or edge triggered. External interrupts can triggered on positive or negative levels or on rising or falling edges. |
|
Source vector register array. Stores the addresses of the corresponding interrupt handlers. |