* * $Log: at91.h,v $ * Revision 1.2 2005/11/20 14:44:14 haraldkipp * Register offsets added. * * Revision 1.1 2005/10/24 10:31:13 haraldkipp * Moved from parent directory. * * *
Chip Select Register | |
#define | EBI_CSR(i) |
Chip select register address. | |
#define | EBI_DBW |
Masks data bus width. | |
#define | EBI_DBW_16 |
16-bit data bus width | |
#define | EBI_DBW_8 |
8-bit data bus width | |
#define | EBI_NWS |
Masks number of wait states. | |
#define | EBI_NWS_1 |
1 wait state | |
#define | EBI_NWS_2 |
2 wait states | |
#define | EBI_NWS_3 |
3 wait states | |
#define | EBI_NWS_4 |
4 wait states | |
#define | EBI_NWS_5 |
5 wait states | |
#define | EBI_NWS_6 |
6 wait states | |
#define | EBI_NWS_7 |
7 wait states | |
#define | EBI_NWS_8 |
8 wait states | |
#define | EBI_WSE |
Wait state enable. | |
#define | EBI_PAGES |
Page size mask. | |
#define | EBI_PAGES_1M |
1 MByte page size | |
#define | EBI_PAGES_4M |
4 MBytes page size | |
#define | EBI_PAGES_16M |
16 MBytes page size | |
#define | EBI_PAGES_64M |
64 MBytes page size | |
#define | EBI_TDF |
Masks data float output time clock cycles. | |
#define | EBI_TDF_0 |
No added cycles. | |
#define | EBI_TDF_1 |
1 cycle | |
#define | EBI_TDF_2 |
2 cycles | |
#define | EBI_TDF_3 |
3 cycles | |
#define | EBI_TDF_4 |
4 cycles | |
#define | EBI_TDF_5 |
5 cycles | |
#define | EBI_TDF_6 |
6 cycles | |
#define | EBI_TDF_7 |
7 cycles | |
#define | EBI_BAT |
Byte access type. | |
#define | EBI_BAT_BYTE_WRITE |
Byte write access type. | |
#define | EBI_BAT_BYTE_SELECT |
Byte select access type. | |
#define | EBI_CSEN |
Chip select enable. | |
#define | EBI_BA |
Page base address mask. | |
Remap Control Register | |
#define | EBI_RCR |
Remap control register address. | |
#define | EBI_RCB |
Remap command. | |
Memory Control Register | |
#define | EBI_MCR |
Memory control register address. | |
#define | EBI_ALE |
Address line enable. | |
#define | EBI_ALE_16M |
16 Mbytes total address space | |
#define | EBI_ALE_8M |
8 Mbytes total address space | |
#define | EBI_ALE_4M |
4 Mbytes total address space | |
#define | EBI_ALE_2M |
2 Mbytes total address space | |
#define | EBI_ALE_1M |
1 Mbyte total address space | |
#define | EBI_DRP |
Data read protocol mask. | |
#define | EBI_DRP_STANDARD |
Standard read protocol. | |
#define | EBI_DRP_EARLY |
Early read protocol. | |
Chip Identification Registers | |
#define | SF_CIDR |
Chip ID register address. | |
#define | SF_EXID |
Chip ID extension register address. | |
#define | SF_VERSION |
Version number mask. | |
#define | SF_NVPSIZ |
Masks non volatile program memory size. | |
#define | SF_NVPSIZ_NONE |
No NV program memory. | |
#define | SF_NVPSIZ_32K |
32 kBytes NV program memory | |
#define | SF_NVPSIZ_64K |
64 kBytes NV program memory | |
#define | SF_NVPSIZ_128K |
128 kBytes NV program memory | |
#define | SF_NVPSIZ_256K |
256 kBytes NV program memory | |
#define | SF_NVDSIZ |
Masks non volatile data memory size. | |
#define | SF_NVDSIZ_NONE |
No NV data memory. | |
#define | SF_VDSIZ |
Masks volatile data memory size. | |
#define | SF_VDSIZ_NONE |
No volatile data memory. | |
#define | SF_VDSIZ_1K |
1 kBytes volatile data memory | |
#define | SF_VDSIZ_2K |
2 kBytes volatile data memory | |
#define | SF_VDSIZ_4K |
4 kBytes volatile data memory | |
#define | SF_VDSIZ_8K |
8 kBytes volatile data memory | |
#define | SF_ARCH |
Architecture code mask. | |
#define | SF_ARCH_AT91x40 |
AT91x40 architecture. | |
#define | SF_ARCH_AT91x55 |
AT91x55 architecture. | |
#define | SF_ARCH_AT91x63 |
AT91x63 architecture. | |
#define | SF_NVPTYP |
Masks non volatile program memory type. | |
#define | SF_NVPTYP_M |
M or F series. | |
#define | SF_NVPTYP_C |
C series. | |
#define | SF_NVPTYP_S |
S series. | |
#define | SF_NVPTYP_R |
R series. | |
#define | SF_EXT |
Extension flag. | |
Reset Status Flag Register | |
#define | SF_RSR |
Reset status register address. | |
#define | SF_EXT_RESET |
Reset caused by external pin. | |
#define | SF_WD_RESET |
Reset caused by internal watch dog. | |
Memory Mode Register | |
#define | SF_MMR |
Memory mode register address. | |
#define | SF_RAMWU |
Internal extended RAM write allowed. | |
Protect Mode Register | |
#define | SF_PMR |
Protect mode register address. | |
#define | SF_AIC |
AIC runs in protect mode. | |
USART Control Register | |
#define | US_CR_OFF |
USART control register offset. | |
#define | US0_CR |
Channel 0 control register address. | |
#define | US1_CR |
Channel 1 control register address. | |
#define | US_RSTRX |
Reset receiver. | |
#define | US_RSTTX |
Reset transmitter. | |
#define | US_RXEN |
Receiver enable. | |
#define | US_RXDIS |
Receiver disable. | |
#define | US_TXEN |
Transmitter enable. | |
#define | US_TXDIS |
Transmitter disable. | |
#define | US_RSTSTA |
Reset status bits. | |
#define | US_STTBRK |
Start break. | |
#define | US_STPBRK |
Stop break. | |
#define | US_STTTO |
Start timeout. | |
#define | US_SENDA |
Send next byte with address bit set. | |
Mode Register | |
#define | US_MR_OFF |
USART mode register offset. | |
#define | US0_MR |
Channel 0 mode register address. | |
#define | US1_MR |
Channel 1 mode register address. | |
#define | US_CLKS |
Clock selection mask. | |
#define | US_CLKS_MCK |
Master clock. | |
#define | US_CLKS_MCK8 |
Master clock divided by 8. | |
#define | US_CLKS_SCK |
External clock. | |
#define | US_CLKS_SLCK |
Slow clock. | |
#define | US_CHRL |
Masks data length. | |
#define | US_CHRL_5 |
5 data bits | |
#define | US_CHRL_6 |
6 data bits | |
#define | US_CHRL_7 |
7 data bits | |
#define | US_CHRL_8 |
8 data bits | |
#define | US_SYNC |
Synchronous mode enable. | |
#define | US_PAR |
Parity mode mask. | |
#define | US_PAR_EVEN |
Even parity. | |
#define | US_PAR_ODD |
Odd parity. | |
#define | US_PAR_SPACE |
Space parity. | |
#define | US_PAR_MARK |
Marked parity. | |
#define | US_PAR_NO |
No parity. | |
#define | US_PAR_MULTIDROP |
Multi-drop mode. | |
#define | US_NBSTOP |
Masks stop bit length. | |
#define | US_NBSTOP_1 |
1 stop bit | |
#define | US_NBSTOP_1_5 |
1.5 stop bits | |
#define | US_NBSTOP_2 |
2 stop bits | |
#define | US_CHMODE |
Channel mode mask. | |
#define | US_CHMODE_NORMAL |
Normal mode. | |
#define | US_CHMODE_AUTOMATIC_ECHO |
Automatic echo. | |
#define | US_CHMODE_LOCAL_LOOPBACK |
Local loopback. | |
#define | US_CHMODE_REMOTE_LOOPBACK |
Remote loopback. | |
#define | US_MODE9 |
9 bit mode | |
#define | US_CLKO |
Baud rate output enable. | |
Status and Interrupt Register | |
#define | US_CSR_OFF |
USART status register offset. | |
#define | US0_CSR |
Channel 0 status register address. | |
#define | US1_CSR |
Channel 1 status register address. | |
#define | US_IER_OFF |
USART interrupt enable register offset. | |
#define | US0_IER |
Channel 0 interrupt enable register address. | |
#define | US1_IER |
Channel 1 interrupt enable register address. | |
#define | US_IDR_OFF |
USART interrupt disable register offset. | |
#define | US0_IDR |
Channel 0 interrupt disable register address. | |
#define | US1_IDR |
Channel 1 interrupt disable register address. | |
#define | US_IMR_OFF |
USART interrupt mask register offset. | |
#define | US0_IMR |
Channel 0 interrupt mask register address. | |
#define | US1_IMR |
Channel 1 interrupt mask register address. | |
#define | US_RXRDY |
Receiver ready. | |
#define | US_TXRDY |
Transmitter ready. | |
#define | US_RXBRK |
Receiver break. | |
#define | US_ENDRX |
End of receiver PDC transfer. | |
#define | US_ENDTX |
End of transmitter PDC transfer. | |
#define | US_OVRE |
Overrun error. | |
#define | US_FRAME |
Framing error. | |
#define | US_PARE |
Parity error. | |
#define | US_TIMEOUT |
Receiver timeout. | |
#define | US_TXEMPTY |
Transmitter empty. | |
#define | AT91_US_BAUD(baud) |
Baud rate calculation helper macro. | |
Receiver Holding Register | |
#define | US_RHR_OFF |
USART receiver holding register offset. | |
#define | US0_RHR |
Channel 0 receiver holding register address. | |
#define | US1_RHR |
Channel 1 receiver holding register address. | |
Transmitter Holding Register | |
#define | US_THR_OFF |
USART transmitter holding register offset. | |
#define | US0_THR |
Channel 0 transmitter holding register address. | |
#define | US1_THR |
Channel 1 transmitter holding register address. | |
Baud Rate Generator Register | |
#define | US_BRGR_OFF |
USART baud rate register offset. | |
#define | US0_BRGR |
Channel 0 baud rate register address. | |
#define | US1_BRGR |
Channel 1 baud rate register address. | |
Receiver Timeout Register | |
#define | US_RTOR_OFF |
USART receiver timeout register offset. | |
#define | US0_RTOR |
Channel 0 receiver timeout register address. | |
#define | US1_RTOR |
Channel 1 receiver timeout register address. | |
Transmitter Time Guard Register | |
#define | US_TTGR_OFF |
USART transmitter time guard register offset. | |
#define | US0_TTGR |
Channel 0 transmitter time guard register address. | |
#define | US1_TTGR |
Channel 1 transmitter time guard register address. | |
Receive Pointer Register | |
#define | US_RPR_OFF |
USART receive pointer register offset. | |
#define | US0_RPR |
Channel 0 receive pointer register address. | |
#define | US1_RPR |
Channel 1 receive pointer register address. | |
Receive Counter Register | |
#define | US_RCR_OFF |
USART receive counter register offset. | |
#define | US0_RCR |
Channel 0 receive counter register address. | |
#define | US1_RCR |
Channel 1 receive counter register address. | |
Transmit Pointer Register | |
#define | US_TPR_OFF |
USART transmit pointer register offset. | |
#define | US0_TPR |
Channel 0 transmit pointer register address. | |
#define | US1_TPR |
Channel 1 transmit pointer register address. | |
Transmit Counter Register | |
#define | US_TCR_OFF |
USART transmit counter register offset. | |
#define | US0_TCR |
Channel 0 transmit counter register address. | |
#define | US1_TCR |
Channel 1 transmit counter register address. | |
Timer Counter Control Register | |
#define | TC0_CCR |
Channel 0 control register address. | |
#define | TC1_CCR |
Channel 1 control register address. | |
#define | TC2_CCR |
Channel 2 control register address. | |
#define | TC_CLKEN |
Clock enable command. | |
#define | TC_CLKDIS |
Clock disable command. | |
#define | TC_SWTRG |
Software trigger command. | |
Timer Counter Channel Mode Register | |
#define | TC0_CMR |
Channel 0 mode register address. | |
#define | TC1_CMR |
Channel 1 mode register address. | |
#define | TC2_CMR |
Channel 2 mode register address. | |
#define | TC_CLKS |
Clock selection mask. | |
#define | TC_CLKS_MCK2 |
Selects MCK / 2. | |
#define | TC_CLKS_MCK8 |
Selects MCK / 8. | |
#define | TC_CLKS_MCK32 |
Selects MCK / 32. | |
#define | TC_CLKS_MCK128 |
Selects MCK / 128. | |
#define | TC_CLKS_MCK1024 |
Selects MCK / 1024. | |
#define | TC_CLKS_XC0 |
Selects external clock 0. | |
#define | TC_CLKS_XC1 |
Selects external clock 1. | |
#define | TC_CLKS_XC2 |
Selects external clock 2. | |
#define | TC_CLKI |
Increments on falling edge. | |
#define | TC_BURST |
Burst signal selection mask. | |
#define | TC_BURST_NONE |
Clock is not gated by an external signal. | |
#define | TC_BUSRT_XC0 |
ANDed with external clock 0. | |
#define | TC_BURST_XC1 |
ANDed with external clock 1. | |
#define | TC_BURST_XC2 |
ANDed with external clock 2. | |
#define | TC_CPCTRG |
RC Compare Enable Trigger Enable. | |
#define | TC_WAVE |
Selects waveform mode. | |
#define | TC_CAPT |
Selects capture mode. | |
Capture Mode | |
#define | TC_LDBSTOP |
Counter clock stopped on RB loading. | |
#define | TC_LDBDIS |
Counter clock disabled on RB loading. | |
#define | TC_ETRGEDG |
External trigger edge selection mask. | |
#define | TC_ETRGEDG_RISING_EDGE |
Trigger on external rising edge. | |
#define | TC_ETRGEDG_FALLING_EDGE |
Trigger on external falling edge. | |
#define | TC_ETRGEDG_BOTH_EDGE |
Trigger on both external edges. | |
#define | TC_ABETRG |
TIOA or TIOB external trigger selection mask. | |
#define | TC_ABETRG_TIOB |
TIOB used as an external trigger. | |
#define | TC_ABETRG_TIOA |
TIOA used as an external trigger. | |
#define | TC_LDRA |
RA loading selection mask. | |
#define | TC_LDRA_RISING_EDGE |
Load RA on rising edge of TIOA. | |
#define | TC_LDRA_FALLING_EDGE |
Load RA on falling edge of TIOA. | |
#define | TC_LDRA_BOTH_EDGE |
Load RA on any edge of TIOA. | |
#define | TC_LDRB |
RB loading selection mask. | |
#define | TC_LDRB_RISING_EDGE |
Load RB on rising edge of TIOA. | |
#define | TC_LDRB_FALLING_EDGE |
Load RB on falling edge of TIOA. | |
#define | TC_LDRB_BOTH_EDGE |
Load RB on any edge of TIOA. | |
Waveform Mode | |
#define | TC_CPCSTOP |
Counter clock stopped on RC compare. | |
#define | TC_CPCDIS |
Counter clock disabled on RC compare. | |
#define | TC_EEVTEDG |
External event edge selection mask. | |
#define | TC_EEVTEDG_RISING_EDGE |
External event on rising edge. | |
#define | TC_EEVTEDG_FALLING_EDGE |
External event on falling edge. | |
#define | TC_EEVTEDG_BOTH_EDGE |
External event on any edge. | |
#define | TC_EEVT |
External event selection mask. | |
#define | TC_EEVT_TIOB |
TIOB selected as external event. | |
#define | TC_EEVT_XC0 |
XC0 selected as external event. | |
#define | TC_EEVT_XC1 |
XC1 selected as external event. | |
#define | TC_EEVT_XC2 |
XC2 selected as external event. | |
#define | TC_ENETRG |
External event trigger enable. | |
#define | TC_ACPA |
Masks RA compare effect on TIOA. | |
#define | TC_ACPA_SET_OUTPUT |
RA compare sets TIOA. | |
#define | TC_ACPA_CLEAR_OUTPUT |
RA compare clears TIOA. | |
#define | TC_ACPA_TOGGLE_OUTPUT |
RA compare toggles TIOA. | |
#define | TC_ACPC |
Masks RC compare effect on TIOA. | |
#define | TC_ACPC_SET_OUTPUT |
RC compare sets TIOA. | |
#define | TC_ACPC_CLEAR_OUTPUT |
RC compare clears TIOA. | |
#define | TC_ACPC_TOGGLE_OUTPUT |
RC compare toggles TIOA. | |
#define | TC_AEEVT |
Masks external event effect on TIOA. | |
#define | TC_AEEVT_SET_OUTPUT |
External event sets TIOA. | |
#define | TC_AEEVT_CLEAR_OUTPUT |
External event clears TIOA. | |
#define | TC_AEEVT_TOGGLE_OUTPUT |
External event toggles TIOA. | |
#define | TC_ASWTRG |
Masks software trigger effect on TIOA. | |
#define | TC_ASWTRG_SET_OUTPUT |
Software trigger sets TIOA. | |
#define | TC_ASWTRG_CLEAR_OUTPUT |
Software trigger clears TIOA. | |
#define | TC_ASWTRG_TOGGLE_OUTPUT |
Software trigger toggles TIOA. | |
#define | TC_BCPB |
Masks RB compare effect on TIOB. | |
#define | TC_BCPB_SET_OUTPUT |
RB compare sets TIOB. | |
#define | TC_BCPB_CLEAR_OUTPUT |
RB compare clears TIOB. | |
#define | TC_BCPB_TOGGLE_OUTPUT |
RB compare toggles TIOB. | |
#define | TC_BCPC |
Masks RC compare effect on TIOB. | |
#define | TC_BCPC_SET_OUTPUT |
RC compare sets TIOB. | |
#define | TC_BCPC_CLEAR_OUTPUT |
RC compare clears TIOB. | |
#define | TC_BCPC_TOGGLE_OUTPUT |
RC compare toggles TIOB. | |
#define | TC_BEEVT |
Masks external event effect on TIOB. | |
#define | TC_BEEVT_SET_OUTPUT |
External event sets TIOB. | |
#define | TC_BEEVT_CLEAR_OUTPUT |
External event clears TIOB. | |
#define | TC_BEEVT_TOGGLE_OUTPUT |
External event toggles TIOB. | |
#define | TC_BSWTRG |
Masks software trigger effect on TIOB. | |
#define | TC_BSWTRG_SET_OUTPUT |
Software trigger sets TIOB. | |
#define | TC_BSWTRG_CLEAR_OUTPUT |
Software trigger clears TIOB. | |
#define | TC_BSWTRG_TOGGLE_OUTPUT |
Software trigger toggles TIOB. | |
Counter Value Register | |
#define | TC0_CV |
Counter 0 value. | |
#define | TC1_CV |
Counter 1 value. | |
#define | TC2_CV |
Counter 2 value. | |
Timer Counter Register A | |
#define | TC0_RA |
Channel 0 register A. | |
#define | TC1_RA |
Channel 1 register A. | |
#define | TC2_RA |
Channel 2 register A. | |
Timer Counter Register B | |
#define | TC0_RB |
Channel 0 register B. | |
#define | TC1_RB |
Channel 1 register B. | |
#define | TC2_RB |
Channel 2 register B. | |
Timer Counter Register C | |
#define | TC0_RC |
Channel 0 register C. | |
#define | TC1_RC |
Channel 1 register C. | |
#define | TC2_RC |
Channel 2 register C. | |
Timer Counter Status and Interrupt Registers | |
#define | TC0_SR |
Status register address. | |
#define | TC1_SR |
Status register address. | |
#define | TC2_SR |
Status register address. | |
#define | TC0_IER |
Channel 0 interrupt enable register address. | |
#define | TC1_IER |
Channel 1 interrupt enable register address. | |
#define | TC2_IER |
Channel 2 interrupt enable register address. | |
#define | TC0_IDR |
Channel 0 interrupt disable register address. | |
#define | TC1_IDR |
Channel 1 interrupt disable register address. | |
#define | TC2_IDR |
Channel 2 interrupt disable register address. | |
#define | TC0_IMR |
Channel 0 interrupt mask register address. | |
#define | TC1_IMR |
Channel 1 interrupt mask register address. | |
#define | TC2_IMR |
Channel 2 interrupt mask register address. | |
#define | TC_COVFS |
Counter overflow flag. | |
#define | TC_LOVRS |
Load overrun flag. | |
#define | TC_CPAS |
RA compare flag. | |
#define | TC_CPBS |
RB compare flag. | |
#define | TC_CPCS |
RC compare flag. | |
#define | TC_LDRAS |
RA loading flag. | |
#define | TC_LDRBS |
RB loading flag. | |
#define | TC_ETRGS |
External trigger flag. | |
#define | TC_CLKSTA |
Clock enable flag. | |
#define | TC_MTIOA |
TIOA flag. | |
#define | TC_MTIOB |
TIOB flag. | |
Timer Counter Block Control Register | |
#define | TC_BCR |
Block control register address. | |
#define | TC_SYNC |
Synchronisation trigger. | |
Timer Counter Block Mode Register | |
#define | TC_BMR |
Block mode register address. | |
#define | TC_TC0XC0S |
External clock signal 0 selection mask. | |
#define | TC_TCLK0XC0 |
Selects TCLK0. | |
#define | TC_NONEXC0 |
None selected. | |
#define | TC_TIOA1XC0 |
Selects TIOA1. | |
#define | TC_TIOA2XC0 |
Selects TIOA2. | |
#define | TC_TC1XC1S |
External clock signal 1 selection mask. | |
#define | TC_TCLK1XC1 |
Selects TCLK1. | |
#define | TC_NONEXC1 |
None selected. | |
#define | TC_TIOA0XC1 |
Selects TIOA0. | |
#define | TC_TIOA2XC1 |
Selects TIOA2. | |
#define | TC_TC2XC2S |
External clock signal 2 selection mask. | |
#define | TC_TCLK2XC2 |
Selects TCLK2. | |
#define | TC_NONEXC2 |
None selected. | |
#define | TC_TIOA0XC2 |
Selects TIOA0. | |
#define | TC_TIOA1XC2 |
Selects TIOA1. | |
PS Control Register | |
#define | PS_CR |
Register address. | |
Peripheral Clock Control Registers | |
#define | PS_PCER |
Peripheral clock enable register address. | |
#define | PS_PCDR |
Peripheral clock disable register address. | |
#define | PS_PCSR |
Peripheral clock status register address. | |
Watch Dog Overflow Mode Register | |
#define | WD_OMR |
Overflow mode register address. | |
#define | WD_WDEN |
Watch Dog enable. | |
#define | WD_RSTEN |
Internal reset enable. | |
#define | WD_IRQEN |
Interrupt enable. | |
#define | WD_EXTEN |
External signal enable. | |
#define | WD_OKEY |
Overflow mode register access key. | |
Watch Dog Clock Register | |
#define | WD_CMR |
Clock mode register address. | |
#define | WD_WDCLKS |
Clock selection mask. | |
#define | WD_WDCLKS_MCK8 |
Selects MCK/8. | |
#define | WD_WDCLKS_MCK32 |
Selects MCK/32. | |
#define | WD_WDCLKS_MCK128 |
Selects MCK/128. | |
#define | WD_WDCLKS_MCK1024 |
Selects MCK/1024. | |
#define | WD_HPCV |
High preload counter value. | |
#define | WD_CKEY |
Clock register access key. | |
Watch Dog Control Register | |
#define | WD_CR |
Control register address. | |
#define | WD_RSTKEY |
Watch Dog restart key. | |
Watch Dog Status Register | |
#define | WD_SR |
Status register address. | |
#define | WD_WDOVF |
Watch Dog overflow status. | |
Interrupt Source Mode Registers | |
#define | AIC_SMR(i) |
Source mode register array. | |
#define | AIC_PRIOR |
Priority mask. | |
#define | AIC_SRCTYPE |
Interrupt source type mask. | |
#define | AIC_SRCTYPE_INT_LEVEL_SENSITIVE |
Internal level sensitive. | |
#define | AIC_SRCTYPE_INT_EDGE_TRIGGERED |
Internal edge triggered. | |
#define | AIC_SRCTYPE_EXT_LOW_LEVEL |
External low level. | |
#define | AIC_SRCTYPE_EXT_NEGATIVE_EDGE |
External falling edge. | |
#define | AIC_SRCTYPE_EXT_HIGH_LEVEL |
External high level. | |
#define | AIC_SRCTYPE_EXT_POSITIVE_EDGE |
External rising edge. | |
Interrupt Source Vector Registers | |
#define | AIC_SVR(i) |
Source vector register array. | |
Interrupt Vector Register | |
#define | AIC_IVR |
IRQ vector register address. | |
Fast Interrupt Vector Register | |
#define | AIC_FVR |
FIQ vector register address. | |
Interrupt Status Register | |
#define | AIC_ISR |
Interrupt status register address. | |
#define | AIC_IRQID |
Current interrupt identifier mask. | |
Interrupt Pending Register | |
#define | AIC_IPR |
Interrupt pending register address. | |
Interrupt Mask Register | |
#define | AIC_IMR |
Interrupt mask register address. | |
Interrupt Core Status Register | |
#define | AIC_CISR |
Core interrupt status register address. | |
#define | AIC_NFIQ |
Core FIQ Status. | |
#define | AIC_NIRQ |
Core IRQ Status. | |
Interrupt Enable Command Register | |
#define | AIC_IECR |
Interrupt enable command register address. | |
Interrupt Disable Command Register | |
#define | AIC_IDCR |
Interrupt disable command register address. | |
Interrupt Clear Command Register | |
#define | AIC_ICCR |
Interrupt clear command register address. | |
Interrupt Set Command Register | |
#define | AIC_ISCR |
Interrupt set command register address. | |
End Of Interrupt Command Register | |
#define | AIC_EOICR |
End of interrupt command register address. | |
Spurious Interrupt Vector Register | |
#define | AIC_SPU |
Spurious vector register address. | |
Peripheral Identifiers and Interrupts | |
#define | FIQ_ID |
Fast interrupt ID. | |
#define | SWIRQ_ID |
Software interrupt ID. | |
#define | US0_ID |
USART 0 ID. | |
#define | US1_ID |
USART 1 ID. | |
#define | TC0_ID |
Timer 0 ID. | |
#define | TC1_ID |
Timer 1 ID. | |
#define | TC2_ID |
Timer 2 ID. | |
#define | WDI_ID |
Watchdog interrupt ID. | |
#define | PIO_ID |
Parallel I/O controller ID. | |
#define | IRQ0_ID |
External interrupt 0 ID. | |
#define | IRQ1_ID |
External interrupt 1 ID. | |
#define | IRQ2_ID |
External interrupt 2 ID. | |
Defines | |
#define | EBI_BASE |
EBI base address. | |
#define | SF_BASE |
Special function register base address. | |
#define | USART1_BASE |
USART 1 base address. | |
#define | USART0_BASE |
USART 0 base address. | |
#define | TC_BASE |
TC base address. | |
#define | PIO_BASE |
PIO base address. | |
#define | PIO_PER |
PIO enable register. | |
#define | PIO_PDR |
PIO disable register. | |
#define | PIO_PSR |
PIO status register. | |
#define | PIO_OER |
Output enable register. | |
#define | PIO_ODR |
Output disable register. | |
#define | PIO_OSR |
Output status register. | |
#define | PIO_IFER |
Input filter enable register. | |
#define | PIO_IFDR |
Input filter disable register. | |
#define | PIO_IFSR |
Input filter status register. | |
#define | PIO_SODR |
Set output data register. | |
#define | PIO_CODR |
Clear output data register. | |
#define | PIO_ODSR |
Output data status register. | |
#define | PIO_PDSR |
Pin data status register. | |
#define | PIO_IER |
Interrupt enable register. | |
#define | PIO_IDR |
Interrupt disable register. | |
#define | PIO_IMR |
Interrupt mask register. | |
#define | PIO_ISR |
Interrupt status register. | |
#define | PS_BASE |
PS base address. | |
#define | WD_BASE |
Watch Dog register base address. | |
#define | AIC_BASE |
#define | IRQ_ENTRY() |
Interrupt entry. | |
#define | IRQ_EXIT() |
Interrupt exit. |